drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <scsi/fc/fc_fcoe.h>
  43
  44 #include "ixgbe.h"
  45 #include "ixgbe_common.h"
  46
  47 char ixgbe_driver_name[] = "ixgbe";
  48 static const char ixgbe_driver_string[] =
  49                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  50
  51 #define DRV_VERSION "2.0.34-k2"
  52 const char ixgbe_driver_version[] = DRV_VERSION;
  53 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  54
  55 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  56         [board_82598] = &ixgbe_82598_info,
  57         [board_82599] = &ixgbe_82599_info,
  58 };
  59
  60 /* ixgbe_pci_tbl - PCI Device ID Table
  61  *
  62  * Wildcard entries (PCI_ANY_ID) should come last
  63  * Last entry must be all 0s
  64  *
  65  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  66  *   Class, Class Mask, private data (not used) }
  67  */
  68 static struct pci_device_id ixgbe_pci_tbl[] = {
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  92          board_82599 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  94          board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  96          board_82599 },
  97
  98         /* required last entry */
  99         {0, }
 100 };
 101 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 102
 103 #ifdef CONFIG_IXGBE_DCA
 104 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 105                             void *p);
 106 static struct notifier_block dca_notifier = {
 107         .notifier_call = ixgbe_notify_dca,
 108         .next          = NULL,
 109         .priority      = 0
 110 };
 111 #endif
 112
 113 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 114 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 115 MODULE_LICENSE("GPL");
 116 MODULE_VERSION(DRV_VERSION);
 117
 118 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 119
 120 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 121 {
 122         u32 ctrl_ext;
 123
 124         /* Let firmware take over control of h/w */
 125         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 126         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 127                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 128 }
 129
 130 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 131 {
 132         u32 ctrl_ext;
 133
 134         /* Let firmware know the driver has taken over */
 135         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 136         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 137                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 138 }
 139
 140 /*
 141  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 142  * @adapter: pointer to adapter struct
 143  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 144  * @queue: queue to map the corresponding interrupt to
 145  * @msix_vector: the vector to map to the corresponding queue
 146  *
 147  */
 148 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 149                            u8 queue, u8 msix_vector)
 150 {
 151         u32 ivar, index;
 152         struct ixgbe_hw *hw = &adapter->hw;
 153         switch (hw->mac.type) {
 154         case ixgbe_mac_82598EB:
 155                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 156                 if (direction == -1)
 157                         direction = 0;
 158                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 159                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 160                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 161                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 162                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 163                 break;
 164         case ixgbe_mac_82599EB:
 165                 if (direction == -1) {
 166                         /* other causes */
 167                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                         index = ((queue & 1) * 8);
 169                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 170                         ivar &= ~(0xFF << index);
 171                         ivar |= (msix_vector << index);
 172                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 173                         break;
 174                 } else {
 175                         /* tx or rx causes */
 176                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 177                         index = ((16 * (queue & 1)) + (8 * direction));
 178                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 179                         ivar &= ~(0xFF << index);
 180                         ivar |= (msix_vector << index);
 181                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 182                         break;
 183                 }
 184         default:
 185                 break;
 186         }
 187 }
 188
 189 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 190                                           u64 qmask)
 191 {
 192         u32 mask;
 193
 194         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 195                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 196                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 197         } else {
 198                 mask = (qmask & 0xFFFFFFFF);
 199                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 200                 mask = (qmask >> 32);
 201                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 202         }
 203 }
 204
 205 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 206                                              struct ixgbe_tx_buffer
 207                                              *tx_buffer_info)
 208 {
 209         tx_buffer_info->dma = 0;
 210         if (tx_buffer_info->skb) {
 211                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 212                               DMA_TO_DEVICE);
 213                 dev_kfree_skb_any(tx_buffer_info->skb);
 214                 tx_buffer_info->skb = NULL;
 215         }
 216         tx_buffer_info->time_stamp = 0;
 217         /* tx_buffer_info must be completely set up in the transmit path */
 218 }
 219
 220 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 221                                        struct ixgbe_ring *tx_ring,
 222                                        unsigned int eop)
 223 {
 224         struct ixgbe_hw *hw = &adapter->hw;
 225
 226         /* Detect a transmit hang in hardware, this serializes the
 227          * check with the clearing of time_stamp and movement of eop */
 228         adapter->detect_tx_hung = false;
 229         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 230             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 231             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 232                 /* detected Tx unit hang */
 233                 union ixgbe_adv_tx_desc *tx_desc;
 234                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 235                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 236                         "  Tx Queue             <%d>\n"
 237                         "  TDH, TDT             <%x>, <%x>\n"
 238                         "  next_to_use          <%x>\n"
 239                         "  next_to_clean        <%x>\n"
 240                         "tx_buffer_info[next_to_clean]\n"
 241                         "  time_stamp           <%lx>\n"
 242                         "  jiffies              <%lx>\n",
 243                         tx_ring->queue_index,
 244                         IXGBE_READ_REG(hw, tx_ring->head),
 245                         IXGBE_READ_REG(hw, tx_ring->tail),
 246                         tx_ring->next_to_use, eop,
 247                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 248                 return true;
 249         }
 250
 251         return false;
 252 }
 253
 254 #define IXGBE_MAX_TXD_PWR       14
 255 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 256
 257 /* Tx Descriptors needed, worst case */
 258 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 259                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 260 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 261         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 262
 263 static void ixgbe_tx_timeout(struct net_device *netdev);
 264
 265 /**
 266  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 267  * @q_vector: structure containing interrupt and ring information
 268  * @tx_ring: tx ring to clean
 269  **/
 270 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 271                                struct ixgbe_ring *tx_ring)
 272 {
 273         struct ixgbe_adapter *adapter = q_vector->adapter;
 274         struct net_device *netdev = adapter->netdev;
 275         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 276         struct ixgbe_tx_buffer *tx_buffer_info;
 277         unsigned int i, eop, count = 0;
 278         unsigned int total_bytes = 0, total_packets = 0;
 279
 280         i = tx_ring->next_to_clean;
 281         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 282         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 283
 284         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 285                (count < tx_ring->work_limit)) {
 286                 bool cleaned = false;
 287                 for ( ; !cleaned; count++) {
 288                         struct sk_buff *skb;
 289                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 290                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 291                         cleaned = (i == eop);
 292                         skb = tx_buffer_info->skb;
 293
 294                         if (cleaned && skb) {
 295                                 unsigned int segs, bytecount;
 296                                 unsigned int hlen = skb_headlen(skb);
 297
 298                                 /* gso_segs is currently only valid for tcp */
 299                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 300 #ifdef IXGBE_FCOE
 301                                 /* adjust for FCoE Sequence Offload */
 302                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 303                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 304                                     skb_is_gso(skb)) {
 305                                         hlen = skb_transport_offset(skb) +
 306                                                 sizeof(struct fc_frame_header) +
 307                                                 sizeof(struct fcoe_crc_eof);
 308                                         segs = DIV_ROUND_UP(skb->len - hlen,
 309                                                 skb_shinfo(skb)->gso_size);
 310                                 }
 311 #endif /* IXGBE_FCOE */
 312                                 /* multiply data chunks by size of headers */
 313                                 bytecount = ((segs - 1) * hlen) + skb->len;
 314                                 total_packets += segs;
 315                                 total_bytes += bytecount;
 316                         }
 317
 318                         ixgbe_unmap_and_free_tx_resource(adapter,
 319                                                          tx_buffer_info);
 320
 321                         tx_desc->wb.status = 0;
 322
 323                         i++;
 324                         if (i == tx_ring->count)
 325                                 i = 0;
 326                 }
 327
 328                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 329                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 330         }
 331
 332         tx_ring->next_to_clean = i;
 333
 334 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 335         if (unlikely(count && netif_carrier_ok(netdev) &&
 336                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 337                 /* Make sure that anybody stopping the queue after this
 338                  * sees the new next_to_clean.
 339                  */
 340                 smp_mb();
 341                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 342                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 343                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 344                         ++adapter->restart_queue;
 345                 }
 346         }
 347
 348         if (adapter->detect_tx_hung) {
 349                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 350                         /* schedule immediate reset if we believe we hung */
 351                         DPRINTK(PROBE, INFO,
 352                                 "tx hang %d detected, resetting adapter\n",
 353                                 adapter->tx_timeout_count + 1);
 354                         ixgbe_tx_timeout(adapter->netdev);
 355                 }
 356         }
 357
 358         /* re-arm the interrupt */
 359         if (count >= tx_ring->work_limit)
 360                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 361
 362         tx_ring->total_bytes += total_bytes;
 363         tx_ring->total_packets += total_packets;
 364         tx_ring->stats.packets += total_packets;
 365         tx_ring->stats.bytes += total_bytes;
 366         adapter->net_stats.tx_bytes += total_bytes;
 367         adapter->net_stats.tx_packets += total_packets;
 368         return (count < tx_ring->work_limit);
 369 }
 370
 371 #ifdef CONFIG_IXGBE_DCA
 372 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 373                                 struct ixgbe_ring *rx_ring)
 374 {
 375         u32 rxctrl;
 376         int cpu = get_cpu();
 377         int q = rx_ring - adapter->rx_ring;
 378
 379         if (rx_ring->cpu != cpu) {
 380                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 381                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 382                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 383                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 384                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 385                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 386                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 387                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 388                 }
 389                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 390                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 391                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 392                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 393                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 394                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 395                 rx_ring->cpu = cpu;
 396         }
 397         put_cpu();
 398 }
 399
 400 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 401                                 struct ixgbe_ring *tx_ring)
 402 {
 403         u32 txctrl;
 404         int cpu = get_cpu();
 405         int q = tx_ring - adapter->tx_ring;
 406
 407         if (tx_ring->cpu != cpu) {
 408                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 409                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 410                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 411                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 412                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 413                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 414                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 415                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 416                 }
 417                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 418                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 419                 tx_ring->cpu = cpu;
 420         }
 421         put_cpu();
 422 }
 423
 424 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 425 {
 426         int i;
 427
 428         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 429                 return;
 430
 431         /* always use CB2 mode, difference is masked in the CB driver */
 432         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 433
 434         for (i = 0; i < adapter->num_tx_queues; i++) {
 435                 adapter->tx_ring[i].cpu = -1;
 436                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 437         }
 438         for (i = 0; i < adapter->num_rx_queues; i++) {
 439                 adapter->rx_ring[i].cpu = -1;
 440                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 441         }
 442 }
 443
 444 static int __ixgbe_notify_dca(struct device *dev, void *data)
 445 {
 446         struct net_device *netdev = dev_get_drvdata(dev);
 447         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 448         unsigned long event = *(unsigned long *)data;
 449
 450         switch (event) {
 451         case DCA_PROVIDER_ADD:
 452                 /* if we're already enabled, don't do it again */
 453                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 454                         break;
 455                 if (dca_add_requester(dev) == 0) {
 456                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 457                         ixgbe_setup_dca(adapter);
 458                         break;
 459                 }
 460                 /* Fall Through since DCA is disabled. */
 461         case DCA_PROVIDER_REMOVE:
 462                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 463                         dca_remove_requester(dev);
 464                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 465                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 466                 }
 467                 break;
 468         }
 469
 470         return 0;
 471 }
 472
 473 #endif /* CONFIG_IXGBE_DCA */
 474 /**
 475  * ixgbe_receive_skb - Send a completed packet up the stack
 476  * @adapter: board private structure
 477  * @skb: packet to send up
 478  * @status: hardware indication of status of receive
 479  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 480  * @rx_desc: rx descriptor
 481  **/
 482 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 483                               struct sk_buff *skb, u8 status,
 484                               struct ixgbe_ring *ring,
 485                               union ixgbe_adv_rx_desc *rx_desc)
 486 {
 487         struct ixgbe_adapter *adapter = q_vector->adapter;
 488         struct napi_struct *napi = &q_vector->napi;
 489         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 490         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 491
 492         skb_record_rx_queue(skb, ring->queue_index);
 493         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 494                 if (adapter->vlgrp && is_vlan && (tag != 0))
 495                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 496                 else
 497                         napi_gro_receive(napi, skb);
 498         } else {
 499                 if (adapter->vlgrp && is_vlan && (tag != 0))
 500                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 501                 else
 502                         netif_rx(skb);
 503         }
 504 }
 505
 506 /**
 507  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 508  * @adapter: address of board private structure
 509  * @status_err: hardware indication of status of receive
 510  * @skb: skb currently being received and modified
 511  **/
 512 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 513                                      u32 status_err, struct sk_buff *skb)
 514 {
 515         skb->ip_summed = CHECKSUM_NONE;
 516
 517         /* Rx csum disabled */
 518         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 519                 return;
 520
 521         /* if IP and error */
 522         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 523             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 524                 adapter->hw_csum_rx_error++;
 525                 return;
 526         }
 527
 528         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 529                 return;
 530
 531         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 532                 adapter->hw_csum_rx_error++;
 533                 return;
 534         }
 535
 536         /* It must be a TCP or UDP packet with a valid checksum */
 537         skb->ip_summed = CHECKSUM_UNNECESSARY;
 538         adapter->hw_csum_rx_good++;
 539 }
 540
 541 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 542                                          struct ixgbe_ring *rx_ring, u32 val)
 543 {
 544         /*
 545          * Force memory writes to complete before letting h/w
 546          * know there are new descriptors to fetch.  (Only
 547          * applicable for weak-ordered memory model archs,
 548          * such as IA-64).
 549          */
 550         wmb();
 551         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 552 }
 553
 554 /**
 555  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 556  * @adapter: address of board private structure
 557  **/
 558 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 559                                    struct ixgbe_ring *rx_ring,
 560                                    int cleaned_count)
 561 {
 562         struct pci_dev *pdev = adapter->pdev;
 563         union ixgbe_adv_rx_desc *rx_desc;
 564         struct ixgbe_rx_buffer *bi;
 565         unsigned int i;
 566
 567         i = rx_ring->next_to_use;
 568         bi = &rx_ring->rx_buffer_info[i];
 569
 570         while (cleaned_count--) {
 571                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 572
 573                 if (!bi->page_dma &&
 574                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 575                         if (!bi->page) {
 576                                 bi->page = alloc_page(GFP_ATOMIC);
 577                                 if (!bi->page) {
 578                                         adapter->alloc_rx_page_failed++;
 579                                         goto no_buffers;
 580                                 }
 581                                 bi->page_offset = 0;
 582                         } else {
 583                                 /* use a half page if we're re-using */
 584                                 bi->page_offset ^= (PAGE_SIZE / 2);
 585                         }
 586
 587                         bi->page_dma = pci_map_page(pdev, bi->page,
 588                                                     bi->page_offset,
 589                                                     (PAGE_SIZE / 2),
 590                                                     PCI_DMA_FROMDEVICE);
 591                 }
 592
 593                 if (!bi->skb) {
 594                         struct sk_buff *skb;
 595                         skb = netdev_alloc_skb(adapter->netdev,
 596                                                (rx_ring->rx_buf_len +
 597                                                 NET_IP_ALIGN));
 598
 599                         if (!skb) {
 600                                 adapter->alloc_rx_buff_failed++;
 601                                 goto no_buffers;
 602                         }
 603
 604                         /*
 605                          * Make buffer alignment 2 beyond a 16 byte boundary
 606                          * this will result in a 16 byte aligned IP header after
 607                          * the 14 byte MAC header is removed
 608                          */
 609                         skb_reserve(skb, NET_IP_ALIGN);
 610
 611                         bi->skb = skb;
 612                         bi->dma = pci_map_single(pdev, skb->data,
 613                                                  rx_ring->rx_buf_len,
 614                                                  PCI_DMA_FROMDEVICE);
 615                 }
 616                 /* Refresh the desc even if buffer_addrs didn't change because
 617                  * each write-back erases this info. */
 618                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 619                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 620                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 621                 } else {
 622                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 623                 }
 624
 625                 i++;
 626                 if (i == rx_ring->count)
 627                         i = 0;
 628                 bi = &rx_ring->rx_buffer_info[i];
 629         }
 630
 631 no_buffers:
 632         if (rx_ring->next_to_use != i) {
 633                 rx_ring->next_to_use = i;
 634                 if (i-- == 0)
 635                         i = (rx_ring->count - 1);
 636
 637                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 638         }
 639 }
 640
 641 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 642 {
 643         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 644 }
 645
 646 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 647 {
 648         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 649 }
 650
 651 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 652 {
 653         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 654                 IXGBE_RXDADV_RSCCNT_MASK) >>
 655                 IXGBE_RXDADV_RSCCNT_SHIFT;
 656 }
 657
 658 /**
 659  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 660  * @skb: pointer to the last skb in the rsc queue
 661  *
 662  * This function changes a queue full of hw rsc buffers into a completed
 663  * packet.  It uses the ->prev pointers to find the first packet and then
 664  * turns it into the frag list owner.
 665  **/
 666 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 667 {
 668         unsigned int frag_list_size = 0;
 669
 670         while (skb->prev) {
 671                 struct sk_buff *prev = skb->prev;
 672                 frag_list_size += skb->len;
 673                 skb->prev = NULL;
 674                 skb = prev;
 675         }
 676
 677         skb_shinfo(skb)->frag_list = skb->next;
 678         skb->next = NULL;
 679         skb->len += frag_list_size;
 680         skb->data_len += frag_list_size;
 681         skb->truesize += frag_list_size;
 682         return skb;
 683 }
 684
 685 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 686                                struct ixgbe_ring *rx_ring,
 687                                int *work_done, int work_to_do)
 688 {
 689         struct ixgbe_adapter *adapter = q_vector->adapter;
 690         struct pci_dev *pdev = adapter->pdev;
 691         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 692         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 693         struct sk_buff *skb;
 694         unsigned int i, rsc_count = 0;
 695         u32 len, staterr;
 696         u16 hdr_info;
 697         bool cleaned = false;
 698         int cleaned_count = 0;
 699         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 700 #ifdef IXGBE_FCOE
 701         int ddp_bytes = 0;
 702 #endif /* IXGBE_FCOE */
 703
 704         i = rx_ring->next_to_clean;
 705         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 706         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 707         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 708
 709         while (staterr & IXGBE_RXD_STAT_DD) {
 710                 u32 upper_len = 0;
 711                 if (*work_done >= work_to_do)
 712                         break;
 713                 (*work_done)++;
 714
 715                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 716                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 717                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 718                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 719                         if (hdr_info & IXGBE_RXDADV_SPH)
 720                                 adapter->rx_hdr_split++;
 721                         if (len > IXGBE_RX_HDR_SIZE)
 722                                 len = IXGBE_RX_HDR_SIZE;
 723                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 724                 } else {
 725                         len = le16_to_cpu(rx_desc->wb.upper.length);
 726                 }
 727
 728                 cleaned = true;
 729                 skb = rx_buffer_info->skb;
 730                 prefetch(skb->data - NET_IP_ALIGN);
 731                 rx_buffer_info->skb = NULL;
 732
 733                 if (rx_buffer_info->dma) {
 734                         pci_unmap_single(pdev, rx_buffer_info->dma,
 735                                          rx_ring->rx_buf_len,
 736                                          PCI_DMA_FROMDEVICE);
 737                         rx_buffer_info->dma = 0;
 738                         skb_put(skb, len);
 739                 }
 740
 741                 if (upper_len) {
 742                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 743                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 744                         rx_buffer_info->page_dma = 0;
 745                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 746                                            rx_buffer_info->page,
 747                                            rx_buffer_info->page_offset,
 748                                            upper_len);
 749
 750                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 751                             (page_count(rx_buffer_info->page) != 1))
 752                                 rx_buffer_info->page = NULL;
 753                         else
 754                                 get_page(rx_buffer_info->page);
 755
 756                         skb->len += upper_len;
 757                         skb->data_len += upper_len;
 758                         skb->truesize += upper_len;
 759                 }
 760
 761                 i++;
 762                 if (i == rx_ring->count)
 763                         i = 0;
 764
 765                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 766                 prefetch(next_rxd);
 767                 cleaned_count++;
 768
 769                 if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)
 770                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 771
 772                 if (rsc_count) {
 773                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 774                                      IXGBE_RXDADV_NEXTP_SHIFT;
 775                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 776                         rx_ring->rsc_count += (rsc_count - 1);
 777                 } else {
 778                         next_buffer = &rx_ring->rx_buffer_info[i];
 779                 }
 780
 781                 if (staterr & IXGBE_RXD_STAT_EOP) {
 782                         if (skb->prev)
 783                                 skb = ixgbe_transform_rsc_queue(skb);
 784                         rx_ring->stats.packets++;
 785                         rx_ring->stats.bytes += skb->len;
 786                 } else {
 787                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 788                                 rx_buffer_info->skb = next_buffer->skb;
 789                                 rx_buffer_info->dma = next_buffer->dma;
 790                                 next_buffer->skb = skb;
 791                                 next_buffer->dma = 0;
 792                         } else {
 793                                 skb->next = next_buffer->skb;
 794                                 skb->next->prev = skb;
 795                         }
 796                         adapter->non_eop_descs++;
 797                         goto next_desc;
 798                 }
 799
 800                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 801                         dev_kfree_skb_irq(skb);
 802                         goto next_desc;
 803                 }
 804
 805                 ixgbe_rx_checksum(adapter, staterr, skb);
 806
 807                 /* probably a little skewed due to removing CRC */
 808                 total_rx_bytes += skb->len;
 809                 total_rx_packets++;
 810
 811                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 812 #ifdef IXGBE_FCOE
 813                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 814                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 815                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 816                         if (!ddp_bytes)
 817                                 goto next_desc;
 818                 }
 819 #endif /* IXGBE_FCOE */
 820                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 821
 822 next_desc:
 823                 rx_desc->wb.upper.status_error = 0;
 824
 825                 /* return some buffers to hardware, one at a time is too slow */
 826                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 827                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 828                         cleaned_count = 0;
 829                 }
 830
 831                 /* use prefetched values */
 832                 rx_desc = next_rxd;
 833                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 834
 835                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 836         }
 837
 838         rx_ring->next_to_clean = i;
 839         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 840
 841         if (cleaned_count)
 842                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 843
 844 #ifdef IXGBE_FCOE
 845         /* include DDPed FCoE data */
 846         if (ddp_bytes > 0) {
 847                 unsigned int mss;
 848
 849                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 850                         sizeof(struct fc_frame_header) -
 851                         sizeof(struct fcoe_crc_eof);
 852                 if (mss > 512)
 853                         mss &= ~511;
 854                 total_rx_bytes += ddp_bytes;
 855                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 856         }
 857 #endif /* IXGBE_FCOE */
 858
 859         rx_ring->total_packets += total_rx_packets;
 860         rx_ring->total_bytes += total_rx_bytes;
 861         adapter->net_stats.rx_bytes += total_rx_bytes;
 862         adapter->net_stats.rx_packets += total_rx_packets;
 863
 864         return cleaned;
 865 }
 866
 867 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 868 /**
 869  * ixgbe_configure_msix - Configure MSI-X hardware
 870  * @adapter: board private structure
 871  *
 872  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 873  * interrupts.
 874  **/
 875 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 876 {
 877         struct ixgbe_q_vector *q_vector;
 878         int i, j, q_vectors, v_idx, r_idx;
 879         u32 mask;
 880
 881         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 882
 883         /*
 884          * Populate the IVAR table and set the ITR values to the
 885          * corresponding register.
 886          */
 887         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 888                 q_vector = adapter->q_vector[v_idx];
 889                 /* XXX for_each_bit(...) */
 890                 r_idx = find_first_bit(q_vector->rxr_idx,
 891                                        adapter->num_rx_queues);
 892
 893                 for (i = 0; i < q_vector->rxr_count; i++) {
 894                         j = adapter->rx_ring[r_idx].reg_idx;
 895                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 896                         r_idx = find_next_bit(q_vector->rxr_idx,
 897                                               adapter->num_rx_queues,
 898                                               r_idx + 1);
 899                 }
 900                 r_idx = find_first_bit(q_vector->txr_idx,
 901                                        adapter->num_tx_queues);
 902
 903                 for (i = 0; i < q_vector->txr_count; i++) {
 904                         j = adapter->tx_ring[r_idx].reg_idx;
 905                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 906                         r_idx = find_next_bit(q_vector->txr_idx,
 907                                               adapter->num_tx_queues,
 908                                               r_idx + 1);
 909                 }
 910
 911                 /* if this is a tx only vector halve the interrupt rate */
 912                 if (q_vector->txr_count && !q_vector->rxr_count)
 913                         q_vector->eitr = (adapter->eitr_param >> 1);
 914                 else if (q_vector->rxr_count)
 915                         /* rx only */
 916                         q_vector->eitr = adapter->eitr_param;
 917
 918                 ixgbe_write_eitr(q_vector);
 919         }
 920
 921         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 922                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 923                                v_idx);
 924         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 925                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 926         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 927
 928         /* set up to autoclear timer, and the vectors */
 929         mask = IXGBE_EIMS_ENABLE_MASK;
 930         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 931         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 932 }
 933
 934 enum latency_range {
 935         lowest_latency = 0,
 936         low_latency = 1,
 937         bulk_latency = 2,
 938         latency_invalid = 255
 939 };
 940
 941 /**
 942  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 943  * @adapter: pointer to adapter
 944  * @eitr: eitr setting (ints per sec) to give last timeslice
 945  * @itr_setting: current throttle rate in ints/second
 946  * @packets: the number of packets during this measurement interval
 947  * @bytes: the number of bytes during this measurement interval
 948  *
 949  *      Stores a new ITR value based on packets and byte
 950  *      counts during the last interrupt.  The advantage of per interrupt
 951  *      computation is faster updates and more accurate ITR for the current
 952  *      traffic pattern.  Constants in this function were computed
 953  *      based on theoretical maximum wire speed and thresholds were set based
 954  *      on testing data as well as attempting to minimize response time
 955  *      while increasing bulk throughput.
 956  *      this functionality is controlled by the InterruptThrottleRate module
 957  *      parameter (see ixgbe_param.c)
 958  **/
 959 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 960                            u32 eitr, u8 itr_setting,
 961                            int packets, int bytes)
 962 {
 963         unsigned int retval = itr_setting;
 964         u32 timepassed_us;
 965         u64 bytes_perint;
 966
 967         if (packets == 0)
 968                 goto update_itr_done;
 969
 970
 971         /* simple throttlerate management
 972          *    0-20MB/s lowest (100000 ints/s)
 973          *   20-100MB/s low   (20000 ints/s)
 974          *  100-1249MB/s bulk (8000 ints/s)
 975          */
 976         /* what was last interrupt timeslice? */
 977         timepassed_us = 1000000/eitr;
 978         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 979
 980         switch (itr_setting) {
 981         case lowest_latency:
 982                 if (bytes_perint > adapter->eitr_low)
 983                         retval = low_latency;
 984                 break;
 985         case low_latency:
 986                 if (bytes_perint > adapter->eitr_high)
 987                         retval = bulk_latency;
 988                 else if (bytes_perint <= adapter->eitr_low)
 989                         retval = lowest_latency;
 990                 break;
 991         case bulk_latency:
 992                 if (bytes_perint <= adapter->eitr_high)
 993                         retval = low_latency;
 994                 break;
 995         }
 996
 997 update_itr_done:
 998         return retval;
 999 }
1000
1001 /**
1002  * ixgbe_write_eitr - write EITR register in hardware specific way
1003  * @q_vector: structure containing interrupt and ring information
1004  *
1005  * This function is made to be called by ethtool and by the driver
1006  * when it needs to update EITR registers at runtime.  Hardware
1007  * specific quirks/differences are taken care of here.
1008  */
1009 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1010 {
1011         struct ixgbe_adapter *adapter = q_vector->adapter;
1012         struct ixgbe_hw *hw = &adapter->hw;
1013         int v_idx = q_vector->v_idx;
1014         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1015
1016         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1017                 /* must write high and low 16 bits to reset counter */
1018                 itr_reg |= (itr_reg << 16);
1019         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1020                 /*
1021                  * set the WDIS bit to not clear the timer bits and cause an
1022                  * immediate assertion of the interrupt
1023                  */
1024                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1025         }
1026         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1027 }
1028
1029 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1030 {
1031         struct ixgbe_adapter *adapter = q_vector->adapter;
1032         u32 new_itr;
1033         u8 current_itr, ret_itr;
1034         int i, r_idx;
1035         struct ixgbe_ring *rx_ring, *tx_ring;
1036
1037         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1038         for (i = 0; i < q_vector->txr_count; i++) {
1039                 tx_ring = &(adapter->tx_ring[r_idx]);
1040                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1041                                            q_vector->tx_itr,
1042                                            tx_ring->total_packets,
1043                                            tx_ring->total_bytes);
1044                 /* if the result for this queue would decrease interrupt
1045                  * rate for this vector then use that result */
1046                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1047                                     q_vector->tx_itr - 1 : ret_itr);
1048                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1049                                       r_idx + 1);
1050         }
1051
1052         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1053         for (i = 0; i < q_vector->rxr_count; i++) {
1054                 rx_ring = &(adapter->rx_ring[r_idx]);
1055                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1056                                            q_vector->rx_itr,
1057                                            rx_ring->total_packets,
1058                                            rx_ring->total_bytes);
1059                 /* if the result for this queue would decrease interrupt
1060                  * rate for this vector then use that result */
1061                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1062                                     q_vector->rx_itr - 1 : ret_itr);
1063                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1064                                       r_idx + 1);
1065         }
1066
1067         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1068
1069         switch (current_itr) {
1070         /* counts and packets in update_itr are dependent on these numbers */
1071         case lowest_latency:
1072                 new_itr = 100000;
1073                 break;
1074         case low_latency:
1075                 new_itr = 20000; /* aka hwitr = ~200 */
1076                 break;
1077         case bulk_latency:
1078         default:
1079                 new_itr = 8000;
1080                 break;
1081         }
1082
1083         if (new_itr != q_vector->eitr) {
1084                 /* do an exponential smoothing */
1085                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1086
1087                 /* save the algorithm value here, not the smoothed one */
1088                 q_vector->eitr = new_itr;
1089
1090                 ixgbe_write_eitr(q_vector);
1091         }
1092
1093         return;
1094 }
1095
1096 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1097 {
1098         struct ixgbe_hw *hw = &adapter->hw;
1099
1100         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1101             (eicr & IXGBE_EICR_GPI_SDP1)) {
1102                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1103                 /* write to clear the interrupt */
1104                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1105         }
1106 }
1107
1108 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1109 {
1110         struct ixgbe_hw *hw = &adapter->hw;
1111
1112         if (eicr & IXGBE_EICR_GPI_SDP1) {
1113                 /* Clear the interrupt */
1114                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1115                 schedule_work(&adapter->multispeed_fiber_task);
1116         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1117                 /* Clear the interrupt */
1118                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1119                 schedule_work(&adapter->sfp_config_module_task);
1120         } else {
1121                 /* Interrupt isn't for us... */
1122                 return;
1123         }
1124 }
1125
1126 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1127 {
1128         struct ixgbe_hw *hw = &adapter->hw;
1129
1130         adapter->lsc_int++;
1131         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1132         adapter->link_check_timeout = jiffies;
1133         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1134                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1135                 schedule_work(&adapter->watchdog_task);
1136         }
1137 }
1138
1139 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1140 {
1141         struct net_device *netdev = data;
1142         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1143         struct ixgbe_hw *hw = &adapter->hw;
1144         u32 eicr;
1145
1146         /*
1147          * Workaround for Silicon errata.  Use clear-by-write instead
1148          * of clear-by-read.  Reading with EICS will return the
1149          * interrupt causes without clearing, which later be done
1150          * with the write to EICR.
1151          */
1152         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1153         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1154
1155         if (eicr & IXGBE_EICR_LSC)
1156                 ixgbe_check_lsc(adapter);
1157
1158         if (hw->mac.type == ixgbe_mac_82598EB)
1159                 ixgbe_check_fan_failure(adapter, eicr);
1160
1161         if (hw->mac.type == ixgbe_mac_82599EB) {
1162                 ixgbe_check_sfp_event(adapter, eicr);
1163
1164                 /* Handle Flow Director Full threshold interrupt */
1165                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1166                         int i;
1167                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1168                         /* Disable transmits before FDIR Re-initialization */
1169                         netif_tx_stop_all_queues(netdev);
1170                         for (i = 0; i < adapter->num_tx_queues; i++) {
1171                                 struct ixgbe_ring *tx_ring =
1172                                                            &adapter->tx_ring[i];
1173                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1174                                                        &tx_ring->reinit_state))
1175                                         schedule_work(&adapter->fdir_reinit_task);
1176                         }
1177                 }
1178         }
1179         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1180                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1181
1182         return IRQ_HANDLED;
1183 }
1184
1185 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1186                                            u64 qmask)
1187 {
1188         u32 mask;
1189
1190         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1191                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1192                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1193         } else {
1194                 mask = (qmask & 0xFFFFFFFF);
1195                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1196                 mask = (qmask >> 32);
1197                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1198         }
1199         /* skip the flush */
1200 }
1201
1202 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1203                                             u64 qmask)
1204 {
1205         u32 mask;
1206
1207         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1208                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1209                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1210         } else {
1211                 mask = (qmask & 0xFFFFFFFF);
1212                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1213                 mask = (qmask >> 32);
1214                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1215         }
1216         /* skip the flush */
1217 }
1218
1219 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1220 {
1221         struct ixgbe_q_vector *q_vector = data;
1222         struct ixgbe_adapter  *adapter = q_vector->adapter;
1223         struct ixgbe_ring     *tx_ring;
1224         int i, r_idx;
1225
1226         if (!q_vector->txr_count)
1227                 return IRQ_HANDLED;
1228
1229         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1230         for (i = 0; i < q_vector->txr_count; i++) {
1231                 tx_ring = &(adapter->tx_ring[r_idx]);
1232                 tx_ring->total_bytes = 0;
1233                 tx_ring->total_packets = 0;
1234                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1235                                       r_idx + 1);
1236         }
1237
1238         /* disable interrupts on this vector only */
1239         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1240         napi_schedule(&q_vector->napi);
1241
1242         return IRQ_HANDLED;
1243 }
1244
1245 /**
1246  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1247  * @irq: unused
1248  * @data: pointer to our q_vector struct for this interrupt vector
1249  **/
1250 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1251 {
1252         struct ixgbe_q_vector *q_vector = data;
1253         struct ixgbe_adapter  *adapter = q_vector->adapter;
1254         struct ixgbe_ring  *rx_ring;
1255         int r_idx;
1256         int i;
1257
1258         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1259         for (i = 0;  i < q_vector->rxr_count; i++) {
1260                 rx_ring = &(adapter->rx_ring[r_idx]);
1261                 rx_ring->total_bytes = 0;
1262                 rx_ring->total_packets = 0;
1263                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1264                                       r_idx + 1);
1265         }
1266
1267         if (!q_vector->rxr_count)
1268                 return IRQ_HANDLED;
1269
1270         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1271         rx_ring = &(adapter->rx_ring[r_idx]);
1272         /* disable interrupts on this vector only */
1273         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1274         napi_schedule(&q_vector->napi);
1275
1276         return IRQ_HANDLED;
1277 }
1278
1279 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1280 {
1281         struct ixgbe_q_vector *q_vector = data;
1282         struct ixgbe_adapter  *adapter = q_vector->adapter;
1283         struct ixgbe_ring  *ring;
1284         int r_idx;
1285         int i;
1286
1287         if (!q_vector->txr_count && !q_vector->rxr_count)
1288                 return IRQ_HANDLED;
1289
1290         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1291         for (i = 0; i < q_vector->txr_count; i++) {
1292                 ring = &(adapter->tx_ring[r_idx]);
1293                 ring->total_bytes = 0;
1294                 ring->total_packets = 0;
1295                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1296                                       r_idx + 1);
1297         }
1298
1299         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1300         for (i = 0; i < q_vector->rxr_count; i++) {
1301                 ring = &(adapter->rx_ring[r_idx]);
1302                 ring->total_bytes = 0;
1303                 ring->total_packets = 0;
1304                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1305                                       r_idx + 1);
1306         }
1307
1308         /* disable interrupts on this vector only */
1309         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1310         napi_schedule(&q_vector->napi);
1311
1312         return IRQ_HANDLED;
1313 }
1314
1315 /**
1316  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1317  * @napi: napi struct with our devices info in it
1318  * @budget: amount of work driver is allowed to do this pass, in packets
1319  *
1320  * This function is optimized for cleaning one queue only on a single
1321  * q_vector!!!
1322  **/
1323 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1324 {
1325         struct ixgbe_q_vector *q_vector =
1326                                container_of(napi, struct ixgbe_q_vector, napi);
1327         struct ixgbe_adapter *adapter = q_vector->adapter;
1328         struct ixgbe_ring *rx_ring = NULL;
1329         int work_done = 0;
1330         long r_idx;
1331
1332         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1333         rx_ring = &(adapter->rx_ring[r_idx]);
1334 #ifdef CONFIG_IXGBE_DCA
1335         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1336                 ixgbe_update_rx_dca(adapter, rx_ring);
1337 #endif
1338
1339         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1340
1341         /* If all Rx work done, exit the polling mode */
1342         if (work_done < budget) {
1343                 napi_complete(napi);
1344                 if (adapter->itr_setting & 1)
1345                         ixgbe_set_itr_msix(q_vector);
1346                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1347                         ixgbe_irq_enable_queues(adapter,
1348                                                 ((u64)1 << q_vector->v_idx));
1349         }
1350
1351         return work_done;
1352 }
1353
1354 /**
1355  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1356  * @napi: napi struct with our devices info in it
1357  * @budget: amount of work driver is allowed to do this pass, in packets
1358  *
1359  * This function will clean more than one rx queue associated with a
1360  * q_vector.
1361  **/
1362 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1363 {
1364         struct ixgbe_q_vector *q_vector =
1365                                container_of(napi, struct ixgbe_q_vector, napi);
1366         struct ixgbe_adapter *adapter = q_vector->adapter;
1367         struct ixgbe_ring *ring = NULL;
1368         int work_done = 0, i;
1369         long r_idx;
1370         bool tx_clean_complete = true;
1371
1372         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1373         for (i = 0; i < q_vector->txr_count; i++) {
1374                 ring = &(adapter->tx_ring[r_idx]);
1375 #ifdef CONFIG_IXGBE_DCA
1376                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1377                         ixgbe_update_tx_dca(adapter, ring);
1378 #endif
1379                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1380                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1381                                       r_idx + 1);
1382         }
1383
1384         /* attempt to distribute budget to each queue fairly, but don't allow
1385          * the budget to go below 1 because we'll exit polling */
1386         budget /= (q_vector->rxr_count ?: 1);
1387         budget = max(budget, 1);
1388         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1389         for (i = 0; i < q_vector->rxr_count; i++) {
1390                 ring = &(adapter->rx_ring[r_idx]);
1391 #ifdef CONFIG_IXGBE_DCA
1392                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1393                         ixgbe_update_rx_dca(adapter, ring);
1394 #endif
1395                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1396                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1397                                       r_idx + 1);
1398         }
1399
1400         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1401         ring = &(adapter->rx_ring[r_idx]);
1402         /* If all Rx work done, exit the polling mode */
1403         if (work_done < budget) {
1404                 napi_complete(napi);
1405                 if (adapter->itr_setting & 1)
1406                         ixgbe_set_itr_msix(q_vector);
1407                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1408                         ixgbe_irq_enable_queues(adapter,
1409                                                 ((u64)1 << q_vector->v_idx));
1410                 return 0;
1411         }
1412
1413         return work_done;
1414 }
1415
1416 /**
1417  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1418  * @napi: napi struct with our devices info in it
1419  * @budget: amount of work driver is allowed to do this pass, in packets
1420  *
1421  * This function is optimized for cleaning one queue only on a single
1422  * q_vector!!!
1423  **/
1424 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1425 {
1426         struct ixgbe_q_vector *q_vector =
1427                                container_of(napi, struct ixgbe_q_vector, napi);
1428         struct ixgbe_adapter *adapter = q_vector->adapter;
1429         struct ixgbe_ring *tx_ring = NULL;
1430         int work_done = 0;
1431         long r_idx;
1432
1433         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1434         tx_ring = &(adapter->tx_ring[r_idx]);
1435 #ifdef CONFIG_IXGBE_DCA
1436         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1437                 ixgbe_update_tx_dca(adapter, tx_ring);
1438 #endif
1439
1440         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1441                 work_done = budget;
1442
1443         /* If all Rx work done, exit the polling mode */
1444         if (work_done < budget) {
1445                 napi_complete(napi);
1446                 if (adapter->itr_setting & 1)
1447                         ixgbe_set_itr_msix(q_vector);
1448                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1449                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1450         }
1451
1452         return work_done;
1453 }
1454
1455 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1456                                      int r_idx)
1457 {
1458         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1459
1460         set_bit(r_idx, q_vector->rxr_idx);
1461         q_vector->rxr_count++;
1462 }
1463
1464 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1465                                      int t_idx)
1466 {
1467         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1468
1469         set_bit(t_idx, q_vector->txr_idx);
1470         q_vector->txr_count++;
1471 }
1472
1473 /**
1474  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1475  * @adapter: board private structure to initialize
1476  * @vectors: allotted vector count for descriptor rings
1477  *
1478  * This function maps descriptor rings to the queue-specific vectors
1479  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1480  * one vector per ring/queue, but on a constrained vector budget, we
1481  * group the rings as "efficiently" as possible.  You would add new
1482  * mapping configurations in here.
1483  **/
1484 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1485                                       int vectors)
1486 {
1487         int v_start = 0;
1488         int rxr_idx = 0, txr_idx = 0;
1489         int rxr_remaining = adapter->num_rx_queues;
1490         int txr_remaining = adapter->num_tx_queues;
1491         int i, j;
1492         int rqpv, tqpv;
1493         int err = 0;
1494
1495         /* No mapping required if MSI-X is disabled. */
1496         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1497                 goto out;
1498
1499         /*
1500          * The ideal configuration...
1501          * We have enough vectors to map one per queue.
1502          */
1503         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1504                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1505                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1506
1507                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1508                         map_vector_to_txq(adapter, v_start, txr_idx);
1509
1510                 goto out;
1511         }
1512
1513         /*
1514          * If we don't have enough vectors for a 1-to-1
1515          * mapping, we'll have to group them so there are
1516          * multiple queues per vector.
1517          */
1518         /* Re-adjusting *qpv takes care of the remainder. */
1519         for (i = v_start; i < vectors; i++) {
1520                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1521                 for (j = 0; j < rqpv; j++) {
1522                         map_vector_to_rxq(adapter, i, rxr_idx);
1523                         rxr_idx++;
1524                         rxr_remaining--;
1525                 }
1526         }
1527         for (i = v_start; i < vectors; i++) {
1528                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1529                 for (j = 0; j < tqpv; j++) {
1530                         map_vector_to_txq(adapter, i, txr_idx);
1531                         txr_idx++;
1532                         txr_remaining--;
1533                 }
1534         }
1535
1536 out:
1537         return err;
1538 }
1539
1540 /**
1541  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1542  * @adapter: board private structure
1543  *
1544  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1545  * interrupts from the kernel.
1546  **/
1547 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1548 {
1549         struct net_device *netdev = adapter->netdev;
1550         irqreturn_t (*handler)(int, void *);
1551         int i, vector, q_vectors, err;
1552         int ri=0, ti=0;
1553
1554         /* Decrement for Other and TCP Timer vectors */
1555         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1556
1557         /* Map the Tx/Rx rings to the vectors we were allotted. */
1558         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1559         if (err)
1560                 goto out;
1561
1562 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1563                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1564                          &ixgbe_msix_clean_many)
1565         for (vector = 0; vector < q_vectors; vector++) {
1566                 handler = SET_HANDLER(adapter->q_vector[vector]);
1567
1568                 if(handler == &ixgbe_msix_clean_rx) {
1569                         sprintf(adapter->name[vector], "%s-%s-%d",
1570                                 netdev->name, "rx", ri++);
1571                 }
1572                 else if(handler == &ixgbe_msix_clean_tx) {
1573                         sprintf(adapter->name[vector], "%s-%s-%d",
1574                                 netdev->name, "tx", ti++);
1575                 }
1576                 else
1577                         sprintf(adapter->name[vector], "%s-%s-%d",
1578                                 netdev->name, "TxRx", vector);
1579
1580                 err = request_irq(adapter->msix_entries[vector].vector,
1581                                   handler, 0, adapter->name[vector],
1582                                   adapter->q_vector[vector]);
1583                 if (err) {
1584                         DPRINTK(PROBE, ERR,
1585                                 "request_irq failed for MSIX interrupt "
1586                                 "Error: %d\n", err);
1587                         goto free_queue_irqs;
1588                 }
1589         }
1590
1591         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1592         err = request_irq(adapter->msix_entries[vector].vector,
1593                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1594         if (err) {
1595                 DPRINTK(PROBE, ERR,
1596                         "request_irq for msix_lsc failed: %d\n", err);
1597                 goto free_queue_irqs;
1598         }
1599
1600         return 0;
1601
1602 free_queue_irqs:
1603         for (i = vector - 1; i >= 0; i--)
1604                 free_irq(adapter->msix_entries[--vector].vector,
1605                          adapter->q_vector[i]);
1606         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1607         pci_disable_msix(adapter->pdev);
1608         kfree(adapter->msix_entries);
1609         adapter->msix_entries = NULL;
1610 out:
1611         return err;
1612 }
1613
1614 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1615 {
1616         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1617         u8 current_itr;
1618         u32 new_itr = q_vector->eitr;
1619         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1620         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1621
1622         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1623                                             q_vector->tx_itr,
1624                                             tx_ring->total_packets,
1625                                             tx_ring->total_bytes);
1626         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1627                                             q_vector->rx_itr,
1628                                             rx_ring->total_packets,
1629                                             rx_ring->total_bytes);
1630
1631         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1632
1633         switch (current_itr) {
1634         /* counts and packets in update_itr are dependent on these numbers */
1635         case lowest_latency:
1636                 new_itr = 100000;
1637                 break;
1638         case low_latency:
1639                 new_itr = 20000; /* aka hwitr = ~200 */
1640                 break;
1641         case bulk_latency:
1642                 new_itr = 8000;
1643                 break;
1644         default:
1645                 break;
1646         }
1647
1648         if (new_itr != q_vector->eitr) {
1649                 /* do an exponential smoothing */
1650                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1651
1652                 /* save the algorithm value here, not the smoothed one */
1653                 q_vector->eitr = new_itr;
1654
1655                 ixgbe_write_eitr(q_vector);
1656         }
1657
1658         return;
1659 }
1660
1661 /**
1662  * ixgbe_irq_enable - Enable default interrupt generation settings
1663  * @adapter: board private structure
1664  **/
1665 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1666 {
1667         u32 mask;
1668
1669         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1670         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1671                 mask |= IXGBE_EIMS_GPI_SDP1;
1672         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1673                 mask |= IXGBE_EIMS_ECC;
1674                 mask |= IXGBE_EIMS_GPI_SDP1;
1675                 mask |= IXGBE_EIMS_GPI_SDP2;
1676         }
1677         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1678             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1679                 mask |= IXGBE_EIMS_FLOW_DIR;
1680
1681         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1682         ixgbe_irq_enable_queues(adapter, ~0);
1683         IXGBE_WRITE_FLUSH(&adapter->hw);
1684 }
1685
1686 /**
1687  * ixgbe_intr - legacy mode Interrupt Handler
1688  * @irq: interrupt number
1689  * @data: pointer to a network interface device structure
1690  **/
1691 static irqreturn_t ixgbe_intr(int irq, void *data)
1692 {
1693         struct net_device *netdev = data;
1694         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1695         struct ixgbe_hw *hw = &adapter->hw;
1696         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1697         u32 eicr;
1698
1699         /*
1700          * Workaround for silicon errata.  Mask the interrupts
1701          * before the read of EICR.
1702          */
1703         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1704
1705         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1706          * therefore no explict interrupt disable is necessary */
1707         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1708         if (!eicr) {
1709                 /* shared interrupt alert!
1710                  * make sure interrupts are enabled because the read will
1711                  * have disabled interrupts due to EIAM */
1712                 ixgbe_irq_enable(adapter);
1713                 return IRQ_NONE;        /* Not our interrupt */
1714         }
1715
1716         if (eicr & IXGBE_EICR_LSC)
1717                 ixgbe_check_lsc(adapter);
1718
1719         if (hw->mac.type == ixgbe_mac_82599EB)
1720                 ixgbe_check_sfp_event(adapter, eicr);
1721
1722         ixgbe_check_fan_failure(adapter, eicr);
1723
1724         if (napi_schedule_prep(&(q_vector->napi))) {
1725                 adapter->tx_ring[0].total_packets = 0;
1726                 adapter->tx_ring[0].total_bytes = 0;
1727                 adapter->rx_ring[0].total_packets = 0;
1728                 adapter->rx_ring[0].total_bytes = 0;
1729                 /* would disable interrupts here but EIAM disabled it */
1730                 __napi_schedule(&(q_vector->napi));
1731         }
1732
1733         return IRQ_HANDLED;
1734 }
1735
1736 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1737 {
1738         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1739
1740         for (i = 0; i < q_vectors; i++) {
1741                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1742                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1743                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1744                 q_vector->rxr_count = 0;
1745                 q_vector->txr_count = 0;
1746         }
1747 }
1748
1749 /**
1750  * ixgbe_request_irq - initialize interrupts
1751  * @adapter: board private structure
1752  *
1753  * Attempts to configure interrupts using the best available
1754  * capabilities of the hardware and kernel.
1755  **/
1756 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1757 {
1758         struct net_device *netdev = adapter->netdev;
1759         int err;
1760
1761         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1762                 err = ixgbe_request_msix_irqs(adapter);
1763         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1764                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1765                                   netdev->name, netdev);
1766         } else {
1767                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1768                                   netdev->name, netdev);
1769         }
1770
1771         if (err)
1772                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1773
1774         return err;
1775 }
1776
1777 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1778 {
1779         struct net_device *netdev = adapter->netdev;
1780
1781         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1782                 int i, q_vectors;
1783
1784                 q_vectors = adapter->num_msix_vectors;
1785
1786                 i = q_vectors - 1;
1787                 free_irq(adapter->msix_entries[i].vector, netdev);
1788
1789                 i--;
1790                 for (; i >= 0; i--) {
1791                         free_irq(adapter->msix_entries[i].vector,
1792                                  adapter->q_vector[i]);
1793                 }
1794
1795                 ixgbe_reset_q_vectors(adapter);
1796         } else {
1797                 free_irq(adapter->pdev->irq, netdev);
1798         }
1799 }
1800
1801 /**
1802  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1803  * @adapter: board private structure
1804  **/
1805 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1806 {
1807         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1808                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1809         } else {
1810                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1811                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1812                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1813         }
1814         IXGBE_WRITE_FLUSH(&adapter->hw);
1815         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1816                 int i;
1817                 for (i = 0; i < adapter->num_msix_vectors; i++)
1818                         synchronize_irq(adapter->msix_entries[i].vector);
1819         } else {
1820                 synchronize_irq(adapter->pdev->irq);
1821         }
1822 }
1823
1824 /**
1825  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1826  *
1827  **/
1828 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1829 {
1830         struct ixgbe_hw *hw = &adapter->hw;
1831
1832         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1833                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1834
1835         ixgbe_set_ivar(adapter, 0, 0, 0);
1836         ixgbe_set_ivar(adapter, 1, 0, 0);
1837
1838         map_vector_to_rxq(adapter, 0, 0);
1839         map_vector_to_txq(adapter, 0, 0);
1840
1841         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1842 }
1843
1844 /**
1845  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1846  * @adapter: board private structure
1847  *
1848  * Configure the Tx unit of the MAC after a reset.
1849  **/
1850 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1851 {
1852         u64 tdba;
1853         struct ixgbe_hw *hw = &adapter->hw;
1854         u32 i, j, tdlen, txctrl;
1855
1856         /* Setup the HW Tx Head and Tail descriptor pointers */
1857         for (i = 0; i < adapter->num_tx_queues; i++) {
1858                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1859                 j = ring->reg_idx;
1860                 tdba = ring->dma;
1861                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1862                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1863                                 (tdba & DMA_BIT_MASK(32)));
1864                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1865                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1866                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1867                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1868                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1869                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1870                 /* Disable Tx Head Writeback RO bit, since this hoses
1871                  * bookkeeping if things aren't delivered in order.
1872                  */
1873                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1874                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1875                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1876         }
1877         if (hw->mac.type == ixgbe_mac_82599EB) {
1878                 /* We enable 8 traffic classes, DCB only */
1879                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1880                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1881                                         IXGBE_MTQC_8TC_8TQ));
1882         }
1883 }
1884
1885 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1886
1887 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1888 {
1889         struct ixgbe_ring *rx_ring;
1890         u32 srrctl;
1891         int queue0 = 0;
1892         unsigned long mask;
1893         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1894
1895         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1896                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1897                         int dcb_i = feature[RING_F_DCB].indices;
1898                         if (dcb_i == 8)
1899                                 queue0 = index >> 4;
1900                         else if (dcb_i == 4)
1901                                 queue0 = index >> 5;
1902                         else
1903                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1904                                         "configuration\n");
1905 #ifdef IXGBE_FCOE
1906                         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1907                                 struct ixgbe_ring_feature *f;
1908
1909                                 rx_ring = &adapter->rx_ring[queue0];
1910                                 f = &adapter->ring_feature[RING_F_FCOE];
1911                                 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1912                                         queue0 = f->mask + index -
1913                                                  rx_ring->reg_idx - 1;
1914                         }
1915 #endif /* IXGBE_FCOE */
1916                 } else {
1917                         queue0 = index;
1918                 }
1919         } else {
1920                 mask = (unsigned long) feature[RING_F_RSS].mask;
1921                 queue0 = index & mask;
1922                 index = index & mask;
1923         }
1924
1925         rx_ring = &adapter->rx_ring[queue0];
1926
1927         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1928
1929         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1930         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1931
1932         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1933                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1934
1935         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1936 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1937                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1938 #else
1939                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1940 #endif
1941                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1942         } else {
1943                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1944                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1945                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1946         }
1947
1948         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1949 }
1950
1951 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1952 {
1953         u32 mrqc = 0;
1954         int mask;
1955
1956         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1957                 return mrqc;
1958
1959         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1960 #ifdef CONFIG_IXGBE_DCB
1961                                  | IXGBE_FLAG_DCB_ENABLED
1962 #endif
1963                                 );
1964
1965         switch (mask) {
1966         case (IXGBE_FLAG_RSS_ENABLED):
1967                 mrqc = IXGBE_MRQC_RSSEN;
1968                 break;
1969 #ifdef CONFIG_IXGBE_DCB
1970         case (IXGBE_FLAG_DCB_ENABLED):
1971                 mrqc = IXGBE_MRQC_RT8TCEN;
1972                 break;
1973 #endif /* CONFIG_IXGBE_DCB */
1974         default:
1975                 break;
1976         }
1977
1978         return mrqc;
1979 }
1980
1981 /**
1982  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1983  * @adapter: board private structure
1984  *
1985  * Configure the Rx unit of the MAC after a reset.
1986  **/
1987 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1988 {
1989         u64 rdba;
1990         struct ixgbe_hw *hw = &adapter->hw;
1991         struct net_device *netdev = adapter->netdev;
1992         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1993         int i, j;
1994         u32 rdlen, rxctrl, rxcsum;
1995         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1996                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1997                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1998         u32 fctrl, hlreg0;
1999         u32 reta = 0, mrqc = 0;
2000         u32 rdrxctl;
2001         u32 rscctrl;
2002         int rx_buf_len;
2003
2004         /* Decide whether to use packet split mode or not */
2005         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2006
2007 #ifdef IXGBE_FCOE
2008         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2009                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2010 #endif /* IXGBE_FCOE */
2011
2012         /* Set the RX buffer length according to the mode */
2013         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2014                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2015                 if (hw->mac.type == ixgbe_mac_82599EB) {
2016                         /* PSRTYPE must be initialized in 82599 */
2017                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2018                                       IXGBE_PSRTYPE_UDPHDR |
2019                                       IXGBE_PSRTYPE_IPV4HDR |
2020                                       IXGBE_PSRTYPE_IPV6HDR |
2021                                       IXGBE_PSRTYPE_L2HDR;
2022                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2023                 }
2024         } else {
2025                 if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) &&
2026                     (netdev->mtu <= ETH_DATA_LEN))
2027                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2028                 else
2029                         rx_buf_len = ALIGN(max_frame, 1024);
2030         }
2031
2032         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2033         fctrl |= IXGBE_FCTRL_BAM;
2034         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2035         fctrl |= IXGBE_FCTRL_PMCF;
2036         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2037
2038         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2039         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2040                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2041         else
2042                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2043 #ifdef IXGBE_FCOE
2044         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2045                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2046 #endif
2047         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2048
2049         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2050         /* disable receives while setting up the descriptors */
2051         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2052         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2053
2054         /*
2055          * Setup the HW Rx Head and Tail Descriptor Pointers and
2056          * the Base and Length of the Rx Descriptor Ring
2057          */
2058         for (i = 0; i < adapter->num_rx_queues; i++) {
2059                 rdba = adapter->rx_ring[i].dma;
2060                 j = adapter->rx_ring[i].reg_idx;
2061                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2062                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2063                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2064                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2065                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2066                 adapter->rx_ring[i].head = IXGBE_RDH(j);
2067                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2068                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
2069
2070 #ifdef IXGBE_FCOE
2071                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2072                         struct ixgbe_ring_feature *f;
2073                         f = &adapter->ring_feature[RING_F_FCOE];
2074                         if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2075                             (i >= f->mask) && (i < f->mask + f->indices))
2076                                 adapter->rx_ring[i].rx_buf_len =
2077                                         IXGBE_FCOE_JUMBO_FRAME_SIZE;
2078                 }
2079
2080 #endif /* IXGBE_FCOE */
2081                 ixgbe_configure_srrctl(adapter, j);
2082         }
2083
2084         if (hw->mac.type == ixgbe_mac_82598EB) {
2085                 /*
2086                  * For VMDq support of different descriptor types or
2087                  * buffer sizes through the use of multiple SRRCTL
2088                  * registers, RDRXCTL.MVMEN must be set to 1
2089                  *
2090                  * also, the manual doesn't mention it clearly but DCA hints
2091                  * will only use queue 0's tags unless this bit is set.  Side
2092                  * effects of setting this bit are only that SRRCTL must be
2093                  * fully programmed [0..15]
2094                  */
2095                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2096                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2097                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2098         }
2099
2100         /* Program MRQC for the distribution of queues */
2101         mrqc = ixgbe_setup_mrqc(adapter);
2102
2103         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2104                 /* Fill out redirection table */
2105                 for (i = 0, j = 0; i < 128; i++, j++) {
2106                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2107                                 j = 0;
2108                         /* reta = 4-byte sliding window of
2109                          * 0x00..(indices-1)(indices-1)00..etc. */
2110                         reta = (reta << 8) | (j * 0x11);
2111                         if ((i & 3) == 3)
2112                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2113                 }
2114
2115                 /* Fill out hash function seeds */
2116                 for (i = 0; i < 10; i++)
2117                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2118
2119                 if (hw->mac.type == ixgbe_mac_82598EB)
2120                         mrqc |= IXGBE_MRQC_RSSEN;
2121                     /* Perform hash on these packet types */
2122                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2123                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2124                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2125                       | IXGBE_MRQC_RSS_FIELD_IPV6
2126                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2127                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2128         }
2129         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2130
2131         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2132
2133         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2134             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2135                 /* Disable indicating checksum in descriptor, enables
2136                  * RSS hash */
2137                 rxcsum |= IXGBE_RXCSUM_PCSD;
2138         }
2139         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2140                 /* Enable IPv4 payload checksum for UDP fragments
2141                  * if PCSD is not set */
2142                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2143         }
2144
2145         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2146
2147         if (hw->mac.type == ixgbe_mac_82599EB) {
2148                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2149                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2150                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2151                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2152         }
2153
2154         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) {
2155                 /* Enable 82599 HW-RSC */
2156                 for (i = 0; i < adapter->num_rx_queues; i++) {
2157                         j = adapter->rx_ring[i].reg_idx;
2158                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2159                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2160                         /*
2161                          * we must limit the number of descriptors so that the
2162                          * total size of max desc * buf_len is not greater
2163                          * than 65535
2164                          */
2165                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2166 #if (MAX_SKB_FRAGS > 16)
2167                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2168 #elif (MAX_SKB_FRAGS > 8)
2169                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2170 #elif (MAX_SKB_FRAGS > 4)
2171                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2172 #else
2173                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2174 #endif
2175                         } else {
2176                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2177                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2178                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2179                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2180                                 else
2181                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2182                         }
2183                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2184                 }
2185                 /* Disable RSC for ACK packets */
2186                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2187                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2188         }
2189 }
2190
2191 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2192 {
2193         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2194         struct ixgbe_hw *hw = &adapter->hw;
2195
2196         /* add VID to filter table */
2197         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2198 }
2199
2200 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2201 {
2202         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2203         struct ixgbe_hw *hw = &adapter->hw;
2204
2205         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2206                 ixgbe_irq_disable(adapter);
2207
2208         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2209
2210         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2211                 ixgbe_irq_enable(adapter);
2212
2213         /* remove VID from filter table */
2214         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2215 }
2216
2217 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2218                                    struct vlan_group *grp)
2219 {
2220         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2221         u32 ctrl;
2222         int i, j;
2223
2224         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2225                 ixgbe_irq_disable(adapter);
2226         adapter->vlgrp = grp;
2227
2228         /*
2229          * For a DCB driver, always enable VLAN tag stripping so we can
2230          * still receive traffic from a DCB-enabled host even if we're
2231          * not in DCB mode.
2232          */
2233         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2234         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2235                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2236                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2237                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2238         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2239                 ctrl |= IXGBE_VLNCTRL_VFE;
2240                 /* enable VLAN tag insert/strip */
2241                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2242                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2243                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2244                 for (i = 0; i < adapter->num_rx_queues; i++) {
2245                         j = adapter->rx_ring[i].reg_idx;
2246                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2247                         ctrl |= IXGBE_RXDCTL_VME;
2248                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2249                 }
2250         }
2251         ixgbe_vlan_rx_add_vid(netdev, 0);
2252
2253         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2254                 ixgbe_irq_enable(adapter);
2255 }
2256
2257 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2258 {
2259         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2260
2261         if (adapter->vlgrp) {
2262                 u16 vid;
2263                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2264                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2265                                 continue;
2266                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2267                 }
2268         }
2269 }
2270
2271 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2272 {
2273         struct dev_mc_list *mc_ptr;
2274         u8 *addr = *mc_addr_ptr;
2275         *vmdq = 0;
2276
2277         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2278         if (mc_ptr->next)
2279                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2280         else
2281                 *mc_addr_ptr = NULL;
2282
2283         return addr;
2284 }
2285
2286 /**
2287  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2288  * @netdev: network interface device structure
2289  *
2290  * The set_rx_method entry point is called whenever the unicast/multicast
2291  * address list or the network interface flags are updated.  This routine is
2292  * responsible for configuring the hardware for proper unicast, multicast and
2293  * promiscuous mode.
2294  **/
2295 static void ixgbe_set_rx_mode(struct net_device *netdev)
2296 {
2297         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2298         struct ixgbe_hw *hw = &adapter->hw;
2299         u32 fctrl, vlnctrl;
2300         u8 *addr_list = NULL;
2301         int addr_count = 0;
2302
2303         /* Check for Promiscuous and All Multicast modes */
2304
2305         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2306         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2307
2308         if (netdev->flags & IFF_PROMISC) {
2309                 hw->addr_ctrl.user_set_promisc = 1;
2310                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2311                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2312         } else {
2313                 if (netdev->flags & IFF_ALLMULTI) {
2314                         fctrl |= IXGBE_FCTRL_MPE;
2315                         fctrl &= ~IXGBE_FCTRL_UPE;
2316                 } else {
2317                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2318                 }
2319                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2320                 hw->addr_ctrl.user_set_promisc = 0;
2321         }
2322
2323         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2324         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2325
2326         /* reprogram secondary unicast list */
2327         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2328
2329         /* reprogram multicast list */
2330         addr_count = netdev->mc_count;
2331         if (addr_count)
2332                 addr_list = netdev->mc_list->dmi_addr;
2333         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2334                                         ixgbe_addr_list_itr);
2335 }
2336
2337 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2338 {
2339         int q_idx;
2340         struct ixgbe_q_vector *q_vector;
2341         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2342
2343         /* legacy and MSI only use one vector */
2344         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2345                 q_vectors = 1;
2346
2347         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2348                 struct napi_struct *napi;
2349                 q_vector = adapter->q_vector[q_idx];
2350                 napi = &q_vector->napi;
2351                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2352                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2353                                 if (q_vector->txr_count == 1)
2354                                         napi->poll = &ixgbe_clean_txonly;
2355                                 else if (q_vector->rxr_count == 1)
2356                                         napi->poll = &ixgbe_clean_rxonly;
2357                         }
2358                 }
2359
2360                 napi_enable(napi);
2361         }
2362 }
2363
2364 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2365 {
2366         int q_idx;
2367         struct ixgbe_q_vector *q_vector;
2368         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2369
2370         /* legacy and MSI only use one vector */
2371         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2372                 q_vectors = 1;
2373
2374         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2375                 q_vector = adapter->q_vector[q_idx];
2376                 napi_disable(&q_vector->napi);
2377         }
2378 }
2379
2380 #ifdef CONFIG_IXGBE_DCB
2381 /*
2382  * ixgbe_configure_dcb - Configure DCB hardware
2383  * @adapter: ixgbe adapter struct
2384  *
2385  * This is called by the driver on open to configure the DCB hardware.
2386  * This is also called by the gennetlink interface when reconfiguring
2387  * the DCB state.
2388  */
2389 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2390 {
2391         struct ixgbe_hw *hw = &adapter->hw;
2392         u32 txdctl, vlnctrl;
2393         int i, j;
2394
2395         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2396         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2397         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2398
2399         /* reconfigure the hardware */
2400         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2401
2402         for (i = 0; i < adapter->num_tx_queues; i++) {
2403                 j = adapter->tx_ring[i].reg_idx;
2404                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2405                 /* PThresh workaround for Tx hang with DFP enabled. */
2406                 txdctl |= 32;
2407                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2408         }
2409         /* Enable VLAN tag insert/strip */
2410         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2411         if (hw->mac.type == ixgbe_mac_82598EB) {
2412                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2413                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2414                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2415         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2416                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2417                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2418                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2419                 for (i = 0; i < adapter->num_rx_queues; i++) {
2420                         j = adapter->rx_ring[i].reg_idx;
2421                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2422                         vlnctrl |= IXGBE_RXDCTL_VME;
2423                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2424                 }
2425         }
2426         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2427 }
2428
2429 #endif
2430 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2431 {
2432         struct net_device *netdev = adapter->netdev;
2433         struct ixgbe_hw *hw = &adapter->hw;
2434         int i;
2435
2436         ixgbe_set_rx_mode(netdev);
2437
2438         ixgbe_restore_vlan(adapter);
2439 #ifdef CONFIG_IXGBE_DCB
2440         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2441                 netif_set_gso_max_size(netdev, 32768);
2442                 ixgbe_configure_dcb(adapter);
2443         } else {
2444                 netif_set_gso_max_size(netdev, 65536);
2445         }
2446 #else
2447         netif_set_gso_max_size(netdev, 65536);
2448 #endif
2449
2450 #ifdef IXGBE_FCOE
2451         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2452                 ixgbe_configure_fcoe(adapter);
2453
2454 #endif /* IXGBE_FCOE */
2455         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2456                 for (i = 0; i < adapter->num_tx_queues; i++)
2457                         adapter->tx_ring[i].atr_sample_rate =
2458                                                        adapter->atr_sample_rate;
2459                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2460         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2461                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2462         }
2463
2464         ixgbe_configure_tx(adapter);
2465         ixgbe_configure_rx(adapter);
2466         for (i = 0; i < adapter->num_rx_queues; i++)
2467                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2468                                        (adapter->rx_ring[i].count - 1));
2469 }
2470
2471 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2472 {
2473         switch (hw->phy.type) {
2474         case ixgbe_phy_sfp_avago:
2475         case ixgbe_phy_sfp_ftl:
2476         case ixgbe_phy_sfp_intel:
2477         case ixgbe_phy_sfp_unknown:
2478         case ixgbe_phy_tw_tyco:
2479         case ixgbe_phy_tw_unknown:
2480                 return true;
2481         default:
2482                 return false;
2483         }
2484 }
2485
2486 /**
2487  * ixgbe_sfp_link_config - set up SFP+ link
2488  * @adapter: pointer to private adapter struct
2489  **/
2490 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2491 {
2492         struct ixgbe_hw *hw = &adapter->hw;
2493
2494                 if (hw->phy.multispeed_fiber) {
2495                         /*
2496                          * In multispeed fiber setups, the device may not have
2497                          * had a physical connection when the driver loaded.
2498                          * If that's the case, the initial link configuration
2499                          * couldn't get the MAC into 10G or 1G mode, so we'll
2500                          * never have a link status change interrupt fire.
2501                          * We need to try and force an autonegotiation
2502                          * session, then bring up link.
2503                          */
2504                         hw->mac.ops.setup_sfp(hw);
2505                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2506                                 schedule_work(&adapter->multispeed_fiber_task);
2507                 } else {
2508                         /*
2509                          * Direct Attach Cu and non-multispeed fiber modules
2510                          * still need to be configured properly prior to
2511                          * attempting link.
2512                          */
2513                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2514                                 schedule_work(&adapter->sfp_config_module_task);
2515                 }
2516 }
2517
2518 /**
2519  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2520  * @hw: pointer to private hardware struct
2521  *
2522  * Returns 0 on success, negative on failure
2523  **/
2524 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2525 {
2526         u32 autoneg;
2527         bool link_up = false;
2528         u32 ret = IXGBE_ERR_LINK_SETUP;
2529
2530         if (hw->mac.ops.check_link)
2531                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2532
2533         if (ret)
2534                 goto link_cfg_out;
2535
2536         if (hw->mac.ops.get_link_capabilities)
2537                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2538                                                         &hw->mac.autoneg);
2539         if (ret)
2540                 goto link_cfg_out;
2541
2542         if (hw->mac.ops.setup_link_speed)
2543                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2544 link_cfg_out:
2545         return ret;
2546 }
2547
2548 #define IXGBE_MAX_RX_DESC_POLL 10
2549 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2550                                               int rxr)
2551 {
2552         int j = adapter->rx_ring[rxr].reg_idx;
2553         int k;
2554
2555         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2556                 if (IXGBE_READ_REG(&adapter->hw,
2557                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2558                         break;
2559                 else
2560                         msleep(1);
2561         }
2562         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2563                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2564                         "not set within the polling period\n", rxr);
2565         }
2566         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2567                               (adapter->rx_ring[rxr].count - 1));
2568 }
2569
2570 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2571 {
2572         struct net_device *netdev = adapter->netdev;
2573         struct ixgbe_hw *hw = &adapter->hw;
2574         int i, j = 0;
2575         int num_rx_rings = adapter->num_rx_queues;
2576         int err;
2577         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2578         u32 txdctl, rxdctl, mhadd;
2579         u32 dmatxctl;
2580         u32 gpie;
2581
2582         ixgbe_get_hw_control(adapter);
2583
2584         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2585             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2586                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2587                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2588                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2589                 } else {
2590                         /* MSI only */
2591                         gpie = 0;
2592                 }
2593                 /* XXX: to interrupt immediately for EICS writes, enable this */
2594                 /* gpie |= IXGBE_GPIE_EIMEN; */
2595                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2596         }
2597
2598         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2599                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2600                  * specifically only auto mask tx and rx interrupts */
2601                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2602         }
2603
2604         /* Enable fan failure interrupt if media type is copper */
2605         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2606                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2607                 gpie |= IXGBE_SDP1_GPIEN;
2608                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2609         }
2610
2611         if (hw->mac.type == ixgbe_mac_82599EB) {
2612                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2613                 gpie |= IXGBE_SDP1_GPIEN;
2614                 gpie |= IXGBE_SDP2_GPIEN;
2615                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2616         }
2617
2618 #ifdef IXGBE_FCOE
2619         /* adjust max frame to be able to do baby jumbo for FCoE */
2620         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2621             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2622                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2623
2624 #endif /* IXGBE_FCOE */
2625         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2626         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2627                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2628                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2629
2630                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2631         }
2632
2633         for (i = 0; i < adapter->num_tx_queues; i++) {
2634                 j = adapter->tx_ring[i].reg_idx;
2635                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2636                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2637                 txdctl |= (8 << 16);
2638                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2639         }
2640
2641         if (hw->mac.type == ixgbe_mac_82599EB) {
2642                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2643                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2644                 dmatxctl |= IXGBE_DMATXCTL_TE;
2645                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2646         }
2647         for (i = 0; i < adapter->num_tx_queues; i++) {
2648                 j = adapter->tx_ring[i].reg_idx;
2649                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2650                 txdctl |= IXGBE_TXDCTL_ENABLE;
2651                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2652         }
2653
2654         for (i = 0; i < num_rx_rings; i++) {
2655                 j = adapter->rx_ring[i].reg_idx;
2656                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2657                 /* enable PTHRESH=32 descriptors (half the internal cache)
2658                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2659                  * this also removes a pesky rx_no_buffer_count increment */
2660                 rxdctl |= 0x0020;
2661                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2662                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2663                 if (hw->mac.type == ixgbe_mac_82599EB)
2664                         ixgbe_rx_desc_queue_enable(adapter, i);
2665         }
2666         /* enable all receives */
2667         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2668         if (hw->mac.type == ixgbe_mac_82598EB)
2669                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2670         else
2671                 rxdctl |= IXGBE_RXCTRL_RXEN;
2672         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2673
2674         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2675                 ixgbe_configure_msix(adapter);
2676         else
2677                 ixgbe_configure_msi_and_legacy(adapter);
2678
2679         clear_bit(__IXGBE_DOWN, &adapter->state);
2680         ixgbe_napi_enable_all(adapter);
2681
2682         /* clear any pending interrupts, may auto mask */
2683         IXGBE_READ_REG(hw, IXGBE_EICR);
2684
2685         ixgbe_irq_enable(adapter);
2686
2687         /*
2688          * If this adapter has a fan, check to see if we had a failure
2689          * before we enabled the interrupt.
2690          */
2691         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2692                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2693                 if (esdp & IXGBE_ESDP_SDP1)
2694                         DPRINTK(DRV, CRIT,
2695                                 "Fan has stopped, replace the adapter\n");
2696         }
2697
2698         /*
2699          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2700          * arrived before interrupts were enabled but after probe.  Such
2701          * devices wouldn't have their type identified yet. We need to
2702          * kick off the SFP+ module setup first, then try to bring up link.
2703          * If we're not hot-pluggable SFP+, we just need to configure link
2704          * and bring it up.
2705          */
2706         if (hw->phy.type == ixgbe_phy_unknown) {
2707                 err = hw->phy.ops.identify(hw);
2708                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2709                         /*
2710                          * Take the device down and schedule the sfp tasklet
2711                          * which will unregister_netdev and log it.
2712                          */
2713                         ixgbe_down(adapter);
2714                         schedule_work(&adapter->sfp_config_module_task);
2715                         return err;
2716                 }
2717         }
2718
2719         if (ixgbe_is_sfp(hw)) {
2720                 ixgbe_sfp_link_config(adapter);
2721         } else {
2722                 err = ixgbe_non_sfp_link_config(hw);
2723                 if (err)
2724                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2725         }
2726
2727         for (i = 0; i < adapter->num_tx_queues; i++)
2728                 set_bit(__IXGBE_FDIR_INIT_DONE,
2729                         &(adapter->tx_ring[i].reinit_state));
2730
2731         /* enable transmits */
2732         netif_tx_start_all_queues(netdev);
2733
2734         /* bring the link up in the watchdog, this could race with our first
2735          * link up interrupt but shouldn't be a problem */
2736         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2737         adapter->link_check_timeout = jiffies;
2738         mod_timer(&adapter->watchdog_timer, jiffies);
2739         return 0;
2740 }
2741
2742 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2743 {
2744         WARN_ON(in_interrupt());
2745         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2746                 msleep(1);
2747         ixgbe_down(adapter);
2748         ixgbe_up(adapter);
2749         clear_bit(__IXGBE_RESETTING, &adapter->state);
2750 }
2751
2752 int ixgbe_up(struct ixgbe_adapter *adapter)
2753 {
2754         /* hardware has been reset, we need to reload some things */
2755         ixgbe_configure(adapter);
2756
2757         return ixgbe_up_complete(adapter);
2758 }
2759
2760 void ixgbe_reset(struct ixgbe_adapter *adapter)
2761 {
2762         struct ixgbe_hw *hw = &adapter->hw;
2763         int err;
2764
2765         err = hw->mac.ops.init_hw(hw);
2766         switch (err) {
2767         case 0:
2768         case IXGBE_ERR_SFP_NOT_PRESENT:
2769                 break;
2770         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2771                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2772                 break;
2773         case IXGBE_ERR_EEPROM_VERSION:
2774                 /* We are running on a pre-production device, log a warning */
2775                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2776                          "adapter/LOM.  Please be aware there may be issues "
2777                          "associated with your hardware.  If you are "
2778                          "experiencing problems please contact your Intel or "
2779                          "hardware representative who provided you with this "
2780                          "hardware.\n");
2781                 break;
2782         default:
2783                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2784         }
2785
2786         /* reprogram the RAR[0] in case user changed it. */
2787         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2788 }
2789
2790 /**
2791  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2792  * @adapter: board private structure
2793  * @rx_ring: ring to free buffers from
2794  **/
2795 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2796                                 struct ixgbe_ring *rx_ring)
2797 {
2798         struct pci_dev *pdev = adapter->pdev;
2799         unsigned long size;
2800         unsigned int i;
2801
2802         /* Free all the Rx ring sk_buffs */
2803
2804         for (i = 0; i < rx_ring->count; i++) {
2805                 struct ixgbe_rx_buffer *rx_buffer_info;
2806
2807                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2808                 if (rx_buffer_info->dma) {
2809                         pci_unmap_single(pdev, rx_buffer_info->dma,
2810                                          rx_ring->rx_buf_len,
2811                                          PCI_DMA_FROMDEVICE);
2812                         rx_buffer_info->dma = 0;
2813                 }
2814                 if (rx_buffer_info->skb) {
2815                         struct sk_buff *skb = rx_buffer_info->skb;
2816                         rx_buffer_info->skb = NULL;
2817                         do {
2818                                 struct sk_buff *this = skb;
2819                                 skb = skb->prev;
2820                                 dev_kfree_skb(this);
2821                         } while (skb);
2822                 }
2823                 if (!rx_buffer_info->page)
2824                         continue;
2825                 if (rx_buffer_info->page_dma) {
2826                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2827                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2828                         rx_buffer_info->page_dma = 0;
2829                 }
2830                 put_page(rx_buffer_info->page);
2831                 rx_buffer_info->page = NULL;
2832                 rx_buffer_info->page_offset = 0;
2833         }
2834
2835         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2836         memset(rx_ring->rx_buffer_info, 0, size);
2837
2838         /* Zero out the descriptor ring */
2839         memset(rx_ring->desc, 0, rx_ring->size);
2840
2841         rx_ring->next_to_clean = 0;
2842         rx_ring->next_to_use = 0;
2843
2844         if (rx_ring->head)
2845                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2846         if (rx_ring->tail)
2847                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2848 }
2849
2850 /**
2851  * ixgbe_clean_tx_ring - Free Tx Buffers
2852  * @adapter: board private structure
2853  * @tx_ring: ring to be cleaned
2854  **/
2855 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2856                                 struct ixgbe_ring *tx_ring)
2857 {
2858         struct ixgbe_tx_buffer *tx_buffer_info;
2859         unsigned long size;
2860         unsigned int i;
2861
2862         /* Free all the Tx ring sk_buffs */
2863
2864         for (i = 0; i < tx_ring->count; i++) {
2865                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2866                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2867         }
2868
2869         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2870         memset(tx_ring->tx_buffer_info, 0, size);
2871
2872         /* Zero out the descriptor ring */
2873         memset(tx_ring->desc, 0, tx_ring->size);
2874
2875         tx_ring->next_to_use = 0;
2876         tx_ring->next_to_clean = 0;
2877
2878         if (tx_ring->head)
2879                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2880         if (tx_ring->tail)
2881                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2882 }
2883
2884 /**
2885  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2886  * @adapter: board private structure
2887  **/
2888 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2889 {
2890         int i;
2891
2892         for (i = 0; i < adapter->num_rx_queues; i++)
2893                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2894 }
2895
2896 /**
2897  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2898  * @adapter: board private structure
2899  **/
2900 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2901 {
2902         int i;
2903
2904         for (i = 0; i < adapter->num_tx_queues; i++)
2905                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2906 }
2907
2908 void ixgbe_down(struct ixgbe_adapter *adapter)
2909 {
2910         struct net_device *netdev = adapter->netdev;
2911         struct ixgbe_hw *hw = &adapter->hw;
2912         u32 rxctrl;
2913         u32 txdctl;
2914         int i, j;
2915
2916         /* signal that we are down to the interrupt handler */
2917         set_bit(__IXGBE_DOWN, &adapter->state);
2918
2919         /* disable receives */
2920         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2921         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2922
2923         netif_tx_disable(netdev);
2924
2925         IXGBE_WRITE_FLUSH(hw);
2926         msleep(10);
2927
2928         netif_tx_stop_all_queues(netdev);
2929
2930         ixgbe_irq_disable(adapter);
2931
2932         ixgbe_napi_disable_all(adapter);
2933
2934         del_timer_sync(&adapter->watchdog_timer);
2935         cancel_work_sync(&adapter->watchdog_task);
2936
2937         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2938             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2939                 cancel_work_sync(&adapter->fdir_reinit_task);
2940
2941         /* disable transmits in the hardware now that interrupts are off */
2942         for (i = 0; i < adapter->num_tx_queues; i++) {
2943                 j = adapter->tx_ring[i].reg_idx;
2944                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2945                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2946                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2947         }
2948         /* Disable the Tx DMA engine on 82599 */
2949         if (hw->mac.type == ixgbe_mac_82599EB)
2950                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2951                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2952                                  ~IXGBE_DMATXCTL_TE));
2953
2954         netif_carrier_off(netdev);
2955
2956         if (!pci_channel_offline(adapter->pdev))
2957                 ixgbe_reset(adapter);
2958         ixgbe_clean_all_tx_rings(adapter);
2959         ixgbe_clean_all_rx_rings(adapter);
2960
2961 #ifdef CONFIG_IXGBE_DCA
2962         /* since we reset the hardware DCA settings were cleared */
2963         ixgbe_setup_dca(adapter);
2964 #endif
2965 }
2966
2967 /**
2968  * ixgbe_poll - NAPI Rx polling callback
2969  * @napi: structure for representing this polling device
2970  * @budget: how many packets driver is allowed to clean
2971  *
2972  * This function is used for legacy and MSI, NAPI mode
2973  **/
2974 static int ixgbe_poll(struct napi_struct *napi, int budget)
2975 {
2976         struct ixgbe_q_vector *q_vector =
2977                                 container_of(napi, struct ixgbe_q_vector, napi);
2978         struct ixgbe_adapter *adapter = q_vector->adapter;
2979         int tx_clean_complete, work_done = 0;
2980
2981 #ifdef CONFIG_IXGBE_DCA
2982         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2983                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2984                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2985         }
2986 #endif
2987
2988         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2989         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2990
2991         if (!tx_clean_complete)
2992                 work_done = budget;
2993
2994         /* If budget not fully consumed, exit the polling mode */
2995         if (work_done < budget) {
2996                 napi_complete(napi);
2997                 if (adapter->itr_setting & 1)
2998                         ixgbe_set_itr(adapter);
2999                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3000                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3001         }
3002         return work_done;
3003 }
3004
3005 /**
3006  * ixgbe_tx_timeout - Respond to a Tx Hang
3007  * @netdev: network interface device structure
3008  **/
3009 static void ixgbe_tx_timeout(struct net_device *netdev)
3010 {
3011         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3012
3013         /* Do the reset outside of interrupt context */
3014         schedule_work(&adapter->reset_task);
3015 }
3016
3017 static void ixgbe_reset_task(struct work_struct *work)
3018 {
3019         struct ixgbe_adapter *adapter;
3020         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3021
3022         /* If we're already down or resetting, just bail */
3023         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3024             test_bit(__IXGBE_RESETTING, &adapter->state))
3025                 return;
3026
3027         adapter->tx_timeout_count++;
3028
3029         ixgbe_reinit_locked(adapter);
3030 }
3031
3032 #ifdef CONFIG_IXGBE_DCB
3033 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3034 {
3035         bool ret = false;
3036         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3037
3038         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3039                 return ret;
3040
3041         f->mask = 0x7 << 3;
3042         adapter->num_rx_queues = f->indices;
3043         adapter->num_tx_queues = f->indices;
3044         ret = true;
3045
3046         return ret;
3047 }
3048 #endif
3049
3050 /**
3051  * ixgbe_set_rss_queues: Allocate queues for RSS
3052  * @adapter: board private structure to initialize
3053  *
3054  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3055  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3056  *
3057  **/
3058 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3059 {
3060         bool ret = false;
3061         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3062
3063         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3064                 f->mask = 0xF;
3065                 adapter->num_rx_queues = f->indices;
3066                 adapter->num_tx_queues = f->indices;
3067                 ret = true;
3068         } else {
3069                 ret = false;
3070         }
3071
3072         return ret;
3073 }
3074
3075 /**
3076  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3077  * @adapter: board private structure to initialize
3078  *
3079  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3080  * to the original CPU that initiated the Tx session.  This runs in addition
3081  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3082  * Rx load across CPUs using RSS.
3083  *
3084  **/
3085 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3086 {
3087         bool ret = false;
3088         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3089
3090         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3091         f_fdir->mask = 0;
3092
3093         /* Flow Director must have RSS enabled */
3094         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3095             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3096              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3097                 adapter->num_tx_queues = f_fdir->indices;
3098                 adapter->num_rx_queues = f_fdir->indices;
3099                 ret = true;
3100         } else {
3101                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3102                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3103         }
3104         return ret;
3105 }
3106
3107 #ifdef IXGBE_FCOE
3108 /**
3109  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3110  * @adapter: board private structure to initialize
3111  *
3112  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3113  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3114  * rx queues out of the max number of rx queues, instead, it is used as the
3115  * index of the first rx queue used by FCoE.
3116  *
3117  **/
3118 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3119 {
3120         bool ret = false;
3121         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3122
3123         f->indices = min((int)num_online_cpus(), f->indices);
3124         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3125 #ifdef CONFIG_IXGBE_DCB
3126                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3127                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3128                         ixgbe_set_dcb_queues(adapter);
3129                 }
3130 #endif
3131                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3132                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3133                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3134                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3135                                 ixgbe_set_fdir_queues(adapter);
3136                         else
3137                                 ixgbe_set_rss_queues(adapter);
3138                 }
3139                 /* adding FCoE rx rings to the end */
3140                 f->mask = adapter->num_rx_queues;
3141                 adapter->num_rx_queues += f->indices;
3142                 if (adapter->num_tx_queues == 0)
3143                         adapter->num_tx_queues = f->indices;
3144
3145                 ret = true;
3146         }
3147
3148         return ret;
3149 }
3150
3151 #endif /* IXGBE_FCOE */
3152 /*
3153  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3154  * @adapter: board private structure to initialize
3155  *
3156  * This is the top level queue allocation routine.  The order here is very
3157  * important, starting with the "most" number of features turned on at once,
3158  * and ending with the smallest set of features.  This way large combinations
3159  * can be allocated if they're turned on, and smaller combinations are the
3160  * fallthrough conditions.
3161  *
3162  **/
3163 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3164 {
3165 #ifdef IXGBE_FCOE
3166         if (ixgbe_set_fcoe_queues(adapter))
3167                 goto done;
3168
3169 #endif /* IXGBE_FCOE */
3170 #ifdef CONFIG_IXGBE_DCB
3171         if (ixgbe_set_dcb_queues(adapter))
3172                 goto done;
3173
3174 #endif
3175         if (ixgbe_set_fdir_queues(adapter))
3176                 goto done;
3177
3178         if (ixgbe_set_rss_queues(adapter))
3179                 goto done;
3180
3181         /* fallback to base case */
3182         adapter->num_rx_queues = 1;
3183         adapter->num_tx_queues = 1;
3184
3185 done:
3186         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3187         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3188 }
3189
3190 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3191                                        int vectors)
3192 {
3193         int err, vector_threshold;
3194
3195         /* We'll want at least 3 (vector_threshold):
3196          * 1) TxQ[0] Cleanup
3197          * 2) RxQ[0] Cleanup
3198          * 3) Other (Link Status Change, etc.)
3199          * 4) TCP Timer (optional)
3200          */
3201         vector_threshold = MIN_MSIX_COUNT;
3202
3203         /* The more we get, the more we will assign to Tx/Rx Cleanup
3204          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3205          * Right now, we simply care about how many we'll get; we'll
3206          * set them up later while requesting irq's.
3207          */
3208         while (vectors >= vector_threshold) {
3209                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3210                                       vectors);
3211                 if (!err) /* Success in acquiring all requested vectors. */
3212                         break;
3213                 else if (err < 0)
3214                         vectors = 0; /* Nasty failure, quit now */
3215                 else /* err == number of vectors we should try again with */
3216                         vectors = err;
3217         }
3218
3219         if (vectors < vector_threshold) {
3220                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3221                  * This just means we'll go with either a single MSI
3222                  * vector or fall back to legacy interrupts.
3223                  */
3224                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3225                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3226                 kfree(adapter->msix_entries);
3227                 adapter->msix_entries = NULL;
3228         } else {
3229                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3230                 /*
3231                  * Adjust for only the vectors we'll use, which is minimum
3232                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3233                  * vectors we were allocated.
3234                  */
3235                 adapter->num_msix_vectors = min(vectors,
3236                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3237         }
3238 }
3239
3240 /**
3241  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3242  * @adapter: board private structure to initialize
3243  *
3244  * Cache the descriptor ring offsets for RSS to the assigned rings.
3245  *
3246  **/
3247 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3248 {
3249         int i;
3250         bool ret = false;
3251
3252         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3253                 for (i = 0; i < adapter->num_rx_queues; i++)
3254                         adapter->rx_ring[i].reg_idx = i;
3255                 for (i = 0; i < adapter->num_tx_queues; i++)
3256                         adapter->tx_ring[i].reg_idx = i;
3257                 ret = true;
3258         } else {
3259                 ret = false;
3260         }
3261
3262         return ret;
3263 }
3264
3265 #ifdef CONFIG_IXGBE_DCB
3266 /**
3267  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3268  * @adapter: board private structure to initialize
3269  *
3270  * Cache the descriptor ring offsets for DCB to the assigned rings.
3271  *
3272  **/
3273 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3274 {
3275         int i;
3276         bool ret = false;
3277         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3278
3279         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3280                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3281                         /* the number of queues is assumed to be symmetric */
3282                         for (i = 0; i < dcb_i; i++) {
3283                                 adapter->rx_ring[i].reg_idx = i << 3;
3284                                 adapter->tx_ring[i].reg_idx = i << 2;
3285                         }
3286                         ret = true;
3287                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3288                         if (dcb_i == 8) {
3289                                 /*
3290                                  * Tx TC0 starts at: descriptor queue 0
3291                                  * Tx TC1 starts at: descriptor queue 32
3292                                  * Tx TC2 starts at: descriptor queue 64
3293                                  * Tx TC3 starts at: descriptor queue 80
3294                                  * Tx TC4 starts at: descriptor queue 96
3295                                  * Tx TC5 starts at: descriptor queue 104
3296                                  * Tx TC6 starts at: descriptor queue 112
3297                                  * Tx TC7 starts at: descriptor queue 120
3298                                  *
3299                                  * Rx TC0-TC7 are offset by 16 queues each
3300                                  */
3301                                 for (i = 0; i < 3; i++) {
3302                                         adapter->tx_ring[i].reg_idx = i << 5;
3303                                         adapter->rx_ring[i].reg_idx = i << 4;
3304                                 }
3305                                 for ( ; i < 5; i++) {
3306                                         adapter->tx_ring[i].reg_idx =
3307                                                                  ((i + 2) << 4);
3308                                         adapter->rx_ring[i].reg_idx = i << 4;
3309                                 }
3310                                 for ( ; i < dcb_i; i++) {
3311                                         adapter->tx_ring[i].reg_idx =
3312                                                                  ((i + 8) << 3);
3313                                         adapter->rx_ring[i].reg_idx = i << 4;
3314                                 }
3315
3316                                 ret = true;
3317                         } else if (dcb_i == 4) {
3318                                 /*
3319                                  * Tx TC0 starts at: descriptor queue 0
3320                                  * Tx TC1 starts at: descriptor queue 64
3321                                  * Tx TC2 starts at: descriptor queue 96
3322                                  * Tx TC3 starts at: descriptor queue 112
3323                                  *
3324                                  * Rx TC0-TC3 are offset by 32 queues each
3325                                  */
3326                                 adapter->tx_ring[0].reg_idx = 0;
3327                                 adapter->tx_ring[1].reg_idx = 64;
3328                                 adapter->tx_ring[2].reg_idx = 96;
3329                                 adapter->tx_ring[3].reg_idx = 112;
3330                                 for (i = 0 ; i < dcb_i; i++)
3331                                         adapter->rx_ring[i].reg_idx = i << 5;
3332
3333                                 ret = true;
3334                         } else {
3335                                 ret = false;
3336                         }
3337                 } else {
3338                         ret = false;
3339                 }
3340         } else {
3341                 ret = false;
3342         }
3343
3344         return ret;
3345 }
3346 #endif
3347
3348 /**
3349  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3350  * @adapter: board private structure to initialize
3351  *
3352  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3353  *
3354  **/
3355 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3356 {
3357         int i;
3358         bool ret = false;
3359
3360         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3361             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3362              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3363                 for (i = 0; i < adapter->num_rx_queues; i++)
3364                         adapter->rx_ring[i].reg_idx = i;
3365                 for (i = 0; i < adapter->num_tx_queues; i++)
3366                         adapter->tx_ring[i].reg_idx = i;
3367                 ret = true;
3368         }
3369
3370         return ret;
3371 }
3372
3373 #ifdef IXGBE_FCOE
3374 /**
3375  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3376  * @adapter: board private structure to initialize
3377  *
3378  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3379  *
3380  */
3381 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3382 {
3383         int i, fcoe_i = 0;
3384         bool ret = false;
3385         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3386
3387         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3388 #ifdef CONFIG_IXGBE_DCB
3389                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3390                         ixgbe_cache_ring_dcb(adapter);
3391                         fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3392                 }
3393 #endif /* CONFIG_IXGBE_DCB */
3394                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3395                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3396                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3397                                 ixgbe_cache_ring_fdir(adapter);
3398                         else
3399                                 ixgbe_cache_ring_rss(adapter);
3400
3401                         fcoe_i = f->mask;
3402                 }
3403                 for (i = 0; i < f->indices; i++, fcoe_i++)
3404                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3405                 ret = true;
3406         }
3407         return ret;
3408 }
3409
3410 #endif /* IXGBE_FCOE */
3411 /**
3412  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3413  * @adapter: board private structure to initialize
3414  *
3415  * Once we know the feature-set enabled for the device, we'll cache
3416  * the register offset the descriptor ring is assigned to.
3417  *
3418  * Note, the order the various feature calls is important.  It must start with
3419  * the "most" features enabled at the same time, then trickle down to the
3420  * least amount of features turned on at once.
3421  **/
3422 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3423 {
3424         /* start with default case */
3425         adapter->rx_ring[0].reg_idx = 0;
3426         adapter->tx_ring[0].reg_idx = 0;
3427
3428 #ifdef IXGBE_FCOE
3429         if (ixgbe_cache_ring_fcoe(adapter))
3430                 return;
3431
3432 #endif /* IXGBE_FCOE */
3433 #ifdef CONFIG_IXGBE_DCB
3434         if (ixgbe_cache_ring_dcb(adapter))
3435                 return;
3436
3437 #endif
3438         if (ixgbe_cache_ring_fdir(adapter))
3439                 return;
3440
3441         if (ixgbe_cache_ring_rss(adapter))
3442                 return;
3443 }
3444
3445 /**
3446  * ixgbe_alloc_queues - Allocate memory for all rings
3447  * @adapter: board private structure to initialize
3448  *
3449  * We allocate one ring per queue at run-time since we don't know the
3450  * number of queues at compile-time.  The polling_netdev array is
3451  * intended for Multiqueue, but should work fine with a single queue.
3452  **/
3453 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3454 {
3455         int i;
3456
3457         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3458                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3459         if (!adapter->tx_ring)
3460                 goto err_tx_ring_allocation;
3461
3462         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3463                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3464         if (!adapter->rx_ring)
3465                 goto err_rx_ring_allocation;
3466
3467         for (i = 0; i < adapter->num_tx_queues; i++) {
3468                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3469                 adapter->tx_ring[i].queue_index = i;
3470         }
3471
3472         for (i = 0; i < adapter->num_rx_queues; i++) {
3473                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3474                 adapter->rx_ring[i].queue_index = i;
3475         }
3476
3477         ixgbe_cache_ring_register(adapter);
3478
3479         return 0;
3480
3481 err_rx_ring_allocation:
3482         kfree(adapter->tx_ring);
3483 err_tx_ring_allocation:
3484         return -ENOMEM;
3485 }
3486
3487 /**
3488  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3489  * @adapter: board private structure to initialize
3490  *
3491  * Attempt to configure the interrupts using the best available
3492  * capabilities of the hardware and the kernel.
3493  **/
3494 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3495 {
3496         struct ixgbe_hw *hw = &adapter->hw;
3497         int err = 0;
3498         int vector, v_budget;
3499
3500         /*
3501          * It's easy to be greedy for MSI-X vectors, but it really
3502          * doesn't do us much good if we have a lot more vectors
3503          * than CPU's.  So let's be conservative and only ask for
3504          * (roughly) twice the number of vectors as there are CPU's.
3505          */
3506         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3507                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3508
3509         /*
3510          * At the same time, hardware can only support a maximum of
3511          * hw.mac->max_msix_vectors vectors.  With features
3512          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3513          * descriptor queues supported by our device.  Thus, we cap it off in
3514          * those rare cases where the cpu count also exceeds our vector limit.
3515          */
3516         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3517
3518         /* A failure in MSI-X entry allocation isn't fatal, but it does
3519          * mean we disable MSI-X capabilities of the adapter. */
3520         adapter->msix_entries = kcalloc(v_budget,
3521                                         sizeof(struct msix_entry), GFP_KERNEL);
3522         if (adapter->msix_entries) {
3523                 for (vector = 0; vector < v_budget; vector++)
3524                         adapter->msix_entries[vector].entry = vector;
3525
3526                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3527
3528                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3529                         goto out;
3530         }
3531
3532         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3533         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3534         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3535         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3536         adapter->atr_sample_rate = 0;
3537         ixgbe_set_num_queues(adapter);
3538
3539         err = pci_enable_msi(adapter->pdev);
3540         if (!err) {
3541                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3542         } else {
3543                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3544                         "falling back to legacy.  Error: %d\n", err);
3545                 /* reset err */
3546                 err = 0;
3547         }
3548
3549 out:
3550         return err;
3551 }
3552
3553 /**
3554  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3555  * @adapter: board private structure to initialize
3556  *
3557  * We allocate one q_vector per queue interrupt.  If allocation fails we
3558  * return -ENOMEM.
3559  **/
3560 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3561 {
3562         int q_idx, num_q_vectors;
3563         struct ixgbe_q_vector *q_vector;
3564         int napi_vectors;
3565         int (*poll)(struct napi_struct *, int);
3566
3567         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3568                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3569                 napi_vectors = adapter->num_rx_queues;
3570                 poll = &ixgbe_clean_rxtx_many;
3571         } else {
3572                 num_q_vectors = 1;
3573                 napi_vectors = 1;
3574                 poll = &ixgbe_poll;
3575         }
3576
3577         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3578                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3579                 if (!q_vector)
3580                         goto err_out;
3581                 q_vector->adapter = adapter;
3582                 q_vector->eitr = adapter->eitr_param;
3583                 q_vector->v_idx = q_idx;
3584                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3585                 adapter->q_vector[q_idx] = q_vector;
3586         }
3587
3588         return 0;
3589
3590 err_out:
3591         while (q_idx) {
3592                 q_idx--;
3593                 q_vector = adapter->q_vector[q_idx];
3594                 netif_napi_del(&q_vector->napi);
3595                 kfree(q_vector);
3596                 adapter->q_vector[q_idx] = NULL;
3597         }
3598         return -ENOMEM;
3599 }
3600
3601 /**
3602  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3603  * @adapter: board private structure to initialize
3604  *
3605  * This function frees the memory allocated to the q_vectors.  In addition if
3606  * NAPI is enabled it will delete any references to the NAPI struct prior
3607  * to freeing the q_vector.
3608  **/
3609 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3610 {
3611         int q_idx, num_q_vectors;
3612
3613         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3614                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3615         else
3616                 num_q_vectors = 1;
3617
3618         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3619                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3620                 adapter->q_vector[q_idx] = NULL;
3621                 netif_napi_del(&q_vector->napi);
3622                 kfree(q_vector);
3623         }
3624 }
3625
3626 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3627 {
3628         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3629                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3630                 pci_disable_msix(adapter->pdev);
3631                 kfree(adapter->msix_entries);
3632                 adapter->msix_entries = NULL;
3633         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3634                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3635                 pci_disable_msi(adapter->pdev);
3636         }
3637         return;
3638 }
3639
3640 /**
3641  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3642  * @adapter: board private structure to initialize
3643  *
3644  * We determine which interrupt scheme to use based on...
3645  * - Kernel support (MSI, MSI-X)
3646  *   - which can be user-defined (via MODULE_PARAM)
3647  * - Hardware queue count (num_*_queues)
3648  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3649  **/
3650 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3651 {
3652         int err;
3653
3654         /* Number of supported queues */
3655         ixgbe_set_num_queues(adapter);
3656
3657         err = ixgbe_set_interrupt_capability(adapter);
3658         if (err) {
3659                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3660                 goto err_set_interrupt;
3661         }
3662
3663         err = ixgbe_alloc_q_vectors(adapter);
3664         if (err) {
3665                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3666                         "vectors\n");
3667                 goto err_alloc_q_vectors;
3668         }
3669
3670         err = ixgbe_alloc_queues(adapter);
3671         if (err) {
3672                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3673                 goto err_alloc_queues;
3674         }
3675
3676         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3677                 "Tx Queue count = %u\n",
3678                 (adapter->num_rx_queues > 1) ? "Enabled" :
3679                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3680
3681         set_bit(__IXGBE_DOWN, &adapter->state);
3682
3683         return 0;
3684
3685 err_alloc_queues:
3686         ixgbe_free_q_vectors(adapter);
3687 err_alloc_q_vectors:
3688         ixgbe_reset_interrupt_capability(adapter);
3689 err_set_interrupt:
3690         return err;
3691 }
3692
3693 /**
3694  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3695  * @adapter: board private structure to clear interrupt scheme on
3696  *
3697  * We go through and clear interrupt specific resources and reset the structure
3698  * to pre-load conditions
3699  **/
3700 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3701 {
3702         kfree(adapter->tx_ring);
3703         kfree(adapter->rx_ring);
3704         adapter->tx_ring = NULL;
3705         adapter->rx_ring = NULL;
3706
3707         ixgbe_free_q_vectors(adapter);
3708         ixgbe_reset_interrupt_capability(adapter);
3709 }
3710
3711 /**
3712  * ixgbe_sfp_timer - worker thread to find a missing module
3713  * @data: pointer to our adapter struct
3714  **/
3715 static void ixgbe_sfp_timer(unsigned long data)
3716 {
3717         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3718
3719         /*
3720          * Do the sfp_timer outside of interrupt context due to the
3721          * delays that sfp+ detection requires
3722          */
3723         schedule_work(&adapter->sfp_task);
3724 }
3725
3726 /**
3727  * ixgbe_sfp_task - worker thread to find a missing module
3728  * @work: pointer to work_struct containing our data
3729  **/
3730 static void ixgbe_sfp_task(struct work_struct *work)
3731 {
3732         struct ixgbe_adapter *adapter = container_of(work,
3733                                                      struct ixgbe_adapter,
3734                                                      sfp_task);
3735         struct ixgbe_hw *hw = &adapter->hw;
3736
3737         if ((hw->phy.type == ixgbe_phy_nl) &&
3738             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3739                 s32 ret = hw->phy.ops.identify_sfp(hw);
3740                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3741                         goto reschedule;
3742                 ret = hw->phy.ops.reset(hw);
3743                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3744                         dev_err(&adapter->pdev->dev, "failed to initialize "
3745                                 "because an unsupported SFP+ module type "
3746                                 "was detected.\n"
3747                                 "Reload the driver after installing a "
3748                                 "supported module.\n");
3749                         unregister_netdev(adapter->netdev);
3750                 } else {
3751                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3752                                 hw->phy.sfp_type);
3753                 }
3754                 /* don't need this routine any more */
3755                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3756         }
3757         return;
3758 reschedule:
3759         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3760                 mod_timer(&adapter->sfp_timer,
3761                           round_jiffies(jiffies + (2 * HZ)));
3762 }
3763
3764 /**
3765  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3766  * @adapter: board private structure to initialize
3767  *
3768  * ixgbe_sw_init initializes the Adapter private data structure.
3769  * Fields are initialized based on PCI device information and
3770  * OS network device settings (MTU size).
3771  **/
3772 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3773 {
3774         struct ixgbe_hw *hw = &adapter->hw;
3775         struct pci_dev *pdev = adapter->pdev;
3776         unsigned int rss;
3777 #ifdef CONFIG_IXGBE_DCB
3778         int j;
3779         struct tc_configuration *tc;
3780 #endif
3781
3782         /* PCI config space info */
3783
3784         hw->vendor_id = pdev->vendor;
3785         hw->device_id = pdev->device;
3786         hw->revision_id = pdev->revision;
3787         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3788         hw->subsystem_device_id = pdev->subsystem_device;
3789
3790         /* Set capability flags */
3791         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3792         adapter->ring_feature[RING_F_RSS].indices = rss;
3793         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3794         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3795         if (hw->mac.type == ixgbe_mac_82598EB) {
3796                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3797                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3798                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3799         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3800                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3801                 adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE;
3802                 adapter->flags |= IXGBE_FLAG2_RSC_ENABLED;
3803                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3804                 adapter->ring_feature[RING_F_FDIR].indices =
3805                                                          IXGBE_MAX_FDIR_INDICES;
3806                 adapter->atr_sample_rate = 20;
3807                 adapter->fdir_pballoc = 0;
3808 #ifdef IXGBE_FCOE
3809                 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
3810                 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
3811 #endif /* IXGBE_FCOE */
3812         }
3813
3814 #ifdef CONFIG_IXGBE_DCB
3815         /* Configure DCB traffic classes */
3816         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3817                 tc = &adapter->dcb_cfg.tc_config[j];
3818                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3819                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3820                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3821                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3822                 tc->dcb_pfc = pfc_disabled;
3823         }
3824         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3825         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3826         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3827         adapter->dcb_cfg.pfc_mode_enable = false;
3828         adapter->dcb_cfg.round_robin_enable = false;
3829         adapter->dcb_set_bitmap = 0x00;
3830         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3831                            adapter->ring_feature[RING_F_DCB].indices);
3832
3833 #endif
3834
3835         /* default flow control settings */
3836         hw->fc.requested_mode = ixgbe_fc_full;
3837         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3838 #ifdef CONFIG_DCB
3839         adapter->last_lfc_mode = hw->fc.current_mode;
3840 #endif
3841         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3842         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3843         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3844         hw->fc.send_xon = true;
3845         hw->fc.disable_fc_autoneg = false;
3846
3847         /* enable itr by default in dynamic mode */
3848         adapter->itr_setting = 1;
3849         adapter->eitr_param = 20000;
3850
3851         /* set defaults for eitr in MegaBytes */
3852         adapter->eitr_low = 10;
3853         adapter->eitr_high = 20;
3854
3855         /* set default ring sizes */
3856         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3857         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3858
3859         /* initialize eeprom parameters */
3860         if (ixgbe_init_eeprom_params_generic(hw)) {
3861                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3862                 return -EIO;
3863         }
3864
3865         /* enable rx csum by default */
3866         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3867
3868         set_bit(__IXGBE_DOWN, &adapter->state);
3869
3870         return 0;
3871 }
3872
3873 /**
3874  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3875  * @adapter: board private structure
3876  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3877  *
3878  * Return 0 on success, negative on failure
3879  **/
3880 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3881                              struct ixgbe_ring *tx_ring)
3882 {
3883         struct pci_dev *pdev = adapter->pdev;
3884         int size;
3885
3886         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3887         tx_ring->tx_buffer_info = vmalloc(size);
3888         if (!tx_ring->tx_buffer_info)
3889                 goto err;
3890         memset(tx_ring->tx_buffer_info, 0, size);
3891
3892         /* round up to nearest 4K */
3893         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3894         tx_ring->size = ALIGN(tx_ring->size, 4096);
3895
3896         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3897                                              &tx_ring->dma);
3898         if (!tx_ring->desc)
3899                 goto err;
3900
3901         tx_ring->next_to_use = 0;
3902         tx_ring->next_to_clean = 0;
3903         tx_ring->work_limit = tx_ring->count;
3904         return 0;
3905
3906 err:
3907         vfree(tx_ring->tx_buffer_info);
3908         tx_ring->tx_buffer_info = NULL;
3909         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3910                             "descriptor ring\n");
3911         return -ENOMEM;
3912 }
3913
3914 /**
3915  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3916  * @adapter: board private structure
3917  *
3918  * If this function returns with an error, then it's possible one or
3919  * more of the rings is populated (while the rest are not).  It is the
3920  * callers duty to clean those orphaned rings.
3921  *
3922  * Return 0 on success, negative on failure
3923  **/
3924 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3925 {
3926         int i, err = 0;
3927
3928         for (i = 0; i < adapter->num_tx_queues; i++) {
3929                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3930                 if (!err)
3931                         continue;
3932                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3933                 break;
3934         }
3935
3936         return err;
3937 }
3938
3939 /**
3940  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3941  * @adapter: board private structure
3942  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3943  *
3944  * Returns 0 on success, negative on failure
3945  **/
3946 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3947                              struct ixgbe_ring *rx_ring)
3948 {
3949         struct pci_dev *pdev = adapter->pdev;
3950         int size;
3951
3952         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3953         rx_ring->rx_buffer_info = vmalloc(size);
3954         if (!rx_ring->rx_buffer_info) {
3955                 DPRINTK(PROBE, ERR,
3956                         "vmalloc allocation failed for the rx desc ring\n");
3957                 goto alloc_failed;
3958         }
3959         memset(rx_ring->rx_buffer_info, 0, size);
3960
3961         /* Round up to nearest 4K */
3962         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3963         rx_ring->size = ALIGN(rx_ring->size, 4096);
3964
3965         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3966
3967         if (!rx_ring->desc) {
3968                 DPRINTK(PROBE, ERR,
3969                         "Memory allocation failed for the rx desc ring\n");
3970                 vfree(rx_ring->rx_buffer_info);
3971                 goto alloc_failed;
3972         }
3973
3974         rx_ring->next_to_clean = 0;
3975         rx_ring->next_to_use = 0;
3976
3977         return 0;
3978
3979 alloc_failed:
3980         return -ENOMEM;
3981 }
3982
3983 /**
3984  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3985  * @adapter: board private structure
3986  *
3987  * If this function returns with an error, then it's possible one or
3988  * more of the rings is populated (while the rest are not).  It is the
3989  * callers duty to clean those orphaned rings.
3990  *
3991  * Return 0 on success, negative on failure
3992  **/
3993
3994 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3995 {
3996         int i, err = 0;
3997
3998         for (i = 0; i < adapter->num_rx_queues; i++) {
3999                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4000                 if (!err)
4001                         continue;
4002                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4003                 break;
4004         }
4005
4006         return err;
4007 }
4008
4009 /**
4010  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4011  * @adapter: board private structure
4012  * @tx_ring: Tx descriptor ring for a specific queue
4013  *
4014  * Free all transmit software resources
4015  **/
4016 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4017                              struct ixgbe_ring *tx_ring)
4018 {
4019         struct pci_dev *pdev = adapter->pdev;
4020
4021         ixgbe_clean_tx_ring(adapter, tx_ring);
4022
4023         vfree(tx_ring->tx_buffer_info);
4024         tx_ring->tx_buffer_info = NULL;
4025
4026         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4027
4028         tx_ring->desc = NULL;
4029 }
4030
4031 /**
4032  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4033  * @adapter: board private structure
4034  *
4035  * Free all transmit software resources
4036  **/
4037 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4038 {
4039         int i;
4040
4041         for (i = 0; i < adapter->num_tx_queues; i++)
4042                 if (adapter->tx_ring[i].desc)
4043                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4044 }
4045
4046 /**
4047  * ixgbe_free_rx_resources - Free Rx Resources
4048  * @adapter: board private structure
4049  * @rx_ring: ring to clean the resources from
4050  *
4051  * Free all receive software resources
4052  **/
4053 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4054                              struct ixgbe_ring *rx_ring)
4055 {
4056         struct pci_dev *pdev = adapter->pdev;
4057
4058         ixgbe_clean_rx_ring(adapter, rx_ring);
4059
4060         vfree(rx_ring->rx_buffer_info);
4061         rx_ring->rx_buffer_info = NULL;
4062
4063         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4064
4065         rx_ring->desc = NULL;
4066 }
4067
4068 /**
4069  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4070  * @adapter: board private structure
4071  *
4072  * Free all receive software resources
4073  **/
4074 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4075 {
4076         int i;
4077
4078         for (i = 0; i < adapter->num_rx_queues; i++)
4079                 if (adapter->rx_ring[i].desc)
4080                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4081 }
4082
4083 /**
4084  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4085  * @netdev: network interface device structure
4086  * @new_mtu: new value for maximum frame size
4087  *
4088  * Returns 0 on success, negative on failure
4089  **/
4090 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4091 {
4092         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4093         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4094
4095         /* MTU < 68 is an error and causes problems on some kernels */
4096         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4097                 return -EINVAL;
4098
4099         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4100                 netdev->mtu, new_mtu);
4101         /* must set new MTU before calling down or up */
4102         netdev->mtu = new_mtu;
4103
4104         if (netif_running(netdev))
4105                 ixgbe_reinit_locked(adapter);
4106
4107         return 0;
4108 }
4109
4110 /**
4111  * ixgbe_open - Called when a network interface is made active
4112  * @netdev: network interface device structure
4113  *
4114  * Returns 0 on success, negative value on failure
4115  *
4116  * The open entry point is called when a network interface is made
4117  * active by the system (IFF_UP).  At this point all resources needed
4118  * for transmit and receive operations are allocated, the interrupt
4119  * handler is registered with the OS, the watchdog timer is started,
4120  * and the stack is notified that the interface is ready.
4121  **/
4122 static int ixgbe_open(struct net_device *netdev)
4123 {
4124         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4125         int err;
4126
4127         /* disallow open during test */
4128         if (test_bit(__IXGBE_TESTING, &adapter->state))
4129                 return -EBUSY;
4130
4131         netif_carrier_off(netdev);
4132
4133         /* allocate transmit descriptors */
4134         err = ixgbe_setup_all_tx_resources(adapter);
4135         if (err)
4136                 goto err_setup_tx;
4137
4138         /* allocate receive descriptors */
4139         err = ixgbe_setup_all_rx_resources(adapter);
4140         if (err)
4141                 goto err_setup_rx;
4142
4143         ixgbe_configure(adapter);
4144
4145         err = ixgbe_request_irq(adapter);
4146         if (err)
4147                 goto err_req_irq;
4148
4149         err = ixgbe_up_complete(adapter);
4150         if (err)
4151                 goto err_up;
4152
4153         netif_tx_start_all_queues(netdev);
4154
4155         return 0;
4156
4157 err_up:
4158         ixgbe_release_hw_control(adapter);
4159         ixgbe_free_irq(adapter);
4160 err_req_irq:
4161 err_setup_rx:
4162         ixgbe_free_all_rx_resources(adapter);
4163 err_setup_tx:
4164         ixgbe_free_all_tx_resources(adapter);
4165         ixgbe_reset(adapter);
4166
4167         return err;
4168 }
4169
4170 /**
4171  * ixgbe_close - Disables a network interface
4172  * @netdev: network interface device structure
4173  *
4174  * Returns 0, this is not allowed to fail
4175  *
4176  * The close entry point is called when an interface is de-activated
4177  * by the OS.  The hardware is still under the drivers control, but
4178  * needs to be disabled.  A global MAC reset is issued to stop the
4179  * hardware, and all transmit and receive resources are freed.
4180  **/
4181 static int ixgbe_close(struct net_device *netdev)
4182 {
4183         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4184
4185         ixgbe_down(adapter);
4186         ixgbe_free_irq(adapter);
4187
4188         ixgbe_free_all_tx_resources(adapter);
4189         ixgbe_free_all_rx_resources(adapter);
4190
4191         ixgbe_release_hw_control(adapter);
4192
4193         return 0;
4194 }
4195
4196 #ifdef CONFIG_PM
4197 static int ixgbe_resume(struct pci_dev *pdev)
4198 {
4199         struct net_device *netdev = pci_get_drvdata(pdev);
4200         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4201         u32 err;
4202
4203         pci_set_power_state(pdev, PCI_D0);
4204         pci_restore_state(pdev);
4205
4206         err = pci_enable_device_mem(pdev);
4207         if (err) {
4208                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4209                                 "suspend\n");
4210                 return err;
4211         }
4212         pci_set_master(pdev);
4213
4214         pci_wake_from_d3(pdev, false);
4215
4216         err = ixgbe_init_interrupt_scheme(adapter);
4217         if (err) {
4218                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4219                                 "device\n");
4220                 return err;
4221         }
4222
4223         ixgbe_reset(adapter);
4224
4225         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4226
4227         if (netif_running(netdev)) {
4228                 err = ixgbe_open(adapter->netdev);
4229                 if (err)
4230                         return err;
4231         }
4232
4233         netif_device_attach(netdev);
4234
4235         return 0;
4236 }
4237 #endif /* CONFIG_PM */
4238
4239 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4240 {
4241         struct net_device *netdev = pci_get_drvdata(pdev);
4242         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4243         struct ixgbe_hw *hw = &adapter->hw;
4244         u32 ctrl, fctrl;
4245         u32 wufc = adapter->wol;
4246 #ifdef CONFIG_PM
4247         int retval = 0;
4248 #endif
4249
4250         netif_device_detach(netdev);
4251
4252         if (netif_running(netdev)) {
4253                 ixgbe_down(adapter);
4254                 ixgbe_free_irq(adapter);
4255                 ixgbe_free_all_tx_resources(adapter);
4256                 ixgbe_free_all_rx_resources(adapter);
4257         }
4258         ixgbe_clear_interrupt_scheme(adapter);
4259
4260 #ifdef CONFIG_PM
4261         retval = pci_save_state(pdev);
4262         if (retval)
4263                 return retval;
4264
4265 #endif
4266         if (wufc) {
4267                 ixgbe_set_rx_mode(netdev);
4268
4269                 /* turn on all-multi mode if wake on multicast is enabled */
4270                 if (wufc & IXGBE_WUFC_MC) {
4271                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4272                         fctrl |= IXGBE_FCTRL_MPE;
4273                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4274                 }
4275
4276                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4277                 ctrl |= IXGBE_CTRL_GIO_DIS;
4278                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4279
4280                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4281         } else {
4282                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4283                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4284         }
4285
4286         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4287                 pci_wake_from_d3(pdev, true);
4288         else
4289                 pci_wake_from_d3(pdev, false);
4290
4291         *enable_wake = !!wufc;
4292
4293         ixgbe_release_hw_control(adapter);
4294
4295         pci_disable_device(pdev);
4296
4297         return 0;
4298 }
4299
4300 #ifdef CONFIG_PM
4301 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4302 {
4303         int retval;
4304         bool wake;
4305
4306         retval = __ixgbe_shutdown(pdev, &wake);
4307         if (retval)
4308                 return retval;
4309
4310         if (wake) {
4311                 pci_prepare_to_sleep(pdev);
4312         } else {
4313                 pci_wake_from_d3(pdev, false);
4314                 pci_set_power_state(pdev, PCI_D3hot);
4315         }
4316
4317         return 0;
4318 }
4319 #endif /* CONFIG_PM */
4320
4321 static void ixgbe_shutdown(struct pci_dev *pdev)
4322 {
4323         bool wake;
4324
4325         __ixgbe_shutdown(pdev, &wake);
4326
4327         if (system_state == SYSTEM_POWER_OFF) {
4328                 pci_wake_from_d3(pdev, wake);
4329                 pci_set_power_state(pdev, PCI_D3hot);
4330         }
4331 }
4332
4333 /**
4334  * ixgbe_update_stats - Update the board statistics counters.
4335  * @adapter: board private structure
4336  **/
4337 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4338 {
4339         struct ixgbe_hw *hw = &adapter->hw;
4340         u64 total_mpc = 0;
4341         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4342
4343         if (hw->mac.type == ixgbe_mac_82599EB) {
4344                 u64 rsc_count = 0;
4345                 for (i = 0; i < 16; i++)
4346                         adapter->hw_rx_no_dma_resources +=
4347                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4348                 for (i = 0; i < adapter->num_rx_queues; i++)
4349                         rsc_count += adapter->rx_ring[i].rsc_count;
4350                 adapter->rsc_count = rsc_count;
4351         }
4352
4353         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4354         for (i = 0; i < 8; i++) {
4355                 /* for packet buffers not used, the register should read 0 */
4356                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4357                 missed_rx += mpc;
4358                 adapter->stats.mpc[i] += mpc;
4359                 total_mpc += adapter->stats.mpc[i];
4360                 if (hw->mac.type == ixgbe_mac_82598EB)
4361                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4362                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4363                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4364                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4365                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4366                 if (hw->mac.type == ixgbe_mac_82599EB) {
4367                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4368                                                             IXGBE_PXONRXCNT(i));
4369                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4370                                                            IXGBE_PXOFFRXCNT(i));
4371                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4372                 } else {
4373                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4374                                                               IXGBE_PXONRXC(i));
4375                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4376                                                              IXGBE_PXOFFRXC(i));
4377                 }
4378                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4379                                                             IXGBE_PXONTXC(i));
4380                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4381                                                              IXGBE_PXOFFTXC(i));
4382         }
4383         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4384         /* work around hardware counting issue */
4385         adapter->stats.gprc -= missed_rx;
4386
4387         /* 82598 hardware only has a 32 bit counter in the high register */
4388         if (hw->mac.type == ixgbe_mac_82599EB) {
4389                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4390                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4391                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4392                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4393                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4394                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4395                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4396                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4397                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4398                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4399 #ifdef IXGBE_FCOE
4400                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4401                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4402                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4403                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4404                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4405                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4406 #endif /* IXGBE_FCOE */
4407         } else {
4408                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4409                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4410                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4411                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4412                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4413         }
4414         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4415         adapter->stats.bprc += bprc;
4416         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4417         if (hw->mac.type == ixgbe_mac_82598EB)
4418                 adapter->stats.mprc -= bprc;
4419         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4420         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4421         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4422         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4423         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4424         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4425         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4426         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4427         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4428         adapter->stats.lxontxc += lxon;
4429         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4430         adapter->stats.lxofftxc += lxoff;
4431         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4432         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4433         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4434         /*
4435          * 82598 errata - tx of flow control packets is included in tx counters
4436          */
4437         xon_off_tot = lxon + lxoff;
4438         adapter->stats.gptc -= xon_off_tot;
4439         adapter->stats.mptc -= xon_off_tot;
4440         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4441         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4442         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4443         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4444         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4445         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4446         adapter->stats.ptc64 -= xon_off_tot;
4447         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4448         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4449         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4450         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4451         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4452         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4453
4454         /* Fill out the OS statistics structure */
4455         adapter->net_stats.multicast = adapter->stats.mprc;
4456
4457         /* Rx Errors */
4458         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4459                                        adapter->stats.rlec;
4460         adapter->net_stats.rx_dropped = 0;
4461         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4462         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4463         adapter->net_stats.rx_missed_errors = total_mpc;
4464 }
4465
4466 /**
4467  * ixgbe_watchdog - Timer Call-back
4468  * @data: pointer to adapter cast into an unsigned long
4469  **/
4470 static void ixgbe_watchdog(unsigned long data)
4471 {
4472         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4473         struct ixgbe_hw *hw = &adapter->hw;
4474         u64 eics = 0;
4475         int i;
4476
4477         /*
4478          *  Do the watchdog outside of interrupt context due to the lovely
4479          * delays that some of the newer hardware requires
4480          */
4481
4482         if (test_bit(__IXGBE_DOWN, &adapter->state))
4483                 goto watchdog_short_circuit;
4484
4485         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4486                 /*
4487                  * for legacy and MSI interrupts don't set any bits
4488                  * that are enabled for EIAM, because this operation
4489                  * would set *both* EIMS and EICS for any bit in EIAM
4490                  */
4491                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4492                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4493                 goto watchdog_reschedule;
4494         }
4495
4496         /* get one bit for every active tx/rx interrupt vector */
4497         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4498                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4499                 if (qv->rxr_count || qv->txr_count)
4500                         eics |= ((u64)1 << i);
4501         }
4502
4503         /* Cause software interrupt to ensure rx rings are cleaned */
4504         ixgbe_irq_rearm_queues(adapter, eics);
4505
4506 watchdog_reschedule:
4507         /* Reset the timer */
4508         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4509
4510 watchdog_short_circuit:
4511         schedule_work(&adapter->watchdog_task);
4512 }
4513
4514 /**
4515  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4516  * @work: pointer to work_struct containing our data
4517  **/
4518 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4519 {
4520         struct ixgbe_adapter *adapter = container_of(work,
4521                                                      struct ixgbe_adapter,
4522                                                      multispeed_fiber_task);
4523         struct ixgbe_hw *hw = &adapter->hw;
4524         u32 autoneg;
4525
4526         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4527         autoneg = hw->phy.autoneg_advertised;
4528         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4529                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4530                                                   &hw->mac.autoneg);
4531         if (hw->mac.ops.setup_link_speed)
4532                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4533         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4534         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4535 }
4536
4537 /**
4538  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4539  * @work: pointer to work_struct containing our data
4540  **/
4541 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4542 {
4543         struct ixgbe_adapter *adapter = container_of(work,
4544                                                      struct ixgbe_adapter,
4545                                                      sfp_config_module_task);
4546         struct ixgbe_hw *hw = &adapter->hw;
4547         u32 err;
4548
4549         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4550
4551         /* Time for electrical oscillations to settle down */
4552         msleep(100);
4553         err = hw->phy.ops.identify_sfp(hw);
4554
4555         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4556                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4557                         "an unsupported SFP+ module type was detected.\n"
4558                         "Reload the driver after installing a supported "
4559                         "module.\n");
4560                 unregister_netdev(adapter->netdev);
4561                 return;
4562         }
4563         hw->mac.ops.setup_sfp(hw);
4564
4565         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4566                 /* This will also work for DA Twinax connections */
4567                 schedule_work(&adapter->multispeed_fiber_task);
4568         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4569 }
4570
4571 /**
4572  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4573  * @work: pointer to work_struct containing our data
4574  **/
4575 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4576 {
4577         struct ixgbe_adapter *adapter = container_of(work,
4578                                                      struct ixgbe_adapter,
4579                                                      fdir_reinit_task);
4580         struct ixgbe_hw *hw = &adapter->hw;
4581         int i;
4582
4583         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4584                 for (i = 0; i < adapter->num_tx_queues; i++)
4585                         set_bit(__IXGBE_FDIR_INIT_DONE,
4586                                 &(adapter->tx_ring[i].reinit_state));
4587         } else {
4588                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4589                         "ignored adding FDIR ATR filters \n");
4590         }
4591         /* Done FDIR Re-initialization, enable transmits */
4592         netif_tx_start_all_queues(adapter->netdev);
4593 }
4594
4595 /**
4596  * ixgbe_watchdog_task - worker thread to bring link up
4597  * @work: pointer to work_struct containing our data
4598  **/
4599 static void ixgbe_watchdog_task(struct work_struct *work)
4600 {
4601         struct ixgbe_adapter *adapter = container_of(work,
4602                                                      struct ixgbe_adapter,
4603                                                      watchdog_task);
4604         struct net_device *netdev = adapter->netdev;
4605         struct ixgbe_hw *hw = &adapter->hw;
4606         u32 link_speed = adapter->link_speed;
4607         bool link_up = adapter->link_up;
4608         int i;
4609         struct ixgbe_ring *tx_ring;
4610         int some_tx_pending = 0;
4611
4612         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4613
4614         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4615                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4616                 if (link_up) {
4617 #ifdef CONFIG_DCB
4618                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4619                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4620                                         hw->mac.ops.fc_enable(hw, i);
4621                         } else {
4622                                 hw->mac.ops.fc_enable(hw, 0);
4623                         }
4624 #else
4625                         hw->mac.ops.fc_enable(hw, 0);
4626 #endif
4627                 }
4628
4629                 if (link_up ||
4630                     time_after(jiffies, (adapter->link_check_timeout +
4631                                          IXGBE_TRY_LINK_TIMEOUT))) {
4632                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4633                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4634                 }
4635                 adapter->link_up = link_up;
4636                 adapter->link_speed = link_speed;
4637         }
4638
4639         if (link_up) {
4640                 if (!netif_carrier_ok(netdev)) {
4641                         bool flow_rx, flow_tx;
4642
4643                         if (hw->mac.type == ixgbe_mac_82599EB) {
4644                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4645                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4646                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4647                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4648                         } else {
4649                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4650                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4651                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4652                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4653                         }
4654
4655                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4656                                "Flow Control: %s\n",
4657                                netdev->name,
4658                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4659                                 "10 Gbps" :
4660                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4661                                  "1 Gbps" : "unknown speed")),
4662                                ((flow_rx && flow_tx) ? "RX/TX" :
4663                                 (flow_rx ? "RX" :
4664                                 (flow_tx ? "TX" : "None"))));
4665
4666                         netif_carrier_on(netdev);
4667                 } else {
4668                         /* Force detection of hung controller */
4669                         adapter->detect_tx_hung = true;
4670                 }
4671         } else {
4672                 adapter->link_up = false;
4673                 adapter->link_speed = 0;
4674                 if (netif_carrier_ok(netdev)) {
4675                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4676                                netdev->name);
4677                         netif_carrier_off(netdev);
4678                 }
4679         }
4680
4681         if (!netif_carrier_ok(netdev)) {
4682                 for (i = 0; i < adapter->num_tx_queues; i++) {
4683                         tx_ring = &adapter->tx_ring[i];
4684                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4685                                 some_tx_pending = 1;
4686                                 break;
4687                         }
4688                 }
4689
4690                 if (some_tx_pending) {
4691                         /* We've lost link, so the controller stops DMA,
4692                          * but we've got queued Tx work that's never going
4693                          * to get done, so reset controller to flush Tx.
4694                          * (Do the reset outside of interrupt context).
4695                          */
4696                          schedule_work(&adapter->reset_task);
4697                 }
4698         }
4699
4700         ixgbe_update_stats(adapter);
4701         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4702 }
4703
4704 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4705                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4706                      u32 tx_flags, u8 *hdr_len)
4707 {
4708         struct ixgbe_adv_tx_context_desc *context_desc;
4709         unsigned int i;
4710         int err;
4711         struct ixgbe_tx_buffer *tx_buffer_info;
4712         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4713         u32 mss_l4len_idx, l4len;
4714
4715         if (skb_is_gso(skb)) {
4716                 if (skb_header_cloned(skb)) {
4717                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4718                         if (err)
4719                                 return err;
4720                 }
4721                 l4len = tcp_hdrlen(skb);
4722                 *hdr_len += l4len;
4723
4724                 if (skb->protocol == htons(ETH_P_IP)) {
4725                         struct iphdr *iph = ip_hdr(skb);
4726                         iph->tot_len = 0;
4727                         iph->check = 0;
4728                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4729                                                                  iph->daddr, 0,
4730                                                                  IPPROTO_TCP,
4731                                                                  0);
4732                         adapter->hw_tso_ctxt++;
4733                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4734                         ipv6_hdr(skb)->payload_len = 0;
4735                         tcp_hdr(skb)->check =
4736                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4737                                              &ipv6_hdr(skb)->daddr,
4738                                              0, IPPROTO_TCP, 0);
4739                         adapter->hw_tso6_ctxt++;
4740                 }
4741
4742                 i = tx_ring->next_to_use;
4743
4744                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4745                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4746
4747                 /* VLAN MACLEN IPLEN */
4748                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4749                         vlan_macip_lens |=
4750                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4751                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4752                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4753                 *hdr_len += skb_network_offset(skb);
4754                 vlan_macip_lens |=
4755                     (skb_transport_header(skb) - skb_network_header(skb));
4756                 *hdr_len +=
4757                     (skb_transport_header(skb) - skb_network_header(skb));
4758                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4759                 context_desc->seqnum_seed = 0;
4760
4761                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4762                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4763                                    IXGBE_ADVTXD_DTYP_CTXT);
4764
4765                 if (skb->protocol == htons(ETH_P_IP))
4766                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4767                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4768                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4769
4770                 /* MSS L4LEN IDX */
4771                 mss_l4len_idx =
4772                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4773                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4774                 /* use index 1 for TSO */
4775                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4776                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4777
4778                 tx_buffer_info->time_stamp = jiffies;
4779                 tx_buffer_info->next_to_watch = i;
4780
4781                 i++;
4782                 if (i == tx_ring->count)
4783                         i = 0;
4784                 tx_ring->next_to_use = i;
4785
4786                 return true;
4787         }
4788         return false;
4789 }
4790
4791 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4792                           struct ixgbe_ring *tx_ring,
4793                           struct sk_buff *skb, u32 tx_flags)
4794 {
4795         struct ixgbe_adv_tx_context_desc *context_desc;
4796         unsigned int i;
4797         struct ixgbe_tx_buffer *tx_buffer_info;
4798         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4799
4800         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4801             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4802                 i = tx_ring->next_to_use;
4803                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4804                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4805
4806                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4807                         vlan_macip_lens |=
4808                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4809                 vlan_macip_lens |= (skb_network_offset(skb) <<
4810                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4811                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4812                         vlan_macip_lens |= (skb_transport_header(skb) -
4813                                             skb_network_header(skb));
4814
4815                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4816                 context_desc->seqnum_seed = 0;
4817
4818                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4819                                     IXGBE_ADVTXD_DTYP_CTXT);
4820
4821                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4822                         switch (skb->protocol) {
4823                         case cpu_to_be16(ETH_P_IP):
4824                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4825                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4826                                         type_tucmd_mlhl |=
4827                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4828                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4829                                         type_tucmd_mlhl |=
4830                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4831                                 break;
4832                         case cpu_to_be16(ETH_P_IPV6):
4833                                 /* XXX what about other V6 headers?? */
4834                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4835                                         type_tucmd_mlhl |=
4836                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4837                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4838                                         type_tucmd_mlhl |=
4839                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4840                                 break;
4841                         default:
4842                                 if (unlikely(net_ratelimit())) {
4843                                         DPRINTK(PROBE, WARNING,
4844                                          "partial checksum but proto=%x!\n",
4845                                          skb->protocol);
4846                                 }
4847                                 break;
4848                         }
4849                 }
4850
4851                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4852                 /* use index zero for tx checksum offload */
4853                 context_desc->mss_l4len_idx = 0;
4854
4855                 tx_buffer_info->time_stamp = jiffies;
4856                 tx_buffer_info->next_to_watch = i;
4857
4858                 adapter->hw_csum_tx_good++;
4859                 i++;
4860                 if (i == tx_ring->count)
4861                         i = 0;
4862                 tx_ring->next_to_use = i;
4863
4864                 return true;
4865         }
4866
4867         return false;
4868 }
4869
4870 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4871                         struct ixgbe_ring *tx_ring,
4872                         struct sk_buff *skb, u32 tx_flags,
4873                         unsigned int first)
4874 {
4875         struct ixgbe_tx_buffer *tx_buffer_info;
4876         unsigned int len;
4877         unsigned int total = skb->len;
4878         unsigned int offset = 0, size, count = 0, i;
4879         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4880         unsigned int f;
4881         dma_addr_t *map;
4882
4883         i = tx_ring->next_to_use;
4884
4885         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4886                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4887                 return 0;
4888         }
4889
4890         map = skb_shinfo(skb)->dma_maps;
4891
4892         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4893                 /* excluding fcoe_crc_eof for FCoE */
4894                 total -= sizeof(struct fcoe_crc_eof);
4895
4896         len = min(skb_headlen(skb), total);
4897         while (len) {
4898                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4899                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4900
4901                 tx_buffer_info->length = size;
4902                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4903                 tx_buffer_info->time_stamp = jiffies;
4904                 tx_buffer_info->next_to_watch = i;
4905
4906                 len -= size;
4907                 total -= size;
4908                 offset += size;
4909                 count++;
4910
4911                 if (len) {
4912                         i++;
4913                         if (i == tx_ring->count)
4914                                 i = 0;
4915                 }
4916         }
4917
4918         for (f = 0; f < nr_frags; f++) {
4919                 struct skb_frag_struct *frag;
4920
4921                 frag = &skb_shinfo(skb)->frags[f];
4922                 len = min((unsigned int)frag->size, total);
4923                 offset = 0;
4924
4925                 while (len) {
4926                         i++;
4927                         if (i == tx_ring->count)
4928                                 i = 0;
4929
4930                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4931                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4932
4933                         tx_buffer_info->length = size;
4934                         tx_buffer_info->dma = map[f] + offset;
4935                         tx_buffer_info->time_stamp = jiffies;
4936                         tx_buffer_info->next_to_watch = i;
4937
4938                         len -= size;
4939                         total -= size;
4940                         offset += size;
4941                         count++;
4942                 }
4943                 if (total == 0)
4944                         break;
4945         }
4946
4947         tx_ring->tx_buffer_info[i].skb = skb;
4948         tx_ring->tx_buffer_info[first].next_to_watch = i;
4949
4950         return count;
4951 }
4952
4953 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4954                            struct ixgbe_ring *tx_ring,
4955                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4956 {
4957         union ixgbe_adv_tx_desc *tx_desc = NULL;
4958         struct ixgbe_tx_buffer *tx_buffer_info;
4959         u32 olinfo_status = 0, cmd_type_len = 0;
4960         unsigned int i;
4961         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4962
4963         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4964
4965         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4966
4967         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4968                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4969
4970         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4971                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4972
4973                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4974                                  IXGBE_ADVTXD_POPTS_SHIFT;
4975
4976                 /* use index 1 context for tso */
4977                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4978                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4979                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4980                                          IXGBE_ADVTXD_POPTS_SHIFT;
4981
4982         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4983                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4984                                  IXGBE_ADVTXD_POPTS_SHIFT;
4985
4986         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4987                 olinfo_status |= IXGBE_ADVTXD_CC;
4988                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4989                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4990                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4991         }
4992
4993         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4994
4995         i = tx_ring->next_to_use;
4996         while (count--) {
4997                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4998                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4999                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5000                 tx_desc->read.cmd_type_len =
5001                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5002                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5003                 i++;
5004                 if (i == tx_ring->count)
5005                         i = 0;
5006         }
5007
5008         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5009
5010         /*
5011          * Force memory writes to complete before letting h/w
5012          * know there are new descriptors to fetch.  (Only
5013          * applicable for weak-ordered memory model archs,
5014          * such as IA-64).
5015          */
5016         wmb();
5017
5018         tx_ring->next_to_use = i;
5019         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5020 }
5021
5022 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5023                       int queue, u32 tx_flags)
5024 {
5025         /* Right now, we support IPv4 only */
5026         struct ixgbe_atr_input atr_input;
5027         struct tcphdr *th;
5028         struct udphdr *uh;
5029         struct iphdr *iph = ip_hdr(skb);
5030         struct ethhdr *eth = (struct ethhdr *)skb->data;
5031         u16 vlan_id, src_port, dst_port, flex_bytes;
5032         u32 src_ipv4_addr, dst_ipv4_addr;
5033         u8 l4type = 0;
5034
5035         /* check if we're UDP or TCP */
5036         if (iph->protocol == IPPROTO_TCP) {
5037                 th = tcp_hdr(skb);
5038                 src_port = th->source;
5039                 dst_port = th->dest;
5040                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5041                 /* l4type IPv4 type is 0, no need to assign */
5042         } else if(iph->protocol == IPPROTO_UDP) {
5043                 uh = udp_hdr(skb);
5044                 src_port = uh->source;
5045                 dst_port = uh->dest;
5046                 l4type |= IXGBE_ATR_L4TYPE_UDP;
5047                 /* l4type IPv4 type is 0, no need to assign */
5048         } else {
5049                 /* Unsupported L4 header, just bail here */
5050                 return;
5051         }
5052
5053         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5054
5055         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5056                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5057         src_ipv4_addr = iph->saddr;
5058         dst_ipv4_addr = iph->daddr;
5059         flex_bytes = eth->h_proto;
5060
5061         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5062         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5063         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5064         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5065         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5066         /* src and dst are inverted, think how the receiver sees them */
5067         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5068         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5069
5070         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5071         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5072 }
5073
5074 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5075                                  struct ixgbe_ring *tx_ring, int size)
5076 {
5077         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5078
5079         netif_stop_subqueue(netdev, tx_ring->queue_index);
5080         /* Herbert's original patch had:
5081          *  smp_mb__after_netif_stop_queue();
5082          * but since that doesn't exist yet, just open code it. */
5083         smp_mb();
5084
5085         /* We need to check again in a case another CPU has just
5086          * made room available. */
5087         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5088                 return -EBUSY;
5089
5090         /* A reprieve! - use start_queue because it doesn't call schedule */
5091         netif_start_subqueue(netdev, tx_ring->queue_index);
5092         ++adapter->restart_queue;
5093         return 0;
5094 }
5095
5096 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5097                               struct ixgbe_ring *tx_ring, int size)
5098 {
5099         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5100                 return 0;
5101         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5102 }
5103
5104 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5105 {
5106         struct ixgbe_adapter *adapter = netdev_priv(dev);
5107
5108         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5109                 return smp_processor_id();
5110
5111         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5112                 return 0;  /* All traffic should default to class 0 */
5113
5114         return skb_tx_hash(dev, skb);
5115 }
5116
5117 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5118 {
5119         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5120         struct ixgbe_ring *tx_ring;
5121         unsigned int first;
5122         unsigned int tx_flags = 0;
5123         u8 hdr_len = 0;
5124         int r_idx = 0, tso;
5125         int count = 0;
5126         unsigned int f;
5127
5128         r_idx = skb->queue_mapping;
5129         tx_ring = &adapter->tx_ring[r_idx];
5130
5131         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5132                 tx_flags |= vlan_tx_tag_get(skb);
5133                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5134                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5135                         tx_flags |= (skb->queue_mapping << 13);
5136                 }
5137                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5138                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5139         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5140                 tx_flags |= (skb->queue_mapping << 13);
5141                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5142                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5143         }
5144
5145         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5146             (skb->protocol == htons(ETH_P_FCOE)))
5147                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5148
5149         /* four things can cause us to need a context descriptor */
5150         if (skb_is_gso(skb) ||
5151             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5152             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5153             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5154                 count++;
5155
5156         count += TXD_USE_COUNT(skb_headlen(skb));
5157         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5158                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5159
5160         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5161                 adapter->tx_busy++;
5162                 return NETDEV_TX_BUSY;
5163         }
5164
5165         first = tx_ring->next_to_use;
5166         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5167 #ifdef IXGBE_FCOE
5168                 /* setup tx offload for FCoE */
5169                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5170                 if (tso < 0) {
5171                         dev_kfree_skb_any(skb);
5172                         return NETDEV_TX_OK;
5173                 }
5174                 if (tso)
5175                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5176 #endif /* IXGBE_FCOE */
5177         } else {
5178                 if (skb->protocol == htons(ETH_P_IP))
5179                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5180                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5181                 if (tso < 0) {
5182                         dev_kfree_skb_any(skb);
5183                         return NETDEV_TX_OK;
5184                 }
5185
5186                 if (tso)
5187                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5188                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5189                          (skb->ip_summed == CHECKSUM_PARTIAL))
5190                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5191         }
5192
5193         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5194         if (count) {
5195                 /* add the ATR filter if ATR is on */
5196                 if (tx_ring->atr_sample_rate) {
5197                         ++tx_ring->atr_count;
5198                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5199                              test_bit(__IXGBE_FDIR_INIT_DONE,
5200                                       &tx_ring->reinit_state)) {
5201                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5202                                           tx_flags);
5203                                 tx_ring->atr_count = 0;
5204                         }
5205                 }
5206                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5207                                hdr_len);
5208                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5209
5210         } else {
5211                 dev_kfree_skb_any(skb);
5212                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5213                 tx_ring->next_to_use = first;
5214         }
5215
5216         return NETDEV_TX_OK;
5217 }
5218
5219 /**
5220  * ixgbe_get_stats - Get System Network Statistics
5221  * @netdev: network interface device structure
5222  *
5223  * Returns the address of the device statistics structure.
5224  * The statistics are actually updated from the timer callback.
5225  **/
5226 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5227 {
5228         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5229
5230         /* only return the current stats */
5231         return &adapter->net_stats;
5232 }
5233
5234 /**
5235  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5236  * @netdev: network interface device structure
5237  * @p: pointer to an address structure
5238  *
5239  * Returns 0 on success, negative on failure
5240  **/
5241 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5242 {
5243         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5244         struct ixgbe_hw *hw = &adapter->hw;
5245         struct sockaddr *addr = p;
5246
5247         if (!is_valid_ether_addr(addr->sa_data))
5248                 return -EADDRNOTAVAIL;
5249
5250         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5251         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5252
5253         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5254
5255         return 0;
5256 }
5257
5258 static int
5259 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5260 {
5261         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5262         struct ixgbe_hw *hw = &adapter->hw;
5263         u16 value;
5264         int rc;
5265
5266         if (prtad != hw->phy.mdio.prtad)
5267                 return -EINVAL;
5268         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5269         if (!rc)
5270                 rc = value;
5271         return rc;
5272 }
5273
5274 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5275                             u16 addr, u16 value)
5276 {
5277         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5278         struct ixgbe_hw *hw = &adapter->hw;
5279
5280         if (prtad != hw->phy.mdio.prtad)
5281                 return -EINVAL;
5282         return hw->phy.ops.write_reg(hw, addr, devad, value);
5283 }
5284
5285 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5286 {
5287         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5288
5289         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5290 }
5291
5292 /**
5293  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5294  * netdev->dev_addrs
5295  * @netdev: network interface device structure
5296  *
5297  * Returns non-zero on failure
5298  **/
5299 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5300 {
5301         int err = 0;
5302         struct ixgbe_adapter *adapter = netdev_priv(dev);
5303         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5304
5305         if (is_valid_ether_addr(mac->san_addr)) {
5306                 rtnl_lock();
5307                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5308                 rtnl_unlock();
5309         }
5310         return err;
5311 }
5312
5313 /**
5314  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5315  * netdev->dev_addrs
5316  * @netdev: network interface device structure
5317  *
5318  * Returns non-zero on failure
5319  **/
5320 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5321 {
5322         int err = 0;
5323         struct ixgbe_adapter *adapter = netdev_priv(dev);
5324         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5325
5326         if (is_valid_ether_addr(mac->san_addr)) {
5327                 rtnl_lock();
5328                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5329                 rtnl_unlock();
5330         }
5331         return err;
5332 }
5333
5334 #ifdef CONFIG_NET_POLL_CONTROLLER
5335 /*
5336  * Polling 'interrupt' - used by things like netconsole to send skbs
5337  * without having to re-enable interrupts. It's not called while
5338  * the interrupt routine is executing.
5339  */
5340 static void ixgbe_netpoll(struct net_device *netdev)
5341 {
5342         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5343
5344         disable_irq(adapter->pdev->irq);
5345         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5346         ixgbe_intr(adapter->pdev->irq, netdev);
5347         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5348         enable_irq(adapter->pdev->irq);
5349 }
5350 #endif
5351
5352 static const struct net_device_ops ixgbe_netdev_ops = {
5353         .ndo_open               = ixgbe_open,
5354         .ndo_stop               = ixgbe_close,
5355         .ndo_start_xmit         = ixgbe_xmit_frame,
5356         .ndo_select_queue       = ixgbe_select_queue,
5357         .ndo_get_stats          = ixgbe_get_stats,
5358         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5359         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5360         .ndo_validate_addr      = eth_validate_addr,
5361         .ndo_set_mac_address    = ixgbe_set_mac,
5362         .ndo_change_mtu         = ixgbe_change_mtu,
5363         .ndo_tx_timeout         = ixgbe_tx_timeout,
5364         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5365         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5366         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5367         .ndo_do_ioctl           = ixgbe_ioctl,
5368 #ifdef CONFIG_NET_POLL_CONTROLLER
5369         .ndo_poll_controller    = ixgbe_netpoll,
5370 #endif
5371 #ifdef IXGBE_FCOE
5372         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5373         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5374 #endif /* IXGBE_FCOE */
5375 };
5376
5377 /**
5378  * ixgbe_probe - Device Initialization Routine
5379  * @pdev: PCI device information struct
5380  * @ent: entry in ixgbe_pci_tbl
5381  *
5382  * Returns 0 on success, negative on failure
5383  *
5384  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5385  * The OS initialization, configuring of the adapter private structure,
5386  * and a hardware reset occur.
5387  **/
5388 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5389                                  const struct pci_device_id *ent)
5390 {
5391         struct net_device *netdev;
5392         struct ixgbe_adapter *adapter = NULL;
5393         struct ixgbe_hw *hw;
5394         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5395         static int cards_found;
5396         int i, err, pci_using_dac;
5397 #ifdef IXGBE_FCOE
5398         u16 device_caps;
5399 #endif
5400         u32 part_num, eec;
5401
5402         err = pci_enable_device_mem(pdev);
5403         if (err)
5404                 return err;
5405
5406         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5407             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5408                 pci_using_dac = 1;
5409         } else {
5410                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5411                 if (err) {
5412                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5413                         if (err) {
5414                                 dev_err(&pdev->dev, "No usable DMA "
5415                                         "configuration, aborting\n");
5416                                 goto err_dma;
5417                         }
5418                 }
5419                 pci_using_dac = 0;
5420         }
5421
5422         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5423                                            IORESOURCE_MEM), ixgbe_driver_name);
5424         if (err) {
5425                 dev_err(&pdev->dev,
5426                         "pci_request_selected_regions failed 0x%x\n", err);
5427                 goto err_pci_reg;
5428         }
5429
5430         err = pci_enable_pcie_error_reporting(pdev);
5431         if (err) {
5432                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5433                                     "0x%x\n", err);
5434                 /* non-fatal, continue */
5435         }
5436
5437         pci_set_master(pdev);
5438         pci_save_state(pdev);
5439
5440         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5441         if (!netdev) {
5442                 err = -ENOMEM;
5443                 goto err_alloc_etherdev;
5444         }
5445
5446         SET_NETDEV_DEV(netdev, &pdev->dev);
5447
5448         pci_set_drvdata(pdev, netdev);
5449         adapter = netdev_priv(netdev);
5450
5451         adapter->netdev = netdev;
5452         adapter->pdev = pdev;
5453         hw = &adapter->hw;
5454         hw->back = adapter;
5455         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5456
5457         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5458                               pci_resource_len(pdev, 0));
5459         if (!hw->hw_addr) {
5460                 err = -EIO;
5461                 goto err_ioremap;
5462         }
5463
5464         for (i = 1; i <= 5; i++) {
5465                 if (pci_resource_len(pdev, i) == 0)
5466                         continue;
5467         }
5468
5469         netdev->netdev_ops = &ixgbe_netdev_ops;
5470         ixgbe_set_ethtool_ops(netdev);
5471         netdev->watchdog_timeo = 5 * HZ;
5472         strcpy(netdev->name, pci_name(pdev));
5473
5474         adapter->bd_number = cards_found;
5475
5476         /* Setup hw api */
5477         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5478         hw->mac.type  = ii->mac;
5479
5480         /* EEPROM */
5481         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5482         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5483         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5484         if (!(eec & (1 << 8)))
5485                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5486
5487         /* PHY */
5488         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5489         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5490         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5491         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5492         hw->phy.mdio.mmds = 0;
5493         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5494         hw->phy.mdio.dev = netdev;
5495         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5496         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5497
5498         /* set up this timer and work struct before calling get_invariants
5499          * which might start the timer
5500          */
5501         init_timer(&adapter->sfp_timer);
5502         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5503         adapter->sfp_timer.data = (unsigned long) adapter;
5504
5505         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5506
5507         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5508         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5509
5510         /* a new SFP+ module arrival, called from GPI SDP2 context */
5511         INIT_WORK(&adapter->sfp_config_module_task,
5512                   ixgbe_sfp_config_module_task);
5513
5514         ii->get_invariants(hw);
5515
5516         /* setup the private structure */
5517         err = ixgbe_sw_init(adapter);
5518         if (err)
5519                 goto err_sw_init;
5520
5521         /*
5522          * If there is a fan on this device and it has failed log the
5523          * failure.
5524          */
5525         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5526                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5527                 if (esdp & IXGBE_ESDP_SDP1)
5528                         DPRINTK(PROBE, CRIT,
5529                                 "Fan has stopped, replace the adapter\n");
5530         }
5531
5532         /* reset_hw fills in the perm_addr as well */
5533         err = hw->mac.ops.reset_hw(hw);
5534         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5535             hw->mac.type == ixgbe_mac_82598EB) {
5536                 /*
5537                  * Start a kernel thread to watch for a module to arrive.
5538                  * Only do this for 82598, since 82599 will generate
5539                  * interrupts on module arrival.
5540                  */
5541                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5542                 mod_timer(&adapter->sfp_timer,
5543                           round_jiffies(jiffies + (2 * HZ)));
5544                 err = 0;
5545         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5546                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5547                         "an unsupported SFP+ module type was detected.\n"
5548                         "Reload the driver after installing a supported "
5549                         "module.\n");
5550                 goto err_sw_init;
5551         } else if (err) {
5552                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5553                 goto err_sw_init;
5554         }
5555
5556         netdev->features = NETIF_F_SG |
5557                            NETIF_F_IP_CSUM |
5558                            NETIF_F_HW_VLAN_TX |
5559                            NETIF_F_HW_VLAN_RX |
5560                            NETIF_F_HW_VLAN_FILTER;
5561
5562         netdev->features |= NETIF_F_IPV6_CSUM;
5563         netdev->features |= NETIF_F_TSO;
5564         netdev->features |= NETIF_F_TSO6;
5565         netdev->features |= NETIF_F_GRO;
5566
5567         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5568                 netdev->features |= NETIF_F_SCTP_CSUM;
5569
5570         netdev->vlan_features |= NETIF_F_TSO;
5571         netdev->vlan_features |= NETIF_F_TSO6;
5572         netdev->vlan_features |= NETIF_F_IP_CSUM;
5573         netdev->vlan_features |= NETIF_F_SG;
5574
5575         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5576                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5577
5578 #ifdef CONFIG_IXGBE_DCB
5579         netdev->dcbnl_ops = &dcbnl_ops;
5580 #endif
5581
5582 #ifdef IXGBE_FCOE
5583         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5584                 if (hw->mac.ops.get_device_caps) {
5585                         hw->mac.ops.get_device_caps(hw, &device_caps);
5586                         if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5587                                 netdev->features |= NETIF_F_FCOE_CRC;
5588                                 netdev->features |= NETIF_F_FSO;
5589                                 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
5590                         } else {
5591                                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5592                         }
5593                 }
5594         }
5595 #endif /* IXGBE_FCOE */
5596         if (pci_using_dac)
5597                 netdev->features |= NETIF_F_HIGHDMA;
5598
5599         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED)
5600                 netdev->features |= NETIF_F_LRO;
5601
5602         /* make sure the EEPROM is good */
5603         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5604                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5605                 err = -EIO;
5606                 goto err_eeprom;
5607         }
5608
5609         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5610         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5611
5612         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5613                 dev_err(&pdev->dev, "invalid MAC address\n");
5614                 err = -EIO;
5615                 goto err_eeprom;
5616         }
5617
5618         init_timer(&adapter->watchdog_timer);
5619         adapter->watchdog_timer.function = &ixgbe_watchdog;
5620         adapter->watchdog_timer.data = (unsigned long)adapter;
5621
5622         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5623         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5624
5625         err = ixgbe_init_interrupt_scheme(adapter);
5626         if (err)
5627                 goto err_sw_init;
5628
5629         switch (pdev->device) {
5630         case IXGBE_DEV_ID_82599_KX4:
5631                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5632                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5633                 /* Enable ACPI wakeup in GRC */
5634                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5635                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5636                 break;
5637         default:
5638                 adapter->wol = 0;
5639                 break;
5640         }
5641         device_init_wakeup(&adapter->pdev->dev, true);
5642         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5643
5644         /* pick up the PCI bus settings for reporting later */
5645         hw->mac.ops.get_bus_info(hw);
5646
5647         /* print bus type/speed/width info */
5648         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5649                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5650                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5651                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5652                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5653                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5654                  "Unknown"),
5655                 netdev->dev_addr);
5656         ixgbe_read_pba_num_generic(hw, &part_num);
5657         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5658                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5659                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5660                          (part_num >> 8), (part_num & 0xff));
5661         else
5662                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5663                          hw->mac.type, hw->phy.type,
5664                          (part_num >> 8), (part_num & 0xff));
5665
5666         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5667                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5668                          "this card is not sufficient for optimal "
5669                          "performance.\n");
5670                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5671                          "PCI-Express slot is required.\n");
5672         }
5673
5674         /* save off EEPROM version number */
5675         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5676
5677         /* reset the hardware with the new settings */
5678         err = hw->mac.ops.start_hw(hw);
5679
5680         if (err == IXGBE_ERR_EEPROM_VERSION) {
5681                 /* We are running on a pre-production device, log a warning */
5682                 dev_warn(&pdev->dev, "This device is a pre-production "
5683                          "adapter/LOM.  Please be aware there may be issues "
5684                          "associated with your hardware.  If you are "
5685                          "experiencing problems please contact your Intel or "
5686                          "hardware representative who provided you with this "
5687                          "hardware.\n");
5688         }
5689         strcpy(netdev->name, "eth%d");
5690         err = register_netdev(netdev);
5691         if (err)
5692                 goto err_register;
5693
5694         /* carrier off reporting is important to ethtool even BEFORE open */
5695         netif_carrier_off(netdev);
5696
5697         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5698             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5699                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5700
5701 #ifdef CONFIG_IXGBE_DCA
5702         if (dca_add_requester(&pdev->dev) == 0) {
5703                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5704                 ixgbe_setup_dca(adapter);
5705         }
5706 #endif
5707         /* add san mac addr to netdev */
5708         ixgbe_add_sanmac_netdev(netdev);
5709
5710         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5711         cards_found++;
5712         return 0;
5713
5714 err_register:
5715         ixgbe_release_hw_control(adapter);
5716         ixgbe_clear_interrupt_scheme(adapter);
5717 err_sw_init:
5718 err_eeprom:
5719         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5720         del_timer_sync(&adapter->sfp_timer);
5721         cancel_work_sync(&adapter->sfp_task);
5722         cancel_work_sync(&adapter->multispeed_fiber_task);
5723         cancel_work_sync(&adapter->sfp_config_module_task);
5724         iounmap(hw->hw_addr);
5725 err_ioremap:
5726         free_netdev(netdev);
5727 err_alloc_etherdev:
5728         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5729                                      IORESOURCE_MEM));
5730 err_pci_reg:
5731 err_dma:
5732         pci_disable_device(pdev);
5733         return err;
5734 }
5735
5736 /**
5737  * ixgbe_remove - Device Removal Routine
5738  * @pdev: PCI device information struct
5739  *
5740  * ixgbe_remove is called by the PCI subsystem to alert the driver
5741  * that it should release a PCI device.  The could be caused by a
5742  * Hot-Plug event, or because the driver is going to be removed from
5743  * memory.
5744  **/
5745 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5746 {
5747         struct net_device *netdev = pci_get_drvdata(pdev);
5748         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5749         int err;
5750
5751         set_bit(__IXGBE_DOWN, &adapter->state);
5752         /* clear the module not found bit to make sure the worker won't
5753          * reschedule
5754          */
5755         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5756         del_timer_sync(&adapter->watchdog_timer);
5757
5758         del_timer_sync(&adapter->sfp_timer);
5759         cancel_work_sync(&adapter->watchdog_task);
5760         cancel_work_sync(&adapter->sfp_task);
5761         cancel_work_sync(&adapter->multispeed_fiber_task);
5762         cancel_work_sync(&adapter->sfp_config_module_task);
5763         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5764             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5765                 cancel_work_sync(&adapter->fdir_reinit_task);
5766         flush_scheduled_work();
5767
5768 #ifdef CONFIG_IXGBE_DCA
5769         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5770                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5771                 dca_remove_requester(&pdev->dev);
5772                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5773         }
5774
5775 #endif
5776 #ifdef IXGBE_FCOE
5777         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5778                 ixgbe_cleanup_fcoe(adapter);
5779
5780 #endif /* IXGBE_FCOE */
5781
5782         /* remove the added san mac */
5783         ixgbe_del_sanmac_netdev(netdev);
5784
5785         if (netdev->reg_state == NETREG_REGISTERED)
5786                 unregister_netdev(netdev);
5787
5788         ixgbe_clear_interrupt_scheme(adapter);
5789
5790         ixgbe_release_hw_control(adapter);
5791
5792         iounmap(adapter->hw.hw_addr);
5793         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5794                                      IORESOURCE_MEM));
5795
5796         DPRINTK(PROBE, INFO, "complete\n");
5797
5798         free_netdev(netdev);
5799
5800         err = pci_disable_pcie_error_reporting(pdev);
5801         if (err)
5802                 dev_err(&pdev->dev,
5803                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5804
5805         pci_disable_device(pdev);
5806 }
5807
5808 /**
5809  * ixgbe_io_error_detected - called when PCI error is detected
5810  * @pdev: Pointer to PCI device
5811  * @state: The current pci connection state
5812  *
5813  * This function is called after a PCI bus error affecting
5814  * this device has been detected.
5815  */
5816 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5817                                                 pci_channel_state_t state)
5818 {
5819         struct net_device *netdev = pci_get_drvdata(pdev);
5820         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5821
5822         netif_device_detach(netdev);
5823
5824         if (state == pci_channel_io_perm_failure)
5825                 return PCI_ERS_RESULT_DISCONNECT;
5826
5827         if (netif_running(netdev))
5828                 ixgbe_down(adapter);
5829         pci_disable_device(pdev);
5830
5831         /* Request a slot reset. */
5832         return PCI_ERS_RESULT_NEED_RESET;
5833 }
5834
5835 /**
5836  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5837  * @pdev: Pointer to PCI device
5838  *
5839  * Restart the card from scratch, as if from a cold-boot.
5840  */
5841 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5842 {
5843         struct net_device *netdev = pci_get_drvdata(pdev);
5844         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5845         pci_ers_result_t result;
5846         int err;
5847
5848         if (pci_enable_device_mem(pdev)) {
5849                 DPRINTK(PROBE, ERR,
5850                         "Cannot re-enable PCI device after reset.\n");
5851                 result = PCI_ERS_RESULT_DISCONNECT;
5852         } else {
5853                 pci_set_master(pdev);
5854                 pci_restore_state(pdev);
5855
5856                 pci_wake_from_d3(pdev, false);
5857
5858                 ixgbe_reset(adapter);
5859                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5860                 result = PCI_ERS_RESULT_RECOVERED;
5861         }
5862
5863         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5864         if (err) {
5865                 dev_err(&pdev->dev,
5866                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5867                 /* non-fatal, continue */
5868         }
5869
5870         return result;
5871 }
5872
5873 /**
5874  * ixgbe_io_resume - called when traffic can start flowing again.
5875  * @pdev: Pointer to PCI device
5876  *
5877  * This callback is called when the error recovery driver tells us that
5878  * its OK to resume normal operation.
5879  */
5880 static void ixgbe_io_resume(struct pci_dev *pdev)
5881 {
5882         struct net_device *netdev = pci_get_drvdata(pdev);
5883         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5884
5885         if (netif_running(netdev)) {
5886                 if (ixgbe_up(adapter)) {
5887                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5888                         return;
5889                 }
5890         }
5891
5892         netif_device_attach(netdev);
5893 }
5894
5895 static struct pci_error_handlers ixgbe_err_handler = {
5896         .error_detected = ixgbe_io_error_detected,
5897         .slot_reset = ixgbe_io_slot_reset,
5898         .resume = ixgbe_io_resume,
5899 };
5900
5901 static struct pci_driver ixgbe_driver = {
5902         .name     = ixgbe_driver_name,
5903         .id_table = ixgbe_pci_tbl,
5904         .probe    = ixgbe_probe,
5905         .remove   = __devexit_p(ixgbe_remove),
5906 #ifdef CONFIG_PM
5907         .suspend  = ixgbe_suspend,
5908         .resume   = ixgbe_resume,
5909 #endif
5910         .shutdown = ixgbe_shutdown,
5911         .err_handler = &ixgbe_err_handler
5912 };
5913
5914 /**
5915  * ixgbe_init_module - Driver Registration Routine
5916  *
5917  * ixgbe_init_module is the first routine called when the driver is
5918  * loaded. All it does is register with the PCI subsystem.
5919  **/
5920 static int __init ixgbe_init_module(void)
5921 {
5922         int ret;
5923         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5924                ixgbe_driver_string, ixgbe_driver_version);
5925
5926         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5927
5928 #ifdef CONFIG_IXGBE_DCA
5929         dca_register_notify(&dca_notifier);
5930 #endif
5931
5932         ret = pci_register_driver(&ixgbe_driver);
5933         return ret;
5934 }
5935
5936 module_init(ixgbe_init_module);
5937
5938 /**
5939  * ixgbe_exit_module - Driver Exit Cleanup Routine
5940  *
5941  * ixgbe_exit_module is called just before the driver is removed
5942  * from memory.
5943  **/
5944 static void __exit ixgbe_exit_module(void)
5945 {
5946 #ifdef CONFIG_IXGBE_DCA
5947         dca_unregister_notify(&dca_notifier);
5948 #endif
5949         pci_unregister_driver(&ixgbe_driver);
5950 }
5951
5952 #ifdef CONFIG_IXGBE_DCA
5953 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5954                             void *p)
5955 {
5956         int ret_val;
5957
5958         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5959                                          __ixgbe_notify_dca);
5960
5961         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5962 }
5963
5964 #endif /* CONFIG_IXGBE_DCA */
5965 #ifdef DEBUG
5966 /**
5967  * ixgbe_get_hw_dev_name - return device name string
5968  * used by hardware layer to print debugging information
5969  **/
5970 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5971 {
5972         struct ixgbe_adapter *adapter = hw->back;
5973         return adapter->netdev->name;
5974 }
5975
5976 #endif
5977 module_exit(ixgbe_exit_module);
5978
5979 /* ixgbe_main.c */