drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47 #include "ixgbe_dcb_82599.h"
  48
  49 char ixgbe_driver_name[] = "ixgbe";
  50 static const char ixgbe_driver_string[] =
  51                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  52
  53 #define DRV_VERSION "2.0.44-k2"
  54 const char ixgbe_driver_version[] = DRV_VERSION;
  55 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  56
  57 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  58         [board_82598] = &ixgbe_82598_info,
  59         [board_82599] = &ixgbe_82599_info,
  60 };
  61
  62 /* ixgbe_pci_tbl - PCI Device ID Table
  63  *
  64  * Wildcard entries (PCI_ANY_ID) should come last
  65  * Last entry must be all 0s
  66  *
  67  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  68  *   Class, Class Mask, private data (not used) }
  69  */
  70 static struct pci_device_id ixgbe_pci_tbl[] = {
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 108          board_82599 },
 109
 110         /* required last entry */
 111         {0, }
 112 };
 113 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 114
 115 #ifdef CONFIG_IXGBE_DCA
 116 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 117                             void *p);
 118 static struct notifier_block dca_notifier = {
 119         .notifier_call = ixgbe_notify_dca,
 120         .next          = NULL,
 121         .priority      = 0
 122 };
 123 #endif
 124
 125 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 126 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 127 MODULE_LICENSE("GPL");
 128 MODULE_VERSION(DRV_VERSION);
 129
 130 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 131
 132 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 133 {
 134         u32 ctrl_ext;
 135
 136         /* Let firmware take over control of h/w */
 137         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 138         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 139                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 140 }
 141
 142 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 143 {
 144         u32 ctrl_ext;
 145
 146         /* Let firmware know the driver has taken over */
 147         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 148         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 149                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 150 }
 151
 152 /*
 153  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 154  * @adapter: pointer to adapter struct
 155  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 156  * @queue: queue to map the corresponding interrupt to
 157  * @msix_vector: the vector to map to the corresponding queue
 158  *
 159  */
 160 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 161                            u8 queue, u8 msix_vector)
 162 {
 163         u32 ivar, index;
 164         struct ixgbe_hw *hw = &adapter->hw;
 165         switch (hw->mac.type) {
 166         case ixgbe_mac_82598EB:
 167                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 168                 if (direction == -1)
 169                         direction = 0;
 170                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 171                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 172                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 173                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 174                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 175                 break;
 176         case ixgbe_mac_82599EB:
 177                 if (direction == -1) {
 178                         /* other causes */
 179                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 180                         index = ((queue & 1) * 8);
 181                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 182                         ivar &= ~(0xFF << index);
 183                         ivar |= (msix_vector << index);
 184                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 185                         break;
 186                 } else {
 187                         /* tx or rx causes */
 188                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 189                         index = ((16 * (queue & 1)) + (8 * direction));
 190                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 191                         ivar &= ~(0xFF << index);
 192                         ivar |= (msix_vector << index);
 193                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 194                         break;
 195                 }
 196         default:
 197                 break;
 198         }
 199 }
 200
 201 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 202                                           u64 qmask)
 203 {
 204         u32 mask;
 205
 206         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 207                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 208                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 209         } else {
 210                 mask = (qmask & 0xFFFFFFFF);
 211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 212                 mask = (qmask >> 32);
 213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 214         }
 215 }
 216
 217 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 218                                              struct ixgbe_tx_buffer
 219                                              *tx_buffer_info)
 220 {
 221         if (tx_buffer_info->dma) {
 222                 if (tx_buffer_info->mapped_as_page)
 223                         pci_unmap_page(adapter->pdev,
 224                                        tx_buffer_info->dma,
 225                                        tx_buffer_info->length,
 226                                        PCI_DMA_TODEVICE);
 227                 else
 228                         pci_unmap_single(adapter->pdev,
 229                                          tx_buffer_info->dma,
 230                                          tx_buffer_info->length,
 231                                          PCI_DMA_TODEVICE);
 232                 tx_buffer_info->dma = 0;
 233         }
 234         if (tx_buffer_info->skb) {
 235                 dev_kfree_skb_any(tx_buffer_info->skb);
 236                 tx_buffer_info->skb = NULL;
 237         }
 238         tx_buffer_info->time_stamp = 0;
 239         /* tx_buffer_info must be completely set up in the transmit path */
 240 }
 241
 242 /**
 243  * ixgbe_tx_is_paused - check if the tx ring is paused
 244  * @adapter: the ixgbe adapter
 245  * @tx_ring: the corresponding tx_ring
 246  *
 247  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 248  * corresponding TC of this tx_ring when checking TFCS.
 249  *
 250  * Returns : true if paused
 251  */
 252 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter *adapter,
 253                                       struct ixgbe_ring *tx_ring)
 254 {
 255         u32 txoff = IXGBE_TFCS_TXOFF;
 256
 257 #ifdef CONFIG_IXGBE_DCB
 258         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 259                 int tc;
 260                 int reg_idx = tx_ring->reg_idx;
 261                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 262
 263                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 264                         tc = reg_idx >> 2;
 265                         txoff = IXGBE_TFCS_TXOFF0;
 266                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 267                         tc = 0;
 268                         txoff = IXGBE_TFCS_TXOFF;
 269                         if (dcb_i == 8) {
 270                                 /* TC0, TC1 */
 271                                 tc = reg_idx >> 5;
 272                                 if (tc == 2) /* TC2, TC3 */
 273                                         tc += (reg_idx - 64) >> 4;
 274                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 275                                         tc += 1 + ((reg_idx - 96) >> 3);
 276                         } else if (dcb_i == 4) {
 277                                 /* TC0, TC1 */
 278                                 tc = reg_idx >> 6;
 279                                 if (tc == 1) {
 280                                         tc += (reg_idx - 64) >> 5;
 281                                         if (tc == 2) /* TC2, TC3 */
 282                                                 tc += (reg_idx - 96) >> 4;
 283                                 }
 284                         }
 285                 }
 286                 txoff <<= tc;
 287         }
 288 #endif
 289         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 290 }
 291
 292 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 293                                        struct ixgbe_ring *tx_ring,
 294                                        unsigned int eop)
 295 {
 296         struct ixgbe_hw *hw = &adapter->hw;
 297
 298         /* Detect a transmit hang in hardware, this serializes the
 299          * check with the clearing of time_stamp and movement of eop */
 300         adapter->detect_tx_hung = false;
 301         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 302             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 303             !ixgbe_tx_is_paused(adapter, tx_ring)) {
 304                 /* detected Tx unit hang */
 305                 union ixgbe_adv_tx_desc *tx_desc;
 306                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 307                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 308                         "  Tx Queue             <%d>\n"
 309                         "  TDH, TDT             <%x>, <%x>\n"
 310                         "  next_to_use          <%x>\n"
 311                         "  next_to_clean        <%x>\n"
 312                         "tx_buffer_info[next_to_clean]\n"
 313                         "  time_stamp           <%lx>\n"
 314                         "  jiffies              <%lx>\n",
 315                         tx_ring->queue_index,
 316                         IXGBE_READ_REG(hw, tx_ring->head),
 317                         IXGBE_READ_REG(hw, tx_ring->tail),
 318                         tx_ring->next_to_use, eop,
 319                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 320                 return true;
 321         }
 322
 323         return false;
 324 }
 325
 326 #define IXGBE_MAX_TXD_PWR       14
 327 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 328
 329 /* Tx Descriptors needed, worst case */
 330 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 331                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 332 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 333         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 334
 335 static void ixgbe_tx_timeout(struct net_device *netdev);
 336
 337 /**
 338  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 339  * @q_vector: structure containing interrupt and ring information
 340  * @tx_ring: tx ring to clean
 341  **/
 342 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 343                                struct ixgbe_ring *tx_ring)
 344 {
 345         struct ixgbe_adapter *adapter = q_vector->adapter;
 346         struct net_device *netdev = adapter->netdev;
 347         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 348         struct ixgbe_tx_buffer *tx_buffer_info;
 349         unsigned int i, eop, count = 0;
 350         unsigned int total_bytes = 0, total_packets = 0;
 351
 352         i = tx_ring->next_to_clean;
 353         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 354         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 355
 356         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 357                (count < tx_ring->work_limit)) {
 358                 bool cleaned = false;
 359                 for ( ; !cleaned; count++) {
 360                         struct sk_buff *skb;
 361                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 362                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 363                         cleaned = (i == eop);
 364                         skb = tx_buffer_info->skb;
 365
 366                         if (cleaned && skb) {
 367                                 unsigned int segs, bytecount;
 368                                 unsigned int hlen = skb_headlen(skb);
 369
 370                                 /* gso_segs is currently only valid for tcp */
 371                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 372 #ifdef IXGBE_FCOE
 373                                 /* adjust for FCoE Sequence Offload */
 374                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 375                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 376                                     skb_is_gso(skb)) {
 377                                         hlen = skb_transport_offset(skb) +
 378                                                 sizeof(struct fc_frame_header) +
 379                                                 sizeof(struct fcoe_crc_eof);
 380                                         segs = DIV_ROUND_UP(skb->len - hlen,
 381                                                 skb_shinfo(skb)->gso_size);
 382                                 }
 383 #endif /* IXGBE_FCOE */
 384                                 /* multiply data chunks by size of headers */
 385                                 bytecount = ((segs - 1) * hlen) + skb->len;
 386                                 total_packets += segs;
 387                                 total_bytes += bytecount;
 388                         }
 389
 390                         ixgbe_unmap_and_free_tx_resource(adapter,
 391                                                          tx_buffer_info);
 392
 393                         tx_desc->wb.status = 0;
 394
 395                         i++;
 396                         if (i == tx_ring->count)
 397                                 i = 0;
 398                 }
 399
 400                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 401                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 402         }
 403
 404         tx_ring->next_to_clean = i;
 405
 406 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 407         if (unlikely(count && netif_carrier_ok(netdev) &&
 408                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 409                 /* Make sure that anybody stopping the queue after this
 410                  * sees the new next_to_clean.
 411                  */
 412                 smp_mb();
 413                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 414                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 415                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 416                         ++adapter->restart_queue;
 417                 }
 418         }
 419
 420         if (adapter->detect_tx_hung) {
 421                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 422                         /* schedule immediate reset if we believe we hung */
 423                         DPRINTK(PROBE, INFO,
 424                                 "tx hang %d detected, resetting adapter\n",
 425                                 adapter->tx_timeout_count + 1);
 426                         ixgbe_tx_timeout(adapter->netdev);
 427                 }
 428         }
 429
 430         /* re-arm the interrupt */
 431         if (count >= tx_ring->work_limit)
 432                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 433
 434         tx_ring->total_bytes += total_bytes;
 435         tx_ring->total_packets += total_packets;
 436         tx_ring->stats.packets += total_packets;
 437         tx_ring->stats.bytes += total_bytes;
 438         netdev->stats.tx_bytes += total_bytes;
 439         netdev->stats.tx_packets += total_packets;
 440         return (count < tx_ring->work_limit);
 441 }
 442
 443 #ifdef CONFIG_IXGBE_DCA
 444 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 445                                 struct ixgbe_ring *rx_ring)
 446 {
 447         u32 rxctrl;
 448         int cpu = get_cpu();
 449         int q = rx_ring - adapter->rx_ring;
 450
 451         if (rx_ring->cpu != cpu) {
 452                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 453                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 454                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 455                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 456                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 457                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 458                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 459                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 460                 }
 461                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 462                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 463                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 464                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 465                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 466                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 467                 rx_ring->cpu = cpu;
 468         }
 469         put_cpu();
 470 }
 471
 472 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 473                                 struct ixgbe_ring *tx_ring)
 474 {
 475         u32 txctrl;
 476         int cpu = get_cpu();
 477         int q = tx_ring - adapter->tx_ring;
 478         struct ixgbe_hw *hw = &adapter->hw;
 479
 480         if (tx_ring->cpu != cpu) {
 481                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 482                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 483                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 484                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 485                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 486                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 487                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 488                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 489                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 490                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 491                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 492                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 493                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 494                 }
 495                 tx_ring->cpu = cpu;
 496         }
 497         put_cpu();
 498 }
 499
 500 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 501 {
 502         int i;
 503
 504         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 505                 return;
 506
 507         /* always use CB2 mode, difference is masked in the CB driver */
 508         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 509
 510         for (i = 0; i < adapter->num_tx_queues; i++) {
 511                 adapter->tx_ring[i].cpu = -1;
 512                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 513         }
 514         for (i = 0; i < adapter->num_rx_queues; i++) {
 515                 adapter->rx_ring[i].cpu = -1;
 516                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 517         }
 518 }
 519
 520 static int __ixgbe_notify_dca(struct device *dev, void *data)
 521 {
 522         struct net_device *netdev = dev_get_drvdata(dev);
 523         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 524         unsigned long event = *(unsigned long *)data;
 525
 526         switch (event) {
 527         case DCA_PROVIDER_ADD:
 528                 /* if we're already enabled, don't do it again */
 529                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 530                         break;
 531                 if (dca_add_requester(dev) == 0) {
 532                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 533                         ixgbe_setup_dca(adapter);
 534                         break;
 535                 }
 536                 /* Fall Through since DCA is disabled. */
 537         case DCA_PROVIDER_REMOVE:
 538                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 539                         dca_remove_requester(dev);
 540                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 541                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 542                 }
 543                 break;
 544         }
 545
 546         return 0;
 547 }
 548
 549 #endif /* CONFIG_IXGBE_DCA */
 550 /**
 551  * ixgbe_receive_skb - Send a completed packet up the stack
 552  * @adapter: board private structure
 553  * @skb: packet to send up
 554  * @status: hardware indication of status of receive
 555  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 556  * @rx_desc: rx descriptor
 557  **/
 558 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 559                               struct sk_buff *skb, u8 status,
 560                               struct ixgbe_ring *ring,
 561                               union ixgbe_adv_rx_desc *rx_desc)
 562 {
 563         struct ixgbe_adapter *adapter = q_vector->adapter;
 564         struct napi_struct *napi = &q_vector->napi;
 565         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 566         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 567
 568         skb_record_rx_queue(skb, ring->queue_index);
 569         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 570                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 571                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 572                 else
 573                         napi_gro_receive(napi, skb);
 574         } else {
 575                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 576                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 577                 else
 578                         netif_rx(skb);
 579         }
 580 }
 581
 582 /**
 583  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 584  * @adapter: address of board private structure
 585  * @status_err: hardware indication of status of receive
 586  * @skb: skb currently being received and modified
 587  **/
 588 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 589                                      union ixgbe_adv_rx_desc *rx_desc,
 590                                      struct sk_buff *skb)
 591 {
 592         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 593
 594         skb->ip_summed = CHECKSUM_NONE;
 595
 596         /* Rx csum disabled */
 597         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 598                 return;
 599
 600         /* if IP and error */
 601         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 602             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 603                 adapter->hw_csum_rx_error++;
 604                 return;
 605         }
 606
 607         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 608                 return;
 609
 610         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 611                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 612
 613                 /*
 614                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 615                  * checksum errors.
 616                  */
 617                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 618                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 619                         return;
 620
 621                 adapter->hw_csum_rx_error++;
 622                 return;
 623         }
 624
 625         /* It must be a TCP or UDP packet with a valid checksum */
 626         skb->ip_summed = CHECKSUM_UNNECESSARY;
 627         adapter->hw_csum_rx_good++;
 628 }
 629
 630 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 631                                          struct ixgbe_ring *rx_ring, u32 val)
 632 {
 633         /*
 634          * Force memory writes to complete before letting h/w
 635          * know there are new descriptors to fetch.  (Only
 636          * applicable for weak-ordered memory model archs,
 637          * such as IA-64).
 638          */
 639         wmb();
 640         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 641 }
 642
 643 /**
 644  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 645  * @adapter: address of board private structure
 646  **/
 647 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 648                                    struct ixgbe_ring *rx_ring,
 649                                    int cleaned_count)
 650 {
 651         struct pci_dev *pdev = adapter->pdev;
 652         union ixgbe_adv_rx_desc *rx_desc;
 653         struct ixgbe_rx_buffer *bi;
 654         unsigned int i;
 655
 656         i = rx_ring->next_to_use;
 657         bi = &rx_ring->rx_buffer_info[i];
 658
 659         while (cleaned_count--) {
 660                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 661
 662                 if (!bi->page_dma &&
 663                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 664                         if (!bi->page) {
 665                                 bi->page = alloc_page(GFP_ATOMIC);
 666                                 if (!bi->page) {
 667                                         adapter->alloc_rx_page_failed++;
 668                                         goto no_buffers;
 669                                 }
 670                                 bi->page_offset = 0;
 671                         } else {
 672                                 /* use a half page if we're re-using */
 673                                 bi->page_offset ^= (PAGE_SIZE / 2);
 674                         }
 675
 676                         bi->page_dma = pci_map_page(pdev, bi->page,
 677                                                     bi->page_offset,
 678                                                     (PAGE_SIZE / 2),
 679                                                     PCI_DMA_FROMDEVICE);
 680                 }
 681
 682                 if (!bi->skb) {
 683                         struct sk_buff *skb;
 684                         skb = netdev_alloc_skb_ip_align(adapter->netdev,
 685                                                         rx_ring->rx_buf_len);
 686
 687                         if (!skb) {
 688                                 adapter->alloc_rx_buff_failed++;
 689                                 goto no_buffers;
 690                         }
 691
 692                         bi->skb = skb;
 693                         bi->dma = pci_map_single(pdev, skb->data,
 694                                                  rx_ring->rx_buf_len,
 695                                                  PCI_DMA_FROMDEVICE);
 696                 }
 697                 /* Refresh the desc even if buffer_addrs didn't change because
 698                  * each write-back erases this info. */
 699                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 700                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 701                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 702                 } else {
 703                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 704                 }
 705
 706                 i++;
 707                 if (i == rx_ring->count)
 708                         i = 0;
 709                 bi = &rx_ring->rx_buffer_info[i];
 710         }
 711
 712 no_buffers:
 713         if (rx_ring->next_to_use != i) {
 714                 rx_ring->next_to_use = i;
 715                 if (i-- == 0)
 716                         i = (rx_ring->count - 1);
 717
 718                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 719         }
 720 }
 721
 722 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 723 {
 724         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 725 }
 726
 727 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 728 {
 729         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 730 }
 731
 732 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 733 {
 734         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 735                 IXGBE_RXDADV_RSCCNT_MASK) >>
 736                 IXGBE_RXDADV_RSCCNT_SHIFT;
 737 }
 738
 739 /**
 740  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 741  * @skb: pointer to the last skb in the rsc queue
 742  * @count: pointer to number of packets coalesced in this context
 743  *
 744  * This function changes a queue full of hw rsc buffers into a completed
 745  * packet.  It uses the ->prev pointers to find the first packet and then
 746  * turns it into the frag list owner.
 747  **/
 748 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
 749                                                         u64 *count)
 750 {
 751         unsigned int frag_list_size = 0;
 752
 753         while (skb->prev) {
 754                 struct sk_buff *prev = skb->prev;
 755                 frag_list_size += skb->len;
 756                 skb->prev = NULL;
 757                 skb = prev;
 758                 *count += 1;
 759         }
 760
 761         skb_shinfo(skb)->frag_list = skb->next;
 762         skb->next = NULL;
 763         skb->len += frag_list_size;
 764         skb->data_len += frag_list_size;
 765         skb->truesize += frag_list_size;
 766         return skb;
 767 }
 768
 769 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 770                                struct ixgbe_ring *rx_ring,
 771                                int *work_done, int work_to_do)
 772 {
 773         struct ixgbe_adapter *adapter = q_vector->adapter;
 774         struct net_device *netdev = adapter->netdev;
 775         struct pci_dev *pdev = adapter->pdev;
 776         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 777         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 778         struct sk_buff *skb;
 779         unsigned int i, rsc_count = 0;
 780         u32 len, staterr;
 781         u16 hdr_info;
 782         bool cleaned = false;
 783         int cleaned_count = 0;
 784         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 785 #ifdef IXGBE_FCOE
 786         int ddp_bytes = 0;
 787 #endif /* IXGBE_FCOE */
 788
 789         i = rx_ring->next_to_clean;
 790         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 791         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 792         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 793
 794         while (staterr & IXGBE_RXD_STAT_DD) {
 795                 u32 upper_len = 0;
 796                 if (*work_done >= work_to_do)
 797                         break;
 798                 (*work_done)++;
 799
 800                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 801                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 802                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 803                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 804                         if (hdr_info & IXGBE_RXDADV_SPH)
 805                                 adapter->rx_hdr_split++;
 806                         if (len > IXGBE_RX_HDR_SIZE)
 807                                 len = IXGBE_RX_HDR_SIZE;
 808                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 809                 } else {
 810                         len = le16_to_cpu(rx_desc->wb.upper.length);
 811                 }
 812
 813                 cleaned = true;
 814                 skb = rx_buffer_info->skb;
 815                 prefetch(skb->data - NET_IP_ALIGN);
 816                 rx_buffer_info->skb = NULL;
 817
 818                 if (rx_buffer_info->dma) {
 819                         pci_unmap_single(pdev, rx_buffer_info->dma,
 820                                          rx_ring->rx_buf_len,
 821                                          PCI_DMA_FROMDEVICE);
 822                         rx_buffer_info->dma = 0;
 823                         skb_put(skb, len);
 824                 }
 825
 826                 if (upper_len) {
 827                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 828                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 829                         rx_buffer_info->page_dma = 0;
 830                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 831                                            rx_buffer_info->page,
 832                                            rx_buffer_info->page_offset,
 833                                            upper_len);
 834
 835                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 836                             (page_count(rx_buffer_info->page) != 1))
 837                                 rx_buffer_info->page = NULL;
 838                         else
 839                                 get_page(rx_buffer_info->page);
 840
 841                         skb->len += upper_len;
 842                         skb->data_len += upper_len;
 843                         skb->truesize += upper_len;
 844                 }
 845
 846                 i++;
 847                 if (i == rx_ring->count)
 848                         i = 0;
 849
 850                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 851                 prefetch(next_rxd);
 852                 cleaned_count++;
 853
 854                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 855                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 856
 857                 if (rsc_count) {
 858                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 859                                      IXGBE_RXDADV_NEXTP_SHIFT;
 860                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 861                 } else {
 862                         next_buffer = &rx_ring->rx_buffer_info[i];
 863                 }
 864
 865                 if (staterr & IXGBE_RXD_STAT_EOP) {
 866                         if (skb->prev)
 867                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
 868                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
 869                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
 870                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
 871                                 else
 872                                         rx_ring->rsc_count++;
 873                                 rx_ring->rsc_flush++;
 874                         }
 875                         rx_ring->stats.packets++;
 876                         rx_ring->stats.bytes += skb->len;
 877                 } else {
 878                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 879                                 rx_buffer_info->skb = next_buffer->skb;
 880                                 rx_buffer_info->dma = next_buffer->dma;
 881                                 next_buffer->skb = skb;
 882                                 next_buffer->dma = 0;
 883                         } else {
 884                                 skb->next = next_buffer->skb;
 885                                 skb->next->prev = skb;
 886                         }
 887                         adapter->non_eop_descs++;
 888                         goto next_desc;
 889                 }
 890
 891                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 892                         dev_kfree_skb_irq(skb);
 893                         goto next_desc;
 894                 }
 895
 896                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 897
 898                 /* probably a little skewed due to removing CRC */
 899                 total_rx_bytes += skb->len;
 900                 total_rx_packets++;
 901
 902                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 903 #ifdef IXGBE_FCOE
 904                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 905                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 906                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 907                         if (!ddp_bytes)
 908                                 goto next_desc;
 909                 }
 910 #endif /* IXGBE_FCOE */
 911                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 912
 913 next_desc:
 914                 rx_desc->wb.upper.status_error = 0;
 915
 916                 /* return some buffers to hardware, one at a time is too slow */
 917                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 918                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 919                         cleaned_count = 0;
 920                 }
 921
 922                 /* use prefetched values */
 923                 rx_desc = next_rxd;
 924                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 925
 926                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 927         }
 928
 929         rx_ring->next_to_clean = i;
 930         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 931
 932         if (cleaned_count)
 933                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 934
 935 #ifdef IXGBE_FCOE
 936         /* include DDPed FCoE data */
 937         if (ddp_bytes > 0) {
 938                 unsigned int mss;
 939
 940                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 941                         sizeof(struct fc_frame_header) -
 942                         sizeof(struct fcoe_crc_eof);
 943                 if (mss > 512)
 944                         mss &= ~511;
 945                 total_rx_bytes += ddp_bytes;
 946                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 947         }
 948 #endif /* IXGBE_FCOE */
 949
 950         rx_ring->total_packets += total_rx_packets;
 951         rx_ring->total_bytes += total_rx_bytes;
 952         netdev->stats.rx_bytes += total_rx_bytes;
 953         netdev->stats.rx_packets += total_rx_packets;
 954
 955         return cleaned;
 956 }
 957
 958 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 959 /**
 960  * ixgbe_configure_msix - Configure MSI-X hardware
 961  * @adapter: board private structure
 962  *
 963  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 964  * interrupts.
 965  **/
 966 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 967 {
 968         struct ixgbe_q_vector *q_vector;
 969         int i, j, q_vectors, v_idx, r_idx;
 970         u32 mask;
 971
 972         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 973
 974         /*
 975          * Populate the IVAR table and set the ITR values to the
 976          * corresponding register.
 977          */
 978         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 979                 q_vector = adapter->q_vector[v_idx];
 980                 /* XXX for_each_bit(...) */
 981                 r_idx = find_first_bit(q_vector->rxr_idx,
 982                                        adapter->num_rx_queues);
 983
 984                 for (i = 0; i < q_vector->rxr_count; i++) {
 985                         j = adapter->rx_ring[r_idx].reg_idx;
 986                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 987                         r_idx = find_next_bit(q_vector->rxr_idx,
 988                                               adapter->num_rx_queues,
 989                                               r_idx + 1);
 990                 }
 991                 r_idx = find_first_bit(q_vector->txr_idx,
 992                                        adapter->num_tx_queues);
 993
 994                 for (i = 0; i < q_vector->txr_count; i++) {
 995                         j = adapter->tx_ring[r_idx].reg_idx;
 996                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 997                         r_idx = find_next_bit(q_vector->txr_idx,
 998                                               adapter->num_tx_queues,
 999                                               r_idx + 1);
1000                 }
1001
1002                 if (q_vector->txr_count && !q_vector->rxr_count)
1003                         /* tx only */
1004                         q_vector->eitr = adapter->tx_eitr_param;
1005                 else if (q_vector->rxr_count)
1006                         /* rx or mixed */
1007                         q_vector->eitr = adapter->rx_eitr_param;
1008
1009                 ixgbe_write_eitr(q_vector);
1010         }
1011
1012         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1013                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1014                                v_idx);
1015         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1016                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1017         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1018
1019         /* set up to autoclear timer, and the vectors */
1020         mask = IXGBE_EIMS_ENABLE_MASK;
1021         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1022         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1023 }
1024
1025 enum latency_range {
1026         lowest_latency = 0,
1027         low_latency = 1,
1028         bulk_latency = 2,
1029         latency_invalid = 255
1030 };
1031
1032 /**
1033  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1034  * @adapter: pointer to adapter
1035  * @eitr: eitr setting (ints per sec) to give last timeslice
1036  * @itr_setting: current throttle rate in ints/second
1037  * @packets: the number of packets during this measurement interval
1038  * @bytes: the number of bytes during this measurement interval
1039  *
1040  *      Stores a new ITR value based on packets and byte
1041  *      counts during the last interrupt.  The advantage of per interrupt
1042  *      computation is faster updates and more accurate ITR for the current
1043  *      traffic pattern.  Constants in this function were computed
1044  *      based on theoretical maximum wire speed and thresholds were set based
1045  *      on testing data as well as attempting to minimize response time
1046  *      while increasing bulk throughput.
1047  *      this functionality is controlled by the InterruptThrottleRate module
1048  *      parameter (see ixgbe_param.c)
1049  **/
1050 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1051                            u32 eitr, u8 itr_setting,
1052                            int packets, int bytes)
1053 {
1054         unsigned int retval = itr_setting;
1055         u32 timepassed_us;
1056         u64 bytes_perint;
1057
1058         if (packets == 0)
1059                 goto update_itr_done;
1060
1061
1062         /* simple throttlerate management
1063          *    0-20MB/s lowest (100000 ints/s)
1064          *   20-100MB/s low   (20000 ints/s)
1065          *  100-1249MB/s bulk (8000 ints/s)
1066          */
1067         /* what was last interrupt timeslice? */
1068         timepassed_us = 1000000/eitr;
1069         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1070
1071         switch (itr_setting) {
1072         case lowest_latency:
1073                 if (bytes_perint > adapter->eitr_low)
1074                         retval = low_latency;
1075                 break;
1076         case low_latency:
1077                 if (bytes_perint > adapter->eitr_high)
1078                         retval = bulk_latency;
1079                 else if (bytes_perint <= adapter->eitr_low)
1080                         retval = lowest_latency;
1081                 break;
1082         case bulk_latency:
1083                 if (bytes_perint <= adapter->eitr_high)
1084                         retval = low_latency;
1085                 break;
1086         }
1087
1088 update_itr_done:
1089         return retval;
1090 }
1091
1092 /**
1093  * ixgbe_write_eitr - write EITR register in hardware specific way
1094  * @q_vector: structure containing interrupt and ring information
1095  *
1096  * This function is made to be called by ethtool and by the driver
1097  * when it needs to update EITR registers at runtime.  Hardware
1098  * specific quirks/differences are taken care of here.
1099  */
1100 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1101 {
1102         struct ixgbe_adapter *adapter = q_vector->adapter;
1103         struct ixgbe_hw *hw = &adapter->hw;
1104         int v_idx = q_vector->v_idx;
1105         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1106
1107         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1108                 /* must write high and low 16 bits to reset counter */
1109                 itr_reg |= (itr_reg << 16);
1110         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1111                 /*
1112                  * set the WDIS bit to not clear the timer bits and cause an
1113                  * immediate assertion of the interrupt
1114                  */
1115                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1116         }
1117         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1118 }
1119
1120 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1121 {
1122         struct ixgbe_adapter *adapter = q_vector->adapter;
1123         u32 new_itr;
1124         u8 current_itr, ret_itr;
1125         int i, r_idx;
1126         struct ixgbe_ring *rx_ring, *tx_ring;
1127
1128         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1129         for (i = 0; i < q_vector->txr_count; i++) {
1130                 tx_ring = &(adapter->tx_ring[r_idx]);
1131                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1132                                            q_vector->tx_itr,
1133                                            tx_ring->total_packets,
1134                                            tx_ring->total_bytes);
1135                 /* if the result for this queue would decrease interrupt
1136                  * rate for this vector then use that result */
1137                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1138                                     q_vector->tx_itr - 1 : ret_itr);
1139                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1140                                       r_idx + 1);
1141         }
1142
1143         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1144         for (i = 0; i < q_vector->rxr_count; i++) {
1145                 rx_ring = &(adapter->rx_ring[r_idx]);
1146                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1147                                            q_vector->rx_itr,
1148                                            rx_ring->total_packets,
1149                                            rx_ring->total_bytes);
1150                 /* if the result for this queue would decrease interrupt
1151                  * rate for this vector then use that result */
1152                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1153                                     q_vector->rx_itr - 1 : ret_itr);
1154                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1155                                       r_idx + 1);
1156         }
1157
1158         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1159
1160         switch (current_itr) {
1161         /* counts and packets in update_itr are dependent on these numbers */
1162         case lowest_latency:
1163                 new_itr = 100000;
1164                 break;
1165         case low_latency:
1166                 new_itr = 20000; /* aka hwitr = ~200 */
1167                 break;
1168         case bulk_latency:
1169         default:
1170                 new_itr = 8000;
1171                 break;
1172         }
1173
1174         if (new_itr != q_vector->eitr) {
1175                 /* do an exponential smoothing */
1176                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1177
1178                 /* save the algorithm value here, not the smoothed one */
1179                 q_vector->eitr = new_itr;
1180
1181                 ixgbe_write_eitr(q_vector);
1182         }
1183
1184         return;
1185 }
1186
1187 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1188 {
1189         struct ixgbe_hw *hw = &adapter->hw;
1190
1191         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1192             (eicr & IXGBE_EICR_GPI_SDP1)) {
1193                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1194                 /* write to clear the interrupt */
1195                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1196         }
1197 }
1198
1199 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1200 {
1201         struct ixgbe_hw *hw = &adapter->hw;
1202
1203         if (eicr & IXGBE_EICR_GPI_SDP1) {
1204                 /* Clear the interrupt */
1205                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1206                 schedule_work(&adapter->multispeed_fiber_task);
1207         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1208                 /* Clear the interrupt */
1209                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1210                 schedule_work(&adapter->sfp_config_module_task);
1211         } else {
1212                 /* Interrupt isn't for us... */
1213                 return;
1214         }
1215 }
1216
1217 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1218 {
1219         struct ixgbe_hw *hw = &adapter->hw;
1220
1221         adapter->lsc_int++;
1222         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1223         adapter->link_check_timeout = jiffies;
1224         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1225                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1226                 IXGBE_WRITE_FLUSH(hw);
1227                 schedule_work(&adapter->watchdog_task);
1228         }
1229 }
1230
1231 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1232 {
1233         struct net_device *netdev = data;
1234         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1235         struct ixgbe_hw *hw = &adapter->hw;
1236         u32 eicr;
1237
1238         /*
1239          * Workaround for Silicon errata.  Use clear-by-write instead
1240          * of clear-by-read.  Reading with EICS will return the
1241          * interrupt causes without clearing, which later be done
1242          * with the write to EICR.
1243          */
1244         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1245         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1246
1247         if (eicr & IXGBE_EICR_LSC)
1248                 ixgbe_check_lsc(adapter);
1249
1250         if (hw->mac.type == ixgbe_mac_82598EB)
1251                 ixgbe_check_fan_failure(adapter, eicr);
1252
1253         if (hw->mac.type == ixgbe_mac_82599EB) {
1254                 ixgbe_check_sfp_event(adapter, eicr);
1255
1256                 /* Handle Flow Director Full threshold interrupt */
1257                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1258                         int i;
1259                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1260                         /* Disable transmits before FDIR Re-initialization */
1261                         netif_tx_stop_all_queues(netdev);
1262                         for (i = 0; i < adapter->num_tx_queues; i++) {
1263                                 struct ixgbe_ring *tx_ring =
1264                                                            &adapter->tx_ring[i];
1265                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1266                                                        &tx_ring->reinit_state))
1267                                         schedule_work(&adapter->fdir_reinit_task);
1268                         }
1269                 }
1270         }
1271         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1272                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1273
1274         return IRQ_HANDLED;
1275 }
1276
1277 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1278                                            u64 qmask)
1279 {
1280         u32 mask;
1281
1282         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1283                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1284                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1285         } else {
1286                 mask = (qmask & 0xFFFFFFFF);
1287                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1288                 mask = (qmask >> 32);
1289                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1290         }
1291         /* skip the flush */
1292 }
1293
1294 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1295                                             u64 qmask)
1296 {
1297         u32 mask;
1298
1299         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1300                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1301                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1302         } else {
1303                 mask = (qmask & 0xFFFFFFFF);
1304                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1305                 mask = (qmask >> 32);
1306                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1307         }
1308         /* skip the flush */
1309 }
1310
1311 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1312 {
1313         struct ixgbe_q_vector *q_vector = data;
1314         struct ixgbe_adapter  *adapter = q_vector->adapter;
1315         struct ixgbe_ring     *tx_ring;
1316         int i, r_idx;
1317
1318         if (!q_vector->txr_count)
1319                 return IRQ_HANDLED;
1320
1321         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1322         for (i = 0; i < q_vector->txr_count; i++) {
1323                 tx_ring = &(adapter->tx_ring[r_idx]);
1324                 tx_ring->total_bytes = 0;
1325                 tx_ring->total_packets = 0;
1326                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1327                                       r_idx + 1);
1328         }
1329
1330         /* disable interrupts on this vector only */
1331         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1332         napi_schedule(&q_vector->napi);
1333
1334         return IRQ_HANDLED;
1335 }
1336
1337 /**
1338  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1339  * @irq: unused
1340  * @data: pointer to our q_vector struct for this interrupt vector
1341  **/
1342 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1343 {
1344         struct ixgbe_q_vector *q_vector = data;
1345         struct ixgbe_adapter  *adapter = q_vector->adapter;
1346         struct ixgbe_ring  *rx_ring;
1347         int r_idx;
1348         int i;
1349
1350         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1351         for (i = 0;  i < q_vector->rxr_count; i++) {
1352                 rx_ring = &(adapter->rx_ring[r_idx]);
1353                 rx_ring->total_bytes = 0;
1354                 rx_ring->total_packets = 0;
1355                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1356                                       r_idx + 1);
1357         }
1358
1359         if (!q_vector->rxr_count)
1360                 return IRQ_HANDLED;
1361
1362         /* disable interrupts on this vector only */
1363         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1364         napi_schedule(&q_vector->napi);
1365
1366         return IRQ_HANDLED;
1367 }
1368
1369 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1370 {
1371         struct ixgbe_q_vector *q_vector = data;
1372         struct ixgbe_adapter  *adapter = q_vector->adapter;
1373         struct ixgbe_ring  *ring;
1374         int r_idx;
1375         int i;
1376
1377         if (!q_vector->txr_count && !q_vector->rxr_count)
1378                 return IRQ_HANDLED;
1379
1380         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1381         for (i = 0; i < q_vector->txr_count; i++) {
1382                 ring = &(adapter->tx_ring[r_idx]);
1383                 ring->total_bytes = 0;
1384                 ring->total_packets = 0;
1385                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1386                                       r_idx + 1);
1387         }
1388
1389         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1390         for (i = 0; i < q_vector->rxr_count; i++) {
1391                 ring = &(adapter->rx_ring[r_idx]);
1392                 ring->total_bytes = 0;
1393                 ring->total_packets = 0;
1394                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1395                                       r_idx + 1);
1396         }
1397
1398         /* disable interrupts on this vector only */
1399         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1400         napi_schedule(&q_vector->napi);
1401
1402         return IRQ_HANDLED;
1403 }
1404
1405 /**
1406  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1407  * @napi: napi struct with our devices info in it
1408  * @budget: amount of work driver is allowed to do this pass, in packets
1409  *
1410  * This function is optimized for cleaning one queue only on a single
1411  * q_vector!!!
1412  **/
1413 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1414 {
1415         struct ixgbe_q_vector *q_vector =
1416                                container_of(napi, struct ixgbe_q_vector, napi);
1417         struct ixgbe_adapter *adapter = q_vector->adapter;
1418         struct ixgbe_ring *rx_ring = NULL;
1419         int work_done = 0;
1420         long r_idx;
1421
1422         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1423         rx_ring = &(adapter->rx_ring[r_idx]);
1424 #ifdef CONFIG_IXGBE_DCA
1425         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1426                 ixgbe_update_rx_dca(adapter, rx_ring);
1427 #endif
1428
1429         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1430
1431         /* If all Rx work done, exit the polling mode */
1432         if (work_done < budget) {
1433                 napi_complete(napi);
1434                 if (adapter->rx_itr_setting & 1)
1435                         ixgbe_set_itr_msix(q_vector);
1436                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1437                         ixgbe_irq_enable_queues(adapter,
1438                                                 ((u64)1 << q_vector->v_idx));
1439         }
1440
1441         return work_done;
1442 }
1443
1444 /**
1445  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1446  * @napi: napi struct with our devices info in it
1447  * @budget: amount of work driver is allowed to do this pass, in packets
1448  *
1449  * This function will clean more than one rx queue associated with a
1450  * q_vector.
1451  **/
1452 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1453 {
1454         struct ixgbe_q_vector *q_vector =
1455                                container_of(napi, struct ixgbe_q_vector, napi);
1456         struct ixgbe_adapter *adapter = q_vector->adapter;
1457         struct ixgbe_ring *ring = NULL;
1458         int work_done = 0, i;
1459         long r_idx;
1460         bool tx_clean_complete = true;
1461
1462         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1463         for (i = 0; i < q_vector->txr_count; i++) {
1464                 ring = &(adapter->tx_ring[r_idx]);
1465 #ifdef CONFIG_IXGBE_DCA
1466                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1467                         ixgbe_update_tx_dca(adapter, ring);
1468 #endif
1469                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1470                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1471                                       r_idx + 1);
1472         }
1473
1474         /* attempt to distribute budget to each queue fairly, but don't allow
1475          * the budget to go below 1 because we'll exit polling */
1476         budget /= (q_vector->rxr_count ?: 1);
1477         budget = max(budget, 1);
1478         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1479         for (i = 0; i < q_vector->rxr_count; i++) {
1480                 ring = &(adapter->rx_ring[r_idx]);
1481 #ifdef CONFIG_IXGBE_DCA
1482                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1483                         ixgbe_update_rx_dca(adapter, ring);
1484 #endif
1485                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1486                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1487                                       r_idx + 1);
1488         }
1489
1490         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1491         ring = &(adapter->rx_ring[r_idx]);
1492         /* If all Rx work done, exit the polling mode */
1493         if (work_done < budget) {
1494                 napi_complete(napi);
1495                 if (adapter->rx_itr_setting & 1)
1496                         ixgbe_set_itr_msix(q_vector);
1497                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1498                         ixgbe_irq_enable_queues(adapter,
1499                                                 ((u64)1 << q_vector->v_idx));
1500                 return 0;
1501         }
1502
1503         return work_done;
1504 }
1505
1506 /**
1507  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1508  * @napi: napi struct with our devices info in it
1509  * @budget: amount of work driver is allowed to do this pass, in packets
1510  *
1511  * This function is optimized for cleaning one queue only on a single
1512  * q_vector!!!
1513  **/
1514 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1515 {
1516         struct ixgbe_q_vector *q_vector =
1517                                container_of(napi, struct ixgbe_q_vector, napi);
1518         struct ixgbe_adapter *adapter = q_vector->adapter;
1519         struct ixgbe_ring *tx_ring = NULL;
1520         int work_done = 0;
1521         long r_idx;
1522
1523         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1524         tx_ring = &(adapter->tx_ring[r_idx]);
1525 #ifdef CONFIG_IXGBE_DCA
1526         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1527                 ixgbe_update_tx_dca(adapter, tx_ring);
1528 #endif
1529
1530         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1531                 work_done = budget;
1532
1533         /* If all Tx work done, exit the polling mode */
1534         if (work_done < budget) {
1535                 napi_complete(napi);
1536                 if (adapter->tx_itr_setting & 1)
1537                         ixgbe_set_itr_msix(q_vector);
1538                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1539                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1540         }
1541
1542         return work_done;
1543 }
1544
1545 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1546                                      int r_idx)
1547 {
1548         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1549
1550         set_bit(r_idx, q_vector->rxr_idx);
1551         q_vector->rxr_count++;
1552 }
1553
1554 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1555                                      int t_idx)
1556 {
1557         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1558
1559         set_bit(t_idx, q_vector->txr_idx);
1560         q_vector->txr_count++;
1561 }
1562
1563 /**
1564  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1565  * @adapter: board private structure to initialize
1566  * @vectors: allotted vector count for descriptor rings
1567  *
1568  * This function maps descriptor rings to the queue-specific vectors
1569  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1570  * one vector per ring/queue, but on a constrained vector budget, we
1571  * group the rings as "efficiently" as possible.  You would add new
1572  * mapping configurations in here.
1573  **/
1574 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1575                                       int vectors)
1576 {
1577         int v_start = 0;
1578         int rxr_idx = 0, txr_idx = 0;
1579         int rxr_remaining = adapter->num_rx_queues;
1580         int txr_remaining = adapter->num_tx_queues;
1581         int i, j;
1582         int rqpv, tqpv;
1583         int err = 0;
1584
1585         /* No mapping required if MSI-X is disabled. */
1586         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1587                 goto out;
1588
1589         /*
1590          * The ideal configuration...
1591          * We have enough vectors to map one per queue.
1592          */
1593         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1594                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1595                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1596
1597                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1598                         map_vector_to_txq(adapter, v_start, txr_idx);
1599
1600                 goto out;
1601         }
1602
1603         /*
1604          * If we don't have enough vectors for a 1-to-1
1605          * mapping, we'll have to group them so there are
1606          * multiple queues per vector.
1607          */
1608         /* Re-adjusting *qpv takes care of the remainder. */
1609         for (i = v_start; i < vectors; i++) {
1610                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1611                 for (j = 0; j < rqpv; j++) {
1612                         map_vector_to_rxq(adapter, i, rxr_idx);
1613                         rxr_idx++;
1614                         rxr_remaining--;
1615                 }
1616         }
1617         for (i = v_start; i < vectors; i++) {
1618                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1619                 for (j = 0; j < tqpv; j++) {
1620                         map_vector_to_txq(adapter, i, txr_idx);
1621                         txr_idx++;
1622                         txr_remaining--;
1623                 }
1624         }
1625
1626 out:
1627         return err;
1628 }
1629
1630 /**
1631  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1632  * @adapter: board private structure
1633  *
1634  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1635  * interrupts from the kernel.
1636  **/
1637 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1638 {
1639         struct net_device *netdev = adapter->netdev;
1640         irqreturn_t (*handler)(int, void *);
1641         int i, vector, q_vectors, err;
1642         int ri=0, ti=0;
1643
1644         /* Decrement for Other and TCP Timer vectors */
1645         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1646
1647         /* Map the Tx/Rx rings to the vectors we were allotted. */
1648         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1649         if (err)
1650                 goto out;
1651
1652 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1653                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1654                          &ixgbe_msix_clean_many)
1655         for (vector = 0; vector < q_vectors; vector++) {
1656                 handler = SET_HANDLER(adapter->q_vector[vector]);
1657
1658                 if(handler == &ixgbe_msix_clean_rx) {
1659                         sprintf(adapter->name[vector], "%s-%s-%d",
1660                                 netdev->name, "rx", ri++);
1661                 }
1662                 else if(handler == &ixgbe_msix_clean_tx) {
1663                         sprintf(adapter->name[vector], "%s-%s-%d",
1664                                 netdev->name, "tx", ti++);
1665                 }
1666                 else
1667                         sprintf(adapter->name[vector], "%s-%s-%d",
1668                                 netdev->name, "TxRx", vector);
1669
1670                 err = request_irq(adapter->msix_entries[vector].vector,
1671                                   handler, 0, adapter->name[vector],
1672                                   adapter->q_vector[vector]);
1673                 if (err) {
1674                         DPRINTK(PROBE, ERR,
1675                                 "request_irq failed for MSIX interrupt "
1676                                 "Error: %d\n", err);
1677                         goto free_queue_irqs;
1678                 }
1679         }
1680
1681         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1682         err = request_irq(adapter->msix_entries[vector].vector,
1683                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1684         if (err) {
1685                 DPRINTK(PROBE, ERR,
1686                         "request_irq for msix_lsc failed: %d\n", err);
1687                 goto free_queue_irqs;
1688         }
1689
1690         return 0;
1691
1692 free_queue_irqs:
1693         for (i = vector - 1; i >= 0; i--)
1694                 free_irq(adapter->msix_entries[--vector].vector,
1695                          adapter->q_vector[i]);
1696         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1697         pci_disable_msix(adapter->pdev);
1698         kfree(adapter->msix_entries);
1699         adapter->msix_entries = NULL;
1700 out:
1701         return err;
1702 }
1703
1704 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1705 {
1706         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1707         u8 current_itr;
1708         u32 new_itr = q_vector->eitr;
1709         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1710         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1711
1712         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1713                                             q_vector->tx_itr,
1714                                             tx_ring->total_packets,
1715                                             tx_ring->total_bytes);
1716         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1717                                             q_vector->rx_itr,
1718                                             rx_ring->total_packets,
1719                                             rx_ring->total_bytes);
1720
1721         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1722
1723         switch (current_itr) {
1724         /* counts and packets in update_itr are dependent on these numbers */
1725         case lowest_latency:
1726                 new_itr = 100000;
1727                 break;
1728         case low_latency:
1729                 new_itr = 20000; /* aka hwitr = ~200 */
1730                 break;
1731         case bulk_latency:
1732                 new_itr = 8000;
1733                 break;
1734         default:
1735                 break;
1736         }
1737
1738         if (new_itr != q_vector->eitr) {
1739                 /* do an exponential smoothing */
1740                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1741
1742                 /* save the algorithm value here, not the smoothed one */
1743                 q_vector->eitr = new_itr;
1744
1745                 ixgbe_write_eitr(q_vector);
1746         }
1747
1748         return;
1749 }
1750
1751 /**
1752  * ixgbe_irq_enable - Enable default interrupt generation settings
1753  * @adapter: board private structure
1754  **/
1755 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1756 {
1757         u32 mask;
1758
1759         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1760         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1761                 mask |= IXGBE_EIMS_GPI_SDP1;
1762         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1763                 mask |= IXGBE_EIMS_ECC;
1764                 mask |= IXGBE_EIMS_GPI_SDP1;
1765                 mask |= IXGBE_EIMS_GPI_SDP2;
1766         }
1767         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1768             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1769                 mask |= IXGBE_EIMS_FLOW_DIR;
1770
1771         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1772         ixgbe_irq_enable_queues(adapter, ~0);
1773         IXGBE_WRITE_FLUSH(&adapter->hw);
1774 }
1775
1776 /**
1777  * ixgbe_intr - legacy mode Interrupt Handler
1778  * @irq: interrupt number
1779  * @data: pointer to a network interface device structure
1780  **/
1781 static irqreturn_t ixgbe_intr(int irq, void *data)
1782 {
1783         struct net_device *netdev = data;
1784         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1785         struct ixgbe_hw *hw = &adapter->hw;
1786         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1787         u32 eicr;
1788
1789         /*
1790          * Workaround for silicon errata.  Mask the interrupts
1791          * before the read of EICR.
1792          */
1793         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1794
1795         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1796          * therefore no explict interrupt disable is necessary */
1797         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1798         if (!eicr) {
1799                 /* shared interrupt alert!
1800                  * make sure interrupts are enabled because the read will
1801                  * have disabled interrupts due to EIAM */
1802                 ixgbe_irq_enable(adapter);
1803                 return IRQ_NONE;        /* Not our interrupt */
1804         }
1805
1806         if (eicr & IXGBE_EICR_LSC)
1807                 ixgbe_check_lsc(adapter);
1808
1809         if (hw->mac.type == ixgbe_mac_82599EB)
1810                 ixgbe_check_sfp_event(adapter, eicr);
1811
1812         ixgbe_check_fan_failure(adapter, eicr);
1813
1814         if (napi_schedule_prep(&(q_vector->napi))) {
1815                 adapter->tx_ring[0].total_packets = 0;
1816                 adapter->tx_ring[0].total_bytes = 0;
1817                 adapter->rx_ring[0].total_packets = 0;
1818                 adapter->rx_ring[0].total_bytes = 0;
1819                 /* would disable interrupts here but EIAM disabled it */
1820                 __napi_schedule(&(q_vector->napi));
1821         }
1822
1823         return IRQ_HANDLED;
1824 }
1825
1826 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1827 {
1828         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1829
1830         for (i = 0; i < q_vectors; i++) {
1831                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1832                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1833                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1834                 q_vector->rxr_count = 0;
1835                 q_vector->txr_count = 0;
1836         }
1837 }
1838
1839 /**
1840  * ixgbe_request_irq - initialize interrupts
1841  * @adapter: board private structure
1842  *
1843  * Attempts to configure interrupts using the best available
1844  * capabilities of the hardware and kernel.
1845  **/
1846 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1847 {
1848         struct net_device *netdev = adapter->netdev;
1849         int err;
1850
1851         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1852                 err = ixgbe_request_msix_irqs(adapter);
1853         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1854                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
1855                                   netdev->name, netdev);
1856         } else {
1857                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
1858                                   netdev->name, netdev);
1859         }
1860
1861         if (err)
1862                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1863
1864         return err;
1865 }
1866
1867 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1868 {
1869         struct net_device *netdev = adapter->netdev;
1870
1871         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1872                 int i, q_vectors;
1873
1874                 q_vectors = adapter->num_msix_vectors;
1875
1876                 i = q_vectors - 1;
1877                 free_irq(adapter->msix_entries[i].vector, netdev);
1878
1879                 i--;
1880                 for (; i >= 0; i--) {
1881                         free_irq(adapter->msix_entries[i].vector,
1882                                  adapter->q_vector[i]);
1883                 }
1884
1885                 ixgbe_reset_q_vectors(adapter);
1886         } else {
1887                 free_irq(adapter->pdev->irq, netdev);
1888         }
1889 }
1890
1891 /**
1892  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1893  * @adapter: board private structure
1894  **/
1895 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1896 {
1897         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1898                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1899         } else {
1900                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1901                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1902                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1903         }
1904         IXGBE_WRITE_FLUSH(&adapter->hw);
1905         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1906                 int i;
1907                 for (i = 0; i < adapter->num_msix_vectors; i++)
1908                         synchronize_irq(adapter->msix_entries[i].vector);
1909         } else {
1910                 synchronize_irq(adapter->pdev->irq);
1911         }
1912 }
1913
1914 /**
1915  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1916  *
1917  **/
1918 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1919 {
1920         struct ixgbe_hw *hw = &adapter->hw;
1921
1922         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1923                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1924
1925         ixgbe_set_ivar(adapter, 0, 0, 0);
1926         ixgbe_set_ivar(adapter, 1, 0, 0);
1927
1928         map_vector_to_rxq(adapter, 0, 0);
1929         map_vector_to_txq(adapter, 0, 0);
1930
1931         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1932 }
1933
1934 /**
1935  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1936  * @adapter: board private structure
1937  *
1938  * Configure the Tx unit of the MAC after a reset.
1939  **/
1940 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1941 {
1942         u64 tdba;
1943         struct ixgbe_hw *hw = &adapter->hw;
1944         u32 i, j, tdlen, txctrl;
1945
1946         /* Setup the HW Tx Head and Tail descriptor pointers */
1947         for (i = 0; i < adapter->num_tx_queues; i++) {
1948                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1949                 j = ring->reg_idx;
1950                 tdba = ring->dma;
1951                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1952                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1953                                 (tdba & DMA_BIT_MASK(32)));
1954                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1955                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1956                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1957                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1958                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1959                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1960                 /*
1961                  * Disable Tx Head Writeback RO bit, since this hoses
1962                  * bookkeeping if things aren't delivered in order.
1963                  */
1964                 switch (hw->mac.type) {
1965                 case ixgbe_mac_82598EB:
1966                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1967                         break;
1968                 case ixgbe_mac_82599EB:
1969                 default:
1970                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1971                         break;
1972                 }
1973                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1974                 switch (hw->mac.type) {
1975                 case ixgbe_mac_82598EB:
1976                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1977                         break;
1978                 case ixgbe_mac_82599EB:
1979                 default:
1980                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1981                         break;
1982                 }
1983         }
1984
1985         if (hw->mac.type == ixgbe_mac_82599EB) {
1986                 u32 rttdcs;
1987
1988                 /* disable the arbiter while setting MTQC */
1989                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
1990                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
1991                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
1992
1993                 /* We enable 8 traffic classes, DCB only */
1994                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1995                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1996                                         IXGBE_MTQC_8TC_8TQ));
1997                 else
1998                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
1999
2000                 /* re-eable the arbiter */
2001                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2002                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2003         }
2004 }
2005
2006 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2007
2008 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2009                                    struct ixgbe_ring *rx_ring)
2010 {
2011         u32 srrctl;
2012         int index;
2013         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2014
2015         index = rx_ring->reg_idx;
2016         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2017                 unsigned long mask;
2018                 mask = (unsigned long) feature[RING_F_RSS].mask;
2019                 index = index & mask;
2020         }
2021         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2022
2023         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2024         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2025
2026         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2027                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2028
2029         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2030 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2031                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2032 #else
2033                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2034 #endif
2035                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2036         } else {
2037                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2038                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2039                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2040         }
2041
2042         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2043 }
2044
2045 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2046 {
2047         u32 mrqc = 0;
2048         int mask;
2049
2050         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2051                 return mrqc;
2052
2053         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2054 #ifdef CONFIG_IXGBE_DCB
2055                                  | IXGBE_FLAG_DCB_ENABLED
2056 #endif
2057                                 );
2058
2059         switch (mask) {
2060         case (IXGBE_FLAG_RSS_ENABLED):
2061                 mrqc = IXGBE_MRQC_RSSEN;
2062                 break;
2063 #ifdef CONFIG_IXGBE_DCB
2064         case (IXGBE_FLAG_DCB_ENABLED):
2065                 mrqc = IXGBE_MRQC_RT8TCEN;
2066                 break;
2067 #endif /* CONFIG_IXGBE_DCB */
2068         default:
2069                 break;
2070         }
2071
2072         return mrqc;
2073 }
2074
2075 /**
2076  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2077  * @adapter:    address of board private structure
2078  * @index:      index of ring to set
2079  **/
2080 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2081 {
2082         struct ixgbe_ring *rx_ring;
2083         struct ixgbe_hw *hw = &adapter->hw;
2084         int j;
2085         u32 rscctrl;
2086         int rx_buf_len;
2087
2088         rx_ring = &adapter->rx_ring[index];
2089         j = rx_ring->reg_idx;
2090         rx_buf_len = rx_ring->rx_buf_len;
2091         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2092         rscctrl |= IXGBE_RSCCTL_RSCEN;
2093         /*
2094          * we must limit the number of descriptors so that the
2095          * total size of max desc * buf_len is not greater
2096          * than 65535
2097          */
2098         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2099 #if (MAX_SKB_FRAGS > 16)
2100                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2101 #elif (MAX_SKB_FRAGS > 8)
2102                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2103 #elif (MAX_SKB_FRAGS > 4)
2104                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2105 #else
2106                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2107 #endif
2108         } else {
2109                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2110                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2111                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2112                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2113                 else
2114                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2115         }
2116         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2117 }
2118
2119 /**
2120  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2121  * @adapter: board private structure
2122  *
2123  * Configure the Rx unit of the MAC after a reset.
2124  **/
2125 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2126 {
2127         u64 rdba;
2128         struct ixgbe_hw *hw = &adapter->hw;
2129         struct ixgbe_ring *rx_ring;
2130         struct net_device *netdev = adapter->netdev;
2131         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2132         int i, j;
2133         u32 rdlen, rxctrl, rxcsum;
2134         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2135                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2136                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2137         u32 fctrl, hlreg0;
2138         u32 reta = 0, mrqc = 0;
2139         u32 rdrxctl;
2140         int rx_buf_len;
2141
2142         /* Decide whether to use packet split mode or not */
2143         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2144
2145         /* Set the RX buffer length according to the mode */
2146         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2147                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2148                 if (hw->mac.type == ixgbe_mac_82599EB) {
2149                         /* PSRTYPE must be initialized in 82599 */
2150                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2151                                       IXGBE_PSRTYPE_UDPHDR |
2152                                       IXGBE_PSRTYPE_IPV4HDR |
2153                                       IXGBE_PSRTYPE_IPV6HDR |
2154                                       IXGBE_PSRTYPE_L2HDR;
2155                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2156                 }
2157         } else {
2158                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2159                     (netdev->mtu <= ETH_DATA_LEN))
2160                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2161                 else
2162                         rx_buf_len = ALIGN(max_frame, 1024);
2163         }
2164
2165         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2166         fctrl |= IXGBE_FCTRL_BAM;
2167         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2168         fctrl |= IXGBE_FCTRL_PMCF;
2169         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2170
2171         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2172         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2173                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2174         else
2175                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2176 #ifdef IXGBE_FCOE
2177         if (netdev->features & NETIF_F_FCOE_MTU)
2178                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2179 #endif
2180         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2181
2182         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2183         /* disable receives while setting up the descriptors */
2184         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2185         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2186
2187         /*
2188          * Setup the HW Rx Head and Tail Descriptor Pointers and
2189          * the Base and Length of the Rx Descriptor Ring
2190          */
2191         for (i = 0; i < adapter->num_rx_queues; i++) {
2192                 rx_ring = &adapter->rx_ring[i];
2193                 rdba = rx_ring->dma;
2194                 j = rx_ring->reg_idx;
2195                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2196                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2197                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2198                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2199                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2200                 rx_ring->head = IXGBE_RDH(j);
2201                 rx_ring->tail = IXGBE_RDT(j);
2202                 rx_ring->rx_buf_len = rx_buf_len;
2203
2204                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2205                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2206                 else
2207                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2208
2209 #ifdef IXGBE_FCOE
2210                 if (netdev->features & NETIF_F_FCOE_MTU) {
2211                         struct ixgbe_ring_feature *f;
2212                         f = &adapter->ring_feature[RING_F_FCOE];
2213                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2214                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2215                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2216                                         rx_ring->rx_buf_len =
2217                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2218                         }
2219                 }
2220
2221 #endif /* IXGBE_FCOE */
2222                 ixgbe_configure_srrctl(adapter, rx_ring);
2223         }
2224
2225         if (hw->mac.type == ixgbe_mac_82598EB) {
2226                 /*
2227                  * For VMDq support of different descriptor types or
2228                  * buffer sizes through the use of multiple SRRCTL
2229                  * registers, RDRXCTL.MVMEN must be set to 1
2230                  *
2231                  * also, the manual doesn't mention it clearly but DCA hints
2232                  * will only use queue 0's tags unless this bit is set.  Side
2233                  * effects of setting this bit are only that SRRCTL must be
2234                  * fully programmed [0..15]
2235                  */
2236                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2237                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2238                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2239         }
2240
2241         /* Program MRQC for the distribution of queues */
2242         mrqc = ixgbe_setup_mrqc(adapter);
2243
2244         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2245                 /* Fill out redirection table */
2246                 for (i = 0, j = 0; i < 128; i++, j++) {
2247                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2248                                 j = 0;
2249                         /* reta = 4-byte sliding window of
2250                          * 0x00..(indices-1)(indices-1)00..etc. */
2251                         reta = (reta << 8) | (j * 0x11);
2252                         if ((i & 3) == 3)
2253                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2254                 }
2255
2256                 /* Fill out hash function seeds */
2257                 for (i = 0; i < 10; i++)
2258                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2259
2260                 if (hw->mac.type == ixgbe_mac_82598EB)
2261                         mrqc |= IXGBE_MRQC_RSSEN;
2262                     /* Perform hash on these packet types */
2263                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2264                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2265                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2266                       | IXGBE_MRQC_RSS_FIELD_IPV6
2267                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2268                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2269         }
2270         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2271
2272         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2273
2274         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2275             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2276                 /* Disable indicating checksum in descriptor, enables
2277                  * RSS hash */
2278                 rxcsum |= IXGBE_RXCSUM_PCSD;
2279         }
2280         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2281                 /* Enable IPv4 payload checksum for UDP fragments
2282                  * if PCSD is not set */
2283                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2284         }
2285
2286         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2287
2288         if (hw->mac.type == ixgbe_mac_82599EB) {
2289                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2290                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2291                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2292                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2293         }
2294
2295         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2296                 /* Enable 82599 HW-RSC */
2297                 for (i = 0; i < adapter->num_rx_queues; i++)
2298                         ixgbe_configure_rscctl(adapter, i);
2299
2300                 /* Disable RSC for ACK packets */
2301                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2302                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2303         }
2304 }
2305
2306 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2307 {
2308         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2309         struct ixgbe_hw *hw = &adapter->hw;
2310
2311         /* add VID to filter table */
2312         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2313 }
2314
2315 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2316 {
2317         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2318         struct ixgbe_hw *hw = &adapter->hw;
2319
2320         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2321                 ixgbe_irq_disable(adapter);
2322
2323         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2324
2325         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2326                 ixgbe_irq_enable(adapter);
2327
2328         /* remove VID from filter table */
2329         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2330 }
2331
2332 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2333                                    struct vlan_group *grp)
2334 {
2335         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2336         u32 ctrl;
2337         int i, j;
2338
2339         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2340                 ixgbe_irq_disable(adapter);
2341         adapter->vlgrp = grp;
2342
2343         /*
2344          * For a DCB driver, always enable VLAN tag stripping so we can
2345          * still receive traffic from a DCB-enabled host even if we're
2346          * not in DCB mode.
2347          */
2348         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2349
2350         /* Disable CFI check */
2351         ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2352
2353         /* enable VLAN tag stripping */
2354         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2355                 ctrl |= IXGBE_VLNCTRL_VME;
2356         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2357                 for (i = 0; i < adapter->num_rx_queues; i++) {
2358                         u32 ctrl;
2359                         j = adapter->rx_ring[i].reg_idx;
2360                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2361                         ctrl |= IXGBE_RXDCTL_VME;
2362                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2363                 }
2364         }
2365
2366         IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2367
2368         ixgbe_vlan_rx_add_vid(netdev, 0);
2369
2370         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2371                 ixgbe_irq_enable(adapter);
2372 }
2373
2374 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2375 {
2376         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2377
2378         if (adapter->vlgrp) {
2379                 u16 vid;
2380                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2381                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2382                                 continue;
2383                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2384                 }
2385         }
2386 }
2387
2388 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2389 {
2390         struct dev_mc_list *mc_ptr;
2391         u8 *addr = *mc_addr_ptr;
2392         *vmdq = 0;
2393
2394         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2395         if (mc_ptr->next)
2396                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2397         else
2398                 *mc_addr_ptr = NULL;
2399
2400         return addr;
2401 }
2402
2403 /**
2404  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2405  * @netdev: network interface device structure
2406  *
2407  * The set_rx_method entry point is called whenever the unicast/multicast
2408  * address list or the network interface flags are updated.  This routine is
2409  * responsible for configuring the hardware for proper unicast, multicast and
2410  * promiscuous mode.
2411  **/
2412 static void ixgbe_set_rx_mode(struct net_device *netdev)
2413 {
2414         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2415         struct ixgbe_hw *hw = &adapter->hw;
2416         u32 fctrl, vlnctrl;
2417         u8 *addr_list = NULL;
2418         int addr_count = 0;
2419
2420         /* Check for Promiscuous and All Multicast modes */
2421
2422         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2423         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2424
2425         if (netdev->flags & IFF_PROMISC) {
2426                 hw->addr_ctrl.user_set_promisc = 1;
2427                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2428                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2429         } else {
2430                 if (netdev->flags & IFF_ALLMULTI) {
2431                         fctrl |= IXGBE_FCTRL_MPE;
2432                         fctrl &= ~IXGBE_FCTRL_UPE;
2433                 } else {
2434                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2435                 }
2436                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2437                 hw->addr_ctrl.user_set_promisc = 0;
2438         }
2439
2440         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2441         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2442
2443         /* reprogram secondary unicast list */
2444         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2445
2446         /* reprogram multicast list */
2447         addr_count = netdev->mc_count;
2448         if (addr_count)
2449                 addr_list = netdev->mc_list->dmi_addr;
2450         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2451                                         ixgbe_addr_list_itr);
2452 }
2453
2454 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2455 {
2456         int q_idx;
2457         struct ixgbe_q_vector *q_vector;
2458         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2459
2460         /* legacy and MSI only use one vector */
2461         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2462                 q_vectors = 1;
2463
2464         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2465                 struct napi_struct *napi;
2466                 q_vector = adapter->q_vector[q_idx];
2467                 napi = &q_vector->napi;
2468                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2469                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2470                                 if (q_vector->txr_count == 1)
2471                                         napi->poll = &ixgbe_clean_txonly;
2472                                 else if (q_vector->rxr_count == 1)
2473                                         napi->poll = &ixgbe_clean_rxonly;
2474                         }
2475                 }
2476
2477                 napi_enable(napi);
2478         }
2479 }
2480
2481 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2482 {
2483         int q_idx;
2484         struct ixgbe_q_vector *q_vector;
2485         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2486
2487         /* legacy and MSI only use one vector */
2488         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2489                 q_vectors = 1;
2490
2491         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2492                 q_vector = adapter->q_vector[q_idx];
2493                 napi_disable(&q_vector->napi);
2494         }
2495 }
2496
2497 #ifdef CONFIG_IXGBE_DCB
2498 /*
2499  * ixgbe_configure_dcb - Configure DCB hardware
2500  * @adapter: ixgbe adapter struct
2501  *
2502  * This is called by the driver on open to configure the DCB hardware.
2503  * This is also called by the gennetlink interface when reconfiguring
2504  * the DCB state.
2505  */
2506 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2507 {
2508         struct ixgbe_hw *hw = &adapter->hw;
2509         u32 txdctl, vlnctrl;
2510         int i, j;
2511
2512         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2513         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2514         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2515
2516         /* reconfigure the hardware */
2517         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2518
2519         for (i = 0; i < adapter->num_tx_queues; i++) {
2520                 j = adapter->tx_ring[i].reg_idx;
2521                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2522                 /* PThresh workaround for Tx hang with DFP enabled. */
2523                 txdctl |= 32;
2524                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2525         }
2526         /* Enable VLAN tag insert/strip */
2527         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2528         if (hw->mac.type == ixgbe_mac_82598EB) {
2529                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2530                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2531                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2532         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2533                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2534                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2535                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2536                 for (i = 0; i < adapter->num_rx_queues; i++) {
2537                         j = adapter->rx_ring[i].reg_idx;
2538                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2539                         vlnctrl |= IXGBE_RXDCTL_VME;
2540                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2541                 }
2542         }
2543         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2544 }
2545
2546 #endif
2547 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2548 {
2549         struct net_device *netdev = adapter->netdev;
2550         struct ixgbe_hw *hw = &adapter->hw;
2551         int i;
2552
2553         ixgbe_set_rx_mode(netdev);
2554
2555         ixgbe_restore_vlan(adapter);
2556 #ifdef CONFIG_IXGBE_DCB
2557         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2558                 if (hw->mac.type == ixgbe_mac_82598EB)
2559                         netif_set_gso_max_size(netdev, 32768);
2560                 else
2561                         netif_set_gso_max_size(netdev, 65536);
2562                 ixgbe_configure_dcb(adapter);
2563         } else {
2564                 netif_set_gso_max_size(netdev, 65536);
2565         }
2566 #else
2567         netif_set_gso_max_size(netdev, 65536);
2568 #endif
2569
2570 #ifdef IXGBE_FCOE
2571         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2572                 ixgbe_configure_fcoe(adapter);
2573
2574 #endif /* IXGBE_FCOE */
2575         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2576                 for (i = 0; i < adapter->num_tx_queues; i++)
2577                         adapter->tx_ring[i].atr_sample_rate =
2578                                                        adapter->atr_sample_rate;
2579                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2580         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2581                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2582         }
2583
2584         ixgbe_configure_tx(adapter);
2585         ixgbe_configure_rx(adapter);
2586         for (i = 0; i < adapter->num_rx_queues; i++)
2587                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2588                                        (adapter->rx_ring[i].count - 1));
2589 }
2590
2591 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2592 {
2593         switch (hw->phy.type) {
2594         case ixgbe_phy_sfp_avago:
2595         case ixgbe_phy_sfp_ftl:
2596         case ixgbe_phy_sfp_intel:
2597         case ixgbe_phy_sfp_unknown:
2598         case ixgbe_phy_tw_tyco:
2599         case ixgbe_phy_tw_unknown:
2600                 return true;
2601         default:
2602                 return false;
2603         }
2604 }
2605
2606 /**
2607  * ixgbe_sfp_link_config - set up SFP+ link
2608  * @adapter: pointer to private adapter struct
2609  **/
2610 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2611 {
2612         struct ixgbe_hw *hw = &adapter->hw;
2613
2614                 if (hw->phy.multispeed_fiber) {
2615                         /*
2616                          * In multispeed fiber setups, the device may not have
2617                          * had a physical connection when the driver loaded.
2618                          * If that's the case, the initial link configuration
2619                          * couldn't get the MAC into 10G or 1G mode, so we'll
2620                          * never have a link status change interrupt fire.
2621                          * We need to try and force an autonegotiation
2622                          * session, then bring up link.
2623                          */
2624                         hw->mac.ops.setup_sfp(hw);
2625                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2626                                 schedule_work(&adapter->multispeed_fiber_task);
2627                 } else {
2628                         /*
2629                          * Direct Attach Cu and non-multispeed fiber modules
2630                          * still need to be configured properly prior to
2631                          * attempting link.
2632                          */
2633                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2634                                 schedule_work(&adapter->sfp_config_module_task);
2635                 }
2636 }
2637
2638 /**
2639  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2640  * @hw: pointer to private hardware struct
2641  *
2642  * Returns 0 on success, negative on failure
2643  **/
2644 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2645 {
2646         u32 autoneg;
2647         bool negotiation, link_up = false;
2648         u32 ret = IXGBE_ERR_LINK_SETUP;
2649
2650         if (hw->mac.ops.check_link)
2651                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2652
2653         if (ret)
2654                 goto link_cfg_out;
2655
2656         if (hw->mac.ops.get_link_capabilities)
2657                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2658         if (ret)
2659                 goto link_cfg_out;
2660
2661         if (hw->mac.ops.setup_link)
2662                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2663 link_cfg_out:
2664         return ret;
2665 }
2666
2667 #define IXGBE_MAX_RX_DESC_POLL 10
2668 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2669                                               int rxr)
2670 {
2671         int j = adapter->rx_ring[rxr].reg_idx;
2672         int k;
2673
2674         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2675                 if (IXGBE_READ_REG(&adapter->hw,
2676                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2677                         break;
2678                 else
2679                         msleep(1);
2680         }
2681         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2682                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2683                         "not set within the polling period\n", rxr);
2684         }
2685         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2686                               (adapter->rx_ring[rxr].count - 1));
2687 }
2688
2689 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2690 {
2691         struct net_device *netdev = adapter->netdev;
2692         struct ixgbe_hw *hw = &adapter->hw;
2693         int i, j = 0;
2694         int num_rx_rings = adapter->num_rx_queues;
2695         int err;
2696         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2697         u32 txdctl, rxdctl, mhadd;
2698         u32 dmatxctl;
2699         u32 gpie;
2700
2701         ixgbe_get_hw_control(adapter);
2702
2703         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2704             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2705                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2706                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2707                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2708                 } else {
2709                         /* MSI only */
2710                         gpie = 0;
2711                 }
2712                 /* XXX: to interrupt immediately for EICS writes, enable this */
2713                 /* gpie |= IXGBE_GPIE_EIMEN; */
2714                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2715         }
2716
2717         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2718                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2719                  * specifically only auto mask tx and rx interrupts */
2720                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2721         }
2722
2723         /* Enable fan failure interrupt if media type is copper */
2724         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2725                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2726                 gpie |= IXGBE_SDP1_GPIEN;
2727                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2728         }
2729
2730         if (hw->mac.type == ixgbe_mac_82599EB) {
2731                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2732                 gpie |= IXGBE_SDP1_GPIEN;
2733                 gpie |= IXGBE_SDP2_GPIEN;
2734                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2735         }
2736
2737 #ifdef IXGBE_FCOE
2738         /* adjust max frame to be able to do baby jumbo for FCoE */
2739         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2740             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2741                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2742
2743 #endif /* IXGBE_FCOE */
2744         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2745         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2746                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2747                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2748
2749                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2750         }
2751
2752         for (i = 0; i < adapter->num_tx_queues; i++) {
2753                 j = adapter->tx_ring[i].reg_idx;
2754                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2755                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2756                 txdctl |= (8 << 16);
2757                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2758         }
2759
2760         if (hw->mac.type == ixgbe_mac_82599EB) {
2761                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2762                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2763                 dmatxctl |= IXGBE_DMATXCTL_TE;
2764                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2765         }
2766         for (i = 0; i < adapter->num_tx_queues; i++) {
2767                 j = adapter->tx_ring[i].reg_idx;
2768                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2769                 txdctl |= IXGBE_TXDCTL_ENABLE;
2770                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2771         }
2772
2773         for (i = 0; i < num_rx_rings; i++) {
2774                 j = adapter->rx_ring[i].reg_idx;
2775                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2776                 /* enable PTHRESH=32 descriptors (half the internal cache)
2777                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2778                  * this also removes a pesky rx_no_buffer_count increment */
2779                 rxdctl |= 0x0020;
2780                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2781                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2782                 if (hw->mac.type == ixgbe_mac_82599EB)
2783                         ixgbe_rx_desc_queue_enable(adapter, i);
2784         }
2785         /* enable all receives */
2786         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2787         if (hw->mac.type == ixgbe_mac_82598EB)
2788                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2789         else
2790                 rxdctl |= IXGBE_RXCTRL_RXEN;
2791         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2792
2793         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2794                 ixgbe_configure_msix(adapter);
2795         else
2796                 ixgbe_configure_msi_and_legacy(adapter);
2797
2798         clear_bit(__IXGBE_DOWN, &adapter->state);
2799         ixgbe_napi_enable_all(adapter);
2800
2801         /* clear any pending interrupts, may auto mask */
2802         IXGBE_READ_REG(hw, IXGBE_EICR);
2803
2804         ixgbe_irq_enable(adapter);
2805
2806         /*
2807          * If this adapter has a fan, check to see if we had a failure
2808          * before we enabled the interrupt.
2809          */
2810         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2811                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2812                 if (esdp & IXGBE_ESDP_SDP1)
2813                         DPRINTK(DRV, CRIT,
2814                                 "Fan has stopped, replace the adapter\n");
2815         }
2816
2817         /*
2818          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2819          * arrived before interrupts were enabled but after probe.  Such
2820          * devices wouldn't have their type identified yet. We need to
2821          * kick off the SFP+ module setup first, then try to bring up link.
2822          * If we're not hot-pluggable SFP+, we just need to configure link
2823          * and bring it up.
2824          */
2825         if (hw->phy.type == ixgbe_phy_unknown) {
2826                 err = hw->phy.ops.identify(hw);
2827                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2828                         /*
2829                          * Take the device down and schedule the sfp tasklet
2830                          * which will unregister_netdev and log it.
2831                          */
2832                         ixgbe_down(adapter);
2833                         schedule_work(&adapter->sfp_config_module_task);
2834                         return err;
2835                 }
2836         }
2837
2838         if (ixgbe_is_sfp(hw)) {
2839                 ixgbe_sfp_link_config(adapter);
2840         } else {
2841                 err = ixgbe_non_sfp_link_config(hw);
2842                 if (err)
2843                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2844         }
2845
2846         for (i = 0; i < adapter->num_tx_queues; i++)
2847                 set_bit(__IXGBE_FDIR_INIT_DONE,
2848                         &(adapter->tx_ring[i].reinit_state));
2849
2850         /* enable transmits */
2851         netif_tx_start_all_queues(netdev);
2852
2853         /* bring the link up in the watchdog, this could race with our first
2854          * link up interrupt but shouldn't be a problem */
2855         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2856         adapter->link_check_timeout = jiffies;
2857         mod_timer(&adapter->watchdog_timer, jiffies);
2858         return 0;
2859 }
2860
2861 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2862 {
2863         WARN_ON(in_interrupt());
2864         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2865                 msleep(1);
2866         ixgbe_down(adapter);
2867         ixgbe_up(adapter);
2868         clear_bit(__IXGBE_RESETTING, &adapter->state);
2869 }
2870
2871 int ixgbe_up(struct ixgbe_adapter *adapter)
2872 {
2873         /* hardware has been reset, we need to reload some things */
2874         ixgbe_configure(adapter);
2875
2876         return ixgbe_up_complete(adapter);
2877 }
2878
2879 void ixgbe_reset(struct ixgbe_adapter *adapter)
2880 {
2881         struct ixgbe_hw *hw = &adapter->hw;
2882         int err;
2883
2884         err = hw->mac.ops.init_hw(hw);
2885         switch (err) {
2886         case 0:
2887         case IXGBE_ERR_SFP_NOT_PRESENT:
2888                 break;
2889         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2890                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2891                 break;
2892         case IXGBE_ERR_EEPROM_VERSION:
2893                 /* We are running on a pre-production device, log a warning */
2894                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2895                          "adapter/LOM.  Please be aware there may be issues "
2896                          "associated with your hardware.  If you are "
2897                          "experiencing problems please contact your Intel or "
2898                          "hardware representative who provided you with this "
2899                          "hardware.\n");
2900                 break;
2901         default:
2902                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2903         }
2904
2905         /* reprogram the RAR[0] in case user changed it. */
2906         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2907 }
2908
2909 /**
2910  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2911  * @adapter: board private structure
2912  * @rx_ring: ring to free buffers from
2913  **/
2914 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2915                                 struct ixgbe_ring *rx_ring)
2916 {
2917         struct pci_dev *pdev = adapter->pdev;
2918         unsigned long size;
2919         unsigned int i;
2920
2921         /* Free all the Rx ring sk_buffs */
2922
2923         for (i = 0; i < rx_ring->count; i++) {
2924                 struct ixgbe_rx_buffer *rx_buffer_info;
2925
2926                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2927                 if (rx_buffer_info->dma) {
2928                         pci_unmap_single(pdev, rx_buffer_info->dma,
2929                                          rx_ring->rx_buf_len,
2930                                          PCI_DMA_FROMDEVICE);
2931                         rx_buffer_info->dma = 0;
2932                 }
2933                 if (rx_buffer_info->skb) {
2934                         struct sk_buff *skb = rx_buffer_info->skb;
2935                         rx_buffer_info->skb = NULL;
2936                         do {
2937                                 struct sk_buff *this = skb;
2938                                 skb = skb->prev;
2939                                 dev_kfree_skb(this);
2940                         } while (skb);
2941                 }
2942                 if (!rx_buffer_info->page)
2943                         continue;
2944                 if (rx_buffer_info->page_dma) {
2945                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2946                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2947                         rx_buffer_info->page_dma = 0;
2948                 }
2949                 put_page(rx_buffer_info->page);
2950                 rx_buffer_info->page = NULL;
2951                 rx_buffer_info->page_offset = 0;
2952         }
2953
2954         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2955         memset(rx_ring->rx_buffer_info, 0, size);
2956
2957         /* Zero out the descriptor ring */
2958         memset(rx_ring->desc, 0, rx_ring->size);
2959
2960         rx_ring->next_to_clean = 0;
2961         rx_ring->next_to_use = 0;
2962
2963         if (rx_ring->head)
2964                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2965         if (rx_ring->tail)
2966                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2967 }
2968
2969 /**
2970  * ixgbe_clean_tx_ring - Free Tx Buffers
2971  * @adapter: board private structure
2972  * @tx_ring: ring to be cleaned
2973  **/
2974 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2975                                 struct ixgbe_ring *tx_ring)
2976 {
2977         struct ixgbe_tx_buffer *tx_buffer_info;
2978         unsigned long size;
2979         unsigned int i;
2980
2981         /* Free all the Tx ring sk_buffs */
2982
2983         for (i = 0; i < tx_ring->count; i++) {
2984                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2985                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2986         }
2987
2988         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2989         memset(tx_ring->tx_buffer_info, 0, size);
2990
2991         /* Zero out the descriptor ring */
2992         memset(tx_ring->desc, 0, tx_ring->size);
2993
2994         tx_ring->next_to_use = 0;
2995         tx_ring->next_to_clean = 0;
2996
2997         if (tx_ring->head)
2998                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2999         if (tx_ring->tail)
3000                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3001 }
3002
3003 /**
3004  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3005  * @adapter: board private structure
3006  **/
3007 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3008 {
3009         int i;
3010
3011         for (i = 0; i < adapter->num_rx_queues; i++)
3012                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
3013 }
3014
3015 /**
3016  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3017  * @adapter: board private structure
3018  **/
3019 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3020 {
3021         int i;
3022
3023         for (i = 0; i < adapter->num_tx_queues; i++)
3024                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
3025 }
3026
3027 void ixgbe_down(struct ixgbe_adapter *adapter)
3028 {
3029         struct net_device *netdev = adapter->netdev;
3030         struct ixgbe_hw *hw = &adapter->hw;
3031         u32 rxctrl;
3032         u32 txdctl;
3033         int i, j;
3034
3035         /* signal that we are down to the interrupt handler */
3036         set_bit(__IXGBE_DOWN, &adapter->state);
3037
3038         /* disable receives */
3039         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3040         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3041
3042         netif_tx_disable(netdev);
3043
3044         IXGBE_WRITE_FLUSH(hw);
3045         msleep(10);
3046
3047         netif_tx_stop_all_queues(netdev);
3048
3049         ixgbe_irq_disable(adapter);
3050
3051         ixgbe_napi_disable_all(adapter);
3052
3053         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3054         del_timer_sync(&adapter->sfp_timer);
3055         del_timer_sync(&adapter->watchdog_timer);
3056         cancel_work_sync(&adapter->watchdog_task);
3057
3058         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3059             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3060                 cancel_work_sync(&adapter->fdir_reinit_task);
3061
3062         /* disable transmits in the hardware now that interrupts are off */
3063         for (i = 0; i < adapter->num_tx_queues; i++) {
3064                 j = adapter->tx_ring[i].reg_idx;
3065                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3066                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3067                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3068         }
3069         /* Disable the Tx DMA engine on 82599 */
3070         if (hw->mac.type == ixgbe_mac_82599EB)
3071                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3072                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3073                                  ~IXGBE_DMATXCTL_TE));
3074
3075         netif_carrier_off(netdev);
3076
3077         if (!pci_channel_offline(adapter->pdev))
3078                 ixgbe_reset(adapter);
3079         ixgbe_clean_all_tx_rings(adapter);
3080         ixgbe_clean_all_rx_rings(adapter);
3081
3082 #ifdef CONFIG_IXGBE_DCA
3083         /* since we reset the hardware DCA settings were cleared */
3084         ixgbe_setup_dca(adapter);
3085 #endif
3086 }
3087
3088 /**
3089  * ixgbe_poll - NAPI Rx polling callback
3090  * @napi: structure for representing this polling device
3091  * @budget: how many packets driver is allowed to clean
3092  *
3093  * This function is used for legacy and MSI, NAPI mode
3094  **/
3095 static int ixgbe_poll(struct napi_struct *napi, int budget)
3096 {
3097         struct ixgbe_q_vector *q_vector =
3098                                 container_of(napi, struct ixgbe_q_vector, napi);
3099         struct ixgbe_adapter *adapter = q_vector->adapter;
3100         int tx_clean_complete, work_done = 0;
3101
3102 #ifdef CONFIG_IXGBE_DCA
3103         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3104                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3105                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3106         }
3107 #endif
3108
3109         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3110         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3111
3112         if (!tx_clean_complete)
3113                 work_done = budget;
3114
3115         /* If budget not fully consumed, exit the polling mode */
3116         if (work_done < budget) {
3117                 napi_complete(napi);
3118                 if (adapter->rx_itr_setting & 1)
3119                         ixgbe_set_itr(adapter);
3120                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3121                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3122         }
3123         return work_done;
3124 }
3125
3126 /**
3127  * ixgbe_tx_timeout - Respond to a Tx Hang
3128  * @netdev: network interface device structure
3129  **/
3130 static void ixgbe_tx_timeout(struct net_device *netdev)
3131 {
3132         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3133
3134         /* Do the reset outside of interrupt context */
3135         schedule_work(&adapter->reset_task);
3136 }
3137
3138 static void ixgbe_reset_task(struct work_struct *work)
3139 {
3140         struct ixgbe_adapter *adapter;
3141         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3142
3143         /* If we're already down or resetting, just bail */
3144         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3145             test_bit(__IXGBE_RESETTING, &adapter->state))
3146                 return;
3147
3148         adapter->tx_timeout_count++;
3149
3150         ixgbe_reinit_locked(adapter);
3151 }
3152
3153 #ifdef CONFIG_IXGBE_DCB
3154 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3155 {
3156         bool ret = false;
3157         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3158
3159         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3160                 return ret;
3161
3162         f->mask = 0x7 << 3;
3163         adapter->num_rx_queues = f->indices;
3164         adapter->num_tx_queues = f->indices;
3165         ret = true;
3166
3167         return ret;
3168 }
3169 #endif
3170
3171 /**
3172  * ixgbe_set_rss_queues: Allocate queues for RSS
3173  * @adapter: board private structure to initialize
3174  *
3175  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3176  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3177  *
3178  **/
3179 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3180 {
3181         bool ret = false;
3182         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3183
3184         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3185                 f->mask = 0xF;
3186                 adapter->num_rx_queues = f->indices;
3187                 adapter->num_tx_queues = f->indices;
3188                 ret = true;
3189         } else {
3190                 ret = false;
3191         }
3192
3193         return ret;
3194 }
3195
3196 /**
3197  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3198  * @adapter: board private structure to initialize
3199  *
3200  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3201  * to the original CPU that initiated the Tx session.  This runs in addition
3202  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3203  * Rx load across CPUs using RSS.
3204  *
3205  **/
3206 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3207 {
3208         bool ret = false;
3209         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3210
3211         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3212         f_fdir->mask = 0;
3213
3214         /* Flow Director must have RSS enabled */
3215         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3216             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3217              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3218                 adapter->num_tx_queues = f_fdir->indices;
3219                 adapter->num_rx_queues = f_fdir->indices;
3220                 ret = true;
3221         } else {
3222                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3223                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3224         }
3225         return ret;
3226 }
3227
3228 #ifdef IXGBE_FCOE
3229 /**
3230  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3231  * @adapter: board private structure to initialize
3232  *
3233  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3234  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3235  * rx queues out of the max number of rx queues, instead, it is used as the
3236  * index of the first rx queue used by FCoE.
3237  *
3238  **/
3239 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3240 {
3241         bool ret = false;
3242         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3243
3244         f->indices = min((int)num_online_cpus(), f->indices);
3245         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3246                 adapter->num_rx_queues = 1;
3247                 adapter->num_tx_queues = 1;
3248 #ifdef CONFIG_IXGBE_DCB
3249                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3250                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3251                         ixgbe_set_dcb_queues(adapter);
3252                 }
3253 #endif
3254                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3255                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3256                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3257                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3258                                 ixgbe_set_fdir_queues(adapter);
3259                         else
3260                                 ixgbe_set_rss_queues(adapter);
3261                 }
3262                 /* adding FCoE rx rings to the end */
3263                 f->mask = adapter->num_rx_queues;
3264                 adapter->num_rx_queues += f->indices;
3265                 adapter->num_tx_queues += f->indices;
3266
3267                 ret = true;
3268         }
3269
3270         return ret;
3271 }
3272
3273 #endif /* IXGBE_FCOE */
3274 /*
3275  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3276  * @adapter: board private structure to initialize
3277  *
3278  * This is the top level queue allocation routine.  The order here is very
3279  * important, starting with the "most" number of features turned on at once,
3280  * and ending with the smallest set of features.  This way large combinations
3281  * can be allocated if they're turned on, and smaller combinations are the
3282  * fallthrough conditions.
3283  *
3284  **/
3285 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3286 {
3287 #ifdef IXGBE_FCOE
3288         if (ixgbe_set_fcoe_queues(adapter))
3289                 goto done;
3290
3291 #endif /* IXGBE_FCOE */
3292 #ifdef CONFIG_IXGBE_DCB
3293         if (ixgbe_set_dcb_queues(adapter))
3294                 goto done;
3295
3296 #endif
3297         if (ixgbe_set_fdir_queues(adapter))
3298                 goto done;
3299
3300         if (ixgbe_set_rss_queues(adapter))
3301                 goto done;
3302
3303         /* fallback to base case */
3304         adapter->num_rx_queues = 1;
3305         adapter->num_tx_queues = 1;
3306
3307 done:
3308         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3309         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3310 }
3311
3312 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3313                                        int vectors)
3314 {
3315         int err, vector_threshold;
3316
3317         /* We'll want at least 3 (vector_threshold):
3318          * 1) TxQ[0] Cleanup
3319          * 2) RxQ[0] Cleanup
3320          * 3) Other (Link Status Change, etc.)
3321          * 4) TCP Timer (optional)
3322          */
3323         vector_threshold = MIN_MSIX_COUNT;
3324
3325         /* The more we get, the more we will assign to Tx/Rx Cleanup
3326          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3327          * Right now, we simply care about how many we'll get; we'll
3328          * set them up later while requesting irq's.
3329          */
3330         while (vectors >= vector_threshold) {
3331                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3332                                       vectors);
3333                 if (!err) /* Success in acquiring all requested vectors. */
3334                         break;
3335                 else if (err < 0)
3336                         vectors = 0; /* Nasty failure, quit now */
3337                 else /* err == number of vectors we should try again with */
3338                         vectors = err;
3339         }
3340
3341         if (vectors < vector_threshold) {
3342                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3343                  * This just means we'll go with either a single MSI
3344                  * vector or fall back to legacy interrupts.
3345                  */
3346                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3347                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3348                 kfree(adapter->msix_entries);
3349                 adapter->msix_entries = NULL;
3350         } else {
3351                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3352                 /*
3353                  * Adjust for only the vectors we'll use, which is minimum
3354                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3355                  * vectors we were allocated.
3356                  */
3357                 adapter->num_msix_vectors = min(vectors,
3358                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3359         }
3360 }
3361
3362 /**
3363  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3364  * @adapter: board private structure to initialize
3365  *
3366  * Cache the descriptor ring offsets for RSS to the assigned rings.
3367  *
3368  **/
3369 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3370 {
3371         int i;
3372         bool ret = false;
3373
3374         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3375                 for (i = 0; i < adapter->num_rx_queues; i++)
3376                         adapter->rx_ring[i].reg_idx = i;
3377                 for (i = 0; i < adapter->num_tx_queues; i++)
3378                         adapter->tx_ring[i].reg_idx = i;
3379                 ret = true;
3380         } else {
3381                 ret = false;
3382         }
3383
3384         return ret;
3385 }
3386
3387 #ifdef CONFIG_IXGBE_DCB
3388 /**
3389  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3390  * @adapter: board private structure to initialize
3391  *
3392  * Cache the descriptor ring offsets for DCB to the assigned rings.
3393  *
3394  **/
3395 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3396 {
3397         int i;
3398         bool ret = false;
3399         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3400
3401         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3402                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3403                         /* the number of queues is assumed to be symmetric */
3404                         for (i = 0; i < dcb_i; i++) {
3405                                 adapter->rx_ring[i].reg_idx = i << 3;
3406                                 adapter->tx_ring[i].reg_idx = i << 2;
3407                         }
3408                         ret = true;
3409                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3410                         if (dcb_i == 8) {
3411                                 /*
3412                                  * Tx TC0 starts at: descriptor queue 0
3413                                  * Tx TC1 starts at: descriptor queue 32
3414                                  * Tx TC2 starts at: descriptor queue 64
3415                                  * Tx TC3 starts at: descriptor queue 80
3416                                  * Tx TC4 starts at: descriptor queue 96
3417                                  * Tx TC5 starts at: descriptor queue 104
3418                                  * Tx TC6 starts at: descriptor queue 112
3419                                  * Tx TC7 starts at: descriptor queue 120
3420                                  *
3421                                  * Rx TC0-TC7 are offset by 16 queues each
3422                                  */
3423                                 for (i = 0; i < 3; i++) {
3424                                         adapter->tx_ring[i].reg_idx = i << 5;
3425                                         adapter->rx_ring[i].reg_idx = i << 4;
3426                                 }
3427                                 for ( ; i < 5; i++) {
3428                                         adapter->tx_ring[i].reg_idx =
3429                                                                  ((i + 2) << 4);
3430                                         adapter->rx_ring[i].reg_idx = i << 4;
3431                                 }
3432                                 for ( ; i < dcb_i; i++) {
3433                                         adapter->tx_ring[i].reg_idx =
3434                                                                  ((i + 8) << 3);
3435                                         adapter->rx_ring[i].reg_idx = i << 4;
3436                                 }
3437
3438                                 ret = true;
3439                         } else if (dcb_i == 4) {
3440                                 /*
3441                                  * Tx TC0 starts at: descriptor queue 0
3442                                  * Tx TC1 starts at: descriptor queue 64
3443                                  * Tx TC2 starts at: descriptor queue 96
3444                                  * Tx TC3 starts at: descriptor queue 112
3445                                  *
3446                                  * Rx TC0-TC3 are offset by 32 queues each
3447                                  */
3448                                 adapter->tx_ring[0].reg_idx = 0;
3449                                 adapter->tx_ring[1].reg_idx = 64;
3450                                 adapter->tx_ring[2].reg_idx = 96;
3451                                 adapter->tx_ring[3].reg_idx = 112;
3452                                 for (i = 0 ; i < dcb_i; i++)
3453                                         adapter->rx_ring[i].reg_idx = i << 5;
3454
3455                                 ret = true;
3456                         } else {
3457                                 ret = false;
3458                         }
3459                 } else {
3460                         ret = false;
3461                 }
3462         } else {
3463                 ret = false;
3464         }
3465
3466         return ret;
3467 }
3468 #endif
3469
3470 /**
3471  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3472  * @adapter: board private structure to initialize
3473  *
3474  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3475  *
3476  **/
3477 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3478 {
3479         int i;
3480         bool ret = false;
3481
3482         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3483             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3484              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3485                 for (i = 0; i < adapter->num_rx_queues; i++)
3486                         adapter->rx_ring[i].reg_idx = i;
3487                 for (i = 0; i < adapter->num_tx_queues; i++)
3488                         adapter->tx_ring[i].reg_idx = i;
3489                 ret = true;
3490         }
3491
3492         return ret;
3493 }
3494
3495 #ifdef IXGBE_FCOE
3496 /**
3497  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3498  * @adapter: board private structure to initialize
3499  *
3500  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3501  *
3502  */
3503 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3504 {
3505         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3506         bool ret = false;
3507         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3508
3509         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3510 #ifdef CONFIG_IXGBE_DCB
3511                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3512                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3513
3514                         ixgbe_cache_ring_dcb(adapter);
3515                         /* find out queues in TC for FCoE */
3516                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3517                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3518                         /*
3519                          * In 82599, the number of Tx queues for each traffic
3520                          * class for both 8-TC and 4-TC modes are:
3521                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3522                          * 8 TCs:  32  32  16  16   8   8   8   8
3523                          * 4 TCs:  64  64  32  32
3524                          * We have max 8 queues for FCoE, where 8 the is
3525                          * FCoE redirection table size. If TC for FCoE is
3526                          * less than or equal to TC3, we have enough queues
3527                          * to add max of 8 queues for FCoE, so we start FCoE
3528                          * tx descriptor from the next one, i.e., reg_idx + 1.
3529                          * If TC for FCoE is above TC3, implying 8 TC mode,
3530                          * and we need 8 for FCoE, we have to take all queues
3531                          * in that traffic class for FCoE.
3532                          */
3533                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3534                                 fcoe_tx_i--;
3535                 }
3536 #endif /* CONFIG_IXGBE_DCB */
3537                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3538                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3539                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3540                                 ixgbe_cache_ring_fdir(adapter);
3541                         else
3542                                 ixgbe_cache_ring_rss(adapter);
3543
3544                         fcoe_rx_i = f->mask;
3545                         fcoe_tx_i = f->mask;
3546                 }
3547                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3548                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3549                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3550                 }
3551                 ret = true;
3552         }
3553         return ret;
3554 }
3555
3556 #endif /* IXGBE_FCOE */
3557 /**
3558  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3559  * @adapter: board private structure to initialize
3560  *
3561  * Once we know the feature-set enabled for the device, we'll cache
3562  * the register offset the descriptor ring is assigned to.
3563  *
3564  * Note, the order the various feature calls is important.  It must start with
3565  * the "most" features enabled at the same time, then trickle down to the
3566  * least amount of features turned on at once.
3567  **/
3568 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3569 {
3570         /* start with default case */
3571         adapter->rx_ring[0].reg_idx = 0;
3572         adapter->tx_ring[0].reg_idx = 0;
3573
3574 #ifdef IXGBE_FCOE
3575         if (ixgbe_cache_ring_fcoe(adapter))
3576                 return;
3577
3578 #endif /* IXGBE_FCOE */
3579 #ifdef CONFIG_IXGBE_DCB
3580         if (ixgbe_cache_ring_dcb(adapter))
3581                 return;
3582
3583 #endif
3584         if (ixgbe_cache_ring_fdir(adapter))
3585                 return;
3586
3587         if (ixgbe_cache_ring_rss(adapter))
3588                 return;
3589 }
3590
3591 /**
3592  * ixgbe_alloc_queues - Allocate memory for all rings
3593  * @adapter: board private structure to initialize
3594  *
3595  * We allocate one ring per queue at run-time since we don't know the
3596  * number of queues at compile-time.  The polling_netdev array is
3597  * intended for Multiqueue, but should work fine with a single queue.
3598  **/
3599 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3600 {
3601         int i;
3602
3603         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3604                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3605         if (!adapter->tx_ring)
3606                 goto err_tx_ring_allocation;
3607
3608         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3609                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3610         if (!adapter->rx_ring)
3611                 goto err_rx_ring_allocation;
3612
3613         for (i = 0; i < adapter->num_tx_queues; i++) {
3614                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3615                 adapter->tx_ring[i].queue_index = i;
3616         }
3617
3618         for (i = 0; i < adapter->num_rx_queues; i++) {
3619                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3620                 adapter->rx_ring[i].queue_index = i;
3621         }
3622
3623         ixgbe_cache_ring_register(adapter);
3624
3625         return 0;
3626
3627 err_rx_ring_allocation:
3628         kfree(adapter->tx_ring);
3629 err_tx_ring_allocation:
3630         return -ENOMEM;
3631 }
3632
3633 /**
3634  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3635  * @adapter: board private structure to initialize
3636  *
3637  * Attempt to configure the interrupts using the best available
3638  * capabilities of the hardware and the kernel.
3639  **/
3640 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3641 {
3642         struct ixgbe_hw *hw = &adapter->hw;
3643         int err = 0;
3644         int vector, v_budget;
3645
3646         /*
3647          * It's easy to be greedy for MSI-X vectors, but it really
3648          * doesn't do us much good if we have a lot more vectors
3649          * than CPU's.  So let's be conservative and only ask for
3650          * (roughly) the same number of vectors as there are CPU's.
3651          */
3652         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3653                        (int)num_online_cpus()) + NON_Q_VECTORS;
3654
3655         /*
3656          * At the same time, hardware can only support a maximum of
3657          * hw.mac->max_msix_vectors vectors.  With features
3658          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3659          * descriptor queues supported by our device.  Thus, we cap it off in
3660          * those rare cases where the cpu count also exceeds our vector limit.
3661          */
3662         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3663
3664         /* A failure in MSI-X entry allocation isn't fatal, but it does
3665          * mean we disable MSI-X capabilities of the adapter. */
3666         adapter->msix_entries = kcalloc(v_budget,
3667                                         sizeof(struct msix_entry), GFP_KERNEL);
3668         if (adapter->msix_entries) {
3669                 for (vector = 0; vector < v_budget; vector++)
3670                         adapter->msix_entries[vector].entry = vector;
3671
3672                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3673
3674                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3675                         goto out;
3676         }
3677
3678         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3679         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3680         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3681         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3682         adapter->atr_sample_rate = 0;
3683         ixgbe_set_num_queues(adapter);
3684
3685         err = pci_enable_msi(adapter->pdev);
3686         if (!err) {
3687                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3688         } else {
3689                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3690                         "falling back to legacy.  Error: %d\n", err);
3691                 /* reset err */
3692                 err = 0;
3693         }
3694
3695 out:
3696         return err;
3697 }
3698
3699 /**
3700  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3701  * @adapter: board private structure to initialize
3702  *
3703  * We allocate one q_vector per queue interrupt.  If allocation fails we
3704  * return -ENOMEM.
3705  **/
3706 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3707 {
3708         int q_idx, num_q_vectors;
3709         struct ixgbe_q_vector *q_vector;
3710         int napi_vectors;
3711         int (*poll)(struct napi_struct *, int);
3712
3713         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3714                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3715                 napi_vectors = adapter->num_rx_queues;
3716                 poll = &ixgbe_clean_rxtx_many;
3717         } else {
3718                 num_q_vectors = 1;
3719                 napi_vectors = 1;
3720                 poll = &ixgbe_poll;
3721         }
3722
3723         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3724                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3725                 if (!q_vector)
3726                         goto err_out;
3727                 q_vector->adapter = adapter;
3728                 if (q_vector->txr_count && !q_vector->rxr_count)
3729                         q_vector->eitr = adapter->tx_eitr_param;
3730                 else
3731                         q_vector->eitr = adapter->rx_eitr_param;
3732                 q_vector->v_idx = q_idx;
3733                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3734                 adapter->q_vector[q_idx] = q_vector;
3735         }
3736
3737         return 0;
3738
3739 err_out:
3740         while (q_idx) {
3741                 q_idx--;
3742                 q_vector = adapter->q_vector[q_idx];
3743                 netif_napi_del(&q_vector->napi);
3744                 kfree(q_vector);
3745                 adapter->q_vector[q_idx] = NULL;
3746         }
3747         return -ENOMEM;
3748 }
3749
3750 /**
3751  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3752  * @adapter: board private structure to initialize
3753  *
3754  * This function frees the memory allocated to the q_vectors.  In addition if
3755  * NAPI is enabled it will delete any references to the NAPI struct prior
3756  * to freeing the q_vector.
3757  **/
3758 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3759 {
3760         int q_idx, num_q_vectors;
3761
3762         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3763                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3764         else
3765                 num_q_vectors = 1;
3766
3767         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3768                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3769                 adapter->q_vector[q_idx] = NULL;
3770                 netif_napi_del(&q_vector->napi);
3771                 kfree(q_vector);
3772         }
3773 }
3774
3775 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3776 {
3777         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3778                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3779                 pci_disable_msix(adapter->pdev);
3780                 kfree(adapter->msix_entries);
3781                 adapter->msix_entries = NULL;
3782         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3783                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3784                 pci_disable_msi(adapter->pdev);
3785         }
3786         return;
3787 }
3788
3789 /**
3790  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3791  * @adapter: board private structure to initialize
3792  *
3793  * We determine which interrupt scheme to use based on...
3794  * - Kernel support (MSI, MSI-X)
3795  *   - which can be user-defined (via MODULE_PARAM)
3796  * - Hardware queue count (num_*_queues)
3797  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3798  **/
3799 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3800 {
3801         int err;
3802
3803         /* Number of supported queues */
3804         ixgbe_set_num_queues(adapter);
3805
3806         err = ixgbe_set_interrupt_capability(adapter);
3807         if (err) {
3808                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3809                 goto err_set_interrupt;
3810         }
3811
3812         err = ixgbe_alloc_q_vectors(adapter);
3813         if (err) {
3814                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3815                         "vectors\n");
3816                 goto err_alloc_q_vectors;
3817         }
3818
3819         err = ixgbe_alloc_queues(adapter);
3820         if (err) {
3821                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3822                 goto err_alloc_queues;
3823         }
3824
3825         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3826                 "Tx Queue count = %u\n",
3827                 (adapter->num_rx_queues > 1) ? "Enabled" :
3828                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3829
3830         set_bit(__IXGBE_DOWN, &adapter->state);
3831
3832         return 0;
3833
3834 err_alloc_queues:
3835         ixgbe_free_q_vectors(adapter);
3836 err_alloc_q_vectors:
3837         ixgbe_reset_interrupt_capability(adapter);
3838 err_set_interrupt:
3839         return err;
3840 }
3841
3842 /**
3843  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3844  * @adapter: board private structure to clear interrupt scheme on
3845  *
3846  * We go through and clear interrupt specific resources and reset the structure
3847  * to pre-load conditions
3848  **/
3849 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3850 {
3851         kfree(adapter->tx_ring);
3852         kfree(adapter->rx_ring);
3853         adapter->tx_ring = NULL;
3854         adapter->rx_ring = NULL;
3855
3856         ixgbe_free_q_vectors(adapter);
3857         ixgbe_reset_interrupt_capability(adapter);
3858 }
3859
3860 /**
3861  * ixgbe_sfp_timer - worker thread to find a missing module
3862  * @data: pointer to our adapter struct
3863  **/
3864 static void ixgbe_sfp_timer(unsigned long data)
3865 {
3866         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3867
3868         /*
3869          * Do the sfp_timer outside of interrupt context due to the
3870          * delays that sfp+ detection requires
3871          */
3872         schedule_work(&adapter->sfp_task);
3873 }
3874
3875 /**
3876  * ixgbe_sfp_task - worker thread to find a missing module
3877  * @work: pointer to work_struct containing our data
3878  **/
3879 static void ixgbe_sfp_task(struct work_struct *work)
3880 {
3881         struct ixgbe_adapter *adapter = container_of(work,
3882                                                      struct ixgbe_adapter,
3883                                                      sfp_task);
3884         struct ixgbe_hw *hw = &adapter->hw;
3885
3886         if ((hw->phy.type == ixgbe_phy_nl) &&
3887             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3888                 s32 ret = hw->phy.ops.identify_sfp(hw);
3889                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3890                         goto reschedule;
3891                 ret = hw->phy.ops.reset(hw);
3892                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3893                         dev_err(&adapter->pdev->dev, "failed to initialize "
3894                                 "because an unsupported SFP+ module type "
3895                                 "was detected.\n"
3896                                 "Reload the driver after installing a "
3897                                 "supported module.\n");
3898                         unregister_netdev(adapter->netdev);
3899                 } else {
3900                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3901                                 hw->phy.sfp_type);
3902                 }
3903                 /* don't need this routine any more */
3904                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3905         }
3906         return;
3907 reschedule:
3908         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3909                 mod_timer(&adapter->sfp_timer,
3910                           round_jiffies(jiffies + (2 * HZ)));
3911 }
3912
3913 /**
3914  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3915  * @adapter: board private structure to initialize
3916  *
3917  * ixgbe_sw_init initializes the Adapter private data structure.
3918  * Fields are initialized based on PCI device information and
3919  * OS network device settings (MTU size).
3920  **/
3921 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3922 {
3923         struct ixgbe_hw *hw = &adapter->hw;
3924         struct pci_dev *pdev = adapter->pdev;
3925         unsigned int rss;
3926 #ifdef CONFIG_IXGBE_DCB
3927         int j;
3928         struct tc_configuration *tc;
3929 #endif
3930
3931         /* PCI config space info */
3932
3933         hw->vendor_id = pdev->vendor;
3934         hw->device_id = pdev->device;
3935         hw->revision_id = pdev->revision;
3936         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3937         hw->subsystem_device_id = pdev->subsystem_device;
3938
3939         /* Set capability flags */
3940         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3941         adapter->ring_feature[RING_F_RSS].indices = rss;
3942         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3943         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3944         if (hw->mac.type == ixgbe_mac_82598EB) {
3945                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3946                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3947                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3948         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3949                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3950                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3951                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3952                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3953                 adapter->ring_feature[RING_F_FDIR].indices =
3954                                                          IXGBE_MAX_FDIR_INDICES;
3955                 adapter->atr_sample_rate = 20;
3956                 adapter->fdir_pballoc = 0;
3957 #ifdef IXGBE_FCOE
3958                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3959                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3960                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3961 #ifdef CONFIG_IXGBE_DCB
3962                 /* Default traffic class to use for FCoE */
3963                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3964 #endif
3965 #endif /* IXGBE_FCOE */
3966         }
3967
3968 #ifdef CONFIG_IXGBE_DCB
3969         /* Configure DCB traffic classes */
3970         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3971                 tc = &adapter->dcb_cfg.tc_config[j];
3972                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3973                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3974                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3975                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3976                 tc->dcb_pfc = pfc_disabled;
3977         }
3978         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3979         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3980         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3981         adapter->dcb_cfg.pfc_mode_enable = false;
3982         adapter->dcb_cfg.round_robin_enable = false;
3983         adapter->dcb_set_bitmap = 0x00;
3984         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3985                            adapter->ring_feature[RING_F_DCB].indices);
3986
3987 #endif
3988
3989         /* default flow control settings */
3990         hw->fc.requested_mode = ixgbe_fc_full;
3991         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3992 #ifdef CONFIG_DCB
3993         adapter->last_lfc_mode = hw->fc.current_mode;
3994 #endif
3995         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3996         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3997         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3998         hw->fc.send_xon = true;
3999         hw->fc.disable_fc_autoneg = false;
4000
4001         /* enable itr by default in dynamic mode */
4002         adapter->rx_itr_setting = 1;
4003         adapter->rx_eitr_param = 20000;
4004         adapter->tx_itr_setting = 1;
4005         adapter->tx_eitr_param = 10000;
4006
4007         /* set defaults for eitr in MegaBytes */
4008         adapter->eitr_low = 10;
4009         adapter->eitr_high = 20;
4010
4011         /* set default ring sizes */
4012         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4013         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4014
4015         /* initialize eeprom parameters */
4016         if (ixgbe_init_eeprom_params_generic(hw)) {
4017                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
4018                 return -EIO;
4019         }
4020
4021         /* enable rx csum by default */
4022         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4023
4024         set_bit(__IXGBE_DOWN, &adapter->state);
4025
4026         return 0;
4027 }
4028
4029 /**
4030  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4031  * @adapter: board private structure
4032  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4033  *
4034  * Return 0 on success, negative on failure
4035  **/
4036 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4037                              struct ixgbe_ring *tx_ring)
4038 {
4039         struct pci_dev *pdev = adapter->pdev;
4040         int size;
4041
4042         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4043         tx_ring->tx_buffer_info = vmalloc(size);
4044         if (!tx_ring->tx_buffer_info)
4045                 goto err;
4046         memset(tx_ring->tx_buffer_info, 0, size);
4047
4048         /* round up to nearest 4K */
4049         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4050         tx_ring->size = ALIGN(tx_ring->size, 4096);
4051
4052         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
4053                                              &tx_ring->dma);
4054         if (!tx_ring->desc)
4055                 goto err;
4056
4057         tx_ring->next_to_use = 0;
4058         tx_ring->next_to_clean = 0;
4059         tx_ring->work_limit = tx_ring->count;
4060         return 0;
4061
4062 err:
4063         vfree(tx_ring->tx_buffer_info);
4064         tx_ring->tx_buffer_info = NULL;
4065         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
4066                             "descriptor ring\n");
4067         return -ENOMEM;
4068 }
4069
4070 /**
4071  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4072  * @adapter: board private structure
4073  *
4074  * If this function returns with an error, then it's possible one or
4075  * more of the rings is populated (while the rest are not).  It is the
4076  * callers duty to clean those orphaned rings.
4077  *
4078  * Return 0 on success, negative on failure
4079  **/
4080 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4081 {
4082         int i, err = 0;
4083
4084         for (i = 0; i < adapter->num_tx_queues; i++) {
4085                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4086                 if (!err)
4087                         continue;
4088                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4089                 break;
4090         }
4091
4092         return err;
4093 }
4094
4095 /**
4096  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4097  * @adapter: board private structure
4098  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4099  *
4100  * Returns 0 on success, negative on failure
4101  **/
4102 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4103                              struct ixgbe_ring *rx_ring)
4104 {
4105         struct pci_dev *pdev = adapter->pdev;
4106         int size;
4107
4108         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4109         rx_ring->rx_buffer_info = vmalloc(size);
4110         if (!rx_ring->rx_buffer_info) {
4111                 DPRINTK(PROBE, ERR,
4112                         "vmalloc allocation failed for the rx desc ring\n");
4113                 goto alloc_failed;
4114         }
4115         memset(rx_ring->rx_buffer_info, 0, size);
4116
4117         /* Round up to nearest 4K */
4118         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4119         rx_ring->size = ALIGN(rx_ring->size, 4096);
4120
4121         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4122
4123         if (!rx_ring->desc) {
4124                 DPRINTK(PROBE, ERR,
4125                         "Memory allocation failed for the rx desc ring\n");
4126                 vfree(rx_ring->rx_buffer_info);
4127                 goto alloc_failed;
4128         }
4129
4130         rx_ring->next_to_clean = 0;
4131         rx_ring->next_to_use = 0;
4132
4133         return 0;
4134
4135 alloc_failed:
4136         return -ENOMEM;
4137 }
4138
4139 /**
4140  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4141  * @adapter: board private structure
4142  *
4143  * If this function returns with an error, then it's possible one or
4144  * more of the rings is populated (while the rest are not).  It is the
4145  * callers duty to clean those orphaned rings.
4146  *
4147  * Return 0 on success, negative on failure
4148  **/
4149
4150 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4151 {
4152         int i, err = 0;
4153
4154         for (i = 0; i < adapter->num_rx_queues; i++) {
4155                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4156                 if (!err)
4157                         continue;
4158                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4159                 break;
4160         }
4161
4162         return err;
4163 }
4164
4165 /**
4166  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4167  * @adapter: board private structure
4168  * @tx_ring: Tx descriptor ring for a specific queue
4169  *
4170  * Free all transmit software resources
4171  **/
4172 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4173                              struct ixgbe_ring *tx_ring)
4174 {
4175         struct pci_dev *pdev = adapter->pdev;
4176
4177         ixgbe_clean_tx_ring(adapter, tx_ring);
4178
4179         vfree(tx_ring->tx_buffer_info);
4180         tx_ring->tx_buffer_info = NULL;
4181
4182         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4183
4184         tx_ring->desc = NULL;
4185 }
4186
4187 /**
4188  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4189  * @adapter: board private structure
4190  *
4191  * Free all transmit software resources
4192  **/
4193 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4194 {
4195         int i;
4196
4197         for (i = 0; i < adapter->num_tx_queues; i++)
4198                 if (adapter->tx_ring[i].desc)
4199                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4200 }
4201
4202 /**
4203  * ixgbe_free_rx_resources - Free Rx Resources
4204  * @adapter: board private structure
4205  * @rx_ring: ring to clean the resources from
4206  *
4207  * Free all receive software resources
4208  **/
4209 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4210                              struct ixgbe_ring *rx_ring)
4211 {
4212         struct pci_dev *pdev = adapter->pdev;
4213
4214         ixgbe_clean_rx_ring(adapter, rx_ring);
4215
4216         vfree(rx_ring->rx_buffer_info);
4217         rx_ring->rx_buffer_info = NULL;
4218
4219         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4220
4221         rx_ring->desc = NULL;
4222 }
4223
4224 /**
4225  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4226  * @adapter: board private structure
4227  *
4228  * Free all receive software resources
4229  **/
4230 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4231 {
4232         int i;
4233
4234         for (i = 0; i < adapter->num_rx_queues; i++)
4235                 if (adapter->rx_ring[i].desc)
4236                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4237 }
4238
4239 /**
4240  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4241  * @netdev: network interface device structure
4242  * @new_mtu: new value for maximum frame size
4243  *
4244  * Returns 0 on success, negative on failure
4245  **/
4246 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4247 {
4248         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4249         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4250
4251         /* MTU < 68 is an error and causes problems on some kernels */
4252         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4253                 return -EINVAL;
4254
4255         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4256                 netdev->mtu, new_mtu);
4257         /* must set new MTU before calling down or up */
4258         netdev->mtu = new_mtu;
4259
4260         if (netif_running(netdev))
4261                 ixgbe_reinit_locked(adapter);
4262
4263         return 0;
4264 }
4265
4266 /**
4267  * ixgbe_open - Called when a network interface is made active
4268  * @netdev: network interface device structure
4269  *
4270  * Returns 0 on success, negative value on failure
4271  *
4272  * The open entry point is called when a network interface is made
4273  * active by the system (IFF_UP).  At this point all resources needed
4274  * for transmit and receive operations are allocated, the interrupt
4275  * handler is registered with the OS, the watchdog timer is started,
4276  * and the stack is notified that the interface is ready.
4277  **/
4278 static int ixgbe_open(struct net_device *netdev)
4279 {
4280         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4281         int err;
4282
4283         /* disallow open during test */
4284         if (test_bit(__IXGBE_TESTING, &adapter->state))
4285                 return -EBUSY;
4286
4287         netif_carrier_off(netdev);
4288
4289         /* allocate transmit descriptors */
4290         err = ixgbe_setup_all_tx_resources(adapter);
4291         if (err)
4292                 goto err_setup_tx;
4293
4294         /* allocate receive descriptors */
4295         err = ixgbe_setup_all_rx_resources(adapter);
4296         if (err)
4297                 goto err_setup_rx;
4298
4299         ixgbe_configure(adapter);
4300
4301         err = ixgbe_request_irq(adapter);
4302         if (err)
4303                 goto err_req_irq;
4304
4305         err = ixgbe_up_complete(adapter);
4306         if (err)
4307                 goto err_up;
4308
4309         netif_tx_start_all_queues(netdev);
4310
4311         return 0;
4312
4313 err_up:
4314         ixgbe_release_hw_control(adapter);
4315         ixgbe_free_irq(adapter);
4316 err_req_irq:
4317 err_setup_rx:
4318         ixgbe_free_all_rx_resources(adapter);
4319 err_setup_tx:
4320         ixgbe_free_all_tx_resources(adapter);
4321         ixgbe_reset(adapter);
4322
4323         return err;
4324 }
4325
4326 /**
4327  * ixgbe_close - Disables a network interface
4328  * @netdev: network interface device structure
4329  *
4330  * Returns 0, this is not allowed to fail
4331  *
4332  * The close entry point is called when an interface is de-activated
4333  * by the OS.  The hardware is still under the drivers control, but
4334  * needs to be disabled.  A global MAC reset is issued to stop the
4335  * hardware, and all transmit and receive resources are freed.
4336  **/
4337 static int ixgbe_close(struct net_device *netdev)
4338 {
4339         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4340
4341         ixgbe_down(adapter);
4342         ixgbe_free_irq(adapter);
4343
4344         ixgbe_free_all_tx_resources(adapter);
4345         ixgbe_free_all_rx_resources(adapter);
4346
4347         ixgbe_release_hw_control(adapter);
4348
4349         return 0;
4350 }
4351
4352 #ifdef CONFIG_PM
4353 static int ixgbe_resume(struct pci_dev *pdev)
4354 {
4355         struct net_device *netdev = pci_get_drvdata(pdev);
4356         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4357         u32 err;
4358
4359         pci_set_power_state(pdev, PCI_D0);
4360         pci_restore_state(pdev);
4361
4362         err = pci_enable_device_mem(pdev);
4363         if (err) {
4364                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4365                                 "suspend\n");
4366                 return err;
4367         }
4368         pci_set_master(pdev);
4369
4370         pci_wake_from_d3(pdev, false);
4371
4372         err = ixgbe_init_interrupt_scheme(adapter);
4373         if (err) {
4374                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4375                                 "device\n");
4376                 return err;
4377         }
4378
4379         ixgbe_reset(adapter);
4380
4381         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4382
4383         if (netif_running(netdev)) {
4384                 err = ixgbe_open(adapter->netdev);
4385                 if (err)
4386                         return err;
4387         }
4388
4389         netif_device_attach(netdev);
4390
4391         return 0;
4392 }
4393 #endif /* CONFIG_PM */
4394
4395 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4396 {
4397         struct net_device *netdev = pci_get_drvdata(pdev);
4398         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4399         struct ixgbe_hw *hw = &adapter->hw;
4400         u32 ctrl, fctrl;
4401         u32 wufc = adapter->wol;
4402 #ifdef CONFIG_PM
4403         int retval = 0;
4404 #endif
4405
4406         netif_device_detach(netdev);
4407
4408         if (netif_running(netdev)) {
4409                 ixgbe_down(adapter);
4410                 ixgbe_free_irq(adapter);
4411                 ixgbe_free_all_tx_resources(adapter);
4412                 ixgbe_free_all_rx_resources(adapter);
4413         }
4414         ixgbe_clear_interrupt_scheme(adapter);
4415
4416 #ifdef CONFIG_PM
4417         retval = pci_save_state(pdev);
4418         if (retval)
4419                 return retval;
4420
4421 #endif
4422         if (wufc) {
4423                 ixgbe_set_rx_mode(netdev);
4424
4425                 /* turn on all-multi mode if wake on multicast is enabled */
4426                 if (wufc & IXGBE_WUFC_MC) {
4427                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4428                         fctrl |= IXGBE_FCTRL_MPE;
4429                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4430                 }
4431
4432                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4433                 ctrl |= IXGBE_CTRL_GIO_DIS;
4434                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4435
4436                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4437         } else {
4438                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4439                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4440         }
4441
4442         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4443                 pci_wake_from_d3(pdev, true);
4444         else
4445                 pci_wake_from_d3(pdev, false);
4446
4447         *enable_wake = !!wufc;
4448
4449         ixgbe_release_hw_control(adapter);
4450
4451         pci_disable_device(pdev);
4452
4453         return 0;
4454 }
4455
4456 #ifdef CONFIG_PM
4457 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4458 {
4459         int retval;
4460         bool wake;
4461
4462         retval = __ixgbe_shutdown(pdev, &wake);
4463         if (retval)
4464                 return retval;
4465
4466         if (wake) {
4467                 pci_prepare_to_sleep(pdev);
4468         } else {
4469                 pci_wake_from_d3(pdev, false);
4470                 pci_set_power_state(pdev, PCI_D3hot);
4471         }
4472
4473         return 0;
4474 }
4475 #endif /* CONFIG_PM */
4476
4477 static void ixgbe_shutdown(struct pci_dev *pdev)
4478 {
4479         bool wake;
4480
4481         __ixgbe_shutdown(pdev, &wake);
4482
4483         if (system_state == SYSTEM_POWER_OFF) {
4484                 pci_wake_from_d3(pdev, wake);
4485                 pci_set_power_state(pdev, PCI_D3hot);
4486         }
4487 }
4488
4489 /**
4490  * ixgbe_update_stats - Update the board statistics counters.
4491  * @adapter: board private structure
4492  **/
4493 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4494 {
4495         struct net_device *netdev = adapter->netdev;
4496         struct ixgbe_hw *hw = &adapter->hw;
4497         u64 total_mpc = 0;
4498         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4499
4500         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4501                 u64 rsc_count = 0;
4502                 u64 rsc_flush = 0;
4503                 for (i = 0; i < 16; i++)
4504                         adapter->hw_rx_no_dma_resources +=
4505                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4506                 for (i = 0; i < adapter->num_rx_queues; i++) {
4507                         rsc_count += adapter->rx_ring[i].rsc_count;
4508                         rsc_flush += adapter->rx_ring[i].rsc_flush;
4509                 }
4510                 adapter->rsc_total_count = rsc_count;
4511                 adapter->rsc_total_flush = rsc_flush;
4512         }
4513
4514         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4515         for (i = 0; i < 8; i++) {
4516                 /* for packet buffers not used, the register should read 0 */
4517                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4518                 missed_rx += mpc;
4519                 adapter->stats.mpc[i] += mpc;
4520                 total_mpc += adapter->stats.mpc[i];
4521                 if (hw->mac.type == ixgbe_mac_82598EB)
4522                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4523                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4524                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4525                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4526                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4527                 if (hw->mac.type == ixgbe_mac_82599EB) {
4528                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4529                                                             IXGBE_PXONRXCNT(i));
4530                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4531                                                            IXGBE_PXOFFRXCNT(i));
4532                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4533                 } else {
4534                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4535                                                               IXGBE_PXONRXC(i));
4536                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4537                                                              IXGBE_PXOFFRXC(i));
4538                 }
4539                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4540                                                             IXGBE_PXONTXC(i));
4541                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4542                                                              IXGBE_PXOFFTXC(i));
4543         }
4544         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4545         /* work around hardware counting issue */
4546         adapter->stats.gprc -= missed_rx;
4547
4548         /* 82598 hardware only has a 32 bit counter in the high register */
4549         if (hw->mac.type == ixgbe_mac_82599EB) {
4550                 u64 tmp;
4551                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4552                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4553                 adapter->stats.gorc += (tmp << 32);
4554                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4555                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4556                 adapter->stats.gotc += (tmp << 32);
4557                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4558                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4559                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4560                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4561                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4562                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4563 #ifdef IXGBE_FCOE
4564                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4565                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4566                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4567                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4568                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4569                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4570 #endif /* IXGBE_FCOE */
4571         } else {
4572                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4573                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4574                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4575                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4576                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4577         }
4578         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4579         adapter->stats.bprc += bprc;
4580         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4581         if (hw->mac.type == ixgbe_mac_82598EB)
4582                 adapter->stats.mprc -= bprc;
4583         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4584         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4585         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4586         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4587         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4588         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4589         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4590         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4591         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4592         adapter->stats.lxontxc += lxon;
4593         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4594         adapter->stats.lxofftxc += lxoff;
4595         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4596         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4597         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4598         /*
4599          * 82598 errata - tx of flow control packets is included in tx counters
4600          */
4601         xon_off_tot = lxon + lxoff;
4602         adapter->stats.gptc -= xon_off_tot;
4603         adapter->stats.mptc -= xon_off_tot;
4604         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4605         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4606         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4607         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4608         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4609         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4610         adapter->stats.ptc64 -= xon_off_tot;
4611         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4612         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4613         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4614         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4615         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4616         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4617
4618         /* Fill out the OS statistics structure */
4619         netdev->stats.multicast = adapter->stats.mprc;
4620
4621         /* Rx Errors */
4622         netdev->stats.rx_errors = adapter->stats.crcerrs +
4623                                        adapter->stats.rlec;
4624         netdev->stats.rx_dropped = 0;
4625         netdev->stats.rx_length_errors = adapter->stats.rlec;
4626         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4627         netdev->stats.rx_missed_errors = total_mpc;
4628 }
4629
4630 /**
4631  * ixgbe_watchdog - Timer Call-back
4632  * @data: pointer to adapter cast into an unsigned long
4633  **/
4634 static void ixgbe_watchdog(unsigned long data)
4635 {
4636         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4637         struct ixgbe_hw *hw = &adapter->hw;
4638         u64 eics = 0;
4639         int i;
4640
4641         /*
4642          *  Do the watchdog outside of interrupt context due to the lovely
4643          * delays that some of the newer hardware requires
4644          */
4645
4646         if (test_bit(__IXGBE_DOWN, &adapter->state))
4647                 goto watchdog_short_circuit;
4648
4649         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4650                 /*
4651                  * for legacy and MSI interrupts don't set any bits
4652                  * that are enabled for EIAM, because this operation
4653                  * would set *both* EIMS and EICS for any bit in EIAM
4654                  */
4655                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4656                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4657                 goto watchdog_reschedule;
4658         }
4659
4660         /* get one bit for every active tx/rx interrupt vector */
4661         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4662                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4663                 if (qv->rxr_count || qv->txr_count)
4664                         eics |= ((u64)1 << i);
4665         }
4666
4667         /* Cause software interrupt to ensure rx rings are cleaned */
4668         ixgbe_irq_rearm_queues(adapter, eics);
4669
4670 watchdog_reschedule:
4671         /* Reset the timer */
4672         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4673
4674 watchdog_short_circuit:
4675         schedule_work(&adapter->watchdog_task);
4676 }
4677
4678 /**
4679  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4680  * @work: pointer to work_struct containing our data
4681  **/
4682 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4683 {
4684         struct ixgbe_adapter *adapter = container_of(work,
4685                                                      struct ixgbe_adapter,
4686                                                      multispeed_fiber_task);
4687         struct ixgbe_hw *hw = &adapter->hw;
4688         u32 autoneg;
4689         bool negotiation;
4690
4691         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4692         autoneg = hw->phy.autoneg_advertised;
4693         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4694                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4695         if (hw->mac.ops.setup_link)
4696                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4697         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4698         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4699 }
4700
4701 /**
4702  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4703  * @work: pointer to work_struct containing our data
4704  **/
4705 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4706 {
4707         struct ixgbe_adapter *adapter = container_of(work,
4708                                                      struct ixgbe_adapter,
4709                                                      sfp_config_module_task);
4710         struct ixgbe_hw *hw = &adapter->hw;
4711         u32 err;
4712
4713         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4714
4715         /* Time for electrical oscillations to settle down */
4716         msleep(100);
4717         err = hw->phy.ops.identify_sfp(hw);
4718
4719         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4720                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4721                         "an unsupported SFP+ module type was detected.\n"
4722                         "Reload the driver after installing a supported "
4723                         "module.\n");
4724                 unregister_netdev(adapter->netdev);
4725                 return;
4726         }
4727         hw->mac.ops.setup_sfp(hw);
4728
4729         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4730                 /* This will also work for DA Twinax connections */
4731                 schedule_work(&adapter->multispeed_fiber_task);
4732         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4733 }
4734
4735 /**
4736  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4737  * @work: pointer to work_struct containing our data
4738  **/
4739 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4740 {
4741         struct ixgbe_adapter *adapter = container_of(work,
4742                                                      struct ixgbe_adapter,
4743                                                      fdir_reinit_task);
4744         struct ixgbe_hw *hw = &adapter->hw;
4745         int i;
4746
4747         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4748                 for (i = 0; i < adapter->num_tx_queues; i++)
4749                         set_bit(__IXGBE_FDIR_INIT_DONE,
4750                                 &(adapter->tx_ring[i].reinit_state));
4751         } else {
4752                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4753                         "ignored adding FDIR ATR filters \n");
4754         }
4755         /* Done FDIR Re-initialization, enable transmits */
4756         netif_tx_start_all_queues(adapter->netdev);
4757 }
4758
4759 /**
4760  * ixgbe_watchdog_task - worker thread to bring link up
4761  * @work: pointer to work_struct containing our data
4762  **/
4763 static void ixgbe_watchdog_task(struct work_struct *work)
4764 {
4765         struct ixgbe_adapter *adapter = container_of(work,
4766                                                      struct ixgbe_adapter,
4767                                                      watchdog_task);
4768         struct net_device *netdev = adapter->netdev;
4769         struct ixgbe_hw *hw = &adapter->hw;
4770         u32 link_speed = adapter->link_speed;
4771         bool link_up = adapter->link_up;
4772         int i;
4773         struct ixgbe_ring *tx_ring;
4774         int some_tx_pending = 0;
4775
4776         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4777
4778         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4779                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4780                 if (link_up) {
4781 #ifdef CONFIG_DCB
4782                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4783                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4784                                         hw->mac.ops.fc_enable(hw, i);
4785                         } else {
4786                                 hw->mac.ops.fc_enable(hw, 0);
4787                         }
4788 #else
4789                         hw->mac.ops.fc_enable(hw, 0);
4790 #endif
4791                 }
4792
4793                 if (link_up ||
4794                     time_after(jiffies, (adapter->link_check_timeout +
4795                                          IXGBE_TRY_LINK_TIMEOUT))) {
4796                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4797                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4798                 }
4799                 adapter->link_up = link_up;
4800                 adapter->link_speed = link_speed;
4801         }
4802
4803         if (link_up) {
4804                 if (!netif_carrier_ok(netdev)) {
4805                         bool flow_rx, flow_tx;
4806
4807                         if (hw->mac.type == ixgbe_mac_82599EB) {
4808                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4809                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4810                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4811                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4812                         } else {
4813                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4814                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4815                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4816                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4817                         }
4818
4819                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4820                                "Flow Control: %s\n",
4821                                netdev->name,
4822                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4823                                 "10 Gbps" :
4824                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4825                                  "1 Gbps" : "unknown speed")),
4826                                ((flow_rx && flow_tx) ? "RX/TX" :
4827                                 (flow_rx ? "RX" :
4828                                 (flow_tx ? "TX" : "None"))));
4829
4830                         netif_carrier_on(netdev);
4831                 } else {
4832                         /* Force detection of hung controller */
4833                         adapter->detect_tx_hung = true;
4834                 }
4835         } else {
4836                 adapter->link_up = false;
4837                 adapter->link_speed = 0;
4838                 if (netif_carrier_ok(netdev)) {
4839                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4840                                netdev->name);
4841                         netif_carrier_off(netdev);
4842                 }
4843         }
4844
4845         if (!netif_carrier_ok(netdev)) {
4846                 for (i = 0; i < adapter->num_tx_queues; i++) {
4847                         tx_ring = &adapter->tx_ring[i];
4848                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4849                                 some_tx_pending = 1;
4850                                 break;
4851                         }
4852                 }
4853
4854                 if (some_tx_pending) {
4855                         /* We've lost link, so the controller stops DMA,
4856                          * but we've got queued Tx work that's never going
4857                          * to get done, so reset controller to flush Tx.
4858                          * (Do the reset outside of interrupt context).
4859                          */
4860                          schedule_work(&adapter->reset_task);
4861                 }
4862         }
4863
4864         ixgbe_update_stats(adapter);
4865         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4866 }
4867
4868 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4869                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4870                      u32 tx_flags, u8 *hdr_len)
4871 {
4872         struct ixgbe_adv_tx_context_desc *context_desc;
4873         unsigned int i;
4874         int err;
4875         struct ixgbe_tx_buffer *tx_buffer_info;
4876         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4877         u32 mss_l4len_idx, l4len;
4878
4879         if (skb_is_gso(skb)) {
4880                 if (skb_header_cloned(skb)) {
4881                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4882                         if (err)
4883                                 return err;
4884                 }
4885                 l4len = tcp_hdrlen(skb);
4886                 *hdr_len += l4len;
4887
4888                 if (skb->protocol == htons(ETH_P_IP)) {
4889                         struct iphdr *iph = ip_hdr(skb);
4890                         iph->tot_len = 0;
4891                         iph->check = 0;
4892                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4893                                                                  iph->daddr, 0,
4894                                                                  IPPROTO_TCP,
4895                                                                  0);
4896                         adapter->hw_tso_ctxt++;
4897                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4898                         ipv6_hdr(skb)->payload_len = 0;
4899                         tcp_hdr(skb)->check =
4900                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4901                                              &ipv6_hdr(skb)->daddr,
4902                                              0, IPPROTO_TCP, 0);
4903                         adapter->hw_tso6_ctxt++;
4904                 }
4905
4906                 i = tx_ring->next_to_use;
4907
4908                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4909                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4910
4911                 /* VLAN MACLEN IPLEN */
4912                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4913                         vlan_macip_lens |=
4914                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4915                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4916                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4917                 *hdr_len += skb_network_offset(skb);
4918                 vlan_macip_lens |=
4919                     (skb_transport_header(skb) - skb_network_header(skb));
4920                 *hdr_len +=
4921                     (skb_transport_header(skb) - skb_network_header(skb));
4922                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4923                 context_desc->seqnum_seed = 0;
4924
4925                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4926                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4927                                    IXGBE_ADVTXD_DTYP_CTXT);
4928
4929                 if (skb->protocol == htons(ETH_P_IP))
4930                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4931                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4932                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4933
4934                 /* MSS L4LEN IDX */
4935                 mss_l4len_idx =
4936                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4937                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4938                 /* use index 1 for TSO */
4939                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4940                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4941
4942                 tx_buffer_info->time_stamp = jiffies;
4943                 tx_buffer_info->next_to_watch = i;
4944
4945                 i++;
4946                 if (i == tx_ring->count)
4947                         i = 0;
4948                 tx_ring->next_to_use = i;
4949
4950                 return true;
4951         }
4952         return false;
4953 }
4954
4955 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4956                           struct ixgbe_ring *tx_ring,
4957                           struct sk_buff *skb, u32 tx_flags)
4958 {
4959         struct ixgbe_adv_tx_context_desc *context_desc;
4960         unsigned int i;
4961         struct ixgbe_tx_buffer *tx_buffer_info;
4962         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4963
4964         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4965             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4966                 i = tx_ring->next_to_use;
4967                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4968                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4969
4970                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4971                         vlan_macip_lens |=
4972                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4973                 vlan_macip_lens |= (skb_network_offset(skb) <<
4974                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4975                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4976                         vlan_macip_lens |= (skb_transport_header(skb) -
4977                                             skb_network_header(skb));
4978
4979                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4980                 context_desc->seqnum_seed = 0;
4981
4982                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4983                                     IXGBE_ADVTXD_DTYP_CTXT);
4984
4985                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4986                         switch (skb->protocol) {
4987                         case cpu_to_be16(ETH_P_IP):
4988                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4989                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4990                                         type_tucmd_mlhl |=
4991                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4992                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4993                                         type_tucmd_mlhl |=
4994                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4995                                 break;
4996                         case cpu_to_be16(ETH_P_IPV6):
4997                                 /* XXX what about other V6 headers?? */
4998                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4999                                         type_tucmd_mlhl |=
5000                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5001                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5002                                         type_tucmd_mlhl |=
5003                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5004                                 break;
5005                         default:
5006                                 if (unlikely(net_ratelimit())) {
5007                                         DPRINTK(PROBE, WARNING,
5008                                          "partial checksum but proto=%x!\n",
5009                                          skb->protocol);
5010                                 }
5011                                 break;
5012                         }
5013                 }
5014
5015                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5016                 /* use index zero for tx checksum offload */
5017                 context_desc->mss_l4len_idx = 0;
5018
5019                 tx_buffer_info->time_stamp = jiffies;
5020                 tx_buffer_info->next_to_watch = i;
5021
5022                 adapter->hw_csum_tx_good++;
5023                 i++;
5024                 if (i == tx_ring->count)
5025                         i = 0;
5026                 tx_ring->next_to_use = i;
5027
5028                 return true;
5029         }
5030
5031         return false;
5032 }
5033
5034 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5035                         struct ixgbe_ring *tx_ring,
5036                         struct sk_buff *skb, u32 tx_flags,
5037                         unsigned int first)
5038 {
5039         struct pci_dev *pdev = adapter->pdev;
5040         struct ixgbe_tx_buffer *tx_buffer_info;
5041         unsigned int len;
5042         unsigned int total = skb->len;
5043         unsigned int offset = 0, size, count = 0, i;
5044         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5045         unsigned int f;
5046
5047         i = tx_ring->next_to_use;
5048
5049         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5050                 /* excluding fcoe_crc_eof for FCoE */
5051                 total -= sizeof(struct fcoe_crc_eof);
5052
5053         len = min(skb_headlen(skb), total);
5054         while (len) {
5055                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5056                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5057
5058                 tx_buffer_info->length = size;
5059                 tx_buffer_info->mapped_as_page = false;
5060                 tx_buffer_info->dma = pci_map_single(pdev,
5061                                                      skb->data + offset,
5062                                                      size, PCI_DMA_TODEVICE);
5063                 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5064                         goto dma_error;
5065                 tx_buffer_info->time_stamp = jiffies;
5066                 tx_buffer_info->next_to_watch = i;
5067
5068                 len -= size;
5069                 total -= size;
5070                 offset += size;
5071                 count++;
5072
5073                 if (len) {
5074                         i++;
5075                         if (i == tx_ring->count)
5076                                 i = 0;
5077                 }
5078         }
5079
5080         for (f = 0; f < nr_frags; f++) {
5081                 struct skb_frag_struct *frag;
5082
5083                 frag = &skb_shinfo(skb)->frags[f];
5084                 len = min((unsigned int)frag->size, total);
5085                 offset = frag->page_offset;
5086
5087                 while (len) {
5088                         i++;
5089                         if (i == tx_ring->count)
5090                                 i = 0;
5091
5092                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5093                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5094
5095                         tx_buffer_info->length = size;
5096                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
5097                                                            frag->page,
5098                                                            offset, size,
5099                                                            PCI_DMA_TODEVICE);
5100                         tx_buffer_info->mapped_as_page = true;
5101                         if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
5102                                 goto dma_error;
5103                         tx_buffer_info->time_stamp = jiffies;
5104                         tx_buffer_info->next_to_watch = i;
5105
5106                         len -= size;
5107                         total -= size;
5108                         offset += size;
5109                         count++;
5110                 }
5111                 if (total == 0)
5112                         break;
5113         }
5114
5115         tx_ring->tx_buffer_info[i].skb = skb;
5116         tx_ring->tx_buffer_info[first].next_to_watch = i;
5117
5118         return count;
5119
5120 dma_error:
5121         dev_err(&pdev->dev, "TX DMA map failed\n");
5122
5123         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5124         tx_buffer_info->dma = 0;
5125         tx_buffer_info->time_stamp = 0;
5126         tx_buffer_info->next_to_watch = 0;
5127         count--;
5128
5129         /* clear timestamp and dma mappings for remaining portion of packet */
5130         while (count >= 0) {
5131                 count--;
5132                 i--;
5133                 if (i < 0)
5134                         i += tx_ring->count;
5135                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5136                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5137         }
5138
5139         return count;
5140 }
5141
5142 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5143                            struct ixgbe_ring *tx_ring,
5144                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5145 {
5146         union ixgbe_adv_tx_desc *tx_desc = NULL;
5147         struct ixgbe_tx_buffer *tx_buffer_info;
5148         u32 olinfo_status = 0, cmd_type_len = 0;
5149         unsigned int i;
5150         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5151
5152         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5153
5154         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5155
5156         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5157                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5158
5159         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5160                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5161
5162                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5163                                  IXGBE_ADVTXD_POPTS_SHIFT;
5164
5165                 /* use index 1 context for tso */
5166                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5167                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5168                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5169                                          IXGBE_ADVTXD_POPTS_SHIFT;
5170
5171         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5172                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5173                                  IXGBE_ADVTXD_POPTS_SHIFT;
5174
5175         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5176                 olinfo_status |= IXGBE_ADVTXD_CC;
5177                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5178                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5179                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5180         }
5181
5182         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5183
5184         i = tx_ring->next_to_use;
5185         while (count--) {
5186                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5187                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5188                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5189                 tx_desc->read.cmd_type_len =
5190                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5191                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5192                 i++;
5193                 if (i == tx_ring->count)
5194                         i = 0;
5195         }
5196
5197         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5198
5199         /*
5200          * Force memory writes to complete before letting h/w
5201          * know there are new descriptors to fetch.  (Only
5202          * applicable for weak-ordered memory model archs,
5203          * such as IA-64).
5204          */
5205         wmb();
5206
5207         tx_ring->next_to_use = i;
5208         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5209 }
5210
5211 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5212                       int queue, u32 tx_flags)
5213 {
5214         /* Right now, we support IPv4 only */
5215         struct ixgbe_atr_input atr_input;
5216         struct tcphdr *th;
5217         struct iphdr *iph = ip_hdr(skb);
5218         struct ethhdr *eth = (struct ethhdr *)skb->data;
5219         u16 vlan_id, src_port, dst_port, flex_bytes;
5220         u32 src_ipv4_addr, dst_ipv4_addr;
5221         u8 l4type = 0;
5222
5223         /* check if we're UDP or TCP */
5224         if (iph->protocol == IPPROTO_TCP) {
5225                 th = tcp_hdr(skb);
5226                 src_port = th->source;
5227                 dst_port = th->dest;
5228                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5229                 /* l4type IPv4 type is 0, no need to assign */
5230         } else {
5231                 /* Unsupported L4 header, just bail here */
5232                 return;
5233         }
5234
5235         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5236
5237         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5238                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5239         src_ipv4_addr = iph->saddr;
5240         dst_ipv4_addr = iph->daddr;
5241         flex_bytes = eth->h_proto;
5242
5243         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5244         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5245         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5246         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5247         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5248         /* src and dst are inverted, think how the receiver sees them */
5249         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5250         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5251
5252         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5253         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5254 }
5255
5256 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5257                                  struct ixgbe_ring *tx_ring, int size)
5258 {
5259         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5260
5261         netif_stop_subqueue(netdev, tx_ring->queue_index);
5262         /* Herbert's original patch had:
5263          *  smp_mb__after_netif_stop_queue();
5264          * but since that doesn't exist yet, just open code it. */
5265         smp_mb();
5266
5267         /* We need to check again in a case another CPU has just
5268          * made room available. */
5269         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5270                 return -EBUSY;
5271
5272         /* A reprieve! - use start_queue because it doesn't call schedule */
5273         netif_start_subqueue(netdev, tx_ring->queue_index);
5274         ++adapter->restart_queue;
5275         return 0;
5276 }
5277
5278 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5279                               struct ixgbe_ring *tx_ring, int size)
5280 {
5281         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5282                 return 0;
5283         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5284 }
5285
5286 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5287 {
5288         struct ixgbe_adapter *adapter = netdev_priv(dev);
5289
5290         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5291                 return smp_processor_id();
5292
5293         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5294                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5295
5296         return skb_tx_hash(dev, skb);
5297 }
5298
5299 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5300                                     struct net_device *netdev)
5301 {
5302         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5303         struct ixgbe_ring *tx_ring;
5304         unsigned int first;
5305         unsigned int tx_flags = 0;
5306         u8 hdr_len = 0;
5307         int r_idx = 0, tso;
5308         int count = 0;
5309         unsigned int f;
5310
5311         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5312                 tx_flags |= vlan_tx_tag_get(skb);
5313                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5314                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5315                         tx_flags |= (skb->queue_mapping << 13);
5316                 }
5317                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5318                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5319         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5320                 if (skb->priority != TC_PRIO_CONTROL) {
5321                         tx_flags |= (skb->queue_mapping << 13);
5322                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5323                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5324                 } else {
5325                         skb->queue_mapping =
5326                                 adapter->ring_feature[RING_F_DCB].indices-1;
5327                 }
5328         }
5329
5330         r_idx = skb->queue_mapping;
5331         tx_ring = &adapter->tx_ring[r_idx];
5332
5333         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5334             (skb->protocol == htons(ETH_P_FCOE))) {
5335                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5336 #ifdef IXGBE_FCOE
5337 #ifdef CONFIG_IXGBE_DCB
5338                 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5339                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5340                 tx_flags |= ((adapter->fcoe.up << 13)
5341                               << IXGBE_TX_FLAGS_VLAN_SHIFT);
5342 #endif
5343                 r_idx = smp_processor_id();
5344                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5345                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5346                 tx_ring = &adapter->tx_ring[r_idx];
5347 #endif
5348         }
5349         /* four things can cause us to need a context descriptor */
5350         if (skb_is_gso(skb) ||
5351             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5352             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5353             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5354                 count++;
5355
5356         count += TXD_USE_COUNT(skb_headlen(skb));
5357         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5358                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5359
5360         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5361                 adapter->tx_busy++;
5362                 return NETDEV_TX_BUSY;
5363         }
5364
5365         first = tx_ring->next_to_use;
5366         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5367 #ifdef IXGBE_FCOE
5368                 /* setup tx offload for FCoE */
5369                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5370                 if (tso < 0) {
5371                         dev_kfree_skb_any(skb);
5372                         return NETDEV_TX_OK;
5373                 }
5374                 if (tso)
5375                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5376 #endif /* IXGBE_FCOE */
5377         } else {
5378                 if (skb->protocol == htons(ETH_P_IP))
5379                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5380                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5381                 if (tso < 0) {
5382                         dev_kfree_skb_any(skb);
5383                         return NETDEV_TX_OK;
5384                 }
5385
5386                 if (tso)
5387                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5388                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5389                          (skb->ip_summed == CHECKSUM_PARTIAL))
5390                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5391         }
5392
5393         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5394         if (count) {
5395                 /* add the ATR filter if ATR is on */
5396                 if (tx_ring->atr_sample_rate) {
5397                         ++tx_ring->atr_count;
5398                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5399                              test_bit(__IXGBE_FDIR_INIT_DONE,
5400                                       &tx_ring->reinit_state)) {
5401                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5402                                           tx_flags);
5403                                 tx_ring->atr_count = 0;
5404                         }
5405                 }
5406                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5407                                hdr_len);
5408                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5409
5410         } else {
5411                 dev_kfree_skb_any(skb);
5412                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5413                 tx_ring->next_to_use = first;
5414         }
5415
5416         return NETDEV_TX_OK;
5417 }
5418
5419 /**
5420  * ixgbe_get_stats - Get System Network Statistics
5421  * @netdev: network interface device structure
5422  *
5423  * Returns the address of the device statistics structure.
5424  * The statistics are actually updated from the timer callback.
5425  **/
5426 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5427 {
5428         /* only return the current stats */
5429         return &netdev->stats;
5430 }
5431
5432 /**
5433  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5434  * @netdev: network interface device structure
5435  * @p: pointer to an address structure
5436  *
5437  * Returns 0 on success, negative on failure
5438  **/
5439 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5440 {
5441         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5442         struct ixgbe_hw *hw = &adapter->hw;
5443         struct sockaddr *addr = p;
5444
5445         if (!is_valid_ether_addr(addr->sa_data))
5446                 return -EADDRNOTAVAIL;
5447
5448         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5449         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5450
5451         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5452
5453         return 0;
5454 }
5455
5456 static int
5457 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5458 {
5459         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5460         struct ixgbe_hw *hw = &adapter->hw;
5461         u16 value;
5462         int rc;
5463
5464         if (prtad != hw->phy.mdio.prtad)
5465                 return -EINVAL;
5466         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5467         if (!rc)
5468                 rc = value;
5469         return rc;
5470 }
5471
5472 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5473                             u16 addr, u16 value)
5474 {
5475         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5476         struct ixgbe_hw *hw = &adapter->hw;
5477
5478         if (prtad != hw->phy.mdio.prtad)
5479                 return -EINVAL;
5480         return hw->phy.ops.write_reg(hw, addr, devad, value);
5481 }
5482
5483 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5484 {
5485         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5486
5487         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5488 }
5489
5490 /**
5491  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5492  * netdev->dev_addrs
5493  * @netdev: network interface device structure
5494  *
5495  * Returns non-zero on failure
5496  **/
5497 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5498 {
5499         int err = 0;
5500         struct ixgbe_adapter *adapter = netdev_priv(dev);
5501         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5502
5503         if (is_valid_ether_addr(mac->san_addr)) {
5504                 rtnl_lock();
5505                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5506                 rtnl_unlock();
5507         }
5508         return err;
5509 }
5510
5511 /**
5512  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5513  * netdev->dev_addrs
5514  * @netdev: network interface device structure
5515  *
5516  * Returns non-zero on failure
5517  **/
5518 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5519 {
5520         int err = 0;
5521         struct ixgbe_adapter *adapter = netdev_priv(dev);
5522         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5523
5524         if (is_valid_ether_addr(mac->san_addr)) {
5525                 rtnl_lock();
5526                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5527                 rtnl_unlock();
5528         }
5529         return err;
5530 }
5531
5532 #ifdef CONFIG_NET_POLL_CONTROLLER
5533 /*
5534  * Polling 'interrupt' - used by things like netconsole to send skbs
5535  * without having to re-enable interrupts. It's not called while
5536  * the interrupt routine is executing.
5537  */
5538 static void ixgbe_netpoll(struct net_device *netdev)
5539 {
5540         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5541         int i;
5542
5543         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5544         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5545                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5546                 for (i = 0; i < num_q_vectors; i++) {
5547                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5548                         ixgbe_msix_clean_many(0, q_vector);
5549                 }
5550         } else {
5551                 ixgbe_intr(adapter->pdev->irq, netdev);
5552         }
5553         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5554 }
5555 #endif
5556
5557 static const struct net_device_ops ixgbe_netdev_ops = {
5558         .ndo_open               = ixgbe_open,
5559         .ndo_stop               = ixgbe_close,
5560         .ndo_start_xmit         = ixgbe_xmit_frame,
5561         .ndo_select_queue       = ixgbe_select_queue,
5562         .ndo_get_stats          = ixgbe_get_stats,
5563         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5564         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5565         .ndo_validate_addr      = eth_validate_addr,
5566         .ndo_set_mac_address    = ixgbe_set_mac,
5567         .ndo_change_mtu         = ixgbe_change_mtu,
5568         .ndo_tx_timeout         = ixgbe_tx_timeout,
5569         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5570         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5571         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5572         .ndo_do_ioctl           = ixgbe_ioctl,
5573 #ifdef CONFIG_NET_POLL_CONTROLLER
5574         .ndo_poll_controller    = ixgbe_netpoll,
5575 #endif
5576 #ifdef IXGBE_FCOE
5577         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5578         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5579         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5580         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5581         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
5582 #endif /* IXGBE_FCOE */
5583 };
5584
5585 /**
5586  * ixgbe_probe - Device Initialization Routine
5587  * @pdev: PCI device information struct
5588  * @ent: entry in ixgbe_pci_tbl
5589  *
5590  * Returns 0 on success, negative on failure
5591  *
5592  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5593  * The OS initialization, configuring of the adapter private structure,
5594  * and a hardware reset occur.
5595  **/
5596 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5597                                  const struct pci_device_id *ent)
5598 {
5599         struct net_device *netdev;
5600         struct ixgbe_adapter *adapter = NULL;
5601         struct ixgbe_hw *hw;
5602         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5603         static int cards_found;
5604         int i, err, pci_using_dac;
5605 #ifdef IXGBE_FCOE
5606         u16 device_caps;
5607 #endif
5608         u32 part_num, eec;
5609
5610         err = pci_enable_device_mem(pdev);
5611         if (err)
5612                 return err;
5613
5614         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5615             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5616                 pci_using_dac = 1;
5617         } else {
5618                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5619                 if (err) {
5620                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5621                         if (err) {
5622                                 dev_err(&pdev->dev, "No usable DMA "
5623                                         "configuration, aborting\n");
5624                                 goto err_dma;
5625                         }
5626                 }
5627                 pci_using_dac = 0;
5628         }
5629
5630         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5631                                            IORESOURCE_MEM), ixgbe_driver_name);
5632         if (err) {
5633                 dev_err(&pdev->dev,
5634                         "pci_request_selected_regions failed 0x%x\n", err);
5635                 goto err_pci_reg;
5636         }
5637
5638         pci_enable_pcie_error_reporting(pdev);
5639
5640         pci_set_master(pdev);
5641         pci_save_state(pdev);
5642
5643         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5644         if (!netdev) {
5645                 err = -ENOMEM;
5646                 goto err_alloc_etherdev;
5647         }
5648
5649         SET_NETDEV_DEV(netdev, &pdev->dev);
5650
5651         pci_set_drvdata(pdev, netdev);
5652         adapter = netdev_priv(netdev);
5653
5654         adapter->netdev = netdev;
5655         adapter->pdev = pdev;
5656         hw = &adapter->hw;
5657         hw->back = adapter;
5658         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5659
5660         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5661                               pci_resource_len(pdev, 0));
5662         if (!hw->hw_addr) {
5663                 err = -EIO;
5664                 goto err_ioremap;
5665         }
5666
5667         for (i = 1; i <= 5; i++) {
5668                 if (pci_resource_len(pdev, i) == 0)
5669                         continue;
5670         }
5671
5672         netdev->netdev_ops = &ixgbe_netdev_ops;
5673         ixgbe_set_ethtool_ops(netdev);
5674         netdev->watchdog_timeo = 5 * HZ;
5675         strcpy(netdev->name, pci_name(pdev));
5676
5677         adapter->bd_number = cards_found;
5678
5679         /* Setup hw api */
5680         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5681         hw->mac.type  = ii->mac;
5682
5683         /* EEPROM */
5684         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5685         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5686         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5687         if (!(eec & (1 << 8)))
5688                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5689
5690         /* PHY */
5691         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5692         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5693         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5694         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5695         hw->phy.mdio.mmds = 0;
5696         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5697         hw->phy.mdio.dev = netdev;
5698         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5699         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5700
5701         /* set up this timer and work struct before calling get_invariants
5702          * which might start the timer
5703          */
5704         init_timer(&adapter->sfp_timer);
5705         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5706         adapter->sfp_timer.data = (unsigned long) adapter;
5707
5708         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5709
5710         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5711         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5712
5713         /* a new SFP+ module arrival, called from GPI SDP2 context */
5714         INIT_WORK(&adapter->sfp_config_module_task,
5715                   ixgbe_sfp_config_module_task);
5716
5717         ii->get_invariants(hw);
5718
5719         /* setup the private structure */
5720         err = ixgbe_sw_init(adapter);
5721         if (err)
5722                 goto err_sw_init;
5723
5724         /*
5725          * If there is a fan on this device and it has failed log the
5726          * failure.
5727          */
5728         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5729                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5730                 if (esdp & IXGBE_ESDP_SDP1)
5731                         DPRINTK(PROBE, CRIT,
5732                                 "Fan has stopped, replace the adapter\n");
5733         }
5734
5735         /* reset_hw fills in the perm_addr as well */
5736         err = hw->mac.ops.reset_hw(hw);
5737         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5738             hw->mac.type == ixgbe_mac_82598EB) {
5739                 /*
5740                  * Start a kernel thread to watch for a module to arrive.
5741                  * Only do this for 82598, since 82599 will generate
5742                  * interrupts on module arrival.
5743                  */
5744                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5745                 mod_timer(&adapter->sfp_timer,
5746                           round_jiffies(jiffies + (2 * HZ)));
5747                 err = 0;
5748         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5749                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5750                         "an unsupported SFP+ module type was detected.\n"
5751                         "Reload the driver after installing a supported "
5752                         "module.\n");
5753                 goto err_sw_init;
5754         } else if (err) {
5755                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5756                 goto err_sw_init;
5757         }
5758
5759         netdev->features = NETIF_F_SG |
5760                            NETIF_F_IP_CSUM |
5761                            NETIF_F_HW_VLAN_TX |
5762                            NETIF_F_HW_VLAN_RX |
5763                            NETIF_F_HW_VLAN_FILTER;
5764
5765         netdev->features |= NETIF_F_IPV6_CSUM;
5766         netdev->features |= NETIF_F_TSO;
5767         netdev->features |= NETIF_F_TSO6;
5768         netdev->features |= NETIF_F_GRO;
5769
5770         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5771                 netdev->features |= NETIF_F_SCTP_CSUM;
5772
5773         netdev->vlan_features |= NETIF_F_TSO;
5774         netdev->vlan_features |= NETIF_F_TSO6;
5775         netdev->vlan_features |= NETIF_F_IP_CSUM;
5776         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5777         netdev->vlan_features |= NETIF_F_SG;
5778
5779         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5780                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5781
5782 #ifdef CONFIG_IXGBE_DCB
5783         netdev->dcbnl_ops = &dcbnl_ops;
5784 #endif
5785
5786 #ifdef IXGBE_FCOE
5787         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5788                 if (hw->mac.ops.get_device_caps) {
5789                         hw->mac.ops.get_device_caps(hw, &device_caps);
5790                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5791                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5792                 }
5793         }
5794 #endif /* IXGBE_FCOE */
5795         if (pci_using_dac)
5796                 netdev->features |= NETIF_F_HIGHDMA;
5797
5798         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5799                 netdev->features |= NETIF_F_LRO;
5800
5801         /* make sure the EEPROM is good */
5802         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5803                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5804                 err = -EIO;
5805                 goto err_eeprom;
5806         }
5807
5808         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5809         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5810
5811         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5812                 dev_err(&pdev->dev, "invalid MAC address\n");
5813                 err = -EIO;
5814                 goto err_eeprom;
5815         }
5816
5817         init_timer(&adapter->watchdog_timer);
5818         adapter->watchdog_timer.function = &ixgbe_watchdog;
5819         adapter->watchdog_timer.data = (unsigned long)adapter;
5820
5821         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5822         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5823
5824         err = ixgbe_init_interrupt_scheme(adapter);
5825         if (err)
5826                 goto err_sw_init;
5827
5828         switch (pdev->device) {
5829         case IXGBE_DEV_ID_82599_KX4:
5830                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5831                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5832                 /* Enable ACPI wakeup in GRC */
5833                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5834                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5835                 break;
5836         default:
5837                 adapter->wol = 0;
5838                 break;
5839         }
5840         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5841
5842         /* pick up the PCI bus settings for reporting later */
5843         hw->mac.ops.get_bus_info(hw);
5844
5845         /* print bus type/speed/width info */
5846         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5847                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5848                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5849                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5850                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5851                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5852                  "Unknown"),
5853                 netdev->dev_addr);
5854         ixgbe_read_pba_num_generic(hw, &part_num);
5855         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5856                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5857                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5858                          (part_num >> 8), (part_num & 0xff));
5859         else
5860                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5861                          hw->mac.type, hw->phy.type,
5862                          (part_num >> 8), (part_num & 0xff));
5863
5864         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5865                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5866                          "this card is not sufficient for optimal "
5867                          "performance.\n");
5868                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5869                          "PCI-Express slot is required.\n");
5870         }
5871
5872         /* save off EEPROM version number */
5873         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5874
5875         /* reset the hardware with the new settings */
5876         err = hw->mac.ops.start_hw(hw);
5877
5878         if (err == IXGBE_ERR_EEPROM_VERSION) {
5879                 /* We are running on a pre-production device, log a warning */
5880                 dev_warn(&pdev->dev, "This device is a pre-production "
5881                          "adapter/LOM.  Please be aware there may be issues "
5882                          "associated with your hardware.  If you are "
5883                          "experiencing problems please contact your Intel or "
5884                          "hardware representative who provided you with this "
5885                          "hardware.\n");
5886         }
5887         strcpy(netdev->name, "eth%d");
5888         err = register_netdev(netdev);
5889         if (err)
5890                 goto err_register;
5891
5892         /* carrier off reporting is important to ethtool even BEFORE open */
5893         netif_carrier_off(netdev);
5894
5895         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5896             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5897                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5898
5899 #ifdef CONFIG_IXGBE_DCA
5900         if (dca_add_requester(&pdev->dev) == 0) {
5901                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5902                 ixgbe_setup_dca(adapter);
5903         }
5904 #endif
5905         /* add san mac addr to netdev */
5906         ixgbe_add_sanmac_netdev(netdev);
5907
5908         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5909         cards_found++;
5910         return 0;
5911
5912 err_register:
5913         ixgbe_release_hw_control(adapter);
5914         ixgbe_clear_interrupt_scheme(adapter);
5915 err_sw_init:
5916 err_eeprom:
5917         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5918         del_timer_sync(&adapter->sfp_timer);
5919         cancel_work_sync(&adapter->sfp_task);
5920         cancel_work_sync(&adapter->multispeed_fiber_task);
5921         cancel_work_sync(&adapter->sfp_config_module_task);
5922         iounmap(hw->hw_addr);
5923 err_ioremap:
5924         free_netdev(netdev);
5925 err_alloc_etherdev:
5926         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5927                                      IORESOURCE_MEM));
5928 err_pci_reg:
5929 err_dma:
5930         pci_disable_device(pdev);
5931         return err;
5932 }
5933
5934 /**
5935  * ixgbe_remove - Device Removal Routine
5936  * @pdev: PCI device information struct
5937  *
5938  * ixgbe_remove is called by the PCI subsystem to alert the driver
5939  * that it should release a PCI device.  The could be caused by a
5940  * Hot-Plug event, or because the driver is going to be removed from
5941  * memory.
5942  **/
5943 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5944 {
5945         struct net_device *netdev = pci_get_drvdata(pdev);
5946         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5947
5948         set_bit(__IXGBE_DOWN, &adapter->state);
5949         /* clear the module not found bit to make sure the worker won't
5950          * reschedule
5951          */
5952         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5953         del_timer_sync(&adapter->watchdog_timer);
5954
5955         del_timer_sync(&adapter->sfp_timer);
5956         cancel_work_sync(&adapter->watchdog_task);
5957         cancel_work_sync(&adapter->sfp_task);
5958         cancel_work_sync(&adapter->multispeed_fiber_task);
5959         cancel_work_sync(&adapter->sfp_config_module_task);
5960         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5961             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5962                 cancel_work_sync(&adapter->fdir_reinit_task);
5963         flush_scheduled_work();
5964
5965 #ifdef CONFIG_IXGBE_DCA
5966         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5967                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5968                 dca_remove_requester(&pdev->dev);
5969                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5970         }
5971
5972 #endif
5973 #ifdef IXGBE_FCOE
5974         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5975                 ixgbe_cleanup_fcoe(adapter);
5976
5977 #endif /* IXGBE_FCOE */
5978
5979         /* remove the added san mac */
5980         ixgbe_del_sanmac_netdev(netdev);
5981
5982         if (netdev->reg_state == NETREG_REGISTERED)
5983                 unregister_netdev(netdev);
5984
5985         ixgbe_clear_interrupt_scheme(adapter);
5986
5987         ixgbe_release_hw_control(adapter);
5988
5989         iounmap(adapter->hw.hw_addr);
5990         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5991                                      IORESOURCE_MEM));
5992
5993         DPRINTK(PROBE, INFO, "complete\n");
5994
5995         free_netdev(netdev);
5996
5997         pci_disable_pcie_error_reporting(pdev);
5998
5999         pci_disable_device(pdev);
6000 }
6001
6002 /**
6003  * ixgbe_io_error_detected - called when PCI error is detected
6004  * @pdev: Pointer to PCI device
6005  * @state: The current pci connection state
6006  *
6007  * This function is called after a PCI bus error affecting
6008  * this device has been detected.
6009  */
6010 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6011                                                 pci_channel_state_t state)
6012 {
6013         struct net_device *netdev = pci_get_drvdata(pdev);
6014         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6015
6016         netif_device_detach(netdev);
6017
6018         if (state == pci_channel_io_perm_failure)
6019                 return PCI_ERS_RESULT_DISCONNECT;
6020
6021         if (netif_running(netdev))
6022                 ixgbe_down(adapter);
6023         pci_disable_device(pdev);
6024
6025         /* Request a slot reset. */
6026         return PCI_ERS_RESULT_NEED_RESET;
6027 }
6028
6029 /**
6030  * ixgbe_io_slot_reset - called after the pci bus has been reset.
6031  * @pdev: Pointer to PCI device
6032  *
6033  * Restart the card from scratch, as if from a cold-boot.
6034  */
6035 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6036 {
6037         struct net_device *netdev = pci_get_drvdata(pdev);
6038         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6039         pci_ers_result_t result;
6040         int err;
6041
6042         if (pci_enable_device_mem(pdev)) {
6043                 DPRINTK(PROBE, ERR,
6044                         "Cannot re-enable PCI device after reset.\n");
6045                 result = PCI_ERS_RESULT_DISCONNECT;
6046         } else {
6047                 pci_set_master(pdev);
6048                 pci_restore_state(pdev);
6049                 pci_save_state(pdev);
6050
6051                 pci_wake_from_d3(pdev, false);
6052
6053                 ixgbe_reset(adapter);
6054                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6055                 result = PCI_ERS_RESULT_RECOVERED;
6056         }
6057
6058         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6059         if (err) {
6060                 dev_err(&pdev->dev,
6061                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
6062                 /* non-fatal, continue */
6063         }
6064
6065         return result;
6066 }
6067
6068 /**
6069  * ixgbe_io_resume - called when traffic can start flowing again.
6070  * @pdev: Pointer to PCI device
6071  *
6072  * This callback is called when the error recovery driver tells us that
6073  * its OK to resume normal operation.
6074  */
6075 static void ixgbe_io_resume(struct pci_dev *pdev)
6076 {
6077         struct net_device *netdev = pci_get_drvdata(pdev);
6078         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6079
6080         if (netif_running(netdev)) {
6081                 if (ixgbe_up(adapter)) {
6082                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
6083                         return;
6084                 }
6085         }
6086
6087         netif_device_attach(netdev);
6088 }
6089
6090 static struct pci_error_handlers ixgbe_err_handler = {
6091         .error_detected = ixgbe_io_error_detected,
6092         .slot_reset = ixgbe_io_slot_reset,
6093         .resume = ixgbe_io_resume,
6094 };
6095
6096 static struct pci_driver ixgbe_driver = {
6097         .name     = ixgbe_driver_name,
6098         .id_table = ixgbe_pci_tbl,
6099         .probe    = ixgbe_probe,
6100         .remove   = __devexit_p(ixgbe_remove),
6101 #ifdef CONFIG_PM
6102         .suspend  = ixgbe_suspend,
6103         .resume   = ixgbe_resume,
6104 #endif
6105         .shutdown = ixgbe_shutdown,
6106         .err_handler = &ixgbe_err_handler
6107 };
6108
6109 /**
6110  * ixgbe_init_module - Driver Registration Routine
6111  *
6112  * ixgbe_init_module is the first routine called when the driver is
6113  * loaded. All it does is register with the PCI subsystem.
6114  **/
6115 static int __init ixgbe_init_module(void)
6116 {
6117         int ret;
6118         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
6119                ixgbe_driver_string, ixgbe_driver_version);
6120
6121         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6122
6123 #ifdef CONFIG_IXGBE_DCA
6124         dca_register_notify(&dca_notifier);
6125 #endif
6126
6127         ret = pci_register_driver(&ixgbe_driver);
6128         return ret;
6129 }
6130
6131 module_init(ixgbe_init_module);
6132
6133 /**
6134  * ixgbe_exit_module - Driver Exit Cleanup Routine
6135  *
6136  * ixgbe_exit_module is called just before the driver is removed
6137  * from memory.
6138  **/
6139 static void __exit ixgbe_exit_module(void)
6140 {
6141 #ifdef CONFIG_IXGBE_DCA
6142         dca_unregister_notify(&dca_notifier);
6143 #endif
6144         pci_unregister_driver(&ixgbe_driver);
6145 }
6146
6147 #ifdef CONFIG_IXGBE_DCA
6148 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6149                             void *p)
6150 {
6151         int ret_val;
6152
6153         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6154                                          __ixgbe_notify_dca);
6155
6156         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6157 }
6158
6159 #endif /* CONFIG_IXGBE_DCA */
6160 #ifdef DEBUG
6161 /**
6162  * ixgbe_get_hw_dev_name - return device name string
6163  * used by hardware layer to print debugging information
6164  **/
6165 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6166 {
6167         struct ixgbe_adapter *adapter = hw->back;
6168         return adapter->netdev->name;
6169 }
6170
6171 #endif
6172 module_exit(ixgbe_exit_module);
6173
6174 /* ixgbe_main.c */