drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42
  43 #include "ixgbe.h"
  44 #include "ixgbe_common.h"
  45
  46 char ixgbe_driver_name[] = "ixgbe";
  47 static const char ixgbe_driver_string[] =
  48                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  49
  50 #define DRV_VERSION "2.0.8-k2"
  51 const char ixgbe_driver_version[] = DRV_VERSION;
  52 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  53
  54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  55         [board_82598] = &ixgbe_82598_info,
  56         [board_82599] = &ixgbe_82599_info,
  57 };
  58
  59 /* ixgbe_pci_tbl - PCI Device ID Table
  60  *
  61  * Wildcard entries (PCI_ANY_ID) should come last
  62  * Last entry must be all 0s
  63  *
  64  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  65  *   Class, Class Mask, private data (not used) }
  66  */
  67 static struct pci_device_id ixgbe_pci_tbl[] = {
  68         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  69          board_82598 },
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  91          board_82599 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  93          board_82599 },
  94
  95         /* required last entry */
  96         {0, }
  97 };
  98 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
  99
 100 #ifdef CONFIG_IXGBE_DCA
 101 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 102                             void *p);
 103 static struct notifier_block dca_notifier = {
 104         .notifier_call = ixgbe_notify_dca,
 105         .next          = NULL,
 106         .priority      = 0
 107 };
 108 #endif
 109
 110 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 111 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 112 MODULE_LICENSE("GPL");
 113 MODULE_VERSION(DRV_VERSION);
 114
 115 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 116
 117 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 118 {
 119         u32 ctrl_ext;
 120
 121         /* Let firmware take over control of h/w */
 122         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 123         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 124                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 125 }
 126
 127 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 128 {
 129         u32 ctrl_ext;
 130
 131         /* Let firmware know the driver has taken over */
 132         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 133         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 134                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 135 }
 136
 137 /*
 138  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 139  * @adapter: pointer to adapter struct
 140  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 141  * @queue: queue to map the corresponding interrupt to
 142  * @msix_vector: the vector to map to the corresponding queue
 143  *
 144  */
 145 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 146                            u8 queue, u8 msix_vector)
 147 {
 148         u32 ivar, index;
 149         struct ixgbe_hw *hw = &adapter->hw;
 150         switch (hw->mac.type) {
 151         case ixgbe_mac_82598EB:
 152                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 153                 if (direction == -1)
 154                         direction = 0;
 155                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 156                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 157                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 158                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 159                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 160                 break;
 161         case ixgbe_mac_82599EB:
 162                 if (direction == -1) {
 163                         /* other causes */
 164                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 165                         index = ((queue & 1) * 8);
 166                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 167                         ivar &= ~(0xFF << index);
 168                         ivar |= (msix_vector << index);
 169                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 170                         break;
 171                 } else {
 172                         /* tx or rx causes */
 173                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 174                         index = ((16 * (queue & 1)) + (8 * direction));
 175                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 176                         ivar &= ~(0xFF << index);
 177                         ivar |= (msix_vector << index);
 178                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 179                         break;
 180                 }
 181         default:
 182                 break;
 183         }
 184 }
 185
 186 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 187                                              struct ixgbe_tx_buffer
 188                                              *tx_buffer_info)
 189 {
 190         if (tx_buffer_info->dma) {
 191                 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
 192                                tx_buffer_info->length, PCI_DMA_TODEVICE);
 193                 tx_buffer_info->dma = 0;
 194         }
 195         if (tx_buffer_info->skb) {
 196                 dev_kfree_skb_any(tx_buffer_info->skb);
 197                 tx_buffer_info->skb = NULL;
 198         }
 199         /* tx_buffer_info must be completely set up in the transmit path */
 200 }
 201
 202 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 203                                        struct ixgbe_ring *tx_ring,
 204                                        unsigned int eop)
 205 {
 206         struct ixgbe_hw *hw = &adapter->hw;
 207         u32 head, tail;
 208
 209         /* Detect a transmit hang in hardware, this serializes the
 210          * check with the clearing of time_stamp and movement of eop */
 211         head = IXGBE_READ_REG(hw, tx_ring->head);
 212         tail = IXGBE_READ_REG(hw, tx_ring->tail);
 213         adapter->detect_tx_hung = false;
 214         if ((head != tail) &&
 215             tx_ring->tx_buffer_info[eop].time_stamp &&
 216             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 217             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 218                 /* detected Tx unit hang */
 219                 union ixgbe_adv_tx_desc *tx_desc;
 220                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 221                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 222                         "  Tx Queue             <%d>\n"
 223                         "  TDH, TDT             <%x>, <%x>\n"
 224                         "  next_to_use          <%x>\n"
 225                         "  next_to_clean        <%x>\n"
 226                         "tx_buffer_info[next_to_clean]\n"
 227                         "  time_stamp           <%lx>\n"
 228                         "  jiffies              <%lx>\n",
 229                         tx_ring->queue_index,
 230                         head, tail,
 231                         tx_ring->next_to_use, eop,
 232                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 233                 return true;
 234         }
 235
 236         return false;
 237 }
 238
 239 #define IXGBE_MAX_TXD_PWR       14
 240 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 241
 242 /* Tx Descriptors needed, worst case */
 243 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 244                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 245 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 246         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 247
 248 static void ixgbe_tx_timeout(struct net_device *netdev);
 249
 250 /**
 251  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 252  * @adapter: board private structure
 253  * @tx_ring: tx ring to clean
 254  **/
 255 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
 256                                struct ixgbe_ring *tx_ring)
 257 {
 258         struct net_device *netdev = adapter->netdev;
 259         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 260         struct ixgbe_tx_buffer *tx_buffer_info;
 261         unsigned int i, eop, count = 0;
 262         unsigned int total_bytes = 0, total_packets = 0;
 263
 264         i = tx_ring->next_to_clean;
 265         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 266         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 267
 268         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 269                (count < tx_ring->count)) {
 270                 bool cleaned = false;
 271                 for ( ; !cleaned; count++) {
 272                         struct sk_buff *skb;
 273                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 274                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 275                         cleaned = (i == eop);
 276                         skb = tx_buffer_info->skb;
 277
 278                         if (cleaned && skb) {
 279                                 unsigned int segs, bytecount;
 280
 281                                 /* gso_segs is currently only valid for tcp */
 282                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 283                                 /* multiply data chunks by size of headers */
 284                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
 285                                             skb->len;
 286                                 total_packets += segs;
 287                                 total_bytes += bytecount;
 288                         }
 289
 290                         ixgbe_unmap_and_free_tx_resource(adapter,
 291                                                          tx_buffer_info);
 292
 293                         tx_desc->wb.status = 0;
 294
 295                         i++;
 296                         if (i == tx_ring->count)
 297                                 i = 0;
 298                 }
 299
 300                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 301                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 302         }
 303
 304         tx_ring->next_to_clean = i;
 305
 306 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 307         if (unlikely(count && netif_carrier_ok(netdev) &&
 308                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 309                 /* Make sure that anybody stopping the queue after this
 310                  * sees the new next_to_clean.
 311                  */
 312                 smp_mb();
 313                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 314                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 315                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 316                         ++adapter->restart_queue;
 317                 }
 318         }
 319
 320         if (adapter->detect_tx_hung) {
 321                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 322                         /* schedule immediate reset if we believe we hung */
 323                         DPRINTK(PROBE, INFO,
 324                                 "tx hang %d detected, resetting adapter\n",
 325                                 adapter->tx_timeout_count + 1);
 326                         ixgbe_tx_timeout(adapter->netdev);
 327                 }
 328         }
 329
 330         /* re-arm the interrupt */
 331         if ((total_packets >= tx_ring->work_limit) ||
 332             (count == tx_ring->count))
 333                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
 334
 335         tx_ring->total_bytes += total_bytes;
 336         tx_ring->total_packets += total_packets;
 337         tx_ring->stats.packets += total_packets;
 338         tx_ring->stats.bytes += total_bytes;
 339         adapter->net_stats.tx_bytes += total_bytes;
 340         adapter->net_stats.tx_packets += total_packets;
 341         return (total_packets ? true : false);
 342 }
 343
 344 #ifdef CONFIG_IXGBE_DCA
 345 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 346                                 struct ixgbe_ring *rx_ring)
 347 {
 348         u32 rxctrl;
 349         int cpu = get_cpu();
 350         int q = rx_ring - adapter->rx_ring;
 351
 352         if (rx_ring->cpu != cpu) {
 353                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 354                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 355                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 356                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 357                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 358                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 359                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 360                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 361                 }
 362                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 363                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 364                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 365                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 366                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 367                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 368                 rx_ring->cpu = cpu;
 369         }
 370         put_cpu();
 371 }
 372
 373 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 374                                 struct ixgbe_ring *tx_ring)
 375 {
 376         u32 txctrl;
 377         int cpu = get_cpu();
 378         int q = tx_ring - adapter->tx_ring;
 379
 380         if (tx_ring->cpu != cpu) {
 381                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 382                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 383                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 384                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 385                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 386                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 387                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 388                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 389                 }
 390                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 391                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 392                 tx_ring->cpu = cpu;
 393         }
 394         put_cpu();
 395 }
 396
 397 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 398 {
 399         int i;
 400
 401         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 402                 return;
 403
 404         for (i = 0; i < adapter->num_tx_queues; i++) {
 405                 adapter->tx_ring[i].cpu = -1;
 406                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 407         }
 408         for (i = 0; i < adapter->num_rx_queues; i++) {
 409                 adapter->rx_ring[i].cpu = -1;
 410                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 411         }
 412 }
 413
 414 static int __ixgbe_notify_dca(struct device *dev, void *data)
 415 {
 416         struct net_device *netdev = dev_get_drvdata(dev);
 417         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 418         unsigned long event = *(unsigned long *)data;
 419
 420         switch (event) {
 421         case DCA_PROVIDER_ADD:
 422                 /* if we're already enabled, don't do it again */
 423                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 424                         break;
 425                 /* Always use CB2 mode, difference is masked
 426                  * in the CB driver. */
 427                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 428                 if (dca_add_requester(dev) == 0) {
 429                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 430                         ixgbe_setup_dca(adapter);
 431                         break;
 432                 }
 433                 /* Fall Through since DCA is disabled. */
 434         case DCA_PROVIDER_REMOVE:
 435                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 436                         dca_remove_requester(dev);
 437                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 438                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 439                 }
 440                 break;
 441         }
 442
 443         return 0;
 444 }
 445
 446 #endif /* CONFIG_IXGBE_DCA */
 447 /**
 448  * ixgbe_receive_skb - Send a completed packet up the stack
 449  * @adapter: board private structure
 450  * @skb: packet to send up
 451  * @status: hardware indication of status of receive
 452  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 453  * @rx_desc: rx descriptor
 454  **/
 455 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 456                               struct sk_buff *skb, u8 status,
 457                               union ixgbe_adv_rx_desc *rx_desc)
 458 {
 459         struct ixgbe_adapter *adapter = q_vector->adapter;
 460         struct napi_struct *napi = &q_vector->napi;
 461         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 462         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 463
 464         skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
 465         if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
 466                 if (adapter->vlgrp && is_vlan && (tag != 0))
 467                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 468                 else
 469                         napi_gro_receive(napi, skb);
 470         } else {
 471                 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 472                         if (adapter->vlgrp && is_vlan && (tag != 0))
 473                                 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
 474                         else
 475                                 netif_receive_skb(skb);
 476                 } else {
 477                         if (adapter->vlgrp && is_vlan && (tag != 0))
 478                                 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 479                         else
 480                                 netif_rx(skb);
 481                 }
 482         }
 483 }
 484
 485 /**
 486  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 487  * @adapter: address of board private structure
 488  * @status_err: hardware indication of status of receive
 489  * @skb: skb currently being received and modified
 490  **/
 491 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 492                                      u32 status_err, struct sk_buff *skb)
 493 {
 494         skb->ip_summed = CHECKSUM_NONE;
 495
 496         /* Rx csum disabled */
 497         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 498                 return;
 499
 500         /* if IP and error */
 501         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 502             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 503                 adapter->hw_csum_rx_error++;
 504                 return;
 505         }
 506
 507         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 508                 return;
 509
 510         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 511                 adapter->hw_csum_rx_error++;
 512                 return;
 513         }
 514
 515         /* It must be a TCP or UDP packet with a valid checksum */
 516         skb->ip_summed = CHECKSUM_UNNECESSARY;
 517         adapter->hw_csum_rx_good++;
 518 }
 519
 520 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 521                                          struct ixgbe_ring *rx_ring, u32 val)
 522 {
 523         /*
 524          * Force memory writes to complete before letting h/w
 525          * know there are new descriptors to fetch.  (Only
 526          * applicable for weak-ordered memory model archs,
 527          * such as IA-64).
 528          */
 529         wmb();
 530         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 531 }
 532
 533 /**
 534  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 535  * @adapter: address of board private structure
 536  **/
 537 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 538                                    struct ixgbe_ring *rx_ring,
 539                                    int cleaned_count)
 540 {
 541         struct pci_dev *pdev = adapter->pdev;
 542         union ixgbe_adv_rx_desc *rx_desc;
 543         struct ixgbe_rx_buffer *bi;
 544         unsigned int i;
 545         unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
 546
 547         i = rx_ring->next_to_use;
 548         bi = &rx_ring->rx_buffer_info[i];
 549
 550         while (cleaned_count--) {
 551                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 552
 553                 if (!bi->page_dma &&
 554                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 555                         if (!bi->page) {
 556                                 bi->page = alloc_page(GFP_ATOMIC);
 557                                 if (!bi->page) {
 558                                         adapter->alloc_rx_page_failed++;
 559                                         goto no_buffers;
 560                                 }
 561                                 bi->page_offset = 0;
 562                         } else {
 563                                 /* use a half page if we're re-using */
 564                                 bi->page_offset ^= (PAGE_SIZE / 2);
 565                         }
 566
 567                         bi->page_dma = pci_map_page(pdev, bi->page,
 568                                                     bi->page_offset,
 569                                                     (PAGE_SIZE / 2),
 570                                                     PCI_DMA_FROMDEVICE);
 571                 }
 572
 573                 if (!bi->skb) {
 574                         struct sk_buff *skb;
 575                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
 576
 577                         if (!skb) {
 578                                 adapter->alloc_rx_buff_failed++;
 579                                 goto no_buffers;
 580                         }
 581
 582                         /*
 583                          * Make buffer alignment 2 beyond a 16 byte boundary
 584                          * this will result in a 16 byte aligned IP header after
 585                          * the 14 byte MAC header is removed
 586                          */
 587                         skb_reserve(skb, NET_IP_ALIGN);
 588
 589                         bi->skb = skb;
 590                         bi->dma = pci_map_single(pdev, skb->data, bufsz,
 591                                                  PCI_DMA_FROMDEVICE);
 592                 }
 593                 /* Refresh the desc even if buffer_addrs didn't change because
 594                  * each write-back erases this info. */
 595                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 596                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 597                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 598                 } else {
 599                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 600                 }
 601
 602                 i++;
 603                 if (i == rx_ring->count)
 604                         i = 0;
 605                 bi = &rx_ring->rx_buffer_info[i];
 606         }
 607
 608 no_buffers:
 609         if (rx_ring->next_to_use != i) {
 610                 rx_ring->next_to_use = i;
 611                 if (i-- == 0)
 612                         i = (rx_ring->count - 1);
 613
 614                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 615         }
 616 }
 617
 618 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 619 {
 620         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 621 }
 622
 623 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 624 {
 625         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 626 }
 627
 628 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 629                                struct ixgbe_ring *rx_ring,
 630                                int *work_done, int work_to_do)
 631 {
 632         struct ixgbe_adapter *adapter = q_vector->adapter;
 633         struct pci_dev *pdev = adapter->pdev;
 634         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 635         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 636         struct sk_buff *skb;
 637         unsigned int i;
 638         u32 len, staterr;
 639         u16 hdr_info;
 640         bool cleaned = false;
 641         int cleaned_count = 0;
 642         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 643
 644         i = rx_ring->next_to_clean;
 645         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 646         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 647         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 648
 649         while (staterr & IXGBE_RXD_STAT_DD) {
 650                 u32 upper_len = 0;
 651                 if (*work_done >= work_to_do)
 652                         break;
 653                 (*work_done)++;
 654
 655                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 656                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 657                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 658                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 659                         if (hdr_info & IXGBE_RXDADV_SPH)
 660                                 adapter->rx_hdr_split++;
 661                         if (len > IXGBE_RX_HDR_SIZE)
 662                                 len = IXGBE_RX_HDR_SIZE;
 663                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 664                 } else {
 665                         len = le16_to_cpu(rx_desc->wb.upper.length);
 666                 }
 667
 668                 cleaned = true;
 669                 skb = rx_buffer_info->skb;
 670                 prefetch(skb->data - NET_IP_ALIGN);
 671                 rx_buffer_info->skb = NULL;
 672
 673                 if (len && !skb_shinfo(skb)->nr_frags) {
 674                         pci_unmap_single(pdev, rx_buffer_info->dma,
 675                                          rx_ring->rx_buf_len,
 676                                          PCI_DMA_FROMDEVICE);
 677                         skb_put(skb, len);
 678                 }
 679
 680                 if (upper_len) {
 681                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 682                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 683                         rx_buffer_info->page_dma = 0;
 684                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 685                                            rx_buffer_info->page,
 686                                            rx_buffer_info->page_offset,
 687                                            upper_len);
 688
 689                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 690                             (page_count(rx_buffer_info->page) != 1))
 691                                 rx_buffer_info->page = NULL;
 692                         else
 693                                 get_page(rx_buffer_info->page);
 694
 695                         skb->len += upper_len;
 696                         skb->data_len += upper_len;
 697                         skb->truesize += upper_len;
 698                 }
 699
 700                 i++;
 701                 if (i == rx_ring->count)
 702                         i = 0;
 703                 next_buffer = &rx_ring->rx_buffer_info[i];
 704
 705                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 706                 prefetch(next_rxd);
 707
 708                 cleaned_count++;
 709                 if (staterr & IXGBE_RXD_STAT_EOP) {
 710                         rx_ring->stats.packets++;
 711                         rx_ring->stats.bytes += skb->len;
 712                 } else {
 713                         rx_buffer_info->skb = next_buffer->skb;
 714                         rx_buffer_info->dma = next_buffer->dma;
 715                         next_buffer->skb = skb;
 716                         next_buffer->dma = 0;
 717                         adapter->non_eop_descs++;
 718                         goto next_desc;
 719                 }
 720
 721                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 722                         dev_kfree_skb_irq(skb);
 723                         goto next_desc;
 724                 }
 725
 726                 ixgbe_rx_checksum(adapter, staterr, skb);
 727
 728                 /* probably a little skewed due to removing CRC */
 729                 total_rx_bytes += skb->len;
 730                 total_rx_packets++;
 731
 732                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 733                 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
 734
 735 next_desc:
 736                 rx_desc->wb.upper.status_error = 0;
 737
 738                 /* return some buffers to hardware, one at a time is too slow */
 739                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 740                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 741                         cleaned_count = 0;
 742                 }
 743
 744                 /* use prefetched values */
 745                 rx_desc = next_rxd;
 746                 rx_buffer_info = next_buffer;
 747
 748                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 749         }
 750
 751         rx_ring->next_to_clean = i;
 752         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 753
 754         if (cleaned_count)
 755                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 756
 757         rx_ring->total_packets += total_rx_packets;
 758         rx_ring->total_bytes += total_rx_bytes;
 759         adapter->net_stats.rx_bytes += total_rx_bytes;
 760         adapter->net_stats.rx_packets += total_rx_packets;
 761
 762         return cleaned;
 763 }
 764
 765 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 766 /**
 767  * ixgbe_configure_msix - Configure MSI-X hardware
 768  * @adapter: board private structure
 769  *
 770  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 771  * interrupts.
 772  **/
 773 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 774 {
 775         struct ixgbe_q_vector *q_vector;
 776         int i, j, q_vectors, v_idx, r_idx;
 777         u32 mask;
 778
 779         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 780
 781         /* Populate the IVAR table and set the ITR values to the
 782          * corresponding register.
 783          */
 784         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 785                 q_vector = &adapter->q_vector[v_idx];
 786                 /* XXX for_each_bit(...) */
 787                 r_idx = find_first_bit(q_vector->rxr_idx,
 788                                        adapter->num_rx_queues);
 789
 790                 for (i = 0; i < q_vector->rxr_count; i++) {
 791                         j = adapter->rx_ring[r_idx].reg_idx;
 792                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 793                         r_idx = find_next_bit(q_vector->rxr_idx,
 794                                               adapter->num_rx_queues,
 795                                               r_idx + 1);
 796                 }
 797                 r_idx = find_first_bit(q_vector->txr_idx,
 798                                        adapter->num_tx_queues);
 799
 800                 for (i = 0; i < q_vector->txr_count; i++) {
 801                         j = adapter->tx_ring[r_idx].reg_idx;
 802                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 803                         r_idx = find_next_bit(q_vector->txr_idx,
 804                                               adapter->num_tx_queues,
 805                                               r_idx + 1);
 806                 }
 807
 808                 /* if this is a tx only vector halve the interrupt rate */
 809                 if (q_vector->txr_count && !q_vector->rxr_count)
 810                         q_vector->eitr = (adapter->eitr_param >> 1);
 811                 else
 812                         /* rx only */
 813                         q_vector->eitr = adapter->eitr_param;
 814
 815                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
 816                                 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
 817         }
 818
 819         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 820                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 821                                v_idx);
 822         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 823                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 824         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 825
 826         /* set up to autoclear timer, and the vectors */
 827         mask = IXGBE_EIMS_ENABLE_MASK;
 828         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 829         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 830 }
 831
 832 enum latency_range {
 833         lowest_latency = 0,
 834         low_latency = 1,
 835         bulk_latency = 2,
 836         latency_invalid = 255
 837 };
 838
 839 /**
 840  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 841  * @adapter: pointer to adapter
 842  * @eitr: eitr setting (ints per sec) to give last timeslice
 843  * @itr_setting: current throttle rate in ints/second
 844  * @packets: the number of packets during this measurement interval
 845  * @bytes: the number of bytes during this measurement interval
 846  *
 847  *      Stores a new ITR value based on packets and byte
 848  *      counts during the last interrupt.  The advantage of per interrupt
 849  *      computation is faster updates and more accurate ITR for the current
 850  *      traffic pattern.  Constants in this function were computed
 851  *      based on theoretical maximum wire speed and thresholds were set based
 852  *      on testing data as well as attempting to minimize response time
 853  *      while increasing bulk throughput.
 854  *      this functionality is controlled by the InterruptThrottleRate module
 855  *      parameter (see ixgbe_param.c)
 856  **/
 857 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 858                            u32 eitr, u8 itr_setting,
 859                            int packets, int bytes)
 860 {
 861         unsigned int retval = itr_setting;
 862         u32 timepassed_us;
 863         u64 bytes_perint;
 864
 865         if (packets == 0)
 866                 goto update_itr_done;
 867
 868
 869         /* simple throttlerate management
 870          *    0-20MB/s lowest (100000 ints/s)
 871          *   20-100MB/s low   (20000 ints/s)
 872          *  100-1249MB/s bulk (8000 ints/s)
 873          */
 874         /* what was last interrupt timeslice? */
 875         timepassed_us = 1000000/eitr;
 876         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 877
 878         switch (itr_setting) {
 879         case lowest_latency:
 880                 if (bytes_perint > adapter->eitr_low)
 881                         retval = low_latency;
 882                 break;
 883         case low_latency:
 884                 if (bytes_perint > adapter->eitr_high)
 885                         retval = bulk_latency;
 886                 else if (bytes_perint <= adapter->eitr_low)
 887                         retval = lowest_latency;
 888                 break;
 889         case bulk_latency:
 890                 if (bytes_perint <= adapter->eitr_high)
 891                         retval = low_latency;
 892                 break;
 893         }
 894
 895 update_itr_done:
 896         return retval;
 897 }
 898
 899 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 900 {
 901         struct ixgbe_adapter *adapter = q_vector->adapter;
 902         struct ixgbe_hw *hw = &adapter->hw;
 903         u32 new_itr;
 904         u8 current_itr, ret_itr;
 905         int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
 906                                sizeof(struct ixgbe_q_vector);
 907         struct ixgbe_ring *rx_ring, *tx_ring;
 908
 909         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 910         for (i = 0; i < q_vector->txr_count; i++) {
 911                 tx_ring = &(adapter->tx_ring[r_idx]);
 912                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 913                                            q_vector->tx_itr,
 914                                            tx_ring->total_packets,
 915                                            tx_ring->total_bytes);
 916                 /* if the result for this queue would decrease interrupt
 917                  * rate for this vector then use that result */
 918                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
 919                                     q_vector->tx_itr - 1 : ret_itr);
 920                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 921                                       r_idx + 1);
 922         }
 923
 924         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 925         for (i = 0; i < q_vector->rxr_count; i++) {
 926                 rx_ring = &(adapter->rx_ring[r_idx]);
 927                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
 928                                            q_vector->rx_itr,
 929                                            rx_ring->total_packets,
 930                                            rx_ring->total_bytes);
 931                 /* if the result for this queue would decrease interrupt
 932                  * rate for this vector then use that result */
 933                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
 934                                     q_vector->rx_itr - 1 : ret_itr);
 935                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 936                                       r_idx + 1);
 937         }
 938
 939         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
 940
 941         switch (current_itr) {
 942         /* counts and packets in update_itr are dependent on these numbers */
 943         case lowest_latency:
 944                 new_itr = 100000;
 945                 break;
 946         case low_latency:
 947                 new_itr = 20000; /* aka hwitr = ~200 */
 948                 break;
 949         case bulk_latency:
 950         default:
 951                 new_itr = 8000;
 952                 break;
 953         }
 954
 955         if (new_itr != q_vector->eitr) {
 956                 u32 itr_reg;
 957                 /* do an exponential smoothing */
 958                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
 959                 q_vector->eitr = new_itr;
 960                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
 961                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 962                         /* Resolution is 2 usec on 82599, so halve the rate */
 963                         itr_reg >>= 1;
 964                 /* must write high and low 16 bits to reset counter */
 965                 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
 966                         itr_reg);
 967                 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
 968         }
 969
 970         return;
 971 }
 972
 973 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
 974 {
 975         struct ixgbe_hw *hw = &adapter->hw;
 976
 977         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
 978             (eicr & IXGBE_EICR_GPI_SDP1)) {
 979                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
 980                 /* write to clear the interrupt */
 981                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
 982         }
 983 }
 984
 985 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
 986 {
 987         struct ixgbe_hw *hw = &adapter->hw;
 988
 989         if (eicr & IXGBE_EICR_GPI_SDP1) {
 990                 /* Clear the interrupt */
 991                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
 992                 schedule_work(&adapter->multispeed_fiber_task);
 993         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
 994                 /* Clear the interrupt */
 995                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
 996                 schedule_work(&adapter->sfp_config_module_task);
 997         } else {
 998                 /* Interrupt isn't for us... */
 999                 return;
1000         }
1001 }
1002
1003 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1004 {
1005         struct ixgbe_hw *hw = &adapter->hw;
1006
1007         adapter->lsc_int++;
1008         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1009         adapter->link_check_timeout = jiffies;
1010         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1011                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1012                 schedule_work(&adapter->watchdog_task);
1013         }
1014 }
1015
1016 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1017 {
1018         struct net_device *netdev = data;
1019         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1020         struct ixgbe_hw *hw = &adapter->hw;
1021         u32 eicr;
1022
1023         /*
1024          * Workaround for Silicon errata.  Use clear-by-write instead
1025          * of clear-by-read.  Reading with EICS will return the
1026          * interrupt causes without clearing, which later be done
1027          * with the write to EICR.
1028          */
1029         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1030         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1031
1032         if (eicr & IXGBE_EICR_LSC)
1033                 ixgbe_check_lsc(adapter);
1034
1035         if (hw->mac.type == ixgbe_mac_82598EB)
1036                 ixgbe_check_fan_failure(adapter, eicr);
1037
1038         if (hw->mac.type == ixgbe_mac_82599EB)
1039                 ixgbe_check_sfp_event(adapter, eicr);
1040         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1041                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1042
1043         return IRQ_HANDLED;
1044 }
1045
1046 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1047 {
1048         struct ixgbe_q_vector *q_vector = data;
1049         struct ixgbe_adapter  *adapter = q_vector->adapter;
1050         struct ixgbe_ring     *tx_ring;
1051         int i, r_idx;
1052
1053         if (!q_vector->txr_count)
1054                 return IRQ_HANDLED;
1055
1056         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1057         for (i = 0; i < q_vector->txr_count; i++) {
1058                 tx_ring = &(adapter->tx_ring[r_idx]);
1059 #ifdef CONFIG_IXGBE_DCA
1060                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1061                         ixgbe_update_tx_dca(adapter, tx_ring);
1062 #endif
1063                 tx_ring->total_bytes = 0;
1064                 tx_ring->total_packets = 0;
1065                 ixgbe_clean_tx_irq(adapter, tx_ring);
1066                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1067                                       r_idx + 1);
1068         }
1069
1070         return IRQ_HANDLED;
1071 }
1072
1073 /**
1074  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1075  * @irq: unused
1076  * @data: pointer to our q_vector struct for this interrupt vector
1077  **/
1078 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1079 {
1080         struct ixgbe_q_vector *q_vector = data;
1081         struct ixgbe_adapter  *adapter = q_vector->adapter;
1082         struct ixgbe_ring  *rx_ring;
1083         int r_idx;
1084         int i;
1085
1086         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1087         for (i = 0;  i < q_vector->rxr_count; i++) {
1088                 rx_ring = &(adapter->rx_ring[r_idx]);
1089                 rx_ring->total_bytes = 0;
1090                 rx_ring->total_packets = 0;
1091                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1092                                       r_idx + 1);
1093         }
1094
1095         if (!q_vector->rxr_count)
1096                 return IRQ_HANDLED;
1097
1098         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1099         rx_ring = &(adapter->rx_ring[r_idx]);
1100         /* disable interrupts on this vector only */
1101         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1102         napi_schedule(&q_vector->napi);
1103
1104         return IRQ_HANDLED;
1105 }
1106
1107 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1108 {
1109         ixgbe_msix_clean_rx(irq, data);
1110         ixgbe_msix_clean_tx(irq, data);
1111
1112         return IRQ_HANDLED;
1113 }
1114
1115 /**
1116  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1117  * @napi: napi struct with our devices info in it
1118  * @budget: amount of work driver is allowed to do this pass, in packets
1119  *
1120  * This function is optimized for cleaning one queue only on a single
1121  * q_vector!!!
1122  **/
1123 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1124 {
1125         struct ixgbe_q_vector *q_vector =
1126                                container_of(napi, struct ixgbe_q_vector, napi);
1127         struct ixgbe_adapter *adapter = q_vector->adapter;
1128         struct ixgbe_ring *rx_ring = NULL;
1129         int work_done = 0;
1130         long r_idx;
1131
1132         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1133         rx_ring = &(adapter->rx_ring[r_idx]);
1134 #ifdef CONFIG_IXGBE_DCA
1135         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1136                 ixgbe_update_rx_dca(adapter, rx_ring);
1137 #endif
1138
1139         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1140
1141         /* If all Rx work done, exit the polling mode */
1142         if (work_done < budget) {
1143                 napi_complete(napi);
1144                 if (adapter->itr_setting & 3)
1145                         ixgbe_set_itr_msix(q_vector);
1146                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1147                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1148         }
1149
1150         return work_done;
1151 }
1152
1153 /**
1154  * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1155  * @napi: napi struct with our devices info in it
1156  * @budget: amount of work driver is allowed to do this pass, in packets
1157  *
1158  * This function will clean more than one rx queue associated with a
1159  * q_vector.
1160  **/
1161 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1162 {
1163         struct ixgbe_q_vector *q_vector =
1164                                container_of(napi, struct ixgbe_q_vector, napi);
1165         struct ixgbe_adapter *adapter = q_vector->adapter;
1166         struct ixgbe_ring *rx_ring = NULL;
1167         int work_done = 0, i;
1168         long r_idx;
1169         u16 enable_mask = 0;
1170
1171         /* attempt to distribute budget to each queue fairly, but don't allow
1172          * the budget to go below 1 because we'll exit polling */
1173         budget /= (q_vector->rxr_count ?: 1);
1174         budget = max(budget, 1);
1175         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1176         for (i = 0; i < q_vector->rxr_count; i++) {
1177                 rx_ring = &(adapter->rx_ring[r_idx]);
1178 #ifdef CONFIG_IXGBE_DCA
1179                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1180                         ixgbe_update_rx_dca(adapter, rx_ring);
1181 #endif
1182                 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1183                 enable_mask |= rx_ring->v_idx;
1184                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1185                                       r_idx + 1);
1186         }
1187
1188         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1189         rx_ring = &(adapter->rx_ring[r_idx]);
1190         /* If all Rx work done, exit the polling mode */
1191         if (work_done < budget) {
1192                 napi_complete(napi);
1193                 if (adapter->itr_setting & 3)
1194                         ixgbe_set_itr_msix(q_vector);
1195                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1196                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1197                 return 0;
1198         }
1199
1200         return work_done;
1201 }
1202 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1203                                      int r_idx)
1204 {
1205         a->q_vector[v_idx].adapter = a;
1206         set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1207         a->q_vector[v_idx].rxr_count++;
1208         a->rx_ring[r_idx].v_idx = 1 << v_idx;
1209 }
1210
1211 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1212                                      int r_idx)
1213 {
1214         a->q_vector[v_idx].adapter = a;
1215         set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1216         a->q_vector[v_idx].txr_count++;
1217         a->tx_ring[r_idx].v_idx = 1 << v_idx;
1218 }
1219
1220 /**
1221  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1222  * @adapter: board private structure to initialize
1223  * @vectors: allotted vector count for descriptor rings
1224  *
1225  * This function maps descriptor rings to the queue-specific vectors
1226  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1227  * one vector per ring/queue, but on a constrained vector budget, we
1228  * group the rings as "efficiently" as possible.  You would add new
1229  * mapping configurations in here.
1230  **/
1231 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1232                                       int vectors)
1233 {
1234         int v_start = 0;
1235         int rxr_idx = 0, txr_idx = 0;
1236         int rxr_remaining = adapter->num_rx_queues;
1237         int txr_remaining = adapter->num_tx_queues;
1238         int i, j;
1239         int rqpv, tqpv;
1240         int err = 0;
1241
1242         /* No mapping required if MSI-X is disabled. */
1243         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1244                 goto out;
1245
1246         /*
1247          * The ideal configuration...
1248          * We have enough vectors to map one per queue.
1249          */
1250         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1251                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1252                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1253
1254                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1255                         map_vector_to_txq(adapter, v_start, txr_idx);
1256
1257                 goto out;
1258         }
1259
1260         /*
1261          * If we don't have enough vectors for a 1-to-1
1262          * mapping, we'll have to group them so there are
1263          * multiple queues per vector.
1264          */
1265         /* Re-adjusting *qpv takes care of the remainder. */
1266         for (i = v_start; i < vectors; i++) {
1267                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1268                 for (j = 0; j < rqpv; j++) {
1269                         map_vector_to_rxq(adapter, i, rxr_idx);
1270                         rxr_idx++;
1271                         rxr_remaining--;
1272                 }
1273         }
1274         for (i = v_start; i < vectors; i++) {
1275                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1276                 for (j = 0; j < tqpv; j++) {
1277                         map_vector_to_txq(adapter, i, txr_idx);
1278                         txr_idx++;
1279                         txr_remaining--;
1280                 }
1281         }
1282
1283 out:
1284         return err;
1285 }
1286
1287 /**
1288  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1289  * @adapter: board private structure
1290  *
1291  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1292  * interrupts from the kernel.
1293  **/
1294 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1295 {
1296         struct net_device *netdev = adapter->netdev;
1297         irqreturn_t (*handler)(int, void *);
1298         int i, vector, q_vectors, err;
1299         int ri=0, ti=0;
1300
1301         /* Decrement for Other and TCP Timer vectors */
1302         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1303
1304         /* Map the Tx/Rx rings to the vectors we were allotted. */
1305         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1306         if (err)
1307                 goto out;
1308
1309 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1310                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1311                          &ixgbe_msix_clean_many)
1312         for (vector = 0; vector < q_vectors; vector++) {
1313                 handler = SET_HANDLER(&adapter->q_vector[vector]);
1314
1315                 if(handler == &ixgbe_msix_clean_rx) {
1316                         sprintf(adapter->name[vector], "%s-%s-%d",
1317                                 netdev->name, "rx", ri++);
1318                 }
1319                 else if(handler == &ixgbe_msix_clean_tx) {
1320                         sprintf(adapter->name[vector], "%s-%s-%d",
1321                                 netdev->name, "tx", ti++);
1322                 }
1323                 else
1324                         sprintf(adapter->name[vector], "%s-%s-%d",
1325                                 netdev->name, "TxRx", vector);
1326
1327                 err = request_irq(adapter->msix_entries[vector].vector,
1328                                   handler, 0, adapter->name[vector],
1329                                   &(adapter->q_vector[vector]));
1330                 if (err) {
1331                         DPRINTK(PROBE, ERR,
1332                                 "request_irq failed for MSIX interrupt "
1333                                 "Error: %d\n", err);
1334                         goto free_queue_irqs;
1335                 }
1336         }
1337
1338         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1339         err = request_irq(adapter->msix_entries[vector].vector,
1340                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1341         if (err) {
1342                 DPRINTK(PROBE, ERR,
1343                         "request_irq for msix_lsc failed: %d\n", err);
1344                 goto free_queue_irqs;
1345         }
1346
1347         return 0;
1348
1349 free_queue_irqs:
1350         for (i = vector - 1; i >= 0; i--)
1351                 free_irq(adapter->msix_entries[--vector].vector,
1352                          &(adapter->q_vector[i]));
1353         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1354         pci_disable_msix(adapter->pdev);
1355         kfree(adapter->msix_entries);
1356         adapter->msix_entries = NULL;
1357 out:
1358         return err;
1359 }
1360
1361 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1362 {
1363         struct ixgbe_hw *hw = &adapter->hw;
1364         struct ixgbe_q_vector *q_vector = adapter->q_vector;
1365         u8 current_itr;
1366         u32 new_itr = q_vector->eitr;
1367         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1368         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1369
1370         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1371                                             q_vector->tx_itr,
1372                                             tx_ring->total_packets,
1373                                             tx_ring->total_bytes);
1374         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1375                                             q_vector->rx_itr,
1376                                             rx_ring->total_packets,
1377                                             rx_ring->total_bytes);
1378
1379         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1380
1381         switch (current_itr) {
1382         /* counts and packets in update_itr are dependent on these numbers */
1383         case lowest_latency:
1384                 new_itr = 100000;
1385                 break;
1386         case low_latency:
1387                 new_itr = 20000; /* aka hwitr = ~200 */
1388                 break;
1389         case bulk_latency:
1390                 new_itr = 8000;
1391                 break;
1392         default:
1393                 break;
1394         }
1395
1396         if (new_itr != q_vector->eitr) {
1397                 u32 itr_reg;
1398                 /* do an exponential smoothing */
1399                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1400                 q_vector->eitr = new_itr;
1401                 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1402                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1403                         /* Resolution is 2 usec on 82599, so halve the rate */
1404                         itr_reg >>= 1;
1405                 /* must write high and low 16 bits to reset counter */
1406                 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1407         }
1408
1409         return;
1410 }
1411
1412 /**
1413  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1414  * @adapter: board private structure
1415  **/
1416 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1417 {
1418         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1419         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1420                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1421                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(2), ~0);
1422         }
1423         IXGBE_WRITE_FLUSH(&adapter->hw);
1424         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1425                 int i;
1426                 for (i = 0; i < adapter->num_msix_vectors; i++)
1427                         synchronize_irq(adapter->msix_entries[i].vector);
1428         } else {
1429                 synchronize_irq(adapter->pdev->irq);
1430         }
1431 }
1432
1433 /**
1434  * ixgbe_irq_enable - Enable default interrupt generation settings
1435  * @adapter: board private structure
1436  **/
1437 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1438 {
1439         u32 mask;
1440         mask = IXGBE_EIMS_ENABLE_MASK;
1441         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1442                 mask |= IXGBE_EIMS_GPI_SDP1;
1443         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1444                 mask |= IXGBE_EIMS_GPI_SDP1;
1445                 mask |= IXGBE_EIMS_GPI_SDP2;
1446         }
1447
1448         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1449         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1450                 /* enable the rest of the queue vectors */
1451                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1),
1452                                 (IXGBE_EIMS_RTX_QUEUE << 16));
1453                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(2),
1454                                 ((IXGBE_EIMS_RTX_QUEUE << 16) |
1455                                   IXGBE_EIMS_RTX_QUEUE));
1456         }
1457         IXGBE_WRITE_FLUSH(&adapter->hw);
1458 }
1459
1460 /**
1461  * ixgbe_intr - legacy mode Interrupt Handler
1462  * @irq: interrupt number
1463  * @data: pointer to a network interface device structure
1464  **/
1465 static irqreturn_t ixgbe_intr(int irq, void *data)
1466 {
1467         struct net_device *netdev = data;
1468         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1469         struct ixgbe_hw *hw = &adapter->hw;
1470         u32 eicr;
1471
1472         /*
1473          * Workaround for silicon errata.  Mask the interrupts
1474          * before the read of EICR.
1475          */
1476         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1477
1478         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1479          * therefore no explict interrupt disable is necessary */
1480         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1481         if (!eicr) {
1482                 /* shared interrupt alert!
1483                  * make sure interrupts are enabled because the read will
1484                  * have disabled interrupts due to EIAM */
1485                 ixgbe_irq_enable(adapter);
1486                 return IRQ_NONE;        /* Not our interrupt */
1487         }
1488
1489         if (eicr & IXGBE_EICR_LSC)
1490                 ixgbe_check_lsc(adapter);
1491
1492         if (hw->mac.type == ixgbe_mac_82599EB)
1493                 ixgbe_check_sfp_event(adapter, eicr);
1494
1495         ixgbe_check_fan_failure(adapter, eicr);
1496
1497         if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
1498                 adapter->tx_ring[0].total_packets = 0;
1499                 adapter->tx_ring[0].total_bytes = 0;
1500                 adapter->rx_ring[0].total_packets = 0;
1501                 adapter->rx_ring[0].total_bytes = 0;
1502                 /* would disable interrupts here but EIAM disabled it */
1503                 __napi_schedule(&adapter->q_vector[0].napi);
1504         }
1505
1506         return IRQ_HANDLED;
1507 }
1508
1509 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1510 {
1511         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1512
1513         for (i = 0; i < q_vectors; i++) {
1514                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1515                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1516                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1517                 q_vector->rxr_count = 0;
1518                 q_vector->txr_count = 0;
1519         }
1520 }
1521
1522 /**
1523  * ixgbe_request_irq - initialize interrupts
1524  * @adapter: board private structure
1525  *
1526  * Attempts to configure interrupts using the best available
1527  * capabilities of the hardware and kernel.
1528  **/
1529 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1530 {
1531         struct net_device *netdev = adapter->netdev;
1532         int err;
1533
1534         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1535                 err = ixgbe_request_msix_irqs(adapter);
1536         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1537                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1538                                   netdev->name, netdev);
1539         } else {
1540                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1541                                   netdev->name, netdev);
1542         }
1543
1544         if (err)
1545                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1546
1547         return err;
1548 }
1549
1550 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1551 {
1552         struct net_device *netdev = adapter->netdev;
1553
1554         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1555                 int i, q_vectors;
1556
1557                 q_vectors = adapter->num_msix_vectors;
1558
1559                 i = q_vectors - 1;
1560                 free_irq(adapter->msix_entries[i].vector, netdev);
1561
1562                 i--;
1563                 for (; i >= 0; i--) {
1564                         free_irq(adapter->msix_entries[i].vector,
1565                                  &(adapter->q_vector[i]));
1566                 }
1567
1568                 ixgbe_reset_q_vectors(adapter);
1569         } else {
1570                 free_irq(adapter->pdev->irq, netdev);
1571         }
1572 }
1573
1574 /**
1575  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1576  *
1577  **/
1578 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1579 {
1580         struct ixgbe_hw *hw = &adapter->hw;
1581
1582         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1583                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1584
1585         ixgbe_set_ivar(adapter, 0, 0, 0);
1586         ixgbe_set_ivar(adapter, 1, 0, 0);
1587
1588         map_vector_to_rxq(adapter, 0, 0);
1589         map_vector_to_txq(adapter, 0, 0);
1590
1591         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1592 }
1593
1594 /**
1595  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1596  * @adapter: board private structure
1597  *
1598  * Configure the Tx unit of the MAC after a reset.
1599  **/
1600 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1601 {
1602         u64 tdba;
1603         struct ixgbe_hw *hw = &adapter->hw;
1604         u32 i, j, tdlen, txctrl;
1605
1606         /* Setup the HW Tx Head and Tail descriptor pointers */
1607         for (i = 0; i < adapter->num_tx_queues; i++) {
1608                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1609                 j = ring->reg_idx;
1610                 tdba = ring->dma;
1611                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1612                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1613                                 (tdba & DMA_32BIT_MASK));
1614                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1615                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1616                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1617                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1618                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1619                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1620                 /* Disable Tx Head Writeback RO bit, since this hoses
1621                  * bookkeeping if things aren't delivered in order.
1622                  */
1623                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1624                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1625                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1626         }
1627         if (hw->mac.type == ixgbe_mac_82599EB) {
1628                 /* We enable 8 traffic classes, DCB only */
1629                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1630                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1631                                         IXGBE_MTQC_8TC_8TQ));
1632         }
1633 }
1634
1635 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1636
1637 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1638 {
1639         struct ixgbe_ring *rx_ring;
1640         u32 srrctl;
1641         int queue0 = 0;
1642         unsigned long mask;
1643
1644         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1645                 queue0 = index;
1646         } else {
1647                 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1648                 queue0 = index & mask;
1649                 index = index & mask;
1650         }
1651
1652         rx_ring = &adapter->rx_ring[queue0];
1653
1654         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1655
1656         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1657         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1658
1659         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1660                 u16 bufsz = IXGBE_RXBUFFER_2048;
1661                 /* grow the amount we can receive on large page machines */
1662                 if (bufsz < (PAGE_SIZE / 2))
1663                         bufsz = (PAGE_SIZE / 2);
1664                 /* cap the bufsz at our largest descriptor size */
1665                 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1666
1667                 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1668                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1669                 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1670                             IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1671                            IXGBE_SRRCTL_BSIZEHDR_MASK);
1672         } else {
1673                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1674
1675                 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1676                         srrctl |= IXGBE_RXBUFFER_2048 >>
1677                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1678                 else
1679                         srrctl |= rx_ring->rx_buf_len >>
1680                                   IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1681         }
1682         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1683                 srrctl |= IXGBE_SRRCTL_DROP_EN;
1684
1685         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1686 }
1687
1688 /**
1689  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1690  * @adapter: board private structure
1691  *
1692  * Configure the Rx unit of the MAC after a reset.
1693  **/
1694 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1695 {
1696         u64 rdba;
1697         struct ixgbe_hw *hw = &adapter->hw;
1698         struct net_device *netdev = adapter->netdev;
1699         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1700         int i, j;
1701         u32 rdlen, rxctrl, rxcsum;
1702         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1703                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1704                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1705         u32 fctrl, hlreg0;
1706         u32 reta = 0, mrqc;
1707         u32 rdrxctl;
1708         int rx_buf_len;
1709
1710         /* Decide whether to use packet split mode or not */
1711         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1712
1713         /* Set the RX buffer length according to the mode */
1714         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1715                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1716                 if (hw->mac.type == ixgbe_mac_82599EB) {
1717                         /* PSRTYPE must be initialized in 82599 */
1718                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1719                                       IXGBE_PSRTYPE_UDPHDR |
1720                                       IXGBE_PSRTYPE_IPV4HDR |
1721                                       IXGBE_PSRTYPE_IPV6HDR;
1722                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1723                 }
1724         } else {
1725                 if (netdev->mtu <= ETH_DATA_LEN)
1726                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1727                 else
1728                         rx_buf_len = ALIGN(max_frame, 1024);
1729         }
1730
1731         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1732         fctrl |= IXGBE_FCTRL_BAM;
1733         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1734         fctrl |= IXGBE_FCTRL_PMCF;
1735         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1736
1737         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1738         if (adapter->netdev->mtu <= ETH_DATA_LEN)
1739                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1740         else
1741                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1742         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1743
1744         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1745         /* disable receives while setting up the descriptors */
1746         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1747         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1748
1749         /* Setup the HW Rx Head and Tail Descriptor Pointers and
1750          * the Base and Length of the Rx Descriptor Ring */
1751         for (i = 0; i < adapter->num_rx_queues; i++) {
1752                 rdba = adapter->rx_ring[i].dma;
1753                 j = adapter->rx_ring[i].reg_idx;
1754                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1755                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1756                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1757                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1758                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1759                 adapter->rx_ring[i].head = IXGBE_RDH(j);
1760                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1761                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1762
1763                 ixgbe_configure_srrctl(adapter, j);
1764         }
1765
1766         if (hw->mac.type == ixgbe_mac_82598EB) {
1767                 /*
1768                  * For VMDq support of different descriptor types or
1769                  * buffer sizes through the use of multiple SRRCTL
1770                  * registers, RDRXCTL.MVMEN must be set to 1
1771                  *
1772                  * also, the manual doesn't mention it clearly but DCA hints
1773                  * will only use queue 0's tags unless this bit is set.  Side
1774                  * effects of setting this bit are only that SRRCTL must be
1775                  * fully programmed [0..15]
1776                  */
1777                 if (adapter->flags &
1778                     (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1779                         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1780                         rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1781                         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1782                 }
1783         }
1784
1785         /* Program MRQC for the distribution of queues */
1786         if (hw->mac.type == ixgbe_mac_82599EB) {
1787                 int mask = adapter->flags & (
1788                                 IXGBE_FLAG_RSS_ENABLED
1789                                 | IXGBE_FLAG_DCB_ENABLED
1790                                 );
1791
1792                 switch (mask) {
1793                 case (IXGBE_FLAG_RSS_ENABLED):
1794                         mrqc = IXGBE_MRQC_RSSEN;
1795                         break;
1796                 case (IXGBE_FLAG_DCB_ENABLED):
1797                         mrqc = IXGBE_MRQC_RT8TCEN;
1798                         break;
1799                 default:
1800                         break;
1801                 }
1802         }
1803         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1804                 /* Fill out redirection table */
1805                 for (i = 0, j = 0; i < 128; i++, j++) {
1806                         if (j == adapter->ring_feature[RING_F_RSS].indices)
1807                                 j = 0;
1808                         /* reta = 4-byte sliding window of
1809                          * 0x00..(indices-1)(indices-1)00..etc. */
1810                         reta = (reta << 8) | (j * 0x11);
1811                         if ((i & 3) == 3)
1812                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1813                 }
1814
1815                 /* Fill out hash function seeds */
1816                 for (i = 0; i < 10; i++)
1817                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1818
1819                 mrqc = IXGBE_MRQC_RSSEN
1820                     /* Perform hash on these packet types */
1821                        | IXGBE_MRQC_RSS_FIELD_IPV4
1822                        | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1823                        | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1824                        | IXGBE_MRQC_RSS_FIELD_IPV6
1825                        | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1826                        | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
1827                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1828         }
1829
1830         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1831
1832         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1833             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1834                 /* Disable indicating checksum in descriptor, enables
1835                  * RSS hash */
1836                 rxcsum |= IXGBE_RXCSUM_PCSD;
1837         }
1838         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1839                 /* Enable IPv4 payload checksum for UDP fragments
1840                  * if PCSD is not set */
1841                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1842         }
1843
1844         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1845
1846         if (hw->mac.type == ixgbe_mac_82599EB) {
1847                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1848                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
1849                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1850         }
1851 }
1852
1853 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1854 {
1855         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1856         struct ixgbe_hw *hw = &adapter->hw;
1857
1858         /* add VID to filter table */
1859         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1860 }
1861
1862 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1863 {
1864         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1865         struct ixgbe_hw *hw = &adapter->hw;
1866
1867         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1868                 ixgbe_irq_disable(adapter);
1869
1870         vlan_group_set_device(adapter->vlgrp, vid, NULL);
1871
1872         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1873                 ixgbe_irq_enable(adapter);
1874
1875         /* remove VID from filter table */
1876         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1877 }
1878
1879 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1880                                    struct vlan_group *grp)
1881 {
1882         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1883         u32 ctrl;
1884         int i, j;
1885
1886         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1887                 ixgbe_irq_disable(adapter);
1888         adapter->vlgrp = grp;
1889
1890         /*
1891          * For a DCB driver, always enable VLAN tag stripping so we can
1892          * still receive traffic from a DCB-enabled host even if we're
1893          * not in DCB mode.
1894          */
1895         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1896         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1897                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1898                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1899                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1900         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1901                 ctrl |= IXGBE_VLNCTRL_VFE;
1902                 /* enable VLAN tag insert/strip */
1903                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1904                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1905                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1906                 for (i = 0; i < adapter->num_rx_queues; i++) {
1907                         j = adapter->rx_ring[i].reg_idx;
1908                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
1909                         ctrl |= IXGBE_RXDCTL_VME;
1910                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
1911                 }
1912         }
1913         ixgbe_vlan_rx_add_vid(netdev, 0);
1914
1915         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1916                 ixgbe_irq_enable(adapter);
1917 }
1918
1919 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1920 {
1921         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1922
1923         if (adapter->vlgrp) {
1924                 u16 vid;
1925                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1926                         if (!vlan_group_get_device(adapter->vlgrp, vid))
1927                                 continue;
1928                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1929                 }
1930         }
1931 }
1932
1933 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1934 {
1935         struct dev_mc_list *mc_ptr;
1936         u8 *addr = *mc_addr_ptr;
1937         *vmdq = 0;
1938
1939         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1940         if (mc_ptr->next)
1941                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1942         else
1943                 *mc_addr_ptr = NULL;
1944
1945         return addr;
1946 }
1947
1948 /**
1949  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1950  * @netdev: network interface device structure
1951  *
1952  * The set_rx_method entry point is called whenever the unicast/multicast
1953  * address list or the network interface flags are updated.  This routine is
1954  * responsible for configuring the hardware for proper unicast, multicast and
1955  * promiscuous mode.
1956  **/
1957 static void ixgbe_set_rx_mode(struct net_device *netdev)
1958 {
1959         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1960         struct ixgbe_hw *hw = &adapter->hw;
1961         u32 fctrl, vlnctrl;
1962         u8 *addr_list = NULL;
1963         int addr_count = 0;
1964
1965         /* Check for Promiscuous and All Multicast modes */
1966
1967         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1968         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1969
1970         if (netdev->flags & IFF_PROMISC) {
1971                 hw->addr_ctrl.user_set_promisc = 1;
1972                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1973                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1974         } else {
1975                 if (netdev->flags & IFF_ALLMULTI) {
1976                         fctrl |= IXGBE_FCTRL_MPE;
1977                         fctrl &= ~IXGBE_FCTRL_UPE;
1978                 } else {
1979                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1980                 }
1981                 vlnctrl |= IXGBE_VLNCTRL_VFE;
1982                 hw->addr_ctrl.user_set_promisc = 0;
1983         }
1984
1985         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1986         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1987
1988         /* reprogram secondary unicast list */
1989         addr_count = netdev->uc_count;
1990         if (addr_count)
1991                 addr_list = netdev->uc_list->dmi_addr;
1992         hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1993                                           ixgbe_addr_list_itr);
1994
1995         /* reprogram multicast list */
1996         addr_count = netdev->mc_count;
1997         if (addr_count)
1998                 addr_list = netdev->mc_list->dmi_addr;
1999         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2000                                         ixgbe_addr_list_itr);
2001 }
2002
2003 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2004 {
2005         int q_idx;
2006         struct ixgbe_q_vector *q_vector;
2007         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2008
2009         /* legacy and MSI only use one vector */
2010         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2011                 q_vectors = 1;
2012
2013         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2014                 struct napi_struct *napi;
2015                 q_vector = &adapter->q_vector[q_idx];
2016                 if (!q_vector->rxr_count)
2017                         continue;
2018                 napi = &q_vector->napi;
2019                 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2020                     (q_vector->rxr_count > 1))
2021                         napi->poll = &ixgbe_clean_rxonly_many;
2022
2023                 napi_enable(napi);
2024         }
2025 }
2026
2027 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2028 {
2029         int q_idx;
2030         struct ixgbe_q_vector *q_vector;
2031         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2032
2033         /* legacy and MSI only use one vector */
2034         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2035                 q_vectors = 1;
2036
2037         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2038                 q_vector = &adapter->q_vector[q_idx];
2039                 if (!q_vector->rxr_count)
2040                         continue;
2041                 napi_disable(&q_vector->napi);
2042         }
2043 }
2044
2045 #ifdef CONFIG_IXGBE_DCB
2046 /*
2047  * ixgbe_configure_dcb - Configure DCB hardware
2048  * @adapter: ixgbe adapter struct
2049  *
2050  * This is called by the driver on open to configure the DCB hardware.
2051  * This is also called by the gennetlink interface when reconfiguring
2052  * the DCB state.
2053  */
2054 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2055 {
2056         struct ixgbe_hw *hw = &adapter->hw;
2057         u32 txdctl, vlnctrl;
2058         int i, j;
2059
2060         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2061         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2062         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2063
2064         /* reconfigure the hardware */
2065         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2066
2067         for (i = 0; i < adapter->num_tx_queues; i++) {
2068                 j = adapter->tx_ring[i].reg_idx;
2069                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2070                 /* PThresh workaround for Tx hang with DFP enabled. */
2071                 txdctl |= 32;
2072                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2073         }
2074         /* Enable VLAN tag insert/strip */
2075         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2076         if (hw->mac.type == ixgbe_mac_82598EB) {
2077                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2078                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2079                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2080         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2081                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2082                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2083                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2084                 for (i = 0; i < adapter->num_rx_queues; i++) {
2085                         j = adapter->rx_ring[i].reg_idx;
2086                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2087                         vlnctrl |= IXGBE_RXDCTL_VME;
2088                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2089                 }
2090         }
2091         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2092 }
2093
2094 #endif
2095 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2096 {
2097         struct net_device *netdev = adapter->netdev;
2098         int i;
2099
2100         ixgbe_set_rx_mode(netdev);
2101
2102         ixgbe_restore_vlan(adapter);
2103 #ifdef CONFIG_IXGBE_DCB
2104         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2105                 netif_set_gso_max_size(netdev, 32768);
2106                 ixgbe_configure_dcb(adapter);
2107         } else {
2108                 netif_set_gso_max_size(netdev, 65536);
2109         }
2110 #else
2111         netif_set_gso_max_size(netdev, 65536);
2112 #endif
2113
2114         ixgbe_configure_tx(adapter);
2115         ixgbe_configure_rx(adapter);
2116         for (i = 0; i < adapter->num_rx_queues; i++)
2117                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2118                                        (adapter->rx_ring[i].count - 1));
2119 }
2120
2121 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2122 {
2123         switch (hw->phy.type) {
2124         case ixgbe_phy_sfp_avago:
2125         case ixgbe_phy_sfp_ftl:
2126         case ixgbe_phy_sfp_intel:
2127         case ixgbe_phy_sfp_unknown:
2128         case ixgbe_phy_tw_tyco:
2129         case ixgbe_phy_tw_unknown:
2130                 return true;
2131         default:
2132                 return false;
2133         }
2134 }
2135
2136 /**
2137  * ixgbe_sfp_link_config - set up SFP+ link
2138  * @adapter: pointer to private adapter struct
2139  **/
2140 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2141 {
2142         struct ixgbe_hw *hw = &adapter->hw;
2143
2144                 if (hw->phy.multispeed_fiber) {
2145                         /*
2146                          * In multispeed fiber setups, the device may not have
2147                          * had a physical connection when the driver loaded.
2148                          * If that's the case, the initial link configuration
2149                          * couldn't get the MAC into 10G or 1G mode, so we'll
2150                          * never have a link status change interrupt fire.
2151                          * We need to try and force an autonegotiation
2152                          * session, then bring up link.
2153                          */
2154                         hw->mac.ops.setup_sfp(hw);
2155                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2156                                 schedule_work(&adapter->multispeed_fiber_task);
2157                 } else {
2158                         /*
2159                          * Direct Attach Cu and non-multispeed fiber modules
2160                          * still need to be configured properly prior to
2161                          * attempting link.
2162                          */
2163                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2164                                 schedule_work(&adapter->sfp_config_module_task);
2165                 }
2166 }
2167
2168 /**
2169  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2170  * @hw: pointer to private hardware struct
2171  *
2172  * Returns 0 on success, negative on failure
2173  **/
2174 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2175 {
2176         u32 autoneg;
2177         bool link_up = false;
2178         u32 ret = IXGBE_ERR_LINK_SETUP;
2179
2180         if (hw->mac.ops.check_link)
2181                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2182
2183         if (ret)
2184                 goto link_cfg_out;
2185
2186         if (hw->mac.ops.get_link_capabilities)
2187                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2188                                                         &hw->mac.autoneg);
2189         if (ret)
2190                 goto link_cfg_out;
2191
2192         if (hw->mac.ops.setup_link_speed)
2193                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2194 link_cfg_out:
2195         return ret;
2196 }
2197
2198 #define IXGBE_MAX_RX_DESC_POLL 10
2199 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2200                                               int rxr)
2201 {
2202         int j = adapter->rx_ring[rxr].reg_idx;
2203         int k;
2204
2205         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2206                 if (IXGBE_READ_REG(&adapter->hw,
2207                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2208                         break;
2209                 else
2210                         msleep(1);
2211         }
2212         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2213                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2214                         "not set within the polling period\n", rxr);
2215         }
2216         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2217                               (adapter->rx_ring[rxr].count - 1));
2218 }
2219
2220 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2221 {
2222         struct net_device *netdev = adapter->netdev;
2223         struct ixgbe_hw *hw = &adapter->hw;
2224         int i, j = 0;
2225         int num_rx_rings = adapter->num_rx_queues;
2226         int err;
2227         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2228         u32 txdctl, rxdctl, mhadd;
2229         u32 dmatxctl;
2230         u32 gpie;
2231
2232         ixgbe_get_hw_control(adapter);
2233
2234         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2235             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2236                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2237                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2238                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2239                 } else {
2240                         /* MSI only */
2241                         gpie = 0;
2242                 }
2243                 /* XXX: to interrupt immediately for EICS writes, enable this */
2244                 /* gpie |= IXGBE_GPIE_EIMEN; */
2245                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2246         }
2247
2248         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2249                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2250                  * specifically only auto mask tx and rx interrupts */
2251                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2252         }
2253
2254         /* Enable fan failure interrupt if media type is copper */
2255         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2256                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2257                 gpie |= IXGBE_SDP1_GPIEN;
2258                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2259         }
2260
2261         if (hw->mac.type == ixgbe_mac_82599EB) {
2262                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2263                 gpie |= IXGBE_SDP1_GPIEN;
2264                 gpie |= IXGBE_SDP2_GPIEN;
2265                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2266         }
2267
2268         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2269         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2270                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2271                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2272
2273                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2274         }
2275
2276         for (i = 0; i < adapter->num_tx_queues; i++) {
2277                 j = adapter->tx_ring[i].reg_idx;
2278                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2279                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2280                 txdctl |= (8 << 16);
2281                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2282         }
2283
2284         if (hw->mac.type == ixgbe_mac_82599EB) {
2285                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2286                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2287                 dmatxctl |= IXGBE_DMATXCTL_TE;
2288                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2289         }
2290         for (i = 0; i < adapter->num_tx_queues; i++) {
2291                 j = adapter->tx_ring[i].reg_idx;
2292                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2293                 txdctl |= IXGBE_TXDCTL_ENABLE;
2294                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2295         }
2296
2297         for (i = 0; i < num_rx_rings; i++) {
2298                 j = adapter->rx_ring[i].reg_idx;
2299                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2300                 /* enable PTHRESH=32 descriptors (half the internal cache)
2301                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2302                  * this also removes a pesky rx_no_buffer_count increment */
2303                 rxdctl |= 0x0020;
2304                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2305                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2306                 if (hw->mac.type == ixgbe_mac_82599EB)
2307                         ixgbe_rx_desc_queue_enable(adapter, i);
2308         }
2309         /* enable all receives */
2310         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2311         if (hw->mac.type == ixgbe_mac_82598EB)
2312                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2313         else
2314                 rxdctl |= IXGBE_RXCTRL_RXEN;
2315         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2316
2317         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2318                 ixgbe_configure_msix(adapter);
2319         else
2320                 ixgbe_configure_msi_and_legacy(adapter);
2321
2322         ixgbe_napi_add_all(adapter);
2323
2324         clear_bit(__IXGBE_DOWN, &adapter->state);
2325         ixgbe_napi_enable_all(adapter);
2326
2327         /* clear any pending interrupts, may auto mask */
2328         IXGBE_READ_REG(hw, IXGBE_EICR);
2329
2330         ixgbe_irq_enable(adapter);
2331
2332         /*
2333          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2334          * arrived before interrupts were enabled.  We need to kick off
2335          * the SFP+ module setup first, then try to bring up link.
2336          * If we're not hot-pluggable SFP+, we just need to configure link
2337          * and bring it up.
2338          */
2339         err = hw->phy.ops.identify(hw);
2340         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2341                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2342                 ixgbe_down(adapter);
2343                 return err;
2344         }
2345
2346         if (ixgbe_is_sfp(hw)) {
2347                 ixgbe_sfp_link_config(adapter);
2348         } else {
2349                 err = ixgbe_non_sfp_link_config(hw);
2350                 if (err)
2351                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2352         }
2353
2354         /* enable transmits */
2355         netif_tx_start_all_queues(netdev);
2356
2357         /* bring the link up in the watchdog, this could race with our first
2358          * link up interrupt but shouldn't be a problem */
2359         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2360         adapter->link_check_timeout = jiffies;
2361         mod_timer(&adapter->watchdog_timer, jiffies);
2362         return 0;
2363 }
2364
2365 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2366 {
2367         WARN_ON(in_interrupt());
2368         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2369                 msleep(1);
2370         ixgbe_down(adapter);
2371         ixgbe_up(adapter);
2372         clear_bit(__IXGBE_RESETTING, &adapter->state);
2373 }
2374
2375 int ixgbe_up(struct ixgbe_adapter *adapter)
2376 {
2377         /* hardware has been reset, we need to reload some things */
2378         ixgbe_configure(adapter);
2379
2380         return ixgbe_up_complete(adapter);
2381 }
2382
2383 void ixgbe_reset(struct ixgbe_adapter *adapter)
2384 {
2385         struct ixgbe_hw *hw = &adapter->hw;
2386         if (hw->mac.ops.init_hw(hw))
2387                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2388
2389         /* reprogram the RAR[0] in case user changed it. */
2390         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2391
2392 }
2393
2394 /**
2395  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2396  * @adapter: board private structure
2397  * @rx_ring: ring to free buffers from
2398  **/
2399 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2400                                 struct ixgbe_ring *rx_ring)
2401 {
2402         struct pci_dev *pdev = adapter->pdev;
2403         unsigned long size;
2404         unsigned int i;
2405
2406         /* Free all the Rx ring sk_buffs */
2407
2408         for (i = 0; i < rx_ring->count; i++) {
2409                 struct ixgbe_rx_buffer *rx_buffer_info;
2410
2411                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2412                 if (rx_buffer_info->dma) {
2413                         pci_unmap_single(pdev, rx_buffer_info->dma,
2414                                          rx_ring->rx_buf_len,
2415                                          PCI_DMA_FROMDEVICE);
2416                         rx_buffer_info->dma = 0;
2417                 }
2418                 if (rx_buffer_info->skb) {
2419                         dev_kfree_skb(rx_buffer_info->skb);
2420                         rx_buffer_info->skb = NULL;
2421                 }
2422                 if (!rx_buffer_info->page)
2423                         continue;
2424                 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2425                                PCI_DMA_FROMDEVICE);
2426                 rx_buffer_info->page_dma = 0;
2427                 put_page(rx_buffer_info->page);
2428                 rx_buffer_info->page = NULL;
2429                 rx_buffer_info->page_offset = 0;
2430         }
2431
2432         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2433         memset(rx_ring->rx_buffer_info, 0, size);
2434
2435         /* Zero out the descriptor ring */
2436         memset(rx_ring->desc, 0, rx_ring->size);
2437
2438         rx_ring->next_to_clean = 0;
2439         rx_ring->next_to_use = 0;
2440
2441         writel(0, adapter->hw.hw_addr + rx_ring->head);
2442         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2443 }
2444
2445 /**
2446  * ixgbe_clean_tx_ring - Free Tx Buffers
2447  * @adapter: board private structure
2448  * @tx_ring: ring to be cleaned
2449  **/
2450 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2451                                 struct ixgbe_ring *tx_ring)
2452 {
2453         struct ixgbe_tx_buffer *tx_buffer_info;
2454         unsigned long size;
2455         unsigned int i;
2456
2457         /* Free all the Tx ring sk_buffs */
2458
2459         for (i = 0; i < tx_ring->count; i++) {
2460                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2461                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2462         }
2463
2464         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2465         memset(tx_ring->tx_buffer_info, 0, size);
2466
2467         /* Zero out the descriptor ring */
2468         memset(tx_ring->desc, 0, tx_ring->size);
2469
2470         tx_ring->next_to_use = 0;
2471         tx_ring->next_to_clean = 0;
2472
2473         writel(0, adapter->hw.hw_addr + tx_ring->head);
2474         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2475 }
2476
2477 /**
2478  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2479  * @adapter: board private structure
2480  **/
2481 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2482 {
2483         int i;
2484
2485         for (i = 0; i < adapter->num_rx_queues; i++)
2486                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2487 }
2488
2489 /**
2490  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2491  * @adapter: board private structure
2492  **/
2493 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2494 {
2495         int i;
2496
2497         for (i = 0; i < adapter->num_tx_queues; i++)
2498                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2499 }
2500
2501 void ixgbe_down(struct ixgbe_adapter *adapter)
2502 {
2503         struct net_device *netdev = adapter->netdev;
2504         struct ixgbe_hw *hw = &adapter->hw;
2505         u32 rxctrl;
2506         u32 txdctl;
2507         int i, j;
2508
2509         /* signal that we are down to the interrupt handler */
2510         set_bit(__IXGBE_DOWN, &adapter->state);
2511
2512         /* disable receives */
2513         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2514         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2515
2516         netif_tx_disable(netdev);
2517
2518         IXGBE_WRITE_FLUSH(hw);
2519         msleep(10);
2520
2521         netif_tx_stop_all_queues(netdev);
2522
2523         ixgbe_irq_disable(adapter);
2524
2525         ixgbe_napi_disable_all(adapter);
2526
2527         del_timer_sync(&adapter->watchdog_timer);
2528         cancel_work_sync(&adapter->watchdog_task);
2529
2530         /* disable transmits in the hardware now that interrupts are off */
2531         for (i = 0; i < adapter->num_tx_queues; i++) {
2532                 j = adapter->tx_ring[i].reg_idx;
2533                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2534                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2535                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2536         }
2537
2538         netif_carrier_off(netdev);
2539
2540 #ifdef CONFIG_IXGBE_DCA
2541         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2542                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2543                 dca_remove_requester(&adapter->pdev->dev);
2544         }
2545
2546 #endif
2547         if (!pci_channel_offline(adapter->pdev))
2548                 ixgbe_reset(adapter);
2549         ixgbe_clean_all_tx_rings(adapter);
2550         ixgbe_clean_all_rx_rings(adapter);
2551
2552 #ifdef CONFIG_IXGBE_DCA
2553         /* since we reset the hardware DCA settings were cleared */
2554         if (dca_add_requester(&adapter->pdev->dev) == 0) {
2555                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2556                 /* always use CB2 mode, difference is masked
2557                  * in the CB driver */
2558                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2559                 ixgbe_setup_dca(adapter);
2560         }
2561 #endif
2562 }
2563
2564 /**
2565  * ixgbe_poll - NAPI Rx polling callback
2566  * @napi: structure for representing this polling device
2567  * @budget: how many packets driver is allowed to clean
2568  *
2569  * This function is used for legacy and MSI, NAPI mode
2570  **/
2571 static int ixgbe_poll(struct napi_struct *napi, int budget)
2572 {
2573         struct ixgbe_q_vector *q_vector = container_of(napi,
2574                                                   struct ixgbe_q_vector, napi);
2575         struct ixgbe_adapter *adapter = q_vector->adapter;
2576         int tx_cleaned, work_done = 0;
2577
2578 #ifdef CONFIG_IXGBE_DCA
2579         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2580                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2581                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2582         }
2583 #endif
2584
2585         tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2586         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2587
2588         if (tx_cleaned)
2589                 work_done = budget;
2590
2591         /* If budget not fully consumed, exit the polling mode */
2592         if (work_done < budget) {
2593                 napi_complete(napi);
2594                 if (adapter->itr_setting & 3)
2595                         ixgbe_set_itr(adapter);
2596                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2597                         ixgbe_irq_enable(adapter);
2598         }
2599         return work_done;
2600 }
2601
2602 /**
2603  * ixgbe_tx_timeout - Respond to a Tx Hang
2604  * @netdev: network interface device structure
2605  **/
2606 static void ixgbe_tx_timeout(struct net_device *netdev)
2607 {
2608         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2609
2610         /* Do the reset outside of interrupt context */
2611         schedule_work(&adapter->reset_task);
2612 }
2613
2614 static void ixgbe_reset_task(struct work_struct *work)
2615 {
2616         struct ixgbe_adapter *adapter;
2617         adapter = container_of(work, struct ixgbe_adapter, reset_task);
2618
2619         /* If we're already down or resetting, just bail */
2620         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2621             test_bit(__IXGBE_RESETTING, &adapter->state))
2622                 return;
2623
2624         adapter->tx_timeout_count++;
2625
2626         ixgbe_reinit_locked(adapter);
2627 }
2628
2629 #ifdef CONFIG_IXGBE_DCB
2630 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
2631 {
2632         bool ret = false;
2633
2634         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2635                 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2636                 adapter->num_rx_queues =
2637                                       adapter->ring_feature[RING_F_DCB].indices;
2638                 adapter->num_tx_queues =
2639                                       adapter->ring_feature[RING_F_DCB].indices;
2640                 ret = true;
2641         } else {
2642                 ret = false;
2643         }
2644
2645         return ret;
2646 }
2647 #endif
2648
2649 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2650 {
2651         bool ret = false;
2652
2653         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2654                 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2655                 adapter->num_rx_queues =
2656                                       adapter->ring_feature[RING_F_RSS].indices;
2657                 adapter->num_tx_queues =
2658                                       adapter->ring_feature[RING_F_RSS].indices;
2659                 ret = true;
2660         } else {
2661                 ret = false;
2662         }
2663
2664         return ret;
2665 }
2666
2667 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2668 {
2669         /* Start with base case */
2670         adapter->num_rx_queues = 1;
2671         adapter->num_tx_queues = 1;
2672
2673 #ifdef CONFIG_IXGBE_DCB
2674         if (ixgbe_set_dcb_queues(adapter))
2675                 return;
2676
2677 #endif
2678         if (ixgbe_set_rss_queues(adapter))
2679                 return;
2680 }
2681
2682 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2683                                        int vectors)
2684 {
2685         int err, vector_threshold;
2686
2687         /* We'll want at least 3 (vector_threshold):
2688          * 1) TxQ[0] Cleanup
2689          * 2) RxQ[0] Cleanup
2690          * 3) Other (Link Status Change, etc.)
2691          * 4) TCP Timer (optional)
2692          */
2693         vector_threshold = MIN_MSIX_COUNT;
2694
2695         /* The more we get, the more we will assign to Tx/Rx Cleanup
2696          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2697          * Right now, we simply care about how many we'll get; we'll
2698          * set them up later while requesting irq's.
2699          */
2700         while (vectors >= vector_threshold) {
2701                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2702                                       vectors);
2703                 if (!err) /* Success in acquiring all requested vectors. */
2704                         break;
2705                 else if (err < 0)
2706                         vectors = 0; /* Nasty failure, quit now */
2707                 else /* err == number of vectors we should try again with */
2708                         vectors = err;
2709         }
2710
2711         if (vectors < vector_threshold) {
2712                 /* Can't allocate enough MSI-X interrupts?  Oh well.
2713                  * This just means we'll go with either a single MSI
2714                  * vector or fall back to legacy interrupts.
2715                  */
2716                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2717                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2718                 kfree(adapter->msix_entries);
2719                 adapter->msix_entries = NULL;
2720                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2721                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2722                 ixgbe_set_num_queues(adapter);
2723         } else {
2724                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2725                 /*
2726                  * Adjust for only the vectors we'll use, which is minimum
2727                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2728                  * vectors we were allocated.
2729                  */
2730                 adapter->num_msix_vectors = min(vectors,
2731                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
2732         }
2733 }
2734
2735 /**
2736  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
2737  * @adapter: board private structure to initialize
2738  *
2739  * Cache the descriptor ring offsets for RSS to the assigned rings.
2740  *
2741  **/
2742 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
2743 {
2744         int i;
2745         bool ret = false;
2746
2747         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2748                 for (i = 0; i < adapter->num_rx_queues; i++)
2749                         adapter->rx_ring[i].reg_idx = i;
2750                 for (i = 0; i < adapter->num_tx_queues; i++)
2751                         adapter->tx_ring[i].reg_idx = i;
2752                 ret = true;
2753         } else {
2754                 ret = false;
2755         }
2756
2757         return ret;
2758 }
2759
2760 #ifdef CONFIG_IXGBE_DCB
2761 /**
2762  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2763  * @adapter: board private structure to initialize
2764  *
2765  * Cache the descriptor ring offsets for DCB to the assigned rings.
2766  *
2767  **/
2768 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2769 {
2770         int i;
2771         bool ret = false;
2772         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2773
2774         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2775                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2776                         /* the number of queues is assumed to be symmetric */
2777                         for (i = 0; i < dcb_i; i++) {
2778                                 adapter->rx_ring[i].reg_idx = i << 3;
2779                                 adapter->tx_ring[i].reg_idx = i << 2;
2780                         }
2781                         ret = true;
2782                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2783                         for (i = 0; i < dcb_i; i++) {
2784                                 adapter->rx_ring[i].reg_idx = i << 4;
2785                                 adapter->tx_ring[i].reg_idx = i << 4;
2786                         }
2787                         ret = true;
2788                 } else {
2789                         ret = false;
2790                 }
2791         } else {
2792                 ret = false;
2793         }
2794
2795         return ret;
2796 }
2797 #endif
2798
2799 /**
2800  * ixgbe_cache_ring_register - Descriptor ring to register mapping
2801  * @adapter: board private structure to initialize
2802  *
2803  * Once we know the feature-set enabled for the device, we'll cache
2804  * the register offset the descriptor ring is assigned to.
2805  *
2806  * Note, the order the various feature calls is important.  It must start with
2807  * the "most" features enabled at the same time, then trickle down to the
2808  * least amount of features turned on at once.
2809  **/
2810 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2811 {
2812         /* start with default case */
2813         adapter->rx_ring[0].reg_idx = 0;
2814         adapter->tx_ring[0].reg_idx = 0;
2815
2816 #ifdef CONFIG_IXGBE_DCB
2817         if (ixgbe_cache_ring_dcb(adapter))
2818                 return;
2819
2820 #endif
2821         if (ixgbe_cache_ring_rss(adapter))
2822                 return;
2823 }
2824
2825 /**
2826  * ixgbe_alloc_queues - Allocate memory for all rings
2827  * @adapter: board private structure to initialize
2828  *
2829  * We allocate one ring per queue at run-time since we don't know the
2830  * number of queues at compile-time.
2831  **/
2832 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2833 {
2834         int i;
2835
2836         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2837                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2838         if (!adapter->tx_ring)
2839                 goto err_tx_ring_allocation;
2840
2841         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2842                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
2843         if (!adapter->rx_ring)
2844                 goto err_rx_ring_allocation;
2845
2846         for (i = 0; i < adapter->num_tx_queues; i++) {
2847                 adapter->tx_ring[i].count = adapter->tx_ring_count;
2848                 adapter->tx_ring[i].queue_index = i;
2849         }
2850
2851         for (i = 0; i < adapter->num_rx_queues; i++) {
2852                 adapter->rx_ring[i].count = adapter->rx_ring_count;
2853                 adapter->rx_ring[i].queue_index = i;
2854         }
2855
2856         ixgbe_cache_ring_register(adapter);
2857
2858         return 0;
2859
2860 err_rx_ring_allocation:
2861         kfree(adapter->tx_ring);
2862 err_tx_ring_allocation:
2863         return -ENOMEM;
2864 }
2865
2866 /**
2867  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2868  * @adapter: board private structure to initialize
2869  *
2870  * Attempt to configure the interrupts using the best available
2871  * capabilities of the hardware and the kernel.
2872  **/
2873 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
2874 {
2875         int err = 0;
2876         int vector, v_budget;
2877
2878         /*
2879          * It's easy to be greedy for MSI-X vectors, but it really
2880          * doesn't do us much good if we have a lot more vectors
2881          * than CPU's.  So let's be conservative and only ask for
2882          * (roughly) twice the number of vectors as there are CPU's.
2883          */
2884         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2885                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2886
2887         /*
2888          * At the same time, hardware can only support a maximum of
2889          * MAX_MSIX_COUNT vectors.  With features such as RSS and VMDq,
2890          * we can easily reach upwards of 64 Rx descriptor queues and
2891          * 32 Tx queues.  Thus, we cap it off in those rare cases where
2892          * the cpu count also exceeds our vector limit.
2893          */
2894         v_budget = min(v_budget, MAX_MSIX_COUNT);
2895
2896         /* A failure in MSI-X entry allocation isn't fatal, but it does
2897          * mean we disable MSI-X capabilities of the adapter. */
2898         adapter->msix_entries = kcalloc(v_budget,
2899                                         sizeof(struct msix_entry), GFP_KERNEL);
2900         if (!adapter->msix_entries) {
2901                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
2902                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2903                 ixgbe_set_num_queues(adapter);
2904                 kfree(adapter->tx_ring);
2905                 kfree(adapter->rx_ring);
2906                 err = ixgbe_alloc_queues(adapter);
2907                 if (err) {
2908                         DPRINTK(PROBE, ERR, "Unable to allocate memory "
2909                                 "for queues\n");
2910                         goto out;
2911                 }
2912
2913                 goto try_msi;
2914         }
2915
2916         for (vector = 0; vector < v_budget; vector++)
2917                 adapter->msix_entries[vector].entry = vector;
2918
2919         ixgbe_acquire_msix_vectors(adapter, v_budget);
2920
2921         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2922                 goto out;
2923
2924 try_msi:
2925         err = pci_enable_msi(adapter->pdev);
2926         if (!err) {
2927                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2928         } else {
2929                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2930                         "falling back to legacy.  Error: %d\n", err);
2931                 /* reset err */
2932                 err = 0;
2933         }
2934
2935 out:
2936         /* Notify the stack of the (possibly) reduced Tx Queue count. */
2937         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2938
2939         return err;
2940 }
2941
2942 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2943 {
2944         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2945                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2946                 pci_disable_msix(adapter->pdev);
2947                 kfree(adapter->msix_entries);
2948                 adapter->msix_entries = NULL;
2949         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2950                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2951                 pci_disable_msi(adapter->pdev);
2952         }
2953         return;
2954 }
2955
2956 /**
2957  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2958  * @adapter: board private structure to initialize
2959  *
2960  * We determine which interrupt scheme to use based on...
2961  * - Kernel support (MSI, MSI-X)
2962  *   - which can be user-defined (via MODULE_PARAM)
2963  * - Hardware queue count (num_*_queues)
2964  *   - defined by miscellaneous hardware support/features (RSS, etc.)
2965  **/
2966 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2967 {
2968         int err;
2969
2970         /* Number of supported queues */
2971         ixgbe_set_num_queues(adapter);
2972
2973         err = ixgbe_alloc_queues(adapter);
2974         if (err) {
2975                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2976                 goto err_alloc_queues;
2977         }
2978
2979         err = ixgbe_set_interrupt_capability(adapter);
2980         if (err) {
2981                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2982                 goto err_set_interrupt;
2983         }
2984
2985         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2986                 "Tx Queue count = %u\n",
2987                 (adapter->num_rx_queues > 1) ? "Enabled" :
2988                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2989
2990         set_bit(__IXGBE_DOWN, &adapter->state);
2991
2992         return 0;
2993
2994 err_set_interrupt:
2995         kfree(adapter->tx_ring);
2996         kfree(adapter->rx_ring);
2997 err_alloc_queues:
2998         return err;
2999 }
3000
3001 /**
3002  * ixgbe_sfp_timer - worker thread to find a missing module
3003  * @data: pointer to our adapter struct
3004  **/
3005 static void ixgbe_sfp_timer(unsigned long data)
3006 {
3007         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3008
3009         /* Do the sfp_timer outside of interrupt context due to the
3010          * delays that sfp+ detection requires
3011          */
3012         schedule_work(&adapter->sfp_task);
3013 }
3014
3015 /**
3016  * ixgbe_sfp_task - worker thread to find a missing module
3017  * @work: pointer to work_struct containing our data
3018  **/
3019 static void ixgbe_sfp_task(struct work_struct *work)
3020 {
3021         struct ixgbe_adapter *adapter = container_of(work,
3022                                                      struct ixgbe_adapter,
3023                                                      sfp_task);
3024         struct ixgbe_hw *hw = &adapter->hw;
3025
3026         if ((hw->phy.type == ixgbe_phy_nl) &&
3027             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3028                 s32 ret = hw->phy.ops.identify_sfp(hw);
3029                 if (ret)
3030                         goto reschedule;
3031                 ret = hw->phy.ops.reset(hw);
3032                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3033                         DPRINTK(PROBE, ERR, "failed to initialize because an "
3034                                 "unsupported SFP+ module type was detected.\n"
3035                                 "Reload the driver after installing a "
3036                                 "supported module.\n");
3037                         unregister_netdev(adapter->netdev);
3038                 } else {
3039                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3040                                 hw->phy.sfp_type);
3041                 }
3042                 /* don't need this routine any more */
3043                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3044         }
3045         return;
3046 reschedule:
3047         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3048                 mod_timer(&adapter->sfp_timer,
3049                           round_jiffies(jiffies + (2 * HZ)));
3050 }
3051
3052 /**
3053  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3054  * @adapter: board private structure to initialize
3055  *
3056  * ixgbe_sw_init initializes the Adapter private data structure.
3057  * Fields are initialized based on PCI device information and
3058  * OS network device settings (MTU size).
3059  **/
3060 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3061 {
3062         struct ixgbe_hw *hw = &adapter->hw;
3063         struct pci_dev *pdev = adapter->pdev;
3064         unsigned int rss;
3065 #ifdef CONFIG_IXGBE_DCB
3066         int j;
3067         struct tc_configuration *tc;
3068 #endif
3069
3070         /* PCI config space info */
3071
3072         hw->vendor_id = pdev->vendor;
3073         hw->device_id = pdev->device;
3074         hw->revision_id = pdev->revision;
3075         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3076         hw->subsystem_device_id = pdev->subsystem_device;
3077
3078         /* Set capability flags */
3079         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3080         adapter->ring_feature[RING_F_RSS].indices = rss;
3081         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3082         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3083         if (hw->mac.type == ixgbe_mac_82598EB)
3084                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3085         else if (hw->mac.type == ixgbe_mac_82599EB)
3086                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3087
3088 #ifdef CONFIG_IXGBE_DCB
3089         /* Configure DCB traffic classes */
3090         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3091                 tc = &adapter->dcb_cfg.tc_config[j];
3092                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3093                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3094                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3095                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3096                 tc->dcb_pfc = pfc_disabled;
3097         }
3098         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3099         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3100         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3101         adapter->dcb_cfg.round_robin_enable = false;
3102         adapter->dcb_set_bitmap = 0x00;
3103         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3104                            adapter->ring_feature[RING_F_DCB].indices);
3105
3106 #endif
3107
3108         /* default flow control settings */
3109         hw->fc.requested_mode = ixgbe_fc_none;
3110         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3111         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3112         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3113         hw->fc.send_xon = true;
3114
3115         /* enable itr by default in dynamic mode */
3116         adapter->itr_setting = 1;
3117         adapter->eitr_param = 20000;
3118
3119         /* set defaults for eitr in MegaBytes */
3120         adapter->eitr_low = 10;
3121         adapter->eitr_high = 20;
3122
3123         /* set default ring sizes */
3124         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3125         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3126
3127         /* initialize eeprom parameters */
3128         if (ixgbe_init_eeprom_params_generic(hw)) {
3129                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3130                 return -EIO;
3131         }
3132
3133         /* enable rx csum by default */
3134         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3135
3136         set_bit(__IXGBE_DOWN, &adapter->state);
3137
3138         return 0;
3139 }
3140
3141 /**
3142  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3143  * @adapter: board private structure
3144  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3145  *
3146  * Return 0 on success, negative on failure
3147  **/
3148 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3149                              struct ixgbe_ring *tx_ring)
3150 {
3151         struct pci_dev *pdev = adapter->pdev;
3152         int size;
3153
3154         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3155         tx_ring->tx_buffer_info = vmalloc(size);
3156         if (!tx_ring->tx_buffer_info)
3157                 goto err;
3158         memset(tx_ring->tx_buffer_info, 0, size);
3159
3160         /* round up to nearest 4K */
3161         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3162         tx_ring->size = ALIGN(tx_ring->size, 4096);
3163
3164         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3165                                              &tx_ring->dma);
3166         if (!tx_ring->desc)
3167                 goto err;
3168
3169         tx_ring->next_to_use = 0;
3170         tx_ring->next_to_clean = 0;
3171         tx_ring->work_limit = tx_ring->count;
3172         return 0;
3173
3174 err:
3175         vfree(tx_ring->tx_buffer_info);
3176         tx_ring->tx_buffer_info = NULL;
3177         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3178                             "descriptor ring\n");
3179         return -ENOMEM;
3180 }
3181
3182 /**
3183  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3184  * @adapter: board private structure
3185  *
3186  * If this function returns with an error, then it's possible one or
3187  * more of the rings is populated (while the rest are not).  It is the
3188  * callers duty to clean those orphaned rings.
3189  *
3190  * Return 0 on success, negative on failure
3191  **/
3192 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3193 {
3194         int i, err = 0;
3195
3196         for (i = 0; i < adapter->num_tx_queues; i++) {
3197                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3198                 if (!err)
3199                         continue;
3200                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3201                 break;
3202         }
3203
3204         return err;
3205 }
3206
3207 /**
3208  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3209  * @adapter: board private structure
3210  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3211  *
3212  * Returns 0 on success, negative on failure
3213  **/
3214 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3215                              struct ixgbe_ring *rx_ring)
3216 {
3217         struct pci_dev *pdev = adapter->pdev;
3218         int size;
3219
3220         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3221         rx_ring->rx_buffer_info = vmalloc(size);
3222         if (!rx_ring->rx_buffer_info) {
3223                 DPRINTK(PROBE, ERR,
3224                         "vmalloc allocation failed for the rx desc ring\n");
3225                 goto alloc_failed;
3226         }
3227         memset(rx_ring->rx_buffer_info, 0, size);
3228
3229         /* Round up to nearest 4K */
3230         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3231         rx_ring->size = ALIGN(rx_ring->size, 4096);
3232
3233         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3234
3235         if (!rx_ring->desc) {
3236                 DPRINTK(PROBE, ERR,
3237                         "Memory allocation failed for the rx desc ring\n");
3238                 vfree(rx_ring->rx_buffer_info);
3239                 goto alloc_failed;
3240         }
3241
3242         rx_ring->next_to_clean = 0;
3243         rx_ring->next_to_use = 0;
3244
3245         return 0;
3246
3247 alloc_failed:
3248         return -ENOMEM;
3249 }
3250
3251 /**
3252  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3253  * @adapter: board private structure
3254  *
3255  * If this function returns with an error, then it's possible one or
3256  * more of the rings is populated (while the rest are not).  It is the
3257  * callers duty to clean those orphaned rings.
3258  *
3259  * Return 0 on success, negative on failure
3260  **/
3261
3262 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3263 {
3264         int i, err = 0;
3265
3266         for (i = 0; i < adapter->num_rx_queues; i++) {
3267                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3268                 if (!err)
3269                         continue;
3270                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3271                 break;
3272         }
3273
3274         return err;
3275 }
3276
3277 /**
3278  * ixgbe_free_tx_resources - Free Tx Resources per Queue
3279  * @adapter: board private structure
3280  * @tx_ring: Tx descriptor ring for a specific queue
3281  *
3282  * Free all transmit software resources
3283  **/
3284 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3285                              struct ixgbe_ring *tx_ring)
3286 {
3287         struct pci_dev *pdev = adapter->pdev;
3288
3289         ixgbe_clean_tx_ring(adapter, tx_ring);
3290
3291         vfree(tx_ring->tx_buffer_info);
3292         tx_ring->tx_buffer_info = NULL;
3293
3294         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3295
3296         tx_ring->desc = NULL;
3297 }
3298
3299 /**
3300  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3301  * @adapter: board private structure
3302  *
3303  * Free all transmit software resources
3304  **/
3305 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3306 {
3307         int i;
3308
3309         for (i = 0; i < adapter->num_tx_queues; i++)
3310                 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
3311 }
3312
3313 /**
3314  * ixgbe_free_rx_resources - Free Rx Resources
3315  * @adapter: board private structure
3316  * @rx_ring: ring to clean the resources from
3317  *
3318  * Free all receive software resources
3319  **/
3320 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3321                              struct ixgbe_ring *rx_ring)
3322 {
3323         struct pci_dev *pdev = adapter->pdev;
3324
3325         ixgbe_clean_rx_ring(adapter, rx_ring);
3326
3327         vfree(rx_ring->rx_buffer_info);
3328         rx_ring->rx_buffer_info = NULL;
3329
3330         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3331
3332         rx_ring->desc = NULL;
3333 }
3334
3335 /**
3336  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3337  * @adapter: board private structure
3338  *
3339  * Free all receive software resources
3340  **/
3341 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3342 {
3343         int i;
3344
3345         for (i = 0; i < adapter->num_rx_queues; i++)
3346                 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
3347 }
3348
3349 /**
3350  * ixgbe_change_mtu - Change the Maximum Transfer Unit
3351  * @netdev: network interface device structure
3352  * @new_mtu: new value for maximum frame size
3353  *
3354  * Returns 0 on success, negative on failure
3355  **/
3356 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3357 {
3358         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3359         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3360
3361         /* MTU < 68 is an error and causes problems on some kernels */
3362         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
3363                 return -EINVAL;
3364
3365         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
3366                 netdev->mtu, new_mtu);
3367         /* must set new MTU before calling down or up */
3368         netdev->mtu = new_mtu;
3369
3370         if (netif_running(netdev))
3371                 ixgbe_reinit_locked(adapter);
3372
3373         return 0;
3374 }
3375
3376 /**
3377  * ixgbe_open - Called when a network interface is made active
3378  * @netdev: network interface device structure
3379  *
3380  * Returns 0 on success, negative value on failure
3381  *
3382  * The open entry point is called when a network interface is made
3383  * active by the system (IFF_UP).  At this point all resources needed
3384  * for transmit and receive operations are allocated, the interrupt
3385  * handler is registered with the OS, the watchdog timer is started,
3386  * and the stack is notified that the interface is ready.
3387  **/
3388 static int ixgbe_open(struct net_device *netdev)
3389 {
3390         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3391         int err;
3392
3393         /* disallow open during test */
3394         if (test_bit(__IXGBE_TESTING, &adapter->state))
3395                 return -EBUSY;
3396
3397         /* allocate transmit descriptors */
3398         err = ixgbe_setup_all_tx_resources(adapter);
3399         if (err)
3400                 goto err_setup_tx;
3401
3402         /* allocate receive descriptors */
3403         err = ixgbe_setup_all_rx_resources(adapter);
3404         if (err)
3405                 goto err_setup_rx;
3406
3407         ixgbe_configure(adapter);
3408
3409         err = ixgbe_request_irq(adapter);
3410         if (err)
3411                 goto err_req_irq;
3412
3413         err = ixgbe_up_complete(adapter);
3414         if (err)
3415                 goto err_up;
3416
3417         netif_tx_start_all_queues(netdev);
3418
3419         return 0;
3420
3421 err_up:
3422         ixgbe_release_hw_control(adapter);
3423         ixgbe_free_irq(adapter);
3424 err_req_irq:
3425         ixgbe_free_all_rx_resources(adapter);
3426 err_setup_rx:
3427         ixgbe_free_all_tx_resources(adapter);
3428 err_setup_tx:
3429         ixgbe_reset(adapter);
3430
3431         return err;
3432 }
3433
3434 /**
3435  * ixgbe_close - Disables a network interface
3436  * @netdev: network interface device structure
3437  *
3438  * Returns 0, this is not allowed to fail
3439  *
3440  * The close entry point is called when an interface is de-activated
3441  * by the OS.  The hardware is still under the drivers control, but
3442  * needs to be disabled.  A global MAC reset is issued to stop the
3443  * hardware, and all transmit and receive resources are freed.
3444  **/
3445 static int ixgbe_close(struct net_device *netdev)
3446 {
3447         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3448
3449         ixgbe_down(adapter);
3450         ixgbe_free_irq(adapter);
3451
3452         ixgbe_free_all_tx_resources(adapter);
3453         ixgbe_free_all_rx_resources(adapter);
3454
3455         ixgbe_release_hw_control(adapter);
3456
3457         return 0;
3458 }
3459
3460 /**
3461  * ixgbe_napi_add_all - prep napi structs for use
3462  * @adapter: private struct
3463  * helper function to napi_add each possible q_vector->napi
3464  */
3465 void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
3466 {
3467         int q_idx, q_vectors;
3468         struct net_device *netdev = adapter->netdev;
3469         int (*poll)(struct napi_struct *, int);
3470
3471         /* check if we already have our netdev->napi_list populated */
3472         if (&netdev->napi_list != netdev->napi_list.next)
3473                 return;
3474
3475         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3476                 poll = &ixgbe_clean_rxonly;
3477                 /* Only enable as many vectors as we have rx queues. */
3478                 q_vectors = adapter->num_rx_queues;
3479         } else {
3480                 poll = &ixgbe_poll;
3481                 /* only one q_vector for legacy modes */
3482                 q_vectors = 1;
3483         }
3484
3485         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3486                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3487                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3488         }
3489 }
3490
3491 void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
3492 {
3493         int q_idx;
3494         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3495
3496         /* legacy and MSI only use one vector */
3497         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3498                 q_vectors = 1;
3499
3500         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3501                 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3502                 if (!q_vector->rxr_count)
3503                         continue;
3504                 netif_napi_del(&q_vector->napi);
3505         }
3506 }
3507
3508 #ifdef CONFIG_PM
3509 static int ixgbe_resume(struct pci_dev *pdev)
3510 {
3511         struct net_device *netdev = pci_get_drvdata(pdev);
3512         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3513         u32 err;
3514
3515         pci_set_power_state(pdev, PCI_D0);
3516         pci_restore_state(pdev);
3517         err = pci_enable_device(pdev);
3518         if (err) {
3519                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
3520                                 "suspend\n");
3521                 return err;
3522         }
3523         pci_set_master(pdev);
3524
3525         pci_enable_wake(pdev, PCI_D3hot, 0);
3526         pci_enable_wake(pdev, PCI_D3cold, 0);
3527
3528         err = ixgbe_init_interrupt_scheme(adapter);
3529         if (err) {
3530                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3531                                 "device\n");
3532                 return err;
3533         }
3534
3535         ixgbe_napi_add_all(adapter);
3536         ixgbe_reset(adapter);
3537
3538         if (netif_running(netdev)) {
3539                 err = ixgbe_open(adapter->netdev);
3540                 if (err)
3541                         return err;
3542         }
3543
3544         netif_device_attach(netdev);
3545
3546         return 0;
3547 }
3548
3549 #endif /* CONFIG_PM */
3550 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3551 {
3552         struct net_device *netdev = pci_get_drvdata(pdev);
3553         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3554         struct ixgbe_hw *hw = &adapter->hw;
3555         u32 ctrl, fctrl;
3556         u32 wufc = adapter->wol;
3557 #ifdef CONFIG_PM
3558         int retval = 0;
3559 #endif
3560
3561         netif_device_detach(netdev);
3562
3563         if (netif_running(netdev)) {
3564                 ixgbe_down(adapter);
3565                 ixgbe_free_irq(adapter);
3566                 ixgbe_free_all_tx_resources(adapter);
3567                 ixgbe_free_all_rx_resources(adapter);
3568         }
3569         ixgbe_reset_interrupt_capability(adapter);
3570         ixgbe_napi_del_all(adapter);
3571         INIT_LIST_HEAD(&netdev->napi_list);
3572         kfree(adapter->tx_ring);
3573         kfree(adapter->rx_ring);
3574
3575 #ifdef CONFIG_PM
3576         retval = pci_save_state(pdev);
3577         if (retval)
3578                 return retval;
3579 #endif
3580         if (wufc) {
3581                 ixgbe_set_rx_mode(netdev);
3582
3583                 /* turn on all-multi mode if wake on multicast is enabled */
3584                 if (wufc & IXGBE_WUFC_MC) {
3585                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3586                         fctrl |= IXGBE_FCTRL_MPE;
3587                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3588                 }
3589
3590                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3591                 ctrl |= IXGBE_CTRL_GIO_DIS;
3592                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3593
3594                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3595         } else {
3596                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3597                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3598         }
3599
3600         if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3601                 pci_enable_wake(pdev, PCI_D3hot, 1);
3602                 pci_enable_wake(pdev, PCI_D3cold, 1);
3603         } else {
3604                 pci_enable_wake(pdev, PCI_D3hot, 0);
3605                 pci_enable_wake(pdev, PCI_D3cold, 0);
3606         }
3607
3608         ixgbe_release_hw_control(adapter);
3609
3610         pci_disable_device(pdev);
3611
3612         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3613
3614         return 0;
3615 }
3616
3617 static void ixgbe_shutdown(struct pci_dev *pdev)
3618 {
3619         ixgbe_suspend(pdev, PMSG_SUSPEND);
3620 }
3621
3622 /**
3623  * ixgbe_update_stats - Update the board statistics counters.
3624  * @adapter: board private structure
3625  **/
3626 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3627 {
3628         struct ixgbe_hw *hw = &adapter->hw;
3629         u64 total_mpc = 0;
3630         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3631
3632         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3633         for (i = 0; i < 8; i++) {
3634                 /* for packet buffers not used, the register should read 0 */
3635                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3636                 missed_rx += mpc;
3637                 adapter->stats.mpc[i] += mpc;
3638                 total_mpc += adapter->stats.mpc[i];
3639                 if (hw->mac.type == ixgbe_mac_82598EB)
3640                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3641                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3642                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3643                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3644                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3645                 if (hw->mac.type == ixgbe_mac_82599EB) {
3646                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3647                                                             IXGBE_PXONRXCNT(i));
3648                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3649                                                            IXGBE_PXOFFRXCNT(i));
3650                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3651                         adapter->hw_rx_no_dma_resources += adapter->stats.qprdc[i];
3652                 } else {
3653                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3654                                                               IXGBE_PXONRXC(i));
3655                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3656                                                              IXGBE_PXOFFRXC(i));
3657                 }
3658                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3659                                                             IXGBE_PXONTXC(i));
3660                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3661                                                              IXGBE_PXOFFTXC(i));
3662         }
3663         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3664         /* work around hardware counting issue */
3665         adapter->stats.gprc -= missed_rx;
3666
3667         /* 82598 hardware only has a 32 bit counter in the high register */
3668         if (hw->mac.type == ixgbe_mac_82599EB) {
3669                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3670                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3671                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3672                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3673                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3674                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3675                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3676                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3677         } else {
3678                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3679                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3680                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3681                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3682                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3683         }
3684         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3685         adapter->stats.bprc += bprc;
3686         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3687         if (hw->mac.type == ixgbe_mac_82598EB)
3688                 adapter->stats.mprc -= bprc;
3689         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3690         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3691         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3692         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3693         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3694         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3695         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3696         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3697         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3698         adapter->stats.lxontxc += lxon;
3699         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3700         adapter->stats.lxofftxc += lxoff;
3701         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3702         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3703         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3704         /*
3705          * 82598 errata - tx of flow control packets is included in tx counters
3706          */
3707         xon_off_tot = lxon + lxoff;
3708         adapter->stats.gptc -= xon_off_tot;
3709         adapter->stats.mptc -= xon_off_tot;
3710         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3711         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3712         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3713         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3714         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3715         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3716         adapter->stats.ptc64 -= xon_off_tot;
3717         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3718         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3719         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3720         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3721         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3722         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3723
3724         /* Fill out the OS statistics structure */
3725         adapter->net_stats.multicast = adapter->stats.mprc;
3726
3727         /* Rx Errors */
3728         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3729                                        adapter->stats.rlec;
3730         adapter->net_stats.rx_dropped = 0;
3731         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3732         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3733         adapter->net_stats.rx_missed_errors = total_mpc;
3734 }
3735
3736 /**
3737  * ixgbe_watchdog - Timer Call-back
3738  * @data: pointer to adapter cast into an unsigned long
3739  **/
3740 static void ixgbe_watchdog(unsigned long data)
3741 {
3742         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3743         struct ixgbe_hw *hw = &adapter->hw;
3744
3745         /* Do the watchdog outside of interrupt context due to the lovely
3746          * delays that some of the newer hardware requires */
3747         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3748                 /* Cause software interrupt to ensure rx rings are cleaned */
3749                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3750                         u32 eics =
3751                          (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3752                         IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3753                 } else {
3754                         /* For legacy and MSI interrupts don't set any bits that
3755                          * are enabled for EIAM, because this operation would
3756                          * set *both* EIMS and EICS for any bit in EIAM */
3757                         IXGBE_WRITE_REG(hw, IXGBE_EICS,
3758                                     (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3759                 }
3760                 /* Reset the timer */
3761                 mod_timer(&adapter->watchdog_timer,
3762                           round_jiffies(jiffies + 2 * HZ));
3763         }
3764
3765         schedule_work(&adapter->watchdog_task);
3766 }
3767
3768 /**
3769  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
3770  * @work: pointer to work_struct containing our data
3771  **/
3772 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
3773 {
3774         struct ixgbe_adapter *adapter = container_of(work,
3775                                                      struct ixgbe_adapter,
3776                                                      multispeed_fiber_task);
3777         struct ixgbe_hw *hw = &adapter->hw;
3778         u32 autoneg;
3779
3780         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
3781         if (hw->mac.ops.get_link_capabilities)
3782                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
3783                                                   &hw->mac.autoneg);
3784         if (hw->mac.ops.setup_link_speed)
3785                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3786         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3787         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
3788 }
3789
3790 /**
3791  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
3792  * @work: pointer to work_struct containing our data
3793  **/
3794 static void ixgbe_sfp_config_module_task(struct work_struct *work)
3795 {
3796         struct ixgbe_adapter *adapter = container_of(work,
3797                                                      struct ixgbe_adapter,
3798                                                      sfp_config_module_task);
3799         struct ixgbe_hw *hw = &adapter->hw;
3800         u32 err;
3801
3802         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
3803         err = hw->phy.ops.identify_sfp(hw);
3804         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3805                 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
3806                 ixgbe_down(adapter);
3807                 return;
3808         }
3809         hw->mac.ops.setup_sfp(hw);
3810
3811         if (!adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)
3812                 /* This will also work for DA Twinax connections */
3813                 schedule_work(&adapter->multispeed_fiber_task);
3814         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
3815 }
3816
3817 /**
3818  * ixgbe_watchdog_task - worker thread to bring link up
3819  * @work: pointer to work_struct containing our data
3820  **/
3821 static void ixgbe_watchdog_task(struct work_struct *work)
3822 {
3823         struct ixgbe_adapter *adapter = container_of(work,
3824                                                      struct ixgbe_adapter,
3825                                                      watchdog_task);
3826         struct net_device *netdev = adapter->netdev;
3827         struct ixgbe_hw *hw = &adapter->hw;
3828         u32 link_speed = adapter->link_speed;
3829         bool link_up = adapter->link_up;
3830
3831         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3832
3833         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3834                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3835                 if (link_up ||
3836                     time_after(jiffies, (adapter->link_check_timeout +
3837                                          IXGBE_TRY_LINK_TIMEOUT))) {
3838                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3839                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3840                 }
3841                 adapter->link_up = link_up;
3842                 adapter->link_speed = link_speed;
3843         }
3844
3845         if (link_up) {
3846                 if (!netif_carrier_ok(netdev)) {
3847                         bool flow_rx, flow_tx;
3848
3849                         if (hw->mac.type == ixgbe_mac_82599EB) {
3850                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3851                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3852                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
3853                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
3854                         } else {
3855                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3856                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3857                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
3858                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
3859                         }
3860
3861                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
3862                                "Flow Control: %s\n",
3863                                netdev->name,
3864                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3865                                 "10 Gbps" :
3866                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3867                                  "1 Gbps" : "unknown speed")),
3868                                ((flow_rx && flow_tx) ? "RX/TX" :
3869                                 (flow_rx ? "RX" :
3870                                 (flow_tx ? "TX" : "None"))));
3871
3872                         netif_carrier_on(netdev);
3873                 } else {
3874                         /* Force detection of hung controller */
3875                         adapter->detect_tx_hung = true;
3876                 }
3877         } else {
3878                 adapter->link_up = false;
3879                 adapter->link_speed = 0;
3880                 if (netif_carrier_ok(netdev)) {
3881                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
3882                                netdev->name);
3883                         netif_carrier_off(netdev);
3884                 }
3885         }
3886
3887         ixgbe_update_stats(adapter);
3888         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3889 }
3890
3891 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3892                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3893                      u32 tx_flags, u8 *hdr_len)
3894 {
3895         struct ixgbe_adv_tx_context_desc *context_desc;
3896         unsigned int i;
3897         int err;
3898         struct ixgbe_tx_buffer *tx_buffer_info;
3899         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3900         u32 mss_l4len_idx, l4len;
3901
3902         if (skb_is_gso(skb)) {
3903                 if (skb_header_cloned(skb)) {
3904                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3905                         if (err)
3906                                 return err;
3907                 }
3908                 l4len = tcp_hdrlen(skb);
3909                 *hdr_len += l4len;
3910
3911                 if (skb->protocol == htons(ETH_P_IP)) {
3912                         struct iphdr *iph = ip_hdr(skb);
3913                         iph->tot_len = 0;
3914                         iph->check = 0;
3915                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3916                                                                  iph->daddr, 0,
3917                                                                  IPPROTO_TCP,
3918                                                                  0);
3919                         adapter->hw_tso_ctxt++;
3920                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3921                         ipv6_hdr(skb)->payload_len = 0;
3922                         tcp_hdr(skb)->check =
3923                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3924                                              &ipv6_hdr(skb)->daddr,
3925                                              0, IPPROTO_TCP, 0);
3926                         adapter->hw_tso6_ctxt++;
3927                 }
3928
3929                 i = tx_ring->next_to_use;
3930
3931                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3932                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3933
3934                 /* VLAN MACLEN IPLEN */
3935                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3936                         vlan_macip_lens |=
3937                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3938                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3939                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3940                 *hdr_len += skb_network_offset(skb);
3941                 vlan_macip_lens |=
3942                     (skb_transport_header(skb) - skb_network_header(skb));
3943                 *hdr_len +=
3944                     (skb_transport_header(skb) - skb_network_header(skb));
3945                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3946                 context_desc->seqnum_seed = 0;
3947
3948                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3949                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
3950                                    IXGBE_ADVTXD_DTYP_CTXT);
3951
3952                 if (skb->protocol == htons(ETH_P_IP))
3953                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3954                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3955                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3956
3957                 /* MSS L4LEN IDX */
3958                 mss_l4len_idx =
3959                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3960                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3961                 /* use index 1 for TSO */
3962                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3963                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3964
3965                 tx_buffer_info->time_stamp = jiffies;
3966                 tx_buffer_info->next_to_watch = i;
3967
3968                 i++;
3969                 if (i == tx_ring->count)
3970                         i = 0;
3971                 tx_ring->next_to_use = i;
3972
3973                 return true;
3974         }
3975         return false;
3976 }
3977
3978 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3979                           struct ixgbe_ring *tx_ring,
3980                           struct sk_buff *skb, u32 tx_flags)
3981 {
3982         struct ixgbe_adv_tx_context_desc *context_desc;
3983         unsigned int i;
3984         struct ixgbe_tx_buffer *tx_buffer_info;
3985         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3986
3987         if (skb->ip_summed == CHECKSUM_PARTIAL ||
3988             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3989                 i = tx_ring->next_to_use;
3990                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3991                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3992
3993                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3994                         vlan_macip_lens |=
3995                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3996                 vlan_macip_lens |= (skb_network_offset(skb) <<
3997                                     IXGBE_ADVTXD_MACLEN_SHIFT);
3998                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3999                         vlan_macip_lens |= (skb_transport_header(skb) -
4000                                             skb_network_header(skb));
4001
4002                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4003                 context_desc->seqnum_seed = 0;
4004
4005                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4006                                     IXGBE_ADVTXD_DTYP_CTXT);
4007
4008                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4009                         switch (skb->protocol) {
4010                         case cpu_to_be16(ETH_P_IP):
4011                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4012                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4013                                         type_tucmd_mlhl |=
4014                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4015                                 break;
4016                         case cpu_to_be16(ETH_P_IPV6):
4017                                 /* XXX what about other V6 headers?? */
4018                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4019                                         type_tucmd_mlhl |=
4020                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4021                                 break;
4022                         default:
4023                                 if (unlikely(net_ratelimit())) {
4024                                         DPRINTK(PROBE, WARNING,
4025                                          "partial checksum but proto=%x!\n",
4026                                          skb->protocol);
4027                                 }
4028                                 break;
4029                         }
4030                 }
4031
4032                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4033                 /* use index zero for tx checksum offload */
4034                 context_desc->mss_l4len_idx = 0;
4035
4036                 tx_buffer_info->time_stamp = jiffies;
4037                 tx_buffer_info->next_to_watch = i;
4038
4039                 adapter->hw_csum_tx_good++;
4040                 i++;
4041                 if (i == tx_ring->count)
4042                         i = 0;
4043                 tx_ring->next_to_use = i;
4044
4045                 return true;
4046         }
4047
4048         return false;
4049 }
4050
4051 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4052                         struct ixgbe_ring *tx_ring,
4053                         struct sk_buff *skb, unsigned int first)
4054 {
4055         struct ixgbe_tx_buffer *tx_buffer_info;
4056         unsigned int len = skb->len;
4057         unsigned int offset = 0, size, count = 0, i;
4058         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4059         unsigned int f;
4060
4061         len -= skb->data_len;
4062
4063         i = tx_ring->next_to_use;
4064
4065         while (len) {
4066                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4067                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4068
4069                 tx_buffer_info->length = size;
4070                 tx_buffer_info->dma = pci_map_single(adapter->pdev,
4071                                                      skb->data + offset,
4072                                                      size, PCI_DMA_TODEVICE);
4073                 tx_buffer_info->time_stamp = jiffies;
4074                 tx_buffer_info->next_to_watch = i;
4075
4076                 len -= size;
4077                 offset += size;
4078                 count++;
4079                 i++;
4080                 if (i == tx_ring->count)
4081                         i = 0;
4082         }
4083
4084         for (f = 0; f < nr_frags; f++) {
4085                 struct skb_frag_struct *frag;
4086
4087                 frag = &skb_shinfo(skb)->frags[f];
4088                 len = frag->size;
4089                 offset = frag->page_offset;
4090
4091                 while (len) {
4092                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4093                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4094
4095                         tx_buffer_info->length = size;
4096                         tx_buffer_info->dma = pci_map_page(adapter->pdev,
4097                                                            frag->page,
4098                                                            offset,
4099                                                            size,
4100                                                            PCI_DMA_TODEVICE);
4101                         tx_buffer_info->time_stamp = jiffies;
4102                         tx_buffer_info->next_to_watch = i;
4103
4104                         len -= size;
4105                         offset += size;
4106                         count++;
4107                         i++;
4108                         if (i == tx_ring->count)
4109                                 i = 0;
4110                 }
4111         }
4112         if (i == 0)
4113                 i = tx_ring->count - 1;
4114         else
4115                 i = i - 1;
4116         tx_ring->tx_buffer_info[i].skb = skb;
4117         tx_ring->tx_buffer_info[first].next_to_watch = i;
4118
4119         return count;
4120 }
4121
4122 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4123                            struct ixgbe_ring *tx_ring,
4124                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4125 {
4126         union ixgbe_adv_tx_desc *tx_desc = NULL;
4127         struct ixgbe_tx_buffer *tx_buffer_info;
4128         u32 olinfo_status = 0, cmd_type_len = 0;
4129         unsigned int i;
4130         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4131
4132         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4133
4134         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4135
4136         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4137                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4138
4139         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4140                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4141
4142                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4143                                  IXGBE_ADVTXD_POPTS_SHIFT;
4144
4145                 /* use index 1 context for tso */
4146                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4147                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4148                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4149                                          IXGBE_ADVTXD_POPTS_SHIFT;
4150
4151         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4152                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4153                                  IXGBE_ADVTXD_POPTS_SHIFT;
4154
4155         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4156
4157         i = tx_ring->next_to_use;
4158         while (count--) {
4159                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4160                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4161                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4162                 tx_desc->read.cmd_type_len =
4163                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4164                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4165                 i++;
4166                 if (i == tx_ring->count)
4167                         i = 0;
4168         }
4169
4170         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4171
4172         /*
4173          * Force memory writes to complete before letting h/w
4174          * know there are new descriptors to fetch.  (Only
4175          * applicable for weak-ordered memory model archs,
4176          * such as IA-64).
4177          */
4178         wmb();
4179
4180         tx_ring->next_to_use = i;
4181         writel(i, adapter->hw.hw_addr + tx_ring->tail);
4182 }
4183
4184 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
4185                                  struct ixgbe_ring *tx_ring, int size)
4186 {
4187         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4188
4189         netif_stop_subqueue(netdev, tx_ring->queue_index);
4190         /* Herbert's original patch had:
4191          *  smp_mb__after_netif_stop_queue();
4192          * but since that doesn't exist yet, just open code it. */
4193         smp_mb();
4194
4195         /* We need to check again in a case another CPU has just
4196          * made room available. */
4197         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4198                 return -EBUSY;
4199
4200         /* A reprieve! - use start_queue because it doesn't call schedule */
4201         netif_start_subqueue(netdev, tx_ring->queue_index);
4202         ++adapter->restart_queue;
4203         return 0;
4204 }
4205
4206 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
4207                               struct ixgbe_ring *tx_ring, int size)
4208 {
4209         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4210                 return 0;
4211         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4212 }
4213
4214 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4215 {
4216         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4217         struct ixgbe_ring *tx_ring;
4218         unsigned int first;
4219         unsigned int tx_flags = 0;
4220         u8 hdr_len = 0;
4221         int r_idx = 0, tso;
4222         int count = 0;
4223         unsigned int f;
4224
4225         r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
4226         tx_ring = &adapter->tx_ring[r_idx];
4227
4228         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4229                 tx_flags |= vlan_tx_tag_get(skb);
4230                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4231                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4232                         tx_flags |= (skb->queue_mapping << 13);
4233                 }
4234                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4235                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4236         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4237                 tx_flags |= (skb->queue_mapping << 13);
4238                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4239                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4240         }
4241         /* three things can cause us to need a context descriptor */
4242         if (skb_is_gso(skb) ||
4243             (skb->ip_summed == CHECKSUM_PARTIAL) ||
4244             (tx_flags & IXGBE_TX_FLAGS_VLAN))
4245                 count++;
4246
4247         count += TXD_USE_COUNT(skb_headlen(skb));
4248         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4249                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4250
4251         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
4252                 adapter->tx_busy++;
4253                 return NETDEV_TX_BUSY;
4254         }
4255
4256         if (skb->protocol == htons(ETH_P_IP))
4257                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4258         first = tx_ring->next_to_use;
4259         tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4260         if (tso < 0) {
4261                 dev_kfree_skb_any(skb);
4262                 return NETDEV_TX_OK;
4263         }
4264
4265         if (tso)
4266                 tx_flags |= IXGBE_TX_FLAGS_TSO;
4267         else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4268                  (skb->ip_summed == CHECKSUM_PARTIAL))
4269                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4270
4271         ixgbe_tx_queue(adapter, tx_ring, tx_flags,
4272                        ixgbe_tx_map(adapter, tx_ring, skb, first),
4273                        skb->len, hdr_len);
4274
4275         netdev->trans_start = jiffies;
4276
4277         ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
4278
4279         return NETDEV_TX_OK;
4280 }
4281
4282 /**
4283  * ixgbe_get_stats - Get System Network Statistics
4284  * @netdev: network interface device structure
4285  *
4286  * Returns the address of the device statistics structure.
4287  * The statistics are actually updated from the timer callback.
4288  **/
4289 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4290 {
4291         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4292
4293         /* only return the current stats */
4294         return &adapter->net_stats;
4295 }
4296
4297 /**
4298  * ixgbe_set_mac - Change the Ethernet Address of the NIC
4299  * @netdev: network interface device structure
4300  * @p: pointer to an address structure
4301  *
4302  * Returns 0 on success, negative on failure
4303  **/
4304 static int ixgbe_set_mac(struct net_device *netdev, void *p)
4305 {
4306         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4307         struct ixgbe_hw *hw = &adapter->hw;
4308         struct sockaddr *addr = p;
4309
4310         if (!is_valid_ether_addr(addr->sa_data))
4311                 return -EADDRNOTAVAIL;
4312
4313         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4314         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4315
4316         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4317
4318         return 0;
4319 }
4320
4321 #ifdef CONFIG_NET_POLL_CONTROLLER
4322 /*
4323  * Polling 'interrupt' - used by things like netconsole to send skbs
4324  * without having to re-enable interrupts. It's not called while
4325  * the interrupt routine is executing.
4326  */
4327 static void ixgbe_netpoll(struct net_device *netdev)
4328 {
4329         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4330
4331         disable_irq(adapter->pdev->irq);
4332         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4333         ixgbe_intr(adapter->pdev->irq, netdev);
4334         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4335         enable_irq(adapter->pdev->irq);
4336 }
4337 #endif
4338
4339 static const struct net_device_ops ixgbe_netdev_ops = {
4340         .ndo_open               = ixgbe_open,
4341         .ndo_stop               = ixgbe_close,
4342         .ndo_start_xmit         = ixgbe_xmit_frame,
4343         .ndo_get_stats          = ixgbe_get_stats,
4344         .ndo_set_multicast_list = ixgbe_set_rx_mode,
4345         .ndo_validate_addr      = eth_validate_addr,
4346         .ndo_set_mac_address    = ixgbe_set_mac,
4347         .ndo_change_mtu         = ixgbe_change_mtu,
4348         .ndo_tx_timeout         = ixgbe_tx_timeout,
4349         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
4350         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
4351         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
4352 #ifdef CONFIG_NET_POLL_CONTROLLER
4353         .ndo_poll_controller    = ixgbe_netpoll,
4354 #endif
4355 };
4356
4357 /**
4358  * ixgbe_probe - Device Initialization Routine
4359  * @pdev: PCI device information struct
4360  * @ent: entry in ixgbe_pci_tbl
4361  *
4362  * Returns 0 on success, negative on failure
4363  *
4364  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4365  * The OS initialization, configuring of the adapter private structure,
4366  * and a hardware reset occur.
4367  **/
4368 static int __devinit ixgbe_probe(struct pci_dev *pdev,
4369                                  const struct pci_device_id *ent)
4370 {
4371         struct net_device *netdev;
4372         struct ixgbe_adapter *adapter = NULL;
4373         struct ixgbe_hw *hw;
4374         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
4375         static int cards_found;
4376         int i, err, pci_using_dac;
4377         u16 pm_value = 0;
4378         u32 part_num, eec;
4379
4380         err = pci_enable_device(pdev);
4381         if (err)
4382                 return err;
4383
4384         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
4385             !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
4386                 pci_using_dac = 1;
4387         } else {
4388                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4389                 if (err) {
4390                         err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
4391                         if (err) {
4392                                 dev_err(&pdev->dev, "No usable DMA "
4393                                         "configuration, aborting\n");
4394                                 goto err_dma;
4395                         }
4396                 }
4397                 pci_using_dac = 0;
4398         }
4399
4400         err = pci_request_regions(pdev, ixgbe_driver_name);
4401         if (err) {
4402                 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4403                 goto err_pci_reg;
4404         }
4405
4406         err = pci_enable_pcie_error_reporting(pdev);
4407         if (err) {
4408                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4409                                     "0x%x\n", err);
4410                 /* non-fatal, continue */
4411         }
4412
4413         pci_set_master(pdev);
4414         pci_save_state(pdev);
4415
4416         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
4417         if (!netdev) {
4418                 err = -ENOMEM;
4419                 goto err_alloc_etherdev;
4420         }
4421
4422         SET_NETDEV_DEV(netdev, &pdev->dev);
4423
4424         pci_set_drvdata(pdev, netdev);
4425         adapter = netdev_priv(netdev);
4426
4427         adapter->netdev = netdev;
4428         adapter->pdev = pdev;
4429         hw = &adapter->hw;
4430         hw->back = adapter;
4431         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4432
4433         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4434                               pci_resource_len(pdev, 0));
4435         if (!hw->hw_addr) {
4436                 err = -EIO;
4437                 goto err_ioremap;
4438         }
4439
4440         for (i = 1; i <= 5; i++) {
4441                 if (pci_resource_len(pdev, i) == 0)
4442                         continue;
4443         }
4444
4445         netdev->netdev_ops = &ixgbe_netdev_ops;
4446         ixgbe_set_ethtool_ops(netdev);
4447         netdev->watchdog_timeo = 5 * HZ;
4448         strcpy(netdev->name, pci_name(pdev));
4449
4450         adapter->bd_number = cards_found;
4451
4452         /* Setup hw api */
4453         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
4454         hw->mac.type  = ii->mac;
4455
4456         /* EEPROM */
4457         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4458         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4459         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4460         if (!(eec & (1 << 8)))
4461                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4462
4463         /* PHY */
4464         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4465         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4466
4467         /* set up this timer and work struct before calling get_invariants
4468          * which might start the timer
4469          */
4470         init_timer(&adapter->sfp_timer);
4471         adapter->sfp_timer.function = &ixgbe_sfp_timer;
4472         adapter->sfp_timer.data = (unsigned long) adapter;
4473
4474         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4475
4476         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4477         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4478
4479         /* a new SFP+ module arrival, called from GPI SDP2 context */
4480         INIT_WORK(&adapter->sfp_config_module_task,
4481                   ixgbe_sfp_config_module_task);
4482
4483         err = ii->get_invariants(hw);
4484         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4485                 /* start a kernel thread to watch for a module to arrive */
4486                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4487                 mod_timer(&adapter->sfp_timer,
4488                           round_jiffies(jiffies + (2 * HZ)));
4489                 err = 0;
4490         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4491                 DPRINTK(PROBE, ERR, "failed to load because an "
4492                         "unsupported SFP+ module type was detected.\n");
4493                 goto err_hw_init;
4494         } else if (err) {
4495                 goto err_hw_init;
4496         }
4497
4498         /* setup the private structure */
4499         err = ixgbe_sw_init(adapter);
4500         if (err)
4501                 goto err_sw_init;
4502
4503         /* reset_hw fills in the perm_addr as well */
4504         err = hw->mac.ops.reset_hw(hw);
4505         if (err) {
4506                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4507                 goto err_sw_init;
4508         }
4509
4510         netdev->features = NETIF_F_SG |
4511                            NETIF_F_IP_CSUM |
4512                            NETIF_F_HW_VLAN_TX |
4513                            NETIF_F_HW_VLAN_RX |
4514                            NETIF_F_HW_VLAN_FILTER;
4515
4516         netdev->features |= NETIF_F_IPV6_CSUM;
4517         netdev->features |= NETIF_F_TSO;
4518         netdev->features |= NETIF_F_TSO6;
4519         netdev->features |= NETIF_F_GRO;
4520
4521         netdev->vlan_features |= NETIF_F_TSO;
4522         netdev->vlan_features |= NETIF_F_TSO6;
4523         netdev->vlan_features |= NETIF_F_IP_CSUM;
4524         netdev->vlan_features |= NETIF_F_SG;
4525
4526         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4527                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4528
4529 #ifdef CONFIG_IXGBE_DCB
4530         netdev->dcbnl_ops = &dcbnl_ops;
4531 #endif
4532
4533         if (pci_using_dac)
4534                 netdev->features |= NETIF_F_HIGHDMA;
4535
4536         /* make sure the EEPROM is good */
4537         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
4538                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4539                 err = -EIO;
4540                 goto err_eeprom;
4541         }
4542
4543         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4544         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4545
4546         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4547                 dev_err(&pdev->dev, "invalid MAC address\n");
4548                 err = -EIO;
4549                 goto err_eeprom;
4550         }
4551
4552         init_timer(&adapter->watchdog_timer);
4553         adapter->watchdog_timer.function = &ixgbe_watchdog;
4554         adapter->watchdog_timer.data = (unsigned long)adapter;
4555
4556         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
4557         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
4558
4559         err = ixgbe_init_interrupt_scheme(adapter);
4560         if (err)
4561                 goto err_sw_init;
4562
4563         switch (pdev->device) {
4564         case IXGBE_DEV_ID_82599_KX4:
4565 #define IXGBE_PCIE_PMCSR 0x44
4566                 adapter->wol = IXGBE_WUFC_MAG;
4567                 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4568                 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4569                                       (pm_value | (1 << 8)));
4570                 break;
4571         default:
4572                 adapter->wol = 0;
4573                 break;
4574         }
4575         device_init_wakeup(&adapter->pdev->dev, true);
4576         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4577
4578         /* print bus type/speed/width info */
4579         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
4580                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4581                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4582                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4583                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4584                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
4585                  "Unknown"),
4586                 netdev->dev_addr);
4587         ixgbe_read_pba_num_generic(hw, &part_num);
4588         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4589                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4590                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4591                          (part_num >> 8), (part_num & 0xff));
4592         else
4593                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4594                          hw->mac.type, hw->phy.type,
4595                          (part_num >> 8), (part_num & 0xff));
4596
4597         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
4598                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
4599                          "this card is not sufficient for optimal "
4600                          "performance.\n");
4601                 dev_warn(&pdev->dev, "For optimal performance a x8 "
4602                          "PCI-Express slot is required.\n");
4603         }
4604
4605         /* save off EEPROM version number */
4606         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4607
4608         /* reset the hardware with the new settings */
4609         hw->mac.ops.start_hw(hw);
4610
4611         netif_carrier_off(netdev);
4612
4613         strcpy(netdev->name, "eth%d");
4614         err = register_netdev(netdev);
4615         if (err)
4616                 goto err_register;
4617
4618 #ifdef CONFIG_IXGBE_DCA
4619         if (dca_add_requester(&pdev->dev) == 0) {
4620                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4621                 /* always use CB2 mode, difference is masked
4622                  * in the CB driver */
4623                 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4624                 ixgbe_setup_dca(adapter);
4625         }
4626 #endif
4627
4628         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4629         cards_found++;
4630         return 0;
4631
4632 err_register:
4633         ixgbe_release_hw_control(adapter);
4634 err_hw_init:
4635 err_sw_init:
4636         ixgbe_reset_interrupt_capability(adapter);
4637 err_eeprom:
4638         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4639         del_timer_sync(&adapter->sfp_timer);
4640         cancel_work_sync(&adapter->sfp_task);
4641         cancel_work_sync(&adapter->multispeed_fiber_task);
4642         cancel_work_sync(&adapter->sfp_config_module_task);
4643         iounmap(hw->hw_addr);
4644 err_ioremap:
4645         free_netdev(netdev);
4646 err_alloc_etherdev:
4647         pci_release_regions(pdev);
4648 err_pci_reg:
4649 err_dma:
4650         pci_disable_device(pdev);
4651         return err;
4652 }
4653
4654 /**
4655  * ixgbe_remove - Device Removal Routine
4656  * @pdev: PCI device information struct
4657  *
4658  * ixgbe_remove is called by the PCI subsystem to alert the driver
4659  * that it should release a PCI device.  The could be caused by a
4660  * Hot-Plug event, or because the driver is going to be removed from
4661  * memory.
4662  **/
4663 static void __devexit ixgbe_remove(struct pci_dev *pdev)
4664 {
4665         struct net_device *netdev = pci_get_drvdata(pdev);
4666         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4667         int err;
4668
4669         set_bit(__IXGBE_DOWN, &adapter->state);
4670         /* clear the module not found bit to make sure the worker won't
4671          * reschedule
4672          */
4673         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4674         del_timer_sync(&adapter->watchdog_timer);
4675
4676         del_timer_sync(&adapter->sfp_timer);
4677         cancel_work_sync(&adapter->watchdog_task);
4678         cancel_work_sync(&adapter->sfp_task);
4679         cancel_work_sync(&adapter->multispeed_fiber_task);
4680         cancel_work_sync(&adapter->sfp_config_module_task);
4681         flush_scheduled_work();
4682
4683 #ifdef CONFIG_IXGBE_DCA
4684         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4685                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4686                 dca_remove_requester(&pdev->dev);
4687                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4688         }
4689
4690 #endif
4691         if (netdev->reg_state == NETREG_REGISTERED)
4692                 unregister_netdev(netdev);
4693
4694         ixgbe_reset_interrupt_capability(adapter);
4695
4696         ixgbe_release_hw_control(adapter);
4697
4698         iounmap(adapter->hw.hw_addr);
4699         pci_release_regions(pdev);
4700
4701         DPRINTK(PROBE, INFO, "complete\n");
4702         kfree(adapter->tx_ring);
4703         kfree(adapter->rx_ring);
4704
4705         free_netdev(netdev);
4706
4707         err = pci_disable_pcie_error_reporting(pdev);
4708         if (err)
4709                 dev_err(&pdev->dev,
4710                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
4711
4712         pci_disable_device(pdev);
4713 }
4714
4715 /**
4716  * ixgbe_io_error_detected - called when PCI error is detected
4717  * @pdev: Pointer to PCI device
4718  * @state: The current pci connection state
4719  *
4720  * This function is called after a PCI bus error affecting
4721  * this device has been detected.
4722  */
4723 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4724                                                 pci_channel_state_t state)
4725 {
4726         struct net_device *netdev = pci_get_drvdata(pdev);
4727         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4728
4729         netif_device_detach(netdev);
4730
4731         if (netif_running(netdev))
4732                 ixgbe_down(adapter);
4733         pci_disable_device(pdev);
4734
4735         /* Request a slot reset. */
4736         return PCI_ERS_RESULT_NEED_RESET;
4737 }
4738
4739 /**
4740  * ixgbe_io_slot_reset - called after the pci bus has been reset.
4741  * @pdev: Pointer to PCI device
4742  *
4743  * Restart the card from scratch, as if from a cold-boot.
4744  */
4745 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4746 {
4747         struct net_device *netdev = pci_get_drvdata(pdev);
4748         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4749         pci_ers_result_t result;
4750         int err;
4751
4752         if (pci_enable_device(pdev)) {
4753                 DPRINTK(PROBE, ERR,
4754                         "Cannot re-enable PCI device after reset.\n");
4755                 result = PCI_ERS_RESULT_DISCONNECT;
4756         } else {
4757                 pci_set_master(pdev);
4758                 pci_restore_state(pdev);
4759
4760                 pci_enable_wake(pdev, PCI_D3hot, 0);
4761                 pci_enable_wake(pdev, PCI_D3cold, 0);
4762
4763                 ixgbe_reset(adapter);
4764
4765                 result = PCI_ERS_RESULT_RECOVERED;
4766         }
4767
4768         err = pci_cleanup_aer_uncorrect_error_status(pdev);
4769         if (err) {
4770                 dev_err(&pdev->dev,
4771                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
4772                 /* non-fatal, continue */
4773         }
4774
4775         return result;
4776 }
4777
4778 /**
4779  * ixgbe_io_resume - called when traffic can start flowing again.
4780  * @pdev: Pointer to PCI device
4781  *
4782  * This callback is called when the error recovery driver tells us that
4783  * its OK to resume normal operation.
4784  */
4785 static void ixgbe_io_resume(struct pci_dev *pdev)
4786 {
4787         struct net_device *netdev = pci_get_drvdata(pdev);
4788         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4789
4790         if (netif_running(netdev)) {
4791                 if (ixgbe_up(adapter)) {
4792                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4793                         return;
4794                 }
4795         }
4796
4797         netif_device_attach(netdev);
4798 }
4799
4800 static struct pci_error_handlers ixgbe_err_handler = {
4801         .error_detected = ixgbe_io_error_detected,
4802         .slot_reset = ixgbe_io_slot_reset,
4803         .resume = ixgbe_io_resume,
4804 };
4805
4806 static struct pci_driver ixgbe_driver = {
4807         .name     = ixgbe_driver_name,
4808         .id_table = ixgbe_pci_tbl,
4809         .probe    = ixgbe_probe,
4810         .remove   = __devexit_p(ixgbe_remove),
4811 #ifdef CONFIG_PM
4812         .suspend  = ixgbe_suspend,
4813         .resume   = ixgbe_resume,
4814 #endif
4815         .shutdown = ixgbe_shutdown,
4816         .err_handler = &ixgbe_err_handler
4817 };
4818
4819 /**
4820  * ixgbe_init_module - Driver Registration Routine
4821  *
4822  * ixgbe_init_module is the first routine called when the driver is
4823  * loaded. All it does is register with the PCI subsystem.
4824  **/
4825 static int __init ixgbe_init_module(void)
4826 {
4827         int ret;
4828         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4829                ixgbe_driver_string, ixgbe_driver_version);
4830
4831         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4832
4833 #ifdef CONFIG_IXGBE_DCA
4834         dca_register_notify(&dca_notifier);
4835 #endif
4836
4837         ret = pci_register_driver(&ixgbe_driver);
4838         return ret;
4839 }
4840
4841 module_init(ixgbe_init_module);
4842
4843 /**
4844  * ixgbe_exit_module - Driver Exit Cleanup Routine
4845  *
4846  * ixgbe_exit_module is called just before the driver is removed
4847  * from memory.
4848  **/
4849 static void __exit ixgbe_exit_module(void)
4850 {
4851 #ifdef CONFIG_IXGBE_DCA
4852         dca_unregister_notify(&dca_notifier);
4853 #endif
4854         pci_unregister_driver(&ixgbe_driver);
4855 }
4856
4857 #ifdef CONFIG_IXGBE_DCA
4858 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4859                             void *p)
4860 {
4861         int ret_val;
4862
4863         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4864                                          __ixgbe_notify_dca);
4865
4866         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4867 }
4868 #endif /* CONFIG_IXGBE_DCA */
4869
4870 module_exit(ixgbe_exit_module);
4871
4872 /* ixgbe_main.c */