drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.62-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 135                  "per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172         if (adapter->vfinfo)
 173                 kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 printk(KERN_ERR "%-15s ", rname);
 293                 for (j = 0; j < 8; j++)
 294                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 295                 printk(KERN_CONT "\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 printk(KERN_INFO "Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 328                 netdev->name,
 329                 netdev->state,
 330                 netdev->trans_start,
 331                 netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         printk(KERN_INFO " Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 348                 "leng ntw timestamp\n");
 349         for (n = 0; n < adapter->num_tx_queues; n++) {
 350                 tx_ring = adapter->tx_ring[n];
 351                 tx_buffer_info =
 352                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 353                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 354                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 355                            (u64)tx_buffer_info->dma,
 356                            tx_buffer_info->length,
 357                            tx_buffer_info->next_to_watch,
 358                            (u64)tx_buffer_info->time_stamp);
 359         }
 360
 361         /* Print TX Rings */
 362         if (!netif_msg_tx_done(adapter))
 363                 goto rx_ring_summary;
 364
 365         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 366
 367         /* Transmit Descriptor Formats
 368          *
 369          * Advanced Transmit Descriptor
 370          *   +--------------------------------------------------------------+
 371          * 0 |         Buffer Address [63:0]                                |
 372          *   +--------------------------------------------------------------+
 373          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 374          *   +--------------------------------------------------------------+
 375          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 376          */
 377
 378         for (n = 0; n < adapter->num_tx_queues; n++) {
 379                 tx_ring = adapter->tx_ring[n];
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 382                 printk(KERN_INFO "------------------------------------\n");
 383                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 384                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 385                         "leng  ntw timestamp        bi->skb\n");
 386
 387                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 388                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 389                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 390                         u0 = (struct my_u0 *)tx_desc;
 391                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 392                                 " %04X  %3X %016llX %p", i,
 393                                 le64_to_cpu(u0->a),
 394                                 le64_to_cpu(u0->b),
 395                                 (u64)tx_buffer_info->dma,
 396                                 tx_buffer_info->length,
 397                                 tx_buffer_info->next_to_watch,
 398                                 (u64)tx_buffer_info->time_stamp,
 399                                 tx_buffer_info->skb);
 400                         if (i == tx_ring->next_to_use &&
 401                                 i == tx_ring->next_to_clean)
 402                                 printk(KERN_CONT " NTC/U\n");
 403                         else if (i == tx_ring->next_to_use)
 404                                 printk(KERN_CONT " NTU\n");
 405                         else if (i == tx_ring->next_to_clean)
 406                                 printk(KERN_CONT " NTC\n");
 407                         else
 408                                 printk(KERN_CONT "\n");
 409
 410                         if (netif_msg_pktdata(adapter) &&
 411                                 tx_buffer_info->dma != 0)
 412                                 print_hex_dump(KERN_INFO, "",
 413                                         DUMP_PREFIX_ADDRESS, 16, 1,
 414                                         phys_to_virt(tx_buffer_info->dma),
 415                                         tx_buffer_info->length, true);
 416                 }
 417         }
 418
 419         /* Print RX Rings Summary */
 420 rx_ring_summary:
 421         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 422         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 423         for (n = 0; n < adapter->num_rx_queues; n++) {
 424                 rx_ring = adapter->rx_ring[n];
 425                 printk(KERN_INFO "%5d %5X %5X\n", n,
 426                            rx_ring->next_to_use, rx_ring->next_to_clean);
 427         }
 428
 429         /* Print RX Rings */
 430         if (!netif_msg_rx_status(adapter))
 431                 goto exit;
 432
 433         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 434
 435         /* Advanced Receive Descriptor (Read) Format
 436          *    63                                           1        0
 437          *    +-----------------------------------------------------+
 438          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 439          *    +----------------------------------------------+------+
 440          *  8 |       Header Buffer Address [63:1]           |  DD  |
 441          *    +-----------------------------------------------------+
 442          *
 443          *
 444          * Advanced Receive Descriptor (Write-Back) Format
 445          *
 446          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 447          *   +------------------------------------------------------+
 448          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 449          *   | Checksum   Ident  |   |           |    | Type | Type |
 450          *   +------------------------------------------------------+
 451          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 452          *   +------------------------------------------------------+
 453          *   63       48 47    32 31            20 19               0
 454          */
 455         for (n = 0; n < adapter->num_rx_queues; n++) {
 456                 rx_ring = adapter->rx_ring[n];
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 459                 printk(KERN_INFO "------------------------------------\n");
 460                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 461                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 462                         "<-- Adv Rx Read format\n");
 463                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 464                         "[vl er S cks ln] ---------------- [bi->skb] "
 465                         "<-- Adv Rx Write-Back format\n");
 466
 467                 for (i = 0; i < rx_ring->count; i++) {
 468                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 469                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 470                         u0 = (struct my_u0 *)rx_desc;
 471                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 472                         if (staterr & IXGBE_RXD_STAT_DD) {
 473                                 /* Descriptor Done */
 474                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 475                                         "%016llX ---------------- %p", i,
 476                                         le64_to_cpu(u0->a),
 477                                         le64_to_cpu(u0->b),
 478                                         rx_buffer_info->skb);
 479                         } else {
 480                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 481                                         "%016llX %016llX %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         (u64)rx_buffer_info->dma,
 485                                         rx_buffer_info->skb);
 486
 487                                 if (netif_msg_pktdata(adapter)) {
 488                                         print_hex_dump(KERN_INFO, "",
 489                                            DUMP_PREFIX_ADDRESS, 16, 1,
 490                                            phys_to_virt(rx_buffer_info->dma),
 491                                            rx_ring->rx_buf_len, true);
 492
 493                                         if (rx_ring->rx_buf_len
 494                                                 < IXGBE_RXBUFFER_2048)
 495                                                 print_hex_dump(KERN_INFO, "",
 496                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 497                                                   phys_to_virt(
 498                                                     rx_buffer_info->page_dma +
 499                                                     rx_buffer_info->page_offset
 500                                                   ),
 501                                                   PAGE_SIZE/2, true);
 502                                 }
 503                         }
 504
 505                         if (i == rx_ring->next_to_use)
 506                                 printk(KERN_CONT " NTU\n");
 507                         else if (i == rx_ring->next_to_clean)
 508                                 printk(KERN_CONT " NTC\n");
 509                         else
 510                                 printk(KERN_CONT "\n");
 511
 512                 }
 513         }
 514
 515 exit:
 516         return;
 517 }
 518
 519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 520 {
 521         u32 ctrl_ext;
 522
 523         /* Let firmware take over control of h/w */
 524         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 526                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 527 }
 528
 529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 530 {
 531         u32 ctrl_ext;
 532
 533         /* Let firmware know the driver has taken over */
 534         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 536                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 537 }
 538
 539 /*
 540  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 541  * @adapter: pointer to adapter struct
 542  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 543  * @queue: queue to map the corresponding interrupt to
 544  * @msix_vector: the vector to map to the corresponding queue
 545  *
 546  */
 547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 548                            u8 queue, u8 msix_vector)
 549 {
 550         u32 ivar, index;
 551         struct ixgbe_hw *hw = &adapter->hw;
 552         switch (hw->mac.type) {
 553         case ixgbe_mac_82598EB:
 554                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 555                 if (direction == -1)
 556                         direction = 0;
 557                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 558                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 559                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 560                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 561                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 562                 break;
 563         case ixgbe_mac_82599EB:
 564                 if (direction == -1) {
 565                         /* other causes */
 566                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 567                         index = ((queue & 1) * 8);
 568                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 569                         ivar &= ~(0xFF << index);
 570                         ivar |= (msix_vector << index);
 571                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 572                         break;
 573                 } else {
 574                         /* tx or rx causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((16 * (queue & 1)) + (8 * direction));
 577                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 581                         break;
 582                 }
 583         default:
 584                 break;
 585         }
 586 }
 587
 588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 589                                           u64 qmask)
 590 {
 591         u32 mask;
 592
 593         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596         } else {
 597                 mask = (qmask & 0xFFFFFFFF);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 599                 mask = (qmask >> 32);
 600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 601         }
 602 }
 603
 604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 605                                              struct ixgbe_tx_buffer
 606                                              *tx_buffer_info)
 607 {
 608         if (tx_buffer_info->dma) {
 609                 if (tx_buffer_info->mapped_as_page)
 610                         dma_unmap_page(&adapter->pdev->dev,
 611                                        tx_buffer_info->dma,
 612                                        tx_buffer_info->length,
 613                                        DMA_TO_DEVICE);
 614                 else
 615                         dma_unmap_single(&adapter->pdev->dev,
 616                                          tx_buffer_info->dma,
 617                                          tx_buffer_info->length,
 618                                          DMA_TO_DEVICE);
 619                 tx_buffer_info->dma = 0;
 620         }
 621         if (tx_buffer_info->skb) {
 622                 dev_kfree_skb_any(tx_buffer_info->skb);
 623                 tx_buffer_info->skb = NULL;
 624         }
 625         tx_buffer_info->time_stamp = 0;
 626         /* tx_buffer_info must be completely set up in the transmit path */
 627 }
 628
 629 /**
 630  * ixgbe_tx_xon_state - check the tx ring xon state
 631  * @adapter: the ixgbe adapter
 632  * @tx_ring: the corresponding tx_ring
 633  *
 634  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 635  * corresponding TC of this tx_ring when checking TFCS.
 636  *
 637  * Returns : true if in xon state (currently not paused)
 638  */
 639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 640                                       struct ixgbe_ring *tx_ring)
 641 {
 642         u32 txoff = IXGBE_TFCS_TXOFF;
 643
 644 #ifdef CONFIG_IXGBE_DCB
 645         if (adapter->dcb_cfg.pfc_mode_enable) {
 646                 int tc;
 647                 int reg_idx = tx_ring->reg_idx;
 648                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 649
 650                 switch (adapter->hw.mac.type) {
 651                 case ixgbe_mac_82598EB:
 652                         tc = reg_idx >> 2;
 653                         txoff = IXGBE_TFCS_TXOFF0;
 654                         break;
 655                 case ixgbe_mac_82599EB:
 656                         tc = 0;
 657                         txoff = IXGBE_TFCS_TXOFF;
 658                         if (dcb_i == 8) {
 659                                 /* TC0, TC1 */
 660                                 tc = reg_idx >> 5;
 661                                 if (tc == 2) /* TC2, TC3 */
 662                                         tc += (reg_idx - 64) >> 4;
 663                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 664                                         tc += 1 + ((reg_idx - 96) >> 3);
 665                         } else if (dcb_i == 4) {
 666                                 /* TC0, TC1 */
 667                                 tc = reg_idx >> 6;
 668                                 if (tc == 1) {
 669                                         tc += (reg_idx - 64) >> 5;
 670                                         if (tc == 2) /* TC2, TC3 */
 671                                                 tc += (reg_idx - 96) >> 4;
 672                                 }
 673                         }
 674                         break;
 675                 default:
 676                         tc = 0;
 677                 }
 678                 txoff <<= tc;
 679         }
 680 #endif
 681         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 682 }
 683
 684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 685                                        struct ixgbe_ring *tx_ring,
 686                                        unsigned int eop)
 687 {
 688         struct ixgbe_hw *hw = &adapter->hw;
 689
 690         /* Detect a transmit hang in hardware, this serializes the
 691          * check with the clearing of time_stamp and movement of eop */
 692         adapter->detect_tx_hung = false;
 693         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 694             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 695             ixgbe_tx_xon_state(adapter, tx_ring)) {
 696                 /* detected Tx unit hang */
 697                 union ixgbe_adv_tx_desc *tx_desc;
 698                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 699                 e_err("Detected Tx Unit Hang\n"
 700                       "  Tx Queue             <%d>\n"
 701                       "  TDH, TDT             <%x>, <%x>\n"
 702                       "  next_to_use          <%x>\n"
 703                       "  next_to_clean        <%x>\n"
 704                       "tx_buffer_info[next_to_clean]\n"
 705                       "  time_stamp           <%lx>\n"
 706                       "  jiffies              <%lx>\n",
 707                       tx_ring->queue_index,
 708                       IXGBE_READ_REG(hw, tx_ring->head),
 709                       IXGBE_READ_REG(hw, tx_ring->tail),
 710                       tx_ring->next_to_use, eop,
 711                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 712                 return true;
 713         }
 714
 715         return false;
 716 }
 717
 718 #define IXGBE_MAX_TXD_PWR       14
 719 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 720
 721 /* Tx Descriptors needed, worst case */
 722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 723                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 725         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 726
 727 static void ixgbe_tx_timeout(struct net_device *netdev);
 728
 729 /**
 730  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 731  * @q_vector: structure containing interrupt and ring information
 732  * @tx_ring: tx ring to clean
 733  **/
 734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 735                                struct ixgbe_ring *tx_ring)
 736 {
 737         struct ixgbe_adapter *adapter = q_vector->adapter;
 738         struct net_device *netdev = adapter->netdev;
 739         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 740         struct ixgbe_tx_buffer *tx_buffer_info;
 741         unsigned int i, eop, count = 0;
 742         unsigned int total_bytes = 0, total_packets = 0;
 743
 744         i = tx_ring->next_to_clean;
 745         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 746         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 747
 748         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 749                (count < tx_ring->work_limit)) {
 750                 bool cleaned = false;
 751                 for ( ; !cleaned; count++) {
 752                         struct sk_buff *skb;
 753                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 754                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 755                         cleaned = (i == eop);
 756                         skb = tx_buffer_info->skb;
 757
 758                         if (cleaned && skb) {
 759                                 unsigned int segs, bytecount;
 760                                 unsigned int hlen = skb_headlen(skb);
 761
 762                                 /* gso_segs is currently only valid for tcp */
 763                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 764 #ifdef IXGBE_FCOE
 765                                 /* adjust for FCoE Sequence Offload */
 766                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 767                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 768                                     skb_is_gso(skb)) {
 769                                         hlen = skb_transport_offset(skb) +
 770                                                 sizeof(struct fc_frame_header) +
 771                                                 sizeof(struct fcoe_crc_eof);
 772                                         segs = DIV_ROUND_UP(skb->len - hlen,
 773                                                 skb_shinfo(skb)->gso_size);
 774                                 }
 775 #endif /* IXGBE_FCOE */
 776                                 /* multiply data chunks by size of headers */
 777                                 bytecount = ((segs - 1) * hlen) + skb->len;
 778                                 total_packets += segs;
 779                                 total_bytes += bytecount;
 780                         }
 781
 782                         ixgbe_unmap_and_free_tx_resource(adapter,
 783                                                          tx_buffer_info);
 784
 785                         tx_desc->wb.status = 0;
 786
 787                         i++;
 788                         if (i == tx_ring->count)
 789                                 i = 0;
 790                 }
 791
 792                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 793                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 794         }
 795
 796         tx_ring->next_to_clean = i;
 797
 798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 799         if (unlikely(count && netif_carrier_ok(netdev) &&
 800                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 801                 /* Make sure that anybody stopping the queue after this
 802                  * sees the new next_to_clean.
 803                  */
 804                 smp_mb();
 805                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 806                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 807                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 808                         ++tx_ring->restart_queue;
 809                 }
 810         }
 811
 812         if (adapter->detect_tx_hung) {
 813                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 814                         /* schedule immediate reset if we believe we hung */
 815                         e_info("tx hang %d detected, resetting adapter\n",
 816                                adapter->tx_timeout_count + 1);
 817                         ixgbe_tx_timeout(adapter->netdev);
 818                 }
 819         }
 820
 821         /* re-arm the interrupt */
 822         if (count >= tx_ring->work_limit)
 823                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 824
 825         tx_ring->total_bytes += total_bytes;
 826         tx_ring->total_packets += total_packets;
 827         tx_ring->stats.packets += total_packets;
 828         tx_ring->stats.bytes += total_bytes;
 829         return (count < tx_ring->work_limit);
 830 }
 831
 832 #ifdef CONFIG_IXGBE_DCA
 833 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 834                                 struct ixgbe_ring *rx_ring)
 835 {
 836         u32 rxctrl;
 837         int cpu = get_cpu();
 838         int q = rx_ring->reg_idx;
 839
 840         if (rx_ring->cpu != cpu) {
 841                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 842                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 843                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 844                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 845                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 846                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 847                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 848                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 849                 }
 850                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 851                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 852                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 853                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 854                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 855                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 856                 rx_ring->cpu = cpu;
 857         }
 858         put_cpu();
 859 }
 860
 861 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 862                                 struct ixgbe_ring *tx_ring)
 863 {
 864         u32 txctrl;
 865         int cpu = get_cpu();
 866         int q = tx_ring->reg_idx;
 867         struct ixgbe_hw *hw = &adapter->hw;
 868
 869         if (tx_ring->cpu != cpu) {
 870                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 871                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 872                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 873                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 874                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 875                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 876                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 877                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 878                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 879                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 880                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 881                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 882                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 883                 }
 884                 tx_ring->cpu = cpu;
 885         }
 886         put_cpu();
 887 }
 888
 889 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 890 {
 891         int i;
 892
 893         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 894                 return;
 895
 896         /* always use CB2 mode, difference is masked in the CB driver */
 897         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 898
 899         for (i = 0; i < adapter->num_tx_queues; i++) {
 900                 adapter->tx_ring[i]->cpu = -1;
 901                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 902         }
 903         for (i = 0; i < adapter->num_rx_queues; i++) {
 904                 adapter->rx_ring[i]->cpu = -1;
 905                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 906         }
 907 }
 908
 909 static int __ixgbe_notify_dca(struct device *dev, void *data)
 910 {
 911         struct net_device *netdev = dev_get_drvdata(dev);
 912         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 913         unsigned long event = *(unsigned long *)data;
 914
 915         switch (event) {
 916         case DCA_PROVIDER_ADD:
 917                 /* if we're already enabled, don't do it again */
 918                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 919                         break;
 920                 if (dca_add_requester(dev) == 0) {
 921                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 922                         ixgbe_setup_dca(adapter);
 923                         break;
 924                 }
 925                 /* Fall Through since DCA is disabled. */
 926         case DCA_PROVIDER_REMOVE:
 927                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 928                         dca_remove_requester(dev);
 929                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 930                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 931                 }
 932                 break;
 933         }
 934
 935         return 0;
 936 }
 937
 938 #endif /* CONFIG_IXGBE_DCA */
 939 /**
 940  * ixgbe_receive_skb - Send a completed packet up the stack
 941  * @adapter: board private structure
 942  * @skb: packet to send up
 943  * @status: hardware indication of status of receive
 944  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 945  * @rx_desc: rx descriptor
 946  **/
 947 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 948                               struct sk_buff *skb, u8 status,
 949                               struct ixgbe_ring *ring,
 950                               union ixgbe_adv_rx_desc *rx_desc)
 951 {
 952         struct ixgbe_adapter *adapter = q_vector->adapter;
 953         struct napi_struct *napi = &q_vector->napi;
 954         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 955         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 956
 957         skb_record_rx_queue(skb, ring->queue_index);
 958         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 959                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 960                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 961                 else
 962                         napi_gro_receive(napi, skb);
 963         } else {
 964                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 965                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 966                 else
 967                         netif_rx(skb);
 968         }
 969 }
 970
 971 /**
 972  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 973  * @adapter: address of board private structure
 974  * @status_err: hardware indication of status of receive
 975  * @skb: skb currently being received and modified
 976  **/
 977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 978                                      union ixgbe_adv_rx_desc *rx_desc,
 979                                      struct sk_buff *skb)
 980 {
 981         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 982
 983         skb->ip_summed = CHECKSUM_NONE;
 984
 985         /* Rx csum disabled */
 986         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 987                 return;
 988
 989         /* if IP and error */
 990         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 991             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 992                 adapter->hw_csum_rx_error++;
 993                 return;
 994         }
 995
 996         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 997                 return;
 998
 999         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002                 /*
1003                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1004                  * checksum errors.
1005                  */
1006                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008                         return;
1009
1010                 adapter->hw_csum_rx_error++;
1011                 return;
1012         }
1013
1014         /* It must be a TCP or UDP packet with a valid checksum */
1015         skb->ip_summed = CHECKSUM_UNNECESSARY;
1016 }
1017
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019                                          struct ixgbe_ring *rx_ring, u32 val)
1020 {
1021         /*
1022          * Force memory writes to complete before letting h/w
1023          * know there are new descriptors to fetch.  (Only
1024          * applicable for weak-ordered memory model archs,
1025          * such as IA-64).
1026          */
1027         wmb();
1028         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029 }
1030
1031 /**
1032  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033  * @adapter: address of board private structure
1034  **/
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036                                    struct ixgbe_ring *rx_ring,
1037                                    int cleaned_count)
1038 {
1039         struct pci_dev *pdev = adapter->pdev;
1040         union ixgbe_adv_rx_desc *rx_desc;
1041         struct ixgbe_rx_buffer *bi;
1042         unsigned int i;
1043
1044         i = rx_ring->next_to_use;
1045         bi = &rx_ring->rx_buffer_info[i];
1046
1047         while (cleaned_count--) {
1048                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1049
1050                 if (!bi->page_dma &&
1051                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1052                         if (!bi->page) {
1053                                 bi->page = alloc_page(GFP_ATOMIC);
1054                                 if (!bi->page) {
1055                                         adapter->alloc_rx_page_failed++;
1056                                         goto no_buffers;
1057                                 }
1058                                 bi->page_offset = 0;
1059                         } else {
1060                                 /* use a half page if we're re-using */
1061                                 bi->page_offset ^= (PAGE_SIZE / 2);
1062                         }
1063
1064                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1065                                                     bi->page_offset,
1066                                                     (PAGE_SIZE / 2),
1067                                                     DMA_FROM_DEVICE);
1068                 }
1069
1070                 if (!bi->skb) {
1071                         struct sk_buff *skb;
1072                         /* netdev_alloc_skb reserves 32 bytes up front!! */
1073                         uint bufsz = rx_ring->rx_buf_len + SMP_CACHE_BYTES;
1074                         skb = netdev_alloc_skb(adapter->netdev, bufsz);
1075
1076                         if (!skb) {
1077                                 adapter->alloc_rx_buff_failed++;
1078                                 goto no_buffers;
1079                         }
1080
1081                         /* advance the data pointer to the next cache line */
1082                         skb_reserve(skb, (PTR_ALIGN(skb->data, SMP_CACHE_BYTES)
1083                                           - skb->data));
1084
1085                         bi->skb = skb;
1086                         bi->dma = dma_map_single(&pdev->dev, skb->data,
1087                                                  rx_ring->rx_buf_len,
1088                                                  DMA_FROM_DEVICE);
1089                 }
1090                 /* Refresh the desc even if buffer_addrs didn't change because
1091                  * each write-back erases this info. */
1092                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1093                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1094                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1095                 } else {
1096                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1097                 }
1098
1099                 i++;
1100                 if (i == rx_ring->count)
1101                         i = 0;
1102                 bi = &rx_ring->rx_buffer_info[i];
1103         }
1104
1105 no_buffers:
1106         if (rx_ring->next_to_use != i) {
1107                 rx_ring->next_to_use = i;
1108                 if (i-- == 0)
1109                         i = (rx_ring->count - 1);
1110
1111                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1112         }
1113 }
1114
1115 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1116 {
1117         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1118 }
1119
1120 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1121 {
1122         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123 }
1124
1125 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1126 {
1127         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1128                 IXGBE_RXDADV_RSCCNT_MASK) >>
1129                 IXGBE_RXDADV_RSCCNT_SHIFT;
1130 }
1131
1132 /**
1133  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1134  * @skb: pointer to the last skb in the rsc queue
1135  * @count: pointer to number of packets coalesced in this context
1136  *
1137  * This function changes a queue full of hw rsc buffers into a completed
1138  * packet.  It uses the ->prev pointers to find the first packet and then
1139  * turns it into the frag list owner.
1140  **/
1141 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1142                                                         u64 *count)
1143 {
1144         unsigned int frag_list_size = 0;
1145
1146         while (skb->prev) {
1147                 struct sk_buff *prev = skb->prev;
1148                 frag_list_size += skb->len;
1149                 skb->prev = NULL;
1150                 skb = prev;
1151                 *count += 1;
1152         }
1153
1154         skb_shinfo(skb)->frag_list = skb->next;
1155         skb->next = NULL;
1156         skb->len += frag_list_size;
1157         skb->data_len += frag_list_size;
1158         skb->truesize += frag_list_size;
1159         return skb;
1160 }
1161
1162 struct ixgbe_rsc_cb {
1163         dma_addr_t dma;
1164         bool delay_unmap;
1165 };
1166
1167 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1168
1169 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1170                                struct ixgbe_ring *rx_ring,
1171                                int *work_done, int work_to_do)
1172 {
1173         struct ixgbe_adapter *adapter = q_vector->adapter;
1174         struct net_device *netdev = adapter->netdev;
1175         struct pci_dev *pdev = adapter->pdev;
1176         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1177         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1178         struct sk_buff *skb;
1179         unsigned int i, rsc_count = 0;
1180         u32 len, staterr;
1181         u16 hdr_info;
1182         bool cleaned = false;
1183         int cleaned_count = 0;
1184         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1185 #ifdef IXGBE_FCOE
1186         int ddp_bytes = 0;
1187 #endif /* IXGBE_FCOE */
1188
1189         i = rx_ring->next_to_clean;
1190         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1191         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1192         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1193
1194         while (staterr & IXGBE_RXD_STAT_DD) {
1195                 u32 upper_len = 0;
1196                 if (*work_done >= work_to_do)
1197                         break;
1198                 (*work_done)++;
1199
1200                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1201                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1202                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1203                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1204                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1205                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1206                         if ((len > IXGBE_RX_HDR_SIZE) ||
1207                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1208                                 len = IXGBE_RX_HDR_SIZE;
1209                 } else {
1210                         len = le16_to_cpu(rx_desc->wb.upper.length);
1211                 }
1212
1213                 cleaned = true;
1214                 skb = rx_buffer_info->skb;
1215                 prefetch(skb->data);
1216                 rx_buffer_info->skb = NULL;
1217
1218                 if (rx_buffer_info->dma) {
1219                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1220                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1221                                  (!(skb->prev))) {
1222                                 /*
1223                                  * When HWRSC is enabled, delay unmapping
1224                                  * of the first packet. It carries the
1225                                  * header information, HW may still
1226                                  * access the header after the writeback.
1227                                  * Only unmap it when EOP is reached
1228                                  */
1229                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1230                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1231                         } else {
1232                                 dma_unmap_single(&pdev->dev,
1233                                                  rx_buffer_info->dma,
1234                                                  rx_ring->rx_buf_len,
1235                                                  DMA_FROM_DEVICE);
1236                         }
1237                         rx_buffer_info->dma = 0;
1238                         skb_put(skb, len);
1239                 }
1240
1241                 if (upper_len) {
1242                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1243                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1244                         rx_buffer_info->page_dma = 0;
1245                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1246                                            rx_buffer_info->page,
1247                                            rx_buffer_info->page_offset,
1248                                            upper_len);
1249
1250                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1251                             (page_count(rx_buffer_info->page) != 1))
1252                                 rx_buffer_info->page = NULL;
1253                         else
1254                                 get_page(rx_buffer_info->page);
1255
1256                         skb->len += upper_len;
1257                         skb->data_len += upper_len;
1258                         skb->truesize += upper_len;
1259                 }
1260
1261                 i++;
1262                 if (i == rx_ring->count)
1263                         i = 0;
1264
1265                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1266                 prefetch(next_rxd);
1267                 cleaned_count++;
1268
1269                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1270                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1271
1272                 if (rsc_count) {
1273                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1274                                      IXGBE_RXDADV_NEXTP_SHIFT;
1275                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1276                 } else {
1277                         next_buffer = &rx_ring->rx_buffer_info[i];
1278                 }
1279
1280                 if (staterr & IXGBE_RXD_STAT_EOP) {
1281                         if (skb->prev)
1282                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1283                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1284                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1285                                         dma_unmap_single(&pdev->dev,
1286                                                          IXGBE_RSC_CB(skb)->dma,
1287                                                          rx_ring->rx_buf_len,
1288                                                          DMA_FROM_DEVICE);
1289                                         IXGBE_RSC_CB(skb)->dma = 0;
1290                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1291                                 }
1292                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1293                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1294                                 else
1295                                         rx_ring->rsc_count++;
1296                                 rx_ring->rsc_flush++;
1297                         }
1298                         rx_ring->stats.packets++;
1299                         rx_ring->stats.bytes += skb->len;
1300                 } else {
1301                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1302                                 rx_buffer_info->skb = next_buffer->skb;
1303                                 rx_buffer_info->dma = next_buffer->dma;
1304                                 next_buffer->skb = skb;
1305                                 next_buffer->dma = 0;
1306                         } else {
1307                                 skb->next = next_buffer->skb;
1308                                 skb->next->prev = skb;
1309                         }
1310                         rx_ring->non_eop_descs++;
1311                         goto next_desc;
1312                 }
1313
1314                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1315                         dev_kfree_skb_irq(skb);
1316                         goto next_desc;
1317                 }
1318
1319                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1320
1321                 /* probably a little skewed due to removing CRC */
1322                 total_rx_bytes += skb->len;
1323                 total_rx_packets++;
1324
1325                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1326 #ifdef IXGBE_FCOE
1327                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1328                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1329                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1330                         if (!ddp_bytes)
1331                                 goto next_desc;
1332                 }
1333 #endif /* IXGBE_FCOE */
1334                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1335
1336 next_desc:
1337                 rx_desc->wb.upper.status_error = 0;
1338
1339                 /* return some buffers to hardware, one at a time is too slow */
1340                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1341                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1342                         cleaned_count = 0;
1343                 }
1344
1345                 /* use prefetched values */
1346                 rx_desc = next_rxd;
1347                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1348
1349                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1350         }
1351
1352         rx_ring->next_to_clean = i;
1353         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1354
1355         if (cleaned_count)
1356                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1357
1358 #ifdef IXGBE_FCOE
1359         /* include DDPed FCoE data */
1360         if (ddp_bytes > 0) {
1361                 unsigned int mss;
1362
1363                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1364                         sizeof(struct fc_frame_header) -
1365                         sizeof(struct fcoe_crc_eof);
1366                 if (mss > 512)
1367                         mss &= ~511;
1368                 total_rx_bytes += ddp_bytes;
1369                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1370         }
1371 #endif /* IXGBE_FCOE */
1372
1373         rx_ring->total_packets += total_rx_packets;
1374         rx_ring->total_bytes += total_rx_bytes;
1375         netdev->stats.rx_bytes += total_rx_bytes;
1376         netdev->stats.rx_packets += total_rx_packets;
1377
1378         return cleaned;
1379 }
1380
1381 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1382 /**
1383  * ixgbe_configure_msix - Configure MSI-X hardware
1384  * @adapter: board private structure
1385  *
1386  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1387  * interrupts.
1388  **/
1389 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1390 {
1391         struct ixgbe_q_vector *q_vector;
1392         int i, j, q_vectors, v_idx, r_idx;
1393         u32 mask;
1394
1395         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1396
1397         /*
1398          * Populate the IVAR table and set the ITR values to the
1399          * corresponding register.
1400          */
1401         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1402                 q_vector = adapter->q_vector[v_idx];
1403                 /* XXX for_each_set_bit(...) */
1404                 r_idx = find_first_bit(q_vector->rxr_idx,
1405                                        adapter->num_rx_queues);
1406
1407                 for (i = 0; i < q_vector->rxr_count; i++) {
1408                         j = adapter->rx_ring[r_idx]->reg_idx;
1409                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1410                         r_idx = find_next_bit(q_vector->rxr_idx,
1411                                               adapter->num_rx_queues,
1412                                               r_idx + 1);
1413                 }
1414                 r_idx = find_first_bit(q_vector->txr_idx,
1415                                        adapter->num_tx_queues);
1416
1417                 for (i = 0; i < q_vector->txr_count; i++) {
1418                         j = adapter->tx_ring[r_idx]->reg_idx;
1419                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1420                         r_idx = find_next_bit(q_vector->txr_idx,
1421                                               adapter->num_tx_queues,
1422                                               r_idx + 1);
1423                 }
1424
1425                 if (q_vector->txr_count && !q_vector->rxr_count)
1426                         /* tx only */
1427                         q_vector->eitr = adapter->tx_eitr_param;
1428                 else if (q_vector->rxr_count)
1429                         /* rx or mixed */
1430                         q_vector->eitr = adapter->rx_eitr_param;
1431
1432                 ixgbe_write_eitr(q_vector);
1433         }
1434
1435         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1436                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1437                                v_idx);
1438         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1439                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1440         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1441
1442         /* set up to autoclear timer, and the vectors */
1443         mask = IXGBE_EIMS_ENABLE_MASK;
1444         if (adapter->num_vfs)
1445                 mask &= ~(IXGBE_EIMS_OTHER |
1446                           IXGBE_EIMS_MAILBOX |
1447                           IXGBE_EIMS_LSC);
1448         else
1449                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1450         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1451 }
1452
1453 enum latency_range {
1454         lowest_latency = 0,
1455         low_latency = 1,
1456         bulk_latency = 2,
1457         latency_invalid = 255
1458 };
1459
1460 /**
1461  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1462  * @adapter: pointer to adapter
1463  * @eitr: eitr setting (ints per sec) to give last timeslice
1464  * @itr_setting: current throttle rate in ints/second
1465  * @packets: the number of packets during this measurement interval
1466  * @bytes: the number of bytes during this measurement interval
1467  *
1468  *      Stores a new ITR value based on packets and byte
1469  *      counts during the last interrupt.  The advantage of per interrupt
1470  *      computation is faster updates and more accurate ITR for the current
1471  *      traffic pattern.  Constants in this function were computed
1472  *      based on theoretical maximum wire speed and thresholds were set based
1473  *      on testing data as well as attempting to minimize response time
1474  *      while increasing bulk throughput.
1475  *      this functionality is controlled by the InterruptThrottleRate module
1476  *      parameter (see ixgbe_param.c)
1477  **/
1478 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1479                            u32 eitr, u8 itr_setting,
1480                            int packets, int bytes)
1481 {
1482         unsigned int retval = itr_setting;
1483         u32 timepassed_us;
1484         u64 bytes_perint;
1485
1486         if (packets == 0)
1487                 goto update_itr_done;
1488
1489
1490         /* simple throttlerate management
1491          *    0-20MB/s lowest (100000 ints/s)
1492          *   20-100MB/s low   (20000 ints/s)
1493          *  100-1249MB/s bulk (8000 ints/s)
1494          */
1495         /* what was last interrupt timeslice? */
1496         timepassed_us = 1000000/eitr;
1497         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1498
1499         switch (itr_setting) {
1500         case lowest_latency:
1501                 if (bytes_perint > adapter->eitr_low)
1502                         retval = low_latency;
1503                 break;
1504         case low_latency:
1505                 if (bytes_perint > adapter->eitr_high)
1506                         retval = bulk_latency;
1507                 else if (bytes_perint <= adapter->eitr_low)
1508                         retval = lowest_latency;
1509                 break;
1510         case bulk_latency:
1511                 if (bytes_perint <= adapter->eitr_high)
1512                         retval = low_latency;
1513                 break;
1514         }
1515
1516 update_itr_done:
1517         return retval;
1518 }
1519
1520 /**
1521  * ixgbe_write_eitr - write EITR register in hardware specific way
1522  * @q_vector: structure containing interrupt and ring information
1523  *
1524  * This function is made to be called by ethtool and by the driver
1525  * when it needs to update EITR registers at runtime.  Hardware
1526  * specific quirks/differences are taken care of here.
1527  */
1528 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1529 {
1530         struct ixgbe_adapter *adapter = q_vector->adapter;
1531         struct ixgbe_hw *hw = &adapter->hw;
1532         int v_idx = q_vector->v_idx;
1533         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1534
1535         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1536                 /* must write high and low 16 bits to reset counter */
1537                 itr_reg |= (itr_reg << 16);
1538         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1539                 /*
1540                  * 82599 can support a value of zero, so allow it for
1541                  * max interrupt rate, but there is an errata where it can
1542                  * not be zero with RSC
1543                  */
1544                 if (itr_reg == 8 &&
1545                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1546                         itr_reg = 0;
1547
1548                 /*
1549                  * set the WDIS bit to not clear the timer bits and cause an
1550                  * immediate assertion of the interrupt
1551                  */
1552                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1553         }
1554         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1555 }
1556
1557 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1558 {
1559         struct ixgbe_adapter *adapter = q_vector->adapter;
1560         u32 new_itr;
1561         u8 current_itr, ret_itr;
1562         int i, r_idx;
1563         struct ixgbe_ring *rx_ring, *tx_ring;
1564
1565         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1566         for (i = 0; i < q_vector->txr_count; i++) {
1567                 tx_ring = adapter->tx_ring[r_idx];
1568                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1569                                            q_vector->tx_itr,
1570                                            tx_ring->total_packets,
1571                                            tx_ring->total_bytes);
1572                 /* if the result for this queue would decrease interrupt
1573                  * rate for this vector then use that result */
1574                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1575                                     q_vector->tx_itr - 1 : ret_itr);
1576                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1577                                       r_idx + 1);
1578         }
1579
1580         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1581         for (i = 0; i < q_vector->rxr_count; i++) {
1582                 rx_ring = adapter->rx_ring[r_idx];
1583                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1584                                            q_vector->rx_itr,
1585                                            rx_ring->total_packets,
1586                                            rx_ring->total_bytes);
1587                 /* if the result for this queue would decrease interrupt
1588                  * rate for this vector then use that result */
1589                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1590                                     q_vector->rx_itr - 1 : ret_itr);
1591                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1592                                       r_idx + 1);
1593         }
1594
1595         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1596
1597         switch (current_itr) {
1598         /* counts and packets in update_itr are dependent on these numbers */
1599         case lowest_latency:
1600                 new_itr = 100000;
1601                 break;
1602         case low_latency:
1603                 new_itr = 20000; /* aka hwitr = ~200 */
1604                 break;
1605         case bulk_latency:
1606         default:
1607                 new_itr = 8000;
1608                 break;
1609         }
1610
1611         if (new_itr != q_vector->eitr) {
1612                 /* do an exponential smoothing */
1613                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1614
1615                 /* save the algorithm value here, not the smoothed one */
1616                 q_vector->eitr = new_itr;
1617
1618                 ixgbe_write_eitr(q_vector);
1619         }
1620 }
1621
1622 /**
1623  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1624  * @work: pointer to work_struct containing our data
1625  **/
1626 static void ixgbe_check_overtemp_task(struct work_struct *work)
1627 {
1628         struct ixgbe_adapter *adapter = container_of(work,
1629                                                      struct ixgbe_adapter,
1630                                                      check_overtemp_task);
1631         struct ixgbe_hw *hw = &adapter->hw;
1632         u32 eicr = adapter->interrupt_event;
1633
1634         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1635                 switch (hw->device_id) {
1636                 case IXGBE_DEV_ID_82599_T3_LOM: {
1637                         u32 autoneg;
1638                         bool link_up = false;
1639
1640                         if (hw->mac.ops.check_link)
1641                                 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1642
1643                         if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1644                             (eicr & IXGBE_EICR_LSC))
1645                                 /* Check if this is due to overtemp */
1646                                 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1647                                         break;
1648                         }
1649                         return;
1650                 default:
1651                         if (!(eicr & IXGBE_EICR_GPI_SDP0))
1652                                 return;
1653                         break;
1654                 }
1655                 e_crit("Network adapter has been stopped because it "
1656                        "has over heated. Restart the computer. If the problem "
1657                        "persists, power off the system and replace the "
1658                        "adapter\n");
1659                 /* write to clear the interrupt */
1660                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1661         }
1662 }
1663
1664 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1665 {
1666         struct ixgbe_hw *hw = &adapter->hw;
1667
1668         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1669             (eicr & IXGBE_EICR_GPI_SDP1)) {
1670                 e_crit("Fan has stopped, replace the adapter\n");
1671                 /* write to clear the interrupt */
1672                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1673         }
1674 }
1675
1676 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1677 {
1678         struct ixgbe_hw *hw = &adapter->hw;
1679
1680         if (eicr & IXGBE_EICR_GPI_SDP1) {
1681                 /* Clear the interrupt */
1682                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1683                 schedule_work(&adapter->multispeed_fiber_task);
1684         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1685                 /* Clear the interrupt */
1686                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1687                 schedule_work(&adapter->sfp_config_module_task);
1688         } else {
1689                 /* Interrupt isn't for us... */
1690                 return;
1691         }
1692 }
1693
1694 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1695 {
1696         struct ixgbe_hw *hw = &adapter->hw;
1697
1698         adapter->lsc_int++;
1699         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1700         adapter->link_check_timeout = jiffies;
1701         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1702                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1703                 IXGBE_WRITE_FLUSH(hw);
1704                 schedule_work(&adapter->watchdog_task);
1705         }
1706 }
1707
1708 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1709 {
1710         struct net_device *netdev = data;
1711         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1712         struct ixgbe_hw *hw = &adapter->hw;
1713         u32 eicr;
1714
1715         /*
1716          * Workaround for Silicon errata.  Use clear-by-write instead
1717          * of clear-by-read.  Reading with EICS will return the
1718          * interrupt causes without clearing, which later be done
1719          * with the write to EICR.
1720          */
1721         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1722         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1723
1724         if (eicr & IXGBE_EICR_LSC)
1725                 ixgbe_check_lsc(adapter);
1726
1727         if (eicr & IXGBE_EICR_MAILBOX)
1728                 ixgbe_msg_task(adapter);
1729
1730         if (hw->mac.type == ixgbe_mac_82598EB)
1731                 ixgbe_check_fan_failure(adapter, eicr);
1732
1733         if (hw->mac.type == ixgbe_mac_82599EB) {
1734                 ixgbe_check_sfp_event(adapter, eicr);
1735                 adapter->interrupt_event = eicr;
1736                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1737                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1738                         schedule_work(&adapter->check_overtemp_task);
1739
1740                 /* Handle Flow Director Full threshold interrupt */
1741                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1742                         int i;
1743                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1744                         /* Disable transmits before FDIR Re-initialization */
1745                         netif_tx_stop_all_queues(netdev);
1746                         for (i = 0; i < adapter->num_tx_queues; i++) {
1747                                 struct ixgbe_ring *tx_ring =
1748                                                             adapter->tx_ring[i];
1749                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1750                                                        &tx_ring->reinit_state))
1751                                         schedule_work(&adapter->fdir_reinit_task);
1752                         }
1753                 }
1754         }
1755         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1756                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1757
1758         return IRQ_HANDLED;
1759 }
1760
1761 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1762                                            u64 qmask)
1763 {
1764         u32 mask;
1765
1766         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1767                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1768                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1769         } else {
1770                 mask = (qmask & 0xFFFFFFFF);
1771                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1772                 mask = (qmask >> 32);
1773                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1774         }
1775         /* skip the flush */
1776 }
1777
1778 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1779                                             u64 qmask)
1780 {
1781         u32 mask;
1782
1783         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1784                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1785                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1786         } else {
1787                 mask = (qmask & 0xFFFFFFFF);
1788                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1789                 mask = (qmask >> 32);
1790                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1791         }
1792         /* skip the flush */
1793 }
1794
1795 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1796 {
1797         struct ixgbe_q_vector *q_vector = data;
1798         struct ixgbe_adapter  *adapter = q_vector->adapter;
1799         struct ixgbe_ring     *tx_ring;
1800         int i, r_idx;
1801
1802         if (!q_vector->txr_count)
1803                 return IRQ_HANDLED;
1804
1805         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1806         for (i = 0; i < q_vector->txr_count; i++) {
1807                 tx_ring = adapter->tx_ring[r_idx];
1808                 tx_ring->total_bytes = 0;
1809                 tx_ring->total_packets = 0;
1810                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1811                                       r_idx + 1);
1812         }
1813
1814         /* EIAM disabled interrupts (on this vector) for us */
1815         napi_schedule(&q_vector->napi);
1816
1817         return IRQ_HANDLED;
1818 }
1819
1820 /**
1821  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1822  * @irq: unused
1823  * @data: pointer to our q_vector struct for this interrupt vector
1824  **/
1825 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1826 {
1827         struct ixgbe_q_vector *q_vector = data;
1828         struct ixgbe_adapter  *adapter = q_vector->adapter;
1829         struct ixgbe_ring  *rx_ring;
1830         int r_idx;
1831         int i;
1832
1833         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1834         for (i = 0;  i < q_vector->rxr_count; i++) {
1835                 rx_ring = adapter->rx_ring[r_idx];
1836                 rx_ring->total_bytes = 0;
1837                 rx_ring->total_packets = 0;
1838                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1839                                       r_idx + 1);
1840         }
1841
1842         if (!q_vector->rxr_count)
1843                 return IRQ_HANDLED;
1844
1845         /* disable interrupts on this vector only */
1846         /* EIAM disabled interrupts (on this vector) for us */
1847         napi_schedule(&q_vector->napi);
1848
1849         return IRQ_HANDLED;
1850 }
1851
1852 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1853 {
1854         struct ixgbe_q_vector *q_vector = data;
1855         struct ixgbe_adapter  *adapter = q_vector->adapter;
1856         struct ixgbe_ring  *ring;
1857         int r_idx;
1858         int i;
1859
1860         if (!q_vector->txr_count && !q_vector->rxr_count)
1861                 return IRQ_HANDLED;
1862
1863         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1864         for (i = 0; i < q_vector->txr_count; i++) {
1865                 ring = adapter->tx_ring[r_idx];
1866                 ring->total_bytes = 0;
1867                 ring->total_packets = 0;
1868                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1869                                       r_idx + 1);
1870         }
1871
1872         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1873         for (i = 0; i < q_vector->rxr_count; i++) {
1874                 ring = adapter->rx_ring[r_idx];
1875                 ring->total_bytes = 0;
1876                 ring->total_packets = 0;
1877                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1878                                       r_idx + 1);
1879         }
1880
1881         /* EIAM disabled interrupts (on this vector) for us */
1882         napi_schedule(&q_vector->napi);
1883
1884         return IRQ_HANDLED;
1885 }
1886
1887 /**
1888  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1889  * @napi: napi struct with our devices info in it
1890  * @budget: amount of work driver is allowed to do this pass, in packets
1891  *
1892  * This function is optimized for cleaning one queue only on a single
1893  * q_vector!!!
1894  **/
1895 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1896 {
1897         struct ixgbe_q_vector *q_vector =
1898                                container_of(napi, struct ixgbe_q_vector, napi);
1899         struct ixgbe_adapter *adapter = q_vector->adapter;
1900         struct ixgbe_ring *rx_ring = NULL;
1901         int work_done = 0;
1902         long r_idx;
1903
1904         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1905         rx_ring = adapter->rx_ring[r_idx];
1906 #ifdef CONFIG_IXGBE_DCA
1907         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1908                 ixgbe_update_rx_dca(adapter, rx_ring);
1909 #endif
1910
1911         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1912
1913         /* If all Rx work done, exit the polling mode */
1914         if (work_done < budget) {
1915                 napi_complete(napi);
1916                 if (adapter->rx_itr_setting & 1)
1917                         ixgbe_set_itr_msix(q_vector);
1918                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1919                         ixgbe_irq_enable_queues(adapter,
1920                                                 ((u64)1 << q_vector->v_idx));
1921         }
1922
1923         return work_done;
1924 }
1925
1926 /**
1927  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1928  * @napi: napi struct with our devices info in it
1929  * @budget: amount of work driver is allowed to do this pass, in packets
1930  *
1931  * This function will clean more than one rx queue associated with a
1932  * q_vector.
1933  **/
1934 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1935 {
1936         struct ixgbe_q_vector *q_vector =
1937                                container_of(napi, struct ixgbe_q_vector, napi);
1938         struct ixgbe_adapter *adapter = q_vector->adapter;
1939         struct ixgbe_ring *ring = NULL;
1940         int work_done = 0, i;
1941         long r_idx;
1942         bool tx_clean_complete = true;
1943
1944         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1945         for (i = 0; i < q_vector->txr_count; i++) {
1946                 ring = adapter->tx_ring[r_idx];
1947 #ifdef CONFIG_IXGBE_DCA
1948                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1949                         ixgbe_update_tx_dca(adapter, ring);
1950 #endif
1951                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1952                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1953                                       r_idx + 1);
1954         }
1955
1956         /* attempt to distribute budget to each queue fairly, but don't allow
1957          * the budget to go below 1 because we'll exit polling */
1958         budget /= (q_vector->rxr_count ?: 1);
1959         budget = max(budget, 1);
1960         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1961         for (i = 0; i < q_vector->rxr_count; i++) {
1962                 ring = adapter->rx_ring[r_idx];
1963 #ifdef CONFIG_IXGBE_DCA
1964                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1965                         ixgbe_update_rx_dca(adapter, ring);
1966 #endif
1967                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1968                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1969                                       r_idx + 1);
1970         }
1971
1972         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1973         ring = adapter->rx_ring[r_idx];
1974         /* If all Rx work done, exit the polling mode */
1975         if (work_done < budget) {
1976                 napi_complete(napi);
1977                 if (adapter->rx_itr_setting & 1)
1978                         ixgbe_set_itr_msix(q_vector);
1979                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1980                         ixgbe_irq_enable_queues(adapter,
1981                                                 ((u64)1 << q_vector->v_idx));
1982                 return 0;
1983         }
1984
1985         return work_done;
1986 }
1987
1988 /**
1989  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1990  * @napi: napi struct with our devices info in it
1991  * @budget: amount of work driver is allowed to do this pass, in packets
1992  *
1993  * This function is optimized for cleaning one queue only on a single
1994  * q_vector!!!
1995  **/
1996 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1997 {
1998         struct ixgbe_q_vector *q_vector =
1999                                container_of(napi, struct ixgbe_q_vector, napi);
2000         struct ixgbe_adapter *adapter = q_vector->adapter;
2001         struct ixgbe_ring *tx_ring = NULL;
2002         int work_done = 0;
2003         long r_idx;
2004
2005         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2006         tx_ring = adapter->tx_ring[r_idx];
2007 #ifdef CONFIG_IXGBE_DCA
2008         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2009                 ixgbe_update_tx_dca(adapter, tx_ring);
2010 #endif
2011
2012         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2013                 work_done = budget;
2014
2015         /* If all Tx work done, exit the polling mode */
2016         if (work_done < budget) {
2017                 napi_complete(napi);
2018                 if (adapter->tx_itr_setting & 1)
2019                         ixgbe_set_itr_msix(q_vector);
2020                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2021                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2022         }
2023
2024         return work_done;
2025 }
2026
2027 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2028                                      int r_idx)
2029 {
2030         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2031
2032         set_bit(r_idx, q_vector->rxr_idx);
2033         q_vector->rxr_count++;
2034 }
2035
2036 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2037                                      int t_idx)
2038 {
2039         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2040
2041         set_bit(t_idx, q_vector->txr_idx);
2042         q_vector->txr_count++;
2043 }
2044
2045 /**
2046  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2047  * @adapter: board private structure to initialize
2048  * @vectors: allotted vector count for descriptor rings
2049  *
2050  * This function maps descriptor rings to the queue-specific vectors
2051  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2052  * one vector per ring/queue, but on a constrained vector budget, we
2053  * group the rings as "efficiently" as possible.  You would add new
2054  * mapping configurations in here.
2055  **/
2056 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2057                                       int vectors)
2058 {
2059         int v_start = 0;
2060         int rxr_idx = 0, txr_idx = 0;
2061         int rxr_remaining = adapter->num_rx_queues;
2062         int txr_remaining = adapter->num_tx_queues;
2063         int i, j;
2064         int rqpv, tqpv;
2065         int err = 0;
2066
2067         /* No mapping required if MSI-X is disabled. */
2068         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2069                 goto out;
2070
2071         /*
2072          * The ideal configuration...
2073          * We have enough vectors to map one per queue.
2074          */
2075         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2076                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2077                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2078
2079                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2080                         map_vector_to_txq(adapter, v_start, txr_idx);
2081
2082                 goto out;
2083         }
2084
2085         /*
2086          * If we don't have enough vectors for a 1-to-1
2087          * mapping, we'll have to group them so there are
2088          * multiple queues per vector.
2089          */
2090         /* Re-adjusting *qpv takes care of the remainder. */
2091         for (i = v_start; i < vectors; i++) {
2092                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2093                 for (j = 0; j < rqpv; j++) {
2094                         map_vector_to_rxq(adapter, i, rxr_idx);
2095                         rxr_idx++;
2096                         rxr_remaining--;
2097                 }
2098         }
2099         for (i = v_start; i < vectors; i++) {
2100                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2101                 for (j = 0; j < tqpv; j++) {
2102                         map_vector_to_txq(adapter, i, txr_idx);
2103                         txr_idx++;
2104                         txr_remaining--;
2105                 }
2106         }
2107
2108 out:
2109         return err;
2110 }
2111
2112 /**
2113  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2114  * @adapter: board private structure
2115  *
2116  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2117  * interrupts from the kernel.
2118  **/
2119 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2120 {
2121         struct net_device *netdev = adapter->netdev;
2122         irqreturn_t (*handler)(int, void *);
2123         int i, vector, q_vectors, err;
2124         int ri=0, ti=0;
2125
2126         /* Decrement for Other and TCP Timer vectors */
2127         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2128
2129         /* Map the Tx/Rx rings to the vectors we were allotted. */
2130         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2131         if (err)
2132                 goto out;
2133
2134 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2135                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2136                          &ixgbe_msix_clean_many)
2137         for (vector = 0; vector < q_vectors; vector++) {
2138                 handler = SET_HANDLER(adapter->q_vector[vector]);
2139
2140                 if(handler == &ixgbe_msix_clean_rx) {
2141                         sprintf(adapter->name[vector], "%s-%s-%d",
2142                                 netdev->name, "rx", ri++);
2143                 }
2144                 else if(handler == &ixgbe_msix_clean_tx) {
2145                         sprintf(adapter->name[vector], "%s-%s-%d",
2146                                 netdev->name, "tx", ti++);
2147                 }
2148                 else
2149                         sprintf(adapter->name[vector], "%s-%s-%d",
2150                                 netdev->name, "TxRx", vector);
2151
2152                 err = request_irq(adapter->msix_entries[vector].vector,
2153                                   handler, 0, adapter->name[vector],
2154                                   adapter->q_vector[vector]);
2155                 if (err) {
2156                         e_err("request_irq failed for MSIX interrupt: "
2157                               "Error: %d\n", err);
2158                         goto free_queue_irqs;
2159                 }
2160         }
2161
2162         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2163         err = request_irq(adapter->msix_entries[vector].vector,
2164                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2165         if (err) {
2166                 e_err("request_irq for msix_lsc failed: %d\n", err);
2167                 goto free_queue_irqs;
2168         }
2169
2170         return 0;
2171
2172 free_queue_irqs:
2173         for (i = vector - 1; i >= 0; i--)
2174                 free_irq(adapter->msix_entries[--vector].vector,
2175                          adapter->q_vector[i]);
2176         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2177         pci_disable_msix(adapter->pdev);
2178         kfree(adapter->msix_entries);
2179         adapter->msix_entries = NULL;
2180 out:
2181         return err;
2182 }
2183
2184 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2185 {
2186         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2187         u8 current_itr;
2188         u32 new_itr = q_vector->eitr;
2189         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2190         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2191
2192         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2193                                             q_vector->tx_itr,
2194                                             tx_ring->total_packets,
2195                                             tx_ring->total_bytes);
2196         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2197                                             q_vector->rx_itr,
2198                                             rx_ring->total_packets,
2199                                             rx_ring->total_bytes);
2200
2201         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2202
2203         switch (current_itr) {
2204         /* counts and packets in update_itr are dependent on these numbers */
2205         case lowest_latency:
2206                 new_itr = 100000;
2207                 break;
2208         case low_latency:
2209                 new_itr = 20000; /* aka hwitr = ~200 */
2210                 break;
2211         case bulk_latency:
2212                 new_itr = 8000;
2213                 break;
2214         default:
2215                 break;
2216         }
2217
2218         if (new_itr != q_vector->eitr) {
2219                 /* do an exponential smoothing */
2220                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2221
2222                 /* save the algorithm value here, not the smoothed one */
2223                 q_vector->eitr = new_itr;
2224
2225                 ixgbe_write_eitr(q_vector);
2226         }
2227 }
2228
2229 /**
2230  * ixgbe_irq_enable - Enable default interrupt generation settings
2231  * @adapter: board private structure
2232  **/
2233 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2234 {
2235         u32 mask;
2236
2237         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2238         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2239                 mask |= IXGBE_EIMS_GPI_SDP0;
2240         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2241                 mask |= IXGBE_EIMS_GPI_SDP1;
2242         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2243                 mask |= IXGBE_EIMS_ECC;
2244                 mask |= IXGBE_EIMS_GPI_SDP1;
2245                 mask |= IXGBE_EIMS_GPI_SDP2;
2246                 if (adapter->num_vfs)
2247                         mask |= IXGBE_EIMS_MAILBOX;
2248         }
2249         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2250             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2251                 mask |= IXGBE_EIMS_FLOW_DIR;
2252
2253         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2254         ixgbe_irq_enable_queues(adapter, ~0);
2255         IXGBE_WRITE_FLUSH(&adapter->hw);
2256
2257         if (adapter->num_vfs > 32) {
2258                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2259                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2260         }
2261 }
2262
2263 /**
2264  * ixgbe_intr - legacy mode Interrupt Handler
2265  * @irq: interrupt number
2266  * @data: pointer to a network interface device structure
2267  **/
2268 static irqreturn_t ixgbe_intr(int irq, void *data)
2269 {
2270         struct net_device *netdev = data;
2271         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2272         struct ixgbe_hw *hw = &adapter->hw;
2273         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2274         u32 eicr;
2275
2276         /*
2277          * Workaround for silicon errata.  Mask the interrupts
2278          * before the read of EICR.
2279          */
2280         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2281
2282         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2283          * therefore no explict interrupt disable is necessary */
2284         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2285         if (!eicr) {
2286                 /* shared interrupt alert!
2287                  * make sure interrupts are enabled because the read will
2288                  * have disabled interrupts due to EIAM */
2289                 ixgbe_irq_enable(adapter);
2290                 return IRQ_NONE;        /* Not our interrupt */
2291         }
2292
2293         if (eicr & IXGBE_EICR_LSC)
2294                 ixgbe_check_lsc(adapter);
2295
2296         if (hw->mac.type == ixgbe_mac_82599EB)
2297                 ixgbe_check_sfp_event(adapter, eicr);
2298
2299         ixgbe_check_fan_failure(adapter, eicr);
2300         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2301             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2302                 schedule_work(&adapter->check_overtemp_task);
2303
2304         if (napi_schedule_prep(&(q_vector->napi))) {
2305                 adapter->tx_ring[0]->total_packets = 0;
2306                 adapter->tx_ring[0]->total_bytes = 0;
2307                 adapter->rx_ring[0]->total_packets = 0;
2308                 adapter->rx_ring[0]->total_bytes = 0;
2309                 /* would disable interrupts here but EIAM disabled it */
2310                 __napi_schedule(&(q_vector->napi));
2311         }
2312
2313         return IRQ_HANDLED;
2314 }
2315
2316 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2317 {
2318         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2319
2320         for (i = 0; i < q_vectors; i++) {
2321                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2322                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2323                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2324                 q_vector->rxr_count = 0;
2325                 q_vector->txr_count = 0;
2326         }
2327 }
2328
2329 /**
2330  * ixgbe_request_irq - initialize interrupts
2331  * @adapter: board private structure
2332  *
2333  * Attempts to configure interrupts using the best available
2334  * capabilities of the hardware and kernel.
2335  **/
2336 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2337 {
2338         struct net_device *netdev = adapter->netdev;
2339         int err;
2340
2341         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2342                 err = ixgbe_request_msix_irqs(adapter);
2343         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2344                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2345                                   netdev->name, netdev);
2346         } else {
2347                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2348                                   netdev->name, netdev);
2349         }
2350
2351         if (err)
2352                 e_err("request_irq failed, Error %d\n", err);
2353
2354         return err;
2355 }
2356
2357 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2358 {
2359         struct net_device *netdev = adapter->netdev;
2360
2361         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2362                 int i, q_vectors;
2363
2364                 q_vectors = adapter->num_msix_vectors;
2365
2366                 i = q_vectors - 1;
2367                 free_irq(adapter->msix_entries[i].vector, netdev);
2368
2369                 i--;
2370                 for (; i >= 0; i--) {
2371                         free_irq(adapter->msix_entries[i].vector,
2372                                  adapter->q_vector[i]);
2373                 }
2374
2375                 ixgbe_reset_q_vectors(adapter);
2376         } else {
2377                 free_irq(adapter->pdev->irq, netdev);
2378         }
2379 }
2380
2381 /**
2382  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2383  * @adapter: board private structure
2384  **/
2385 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2386 {
2387         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2388                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2389         } else {
2390                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2391                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2392                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2393                 if (adapter->num_vfs > 32)
2394                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2395         }
2396         IXGBE_WRITE_FLUSH(&adapter->hw);
2397         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2398                 int i;
2399                 for (i = 0; i < adapter->num_msix_vectors; i++)
2400                         synchronize_irq(adapter->msix_entries[i].vector);
2401         } else {
2402                 synchronize_irq(adapter->pdev->irq);
2403         }
2404 }
2405
2406 /**
2407  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2408  *
2409  **/
2410 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2411 {
2412         struct ixgbe_hw *hw = &adapter->hw;
2413
2414         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2415                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2416
2417         ixgbe_set_ivar(adapter, 0, 0, 0);
2418         ixgbe_set_ivar(adapter, 1, 0, 0);
2419
2420         map_vector_to_rxq(adapter, 0, 0);
2421         map_vector_to_txq(adapter, 0, 0);
2422
2423         e_info("Legacy interrupt IVAR setup done\n");
2424 }
2425
2426 /**
2427  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2428  * @adapter: board private structure
2429  *
2430  * Configure the Tx unit of the MAC after a reset.
2431  **/
2432 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2433 {
2434         u64 tdba;
2435         struct ixgbe_hw *hw = &adapter->hw;
2436         u32 i, j, tdlen, txctrl;
2437
2438         /* Setup the HW Tx Head and Tail descriptor pointers */
2439         for (i = 0; i < adapter->num_tx_queues; i++) {
2440                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2441                 j = ring->reg_idx;
2442                 tdba = ring->dma;
2443                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2444                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2445                                 (tdba & DMA_BIT_MASK(32)));
2446                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2447                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2448                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2449                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2450                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2451                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2452                 /*
2453                  * Disable Tx Head Writeback RO bit, since this hoses
2454                  * bookkeeping if things aren't delivered in order.
2455                  */
2456                 switch (hw->mac.type) {
2457                 case ixgbe_mac_82598EB:
2458                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2459                         break;
2460                 case ixgbe_mac_82599EB:
2461                 default:
2462                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2463                         break;
2464                 }
2465                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2466                 switch (hw->mac.type) {
2467                 case ixgbe_mac_82598EB:
2468                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2469                         break;
2470                 case ixgbe_mac_82599EB:
2471                 default:
2472                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2473                         break;
2474                 }
2475         }
2476
2477         if (hw->mac.type == ixgbe_mac_82599EB) {
2478                 u32 rttdcs;
2479                 u32 mask;
2480
2481                 /* disable the arbiter while setting MTQC */
2482                 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2483                 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2484                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2485
2486                 /* set transmit pool layout */
2487                 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2488                 switch (adapter->flags & mask) {
2489
2490                 case (IXGBE_FLAG_SRIOV_ENABLED):
2491                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2492                                         (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2493                         break;
2494
2495                 case (IXGBE_FLAG_DCB_ENABLED):
2496                         /* We enable 8 traffic classes, DCB only */
2497                         IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2498                                       (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2499                         break;
2500
2501                 default:
2502                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2503                         break;
2504                 }
2505
2506                 /* re-eable the arbiter */
2507                 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2508                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2509         }
2510 }
2511
2512 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2513
2514 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2515                                    struct ixgbe_ring *rx_ring)
2516 {
2517         u32 srrctl;
2518         int index;
2519         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2520
2521         index = rx_ring->reg_idx;
2522         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2523                 unsigned long mask;
2524                 mask = (unsigned long) feature[RING_F_RSS].mask;
2525                 index = index & mask;
2526         }
2527         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2528
2529         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2530         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2531
2532         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2533                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2534
2535         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2536 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2537                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2538 #else
2539                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2540 #endif
2541                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2542         } else {
2543                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2544                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2545                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2546         }
2547
2548         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2549 }
2550
2551 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2552 {
2553         u32 mrqc = 0;
2554         int mask;
2555
2556         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2557                 return mrqc;
2558
2559         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2560 #ifdef CONFIG_IXGBE_DCB
2561                                  | IXGBE_FLAG_DCB_ENABLED
2562 #endif
2563                                  | IXGBE_FLAG_SRIOV_ENABLED
2564                                 );
2565
2566         switch (mask) {
2567         case (IXGBE_FLAG_RSS_ENABLED):
2568                 mrqc = IXGBE_MRQC_RSSEN;
2569                 break;
2570         case (IXGBE_FLAG_SRIOV_ENABLED):
2571                 mrqc = IXGBE_MRQC_VMDQEN;
2572                 break;
2573 #ifdef CONFIG_IXGBE_DCB
2574         case (IXGBE_FLAG_DCB_ENABLED):
2575                 mrqc = IXGBE_MRQC_RT8TCEN;
2576                 break;
2577 #endif /* CONFIG_IXGBE_DCB */
2578         default:
2579                 break;
2580         }
2581
2582         return mrqc;
2583 }
2584
2585 /**
2586  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2587  * @adapter:    address of board private structure
2588  * @index:      index of ring to set
2589  **/
2590 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2591 {
2592         struct ixgbe_ring *rx_ring;
2593         struct ixgbe_hw *hw = &adapter->hw;
2594         int j;
2595         u32 rscctrl;
2596         int rx_buf_len;
2597
2598         rx_ring = adapter->rx_ring[index];
2599         j = rx_ring->reg_idx;
2600         rx_buf_len = rx_ring->rx_buf_len;
2601         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2602         rscctrl |= IXGBE_RSCCTL_RSCEN;
2603         /*
2604          * we must limit the number of descriptors so that the
2605          * total size of max desc * buf_len is not greater
2606          * than 65535
2607          */
2608         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2609 #if (MAX_SKB_FRAGS > 16)
2610                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2611 #elif (MAX_SKB_FRAGS > 8)
2612                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2613 #elif (MAX_SKB_FRAGS > 4)
2614                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2615 #else
2616                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2617 #endif
2618         } else {
2619                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2620                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2621                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2622                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2623                 else
2624                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2625         }
2626         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2627 }
2628
2629 /**
2630  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2631  * @adapter: board private structure
2632  *
2633  * Configure the Rx unit of the MAC after a reset.
2634  **/
2635 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2636 {
2637         u64 rdba;
2638         struct ixgbe_hw *hw = &adapter->hw;
2639         struct ixgbe_ring *rx_ring;
2640         struct net_device *netdev = adapter->netdev;
2641         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2642         int i, j;
2643         u32 rdlen, rxctrl, rxcsum;
2644         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2645                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2646                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2647         u32 fctrl, hlreg0;
2648         u32 reta = 0, mrqc = 0;
2649         u32 rdrxctl;
2650         int rx_buf_len;
2651
2652         /* Decide whether to use packet split mode or not */
2653         /* Do not use packet split if we're in SR-IOV Mode */
2654         if (!adapter->num_vfs)
2655                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2656
2657         /* Set the RX buffer length according to the mode */
2658         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2659                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2660                 if (hw->mac.type == ixgbe_mac_82599EB) {
2661                         /* PSRTYPE must be initialized in 82599 */
2662                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2663                                       IXGBE_PSRTYPE_UDPHDR |
2664                                       IXGBE_PSRTYPE_IPV4HDR |
2665                                       IXGBE_PSRTYPE_IPV6HDR |
2666                                       IXGBE_PSRTYPE_L2HDR;
2667                         IXGBE_WRITE_REG(hw,
2668                                         IXGBE_PSRTYPE(adapter->num_vfs),
2669                                         psrtype);
2670                 }
2671         } else {
2672                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2673                     (netdev->mtu <= ETH_DATA_LEN))
2674                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2675                 else
2676                         rx_buf_len = ALIGN(max_frame, 1024);
2677         }
2678
2679         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2680         fctrl |= IXGBE_FCTRL_BAM;
2681         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2682         fctrl |= IXGBE_FCTRL_PMCF;
2683         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2684
2685         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2686         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2687                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2688         else
2689                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2690 #ifdef IXGBE_FCOE
2691         if (netdev->features & NETIF_F_FCOE_MTU)
2692                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2693 #endif
2694         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2695
2696         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2697         /* disable receives while setting up the descriptors */
2698         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2699         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2700
2701         /*
2702          * Setup the HW Rx Head and Tail Descriptor Pointers and
2703          * the Base and Length of the Rx Descriptor Ring
2704          */
2705         for (i = 0; i < adapter->num_rx_queues; i++) {
2706                 rx_ring = adapter->rx_ring[i];
2707                 rdba = rx_ring->dma;
2708                 j = rx_ring->reg_idx;
2709                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2710                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2711                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2712                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2713                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2714                 rx_ring->head = IXGBE_RDH(j);
2715                 rx_ring->tail = IXGBE_RDT(j);
2716                 rx_ring->rx_buf_len = rx_buf_len;
2717
2718                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2719                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2720                 else
2721                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2722
2723 #ifdef IXGBE_FCOE
2724                 if (netdev->features & NETIF_F_FCOE_MTU) {
2725                         struct ixgbe_ring_feature *f;
2726                         f = &adapter->ring_feature[RING_F_FCOE];
2727                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2728                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2729                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2730                                         rx_ring->rx_buf_len =
2731                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2732                         }
2733                 }
2734
2735 #endif /* IXGBE_FCOE */
2736                 ixgbe_configure_srrctl(adapter, rx_ring);
2737         }
2738
2739         if (hw->mac.type == ixgbe_mac_82598EB) {
2740                 /*
2741                  * For VMDq support of different descriptor types or
2742                  * buffer sizes through the use of multiple SRRCTL
2743                  * registers, RDRXCTL.MVMEN must be set to 1
2744                  *
2745                  * also, the manual doesn't mention it clearly but DCA hints
2746                  * will only use queue 0's tags unless this bit is set.  Side
2747                  * effects of setting this bit are only that SRRCTL must be
2748                  * fully programmed [0..15]
2749                  */
2750                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2751                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2752                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2753         }
2754
2755         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2756                 u32 vt_reg_bits;
2757                 u32 reg_offset, vf_shift;
2758                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2759                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2760                         | IXGBE_VT_CTL_REPLEN;
2761                 vt_reg_bits |= (adapter->num_vfs <<
2762                                 IXGBE_VT_CTL_POOL_SHIFT);
2763                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2764                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2765
2766                 vf_shift = adapter->num_vfs % 32;
2767                 reg_offset = adapter->num_vfs / 32;
2768                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2769                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2770                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2771                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2772                 /* Enable only the PF's pool for Tx/Rx */
2773                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2774                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2775                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2776                 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2777         }
2778
2779         /* Program MRQC for the distribution of queues */
2780         mrqc = ixgbe_setup_mrqc(adapter);
2781
2782         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2783                 /* Fill out redirection table */
2784                 for (i = 0, j = 0; i < 128; i++, j++) {
2785                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2786                                 j = 0;
2787                         /* reta = 4-byte sliding window of
2788                          * 0x00..(indices-1)(indices-1)00..etc. */
2789                         reta = (reta << 8) | (j * 0x11);
2790                         if ((i & 3) == 3)
2791                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2792                 }
2793
2794                 /* Fill out hash function seeds */
2795                 for (i = 0; i < 10; i++)
2796                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2797
2798                 if (hw->mac.type == ixgbe_mac_82598EB)
2799                         mrqc |= IXGBE_MRQC_RSSEN;
2800                     /* Perform hash on these packet types */
2801                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2802                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2803                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2804                       | IXGBE_MRQC_RSS_FIELD_IPV6
2805                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2806                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2807         }
2808         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2809
2810         if (adapter->num_vfs) {
2811                 u32 reg;
2812
2813                 /* Map PF MAC address in RAR Entry 0 to first pool
2814                  * following VFs */
2815                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2816
2817                 /* Set up VF register offsets for selected VT Mode, i.e.
2818                  * 64 VFs for SR-IOV */
2819                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2820                 reg |= IXGBE_GCR_EXT_SRIOV;
2821                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2822         }
2823
2824         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2825
2826         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2827             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2828                 /* Disable indicating checksum in descriptor, enables
2829                  * RSS hash */
2830                 rxcsum |= IXGBE_RXCSUM_PCSD;
2831         }
2832         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2833                 /* Enable IPv4 payload checksum for UDP fragments
2834                  * if PCSD is not set */
2835                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2836         }
2837
2838         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2839
2840         if (hw->mac.type == ixgbe_mac_82599EB) {
2841                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2842                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2843                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2844                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2845         }
2846
2847         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2848                 /* Enable 82599 HW-RSC */
2849                 for (i = 0; i < adapter->num_rx_queues; i++)
2850                         ixgbe_configure_rscctl(adapter, i);
2851
2852                 /* Disable RSC for ACK packets */
2853                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2854                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2855         }
2856 }
2857
2858 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2859 {
2860         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2861         struct ixgbe_hw *hw = &adapter->hw;
2862         int pool_ndx = adapter->num_vfs;
2863
2864         /* add VID to filter table */
2865         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2866 }
2867
2868 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2869 {
2870         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2871         struct ixgbe_hw *hw = &adapter->hw;
2872         int pool_ndx = adapter->num_vfs;
2873
2874         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2875                 ixgbe_irq_disable(adapter);
2876
2877         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2878
2879         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2880                 ixgbe_irq_enable(adapter);
2881
2882         /* remove VID from filter table */
2883         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2884 }
2885
2886 /**
2887  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2888  * @adapter: driver data
2889  */
2890 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2891 {
2892         struct ixgbe_hw *hw = &adapter->hw;
2893         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2894         int i, j;
2895
2896         switch (hw->mac.type) {
2897         case ixgbe_mac_82598EB:
2898                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2899 #ifdef CONFIG_IXGBE_DCB
2900                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2901                         vlnctrl &= ~IXGBE_VLNCTRL_VME;
2902 #endif
2903                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2904                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2905                 break;
2906         case ixgbe_mac_82599EB:
2907                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2908                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2909                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2910 #ifdef CONFIG_IXGBE_DCB
2911                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2912                         break;
2913 #endif
2914                 for (i = 0; i < adapter->num_rx_queues; i++) {
2915                         j = adapter->rx_ring[i]->reg_idx;
2916                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2917                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2918                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2919                 }
2920                 break;
2921         default:
2922                 break;
2923         }
2924 }
2925
2926 /**
2927  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2928  * @adapter: driver data
2929  */
2930 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2931 {
2932         struct ixgbe_hw *hw = &adapter->hw;
2933         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2934         int i, j;
2935
2936         switch (hw->mac.type) {
2937         case ixgbe_mac_82598EB:
2938                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2939                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2940                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2941                 break;
2942         case ixgbe_mac_82599EB:
2943                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2944                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2945                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2946                 for (i = 0; i < adapter->num_rx_queues; i++) {
2947                         j = adapter->rx_ring[i]->reg_idx;
2948                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2949                         vlnctrl |= IXGBE_RXDCTL_VME;
2950                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2951                 }
2952                 break;
2953         default:
2954                 break;
2955         }
2956 }
2957
2958 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2959                                    struct vlan_group *grp)
2960 {
2961         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2962
2963         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2964                 ixgbe_irq_disable(adapter);
2965         adapter->vlgrp = grp;
2966
2967         /*
2968          * For a DCB driver, always enable VLAN tag stripping so we can
2969          * still receive traffic from a DCB-enabled host even if we're
2970          * not in DCB mode.
2971          */
2972         ixgbe_vlan_filter_enable(adapter);
2973
2974         ixgbe_vlan_rx_add_vid(netdev, 0);
2975
2976         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2977                 ixgbe_irq_enable(adapter);
2978 }
2979
2980 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2981 {
2982         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2983
2984         if (adapter->vlgrp) {
2985                 u16 vid;
2986                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2987                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2988                                 continue;
2989                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2990                 }
2991         }
2992 }
2993
2994 /**
2995  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
2996  * @netdev: network interface device structure
2997  *
2998  * Writes unicast address list to the RAR table.
2999  * Returns: -ENOMEM on failure/insufficient address space
3000  *                0 on no addresses written
3001  *                X on writing X addresses to the RAR table
3002  **/
3003 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3004 {
3005         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3006         struct ixgbe_hw *hw = &adapter->hw;
3007         unsigned int vfn = adapter->num_vfs;
3008         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3009         int count = 0;
3010
3011         /* return ENOMEM indicating insufficient memory for addresses */
3012         if (netdev_uc_count(netdev) > rar_entries)
3013                 return -ENOMEM;
3014
3015         if (!netdev_uc_empty(netdev) && rar_entries) {
3016                 struct netdev_hw_addr *ha;
3017                 /* return error if we do not support writing to RAR table */
3018                 if (!hw->mac.ops.set_rar)
3019                         return -ENOMEM;
3020
3021                 netdev_for_each_uc_addr(ha, netdev) {
3022                         if (!rar_entries)
3023                                 break;
3024                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3025                                             vfn, IXGBE_RAH_AV);
3026                         count++;
3027                 }
3028         }
3029         /* write the addresses in reverse order to avoid write combining */
3030         for (; rar_entries > 0 ; rar_entries--)
3031                 hw->mac.ops.clear_rar(hw, rar_entries);
3032
3033         return count;
3034 }
3035
3036 /**
3037  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3038  * @netdev: network interface device structure
3039  *
3040  * The set_rx_method entry point is called whenever the unicast/multicast
3041  * address list or the network interface flags are updated.  This routine is
3042  * responsible for configuring the hardware for proper unicast, multicast and
3043  * promiscuous mode.
3044  **/
3045 void ixgbe_set_rx_mode(struct net_device *netdev)
3046 {
3047         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3048         struct ixgbe_hw *hw = &adapter->hw;
3049         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3050         int count;
3051
3052         /* Check for Promiscuous and All Multicast modes */
3053
3054         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3055
3056         /* clear the bits we are changing the status of */
3057         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3058
3059         if (netdev->flags & IFF_PROMISC) {
3060                 hw->addr_ctrl.user_set_promisc = true;
3061                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3062                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3063                 /* don't hardware filter vlans in promisc mode */
3064                 ixgbe_vlan_filter_disable(adapter);
3065         } else {
3066                 if (netdev->flags & IFF_ALLMULTI) {
3067                         fctrl |= IXGBE_FCTRL_MPE;
3068                         vmolr |= IXGBE_VMOLR_MPE;
3069                 } else {
3070                         /*
3071                          * Write addresses to the MTA, if the attempt fails
3072                          * then we should just turn on promiscous mode so
3073                          * that we can at least receive multicast traffic
3074                          */
3075                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3076                         vmolr |= IXGBE_VMOLR_ROMPE;
3077                 }
3078                 ixgbe_vlan_filter_enable(adapter);
3079                 hw->addr_ctrl.user_set_promisc = false;
3080                 /*
3081                  * Write addresses to available RAR registers, if there is not
3082                  * sufficient space to store all the addresses then enable
3083                  * unicast promiscous mode
3084                  */
3085                 count = ixgbe_write_uc_addr_list(netdev);
3086                 if (count < 0) {
3087                         fctrl |= IXGBE_FCTRL_UPE;
3088                         vmolr |= IXGBE_VMOLR_ROPE;
3089                 }
3090         }
3091
3092         if (adapter->num_vfs) {
3093                 ixgbe_restore_vf_multicasts(adapter);
3094                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3095                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3096                            IXGBE_VMOLR_ROPE);
3097                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3098         }
3099
3100         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3101 }
3102
3103 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3104 {
3105         int q_idx;
3106         struct ixgbe_q_vector *q_vector;
3107         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3108
3109         /* legacy and MSI only use one vector */
3110         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3111                 q_vectors = 1;
3112
3113         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3114                 struct napi_struct *napi;
3115                 q_vector = adapter->q_vector[q_idx];
3116                 napi = &q_vector->napi;
3117                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3118                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3119                                 if (q_vector->txr_count == 1)
3120                                         napi->poll = &ixgbe_clean_txonly;
3121                                 else if (q_vector->rxr_count == 1)
3122                                         napi->poll = &ixgbe_clean_rxonly;
3123                         }
3124                 }
3125
3126                 napi_enable(napi);
3127         }
3128 }
3129
3130 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3131 {
3132         int q_idx;
3133         struct ixgbe_q_vector *q_vector;
3134         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3135
3136         /* legacy and MSI only use one vector */
3137         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3138                 q_vectors = 1;
3139
3140         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3141                 q_vector = adapter->q_vector[q_idx];
3142                 napi_disable(&q_vector->napi);
3143         }
3144 }
3145
3146 #ifdef CONFIG_IXGBE_DCB
3147 /*
3148  * ixgbe_configure_dcb - Configure DCB hardware
3149  * @adapter: ixgbe adapter struct
3150  *
3151  * This is called by the driver on open to configure the DCB hardware.
3152  * This is also called by the gennetlink interface when reconfiguring
3153  * the DCB state.
3154  */
3155 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3156 {
3157         struct ixgbe_hw *hw = &adapter->hw;
3158         u32 txdctl;
3159         int i, j;
3160
3161         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3162         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3163         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3164
3165         /* reconfigure the hardware */
3166         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3167
3168         for (i = 0; i < adapter->num_tx_queues; i++) {
3169                 j = adapter->tx_ring[i]->reg_idx;
3170                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3171                 /* PThresh workaround for Tx hang with DFP enabled. */
3172                 txdctl |= 32;
3173                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3174         }
3175         /* Enable VLAN tag insert/strip */
3176         ixgbe_vlan_filter_enable(adapter);
3177
3178         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3179 }
3180
3181 #endif
3182 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3183 {
3184         struct net_device *netdev = adapter->netdev;
3185         struct ixgbe_hw *hw = &adapter->hw;
3186         int i;
3187
3188         ixgbe_set_rx_mode(netdev);
3189
3190         ixgbe_restore_vlan(adapter);
3191 #ifdef CONFIG_IXGBE_DCB
3192         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3193                 if (hw->mac.type == ixgbe_mac_82598EB)
3194                         netif_set_gso_max_size(netdev, 32768);
3195                 else
3196                         netif_set_gso_max_size(netdev, 65536);
3197                 ixgbe_configure_dcb(adapter);
3198         } else {
3199                 netif_set_gso_max_size(netdev, 65536);
3200         }
3201 #else
3202         netif_set_gso_max_size(netdev, 65536);
3203 #endif
3204
3205 #ifdef IXGBE_FCOE
3206         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3207                 ixgbe_configure_fcoe(adapter);
3208
3209 #endif /* IXGBE_FCOE */
3210         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3211                 for (i = 0; i < adapter->num_tx_queues; i++)
3212                         adapter->tx_ring[i]->atr_sample_rate =
3213                                                        adapter->atr_sample_rate;
3214                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3215         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3216                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3217         }
3218
3219         ixgbe_configure_tx(adapter);
3220         ixgbe_configure_rx(adapter);
3221         for (i = 0; i < adapter->num_rx_queues; i++)
3222                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3223                                        (adapter->rx_ring[i]->count - 1));
3224 }
3225
3226 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3227 {
3228         switch (hw->phy.type) {
3229         case ixgbe_phy_sfp_avago:
3230         case ixgbe_phy_sfp_ftl:
3231         case ixgbe_phy_sfp_intel:
3232         case ixgbe_phy_sfp_unknown:
3233         case ixgbe_phy_sfp_passive_tyco:
3234         case ixgbe_phy_sfp_passive_unknown:
3235         case ixgbe_phy_sfp_active_unknown:
3236         case ixgbe_phy_sfp_ftl_active:
3237                 return true;
3238         default:
3239                 return false;
3240         }
3241 }
3242
3243 /**
3244  * ixgbe_sfp_link_config - set up SFP+ link
3245  * @adapter: pointer to private adapter struct
3246  **/
3247 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3248 {
3249         struct ixgbe_hw *hw = &adapter->hw;
3250
3251                 if (hw->phy.multispeed_fiber) {
3252                         /*
3253                          * In multispeed fiber setups, the device may not have
3254                          * had a physical connection when the driver loaded.
3255                          * If that's the case, the initial link configuration
3256                          * couldn't get the MAC into 10G or 1G mode, so we'll
3257                          * never have a link status change interrupt fire.
3258                          * We need to try and force an autonegotiation
3259                          * session, then bring up link.
3260                          */
3261                         hw->mac.ops.setup_sfp(hw);
3262                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3263                                 schedule_work(&adapter->multispeed_fiber_task);
3264                 } else {
3265                         /*
3266                          * Direct Attach Cu and non-multispeed fiber modules
3267                          * still need to be configured properly prior to
3268                          * attempting link.
3269                          */
3270                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3271                                 schedule_work(&adapter->sfp_config_module_task);
3272                 }
3273 }
3274
3275 /**
3276  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3277  * @hw: pointer to private hardware struct
3278  *
3279  * Returns 0 on success, negative on failure
3280  **/
3281 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3282 {
3283         u32 autoneg;
3284         bool negotiation, link_up = false;
3285         u32 ret = IXGBE_ERR_LINK_SETUP;
3286
3287         if (hw->mac.ops.check_link)
3288                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3289
3290         if (ret)
3291                 goto link_cfg_out;
3292
3293         if (hw->mac.ops.get_link_capabilities)
3294                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3295         if (ret)
3296                 goto link_cfg_out;
3297
3298         if (hw->mac.ops.setup_link)
3299                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3300 link_cfg_out:
3301         return ret;
3302 }
3303
3304 #define IXGBE_MAX_RX_DESC_POLL 10
3305 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3306                                               int rxr)
3307 {
3308         int j = adapter->rx_ring[rxr]->reg_idx;
3309         int k;
3310
3311         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3312                 if (IXGBE_READ_REG(&adapter->hw,
3313                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3314                         break;
3315                 else
3316                         msleep(1);
3317         }
3318         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3319                 e_err("RXDCTL.ENABLE on Rx queue %d not set within "
3320                       "the polling period\n", rxr);
3321         }
3322         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3323                               (adapter->rx_ring[rxr]->count - 1));
3324 }
3325
3326 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3327 {
3328         struct net_device *netdev = adapter->netdev;
3329         struct ixgbe_hw *hw = &adapter->hw;
3330         int i, j = 0;
3331         int num_rx_rings = adapter->num_rx_queues;
3332         int err;
3333         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3334         u32 txdctl, rxdctl, mhadd;
3335         u32 dmatxctl;
3336         u32 gpie;
3337         u32 ctrl_ext;
3338
3339         ixgbe_get_hw_control(adapter);
3340
3341         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3342             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3343                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3344                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3345                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3346                 } else {
3347                         /* MSI only */
3348                         gpie = 0;
3349                 }
3350                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3351                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3352                         gpie |= IXGBE_GPIE_VTMODE_64;
3353                 }
3354                 /* XXX: to interrupt immediately for EICS writes, enable this */
3355                 /* gpie |= IXGBE_GPIE_EIMEN; */
3356                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3357         }
3358
3359         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3360                 /*
3361                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3362                  * this saves a register write for every interrupt
3363                  */
3364                 switch (hw->mac.type) {
3365                 case ixgbe_mac_82598EB:
3366                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3367                         break;
3368                 default:
3369                 case ixgbe_mac_82599EB:
3370                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3371                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3372                         break;
3373                 }
3374         } else {
3375                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3376                  * specifically only auto mask tx and rx interrupts */
3377                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3378         }
3379
3380         /* Enable Thermal over heat sensor interrupt */
3381         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3382                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3383                 gpie |= IXGBE_SDP0_GPIEN;
3384                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3385         }
3386
3387         /* Enable fan failure interrupt if media type is copper */
3388         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3389                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3390                 gpie |= IXGBE_SDP1_GPIEN;
3391                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3392         }
3393
3394         if (hw->mac.type == ixgbe_mac_82599EB) {
3395                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3396                 gpie |= IXGBE_SDP1_GPIEN;
3397                 gpie |= IXGBE_SDP2_GPIEN;
3398                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3399         }
3400
3401 #ifdef IXGBE_FCOE
3402         /* adjust max frame to be able to do baby jumbo for FCoE */
3403         if ((netdev->features & NETIF_F_FCOE_MTU) &&
3404             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3405                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3406
3407 #endif /* IXGBE_FCOE */
3408         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3409         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3410                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3411                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3412
3413                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3414         }
3415
3416         for (i = 0; i < adapter->num_tx_queues; i++) {
3417                 j = adapter->tx_ring[i]->reg_idx;
3418                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3419                 if (adapter->rx_itr_setting == 0) {
3420                         /* cannot set wthresh when itr==0 */
3421                         txdctl &= ~0x007F0000;
3422                 } else {
3423                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3424                         txdctl |= (8 << 16);
3425                 }
3426                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3427         }
3428
3429         if (hw->mac.type == ixgbe_mac_82599EB) {
3430                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3431                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3432                 dmatxctl |= IXGBE_DMATXCTL_TE;
3433                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3434         }
3435         for (i = 0; i < adapter->num_tx_queues; i++) {
3436                 j = adapter->tx_ring[i]->reg_idx;
3437                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3438                 txdctl |= IXGBE_TXDCTL_ENABLE;
3439                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3440                 if (hw->mac.type == ixgbe_mac_82599EB) {
3441                         int wait_loop = 10;
3442                         /* poll for Tx Enable ready */
3443                         do {
3444                                 msleep(1);
3445                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3446                         } while (--wait_loop &&
3447                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3448                         if (!wait_loop)
3449                                 e_err("Could not enable Tx Queue %d\n", j);
3450                 }
3451         }
3452
3453         for (i = 0; i < num_rx_rings; i++) {
3454                 j = adapter->rx_ring[i]->reg_idx;
3455                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3456                 /* enable PTHRESH=32 descriptors (half the internal cache)
3457                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3458                  * this also removes a pesky rx_no_buffer_count increment */
3459                 rxdctl |= 0x0020;
3460                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3461                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3462                 if (hw->mac.type == ixgbe_mac_82599EB)
3463                         ixgbe_rx_desc_queue_enable(adapter, i);
3464         }
3465         /* enable all receives */
3466         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3467         if (hw->mac.type == ixgbe_mac_82598EB)
3468                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3469         else
3470                 rxdctl |= IXGBE_RXCTRL_RXEN;
3471         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3472
3473         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3474                 ixgbe_configure_msix(adapter);
3475         else
3476                 ixgbe_configure_msi_and_legacy(adapter);
3477
3478         /* enable the optics */
3479         if (hw->phy.multispeed_fiber)
3480                 hw->mac.ops.enable_tx_laser(hw);
3481
3482         clear_bit(__IXGBE_DOWN, &adapter->state);
3483         ixgbe_napi_enable_all(adapter);
3484
3485         /* clear any pending interrupts, may auto mask */
3486         IXGBE_READ_REG(hw, IXGBE_EICR);
3487
3488         ixgbe_irq_enable(adapter);
3489
3490         /*
3491          * If this adapter has a fan, check to see if we had a failure
3492          * before we enabled the interrupt.
3493          */
3494         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3495                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3496                 if (esdp & IXGBE_ESDP_SDP1)
3497                         e_crit("Fan has stopped, replace the adapter\n");
3498         }
3499
3500         /*
3501          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3502          * arrived before interrupts were enabled but after probe.  Such
3503          * devices wouldn't have their type identified yet. We need to
3504          * kick off the SFP+ module setup first, then try to bring up link.
3505          * If we're not hot-pluggable SFP+, we just need to configure link
3506          * and bring it up.
3507          */
3508         if (hw->phy.type == ixgbe_phy_unknown) {
3509                 err = hw->phy.ops.identify(hw);
3510                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3511                         /*
3512                          * Take the device down and schedule the sfp tasklet
3513                          * which will unregister_netdev and log it.
3514                          */
3515                         ixgbe_down(adapter);
3516                         schedule_work(&adapter->sfp_config_module_task);
3517                         return err;
3518                 }
3519         }
3520
3521         if (ixgbe_is_sfp(hw)) {
3522                 ixgbe_sfp_link_config(adapter);
3523         } else {
3524                 err = ixgbe_non_sfp_link_config(hw);
3525                 if (err)
3526                         e_err("link_config FAILED %d\n", err);
3527         }
3528
3529         for (i = 0; i < adapter->num_tx_queues; i++)
3530                 set_bit(__IXGBE_FDIR_INIT_DONE,
3531                         &(adapter->tx_ring[i]->reinit_state));
3532
3533         /* enable transmits */
3534         netif_tx_start_all_queues(netdev);
3535
3536         /* bring the link up in the watchdog, this could race with our first
3537          * link up interrupt but shouldn't be a problem */
3538         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3539         adapter->link_check_timeout = jiffies;
3540         mod_timer(&adapter->watchdog_timer, jiffies);
3541
3542         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3543         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3544         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3545         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3546
3547         return 0;
3548 }
3549
3550 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3551 {
3552         WARN_ON(in_interrupt());
3553         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3554                 msleep(1);
3555         ixgbe_down(adapter);
3556         /*
3557          * If SR-IOV enabled then wait a bit before bringing the adapter
3558          * back up to give the VFs time to respond to the reset.  The
3559          * two second wait is based upon the watchdog timer cycle in
3560          * the VF driver.
3561          */
3562         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3563                 msleep(2000);
3564         ixgbe_up(adapter);
3565         clear_bit(__IXGBE_RESETTING, &adapter->state);
3566 }
3567
3568 int ixgbe_up(struct ixgbe_adapter *adapter)
3569 {
3570         /* hardware has been reset, we need to reload some things */
3571         ixgbe_configure(adapter);
3572
3573         return ixgbe_up_complete(adapter);
3574 }
3575
3576 void ixgbe_reset(struct ixgbe_adapter *adapter)
3577 {
3578         struct ixgbe_hw *hw = &adapter->hw;
3579         int err;
3580
3581         err = hw->mac.ops.init_hw(hw);
3582         switch (err) {
3583         case 0:
3584         case IXGBE_ERR_SFP_NOT_PRESENT:
3585                 break;
3586         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3587                 e_dev_err("master disable timed out\n");
3588                 break;
3589         case IXGBE_ERR_EEPROM_VERSION:
3590                 /* We are running on a pre-production device, log a warning */
3591                 e_dev_warn("This device is a pre-production adapter/LOM. "
3592                            "Please be aware there may be issuesassociated with "
3593                            "your hardware.  If you are experiencing problems "
3594                            "please contact your Intel or hardware "
3595                            "representative who provided you with this "
3596                            "hardware.\n");
3597                 break;
3598         default:
3599                 e_dev_err("Hardware Error: %d\n", err);
3600         }
3601
3602         /* reprogram the RAR[0] in case user changed it. */
3603         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3604                             IXGBE_RAH_AV);
3605 }
3606
3607 /**
3608  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3609  * @adapter: board private structure
3610  * @rx_ring: ring to free buffers from
3611  **/
3612 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3613                                 struct ixgbe_ring *rx_ring)
3614 {
3615         struct pci_dev *pdev = adapter->pdev;
3616         unsigned long size;
3617         unsigned int i;
3618
3619         /* Free all the Rx ring sk_buffs */
3620
3621         for (i = 0; i < rx_ring->count; i++) {
3622                 struct ixgbe_rx_buffer *rx_buffer_info;
3623
3624                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3625                 if (rx_buffer_info->dma) {
3626                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3627                                          rx_ring->rx_buf_len,
3628                                          DMA_FROM_DEVICE);
3629                         rx_buffer_info->dma = 0;
3630                 }
3631                 if (rx_buffer_info->skb) {
3632                         struct sk_buff *skb = rx_buffer_info->skb;
3633                         rx_buffer_info->skb = NULL;
3634                         do {
3635                                 struct sk_buff *this = skb;
3636                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3637                                         dma_unmap_single(&pdev->dev,
3638                                                          IXGBE_RSC_CB(this)->dma,
3639                                                          rx_ring->rx_buf_len,
3640                                                          DMA_FROM_DEVICE);
3641                                         IXGBE_RSC_CB(this)->dma = 0;
3642                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3643                                 }
3644                                 skb = skb->prev;
3645                                 dev_kfree_skb(this);
3646                         } while (skb);
3647                 }
3648                 if (!rx_buffer_info->page)
3649                         continue;
3650                 if (rx_buffer_info->page_dma) {
3651                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3652                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3653                         rx_buffer_info->page_dma = 0;
3654                 }
3655                 put_page(rx_buffer_info->page);
3656                 rx_buffer_info->page = NULL;
3657                 rx_buffer_info->page_offset = 0;
3658         }
3659
3660         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3661         memset(rx_ring->rx_buffer_info, 0, size);
3662
3663         /* Zero out the descriptor ring */
3664         memset(rx_ring->desc, 0, rx_ring->size);
3665
3666         rx_ring->next_to_clean = 0;
3667         rx_ring->next_to_use = 0;
3668
3669         if (rx_ring->head)
3670                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3671         if (rx_ring->tail)
3672                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3673 }
3674
3675 /**
3676  * ixgbe_clean_tx_ring - Free Tx Buffers
3677  * @adapter: board private structure
3678  * @tx_ring: ring to be cleaned
3679  **/
3680 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3681                                 struct ixgbe_ring *tx_ring)
3682 {
3683         struct ixgbe_tx_buffer *tx_buffer_info;
3684         unsigned long size;
3685         unsigned int i;
3686
3687         /* Free all the Tx ring sk_buffs */
3688
3689         for (i = 0; i < tx_ring->count; i++) {
3690                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3691                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3692         }
3693
3694         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3695         memset(tx_ring->tx_buffer_info, 0, size);
3696
3697         /* Zero out the descriptor ring */
3698         memset(tx_ring->desc, 0, tx_ring->size);
3699
3700         tx_ring->next_to_use = 0;
3701         tx_ring->next_to_clean = 0;
3702
3703         if (tx_ring->head)
3704                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3705         if (tx_ring->tail)
3706                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3707 }
3708
3709 /**
3710  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3711  * @adapter: board private structure
3712  **/
3713 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3714 {
3715         int i;
3716
3717         for (i = 0; i < adapter->num_rx_queues; i++)
3718                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3719 }
3720
3721 /**
3722  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3723  * @adapter: board private structure
3724  **/
3725 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3726 {
3727         int i;
3728
3729         for (i = 0; i < adapter->num_tx_queues; i++)
3730                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3731 }
3732
3733 void ixgbe_down(struct ixgbe_adapter *adapter)
3734 {
3735         struct net_device *netdev = adapter->netdev;
3736         struct ixgbe_hw *hw = &adapter->hw;
3737         u32 rxctrl;
3738         u32 txdctl;
3739         int i, j;
3740
3741         /* signal that we are down to the interrupt handler */
3742         set_bit(__IXGBE_DOWN, &adapter->state);
3743
3744         /* power down the optics */
3745         if (hw->phy.multispeed_fiber)
3746                 hw->mac.ops.disable_tx_laser(hw);
3747
3748         /* disable receive for all VFs and wait one second */
3749         if (adapter->num_vfs) {
3750                 /* ping all the active vfs to let them know we are going down */
3751                 ixgbe_ping_all_vfs(adapter);
3752
3753                 /* Disable all VFTE/VFRE TX/RX */
3754                 ixgbe_disable_tx_rx(adapter);
3755
3756                 /* Mark all the VFs as inactive */
3757                 for (i = 0 ; i < adapter->num_vfs; i++)
3758                         adapter->vfinfo[i].clear_to_send = 0;
3759         }
3760
3761         /* disable receives */
3762         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3763         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3764
3765         IXGBE_WRITE_FLUSH(hw);
3766         msleep(10);
3767
3768         netif_tx_stop_all_queues(netdev);
3769
3770         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3771         del_timer_sync(&adapter->sfp_timer);
3772         del_timer_sync(&adapter->watchdog_timer);
3773         cancel_work_sync(&adapter->watchdog_task);
3774
3775         netif_carrier_off(netdev);
3776         netif_tx_disable(netdev);
3777
3778         ixgbe_irq_disable(adapter);
3779
3780         ixgbe_napi_disable_all(adapter);
3781
3782         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3783             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3784                 cancel_work_sync(&adapter->fdir_reinit_task);
3785
3786         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3787                 cancel_work_sync(&adapter->check_overtemp_task);
3788
3789         /* disable transmits in the hardware now that interrupts are off */
3790         for (i = 0; i < adapter->num_tx_queues; i++) {
3791                 j = adapter->tx_ring[i]->reg_idx;
3792                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3793                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3794                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3795         }
3796         /* Disable the Tx DMA engine on 82599 */
3797         if (hw->mac.type == ixgbe_mac_82599EB)
3798                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3799                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3800                                  ~IXGBE_DMATXCTL_TE));
3801
3802         /* clear n-tuple filters that are cached */
3803         ethtool_ntuple_flush(netdev);
3804
3805         if (!pci_channel_offline(adapter->pdev))
3806                 ixgbe_reset(adapter);
3807         ixgbe_clean_all_tx_rings(adapter);
3808         ixgbe_clean_all_rx_rings(adapter);
3809
3810 #ifdef CONFIG_IXGBE_DCA
3811         /* since we reset the hardware DCA settings were cleared */
3812         ixgbe_setup_dca(adapter);
3813 #endif
3814 }
3815
3816 /**
3817  * ixgbe_poll - NAPI Rx polling callback
3818  * @napi: structure for representing this polling device
3819  * @budget: how many packets driver is allowed to clean
3820  *
3821  * This function is used for legacy and MSI, NAPI mode
3822  **/
3823 static int ixgbe_poll(struct napi_struct *napi, int budget)
3824 {
3825         struct ixgbe_q_vector *q_vector =
3826                                 container_of(napi, struct ixgbe_q_vector, napi);
3827         struct ixgbe_adapter *adapter = q_vector->adapter;
3828         int tx_clean_complete, work_done = 0;
3829
3830 #ifdef CONFIG_IXGBE_DCA
3831         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3832                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3833                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3834         }
3835 #endif
3836
3837         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3838         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3839
3840         if (!tx_clean_complete)
3841                 work_done = budget;
3842
3843         /* If budget not fully consumed, exit the polling mode */
3844         if (work_done < budget) {
3845                 napi_complete(napi);
3846                 if (adapter->rx_itr_setting & 1)
3847                         ixgbe_set_itr(adapter);
3848                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3849                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3850         }
3851         return work_done;
3852 }
3853
3854 /**
3855  * ixgbe_tx_timeout - Respond to a Tx Hang
3856  * @netdev: network interface device structure
3857  **/
3858 static void ixgbe_tx_timeout(struct net_device *netdev)
3859 {
3860         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3861
3862         /* Do the reset outside of interrupt context */
3863         schedule_work(&adapter->reset_task);
3864 }
3865
3866 static void ixgbe_reset_task(struct work_struct *work)
3867 {
3868         struct ixgbe_adapter *adapter;
3869         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3870
3871         /* If we're already down or resetting, just bail */
3872         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3873             test_bit(__IXGBE_RESETTING, &adapter->state))
3874                 return;
3875
3876         adapter->tx_timeout_count++;
3877
3878         ixgbe_dump(adapter);
3879         netdev_err(adapter->netdev, "Reset adapter\n");
3880         ixgbe_reinit_locked(adapter);
3881 }
3882
3883 #ifdef CONFIG_IXGBE_DCB
3884 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3885 {
3886         bool ret = false;
3887         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3888
3889         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3890                 return ret;
3891
3892         f->mask = 0x7 << 3;
3893         adapter->num_rx_queues = f->indices;
3894         adapter->num_tx_queues = f->indices;
3895         ret = true;
3896
3897         return ret;
3898 }
3899 #endif
3900
3901 /**
3902  * ixgbe_set_rss_queues: Allocate queues for RSS
3903  * @adapter: board private structure to initialize
3904  *
3905  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3906  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3907  *
3908  **/
3909 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3910 {
3911         bool ret = false;
3912         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3913
3914         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3915                 f->mask = 0xF;
3916                 adapter->num_rx_queues = f->indices;
3917                 adapter->num_tx_queues = f->indices;
3918                 ret = true;
3919         } else {
3920                 ret = false;
3921         }
3922
3923         return ret;
3924 }
3925
3926 /**
3927  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3928  * @adapter: board private structure to initialize
3929  *
3930  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3931  * to the original CPU that initiated the Tx session.  This runs in addition
3932  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3933  * Rx load across CPUs using RSS.
3934  *
3935  **/
3936 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3937 {
3938         bool ret = false;
3939         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3940
3941         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3942         f_fdir->mask = 0;
3943
3944         /* Flow Director must have RSS enabled */
3945         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3946             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3947              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3948                 adapter->num_tx_queues = f_fdir->indices;
3949                 adapter->num_rx_queues = f_fdir->indices;
3950                 ret = true;
3951         } else {
3952                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3953                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3954         }
3955         return ret;
3956 }
3957
3958 #ifdef IXGBE_FCOE
3959 /**
3960  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3961  * @adapter: board private structure to initialize
3962  *
3963  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3964  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3965  * rx queues out of the max number of rx queues, instead, it is used as the
3966  * index of the first rx queue used by FCoE.
3967  *
3968  **/
3969 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3970 {
3971         bool ret = false;
3972         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3973
3974         f->indices = min((int)num_online_cpus(), f->indices);
3975         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3976                 adapter->num_rx_queues = 1;
3977                 adapter->num_tx_queues = 1;
3978 #ifdef CONFIG_IXGBE_DCB
3979                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3980                         e_info("FCoE enabled with DCB\n");
3981                         ixgbe_set_dcb_queues(adapter);
3982                 }
3983 #endif
3984                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3985                         e_info("FCoE enabled with RSS\n");
3986                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3987                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3988                                 ixgbe_set_fdir_queues(adapter);
3989                         else
3990                                 ixgbe_set_rss_queues(adapter);
3991                 }
3992                 /* adding FCoE rx rings to the end */
3993                 f->mask = adapter->num_rx_queues;
3994                 adapter->num_rx_queues += f->indices;
3995                 adapter->num_tx_queues += f->indices;
3996
3997                 ret = true;
3998         }
3999
4000         return ret;
4001 }
4002
4003 #endif /* IXGBE_FCOE */
4004 /**
4005  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4006  * @adapter: board private structure to initialize
4007  *
4008  * IOV doesn't actually use anything, so just NAK the
4009  * request for now and let the other queue routines
4010  * figure out what to do.
4011  */
4012 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4013 {
4014         return false;
4015 }
4016
4017 /*
4018  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4019  * @adapter: board private structure to initialize
4020  *
4021  * This is the top level queue allocation routine.  The order here is very
4022  * important, starting with the "most" number of features turned on at once,
4023  * and ending with the smallest set of features.  This way large combinations
4024  * can be allocated if they're turned on, and smaller combinations are the
4025  * fallthrough conditions.
4026  *
4027  **/
4028 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4029 {
4030         /* Start with base case */
4031         adapter->num_rx_queues = 1;
4032         adapter->num_tx_queues = 1;
4033         adapter->num_rx_pools = adapter->num_rx_queues;
4034         adapter->num_rx_queues_per_pool = 1;
4035
4036         if (ixgbe_set_sriov_queues(adapter))
4037                 return;
4038
4039 #ifdef IXGBE_FCOE
4040         if (ixgbe_set_fcoe_queues(adapter))
4041                 goto done;
4042
4043 #endif /* IXGBE_FCOE */
4044 #ifdef CONFIG_IXGBE_DCB
4045         if (ixgbe_set_dcb_queues(adapter))
4046                 goto done;
4047
4048 #endif
4049         if (ixgbe_set_fdir_queues(adapter))
4050                 goto done;
4051
4052         if (ixgbe_set_rss_queues(adapter))
4053                 goto done;
4054
4055         /* fallback to base case */
4056         adapter->num_rx_queues = 1;
4057         adapter->num_tx_queues = 1;
4058
4059 done:
4060         /* Notify the stack of the (possibly) reduced Tx Queue count. */
4061         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
4062 }
4063
4064 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4065                                        int vectors)
4066 {
4067         int err, vector_threshold;
4068
4069         /* We'll want at least 3 (vector_threshold):
4070          * 1) TxQ[0] Cleanup
4071          * 2) RxQ[0] Cleanup
4072          * 3) Other (Link Status Change, etc.)
4073          * 4) TCP Timer (optional)
4074          */
4075         vector_threshold = MIN_MSIX_COUNT;
4076
4077         /* The more we get, the more we will assign to Tx/Rx Cleanup
4078          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4079          * Right now, we simply care about how many we'll get; we'll
4080          * set them up later while requesting irq's.
4081          */
4082         while (vectors >= vector_threshold) {
4083                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4084                                       vectors);
4085                 if (!err) /* Success in acquiring all requested vectors. */
4086                         break;
4087                 else if (err < 0)
4088                         vectors = 0; /* Nasty failure, quit now */
4089                 else /* err == number of vectors we should try again with */
4090                         vectors = err;
4091         }
4092
4093         if (vectors < vector_threshold) {
4094                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4095                  * This just means we'll go with either a single MSI
4096                  * vector or fall back to legacy interrupts.
4097                  */
4098                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4099                              "Unable to allocate MSI-X interrupts\n");
4100                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4101                 kfree(adapter->msix_entries);
4102                 adapter->msix_entries = NULL;
4103         } else {
4104                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4105                 /*
4106                  * Adjust for only the vectors we'll use, which is minimum
4107                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4108                  * vectors we were allocated.
4109                  */
4110                 adapter->num_msix_vectors = min(vectors,
4111                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4112         }
4113 }
4114
4115 /**
4116  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4117  * @adapter: board private structure to initialize
4118  *
4119  * Cache the descriptor ring offsets for RSS to the assigned rings.
4120  *
4121  **/
4122 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4123 {
4124         int i;
4125         bool ret = false;
4126
4127         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4128                 for (i = 0; i < adapter->num_rx_queues; i++)
4129                         adapter->rx_ring[i]->reg_idx = i;
4130                 for (i = 0; i < adapter->num_tx_queues; i++)
4131                         adapter->tx_ring[i]->reg_idx = i;
4132                 ret = true;
4133         } else {
4134                 ret = false;
4135         }
4136
4137         return ret;
4138 }
4139
4140 #ifdef CONFIG_IXGBE_DCB
4141 /**
4142  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4143  * @adapter: board private structure to initialize
4144  *
4145  * Cache the descriptor ring offsets for DCB to the assigned rings.
4146  *
4147  **/
4148 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4149 {
4150         int i;
4151         bool ret = false;
4152         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4153
4154         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4155                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4156                         /* the number of queues is assumed to be symmetric */
4157                         for (i = 0; i < dcb_i; i++) {
4158                                 adapter->rx_ring[i]->reg_idx = i << 3;
4159                                 adapter->tx_ring[i]->reg_idx = i << 2;
4160                         }
4161                         ret = true;
4162                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4163                         if (dcb_i == 8) {
4164                                 /*
4165                                  * Tx TC0 starts at: descriptor queue 0
4166                                  * Tx TC1 starts at: descriptor queue 32
4167                                  * Tx TC2 starts at: descriptor queue 64
4168                                  * Tx TC3 starts at: descriptor queue 80
4169                                  * Tx TC4 starts at: descriptor queue 96
4170                                  * Tx TC5 starts at: descriptor queue 104
4171                                  * Tx TC6 starts at: descriptor queue 112
4172                                  * Tx TC7 starts at: descriptor queue 120
4173                                  *
4174                                  * Rx TC0-TC7 are offset by 16 queues each
4175                                  */
4176                                 for (i = 0; i < 3; i++) {
4177                                         adapter->tx_ring[i]->reg_idx = i << 5;
4178                                         adapter->rx_ring[i]->reg_idx = i << 4;
4179                                 }
4180                                 for ( ; i < 5; i++) {
4181                                         adapter->tx_ring[i]->reg_idx =
4182                                                                  ((i + 2) << 4);
4183                                         adapter->rx_ring[i]->reg_idx = i << 4;
4184                                 }
4185                                 for ( ; i < dcb_i; i++) {
4186                                         adapter->tx_ring[i]->reg_idx =
4187                                                                  ((i + 8) << 3);
4188                                         adapter->rx_ring[i]->reg_idx = i << 4;
4189                                 }
4190
4191                                 ret = true;
4192                         } else if (dcb_i == 4) {
4193                                 /*
4194                                  * Tx TC0 starts at: descriptor queue 0
4195                                  * Tx TC1 starts at: descriptor queue 64
4196                                  * Tx TC2 starts at: descriptor queue 96
4197                                  * Tx TC3 starts at: descriptor queue 112
4198                                  *
4199                                  * Rx TC0-TC3 are offset by 32 queues each
4200                                  */
4201                                 adapter->tx_ring[0]->reg_idx = 0;
4202                                 adapter->tx_ring[1]->reg_idx = 64;
4203                                 adapter->tx_ring[2]->reg_idx = 96;
4204                                 adapter->tx_ring[3]->reg_idx = 112;
4205                                 for (i = 0 ; i < dcb_i; i++)
4206                                         adapter->rx_ring[i]->reg_idx = i << 5;
4207
4208                                 ret = true;
4209                         } else {
4210                                 ret = false;
4211                         }
4212                 } else {
4213                         ret = false;
4214                 }
4215         } else {
4216                 ret = false;
4217         }
4218
4219         return ret;
4220 }
4221 #endif
4222
4223 /**
4224  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4225  * @adapter: board private structure to initialize
4226  *
4227  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4228  *
4229  **/
4230 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4231 {
4232         int i;
4233         bool ret = false;
4234
4235         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4236             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4237              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4238                 for (i = 0; i < adapter->num_rx_queues; i++)
4239                         adapter->rx_ring[i]->reg_idx = i;
4240                 for (i = 0; i < adapter->num_tx_queues; i++)
4241                         adapter->tx_ring[i]->reg_idx = i;
4242                 ret = true;
4243         }
4244
4245         return ret;
4246 }
4247
4248 #ifdef IXGBE_FCOE
4249 /**
4250  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4251  * @adapter: board private structure to initialize
4252  *
4253  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4254  *
4255  */
4256 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4257 {
4258         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4259         bool ret = false;
4260         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4261
4262         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4263 #ifdef CONFIG_IXGBE_DCB
4264                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4265                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4266
4267                         ixgbe_cache_ring_dcb(adapter);
4268                         /* find out queues in TC for FCoE */
4269                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4270                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4271                         /*
4272                          * In 82599, the number of Tx queues for each traffic
4273                          * class for both 8-TC and 4-TC modes are:
4274                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4275                          * 8 TCs:  32  32  16  16   8   8   8   8
4276                          * 4 TCs:  64  64  32  32
4277                          * We have max 8 queues for FCoE, where 8 the is
4278                          * FCoE redirection table size. If TC for FCoE is
4279                          * less than or equal to TC3, we have enough queues
4280                          * to add max of 8 queues for FCoE, so we start FCoE
4281                          * tx descriptor from the next one, i.e., reg_idx + 1.
4282                          * If TC for FCoE is above TC3, implying 8 TC mode,
4283                          * and we need 8 for FCoE, we have to take all queues
4284                          * in that traffic class for FCoE.
4285                          */
4286                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4287                                 fcoe_tx_i--;
4288                 }
4289 #endif /* CONFIG_IXGBE_DCB */
4290                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4291                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4292                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4293                                 ixgbe_cache_ring_fdir(adapter);
4294                         else
4295                                 ixgbe_cache_ring_rss(adapter);
4296
4297                         fcoe_rx_i = f->mask;
4298                         fcoe_tx_i = f->mask;
4299                 }
4300                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4301                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4302                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4303                 }
4304                 ret = true;
4305         }
4306         return ret;
4307 }
4308
4309 #endif /* IXGBE_FCOE */
4310 /**
4311  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4312  * @adapter: board private structure to initialize
4313  *
4314  * SR-IOV doesn't use any descriptor rings but changes the default if
4315  * no other mapping is used.
4316  *
4317  */
4318 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4319 {
4320         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4321         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4322         if (adapter->num_vfs)
4323                 return true;
4324         else
4325                 return false;
4326 }
4327
4328 /**
4329  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4330  * @adapter: board private structure to initialize
4331  *
4332  * Once we know the feature-set enabled for the device, we'll cache
4333  * the register offset the descriptor ring is assigned to.
4334  *
4335  * Note, the order the various feature calls is important.  It must start with
4336  * the "most" features enabled at the same time, then trickle down to the
4337  * least amount of features turned on at once.
4338  **/
4339 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4340 {
4341         /* start with default case */
4342         adapter->rx_ring[0]->reg_idx = 0;
4343         adapter->tx_ring[0]->reg_idx = 0;
4344
4345         if (ixgbe_cache_ring_sriov(adapter))
4346                 return;
4347
4348 #ifdef IXGBE_FCOE
4349         if (ixgbe_cache_ring_fcoe(adapter))
4350                 return;
4351
4352 #endif /* IXGBE_FCOE */
4353 #ifdef CONFIG_IXGBE_DCB
4354         if (ixgbe_cache_ring_dcb(adapter))
4355                 return;
4356
4357 #endif
4358         if (ixgbe_cache_ring_fdir(adapter))
4359                 return;
4360
4361         if (ixgbe_cache_ring_rss(adapter))
4362                 return;
4363 }
4364
4365 /**
4366  * ixgbe_alloc_queues - Allocate memory for all rings
4367  * @adapter: board private structure to initialize
4368  *
4369  * We allocate one ring per queue at run-time since we don't know the
4370  * number of queues at compile-time.  The polling_netdev array is
4371  * intended for Multiqueue, but should work fine with a single queue.
4372  **/
4373 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4374 {
4375         int i;
4376         int orig_node = adapter->node;
4377
4378         for (i = 0; i < adapter->num_tx_queues; i++) {
4379                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4380                 if (orig_node == -1) {
4381                         int cur_node = next_online_node(adapter->node);
4382                         if (cur_node == MAX_NUMNODES)
4383                                 cur_node = first_online_node;
4384                         adapter->node = cur_node;
4385                 }
4386                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4387                                     adapter->node);
4388                 if (!ring)
4389                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4390                 if (!ring)
4391                         goto err_tx_ring_allocation;
4392                 ring->count = adapter->tx_ring_count;
4393                 ring->queue_index = i;
4394                 ring->numa_node = adapter->node;
4395
4396                 adapter->tx_ring[i] = ring;
4397         }
4398
4399         /* Restore the adapter's original node */
4400         adapter->node = orig_node;
4401
4402         for (i = 0; i < adapter->num_rx_queues; i++) {
4403                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4404                 if (orig_node == -1) {
4405                         int cur_node = next_online_node(adapter->node);
4406                         if (cur_node == MAX_NUMNODES)
4407                                 cur_node = first_online_node;
4408                         adapter->node = cur_node;
4409                 }
4410                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4411                                     adapter->node);
4412                 if (!ring)
4413                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4414                 if (!ring)
4415                         goto err_rx_ring_allocation;
4416                 ring->count = adapter->rx_ring_count;
4417                 ring->queue_index = i;
4418                 ring->numa_node = adapter->node;
4419
4420                 adapter->rx_ring[i] = ring;
4421         }
4422
4423         /* Restore the adapter's original node */
4424         adapter->node = orig_node;
4425
4426         ixgbe_cache_ring_register(adapter);
4427
4428         return 0;
4429
4430 err_rx_ring_allocation:
4431         for (i = 0; i < adapter->num_tx_queues; i++)
4432                 kfree(adapter->tx_ring[i]);
4433 err_tx_ring_allocation:
4434         return -ENOMEM;
4435 }
4436
4437 /**
4438  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4439  * @adapter: board private structure to initialize
4440  *
4441  * Attempt to configure the interrupts using the best available
4442  * capabilities of the hardware and the kernel.
4443  **/
4444 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4445 {
4446         struct ixgbe_hw *hw = &adapter->hw;
4447         int err = 0;
4448         int vector, v_budget;
4449
4450         /*
4451          * It's easy to be greedy for MSI-X vectors, but it really
4452          * doesn't do us much good if we have a lot more vectors
4453          * than CPU's.  So let's be conservative and only ask for
4454          * (roughly) the same number of vectors as there are CPU's.
4455          */
4456         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4457                        (int)num_online_cpus()) + NON_Q_VECTORS;
4458
4459         /*
4460          * At the same time, hardware can only support a maximum of
4461          * hw.mac->max_msix_vectors vectors.  With features
4462          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4463          * descriptor queues supported by our device.  Thus, we cap it off in
4464          * those rare cases where the cpu count also exceeds our vector limit.
4465          */
4466         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4467
4468         /* A failure in MSI-X entry allocation isn't fatal, but it does
4469          * mean we disable MSI-X capabilities of the adapter. */
4470         adapter->msix_entries = kcalloc(v_budget,
4471                                         sizeof(struct msix_entry), GFP_KERNEL);
4472         if (adapter->msix_entries) {
4473                 for (vector = 0; vector < v_budget; vector++)
4474                         adapter->msix_entries[vector].entry = vector;
4475
4476                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4477
4478                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4479                         goto out;
4480         }
4481
4482         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4483         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4484         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4485         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4486         adapter->atr_sample_rate = 0;
4487         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4488                 ixgbe_disable_sriov(adapter);
4489
4490         ixgbe_set_num_queues(adapter);
4491
4492         err = pci_enable_msi(adapter->pdev);
4493         if (!err) {
4494                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4495         } else {
4496                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4497                              "Unable to allocate MSI interrupt, "
4498                              "falling back to legacy.  Error: %d\n", err);
4499                 /* reset err */
4500                 err = 0;
4501         }
4502
4503 out:
4504         return err;
4505 }
4506
4507 /**
4508  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4509  * @adapter: board private structure to initialize
4510  *
4511  * We allocate one q_vector per queue interrupt.  If allocation fails we
4512  * return -ENOMEM.
4513  **/
4514 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4515 {
4516         int q_idx, num_q_vectors;
4517         struct ixgbe_q_vector *q_vector;
4518         int napi_vectors;
4519         int (*poll)(struct napi_struct *, int);
4520
4521         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4522                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4523                 napi_vectors = adapter->num_rx_queues;
4524                 poll = &ixgbe_clean_rxtx_many;
4525         } else {
4526                 num_q_vectors = 1;
4527                 napi_vectors = 1;
4528                 poll = &ixgbe_poll;
4529         }
4530
4531         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4532                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4533                                         GFP_KERNEL, adapter->node);
4534                 if (!q_vector)
4535                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4536                                            GFP_KERNEL);
4537                 if (!q_vector)
4538                         goto err_out;
4539                 q_vector->adapter = adapter;
4540                 if (q_vector->txr_count && !q_vector->rxr_count)
4541                         q_vector->eitr = adapter->tx_eitr_param;
4542                 else
4543                         q_vector->eitr = adapter->rx_eitr_param;
4544                 q_vector->v_idx = q_idx;
4545                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4546                 adapter->q_vector[q_idx] = q_vector;
4547         }
4548
4549         return 0;
4550
4551 err_out:
4552         while (q_idx) {
4553                 q_idx--;
4554                 q_vector = adapter->q_vector[q_idx];
4555                 netif_napi_del(&q_vector->napi);
4556                 kfree(q_vector);
4557                 adapter->q_vector[q_idx] = NULL;
4558         }
4559         return -ENOMEM;
4560 }
4561
4562 /**
4563  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4564  * @adapter: board private structure to initialize
4565  *
4566  * This function frees the memory allocated to the q_vectors.  In addition if
4567  * NAPI is enabled it will delete any references to the NAPI struct prior
4568  * to freeing the q_vector.
4569  **/
4570 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4571 {
4572         int q_idx, num_q_vectors;
4573
4574         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4575                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4576         else
4577                 num_q_vectors = 1;
4578
4579         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4580                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4581                 adapter->q_vector[q_idx] = NULL;
4582                 netif_napi_del(&q_vector->napi);
4583                 kfree(q_vector);
4584         }
4585 }
4586
4587 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4588 {
4589         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4590                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4591                 pci_disable_msix(adapter->pdev);
4592                 kfree(adapter->msix_entries);
4593                 adapter->msix_entries = NULL;
4594         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4595                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4596                 pci_disable_msi(adapter->pdev);
4597         }
4598 }
4599
4600 /**
4601  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4602  * @adapter: board private structure to initialize
4603  *
4604  * We determine which interrupt scheme to use based on...
4605  * - Kernel support (MSI, MSI-X)
4606  *   - which can be user-defined (via MODULE_PARAM)
4607  * - Hardware queue count (num_*_queues)
4608  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4609  **/
4610 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4611 {
4612         int err;
4613
4614         /* Number of supported queues */
4615         ixgbe_set_num_queues(adapter);
4616
4617         err = ixgbe_set_interrupt_capability(adapter);
4618         if (err) {
4619                 e_dev_err("Unable to setup interrupt capabilities\n");
4620                 goto err_set_interrupt;
4621         }
4622
4623         err = ixgbe_alloc_q_vectors(adapter);
4624         if (err) {
4625                 e_dev_err("Unable to allocate memory for queue vectors\n");
4626                 goto err_alloc_q_vectors;
4627         }
4628
4629         err = ixgbe_alloc_queues(adapter);
4630         if (err) {
4631                 e_dev_err("Unable to allocate memory for queues\n");
4632                 goto err_alloc_queues;
4633         }
4634
4635         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4636                (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4637                adapter->num_rx_queues, adapter->num_tx_queues);
4638
4639         set_bit(__IXGBE_DOWN, &adapter->state);
4640
4641         return 0;
4642
4643 err_alloc_queues:
4644         ixgbe_free_q_vectors(adapter);
4645 err_alloc_q_vectors:
4646         ixgbe_reset_interrupt_capability(adapter);
4647 err_set_interrupt:
4648         return err;
4649 }
4650
4651 /**
4652  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4653  * @adapter: board private structure to clear interrupt scheme on
4654  *
4655  * We go through and clear interrupt specific resources and reset the structure
4656  * to pre-load conditions
4657  **/
4658 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4659 {
4660         int i;
4661
4662         for (i = 0; i < adapter->num_tx_queues; i++) {
4663                 kfree(adapter->tx_ring[i]);
4664                 adapter->tx_ring[i] = NULL;
4665         }
4666         for (i = 0; i < adapter->num_rx_queues; i++) {
4667                 kfree(adapter->rx_ring[i]);
4668                 adapter->rx_ring[i] = NULL;
4669         }
4670
4671         ixgbe_free_q_vectors(adapter);
4672         ixgbe_reset_interrupt_capability(adapter);
4673 }
4674
4675 /**
4676  * ixgbe_sfp_timer - worker thread to find a missing module
4677  * @data: pointer to our adapter struct
4678  **/
4679 static void ixgbe_sfp_timer(unsigned long data)
4680 {
4681         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4682
4683         /*
4684          * Do the sfp_timer outside of interrupt context due to the
4685          * delays that sfp+ detection requires
4686          */
4687         schedule_work(&adapter->sfp_task);
4688 }
4689
4690 /**
4691  * ixgbe_sfp_task - worker thread to find a missing module
4692  * @work: pointer to work_struct containing our data
4693  **/
4694 static void ixgbe_sfp_task(struct work_struct *work)
4695 {
4696         struct ixgbe_adapter *adapter = container_of(work,
4697                                                      struct ixgbe_adapter,
4698                                                      sfp_task);
4699         struct ixgbe_hw *hw = &adapter->hw;
4700
4701         if ((hw->phy.type == ixgbe_phy_nl) &&
4702             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4703                 s32 ret = hw->phy.ops.identify_sfp(hw);
4704                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4705                         goto reschedule;
4706                 ret = hw->phy.ops.reset(hw);
4707                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4708                         e_dev_err("failed to initialize because an unsupported "
4709                                   "SFP+ module type was detected.\n");
4710                         e_dev_err("Reload the driver after installing a "
4711                                   "supported module.\n");
4712                         unregister_netdev(adapter->netdev);
4713                 } else {
4714                         e_info("detected SFP+: %d\n", hw->phy.sfp_type);
4715                 }
4716                 /* don't need this routine any more */
4717                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4718         }
4719         return;
4720 reschedule:
4721         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4722                 mod_timer(&adapter->sfp_timer,
4723                           round_jiffies(jiffies + (2 * HZ)));
4724 }
4725
4726 /**
4727  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4728  * @adapter: board private structure to initialize
4729  *
4730  * ixgbe_sw_init initializes the Adapter private data structure.
4731  * Fields are initialized based on PCI device information and
4732  * OS network device settings (MTU size).
4733  **/
4734 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4735 {
4736         struct ixgbe_hw *hw = &adapter->hw;
4737         struct pci_dev *pdev = adapter->pdev;
4738         struct net_device *dev = adapter->netdev;
4739         unsigned int rss;
4740 #ifdef CONFIG_IXGBE_DCB
4741         int j;
4742         struct tc_configuration *tc;
4743 #endif
4744
4745         /* PCI config space info */
4746
4747         hw->vendor_id = pdev->vendor;
4748         hw->device_id = pdev->device;
4749         hw->revision_id = pdev->revision;
4750         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4751         hw->subsystem_device_id = pdev->subsystem_device;
4752
4753         /* Set capability flags */
4754         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4755         adapter->ring_feature[RING_F_RSS].indices = rss;
4756         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4757         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4758         if (hw->mac.type == ixgbe_mac_82598EB) {
4759                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4760                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4761                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4762         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4763                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4764                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4765                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4766                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4767                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4768                 if (dev->features & NETIF_F_NTUPLE) {
4769                         /* Flow Director perfect filter enabled */
4770                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4771                         adapter->atr_sample_rate = 0;
4772                         spin_lock_init(&adapter->fdir_perfect_lock);
4773                 } else {
4774                         /* Flow Director hash filters enabled */
4775                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4776                         adapter->atr_sample_rate = 20;
4777                 }
4778                 adapter->ring_feature[RING_F_FDIR].indices =
4779                                                          IXGBE_MAX_FDIR_INDICES;
4780                 adapter->fdir_pballoc = 0;
4781 #ifdef IXGBE_FCOE
4782                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4783                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4784                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4785 #ifdef CONFIG_IXGBE_DCB
4786                 /* Default traffic class to use for FCoE */
4787                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4788 #endif
4789 #endif /* IXGBE_FCOE */
4790         }
4791
4792 #ifdef CONFIG_IXGBE_DCB
4793         /* Configure DCB traffic classes */
4794         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4795                 tc = &adapter->dcb_cfg.tc_config[j];
4796                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4797                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4798                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4799                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4800                 tc->dcb_pfc = pfc_disabled;
4801         }
4802         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4803         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4804         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4805         adapter->dcb_cfg.pfc_mode_enable = false;
4806         adapter->dcb_cfg.round_robin_enable = false;
4807         adapter->dcb_set_bitmap = 0x00;
4808         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4809                            adapter->ring_feature[RING_F_DCB].indices);
4810
4811 #endif
4812
4813         /* default flow control settings */
4814         hw->fc.requested_mode = ixgbe_fc_full;
4815         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4816 #ifdef CONFIG_DCB
4817         adapter->last_lfc_mode = hw->fc.current_mode;
4818 #endif
4819         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4820         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4821         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4822         hw->fc.send_xon = true;
4823         hw->fc.disable_fc_autoneg = false;
4824
4825         /* enable itr by default in dynamic mode */
4826         adapter->rx_itr_setting = 1;
4827         adapter->rx_eitr_param = 20000;
4828         adapter->tx_itr_setting = 1;
4829         adapter->tx_eitr_param = 10000;
4830
4831         /* set defaults for eitr in MegaBytes */
4832         adapter->eitr_low = 10;
4833         adapter->eitr_high = 20;
4834
4835         /* set default ring sizes */
4836         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4837         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4838
4839         /* initialize eeprom parameters */
4840         if (ixgbe_init_eeprom_params_generic(hw)) {
4841                 e_dev_err("EEPROM initialization failed\n");
4842                 return -EIO;
4843         }
4844
4845         /* enable rx csum by default */
4846         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4847
4848         /* get assigned NUMA node */
4849         adapter->node = dev_to_node(&pdev->dev);
4850
4851         set_bit(__IXGBE_DOWN, &adapter->state);
4852
4853         return 0;
4854 }
4855
4856 /**
4857  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4858  * @adapter: board private structure
4859  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4860  *
4861  * Return 0 on success, negative on failure
4862  **/
4863 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4864                              struct ixgbe_ring *tx_ring)
4865 {
4866         struct pci_dev *pdev = adapter->pdev;
4867         int size;
4868
4869         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4870         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4871         if (!tx_ring->tx_buffer_info)
4872                 tx_ring->tx_buffer_info = vmalloc(size);
4873         if (!tx_ring->tx_buffer_info)
4874                 goto err;
4875         memset(tx_ring->tx_buffer_info, 0, size);
4876
4877         /* round up to nearest 4K */
4878         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4879         tx_ring->size = ALIGN(tx_ring->size, 4096);
4880
4881         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4882                                            &tx_ring->dma, GFP_KERNEL);
4883         if (!tx_ring->desc)
4884                 goto err;
4885
4886         tx_ring->next_to_use = 0;
4887         tx_ring->next_to_clean = 0;
4888         tx_ring->work_limit = tx_ring->count;
4889         return 0;
4890
4891 err:
4892         vfree(tx_ring->tx_buffer_info);
4893         tx_ring->tx_buffer_info = NULL;
4894         e_err("Unable to allocate memory for the Tx descriptor ring\n");
4895         return -ENOMEM;
4896 }
4897
4898 /**
4899  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4900  * @adapter: board private structure
4901  *
4902  * If this function returns with an error, then it's possible one or
4903  * more of the rings is populated (while the rest are not).  It is the
4904  * callers duty to clean those orphaned rings.
4905  *
4906  * Return 0 on success, negative on failure
4907  **/
4908 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4909 {
4910         int i, err = 0;
4911
4912         for (i = 0; i < adapter->num_tx_queues; i++) {
4913                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4914                 if (!err)
4915                         continue;
4916                 e_err("Allocation for Tx Queue %u failed\n", i);
4917                 break;
4918         }
4919
4920         return err;
4921 }
4922
4923 /**
4924  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4925  * @adapter: board private structure
4926  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4927  *
4928  * Returns 0 on success, negative on failure
4929  **/
4930 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4931                              struct ixgbe_ring *rx_ring)
4932 {
4933         struct pci_dev *pdev = adapter->pdev;
4934         int size;
4935
4936         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4937         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4938         if (!rx_ring->rx_buffer_info)
4939                 rx_ring->rx_buffer_info = vmalloc(size);
4940         if (!rx_ring->rx_buffer_info) {
4941                 e_err("vmalloc allocation failed for the Rx desc ring\n");
4942                 goto alloc_failed;
4943         }
4944         memset(rx_ring->rx_buffer_info, 0, size);
4945
4946         /* Round up to nearest 4K */
4947         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4948         rx_ring->size = ALIGN(rx_ring->size, 4096);
4949
4950         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4951                                            &rx_ring->dma, GFP_KERNEL);
4952
4953         if (!rx_ring->desc) {
4954                 e_err("Memory allocation failed for the Rx desc ring\n");
4955                 vfree(rx_ring->rx_buffer_info);
4956                 goto alloc_failed;
4957         }
4958
4959         rx_ring->next_to_clean = 0;
4960         rx_ring->next_to_use = 0;
4961
4962         return 0;
4963
4964 alloc_failed:
4965         return -ENOMEM;
4966 }
4967
4968 /**
4969  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4970  * @adapter: board private structure
4971  *
4972  * If this function returns with an error, then it's possible one or
4973  * more of the rings is populated (while the rest are not).  It is the
4974  * callers duty to clean those orphaned rings.
4975  *
4976  * Return 0 on success, negative on failure
4977  **/
4978
4979 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4980 {
4981         int i, err = 0;
4982
4983         for (i = 0; i < adapter->num_rx_queues; i++) {
4984                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4985                 if (!err)
4986                         continue;
4987                 e_err("Allocation for Rx Queue %u failed\n", i);
4988                 break;
4989         }
4990
4991         return err;
4992 }
4993
4994 /**
4995  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4996  * @adapter: board private structure
4997  * @tx_ring: Tx descriptor ring for a specific queue
4998  *
4999  * Free all transmit software resources
5000  **/
5001 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5002                              struct ixgbe_ring *tx_ring)
5003 {
5004         struct pci_dev *pdev = adapter->pdev;
5005
5006         ixgbe_clean_tx_ring(adapter, tx_ring);
5007
5008         vfree(tx_ring->tx_buffer_info);
5009         tx_ring->tx_buffer_info = NULL;
5010
5011         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5012                           tx_ring->dma);
5013
5014         tx_ring->desc = NULL;
5015 }
5016
5017 /**
5018  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5019  * @adapter: board private structure
5020  *
5021  * Free all transmit software resources
5022  **/
5023 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5024 {
5025         int i;
5026
5027         for (i = 0; i < adapter->num_tx_queues; i++)
5028                 if (adapter->tx_ring[i]->desc)
5029                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5030 }
5031
5032 /**
5033  * ixgbe_free_rx_resources - Free Rx Resources
5034  * @adapter: board private structure
5035  * @rx_ring: ring to clean the resources from
5036  *
5037  * Free all receive software resources
5038  **/
5039 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5040                              struct ixgbe_ring *rx_ring)
5041 {
5042         struct pci_dev *pdev = adapter->pdev;
5043
5044         ixgbe_clean_rx_ring(adapter, rx_ring);
5045
5046         vfree(rx_ring->rx_buffer_info);
5047         rx_ring->rx_buffer_info = NULL;
5048
5049         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5050                           rx_ring->dma);
5051
5052         rx_ring->desc = NULL;
5053 }
5054
5055 /**
5056  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5057  * @adapter: board private structure
5058  *
5059  * Free all receive software resources
5060  **/
5061 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5062 {
5063         int i;
5064
5065         for (i = 0; i < adapter->num_rx_queues; i++)
5066                 if (adapter->rx_ring[i]->desc)
5067                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5068 }
5069
5070 /**
5071  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5072  * @netdev: network interface device structure
5073  * @new_mtu: new value for maximum frame size
5074  *
5075  * Returns 0 on success, negative on failure
5076  **/
5077 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5078 {
5079         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5080         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5081
5082         /* MTU < 68 is an error and causes problems on some kernels */
5083         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5084                 return -EINVAL;
5085
5086         e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5087         /* must set new MTU before calling down or up */
5088         netdev->mtu = new_mtu;
5089
5090         if (netif_running(netdev))
5091                 ixgbe_reinit_locked(adapter);
5092
5093         return 0;
5094 }
5095
5096 /**
5097  * ixgbe_open - Called when a network interface is made active
5098  * @netdev: network interface device structure
5099  *
5100  * Returns 0 on success, negative value on failure
5101  *
5102  * The open entry point is called when a network interface is made
5103  * active by the system (IFF_UP).  At this point all resources needed
5104  * for transmit and receive operations are allocated, the interrupt
5105  * handler is registered with the OS, the watchdog timer is started,
5106  * and the stack is notified that the interface is ready.
5107  **/
5108 static int ixgbe_open(struct net_device *netdev)
5109 {
5110         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5111         int err;
5112
5113         /* disallow open during test */
5114         if (test_bit(__IXGBE_TESTING, &adapter->state))
5115                 return -EBUSY;
5116
5117         netif_carrier_off(netdev);
5118
5119         /* allocate transmit descriptors */
5120         err = ixgbe_setup_all_tx_resources(adapter);
5121         if (err)
5122                 goto err_setup_tx;
5123
5124         /* allocate receive descriptors */
5125         err = ixgbe_setup_all_rx_resources(adapter);
5126         if (err)
5127                 goto err_setup_rx;
5128
5129         ixgbe_configure(adapter);
5130
5131         err = ixgbe_request_irq(adapter);
5132         if (err)
5133                 goto err_req_irq;
5134
5135         err = ixgbe_up_complete(adapter);
5136         if (err)
5137                 goto err_up;
5138
5139         netif_tx_start_all_queues(netdev);
5140
5141         return 0;
5142
5143 err_up:
5144         ixgbe_release_hw_control(adapter);
5145         ixgbe_free_irq(adapter);
5146 err_req_irq:
5147 err_setup_rx:
5148         ixgbe_free_all_rx_resources(adapter);
5149 err_setup_tx:
5150         ixgbe_free_all_tx_resources(adapter);
5151         ixgbe_reset(adapter);
5152
5153         return err;
5154 }
5155
5156 /**
5157  * ixgbe_close - Disables a network interface
5158  * @netdev: network interface device structure
5159  *
5160  * Returns 0, this is not allowed to fail
5161  *
5162  * The close entry point is called when an interface is de-activated
5163  * by the OS.  The hardware is still under the drivers control, but
5164  * needs to be disabled.  A global MAC reset is issued to stop the
5165  * hardware, and all transmit and receive resources are freed.
5166  **/
5167 static int ixgbe_close(struct net_device *netdev)
5168 {
5169         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5170
5171         ixgbe_down(adapter);
5172         ixgbe_free_irq(adapter);
5173
5174         ixgbe_free_all_tx_resources(adapter);
5175         ixgbe_free_all_rx_resources(adapter);
5176
5177         ixgbe_release_hw_control(adapter);
5178
5179         return 0;
5180 }
5181
5182 #ifdef CONFIG_PM
5183 static int ixgbe_resume(struct pci_dev *pdev)
5184 {
5185         struct net_device *netdev = pci_get_drvdata(pdev);
5186         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5187         u32 err;
5188
5189         pci_set_power_state(pdev, PCI_D0);
5190         pci_restore_state(pdev);
5191         /*
5192          * pci_restore_state clears dev->state_saved so call
5193          * pci_save_state to restore it.
5194          */
5195         pci_save_state(pdev);
5196
5197         err = pci_enable_device_mem(pdev);
5198         if (err) {
5199                 e_dev_err("Cannot enable PCI device from suspend\n");
5200                 return err;
5201         }
5202         pci_set_master(pdev);
5203
5204         pci_wake_from_d3(pdev, false);
5205
5206         err = ixgbe_init_interrupt_scheme(adapter);
5207         if (err) {
5208                 e_dev_err("Cannot initialize interrupts for device\n");
5209                 return err;
5210         }
5211
5212         ixgbe_reset(adapter);
5213
5214         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5215
5216         if (netif_running(netdev)) {
5217                 err = ixgbe_open(adapter->netdev);
5218                 if (err)
5219                         return err;
5220         }
5221
5222         netif_device_attach(netdev);
5223
5224         return 0;
5225 }
5226 #endif /* CONFIG_PM */
5227
5228 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5229 {
5230         struct net_device *netdev = pci_get_drvdata(pdev);
5231         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5232         struct ixgbe_hw *hw = &adapter->hw;
5233         u32 ctrl, fctrl;
5234         u32 wufc = adapter->wol;
5235 #ifdef CONFIG_PM
5236         int retval = 0;
5237 #endif
5238
5239         netif_device_detach(netdev);
5240
5241         if (netif_running(netdev)) {
5242                 ixgbe_down(adapter);
5243                 ixgbe_free_irq(adapter);
5244                 ixgbe_free_all_tx_resources(adapter);
5245                 ixgbe_free_all_rx_resources(adapter);
5246         }
5247         ixgbe_clear_interrupt_scheme(adapter);
5248
5249 #ifdef CONFIG_PM
5250         retval = pci_save_state(pdev);
5251         if (retval)
5252                 return retval;
5253
5254 #endif
5255         if (wufc) {
5256                 ixgbe_set_rx_mode(netdev);
5257
5258                 /* turn on all-multi mode if wake on multicast is enabled */
5259                 if (wufc & IXGBE_WUFC_MC) {
5260                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5261                         fctrl |= IXGBE_FCTRL_MPE;
5262                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5263                 }
5264
5265                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5266                 ctrl |= IXGBE_CTRL_GIO_DIS;
5267                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5268
5269                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5270         } else {
5271                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5272                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5273         }
5274
5275         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5276                 pci_wake_from_d3(pdev, true);
5277         else
5278                 pci_wake_from_d3(pdev, false);
5279
5280         *enable_wake = !!wufc;
5281
5282         ixgbe_release_hw_control(adapter);
5283
5284         pci_disable_device(pdev);
5285
5286         return 0;
5287 }
5288
5289 #ifdef CONFIG_PM
5290 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5291 {
5292         int retval;
5293         bool wake;
5294
5295         retval = __ixgbe_shutdown(pdev, &wake);
5296         if (retval)
5297                 return retval;
5298
5299         if (wake) {
5300                 pci_prepare_to_sleep(pdev);
5301         } else {
5302                 pci_wake_from_d3(pdev, false);
5303                 pci_set_power_state(pdev, PCI_D3hot);
5304         }
5305
5306         return 0;
5307 }
5308 #endif /* CONFIG_PM */
5309
5310 static void ixgbe_shutdown(struct pci_dev *pdev)
5311 {
5312         bool wake;
5313
5314         __ixgbe_shutdown(pdev, &wake);
5315
5316         if (system_state == SYSTEM_POWER_OFF) {
5317                 pci_wake_from_d3(pdev, wake);
5318                 pci_set_power_state(pdev, PCI_D3hot);
5319         }
5320 }
5321
5322 /**
5323  * ixgbe_update_stats - Update the board statistics counters.
5324  * @adapter: board private structure
5325  **/
5326 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5327 {
5328         struct net_device *netdev = adapter->netdev;
5329         struct ixgbe_hw *hw = &adapter->hw;
5330         u64 total_mpc = 0;
5331         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5332         u64 non_eop_descs = 0, restart_queue = 0;
5333
5334         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5335             test_bit(__IXGBE_RESETTING, &adapter->state))
5336                 return;
5337
5338         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5339                 u64 rsc_count = 0;
5340                 u64 rsc_flush = 0;
5341                 for (i = 0; i < 16; i++)
5342                         adapter->hw_rx_no_dma_resources +=
5343                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5344                 for (i = 0; i < adapter->num_rx_queues; i++) {
5345                         rsc_count += adapter->rx_ring[i]->rsc_count;
5346                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5347                 }
5348                 adapter->rsc_total_count = rsc_count;
5349                 adapter->rsc_total_flush = rsc_flush;
5350         }
5351
5352         /* gather some stats to the adapter struct that are per queue */
5353         for (i = 0; i < adapter->num_tx_queues; i++)
5354                 restart_queue += adapter->tx_ring[i]->restart_queue;
5355         adapter->restart_queue = restart_queue;
5356
5357         for (i = 0; i < adapter->num_rx_queues; i++)
5358                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5359         adapter->non_eop_descs = non_eop_descs;
5360
5361         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5362         for (i = 0; i < 8; i++) {
5363                 /* for packet buffers not used, the register should read 0 */
5364                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5365                 missed_rx += mpc;
5366                 adapter->stats.mpc[i] += mpc;
5367                 total_mpc += adapter->stats.mpc[i];
5368                 if (hw->mac.type == ixgbe_mac_82598EB)
5369                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5370                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5371                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5372                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5373                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5374                 if (hw->mac.type == ixgbe_mac_82599EB) {
5375                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5376                                                             IXGBE_PXONRXCNT(i));
5377                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5378                                                            IXGBE_PXOFFRXCNT(i));
5379                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5380                 } else {
5381                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5382                                                               IXGBE_PXONRXC(i));
5383                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5384                                                              IXGBE_PXOFFRXC(i));
5385                 }
5386                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5387                                                             IXGBE_PXONTXC(i));
5388                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5389                                                              IXGBE_PXOFFTXC(i));
5390         }
5391         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5392         /* work around hardware counting issue */
5393         adapter->stats.gprc -= missed_rx;
5394
5395         /* 82598 hardware only has a 32 bit counter in the high register */
5396         if (hw->mac.type == ixgbe_mac_82599EB) {
5397                 u64 tmp;
5398                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5399                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5400                 adapter->stats.gorc += (tmp << 32);
5401                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5402                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5403                 adapter->stats.gotc += (tmp << 32);
5404                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5405                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5406                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5407                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5408                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5409                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5410 #ifdef IXGBE_FCOE
5411                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5412                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5413                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5414                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5415                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5416                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5417 #endif /* IXGBE_FCOE */
5418         } else {
5419                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5420                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5421                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5422                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5423                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5424         }
5425         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5426         adapter->stats.bprc += bprc;
5427         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5428         if (hw->mac.type == ixgbe_mac_82598EB)
5429                 adapter->stats.mprc -= bprc;
5430         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5431         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5432         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5433         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5434         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5435         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5436         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5437         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5438         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5439         adapter->stats.lxontxc += lxon;
5440         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5441         adapter->stats.lxofftxc += lxoff;
5442         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5443         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5444         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5445         /*
5446          * 82598 errata - tx of flow control packets is included in tx counters
5447          */
5448         xon_off_tot = lxon + lxoff;
5449         adapter->stats.gptc -= xon_off_tot;
5450         adapter->stats.mptc -= xon_off_tot;
5451         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5452         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5453         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5454         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5455         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5456         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5457         adapter->stats.ptc64 -= xon_off_tot;
5458         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5459         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5460         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5461         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5462         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5463         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5464
5465         /* Fill out the OS statistics structure */
5466         netdev->stats.multicast = adapter->stats.mprc;
5467
5468         /* Rx Errors */
5469         netdev->stats.rx_errors = adapter->stats.crcerrs +
5470                                        adapter->stats.rlec;
5471         netdev->stats.rx_dropped = 0;
5472         netdev->stats.rx_length_errors = adapter->stats.rlec;
5473         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5474         netdev->stats.rx_missed_errors = total_mpc;
5475 }
5476
5477 /**
5478  * ixgbe_watchdog - Timer Call-back
5479  * @data: pointer to adapter cast into an unsigned long
5480  **/
5481 static void ixgbe_watchdog(unsigned long data)
5482 {
5483         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5484         struct ixgbe_hw *hw = &adapter->hw;
5485         u64 eics = 0;
5486         int i;
5487
5488         /*
5489          *  Do the watchdog outside of interrupt context due to the lovely
5490          * delays that some of the newer hardware requires
5491          */
5492
5493         if (test_bit(__IXGBE_DOWN, &adapter->state))
5494                 goto watchdog_short_circuit;
5495
5496         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5497                 /*
5498                  * for legacy and MSI interrupts don't set any bits
5499                  * that are enabled for EIAM, because this operation
5500                  * would set *both* EIMS and EICS for any bit in EIAM
5501                  */
5502                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5503                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5504                 goto watchdog_reschedule;
5505         }
5506
5507         /* get one bit for every active tx/rx interrupt vector */
5508         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5509                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5510                 if (qv->rxr_count || qv->txr_count)
5511                         eics |= ((u64)1 << i);
5512         }
5513
5514         /* Cause software interrupt to ensure rx rings are cleaned */
5515         ixgbe_irq_rearm_queues(adapter, eics);
5516
5517 watchdog_reschedule:
5518         /* Reset the timer */
5519         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5520
5521 watchdog_short_circuit:
5522         schedule_work(&adapter->watchdog_task);
5523 }
5524
5525 /**
5526  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5527  * @work: pointer to work_struct containing our data
5528  **/
5529 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5530 {
5531         struct ixgbe_adapter *adapter = container_of(work,
5532                                                      struct ixgbe_adapter,
5533                                                      multispeed_fiber_task);
5534         struct ixgbe_hw *hw = &adapter->hw;
5535         u32 autoneg;
5536         bool negotiation;
5537
5538         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5539         autoneg = hw->phy.autoneg_advertised;
5540         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5541                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5542         hw->mac.autotry_restart = false;
5543         if (hw->mac.ops.setup_link)
5544                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5545         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5546         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5547 }
5548
5549 /**
5550  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5551  * @work: pointer to work_struct containing our data
5552  **/
5553 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5554 {
5555         struct ixgbe_adapter *adapter = container_of(work,
5556                                                      struct ixgbe_adapter,
5557                                                      sfp_config_module_task);
5558         struct ixgbe_hw *hw = &adapter->hw;
5559         u32 err;
5560
5561         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5562
5563         /* Time for electrical oscillations to settle down */
5564         msleep(100);
5565         err = hw->phy.ops.identify_sfp(hw);
5566
5567         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5568                 e_dev_err("failed to initialize because an unsupported SFP+ "
5569                           "module type was detected.\n");
5570                 e_dev_err("Reload the driver after installing a supported "
5571                           "module.\n");
5572                 unregister_netdev(adapter->netdev);
5573                 return;
5574         }
5575         hw->mac.ops.setup_sfp(hw);
5576
5577         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5578                 /* This will also work for DA Twinax connections */
5579                 schedule_work(&adapter->multispeed_fiber_task);
5580         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5581 }
5582
5583 /**
5584  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5585  * @work: pointer to work_struct containing our data
5586  **/
5587 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5588 {
5589         struct ixgbe_adapter *adapter = container_of(work,
5590                                                      struct ixgbe_adapter,
5591                                                      fdir_reinit_task);
5592         struct ixgbe_hw *hw = &adapter->hw;
5593         int i;
5594
5595         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5596                 for (i = 0; i < adapter->num_tx_queues; i++)
5597                         set_bit(__IXGBE_FDIR_INIT_DONE,
5598                                 &(adapter->tx_ring[i]->reinit_state));
5599         } else {
5600                 e_err("failed to finish FDIR re-initialization, "
5601                       "ignored adding FDIR ATR filters\n");
5602         }
5603         /* Done FDIR Re-initialization, enable transmits */
5604         netif_tx_start_all_queues(adapter->netdev);
5605 }
5606
5607 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5608
5609 /**
5610  * ixgbe_watchdog_task - worker thread to bring link up
5611  * @work: pointer to work_struct containing our data
5612  **/
5613 static void ixgbe_watchdog_task(struct work_struct *work)
5614 {
5615         struct ixgbe_adapter *adapter = container_of(work,
5616                                                      struct ixgbe_adapter,
5617                                                      watchdog_task);
5618         struct net_device *netdev = adapter->netdev;
5619         struct ixgbe_hw *hw = &adapter->hw;
5620         u32 link_speed;
5621         bool link_up;
5622         int i;
5623         struct ixgbe_ring *tx_ring;
5624         int some_tx_pending = 0;
5625
5626         mutex_lock(&ixgbe_watchdog_lock);
5627
5628         link_up = adapter->link_up;
5629         link_speed = adapter->link_speed;
5630
5631         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5632                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5633                 if (link_up) {
5634 #ifdef CONFIG_DCB
5635                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5636                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5637                                         hw->mac.ops.fc_enable(hw, i);
5638                         } else {
5639                                 hw->mac.ops.fc_enable(hw, 0);
5640                         }
5641 #else
5642                         hw->mac.ops.fc_enable(hw, 0);
5643 #endif
5644                 }
5645
5646                 if (link_up ||
5647                     time_after(jiffies, (adapter->link_check_timeout +
5648                                          IXGBE_TRY_LINK_TIMEOUT))) {
5649                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5650                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5651                 }
5652                 adapter->link_up = link_up;
5653                 adapter->link_speed = link_speed;
5654         }
5655
5656         if (link_up) {
5657                 if (!netif_carrier_ok(netdev)) {
5658                         bool flow_rx, flow_tx;
5659
5660                         if (hw->mac.type == ixgbe_mac_82599EB) {
5661                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5662                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5663                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5664                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5665                         } else {
5666                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5667                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5668                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5669                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5670                         }
5671
5672                         e_info("NIC Link is Up %s, Flow Control: %s\n",
5673                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5674                                "10 Gbps" :
5675                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5676                                "1 Gbps" : "unknown speed")),
5677                                ((flow_rx && flow_tx) ? "RX/TX" :
5678                                (flow_rx ? "RX" :
5679                                (flow_tx ? "TX" : "None"))));
5680
5681                         netif_carrier_on(netdev);
5682                 } else {
5683                         /* Force detection of hung controller */
5684                         adapter->detect_tx_hung = true;
5685                 }
5686         } else {
5687                 adapter->link_up = false;
5688                 adapter->link_speed = 0;
5689                 if (netif_carrier_ok(netdev)) {
5690                         e_info("NIC Link is Down\n");
5691                         netif_carrier_off(netdev);
5692                 }
5693         }
5694
5695         if (!netif_carrier_ok(netdev)) {
5696                 for (i = 0; i < adapter->num_tx_queues; i++) {
5697                         tx_ring = adapter->tx_ring[i];
5698                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5699                                 some_tx_pending = 1;
5700                                 break;
5701                         }
5702                 }
5703
5704                 if (some_tx_pending) {
5705                         /* We've lost link, so the controller stops DMA,
5706                          * but we've got queued Tx work that's never going
5707                          * to get done, so reset controller to flush Tx.
5708                          * (Do the reset outside of interrupt context).
5709                          */
5710                          schedule_work(&adapter->reset_task);
5711                 }
5712         }
5713
5714         ixgbe_update_stats(adapter);
5715         mutex_unlock(&ixgbe_watchdog_lock);
5716 }
5717
5718 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5719                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5720                      u32 tx_flags, u8 *hdr_len)
5721 {
5722         struct ixgbe_adv_tx_context_desc *context_desc;
5723         unsigned int i;
5724         int err;
5725         struct ixgbe_tx_buffer *tx_buffer_info;
5726         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5727         u32 mss_l4len_idx, l4len;
5728
5729         if (skb_is_gso(skb)) {
5730                 if (skb_header_cloned(skb)) {
5731                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5732                         if (err)
5733                                 return err;
5734                 }
5735                 l4len = tcp_hdrlen(skb);
5736                 *hdr_len += l4len;
5737
5738                 if (skb->protocol == htons(ETH_P_IP)) {
5739                         struct iphdr *iph = ip_hdr(skb);
5740                         iph->tot_len = 0;
5741                         iph->check = 0;
5742                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5743                                                                  iph->daddr, 0,
5744                                                                  IPPROTO_TCP,
5745                                                                  0);
5746                 } else if (skb_is_gso_v6(skb)) {
5747                         ipv6_hdr(skb)->payload_len = 0;
5748                         tcp_hdr(skb)->check =
5749                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5750                                              &ipv6_hdr(skb)->daddr,
5751                                              0, IPPROTO_TCP, 0);
5752                 }
5753
5754                 i = tx_ring->next_to_use;
5755
5756                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5757                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5758
5759                 /* VLAN MACLEN IPLEN */
5760                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5761                         vlan_macip_lens |=
5762                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5763                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5764                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5765                 *hdr_len += skb_network_offset(skb);
5766                 vlan_macip_lens |=
5767                     (skb_transport_header(skb) - skb_network_header(skb));
5768                 *hdr_len +=
5769                     (skb_transport_header(skb) - skb_network_header(skb));
5770                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5771                 context_desc->seqnum_seed = 0;
5772
5773                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5774                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5775                                    IXGBE_ADVTXD_DTYP_CTXT);
5776
5777                 if (skb->protocol == htons(ETH_P_IP))
5778                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5779                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5780                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5781
5782                 /* MSS L4LEN IDX */
5783                 mss_l4len_idx =
5784                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5785                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5786                 /* use index 1 for TSO */
5787                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5788                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5789
5790                 tx_buffer_info->time_stamp = jiffies;
5791                 tx_buffer_info->next_to_watch = i;
5792
5793                 i++;
5794                 if (i == tx_ring->count)
5795                         i = 0;
5796                 tx_ring->next_to_use = i;
5797
5798                 return true;
5799         }
5800         return false;
5801 }
5802
5803 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5804                           struct ixgbe_ring *tx_ring,
5805                           struct sk_buff *skb, u32 tx_flags)
5806 {
5807         struct ixgbe_adv_tx_context_desc *context_desc;
5808         unsigned int i;
5809         struct ixgbe_tx_buffer *tx_buffer_info;
5810         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5811
5812         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5813             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5814                 i = tx_ring->next_to_use;
5815                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5816                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5817
5818                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5819                         vlan_macip_lens |=
5820                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5821                 vlan_macip_lens |= (skb_network_offset(skb) <<
5822                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5823                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5824                         vlan_macip_lens |= (skb_transport_header(skb) -
5825                                             skb_network_header(skb));
5826
5827                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5828                 context_desc->seqnum_seed = 0;
5829
5830                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5831                                     IXGBE_ADVTXD_DTYP_CTXT);
5832
5833                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5834                         __be16 protocol;
5835
5836                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5837                                 const struct vlan_ethhdr *vhdr =
5838                                         (const struct vlan_ethhdr *)skb->data;
5839
5840                                 protocol = vhdr->h_vlan_encapsulated_proto;
5841                         } else {
5842                                 protocol = skb->protocol;
5843                         }
5844
5845                         switch (protocol) {
5846                         case cpu_to_be16(ETH_P_IP):
5847                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5848                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5849                                         type_tucmd_mlhl |=
5850                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5851                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5852                                         type_tucmd_mlhl |=
5853                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5854                                 break;
5855                         case cpu_to_be16(ETH_P_IPV6):
5856                                 /* XXX what about other V6 headers?? */
5857                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5858                                         type_tucmd_mlhl |=
5859                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5860                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5861                                         type_tucmd_mlhl |=
5862                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5863                                 break;
5864                         default:
5865                                 if (unlikely(net_ratelimit())) {
5866                                         e_warn("partial checksum but "
5867                                                "proto=%x!\n", skb->protocol);
5868                                 }
5869                                 break;
5870                         }
5871                 }
5872
5873                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5874                 /* use index zero for tx checksum offload */
5875                 context_desc->mss_l4len_idx = 0;
5876
5877                 tx_buffer_info->time_stamp = jiffies;
5878                 tx_buffer_info->next_to_watch = i;
5879
5880                 i++;
5881                 if (i == tx_ring->count)
5882                         i = 0;
5883                 tx_ring->next_to_use = i;
5884
5885                 return true;
5886         }
5887
5888         return false;
5889 }
5890
5891 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5892                         struct ixgbe_ring *tx_ring,
5893                         struct sk_buff *skb, u32 tx_flags,
5894                         unsigned int first)
5895 {
5896         struct pci_dev *pdev = adapter->pdev;
5897         struct ixgbe_tx_buffer *tx_buffer_info;
5898         unsigned int len;
5899         unsigned int total = skb->len;
5900         unsigned int offset = 0, size, count = 0, i;
5901         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5902         unsigned int f;
5903
5904         i = tx_ring->next_to_use;
5905
5906         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5907                 /* excluding fcoe_crc_eof for FCoE */
5908                 total -= sizeof(struct fcoe_crc_eof);
5909
5910         len = min(skb_headlen(skb), total);
5911         while (len) {
5912                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5913                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5914
5915                 tx_buffer_info->length = size;
5916                 tx_buffer_info->mapped_as_page = false;
5917                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5918                                                      skb->data + offset,
5919                                                      size, DMA_TO_DEVICE);
5920                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5921                         goto dma_error;
5922                 tx_buffer_info->time_stamp = jiffies;
5923                 tx_buffer_info->next_to_watch = i;
5924
5925                 len -= size;
5926                 total -= size;
5927                 offset += size;
5928                 count++;
5929
5930                 if (len) {
5931                         i++;
5932                         if (i == tx_ring->count)
5933                                 i = 0;
5934                 }
5935         }
5936
5937         for (f = 0; f < nr_frags; f++) {
5938                 struct skb_frag_struct *frag;
5939
5940                 frag = &skb_shinfo(skb)->frags[f];
5941                 len = min((unsigned int)frag->size, total);
5942                 offset = frag->page_offset;
5943
5944                 while (len) {
5945                         i++;
5946                         if (i == tx_ring->count)
5947                                 i = 0;
5948
5949                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5950                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5951
5952                         tx_buffer_info->length = size;
5953                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5954                                                            frag->page,
5955                                                            offset, size,
5956                                                            DMA_TO_DEVICE);
5957                         tx_buffer_info->mapped_as_page = true;
5958                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5959                                 goto dma_error;
5960                         tx_buffer_info->time_stamp = jiffies;
5961                         tx_buffer_info->next_to_watch = i;
5962
5963                         len -= size;
5964                         total -= size;
5965                         offset += size;
5966                         count++;
5967                 }
5968                 if (total == 0)
5969                         break;
5970         }
5971
5972         tx_ring->tx_buffer_info[i].skb = skb;
5973         tx_ring->tx_buffer_info[first].next_to_watch = i;
5974
5975         return count;
5976
5977 dma_error:
5978         e_dev_err("TX DMA map failed\n");
5979
5980         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5981         tx_buffer_info->dma = 0;
5982         tx_buffer_info->time_stamp = 0;
5983         tx_buffer_info->next_to_watch = 0;
5984         if (count)
5985                 count--;
5986
5987         /* clear timestamp and dma mappings for remaining portion of packet */
5988         while (count--) {
5989                 if (i==0)
5990                         i += tx_ring->count;
5991                 i--;
5992                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5993                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5994         }
5995
5996         return 0;
5997 }
5998
5999 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6000                            struct ixgbe_ring *tx_ring,
6001                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6002 {
6003         union ixgbe_adv_tx_desc *tx_desc = NULL;
6004         struct ixgbe_tx_buffer *tx_buffer_info;
6005         u32 olinfo_status = 0, cmd_type_len = 0;
6006         unsigned int i;
6007         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6008
6009         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6010
6011         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6012
6013         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6014                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6015
6016         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6017                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6018
6019                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6020                                  IXGBE_ADVTXD_POPTS_SHIFT;
6021
6022                 /* use index 1 context for tso */
6023                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6024                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6025                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6026                                          IXGBE_ADVTXD_POPTS_SHIFT;
6027
6028         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6029                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6030                                  IXGBE_ADVTXD_POPTS_SHIFT;
6031
6032         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6033                 olinfo_status |= IXGBE_ADVTXD_CC;
6034                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6035                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6036                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6037         }
6038
6039         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6040
6041         i = tx_ring->next_to_use;
6042         while (count--) {
6043                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6044                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6045                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6046                 tx_desc->read.cmd_type_len =
6047                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6048                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6049                 i++;
6050                 if (i == tx_ring->count)
6051                         i = 0;
6052         }
6053
6054         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6055
6056         /*
6057          * Force memory writes to complete before letting h/w
6058          * know there are new descriptors to fetch.  (Only
6059          * applicable for weak-ordered memory model archs,
6060          * such as IA-64).
6061          */
6062         wmb();
6063
6064         tx_ring->next_to_use = i;
6065         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6066 }
6067
6068 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6069                       int queue, u32 tx_flags)
6070 {
6071         /* Right now, we support IPv4 only */
6072         struct ixgbe_atr_input atr_input;
6073         struct tcphdr *th;
6074         struct iphdr *iph = ip_hdr(skb);
6075         struct ethhdr *eth = (struct ethhdr *)skb->data;
6076         u16 vlan_id, src_port, dst_port, flex_bytes;
6077         u32 src_ipv4_addr, dst_ipv4_addr;
6078         u8 l4type = 0;
6079
6080         /* check if we're UDP or TCP */
6081         if (iph->protocol == IPPROTO_TCP) {
6082                 th = tcp_hdr(skb);
6083                 src_port = th->source;
6084                 dst_port = th->dest;
6085                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6086                 /* l4type IPv4 type is 0, no need to assign */
6087         } else {
6088                 /* Unsupported L4 header, just bail here */
6089                 return;
6090         }
6091
6092         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6093
6094         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6095                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6096         src_ipv4_addr = iph->saddr;
6097         dst_ipv4_addr = iph->daddr;
6098         flex_bytes = eth->h_proto;
6099
6100         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6101         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6102         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6103         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6104         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6105         /* src and dst are inverted, think how the receiver sees them */
6106         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6107         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6108
6109         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6110         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6111 }
6112
6113 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6114                                  struct ixgbe_ring *tx_ring, int size)
6115 {
6116         netif_stop_subqueue(netdev, tx_ring->queue_index);
6117         /* Herbert's original patch had:
6118          *  smp_mb__after_netif_stop_queue();
6119          * but since that doesn't exist yet, just open code it. */
6120         smp_mb();
6121
6122         /* We need to check again in a case another CPU has just
6123          * made room available. */
6124         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6125                 return -EBUSY;
6126
6127         /* A reprieve! - use start_queue because it doesn't call schedule */
6128         netif_start_subqueue(netdev, tx_ring->queue_index);
6129         ++tx_ring->restart_queue;
6130         return 0;
6131 }
6132
6133 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6134                               struct ixgbe_ring *tx_ring, int size)
6135 {
6136         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6137                 return 0;
6138         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6139 }
6140
6141 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6142 {
6143         struct ixgbe_adapter *adapter = netdev_priv(dev);
6144         int txq = smp_processor_id();
6145
6146         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6147                 while (unlikely(txq >= dev->real_num_tx_queues))
6148                         txq -= dev->real_num_tx_queues;
6149                 return txq;
6150         }
6151
6152 #ifdef IXGBE_FCOE
6153         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
6154             ((skb->protocol == htons(ETH_P_FCOE)) ||
6155              (skb->protocol == htons(ETH_P_FIP)))) {
6156                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6157                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6158                 return txq;
6159         }
6160 #endif
6161         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6162                 if (skb->priority == TC_PRIO_CONTROL)
6163                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6164                 else
6165                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6166                                >> 13;
6167                 return txq;
6168         }
6169
6170         return skb_tx_hash(dev, skb);
6171 }
6172
6173 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6174                                     struct net_device *netdev)
6175 {
6176         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6177         struct ixgbe_ring *tx_ring;
6178         struct netdev_queue *txq;
6179         unsigned int first;
6180         unsigned int tx_flags = 0;
6181         u8 hdr_len = 0;
6182         int tso;
6183         int count = 0;
6184         unsigned int f;
6185
6186         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6187                 tx_flags |= vlan_tx_tag_get(skb);
6188                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6189                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6190                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6191                 }
6192                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6193                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6194         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6195                    skb->priority != TC_PRIO_CONTROL) {
6196                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6197                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6198                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6199         }
6200
6201         tx_ring = adapter->tx_ring[skb->queue_mapping];
6202
6203 #ifdef IXGBE_FCOE
6204         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6205 #ifdef CONFIG_IXGBE_DCB
6206                 /* for FCoE with DCB, we force the priority to what
6207                  * was specified by the switch */
6208                 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6209                     (skb->protocol == htons(ETH_P_FIP))) {
6210                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6211                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6212                         tx_flags |= ((adapter->fcoe.up << 13)
6213                                      << IXGBE_TX_FLAGS_VLAN_SHIFT);
6214                 }
6215 #endif
6216                 /* flag for FCoE offloads */
6217                 if (skb->protocol == htons(ETH_P_FCOE))
6218                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6219         }
6220 #endif
6221
6222         /* four things can cause us to need a context descriptor */
6223         if (skb_is_gso(skb) ||
6224             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6225             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6226             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6227                 count++;
6228
6229         count += TXD_USE_COUNT(skb_headlen(skb));
6230         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6231                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6232
6233         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6234                 adapter->tx_busy++;
6235                 return NETDEV_TX_BUSY;
6236         }
6237
6238         first = tx_ring->next_to_use;
6239         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6240 #ifdef IXGBE_FCOE
6241                 /* setup tx offload for FCoE */
6242                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6243                 if (tso < 0) {
6244                         dev_kfree_skb_any(skb);
6245                         return NETDEV_TX_OK;
6246                 }
6247                 if (tso)
6248                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6249 #endif /* IXGBE_FCOE */
6250         } else {
6251                 if (skb->protocol == htons(ETH_P_IP))
6252                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6253                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6254                 if (tso < 0) {
6255                         dev_kfree_skb_any(skb);
6256                         return NETDEV_TX_OK;
6257                 }
6258
6259                 if (tso)
6260                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6261                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6262                          (skb->ip_summed == CHECKSUM_PARTIAL))
6263                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6264         }
6265
6266         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6267         if (count) {
6268                 /* add the ATR filter if ATR is on */
6269                 if (tx_ring->atr_sample_rate) {
6270                         ++tx_ring->atr_count;
6271                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6272                              test_bit(__IXGBE_FDIR_INIT_DONE,
6273                                       &tx_ring->reinit_state)) {
6274                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6275                                           tx_flags);
6276                                 tx_ring->atr_count = 0;
6277                         }
6278                 }
6279                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6280                 txq->tx_bytes += skb->len;
6281                 txq->tx_packets++;
6282                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6283                                hdr_len);
6284                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6285
6286         } else {
6287                 dev_kfree_skb_any(skb);
6288                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6289                 tx_ring->next_to_use = first;
6290         }
6291
6292         return NETDEV_TX_OK;
6293 }
6294
6295 /**
6296  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6297  * @netdev: network interface device structure
6298  * @p: pointer to an address structure
6299  *
6300  * Returns 0 on success, negative on failure
6301  **/
6302 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6303 {
6304         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6305         struct ixgbe_hw *hw = &adapter->hw;
6306         struct sockaddr *addr = p;
6307
6308         if (!is_valid_ether_addr(addr->sa_data))
6309                 return -EADDRNOTAVAIL;
6310
6311         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6312         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6313
6314         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6315                             IXGBE_RAH_AV);
6316
6317         return 0;
6318 }
6319
6320 static int
6321 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6322 {
6323         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6324         struct ixgbe_hw *hw = &adapter->hw;
6325         u16 value;
6326         int rc;
6327
6328         if (prtad != hw->phy.mdio.prtad)
6329                 return -EINVAL;
6330         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6331         if (!rc)
6332                 rc = value;
6333         return rc;
6334 }
6335
6336 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6337                             u16 addr, u16 value)
6338 {
6339         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6340         struct ixgbe_hw *hw = &adapter->hw;
6341
6342         if (prtad != hw->phy.mdio.prtad)
6343                 return -EINVAL;
6344         return hw->phy.ops.write_reg(hw, addr, devad, value);
6345 }
6346
6347 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6348 {
6349         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6350
6351         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6352 }
6353
6354 /**
6355  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6356  * netdev->dev_addrs
6357  * @netdev: network interface device structure
6358  *
6359  * Returns non-zero on failure
6360  **/
6361 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6362 {
6363         int err = 0;
6364         struct ixgbe_adapter *adapter = netdev_priv(dev);
6365         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6366
6367         if (is_valid_ether_addr(mac->san_addr)) {
6368                 rtnl_lock();
6369                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6370                 rtnl_unlock();
6371         }
6372         return err;
6373 }
6374
6375 /**
6376  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6377  * netdev->dev_addrs
6378  * @netdev: network interface device structure
6379  *
6380  * Returns non-zero on failure
6381  **/
6382 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6383 {
6384         int err = 0;
6385         struct ixgbe_adapter *adapter = netdev_priv(dev);
6386         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6387
6388         if (is_valid_ether_addr(mac->san_addr)) {
6389                 rtnl_lock();
6390                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6391                 rtnl_unlock();
6392         }
6393         return err;
6394 }
6395
6396 #ifdef CONFIG_NET_POLL_CONTROLLER
6397 /*
6398  * Polling 'interrupt' - used by things like netconsole to send skbs
6399  * without having to re-enable interrupts. It's not called while
6400  * the interrupt routine is executing.
6401  */
6402 static void ixgbe_netpoll(struct net_device *netdev)
6403 {
6404         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6405         int i;
6406
6407         /* if interface is down do nothing */
6408         if (test_bit(__IXGBE_DOWN, &adapter->state))
6409                 return;
6410
6411         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6412         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6413                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6414                 for (i = 0; i < num_q_vectors; i++) {
6415                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6416                         ixgbe_msix_clean_many(0, q_vector);
6417                 }
6418         } else {
6419                 ixgbe_intr(adapter->pdev->irq, netdev);
6420         }
6421         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6422 }
6423 #endif
6424
6425 static const struct net_device_ops ixgbe_netdev_ops = {
6426         .ndo_open               = ixgbe_open,
6427         .ndo_stop               = ixgbe_close,
6428         .ndo_start_xmit         = ixgbe_xmit_frame,
6429         .ndo_select_queue       = ixgbe_select_queue,
6430         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6431         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6432         .ndo_validate_addr      = eth_validate_addr,
6433         .ndo_set_mac_address    = ixgbe_set_mac,
6434         .ndo_change_mtu         = ixgbe_change_mtu,
6435         .ndo_tx_timeout         = ixgbe_tx_timeout,
6436         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6437         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6438         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6439         .ndo_do_ioctl           = ixgbe_ioctl,
6440         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6441         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6442         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6443         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6444 #ifdef CONFIG_NET_POLL_CONTROLLER
6445         .ndo_poll_controller    = ixgbe_netpoll,
6446 #endif
6447 #ifdef IXGBE_FCOE
6448         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6449         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6450         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6451         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6452         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6453 #endif /* IXGBE_FCOE */
6454 };
6455
6456 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6457                            const struct ixgbe_info *ii)
6458 {
6459 #ifdef CONFIG_PCI_IOV
6460         struct ixgbe_hw *hw = &adapter->hw;
6461         int err;
6462
6463         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6464                 return;
6465
6466         /* The 82599 supports up to 64 VFs per physical function
6467          * but this implementation limits allocation to 63 so that
6468          * basic networking resources are still available to the
6469          * physical function
6470          */
6471         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6472         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6473         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6474         if (err) {
6475                 e_err("Failed to enable PCI sriov: %d\n", err);
6476                 goto err_novfs;
6477         }
6478         /* If call to enable VFs succeeded then allocate memory
6479          * for per VF control structures.
6480          */
6481         adapter->vfinfo =
6482                 kcalloc(adapter->num_vfs,
6483                         sizeof(struct vf_data_storage), GFP_KERNEL);
6484         if (adapter->vfinfo) {
6485                 /* Now that we're sure SR-IOV is enabled
6486                  * and memory allocated set up the mailbox parameters
6487                  */
6488                 ixgbe_init_mbx_params_pf(hw);
6489                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6490                        sizeof(hw->mbx.ops));
6491
6492                 /* Disable RSC when in SR-IOV mode */
6493                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6494                                      IXGBE_FLAG2_RSC_ENABLED);
6495                 return;
6496         }
6497
6498         /* Oh oh */
6499         e_err("Unable to allocate memory for VF Data Storage - SRIOV "
6500               "disabled\n");
6501         pci_disable_sriov(adapter->pdev);
6502
6503 err_novfs:
6504         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6505         adapter->num_vfs = 0;
6506 #endif /* CONFIG_PCI_IOV */
6507 }
6508
6509 /**
6510  * ixgbe_probe - Device Initialization Routine
6511  * @pdev: PCI device information struct
6512  * @ent: entry in ixgbe_pci_tbl
6513  *
6514  * Returns 0 on success, negative on failure
6515  *
6516  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6517  * The OS initialization, configuring of the adapter private structure,
6518  * and a hardware reset occur.
6519  **/
6520 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6521                                  const struct pci_device_id *ent)
6522 {
6523         struct net_device *netdev;
6524         struct ixgbe_adapter *adapter = NULL;
6525         struct ixgbe_hw *hw;
6526         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6527         static int cards_found;
6528         int i, err, pci_using_dac;
6529         unsigned int indices = num_possible_cpus();
6530 #ifdef IXGBE_FCOE
6531         u16 device_caps;
6532 #endif
6533         u32 part_num, eec;
6534
6535         err = pci_enable_device_mem(pdev);
6536         if (err)
6537                 return err;
6538
6539         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6540             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6541                 pci_using_dac = 1;
6542         } else {
6543                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6544                 if (err) {
6545                         err = dma_set_coherent_mask(&pdev->dev,
6546                                                     DMA_BIT_MASK(32));
6547                         if (err) {
6548                                 e_dev_err("No usable DMA configuration, "
6549                                           "aborting\n");
6550                                 goto err_dma;
6551                         }
6552                 }
6553                 pci_using_dac = 0;
6554         }
6555
6556         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6557                                            IORESOURCE_MEM), ixgbe_driver_name);
6558         if (err) {
6559                 e_dev_err("pci_request_selected_regions failed 0x%x\n", err);
6560                 goto err_pci_reg;
6561         }
6562
6563         pci_enable_pcie_error_reporting(pdev);
6564
6565         pci_set_master(pdev);
6566         pci_save_state(pdev);
6567
6568         if (ii->mac == ixgbe_mac_82598EB)
6569                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6570         else
6571                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6572
6573         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6574 #ifdef IXGBE_FCOE
6575         indices += min_t(unsigned int, num_possible_cpus(),
6576                          IXGBE_MAX_FCOE_INDICES);
6577 #endif
6578         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6579         if (!netdev) {
6580                 err = -ENOMEM;
6581                 goto err_alloc_etherdev;
6582         }
6583
6584         SET_NETDEV_DEV(netdev, &pdev->dev);
6585
6586         pci_set_drvdata(pdev, netdev);
6587         adapter = netdev_priv(netdev);
6588
6589         adapter->netdev = netdev;
6590         adapter->pdev = pdev;
6591         hw = &adapter->hw;
6592         hw->back = adapter;
6593         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6594
6595         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6596                               pci_resource_len(pdev, 0));
6597         if (!hw->hw_addr) {
6598                 err = -EIO;
6599                 goto err_ioremap;
6600         }
6601
6602         for (i = 1; i <= 5; i++) {
6603                 if (pci_resource_len(pdev, i) == 0)
6604                         continue;
6605         }
6606
6607         netdev->netdev_ops = &ixgbe_netdev_ops;
6608         ixgbe_set_ethtool_ops(netdev);
6609         netdev->watchdog_timeo = 5 * HZ;
6610         strcpy(netdev->name, pci_name(pdev));
6611
6612         adapter->bd_number = cards_found;
6613
6614         /* Setup hw api */
6615         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6616         hw->mac.type  = ii->mac;
6617
6618         /* EEPROM */
6619         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6620         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6621         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6622         if (!(eec & (1 << 8)))
6623                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6624
6625         /* PHY */
6626         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6627         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6628         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6629         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6630         hw->phy.mdio.mmds = 0;
6631         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6632         hw->phy.mdio.dev = netdev;
6633         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6634         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6635
6636         /* set up this timer and work struct before calling get_invariants
6637          * which might start the timer
6638          */
6639         init_timer(&adapter->sfp_timer);
6640         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6641         adapter->sfp_timer.data = (unsigned long) adapter;
6642
6643         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6644
6645         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6646         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6647
6648         /* a new SFP+ module arrival, called from GPI SDP2 context */
6649         INIT_WORK(&adapter->sfp_config_module_task,
6650                   ixgbe_sfp_config_module_task);
6651
6652         ii->get_invariants(hw);
6653
6654         /* setup the private structure */
6655         err = ixgbe_sw_init(adapter);
6656         if (err)
6657                 goto err_sw_init;
6658
6659         /* Make it possible the adapter to be woken up via WOL */
6660         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6661                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6662
6663         /*
6664          * If there is a fan on this device and it has failed log the
6665          * failure.
6666          */
6667         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6668                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6669                 if (esdp & IXGBE_ESDP_SDP1)
6670                         e_crit("Fan has stopped, replace the adapter\n");
6671         }
6672
6673         /* reset_hw fills in the perm_addr as well */
6674         hw->phy.reset_if_overtemp = true;
6675         err = hw->mac.ops.reset_hw(hw);
6676         hw->phy.reset_if_overtemp = false;
6677         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6678             hw->mac.type == ixgbe_mac_82598EB) {
6679                 /*
6680                  * Start a kernel thread to watch for a module to arrive.
6681                  * Only do this for 82598, since 82599 will generate
6682                  * interrupts on module arrival.
6683                  */
6684                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6685                 mod_timer(&adapter->sfp_timer,
6686                           round_jiffies(jiffies + (2 * HZ)));
6687                 err = 0;
6688         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6689                 e_dev_err("failed to initialize because an unsupported SFP+ "
6690                           "module type was detected.\n");
6691                 e_dev_err("Reload the driver after installing a supported "
6692                           "module.\n");
6693                 goto err_sw_init;
6694         } else if (err) {
6695                 e_dev_err("HW Init failed: %d\n", err);
6696                 goto err_sw_init;
6697         }
6698
6699         ixgbe_probe_vf(adapter, ii);
6700
6701         netdev->features =    NETIF_F_SG |
6702                            NETIF_F_IP_CSUM |
6703                            NETIF_F_HW_VLAN_TX |
6704                            NETIF_F_HW_VLAN_RX |
6705                            NETIF_F_HW_VLAN_FILTER;
6706
6707         netdev->features |= NETIF_F_IPV6_CSUM;
6708         netdev->features |= NETIF_F_TSO;
6709         netdev->features |= NETIF_F_TSO6;
6710         netdev->features |= NETIF_F_GRO;
6711
6712         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6713                 netdev->features |= NETIF_F_SCTP_CSUM;
6714
6715         netdev->vlan_features |= NETIF_F_TSO;
6716         netdev->vlan_features |= NETIF_F_TSO6;
6717         netdev->vlan_features |= NETIF_F_IP_CSUM;
6718         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6719         netdev->vlan_features |= NETIF_F_SG;
6720
6721         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6722                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6723                                     IXGBE_FLAG_DCB_ENABLED);
6724         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6725                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6726
6727 #ifdef CONFIG_IXGBE_DCB
6728         netdev->dcbnl_ops = &dcbnl_ops;
6729 #endif
6730
6731 #ifdef IXGBE_FCOE
6732         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6733                 if (hw->mac.ops.get_device_caps) {
6734                         hw->mac.ops.get_device_caps(hw, &device_caps);
6735                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6736                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6737                 }
6738         }
6739 #endif /* IXGBE_FCOE */
6740         if (pci_using_dac)
6741                 netdev->features |= NETIF_F_HIGHDMA;
6742
6743         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6744                 netdev->features |= NETIF_F_LRO;
6745
6746         /* make sure the EEPROM is good */
6747         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6748                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6749                 err = -EIO;
6750                 goto err_eeprom;
6751         }
6752
6753         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6754         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6755
6756         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6757                 e_dev_err("invalid MAC address\n");
6758                 err = -EIO;
6759                 goto err_eeprom;
6760         }
6761
6762         /* power down the optics */
6763         if (hw->phy.multispeed_fiber)
6764                 hw->mac.ops.disable_tx_laser(hw);
6765
6766         init_timer(&adapter->watchdog_timer);
6767         adapter->watchdog_timer.function = &ixgbe_watchdog;
6768         adapter->watchdog_timer.data = (unsigned long)adapter;
6769
6770         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6771         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6772
6773         err = ixgbe_init_interrupt_scheme(adapter);
6774         if (err)
6775                 goto err_sw_init;
6776
6777         switch (pdev->device) {
6778         case IXGBE_DEV_ID_82599_KX4:
6779                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6780                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6781                 break;
6782         default:
6783                 adapter->wol = 0;
6784                 break;
6785         }
6786         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6787
6788         /* pick up the PCI bus settings for reporting later */
6789         hw->mac.ops.get_bus_info(hw);
6790
6791         /* print bus type/speed/width info */
6792         e_dev_info("(PCI Express:%s:%s) %pM\n",
6793                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6794                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6795                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6796                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6797                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6798                  "Unknown"),
6799                 netdev->dev_addr);
6800         ixgbe_read_pba_num_generic(hw, &part_num);
6801         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6802                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6803                            "PBA No: %06x-%03x\n",
6804                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6805                            (part_num >> 8), (part_num & 0xff));
6806         else
6807                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6808                            hw->mac.type, hw->phy.type,
6809                            (part_num >> 8), (part_num & 0xff));
6810
6811         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6812                 e_dev_warn("PCI-Express bandwidth available for this card is "
6813                            "not sufficient for optimal performance.\n");
6814                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6815                            "is required.\n");
6816         }
6817
6818         /* save off EEPROM version number */
6819         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6820
6821         /* reset the hardware with the new settings */
6822         err = hw->mac.ops.start_hw(hw);
6823
6824         if (err == IXGBE_ERR_EEPROM_VERSION) {
6825                 /* We are running on a pre-production device, log a warning */
6826                 e_dev_warn("This device is a pre-production adapter/LOM. "
6827                            "Please be aware there may be issues associated "
6828                            "with your hardware.  If you are experiencing "
6829                            "problems please contact your Intel or hardware "
6830                            "representative who provided you with this "
6831                            "hardware.\n");
6832         }
6833         strcpy(netdev->name, "eth%d");
6834         err = register_netdev(netdev);
6835         if (err)
6836                 goto err_register;
6837
6838         /* carrier off reporting is important to ethtool even BEFORE open */
6839         netif_carrier_off(netdev);
6840
6841         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6842             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6843                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6844
6845         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6846                 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6847 #ifdef CONFIG_IXGBE_DCA
6848         if (dca_add_requester(&pdev->dev) == 0) {
6849                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6850                 ixgbe_setup_dca(adapter);
6851         }
6852 #endif
6853         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6854                 e_info("IOV is enabled with %d VFs\n", adapter->num_vfs);
6855                 for (i = 0; i < adapter->num_vfs; i++)
6856                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6857         }
6858
6859         /* add san mac addr to netdev */
6860         ixgbe_add_sanmac_netdev(netdev);
6861
6862         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6863         cards_found++;
6864         return 0;
6865
6866 err_register:
6867         ixgbe_release_hw_control(adapter);
6868         ixgbe_clear_interrupt_scheme(adapter);
6869 err_sw_init:
6870 err_eeprom:
6871         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6872                 ixgbe_disable_sriov(adapter);
6873         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6874         del_timer_sync(&adapter->sfp_timer);
6875         cancel_work_sync(&adapter->sfp_task);
6876         cancel_work_sync(&adapter->multispeed_fiber_task);
6877         cancel_work_sync(&adapter->sfp_config_module_task);
6878         iounmap(hw->hw_addr);
6879 err_ioremap:
6880         free_netdev(netdev);
6881 err_alloc_etherdev:
6882         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6883                                      IORESOURCE_MEM));
6884 err_pci_reg:
6885 err_dma:
6886         pci_disable_device(pdev);
6887         return err;
6888 }
6889
6890 /**
6891  * ixgbe_remove - Device Removal Routine
6892  * @pdev: PCI device information struct
6893  *
6894  * ixgbe_remove is called by the PCI subsystem to alert the driver
6895  * that it should release a PCI device.  The could be caused by a
6896  * Hot-Plug event, or because the driver is going to be removed from
6897  * memory.
6898  **/
6899 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6900 {
6901         struct net_device *netdev = pci_get_drvdata(pdev);
6902         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6903
6904         set_bit(__IXGBE_DOWN, &adapter->state);
6905         /* clear the module not found bit to make sure the worker won't
6906          * reschedule
6907          */
6908         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6909         del_timer_sync(&adapter->watchdog_timer);
6910
6911         del_timer_sync(&adapter->sfp_timer);
6912         cancel_work_sync(&adapter->watchdog_task);
6913         cancel_work_sync(&adapter->sfp_task);
6914         cancel_work_sync(&adapter->multispeed_fiber_task);
6915         cancel_work_sync(&adapter->sfp_config_module_task);
6916         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6917             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6918                 cancel_work_sync(&adapter->fdir_reinit_task);
6919         flush_scheduled_work();
6920
6921 #ifdef CONFIG_IXGBE_DCA
6922         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6923                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6924                 dca_remove_requester(&pdev->dev);
6925                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6926         }
6927
6928 #endif
6929 #ifdef IXGBE_FCOE
6930         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6931                 ixgbe_cleanup_fcoe(adapter);
6932
6933 #endif /* IXGBE_FCOE */
6934
6935         /* remove the added san mac */
6936         ixgbe_del_sanmac_netdev(netdev);
6937
6938         if (netdev->reg_state == NETREG_REGISTERED)
6939                 unregister_netdev(netdev);
6940
6941         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6942                 ixgbe_disable_sriov(adapter);
6943
6944         ixgbe_clear_interrupt_scheme(adapter);
6945
6946         ixgbe_release_hw_control(adapter);
6947
6948         iounmap(adapter->hw.hw_addr);
6949         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6950                                      IORESOURCE_MEM));
6951
6952         e_dev_info("complete\n");
6953
6954         free_netdev(netdev);
6955
6956         pci_disable_pcie_error_reporting(pdev);
6957
6958         pci_disable_device(pdev);
6959 }
6960
6961 /**
6962  * ixgbe_io_error_detected - called when PCI error is detected
6963  * @pdev: Pointer to PCI device
6964  * @state: The current pci connection state
6965  *
6966  * This function is called after a PCI bus error affecting
6967  * this device has been detected.
6968  */
6969 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6970                                                 pci_channel_state_t state)
6971 {
6972         struct net_device *netdev = pci_get_drvdata(pdev);
6973         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6974
6975         netif_device_detach(netdev);
6976
6977         if (state == pci_channel_io_perm_failure)
6978                 return PCI_ERS_RESULT_DISCONNECT;
6979
6980         if (netif_running(netdev))
6981                 ixgbe_down(adapter);
6982         pci_disable_device(pdev);
6983
6984         /* Request a slot reset. */
6985         return PCI_ERS_RESULT_NEED_RESET;
6986 }
6987
6988 /**
6989  * ixgbe_io_slot_reset - called after the pci bus has been reset.
6990  * @pdev: Pointer to PCI device
6991  *
6992  * Restart the card from scratch, as if from a cold-boot.
6993  */
6994 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
6995 {
6996         struct net_device *netdev = pci_get_drvdata(pdev);
6997         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6998         pci_ers_result_t result;
6999         int err;
7000
7001         if (pci_enable_device_mem(pdev)) {
7002                 e_err("Cannot re-enable PCI device after reset.\n");
7003                 result = PCI_ERS_RESULT_DISCONNECT;
7004         } else {
7005                 pci_set_master(pdev);
7006                 pci_restore_state(pdev);
7007                 pci_save_state(pdev);
7008
7009                 pci_wake_from_d3(pdev, false);
7010
7011                 ixgbe_reset(adapter);
7012                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7013                 result = PCI_ERS_RESULT_RECOVERED;
7014         }
7015
7016         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7017         if (err) {
7018                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7019                           "failed 0x%0x\n", err);
7020                 /* non-fatal, continue */
7021         }
7022
7023         return result;
7024 }
7025
7026 /**
7027  * ixgbe_io_resume - called when traffic can start flowing again.
7028  * @pdev: Pointer to PCI device
7029  *
7030  * This callback is called when the error recovery driver tells us that
7031  * its OK to resume normal operation.
7032  */
7033 static void ixgbe_io_resume(struct pci_dev *pdev)
7034 {
7035         struct net_device *netdev = pci_get_drvdata(pdev);
7036         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7037
7038         if (netif_running(netdev)) {
7039                 if (ixgbe_up(adapter)) {
7040                         e_info("ixgbe_up failed after reset\n");
7041                         return;
7042                 }
7043         }
7044
7045         netif_device_attach(netdev);
7046 }
7047
7048 static struct pci_error_handlers ixgbe_err_handler = {
7049         .error_detected = ixgbe_io_error_detected,
7050         .slot_reset = ixgbe_io_slot_reset,
7051         .resume = ixgbe_io_resume,
7052 };
7053
7054 static struct pci_driver ixgbe_driver = {
7055         .name     = ixgbe_driver_name,
7056         .id_table = ixgbe_pci_tbl,
7057         .probe    = ixgbe_probe,
7058         .remove   = __devexit_p(ixgbe_remove),
7059 #ifdef CONFIG_PM
7060         .suspend  = ixgbe_suspend,
7061         .resume   = ixgbe_resume,
7062 #endif
7063         .shutdown = ixgbe_shutdown,
7064         .err_handler = &ixgbe_err_handler
7065 };
7066
7067 /**
7068  * ixgbe_init_module - Driver Registration Routine
7069  *
7070  * ixgbe_init_module is the first routine called when the driver is
7071  * loaded. All it does is register with the PCI subsystem.
7072  **/
7073 static int __init ixgbe_init_module(void)
7074 {
7075         int ret;
7076         pr_info("%s - version %s\n", ixgbe_driver_string,
7077                    ixgbe_driver_version);
7078         pr_info("%s\n", ixgbe_copyright);
7079
7080 #ifdef CONFIG_IXGBE_DCA
7081         dca_register_notify(&dca_notifier);
7082 #endif
7083
7084         ret = pci_register_driver(&ixgbe_driver);
7085         return ret;
7086 }
7087
7088 module_init(ixgbe_init_module);
7089
7090 /**
7091  * ixgbe_exit_module - Driver Exit Cleanup Routine
7092  *
7093  * ixgbe_exit_module is called just before the driver is removed
7094  * from memory.
7095  **/
7096 static void __exit ixgbe_exit_module(void)
7097 {
7098 #ifdef CONFIG_IXGBE_DCA
7099         dca_unregister_notify(&dca_notifier);
7100 #endif
7101         pci_unregister_driver(&ixgbe_driver);
7102 }
7103
7104 #ifdef CONFIG_IXGBE_DCA
7105 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7106                             void *p)
7107 {
7108         int ret_val;
7109
7110         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7111                                          __ixgbe_notify_dca);
7112
7113         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7114 }
7115
7116 #endif /* CONFIG_IXGBE_DCA */
7117
7118 /**
7119  * ixgbe_get_hw_dev return device
7120  * used by hardware layer to print debugging information
7121  **/
7122 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7123 {
7124         struct ixgbe_adapter *adapter = hw->back;
7125         return adapter->netdev;
7126 }
7127
7128 module_exit(ixgbe_exit_module);
7129
7130 /* ixgbe_main.c */