1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
147 struct ixgbe_hw *hw = &adapter->hw;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
170 /* take a breather then clean up driver data */
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
180 struct ixgbe_reg_info {
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
285 pr_info("%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 pr_err("%-15s", rname);
293 for (j = 0; j < 8; j++)
294 pr_cont(" %08x", regs[i*8+j]);
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
319 if (!netif_msg_hw(adapter))
322 /* Print netdevice Info */
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 pr_info("Device Name state "
326 "trans_start last_rx\n");
327 pr_info("%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 pr_info(" Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366 /* Transmit Descriptor Formats
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
390 pr_info("T [0x%03X] %016llX %016llX %016llX"
391 " %04X %3X %016llX %p", i,
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
402 else if (i == tx_ring->next_to_use)
404 else if (i == tx_ring->next_to_clean)
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
418 /* Print RX Rings Summary */
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
421 pr_info("Queue [NTU] [NTC]\n");
422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
429 if (!netif_msg_rx_status(adapter))
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434 /* Advanced Receive Descriptor (Read) Format
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
443 * Advanced Receive Descriptor (Write-Back) Format
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
473 pr_info("RWB[0x%03X] %016llX "
474 "%016llX ---------------- %p", i,
477 rx_buffer_info->skb);
479 pr_info("R [0x%03X] %016llX "
480 "%016llX %016llX %p", i,
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
504 if (i == rx_ring->next_to_use)
506 else if (i == rx_ring->next_to_clean)
518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
547 u8 queue, u8 msix_vector)
550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
592 switch (adapter->hw.mac.type) {
593 case ixgbe_mac_82598EB:
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
597 case ixgbe_mac_82599EB:
598 mask = (qmask & 0xFFFFFFFF);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
600 mask = (qmask >> 32);
601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
608 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
609 struct ixgbe_tx_buffer *tx_buffer_info)
611 if (tx_buffer_info->dma) {
612 if (tx_buffer_info->mapped_as_page)
613 dma_unmap_page(tx_ring->dev,
615 tx_buffer_info->length,
618 dma_unmap_single(tx_ring->dev,
620 tx_buffer_info->length,
622 tx_buffer_info->dma = 0;
624 if (tx_buffer_info->skb) {
625 dev_kfree_skb_any(tx_buffer_info->skb);
626 tx_buffer_info->skb = NULL;
628 tx_buffer_info->time_stamp = 0;
629 /* tx_buffer_info must be completely set up in the transmit path */
633 * ixgbe_tx_xon_state - check the tx ring xon state
634 * @adapter: the ixgbe adapter
635 * @tx_ring: the corresponding tx_ring
637 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
638 * corresponding TC of this tx_ring when checking TFCS.
640 * Returns : true if in xon state (currently not paused)
642 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
643 struct ixgbe_ring *tx_ring)
645 u32 txoff = IXGBE_TFCS_TXOFF;
647 #ifdef CONFIG_IXGBE_DCB
648 if (adapter->dcb_cfg.pfc_mode_enable) {
650 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
651 u8 reg_idx = tx_ring->reg_idx;
653 switch (adapter->hw.mac.type) {
654 case ixgbe_mac_82598EB:
656 txoff = IXGBE_TFCS_TXOFF0;
658 case ixgbe_mac_82599EB:
660 txoff = IXGBE_TFCS_TXOFF;
664 if (tc == 2) /* TC2, TC3 */
665 tc += (reg_idx - 64) >> 4;
666 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
667 tc += 1 + ((reg_idx - 96) >> 3);
668 } else if (dcb_i == 4) {
672 tc += (reg_idx - 64) >> 5;
673 if (tc == 2) /* TC2, TC3 */
674 tc += (reg_idx - 96) >> 4;
685 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
688 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
689 struct ixgbe_ring *tx_ring,
692 struct ixgbe_hw *hw = &adapter->hw;
694 /* Detect a transmit hang in hardware, this serializes the
695 * check with the clearing of time_stamp and movement of eop */
696 clear_check_for_tx_hang(tx_ring);
697 if (tx_ring->tx_buffer_info[eop].time_stamp &&
698 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
699 ixgbe_tx_xon_state(adapter, tx_ring)) {
700 /* detected Tx unit hang */
701 union ixgbe_adv_tx_desc *tx_desc;
702 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
703 e_err(drv, "Detected Tx Unit Hang\n"
705 " TDH, TDT <%x>, <%x>\n"
706 " next_to_use <%x>\n"
707 " next_to_clean <%x>\n"
708 "tx_buffer_info[next_to_clean]\n"
709 " time_stamp <%lx>\n"
711 tx_ring->queue_index,
712 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
713 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
714 tx_ring->next_to_use, eop,
715 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
722 #define IXGBE_MAX_TXD_PWR 14
723 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
725 /* Tx Descriptors needed, worst case */
726 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
727 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
728 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
729 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
731 static void ixgbe_tx_timeout(struct net_device *netdev);
734 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
735 * @q_vector: structure containing interrupt and ring information
736 * @tx_ring: tx ring to clean
738 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
739 struct ixgbe_ring *tx_ring)
741 struct ixgbe_adapter *adapter = q_vector->adapter;
742 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
743 struct ixgbe_tx_buffer *tx_buffer_info;
744 unsigned int total_bytes = 0, total_packets = 0;
745 u16 i, eop, count = 0;
747 i = tx_ring->next_to_clean;
748 eop = tx_ring->tx_buffer_info[i].next_to_watch;
749 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
751 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
752 (count < tx_ring->work_limit)) {
753 bool cleaned = false;
754 rmb(); /* read buffer_info after eop_desc */
755 for ( ; !cleaned; count++) {
756 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
757 tx_buffer_info = &tx_ring->tx_buffer_info[i];
759 tx_desc->wb.status = 0;
760 cleaned = (i == eop);
763 if (i == tx_ring->count)
766 if (cleaned && tx_buffer_info->skb) {
767 total_bytes += tx_buffer_info->bytecount;
768 total_packets += tx_buffer_info->gso_segs;
771 ixgbe_unmap_and_free_tx_resource(tx_ring,
775 eop = tx_ring->tx_buffer_info[i].next_to_watch;
776 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
779 tx_ring->next_to_clean = i;
780 tx_ring->total_bytes += total_bytes;
781 tx_ring->total_packets += total_packets;
782 u64_stats_update_begin(&tx_ring->syncp);
783 tx_ring->stats.packets += total_packets;
784 tx_ring->stats.bytes += total_bytes;
785 u64_stats_update_end(&tx_ring->syncp);
787 if (check_for_tx_hang(tx_ring) &&
788 ixgbe_check_tx_hang(adapter, tx_ring, i)) {
789 /* schedule immediate reset if we believe we hung */
790 e_info(probe, "tx hang %d detected, resetting "
791 "adapter\n", adapter->tx_timeout_count + 1);
792 ixgbe_tx_timeout(adapter->netdev);
794 /* the adapter is about to reset, no point in enabling stuff */
798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
799 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
800 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
801 /* Make sure that anybody stopping the queue after this
802 * sees the new next_to_clean.
805 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
806 !test_bit(__IXGBE_DOWN, &adapter->state)) {
807 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
808 ++tx_ring->tx_stats.restart_queue;
812 return count < tx_ring->work_limit;
815 #ifdef CONFIG_IXGBE_DCA
816 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
817 struct ixgbe_ring *rx_ring,
820 struct ixgbe_hw *hw = &adapter->hw;
822 u8 reg_idx = rx_ring->reg_idx;
824 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
828 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
830 case ixgbe_mac_82599EB:
831 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
832 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
833 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
838 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
839 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
840 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
841 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
842 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
843 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
846 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
847 struct ixgbe_ring *tx_ring,
850 struct ixgbe_hw *hw = &adapter->hw;
852 u8 reg_idx = tx_ring->reg_idx;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
857 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
858 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
859 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
860 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
861 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
863 case ixgbe_mac_82599EB:
864 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
865 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
866 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
867 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
868 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
869 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
870 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
877 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
879 struct ixgbe_adapter *adapter = q_vector->adapter;
884 if (q_vector->cpu == cpu)
887 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
888 for (i = 0; i < q_vector->txr_count; i++) {
889 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
890 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
894 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
895 for (i = 0; i < q_vector->rxr_count; i++) {
896 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
897 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
906 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
911 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
914 /* always use CB2 mode, difference is masked in the CB driver */
915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
917 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
918 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
922 for (i = 0; i < num_q_vectors; i++) {
923 adapter->q_vector[i]->cpu = -1;
924 ixgbe_update_dca(adapter->q_vector[i]);
928 static int __ixgbe_notify_dca(struct device *dev, void *data)
930 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
931 unsigned long event = *(unsigned long *)data;
933 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
937 case DCA_PROVIDER_ADD:
938 /* if we're already enabled, don't do it again */
939 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
941 if (dca_add_requester(dev) == 0) {
942 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
943 ixgbe_setup_dca(adapter);
946 /* Fall Through since DCA is disabled. */
947 case DCA_PROVIDER_REMOVE:
948 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
949 dca_remove_requester(dev);
950 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
959 #endif /* CONFIG_IXGBE_DCA */
961 * ixgbe_receive_skb - Send a completed packet up the stack
962 * @adapter: board private structure
963 * @skb: packet to send up
964 * @status: hardware indication of status of receive
965 * @rx_ring: rx descriptor ring (for a specific queue) to setup
966 * @rx_desc: rx descriptor
968 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
969 struct sk_buff *skb, u8 status,
970 struct ixgbe_ring *ring,
971 union ixgbe_adv_rx_desc *rx_desc)
973 struct ixgbe_adapter *adapter = q_vector->adapter;
974 struct napi_struct *napi = &q_vector->napi;
975 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
976 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
978 if (is_vlan && (tag & VLAN_VID_MASK))
979 __vlan_hwaccel_put_tag(skb, tag);
981 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
982 napi_gro_receive(napi, skb);
988 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
989 * @adapter: address of board private structure
990 * @status_err: hardware indication of status of receive
991 * @skb: skb currently being received and modified
993 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
994 union ixgbe_adv_rx_desc *rx_desc,
997 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
999 skb_checksum_none_assert(skb);
1001 /* Rx csum disabled */
1002 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1005 /* if IP and error */
1006 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1007 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1008 adapter->hw_csum_rx_error++;
1012 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1015 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1016 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1019 * 82599 errata, UDP frames with a 0 checksum can be marked as
1022 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1023 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1026 adapter->hw_csum_rx_error++;
1030 /* It must be a TCP or UDP packet with a valid checksum */
1031 skb->ip_summed = CHECKSUM_UNNECESSARY;
1034 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1037 * Force memory writes to complete before letting h/w
1038 * know there are new descriptors to fetch. (Only
1039 * applicable for weak-ordered memory model archs,
1043 writel(val, rx_ring->tail);
1047 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1048 * @rx_ring: ring to place buffers on
1049 * @cleaned_count: number of buffers to replace
1051 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1053 union ixgbe_adv_rx_desc *rx_desc;
1054 struct ixgbe_rx_buffer *bi;
1055 struct sk_buff *skb;
1056 u16 i = rx_ring->next_to_use;
1058 /* do nothing if no valid netdev defined */
1059 if (!rx_ring->netdev)
1062 while (cleaned_count--) {
1063 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1064 bi = &rx_ring->rx_buffer_info[i];
1068 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1069 rx_ring->rx_buf_len);
1071 rx_ring->rx_stats.alloc_rx_buff_failed++;
1074 /* initialize queue mapping */
1075 skb_record_rx_queue(skb, rx_ring->queue_index);
1080 bi->dma = dma_map_single(rx_ring->dev,
1082 rx_ring->rx_buf_len,
1084 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1085 rx_ring->rx_stats.alloc_rx_buff_failed++;
1091 if (ring_is_ps_enabled(rx_ring)) {
1093 bi->page = netdev_alloc_page(rx_ring->netdev);
1095 rx_ring->rx_stats.alloc_rx_page_failed++;
1100 if (!bi->page_dma) {
1101 /* use a half page if we're re-using */
1102 bi->page_offset ^= PAGE_SIZE / 2;
1103 bi->page_dma = dma_map_page(rx_ring->dev,
1108 if (dma_mapping_error(rx_ring->dev,
1110 rx_ring->rx_stats.alloc_rx_page_failed++;
1116 /* Refresh the desc even if buffer_addrs didn't change
1117 * because each write-back erases this info. */
1118 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1119 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1121 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1122 rx_desc->read.hdr_addr = 0;
1126 if (i == rx_ring->count)
1131 if (rx_ring->next_to_use != i) {
1132 rx_ring->next_to_use = i;
1133 ixgbe_release_rx_desc(rx_ring, i);
1137 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1139 /* HW will not DMA in data larger than the given buffer, even if it
1140 * parses the (NFS, of course) header to be larger. In that case, it
1141 * fills the header buffer and spills the rest into the page.
1143 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1144 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1145 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1146 if (hlen > IXGBE_RX_HDR_SIZE)
1147 hlen = IXGBE_RX_HDR_SIZE;
1152 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1153 * @skb: pointer to the last skb in the rsc queue
1155 * This function changes a queue full of hw rsc buffers into a completed
1156 * packet. It uses the ->prev pointers to find the first packet and then
1157 * turns it into the frag list owner.
1159 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1161 unsigned int frag_list_size = 0;
1162 unsigned int skb_cnt = 1;
1165 struct sk_buff *prev = skb->prev;
1166 frag_list_size += skb->len;
1172 skb_shinfo(skb)->frag_list = skb->next;
1174 skb->len += frag_list_size;
1175 skb->data_len += frag_list_size;
1176 skb->truesize += frag_list_size;
1177 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1182 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1184 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1185 IXGBE_RXDADV_RSCCNT_MASK);
1188 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1189 struct ixgbe_ring *rx_ring,
1190 int *work_done, int work_to_do)
1192 struct ixgbe_adapter *adapter = q_vector->adapter;
1193 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1194 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1195 struct sk_buff *skb;
1196 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1197 const int current_node = numa_node_id();
1200 #endif /* IXGBE_FCOE */
1203 u16 cleaned_count = 0;
1204 bool pkt_is_rsc = false;
1206 i = rx_ring->next_to_clean;
1207 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1208 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1210 while (staterr & IXGBE_RXD_STAT_DD) {
1213 rmb(); /* read descriptor and rx_buffer_info after status DD */
1215 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1217 skb = rx_buffer_info->skb;
1218 rx_buffer_info->skb = NULL;
1219 prefetch(skb->data);
1221 if (ring_is_rsc_enabled(rx_ring))
1222 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1224 /* if this is a skb from previous receive DMA will be 0 */
1225 if (rx_buffer_info->dma) {
1228 !(staterr & IXGBE_RXD_STAT_EOP) &&
1231 * When HWRSC is enabled, delay unmapping
1232 * of the first packet. It carries the
1233 * header information, HW may still
1234 * access the header after the writeback.
1235 * Only unmap it when EOP is reached
1237 IXGBE_RSC_CB(skb)->delay_unmap = true;
1238 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1240 dma_unmap_single(rx_ring->dev,
1241 rx_buffer_info->dma,
1242 rx_ring->rx_buf_len,
1245 rx_buffer_info->dma = 0;
1247 if (ring_is_ps_enabled(rx_ring)) {
1248 hlen = ixgbe_get_hlen(rx_desc);
1249 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1251 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1256 /* assume packet split since header is unmapped */
1257 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1261 dma_unmap_page(rx_ring->dev,
1262 rx_buffer_info->page_dma,
1265 rx_buffer_info->page_dma = 0;
1266 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1267 rx_buffer_info->page,
1268 rx_buffer_info->page_offset,
1271 if ((page_count(rx_buffer_info->page) == 1) &&
1272 (page_to_nid(rx_buffer_info->page) == current_node))
1273 get_page(rx_buffer_info->page);
1275 rx_buffer_info->page = NULL;
1277 skb->len += upper_len;
1278 skb->data_len += upper_len;
1279 skb->truesize += upper_len;
1283 if (i == rx_ring->count)
1286 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1291 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1292 IXGBE_RXDADV_NEXTP_SHIFT;
1293 next_buffer = &rx_ring->rx_buffer_info[nextp];
1295 next_buffer = &rx_ring->rx_buffer_info[i];
1298 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1299 if (ring_is_ps_enabled(rx_ring)) {
1300 rx_buffer_info->skb = next_buffer->skb;
1301 rx_buffer_info->dma = next_buffer->dma;
1302 next_buffer->skb = skb;
1303 next_buffer->dma = 0;
1305 skb->next = next_buffer->skb;
1306 skb->next->prev = skb;
1308 rx_ring->rx_stats.non_eop_descs++;
1313 skb = ixgbe_transform_rsc_queue(skb);
1314 /* if we got here without RSC the packet is invalid */
1316 __pskb_trim(skb, 0);
1317 rx_buffer_info->skb = skb;
1322 if (ring_is_rsc_enabled(rx_ring)) {
1323 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1324 dma_unmap_single(rx_ring->dev,
1325 IXGBE_RSC_CB(skb)->dma,
1326 rx_ring->rx_buf_len,
1328 IXGBE_RSC_CB(skb)->dma = 0;
1329 IXGBE_RSC_CB(skb)->delay_unmap = false;
1333 if (ring_is_ps_enabled(rx_ring))
1334 rx_ring->rx_stats.rsc_count +=
1335 skb_shinfo(skb)->nr_frags;
1337 rx_ring->rx_stats.rsc_count +=
1338 IXGBE_RSC_CB(skb)->skb_cnt;
1339 rx_ring->rx_stats.rsc_flush++;
1342 /* ERR_MASK will only have valid bits if EOP set */
1343 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1344 /* trim packet back to size 0 and recycle it */
1345 __pskb_trim(skb, 0);
1346 rx_buffer_info->skb = skb;
1350 ixgbe_rx_checksum(adapter, rx_desc, skb);
1352 /* probably a little skewed due to removing CRC */
1353 total_rx_bytes += skb->len;
1356 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1358 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1359 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1360 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1364 #endif /* IXGBE_FCOE */
1365 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1368 rx_desc->wb.upper.status_error = 0;
1371 if (*work_done >= work_to_do)
1374 /* return some buffers to hardware, one at a time is too slow */
1375 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1376 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1380 /* use prefetched values */
1382 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1385 rx_ring->next_to_clean = i;
1386 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1389 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1392 /* include DDPed FCoE data */
1393 if (ddp_bytes > 0) {
1396 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1397 sizeof(struct fc_frame_header) -
1398 sizeof(struct fcoe_crc_eof);
1401 total_rx_bytes += ddp_bytes;
1402 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1404 #endif /* IXGBE_FCOE */
1406 rx_ring->total_packets += total_rx_packets;
1407 rx_ring->total_bytes += total_rx_bytes;
1408 u64_stats_update_begin(&rx_ring->syncp);
1409 rx_ring->stats.packets += total_rx_packets;
1410 rx_ring->stats.bytes += total_rx_bytes;
1411 u64_stats_update_end(&rx_ring->syncp);
1414 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1416 * ixgbe_configure_msix - Configure MSI-X hardware
1417 * @adapter: board private structure
1419 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1422 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1424 struct ixgbe_q_vector *q_vector;
1425 int i, q_vectors, v_idx, r_idx;
1428 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1431 * Populate the IVAR table and set the ITR values to the
1432 * corresponding register.
1434 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1435 q_vector = adapter->q_vector[v_idx];
1436 /* XXX for_each_set_bit(...) */
1437 r_idx = find_first_bit(q_vector->rxr_idx,
1438 adapter->num_rx_queues);
1440 for (i = 0; i < q_vector->rxr_count; i++) {
1441 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1442 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1443 r_idx = find_next_bit(q_vector->rxr_idx,
1444 adapter->num_rx_queues,
1447 r_idx = find_first_bit(q_vector->txr_idx,
1448 adapter->num_tx_queues);
1450 for (i = 0; i < q_vector->txr_count; i++) {
1451 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1452 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1453 r_idx = find_next_bit(q_vector->txr_idx,
1454 adapter->num_tx_queues,
1458 if (q_vector->txr_count && !q_vector->rxr_count)
1460 q_vector->eitr = adapter->tx_eitr_param;
1461 else if (q_vector->rxr_count)
1463 q_vector->eitr = adapter->rx_eitr_param;
1465 ixgbe_write_eitr(q_vector);
1466 /* If Flow Director is enabled, set interrupt affinity */
1467 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1468 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1470 * Allocate the affinity_hint cpumask, assign the mask
1471 * for this vector, and set our affinity_hint for
1474 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1477 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1478 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1479 q_vector->affinity_mask);
1483 switch (adapter->hw.mac.type) {
1484 case ixgbe_mac_82598EB:
1485 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1488 case ixgbe_mac_82599EB:
1489 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1495 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1497 /* set up to autoclear timer, and the vectors */
1498 mask = IXGBE_EIMS_ENABLE_MASK;
1499 if (adapter->num_vfs)
1500 mask &= ~(IXGBE_EIMS_OTHER |
1501 IXGBE_EIMS_MAILBOX |
1504 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1508 enum latency_range {
1512 latency_invalid = 255
1516 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1517 * @adapter: pointer to adapter
1518 * @eitr: eitr setting (ints per sec) to give last timeslice
1519 * @itr_setting: current throttle rate in ints/second
1520 * @packets: the number of packets during this measurement interval
1521 * @bytes: the number of bytes during this measurement interval
1523 * Stores a new ITR value based on packets and byte
1524 * counts during the last interrupt. The advantage of per interrupt
1525 * computation is faster updates and more accurate ITR for the current
1526 * traffic pattern. Constants in this function were computed
1527 * based on theoretical maximum wire speed and thresholds were set based
1528 * on testing data as well as attempting to minimize response time
1529 * while increasing bulk throughput.
1530 * this functionality is controlled by the InterruptThrottleRate module
1531 * parameter (see ixgbe_param.c)
1533 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1534 u32 eitr, u8 itr_setting,
1535 int packets, int bytes)
1537 unsigned int retval = itr_setting;
1542 goto update_itr_done;
1545 /* simple throttlerate management
1546 * 0-20MB/s lowest (100000 ints/s)
1547 * 20-100MB/s low (20000 ints/s)
1548 * 100-1249MB/s bulk (8000 ints/s)
1550 /* what was last interrupt timeslice? */
1551 timepassed_us = 1000000/eitr;
1552 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1554 switch (itr_setting) {
1555 case lowest_latency:
1556 if (bytes_perint > adapter->eitr_low)
1557 retval = low_latency;
1560 if (bytes_perint > adapter->eitr_high)
1561 retval = bulk_latency;
1562 else if (bytes_perint <= adapter->eitr_low)
1563 retval = lowest_latency;
1566 if (bytes_perint <= adapter->eitr_high)
1567 retval = low_latency;
1576 * ixgbe_write_eitr - write EITR register in hardware specific way
1577 * @q_vector: structure containing interrupt and ring information
1579 * This function is made to be called by ethtool and by the driver
1580 * when it needs to update EITR registers at runtime. Hardware
1581 * specific quirks/differences are taken care of here.
1583 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1585 struct ixgbe_adapter *adapter = q_vector->adapter;
1586 struct ixgbe_hw *hw = &adapter->hw;
1587 int v_idx = q_vector->v_idx;
1588 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1590 switch (adapter->hw.mac.type) {
1591 case ixgbe_mac_82598EB:
1592 /* must write high and low 16 bits to reset counter */
1593 itr_reg |= (itr_reg << 16);
1595 case ixgbe_mac_82599EB:
1597 * 82599 can support a value of zero, so allow it for
1598 * max interrupt rate, but there is an errata where it can
1599 * not be zero with RSC
1602 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1606 * set the WDIS bit to not clear the timer bits and cause an
1607 * immediate assertion of the interrupt
1609 itr_reg |= IXGBE_EITR_CNT_WDIS;
1614 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1617 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1619 struct ixgbe_adapter *adapter = q_vector->adapter;
1622 u8 current_itr, ret_itr;
1624 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1625 for (i = 0; i < q_vector->txr_count; i++) {
1626 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1627 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1629 tx_ring->total_packets,
1630 tx_ring->total_bytes);
1631 /* if the result for this queue would decrease interrupt
1632 * rate for this vector then use that result */
1633 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1634 q_vector->tx_itr - 1 : ret_itr);
1635 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1639 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1640 for (i = 0; i < q_vector->rxr_count; i++) {
1641 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1642 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1644 rx_ring->total_packets,
1645 rx_ring->total_bytes);
1646 /* if the result for this queue would decrease interrupt
1647 * rate for this vector then use that result */
1648 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1649 q_vector->rx_itr - 1 : ret_itr);
1650 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1654 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1656 switch (current_itr) {
1657 /* counts and packets in update_itr are dependent on these numbers */
1658 case lowest_latency:
1662 new_itr = 20000; /* aka hwitr = ~200 */
1670 if (new_itr != q_vector->eitr) {
1671 /* do an exponential smoothing */
1672 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1674 /* save the algorithm value here, not the smoothed one */
1675 q_vector->eitr = new_itr;
1677 ixgbe_write_eitr(q_vector);
1682 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1683 * @work: pointer to work_struct containing our data
1685 static void ixgbe_check_overtemp_task(struct work_struct *work)
1687 struct ixgbe_adapter *adapter = container_of(work,
1688 struct ixgbe_adapter,
1689 check_overtemp_task);
1690 struct ixgbe_hw *hw = &adapter->hw;
1691 u32 eicr = adapter->interrupt_event;
1693 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1696 switch (hw->device_id) {
1697 case IXGBE_DEV_ID_82599_T3_LOM: {
1699 bool link_up = false;
1701 if (hw->mac.ops.check_link)
1702 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1704 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1705 (eicr & IXGBE_EICR_LSC))
1706 /* Check if this is due to overtemp */
1707 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1712 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1717 "Network adapter has been stopped because it has over heated. "
1718 "Restart the computer. If the problem persists, "
1719 "power off the system and replace the adapter\n");
1720 /* write to clear the interrupt */
1721 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1724 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1726 struct ixgbe_hw *hw = &adapter->hw;
1728 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1729 (eicr & IXGBE_EICR_GPI_SDP1)) {
1730 e_crit(probe, "Fan has stopped, replace the adapter\n");
1731 /* write to clear the interrupt */
1732 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1736 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1738 struct ixgbe_hw *hw = &adapter->hw;
1740 if (eicr & IXGBE_EICR_GPI_SDP2) {
1741 /* Clear the interrupt */
1742 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1743 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1744 schedule_work(&adapter->sfp_config_module_task);
1747 if (eicr & IXGBE_EICR_GPI_SDP1) {
1748 /* Clear the interrupt */
1749 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1750 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1751 schedule_work(&adapter->multispeed_fiber_task);
1755 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1757 struct ixgbe_hw *hw = &adapter->hw;
1760 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1761 adapter->link_check_timeout = jiffies;
1762 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1763 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1764 IXGBE_WRITE_FLUSH(hw);
1765 schedule_work(&adapter->watchdog_task);
1769 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1771 struct net_device *netdev = data;
1772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1773 struct ixgbe_hw *hw = &adapter->hw;
1777 * Workaround for Silicon errata. Use clear-by-write instead
1778 * of clear-by-read. Reading with EICS will return the
1779 * interrupt causes without clearing, which later be done
1780 * with the write to EICR.
1782 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1783 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1785 if (eicr & IXGBE_EICR_LSC)
1786 ixgbe_check_lsc(adapter);
1788 if (eicr & IXGBE_EICR_MAILBOX)
1789 ixgbe_msg_task(adapter);
1791 switch (hw->mac.type) {
1792 case ixgbe_mac_82599EB:
1793 /* Handle Flow Director Full threshold interrupt */
1794 if (eicr & IXGBE_EICR_FLOW_DIR) {
1796 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1797 /* Disable transmits before FDIR Re-initialization */
1798 netif_tx_stop_all_queues(netdev);
1799 for (i = 0; i < adapter->num_tx_queues; i++) {
1800 struct ixgbe_ring *tx_ring =
1801 adapter->tx_ring[i];
1802 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1804 schedule_work(&adapter->fdir_reinit_task);
1807 ixgbe_check_sfp_event(adapter, eicr);
1808 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1809 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1810 adapter->interrupt_event = eicr;
1811 schedule_work(&adapter->check_overtemp_task);
1818 ixgbe_check_fan_failure(adapter, eicr);
1820 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1821 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1826 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1830 struct ixgbe_hw *hw = &adapter->hw;
1832 switch (hw->mac.type) {
1833 case ixgbe_mac_82598EB:
1834 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1835 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1837 case ixgbe_mac_82599EB:
1838 mask = (qmask & 0xFFFFFFFF);
1840 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1841 mask = (qmask >> 32);
1843 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1848 /* skip the flush */
1851 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1855 struct ixgbe_hw *hw = &adapter->hw;
1857 switch (hw->mac.type) {
1858 case ixgbe_mac_82598EB:
1859 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1862 case ixgbe_mac_82599EB:
1863 mask = (qmask & 0xFFFFFFFF);
1865 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1866 mask = (qmask >> 32);
1868 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1873 /* skip the flush */
1876 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1878 struct ixgbe_q_vector *q_vector = data;
1879 struct ixgbe_adapter *adapter = q_vector->adapter;
1880 struct ixgbe_ring *tx_ring;
1883 if (!q_vector->txr_count)
1886 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1887 for (i = 0; i < q_vector->txr_count; i++) {
1888 tx_ring = adapter->tx_ring[r_idx];
1889 tx_ring->total_bytes = 0;
1890 tx_ring->total_packets = 0;
1891 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1895 /* EIAM disabled interrupts (on this vector) for us */
1896 napi_schedule(&q_vector->napi);
1902 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1904 * @data: pointer to our q_vector struct for this interrupt vector
1906 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1908 struct ixgbe_q_vector *q_vector = data;
1909 struct ixgbe_adapter *adapter = q_vector->adapter;
1910 struct ixgbe_ring *rx_ring;
1914 #ifdef CONFIG_IXGBE_DCA
1915 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1916 ixgbe_update_dca(q_vector);
1919 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1920 for (i = 0; i < q_vector->rxr_count; i++) {
1921 rx_ring = adapter->rx_ring[r_idx];
1922 rx_ring->total_bytes = 0;
1923 rx_ring->total_packets = 0;
1924 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1928 if (!q_vector->rxr_count)
1931 /* EIAM disabled interrupts (on this vector) for us */
1932 napi_schedule(&q_vector->napi);
1937 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1939 struct ixgbe_q_vector *q_vector = data;
1940 struct ixgbe_adapter *adapter = q_vector->adapter;
1941 struct ixgbe_ring *ring;
1945 if (!q_vector->txr_count && !q_vector->rxr_count)
1948 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1949 for (i = 0; i < q_vector->txr_count; i++) {
1950 ring = adapter->tx_ring[r_idx];
1951 ring->total_bytes = 0;
1952 ring->total_packets = 0;
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1957 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1958 for (i = 0; i < q_vector->rxr_count; i++) {
1959 ring = adapter->rx_ring[r_idx];
1960 ring->total_bytes = 0;
1961 ring->total_packets = 0;
1962 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1966 /* EIAM disabled interrupts (on this vector) for us */
1967 napi_schedule(&q_vector->napi);
1973 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1974 * @napi: napi struct with our devices info in it
1975 * @budget: amount of work driver is allowed to do this pass, in packets
1977 * This function is optimized for cleaning one queue only on a single
1980 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1982 struct ixgbe_q_vector *q_vector =
1983 container_of(napi, struct ixgbe_q_vector, napi);
1984 struct ixgbe_adapter *adapter = q_vector->adapter;
1985 struct ixgbe_ring *rx_ring = NULL;
1989 #ifdef CONFIG_IXGBE_DCA
1990 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1991 ixgbe_update_dca(q_vector);
1994 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1995 rx_ring = adapter->rx_ring[r_idx];
1997 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1999 /* If all Rx work done, exit the polling mode */
2000 if (work_done < budget) {
2001 napi_complete(napi);
2002 if (adapter->rx_itr_setting & 1)
2003 ixgbe_set_itr_msix(q_vector);
2004 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2005 ixgbe_irq_enable_queues(adapter,
2006 ((u64)1 << q_vector->v_idx));
2013 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2014 * @napi: napi struct with our devices info in it
2015 * @budget: amount of work driver is allowed to do this pass, in packets
2017 * This function will clean more than one rx queue associated with a
2020 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2022 struct ixgbe_q_vector *q_vector =
2023 container_of(napi, struct ixgbe_q_vector, napi);
2024 struct ixgbe_adapter *adapter = q_vector->adapter;
2025 struct ixgbe_ring *ring = NULL;
2026 int work_done = 0, i;
2028 bool tx_clean_complete = true;
2030 #ifdef CONFIG_IXGBE_DCA
2031 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2032 ixgbe_update_dca(q_vector);
2035 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2036 for (i = 0; i < q_vector->txr_count; i++) {
2037 ring = adapter->tx_ring[r_idx];
2038 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2039 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2043 /* attempt to distribute budget to each queue fairly, but don't allow
2044 * the budget to go below 1 because we'll exit polling */
2045 budget /= (q_vector->rxr_count ?: 1);
2046 budget = max(budget, 1);
2047 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2048 for (i = 0; i < q_vector->rxr_count; i++) {
2049 ring = adapter->rx_ring[r_idx];
2050 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2051 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2055 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2056 ring = adapter->rx_ring[r_idx];
2057 /* If all Rx work done, exit the polling mode */
2058 if (work_done < budget) {
2059 napi_complete(napi);
2060 if (adapter->rx_itr_setting & 1)
2061 ixgbe_set_itr_msix(q_vector);
2062 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2063 ixgbe_irq_enable_queues(adapter,
2064 ((u64)1 << q_vector->v_idx));
2072 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2073 * @napi: napi struct with our devices info in it
2074 * @budget: amount of work driver is allowed to do this pass, in packets
2076 * This function is optimized for cleaning one queue only on a single
2079 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2081 struct ixgbe_q_vector *q_vector =
2082 container_of(napi, struct ixgbe_q_vector, napi);
2083 struct ixgbe_adapter *adapter = q_vector->adapter;
2084 struct ixgbe_ring *tx_ring = NULL;
2088 #ifdef CONFIG_IXGBE_DCA
2089 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2090 ixgbe_update_dca(q_vector);
2093 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2094 tx_ring = adapter->tx_ring[r_idx];
2096 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2099 /* If all Tx work done, exit the polling mode */
2100 if (work_done < budget) {
2101 napi_complete(napi);
2102 if (adapter->tx_itr_setting & 1)
2103 ixgbe_set_itr_msix(q_vector);
2104 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2105 ixgbe_irq_enable_queues(adapter,
2106 ((u64)1 << q_vector->v_idx));
2112 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2115 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2116 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2118 set_bit(r_idx, q_vector->rxr_idx);
2119 q_vector->rxr_count++;
2120 rx_ring->q_vector = q_vector;
2123 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2126 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2127 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2129 set_bit(t_idx, q_vector->txr_idx);
2130 q_vector->txr_count++;
2131 tx_ring->q_vector = q_vector;
2135 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2136 * @adapter: board private structure to initialize
2138 * This function maps descriptor rings to the queue-specific vectors
2139 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2140 * one vector per ring/queue, but on a constrained vector budget, we
2141 * group the rings as "efficiently" as possible. You would add new
2142 * mapping configurations in here.
2144 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2148 int rxr_idx = 0, txr_idx = 0;
2149 int rxr_remaining = adapter->num_rx_queues;
2150 int txr_remaining = adapter->num_tx_queues;
2155 /* No mapping required if MSI-X is disabled. */
2156 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2159 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2162 * The ideal configuration...
2163 * We have enough vectors to map one per queue.
2165 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2166 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2167 map_vector_to_rxq(adapter, v_start, rxr_idx);
2169 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2170 map_vector_to_txq(adapter, v_start, txr_idx);
2176 * If we don't have enough vectors for a 1-to-1
2177 * mapping, we'll have to group them so there are
2178 * multiple queues per vector.
2180 /* Re-adjusting *qpv takes care of the remainder. */
2181 for (i = v_start; i < q_vectors; i++) {
2182 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2183 for (j = 0; j < rqpv; j++) {
2184 map_vector_to_rxq(adapter, i, rxr_idx);
2188 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2189 for (j = 0; j < tqpv; j++) {
2190 map_vector_to_txq(adapter, i, txr_idx);
2200 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2201 * @adapter: board private structure
2203 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2204 * interrupts from the kernel.
2206 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2208 struct net_device *netdev = adapter->netdev;
2209 irqreturn_t (*handler)(int, void *);
2210 int i, vector, q_vectors, err;
2213 /* Decrement for Other and TCP Timer vectors */
2214 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2216 err = ixgbe_map_rings_to_vectors(adapter);
2220 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2221 ? &ixgbe_msix_clean_many : \
2222 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2223 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2225 for (vector = 0; vector < q_vectors; vector++) {
2226 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2227 handler = SET_HANDLER(q_vector);
2229 if (handler == &ixgbe_msix_clean_rx) {
2230 sprintf(q_vector->name, "%s-%s-%d",
2231 netdev->name, "rx", ri++);
2232 } else if (handler == &ixgbe_msix_clean_tx) {
2233 sprintf(q_vector->name, "%s-%s-%d",
2234 netdev->name, "tx", ti++);
2235 } else if (handler == &ixgbe_msix_clean_many) {
2236 sprintf(q_vector->name, "%s-%s-%d",
2237 netdev->name, "TxRx", ri++);
2240 /* skip this unused q_vector */
2243 err = request_irq(adapter->msix_entries[vector].vector,
2244 handler, 0, q_vector->name,
2247 e_err(probe, "request_irq failed for MSIX interrupt "
2248 "Error: %d\n", err);
2249 goto free_queue_irqs;
2253 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2254 err = request_irq(adapter->msix_entries[vector].vector,
2255 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2257 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2258 goto free_queue_irqs;
2264 for (i = vector - 1; i >= 0; i--)
2265 free_irq(adapter->msix_entries[--vector].vector,
2266 adapter->q_vector[i]);
2267 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2268 pci_disable_msix(adapter->pdev);
2269 kfree(adapter->msix_entries);
2270 adapter->msix_entries = NULL;
2274 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2276 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2277 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2278 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2279 u32 new_itr = q_vector->eitr;
2282 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2284 tx_ring->total_packets,
2285 tx_ring->total_bytes);
2286 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2288 rx_ring->total_packets,
2289 rx_ring->total_bytes);
2291 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2293 switch (current_itr) {
2294 /* counts and packets in update_itr are dependent on these numbers */
2295 case lowest_latency:
2299 new_itr = 20000; /* aka hwitr = ~200 */
2308 if (new_itr != q_vector->eitr) {
2309 /* do an exponential smoothing */
2310 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2312 /* save the algorithm value here */
2313 q_vector->eitr = new_itr;
2315 ixgbe_write_eitr(q_vector);
2320 * ixgbe_irq_enable - Enable default interrupt generation settings
2321 * @adapter: board private structure
2323 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2328 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2329 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2330 mask |= IXGBE_EIMS_GPI_SDP0;
2331 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2332 mask |= IXGBE_EIMS_GPI_SDP1;
2333 switch (adapter->hw.mac.type) {
2334 case ixgbe_mac_82599EB:
2335 mask |= IXGBE_EIMS_ECC;
2336 mask |= IXGBE_EIMS_GPI_SDP1;
2337 mask |= IXGBE_EIMS_GPI_SDP2;
2338 if (adapter->num_vfs)
2339 mask |= IXGBE_EIMS_MAILBOX;
2344 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2345 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2346 mask |= IXGBE_EIMS_FLOW_DIR;
2348 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2350 ixgbe_irq_enable_queues(adapter, ~0);
2352 IXGBE_WRITE_FLUSH(&adapter->hw);
2354 if (adapter->num_vfs > 32) {
2355 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2356 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2361 * ixgbe_intr - legacy mode Interrupt Handler
2362 * @irq: interrupt number
2363 * @data: pointer to a network interface device structure
2365 static irqreturn_t ixgbe_intr(int irq, void *data)
2367 struct net_device *netdev = data;
2368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2369 struct ixgbe_hw *hw = &adapter->hw;
2370 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2374 * Workaround for silicon errata on 82598. Mask the interrupts
2375 * before the read of EICR.
2377 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2379 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2380 * therefore no explict interrupt disable is necessary */
2381 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2384 * shared interrupt alert!
2385 * make sure interrupts are enabled because the read will
2386 * have disabled interrupts due to EIAM
2387 * finish the workaround of silicon errata on 82598. Unmask
2388 * the interrupt that we masked before the EICR read.
2390 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2391 ixgbe_irq_enable(adapter, true, true);
2392 return IRQ_NONE; /* Not our interrupt */
2395 if (eicr & IXGBE_EICR_LSC)
2396 ixgbe_check_lsc(adapter);
2398 switch (hw->mac.type) {
2399 case ixgbe_mac_82599EB:
2400 ixgbe_check_sfp_event(adapter, eicr);
2401 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2402 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2403 adapter->interrupt_event = eicr;
2404 schedule_work(&adapter->check_overtemp_task);
2411 ixgbe_check_fan_failure(adapter, eicr);
2413 if (napi_schedule_prep(&(q_vector->napi))) {
2414 adapter->tx_ring[0]->total_packets = 0;
2415 adapter->tx_ring[0]->total_bytes = 0;
2416 adapter->rx_ring[0]->total_packets = 0;
2417 adapter->rx_ring[0]->total_bytes = 0;
2418 /* would disable interrupts here but EIAM disabled it */
2419 __napi_schedule(&(q_vector->napi));
2423 * re-enable link(maybe) and non-queue interrupts, no flush.
2424 * ixgbe_poll will re-enable the queue interrupts
2427 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2428 ixgbe_irq_enable(adapter, false, false);
2433 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2435 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2437 for (i = 0; i < q_vectors; i++) {
2438 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2439 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2440 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2441 q_vector->rxr_count = 0;
2442 q_vector->txr_count = 0;
2447 * ixgbe_request_irq - initialize interrupts
2448 * @adapter: board private structure
2450 * Attempts to configure interrupts using the best available
2451 * capabilities of the hardware and kernel.
2453 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2455 struct net_device *netdev = adapter->netdev;
2458 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2459 err = ixgbe_request_msix_irqs(adapter);
2460 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2461 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2462 netdev->name, netdev);
2464 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2465 netdev->name, netdev);
2469 e_err(probe, "request_irq failed, Error %d\n", err);
2474 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2476 struct net_device *netdev = adapter->netdev;
2478 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2481 q_vectors = adapter->num_msix_vectors;
2484 free_irq(adapter->msix_entries[i].vector, netdev);
2487 for (; i >= 0; i--) {
2488 free_irq(adapter->msix_entries[i].vector,
2489 adapter->q_vector[i]);
2492 ixgbe_reset_q_vectors(adapter);
2494 free_irq(adapter->pdev->irq, netdev);
2499 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2500 * @adapter: board private structure
2502 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2504 switch (adapter->hw.mac.type) {
2505 case ixgbe_mac_82598EB:
2506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2508 case ixgbe_mac_82599EB:
2509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2510 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2511 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2512 if (adapter->num_vfs > 32)
2513 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2518 IXGBE_WRITE_FLUSH(&adapter->hw);
2519 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2521 for (i = 0; i < adapter->num_msix_vectors; i++)
2522 synchronize_irq(adapter->msix_entries[i].vector);
2524 synchronize_irq(adapter->pdev->irq);
2529 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2532 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2534 struct ixgbe_hw *hw = &adapter->hw;
2536 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2537 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2539 ixgbe_set_ivar(adapter, 0, 0, 0);
2540 ixgbe_set_ivar(adapter, 1, 0, 0);
2542 map_vector_to_rxq(adapter, 0, 0);
2543 map_vector_to_txq(adapter, 0, 0);
2545 e_info(hw, "Legacy interrupt IVAR setup done\n");
2549 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2550 * @adapter: board private structure
2551 * @ring: structure containing ring specific data
2553 * Configure the Tx descriptor ring after a reset.
2555 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2556 struct ixgbe_ring *ring)
2558 struct ixgbe_hw *hw = &adapter->hw;
2559 u64 tdba = ring->dma;
2562 u8 reg_idx = ring->reg_idx;
2564 /* disable queue to avoid issues while updating state */
2565 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2566 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2567 txdctl & ~IXGBE_TXDCTL_ENABLE);
2568 IXGBE_WRITE_FLUSH(hw);
2570 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2571 (tdba & DMA_BIT_MASK(32)));
2572 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2573 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2574 ring->count * sizeof(union ixgbe_adv_tx_desc));
2575 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2576 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2577 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2579 /* configure fetching thresholds */
2580 if (adapter->rx_itr_setting == 0) {
2581 /* cannot set wthresh when itr==0 */
2582 txdctl &= ~0x007F0000;
2584 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2585 txdctl |= (8 << 16);
2587 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2588 /* PThresh workaround for Tx hang with DFP enabled. */
2592 /* reinitialize flowdirector state */
2593 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2594 adapter->atr_sample_rate) {
2595 ring->atr_sample_rate = adapter->atr_sample_rate;
2596 ring->atr_count = 0;
2597 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2599 ring->atr_sample_rate = 0;
2603 txdctl |= IXGBE_TXDCTL_ENABLE;
2604 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2606 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2607 if (hw->mac.type == ixgbe_mac_82598EB &&
2608 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2611 /* poll to verify queue is enabled */
2614 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2615 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2617 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2620 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2622 struct ixgbe_hw *hw = &adapter->hw;
2626 if (hw->mac.type == ixgbe_mac_82598EB)
2629 /* disable the arbiter while setting MTQC */
2630 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2631 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2632 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2634 /* set transmit pool layout */
2635 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2636 switch (adapter->flags & mask) {
2638 case (IXGBE_FLAG_SRIOV_ENABLED):
2639 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2640 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2643 case (IXGBE_FLAG_DCB_ENABLED):
2644 /* We enable 8 traffic classes, DCB only */
2645 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2646 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2650 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2654 /* re-enable the arbiter */
2655 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2656 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2660 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2661 * @adapter: board private structure
2663 * Configure the Tx unit of the MAC after a reset.
2665 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2667 struct ixgbe_hw *hw = &adapter->hw;
2671 ixgbe_setup_mtqc(adapter);
2673 if (hw->mac.type != ixgbe_mac_82598EB) {
2674 /* DMATXCTL.EN must be before Tx queues are enabled */
2675 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2676 dmatxctl |= IXGBE_DMATXCTL_TE;
2677 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2680 /* Setup the HW Tx Head and Tail descriptor pointers */
2681 for (i = 0; i < adapter->num_tx_queues; i++)
2682 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2685 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2687 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2688 struct ixgbe_ring *rx_ring)
2691 u8 reg_idx = rx_ring->reg_idx;
2693 switch (adapter->hw.mac.type) {
2694 case ixgbe_mac_82598EB: {
2695 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2696 const int mask = feature[RING_F_RSS].mask;
2697 reg_idx = reg_idx & mask;
2700 case ixgbe_mac_82599EB:
2705 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2707 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2708 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2709 if (adapter->num_vfs)
2710 srrctl |= IXGBE_SRRCTL_DROP_EN;
2712 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2713 IXGBE_SRRCTL_BSIZEHDR_MASK;
2715 if (ring_is_ps_enabled(rx_ring)) {
2716 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2717 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2719 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2721 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2723 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2724 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2725 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2728 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2731 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2733 struct ixgbe_hw *hw = &adapter->hw;
2734 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2735 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2736 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2737 u32 mrqc = 0, reta = 0;
2742 /* Fill out hash function seeds */
2743 for (i = 0; i < 10; i++)
2744 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2746 /* Fill out redirection table */
2747 for (i = 0, j = 0; i < 128; i++, j++) {
2748 if (j == adapter->ring_feature[RING_F_RSS].indices)
2750 /* reta = 4-byte sliding window of
2751 * 0x00..(indices-1)(indices-1)00..etc. */
2752 reta = (reta << 8) | (j * 0x11);
2754 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2757 /* Disable indicating checksum in descriptor, enables RSS hash */
2758 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2759 rxcsum |= IXGBE_RXCSUM_PCSD;
2760 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2762 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2763 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2765 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2766 #ifdef CONFIG_IXGBE_DCB
2767 | IXGBE_FLAG_DCB_ENABLED
2769 | IXGBE_FLAG_SRIOV_ENABLED
2773 case (IXGBE_FLAG_RSS_ENABLED):
2774 mrqc = IXGBE_MRQC_RSSEN;
2776 case (IXGBE_FLAG_SRIOV_ENABLED):
2777 mrqc = IXGBE_MRQC_VMDQEN;
2779 #ifdef CONFIG_IXGBE_DCB
2780 case (IXGBE_FLAG_DCB_ENABLED):
2781 mrqc = IXGBE_MRQC_RT8TCEN;
2783 #endif /* CONFIG_IXGBE_DCB */
2788 /* Perform hash on these packet types */
2789 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2790 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2791 | IXGBE_MRQC_RSS_FIELD_IPV6
2792 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2794 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2798 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2799 * @adapter: address of board private structure
2800 * @index: index of ring to set
2802 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2803 struct ixgbe_ring *ring)
2805 struct ixgbe_hw *hw = &adapter->hw;
2808 u8 reg_idx = ring->reg_idx;
2810 if (!ring_is_rsc_enabled(ring))
2813 rx_buf_len = ring->rx_buf_len;
2814 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2815 rscctrl |= IXGBE_RSCCTL_RSCEN;
2817 * we must limit the number of descriptors so that the
2818 * total size of max desc * buf_len is not greater
2821 if (ring_is_ps_enabled(ring)) {
2822 #if (MAX_SKB_FRAGS > 16)
2823 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2824 #elif (MAX_SKB_FRAGS > 8)
2825 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2826 #elif (MAX_SKB_FRAGS > 4)
2827 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2829 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2832 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2833 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2834 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2835 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2837 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2839 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2843 * ixgbe_set_uta - Set unicast filter table address
2844 * @adapter: board private structure
2846 * The unicast table address is a register array of 32-bit registers.
2847 * The table is meant to be used in a way similar to how the MTA is used
2848 * however due to certain limitations in the hardware it is necessary to
2849 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2850 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2852 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2854 struct ixgbe_hw *hw = &adapter->hw;
2857 /* The UTA table only exists on 82599 hardware and newer */
2858 if (hw->mac.type < ixgbe_mac_82599EB)
2861 /* we only need to do this if VMDq is enabled */
2862 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2865 for (i = 0; i < 128; i++)
2866 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2869 #define IXGBE_MAX_RX_DESC_POLL 10
2870 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2871 struct ixgbe_ring *ring)
2873 struct ixgbe_hw *hw = &adapter->hw;
2874 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2876 u8 reg_idx = ring->reg_idx;
2878 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2879 if (hw->mac.type == ixgbe_mac_82598EB &&
2880 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2885 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2886 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2889 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2890 "the polling period\n", reg_idx);
2894 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2895 struct ixgbe_ring *ring)
2897 struct ixgbe_hw *hw = &adapter->hw;
2898 u64 rdba = ring->dma;
2900 u8 reg_idx = ring->reg_idx;
2902 /* disable queue to avoid issues while updating state */
2903 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2904 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2905 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2906 IXGBE_WRITE_FLUSH(hw);
2908 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2909 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2910 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2911 ring->count * sizeof(union ixgbe_adv_rx_desc));
2912 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2913 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2914 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2916 ixgbe_configure_srrctl(adapter, ring);
2917 ixgbe_configure_rscctl(adapter, ring);
2919 if (hw->mac.type == ixgbe_mac_82598EB) {
2921 * enable cache line friendly hardware writes:
2922 * PTHRESH=32 descriptors (half the internal cache),
2923 * this also removes ugly rx_no_buffer_count increment
2924 * HTHRESH=4 descriptors (to minimize latency on fetch)
2925 * WTHRESH=8 burst writeback up to two cache lines
2927 rxdctl &= ~0x3FFFFF;
2931 /* enable receive descriptor ring */
2932 rxdctl |= IXGBE_RXDCTL_ENABLE;
2933 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2935 ixgbe_rx_desc_queue_enable(adapter, ring);
2936 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2939 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2941 struct ixgbe_hw *hw = &adapter->hw;
2944 /* PSRTYPE must be initialized in non 82598 adapters */
2945 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2946 IXGBE_PSRTYPE_UDPHDR |
2947 IXGBE_PSRTYPE_IPV4HDR |
2948 IXGBE_PSRTYPE_L2HDR |
2949 IXGBE_PSRTYPE_IPV6HDR;
2951 if (hw->mac.type == ixgbe_mac_82598EB)
2954 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2955 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2957 for (p = 0; p < adapter->num_rx_pools; p++)
2958 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2962 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2964 struct ixgbe_hw *hw = &adapter->hw;
2967 u32 reg_offset, vf_shift;
2970 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2973 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2974 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2975 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2976 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2978 vf_shift = adapter->num_vfs % 32;
2979 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2981 /* Enable only the PF's pool for Tx/Rx */
2982 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2983 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2984 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2985 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2986 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2988 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2989 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2992 * Set up VF register offsets for selected VT Mode,
2993 * i.e. 32 or 64 VFs for SR-IOV
2995 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2996 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2997 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2998 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3000 /* enable Tx loopback for VF/PF communication */
3001 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3004 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3006 struct ixgbe_hw *hw = &adapter->hw;
3007 struct net_device *netdev = adapter->netdev;
3008 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3010 struct ixgbe_ring *rx_ring;
3014 /* Decide whether to use packet split mode or not */
3015 /* Do not use packet split if we're in SR-IOV Mode */
3016 if (!adapter->num_vfs)
3017 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3019 /* Set the RX buffer length according to the mode */
3020 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3021 rx_buf_len = IXGBE_RX_HDR_SIZE;
3023 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3024 (netdev->mtu <= ETH_DATA_LEN))
3025 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3027 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3031 /* adjust max frame to be able to do baby jumbo for FCoE */
3032 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3033 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3034 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3036 #endif /* IXGBE_FCOE */
3037 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3038 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3039 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3040 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3042 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3045 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3046 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3047 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3048 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3051 * Setup the HW Rx Head and Tail Descriptor Pointers and
3052 * the Base and Length of the Rx Descriptor Ring
3054 for (i = 0; i < adapter->num_rx_queues; i++) {
3055 rx_ring = adapter->rx_ring[i];
3056 rx_ring->rx_buf_len = rx_buf_len;
3058 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3059 set_ring_ps_enabled(rx_ring);
3061 clear_ring_ps_enabled(rx_ring);
3063 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3064 set_ring_rsc_enabled(rx_ring);
3066 clear_ring_rsc_enabled(rx_ring);
3069 if (netdev->features & NETIF_F_FCOE_MTU) {
3070 struct ixgbe_ring_feature *f;
3071 f = &adapter->ring_feature[RING_F_FCOE];
3072 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3073 clear_ring_ps_enabled(rx_ring);
3074 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3075 rx_ring->rx_buf_len =
3076 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3077 } else if (!ring_is_rsc_enabled(rx_ring) &&
3078 !ring_is_ps_enabled(rx_ring)) {
3079 rx_ring->rx_buf_len =
3080 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3083 #endif /* IXGBE_FCOE */
3087 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3089 struct ixgbe_hw *hw = &adapter->hw;
3090 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3092 switch (hw->mac.type) {
3093 case ixgbe_mac_82598EB:
3095 * For VMDq support of different descriptor types or
3096 * buffer sizes through the use of multiple SRRCTL
3097 * registers, RDRXCTL.MVMEN must be set to 1
3099 * also, the manual doesn't mention it clearly but DCA hints
3100 * will only use queue 0's tags unless this bit is set. Side
3101 * effects of setting this bit are only that SRRCTL must be
3102 * fully programmed [0..15]
3104 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3106 case ixgbe_mac_82599EB:
3107 /* Disable RSC for ACK packets */
3108 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3109 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3110 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3111 /* hardware requires some bits to be set by default */
3112 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3113 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3116 /* We should do nothing since we don't know this hardware */
3120 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3124 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3125 * @adapter: board private structure
3127 * Configure the Rx unit of the MAC after a reset.
3129 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3131 struct ixgbe_hw *hw = &adapter->hw;
3135 /* disable receives while setting up the descriptors */
3136 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3137 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3139 ixgbe_setup_psrtype(adapter);
3140 ixgbe_setup_rdrxctl(adapter);
3142 /* Program registers for the distribution of queues */
3143 ixgbe_setup_mrqc(adapter);
3145 ixgbe_set_uta(adapter);
3147 /* set_rx_buffer_len must be called before ring initialization */
3148 ixgbe_set_rx_buffer_len(adapter);
3151 * Setup the HW Rx Head and Tail Descriptor Pointers and
3152 * the Base and Length of the Rx Descriptor Ring
3154 for (i = 0; i < adapter->num_rx_queues; i++)
3155 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3157 /* disable drop enable for 82598 parts */
3158 if (hw->mac.type == ixgbe_mac_82598EB)
3159 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3161 /* enable all receives */
3162 rxctrl |= IXGBE_RXCTRL_RXEN;
3163 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3166 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3168 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3169 struct ixgbe_hw *hw = &adapter->hw;
3170 int pool_ndx = adapter->num_vfs;
3172 /* add VID to filter table */
3173 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3174 set_bit(vid, adapter->active_vlans);
3177 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3179 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3180 struct ixgbe_hw *hw = &adapter->hw;
3181 int pool_ndx = adapter->num_vfs;
3183 /* remove VID from filter table */
3184 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3185 clear_bit(vid, adapter->active_vlans);
3189 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3190 * @adapter: driver data
3192 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3194 struct ixgbe_hw *hw = &adapter->hw;
3197 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3198 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3199 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3203 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3204 * @adapter: driver data
3206 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3208 struct ixgbe_hw *hw = &adapter->hw;
3211 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3212 vlnctrl |= IXGBE_VLNCTRL_VFE;
3213 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3214 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3218 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3219 * @adapter: driver data
3221 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3223 struct ixgbe_hw *hw = &adapter->hw;
3227 switch (hw->mac.type) {
3228 case ixgbe_mac_82598EB:
3229 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3230 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3231 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3233 case ixgbe_mac_82599EB:
3234 for (i = 0; i < adapter->num_rx_queues; i++) {
3235 j = adapter->rx_ring[i]->reg_idx;
3236 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3237 vlnctrl &= ~IXGBE_RXDCTL_VME;
3238 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3247 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3248 * @adapter: driver data
3250 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3252 struct ixgbe_hw *hw = &adapter->hw;
3256 switch (hw->mac.type) {
3257 case ixgbe_mac_82598EB:
3258 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3259 vlnctrl |= IXGBE_VLNCTRL_VME;
3260 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3262 case ixgbe_mac_82599EB:
3263 for (i = 0; i < adapter->num_rx_queues; i++) {
3264 j = adapter->rx_ring[i]->reg_idx;
3265 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3266 vlnctrl |= IXGBE_RXDCTL_VME;
3267 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3275 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3279 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3281 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3282 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3286 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3287 * @netdev: network interface device structure
3289 * Writes unicast address list to the RAR table.
3290 * Returns: -ENOMEM on failure/insufficient address space
3291 * 0 on no addresses written
3292 * X on writing X addresses to the RAR table
3294 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3296 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3297 struct ixgbe_hw *hw = &adapter->hw;
3298 unsigned int vfn = adapter->num_vfs;
3299 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3302 /* return ENOMEM indicating insufficient memory for addresses */
3303 if (netdev_uc_count(netdev) > rar_entries)
3306 if (!netdev_uc_empty(netdev) && rar_entries) {
3307 struct netdev_hw_addr *ha;
3308 /* return error if we do not support writing to RAR table */
3309 if (!hw->mac.ops.set_rar)
3312 netdev_for_each_uc_addr(ha, netdev) {
3315 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3320 /* write the addresses in reverse order to avoid write combining */
3321 for (; rar_entries > 0 ; rar_entries--)
3322 hw->mac.ops.clear_rar(hw, rar_entries);
3328 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3329 * @netdev: network interface device structure
3331 * The set_rx_method entry point is called whenever the unicast/multicast
3332 * address list or the network interface flags are updated. This routine is
3333 * responsible for configuring the hardware for proper unicast, multicast and
3336 void ixgbe_set_rx_mode(struct net_device *netdev)
3338 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3339 struct ixgbe_hw *hw = &adapter->hw;
3340 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3343 /* Check for Promiscuous and All Multicast modes */
3345 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3347 /* set all bits that we expect to always be set */
3348 fctrl |= IXGBE_FCTRL_BAM;
3349 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3350 fctrl |= IXGBE_FCTRL_PMCF;
3352 /* clear the bits we are changing the status of */
3353 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3355 if (netdev->flags & IFF_PROMISC) {
3356 hw->addr_ctrl.user_set_promisc = true;
3357 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3358 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3359 /* don't hardware filter vlans in promisc mode */
3360 ixgbe_vlan_filter_disable(adapter);
3362 if (netdev->flags & IFF_ALLMULTI) {
3363 fctrl |= IXGBE_FCTRL_MPE;
3364 vmolr |= IXGBE_VMOLR_MPE;
3367 * Write addresses to the MTA, if the attempt fails
3368 * then we should just turn on promiscous mode so
3369 * that we can at least receive multicast traffic
3371 hw->mac.ops.update_mc_addr_list(hw, netdev);
3372 vmolr |= IXGBE_VMOLR_ROMPE;
3374 ixgbe_vlan_filter_enable(adapter);
3375 hw->addr_ctrl.user_set_promisc = false;
3377 * Write addresses to available RAR registers, if there is not
3378 * sufficient space to store all the addresses then enable
3379 * unicast promiscous mode
3381 count = ixgbe_write_uc_addr_list(netdev);
3383 fctrl |= IXGBE_FCTRL_UPE;
3384 vmolr |= IXGBE_VMOLR_ROPE;
3388 if (adapter->num_vfs) {
3389 ixgbe_restore_vf_multicasts(adapter);
3390 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3391 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3393 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3396 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3398 if (netdev->features & NETIF_F_HW_VLAN_RX)
3399 ixgbe_vlan_strip_enable(adapter);
3401 ixgbe_vlan_strip_disable(adapter);
3404 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3407 struct ixgbe_q_vector *q_vector;
3408 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3410 /* legacy and MSI only use one vector */
3411 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3414 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3415 struct napi_struct *napi;
3416 q_vector = adapter->q_vector[q_idx];
3417 napi = &q_vector->napi;
3418 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3419 if (!q_vector->rxr_count || !q_vector->txr_count) {
3420 if (q_vector->txr_count == 1)
3421 napi->poll = &ixgbe_clean_txonly;
3422 else if (q_vector->rxr_count == 1)
3423 napi->poll = &ixgbe_clean_rxonly;
3431 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3434 struct ixgbe_q_vector *q_vector;
3435 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3437 /* legacy and MSI only use one vector */
3438 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3441 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3442 q_vector = adapter->q_vector[q_idx];
3443 napi_disable(&q_vector->napi);
3447 #ifdef CONFIG_IXGBE_DCB
3449 * ixgbe_configure_dcb - Configure DCB hardware
3450 * @adapter: ixgbe adapter struct
3452 * This is called by the driver on open to configure the DCB hardware.
3453 * This is also called by the gennetlink interface when reconfiguring
3456 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3458 struct ixgbe_hw *hw = &adapter->hw;
3459 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3461 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3462 if (hw->mac.type == ixgbe_mac_82598EB)
3463 netif_set_gso_max_size(adapter->netdev, 65536);
3467 if (hw->mac.type == ixgbe_mac_82598EB)
3468 netif_set_gso_max_size(adapter->netdev, 32768);
3471 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3472 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3475 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3477 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3480 /* Enable VLAN tag insert/strip */
3481 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3483 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3485 /* reconfigure the hardware */
3486 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3490 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3492 struct net_device *netdev = adapter->netdev;
3493 struct ixgbe_hw *hw = &adapter->hw;
3496 #ifdef CONFIG_IXGBE_DCB
3497 ixgbe_configure_dcb(adapter);
3500 ixgbe_set_rx_mode(netdev);
3501 ixgbe_restore_vlan(adapter);
3504 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3505 ixgbe_configure_fcoe(adapter);
3507 #endif /* IXGBE_FCOE */
3508 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3509 for (i = 0; i < adapter->num_tx_queues; i++)
3510 adapter->tx_ring[i]->atr_sample_rate =
3511 adapter->atr_sample_rate;
3512 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3513 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3514 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3516 ixgbe_configure_virtualization(adapter);
3518 ixgbe_configure_tx(adapter);
3519 ixgbe_configure_rx(adapter);
3522 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3524 switch (hw->phy.type) {
3525 case ixgbe_phy_sfp_avago:
3526 case ixgbe_phy_sfp_ftl:
3527 case ixgbe_phy_sfp_intel:
3528 case ixgbe_phy_sfp_unknown:
3529 case ixgbe_phy_sfp_passive_tyco:
3530 case ixgbe_phy_sfp_passive_unknown:
3531 case ixgbe_phy_sfp_active_unknown:
3532 case ixgbe_phy_sfp_ftl_active:
3540 * ixgbe_sfp_link_config - set up SFP+ link
3541 * @adapter: pointer to private adapter struct
3543 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3545 struct ixgbe_hw *hw = &adapter->hw;
3547 if (hw->phy.multispeed_fiber) {
3549 * In multispeed fiber setups, the device may not have
3550 * had a physical connection when the driver loaded.
3551 * If that's the case, the initial link configuration
3552 * couldn't get the MAC into 10G or 1G mode, so we'll
3553 * never have a link status change interrupt fire.
3554 * We need to try and force an autonegotiation
3555 * session, then bring up link.
3557 hw->mac.ops.setup_sfp(hw);
3558 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3559 schedule_work(&adapter->multispeed_fiber_task);
3562 * Direct Attach Cu and non-multispeed fiber modules
3563 * still need to be configured properly prior to
3566 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3567 schedule_work(&adapter->sfp_config_module_task);
3572 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3573 * @hw: pointer to private hardware struct
3575 * Returns 0 on success, negative on failure
3577 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3580 bool negotiation, link_up = false;
3581 u32 ret = IXGBE_ERR_LINK_SETUP;
3583 if (hw->mac.ops.check_link)
3584 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3589 if (hw->mac.ops.get_link_capabilities)
3590 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3595 if (hw->mac.ops.setup_link)
3596 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3601 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3603 struct ixgbe_hw *hw = &adapter->hw;
3606 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3607 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3609 gpie |= IXGBE_GPIE_EIAME;
3611 * use EIAM to auto-mask when MSI-X interrupt is asserted
3612 * this saves a register write for every interrupt
3614 switch (hw->mac.type) {
3615 case ixgbe_mac_82598EB:
3616 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3619 case ixgbe_mac_82599EB:
3620 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3621 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3625 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3626 * specifically only auto mask tx and rx interrupts */
3627 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3630 /* XXX: to interrupt immediately for EICS writes, enable this */
3631 /* gpie |= IXGBE_GPIE_EIMEN; */
3633 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3634 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3635 gpie |= IXGBE_GPIE_VTMODE_64;
3638 /* Enable fan failure interrupt */
3639 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3640 gpie |= IXGBE_SDP1_GPIEN;
3642 if (hw->mac.type == ixgbe_mac_82599EB)
3643 gpie |= IXGBE_SDP1_GPIEN;
3644 gpie |= IXGBE_SDP2_GPIEN;
3646 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3649 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3651 struct ixgbe_hw *hw = &adapter->hw;
3655 ixgbe_get_hw_control(adapter);
3656 ixgbe_setup_gpie(adapter);
3658 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3659 ixgbe_configure_msix(adapter);
3661 ixgbe_configure_msi_and_legacy(adapter);
3663 /* enable the optics */
3664 if (hw->phy.multispeed_fiber && hw->mac.ops.enable_tx_laser)
3665 hw->mac.ops.enable_tx_laser(hw);
3667 clear_bit(__IXGBE_DOWN, &adapter->state);
3668 ixgbe_napi_enable_all(adapter);
3670 if (ixgbe_is_sfp(hw)) {
3671 ixgbe_sfp_link_config(adapter);
3673 err = ixgbe_non_sfp_link_config(hw);
3675 e_err(probe, "link_config FAILED %d\n", err);
3678 /* clear any pending interrupts, may auto mask */
3679 IXGBE_READ_REG(hw, IXGBE_EICR);
3680 ixgbe_irq_enable(adapter, true, true);
3683 * If this adapter has a fan, check to see if we had a failure
3684 * before we enabled the interrupt.
3686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3687 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3688 if (esdp & IXGBE_ESDP_SDP1)
3689 e_crit(drv, "Fan has stopped, replace the adapter\n");
3693 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3694 * arrived before interrupts were enabled but after probe. Such
3695 * devices wouldn't have their type identified yet. We need to
3696 * kick off the SFP+ module setup first, then try to bring up link.
3697 * If we're not hot-pluggable SFP+, we just need to configure link
3700 if (hw->phy.type == ixgbe_phy_unknown)
3701 schedule_work(&adapter->sfp_config_module_task);
3703 /* enable transmits */
3704 netif_tx_start_all_queues(adapter->netdev);
3706 /* bring the link up in the watchdog, this could race with our first
3707 * link up interrupt but shouldn't be a problem */
3708 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3709 adapter->link_check_timeout = jiffies;
3710 mod_timer(&adapter->watchdog_timer, jiffies);
3712 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3713 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3714 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3715 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3720 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3722 WARN_ON(in_interrupt());
3723 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3725 ixgbe_down(adapter);
3727 * If SR-IOV enabled then wait a bit before bringing the adapter
3728 * back up to give the VFs time to respond to the reset. The
3729 * two second wait is based upon the watchdog timer cycle in
3732 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3735 clear_bit(__IXGBE_RESETTING, &adapter->state);
3738 int ixgbe_up(struct ixgbe_adapter *adapter)
3740 /* hardware has been reset, we need to reload some things */
3741 ixgbe_configure(adapter);
3743 return ixgbe_up_complete(adapter);
3746 void ixgbe_reset(struct ixgbe_adapter *adapter)
3748 struct ixgbe_hw *hw = &adapter->hw;
3751 err = hw->mac.ops.init_hw(hw);
3754 case IXGBE_ERR_SFP_NOT_PRESENT:
3756 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3757 e_dev_err("master disable timed out\n");
3759 case IXGBE_ERR_EEPROM_VERSION:
3760 /* We are running on a pre-production device, log a warning */
3761 e_dev_warn("This device is a pre-production adapter/LOM. "
3762 "Please be aware there may be issuesassociated with "
3763 "your hardware. If you are experiencing problems "
3764 "please contact your Intel or hardware "
3765 "representative who provided you with this "
3769 e_dev_err("Hardware Error: %d\n", err);
3772 /* reprogram the RAR[0] in case user changed it. */
3773 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3778 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3779 * @rx_ring: ring to free buffers from
3781 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3783 struct device *dev = rx_ring->dev;
3787 /* ring already cleared, nothing to do */
3788 if (!rx_ring->rx_buffer_info)
3791 /* Free all the Rx ring sk_buffs */
3792 for (i = 0; i < rx_ring->count; i++) {
3793 struct ixgbe_rx_buffer *rx_buffer_info;
3795 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3796 if (rx_buffer_info->dma) {
3797 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3798 rx_ring->rx_buf_len,
3800 rx_buffer_info->dma = 0;
3802 if (rx_buffer_info->skb) {
3803 struct sk_buff *skb = rx_buffer_info->skb;
3804 rx_buffer_info->skb = NULL;
3806 struct sk_buff *this = skb;
3807 if (IXGBE_RSC_CB(this)->delay_unmap) {
3808 dma_unmap_single(dev,
3809 IXGBE_RSC_CB(this)->dma,
3810 rx_ring->rx_buf_len,
3812 IXGBE_RSC_CB(this)->dma = 0;
3813 IXGBE_RSC_CB(skb)->delay_unmap = false;
3816 dev_kfree_skb(this);
3819 if (!rx_buffer_info->page)
3821 if (rx_buffer_info->page_dma) {
3822 dma_unmap_page(dev, rx_buffer_info->page_dma,
3823 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3824 rx_buffer_info->page_dma = 0;
3826 put_page(rx_buffer_info->page);
3827 rx_buffer_info->page = NULL;
3828 rx_buffer_info->page_offset = 0;
3831 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3832 memset(rx_ring->rx_buffer_info, 0, size);
3834 /* Zero out the descriptor ring */
3835 memset(rx_ring->desc, 0, rx_ring->size);
3837 rx_ring->next_to_clean = 0;
3838 rx_ring->next_to_use = 0;
3842 * ixgbe_clean_tx_ring - Free Tx Buffers
3843 * @tx_ring: ring to be cleaned
3845 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3847 struct ixgbe_tx_buffer *tx_buffer_info;
3851 /* ring already cleared, nothing to do */
3852 if (!tx_ring->tx_buffer_info)
3855 /* Free all the Tx ring sk_buffs */
3856 for (i = 0; i < tx_ring->count; i++) {
3857 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3858 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3861 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3862 memset(tx_ring->tx_buffer_info, 0, size);
3864 /* Zero out the descriptor ring */
3865 memset(tx_ring->desc, 0, tx_ring->size);
3867 tx_ring->next_to_use = 0;
3868 tx_ring->next_to_clean = 0;
3872 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3873 * @adapter: board private structure
3875 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3879 for (i = 0; i < adapter->num_rx_queues; i++)
3880 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3884 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3885 * @adapter: board private structure
3887 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3891 for (i = 0; i < adapter->num_tx_queues; i++)
3892 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3895 void ixgbe_down(struct ixgbe_adapter *adapter)
3897 struct net_device *netdev = adapter->netdev;
3898 struct ixgbe_hw *hw = &adapter->hw;
3902 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3904 /* signal that we are down to the interrupt handler */
3905 set_bit(__IXGBE_DOWN, &adapter->state);
3907 /* disable receive for all VFs and wait one second */
3908 if (adapter->num_vfs) {
3909 /* ping all the active vfs to let them know we are going down */
3910 ixgbe_ping_all_vfs(adapter);
3912 /* Disable all VFTE/VFRE TX/RX */
3913 ixgbe_disable_tx_rx(adapter);
3915 /* Mark all the VFs as inactive */
3916 for (i = 0 ; i < adapter->num_vfs; i++)
3917 adapter->vfinfo[i].clear_to_send = 0;
3920 /* disable receives */
3921 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3922 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3924 IXGBE_WRITE_FLUSH(hw);
3927 netif_tx_stop_all_queues(netdev);
3929 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3930 del_timer_sync(&adapter->sfp_timer);
3931 del_timer_sync(&adapter->watchdog_timer);
3932 cancel_work_sync(&adapter->watchdog_task);
3934 netif_carrier_off(netdev);
3935 netif_tx_disable(netdev);
3937 ixgbe_irq_disable(adapter);
3939 ixgbe_napi_disable_all(adapter);
3941 /* Cleanup the affinity_hint CPU mask memory and callback */
3942 for (i = 0; i < num_q_vectors; i++) {
3943 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3944 /* clear the affinity_mask in the IRQ descriptor */
3945 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3946 /* release the CPU mask memory */
3947 free_cpumask_var(q_vector->affinity_mask);
3950 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3951 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3952 cancel_work_sync(&adapter->fdir_reinit_task);
3954 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3955 cancel_work_sync(&adapter->check_overtemp_task);
3957 /* disable transmits in the hardware now that interrupts are off */
3958 for (i = 0; i < adapter->num_tx_queues; i++) {
3959 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3960 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3961 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
3962 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3964 /* Disable the Tx DMA engine on 82599 */
3965 switch (hw->mac.type) {
3966 case ixgbe_mac_82599EB:
3967 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3968 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3969 ~IXGBE_DMATXCTL_TE));
3975 /* power down the optics */
3976 if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
3977 hw->mac.ops.disable_tx_laser(hw);
3979 /* clear n-tuple filters that are cached */
3980 ethtool_ntuple_flush(netdev);
3982 if (!pci_channel_offline(adapter->pdev))
3983 ixgbe_reset(adapter);
3984 ixgbe_clean_all_tx_rings(adapter);
3985 ixgbe_clean_all_rx_rings(adapter);
3987 #ifdef CONFIG_IXGBE_DCA
3988 /* since we reset the hardware DCA settings were cleared */
3989 ixgbe_setup_dca(adapter);
3994 * ixgbe_poll - NAPI Rx polling callback
3995 * @napi: structure for representing this polling device
3996 * @budget: how many packets driver is allowed to clean
3998 * This function is used for legacy and MSI, NAPI mode
4000 static int ixgbe_poll(struct napi_struct *napi, int budget)
4002 struct ixgbe_q_vector *q_vector =
4003 container_of(napi, struct ixgbe_q_vector, napi);
4004 struct ixgbe_adapter *adapter = q_vector->adapter;
4005 int tx_clean_complete, work_done = 0;
4007 #ifdef CONFIG_IXGBE_DCA
4008 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4009 ixgbe_update_dca(q_vector);
4012 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4013 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4015 if (!tx_clean_complete)
4018 /* If budget not fully consumed, exit the polling mode */
4019 if (work_done < budget) {
4020 napi_complete(napi);
4021 if (adapter->rx_itr_setting & 1)
4022 ixgbe_set_itr(adapter);
4023 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4024 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4030 * ixgbe_tx_timeout - Respond to a Tx Hang
4031 * @netdev: network interface device structure
4033 static void ixgbe_tx_timeout(struct net_device *netdev)
4035 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4037 /* Do the reset outside of interrupt context */
4038 schedule_work(&adapter->reset_task);
4041 static void ixgbe_reset_task(struct work_struct *work)
4043 struct ixgbe_adapter *adapter;
4044 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4046 /* If we're already down or resetting, just bail */
4047 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4048 test_bit(__IXGBE_RESETTING, &adapter->state))
4051 adapter->tx_timeout_count++;
4053 ixgbe_dump(adapter);
4054 netdev_err(adapter->netdev, "Reset adapter\n");
4055 ixgbe_reinit_locked(adapter);
4058 #ifdef CONFIG_IXGBE_DCB
4059 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4062 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4064 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4068 adapter->num_rx_queues = f->indices;
4069 adapter->num_tx_queues = f->indices;
4077 * ixgbe_set_rss_queues: Allocate queues for RSS
4078 * @adapter: board private structure to initialize
4080 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4081 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4084 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4087 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4089 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4091 adapter->num_rx_queues = f->indices;
4092 adapter->num_tx_queues = f->indices;
4102 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4103 * @adapter: board private structure to initialize
4105 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4106 * to the original CPU that initiated the Tx session. This runs in addition
4107 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4108 * Rx load across CPUs using RSS.
4111 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4114 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4116 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4119 /* Flow Director must have RSS enabled */
4120 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4121 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4122 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4123 adapter->num_tx_queues = f_fdir->indices;
4124 adapter->num_rx_queues = f_fdir->indices;
4127 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4128 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4135 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4136 * @adapter: board private structure to initialize
4138 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4139 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4140 * rx queues out of the max number of rx queues, instead, it is used as the
4141 * index of the first rx queue used by FCoE.
4144 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4147 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4149 f->indices = min((int)num_online_cpus(), f->indices);
4150 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4151 adapter->num_rx_queues = 1;
4152 adapter->num_tx_queues = 1;
4153 #ifdef CONFIG_IXGBE_DCB
4154 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4155 e_info(probe, "FCoE enabled with DCB\n");
4156 ixgbe_set_dcb_queues(adapter);
4159 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4160 e_info(probe, "FCoE enabled with RSS\n");
4161 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4162 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4163 ixgbe_set_fdir_queues(adapter);
4165 ixgbe_set_rss_queues(adapter);
4167 /* adding FCoE rx rings to the end */
4168 f->mask = adapter->num_rx_queues;
4169 adapter->num_rx_queues += f->indices;
4170 adapter->num_tx_queues += f->indices;
4178 #endif /* IXGBE_FCOE */
4180 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4181 * @adapter: board private structure to initialize
4183 * IOV doesn't actually use anything, so just NAK the
4184 * request for now and let the other queue routines
4185 * figure out what to do.
4187 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4193 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4194 * @adapter: board private structure to initialize
4196 * This is the top level queue allocation routine. The order here is very
4197 * important, starting with the "most" number of features turned on at once,
4198 * and ending with the smallest set of features. This way large combinations
4199 * can be allocated if they're turned on, and smaller combinations are the
4200 * fallthrough conditions.
4203 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4205 /* Start with base case */
4206 adapter->num_rx_queues = 1;
4207 adapter->num_tx_queues = 1;
4208 adapter->num_rx_pools = adapter->num_rx_queues;
4209 adapter->num_rx_queues_per_pool = 1;
4211 if (ixgbe_set_sriov_queues(adapter))
4215 if (ixgbe_set_fcoe_queues(adapter))
4218 #endif /* IXGBE_FCOE */
4219 #ifdef CONFIG_IXGBE_DCB
4220 if (ixgbe_set_dcb_queues(adapter))
4224 if (ixgbe_set_fdir_queues(adapter))
4227 if (ixgbe_set_rss_queues(adapter))
4230 /* fallback to base case */
4231 adapter->num_rx_queues = 1;
4232 adapter->num_tx_queues = 1;
4235 /* Notify the stack of the (possibly) reduced queue counts. */
4236 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4237 return netif_set_real_num_rx_queues(adapter->netdev,
4238 adapter->num_rx_queues);
4241 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4244 int err, vector_threshold;
4246 /* We'll want at least 3 (vector_threshold):
4249 * 3) Other (Link Status Change, etc.)
4250 * 4) TCP Timer (optional)
4252 vector_threshold = MIN_MSIX_COUNT;
4254 /* The more we get, the more we will assign to Tx/Rx Cleanup
4255 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4256 * Right now, we simply care about how many we'll get; we'll
4257 * set them up later while requesting irq's.
4259 while (vectors >= vector_threshold) {
4260 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4262 if (!err) /* Success in acquiring all requested vectors. */
4265 vectors = 0; /* Nasty failure, quit now */
4266 else /* err == number of vectors we should try again with */
4270 if (vectors < vector_threshold) {
4271 /* Can't allocate enough MSI-X interrupts? Oh well.
4272 * This just means we'll go with either a single MSI
4273 * vector or fall back to legacy interrupts.
4275 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4276 "Unable to allocate MSI-X interrupts\n");
4277 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4278 kfree(adapter->msix_entries);
4279 adapter->msix_entries = NULL;
4281 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4283 * Adjust for only the vectors we'll use, which is minimum
4284 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4285 * vectors we were allocated.
4287 adapter->num_msix_vectors = min(vectors,
4288 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4293 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4294 * @adapter: board private structure to initialize
4296 * Cache the descriptor ring offsets for RSS to the assigned rings.
4299 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4303 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4306 for (i = 0; i < adapter->num_rx_queues; i++)
4307 adapter->rx_ring[i]->reg_idx = i;
4308 for (i = 0; i < adapter->num_tx_queues; i++)
4309 adapter->tx_ring[i]->reg_idx = i;
4314 #ifdef CONFIG_IXGBE_DCB
4316 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4317 * @adapter: board private structure to initialize
4319 * Cache the descriptor ring offsets for DCB to the assigned rings.
4322 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4326 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4328 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4331 /* the number of queues is assumed to be symmetric */
4332 switch (adapter->hw.mac.type) {
4333 case ixgbe_mac_82598EB:
4334 for (i = 0; i < dcb_i; i++) {
4335 adapter->rx_ring[i]->reg_idx = i << 3;
4336 adapter->tx_ring[i]->reg_idx = i << 2;
4340 case ixgbe_mac_82599EB:
4343 * Tx TC0 starts at: descriptor queue 0
4344 * Tx TC1 starts at: descriptor queue 32
4345 * Tx TC2 starts at: descriptor queue 64
4346 * Tx TC3 starts at: descriptor queue 80
4347 * Tx TC4 starts at: descriptor queue 96
4348 * Tx TC5 starts at: descriptor queue 104
4349 * Tx TC6 starts at: descriptor queue 112
4350 * Tx TC7 starts at: descriptor queue 120
4352 * Rx TC0-TC7 are offset by 16 queues each
4354 for (i = 0; i < 3; i++) {
4355 adapter->tx_ring[i]->reg_idx = i << 5;
4356 adapter->rx_ring[i]->reg_idx = i << 4;
4358 for ( ; i < 5; i++) {
4359 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4360 adapter->rx_ring[i]->reg_idx = i << 4;
4362 for ( ; i < dcb_i; i++) {
4363 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4364 adapter->rx_ring[i]->reg_idx = i << 4;
4367 } else if (dcb_i == 4) {
4369 * Tx TC0 starts at: descriptor queue 0
4370 * Tx TC1 starts at: descriptor queue 64
4371 * Tx TC2 starts at: descriptor queue 96
4372 * Tx TC3 starts at: descriptor queue 112
4374 * Rx TC0-TC3 are offset by 32 queues each
4376 adapter->tx_ring[0]->reg_idx = 0;
4377 adapter->tx_ring[1]->reg_idx = 64;
4378 adapter->tx_ring[2]->reg_idx = 96;
4379 adapter->tx_ring[3]->reg_idx = 112;
4380 for (i = 0 ; i < dcb_i; i++)
4381 adapter->rx_ring[i]->reg_idx = i << 5;
4393 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4394 * @adapter: board private structure to initialize
4396 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4399 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4404 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4405 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4406 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4407 for (i = 0; i < adapter->num_rx_queues; i++)
4408 adapter->rx_ring[i]->reg_idx = i;
4409 for (i = 0; i < adapter->num_tx_queues; i++)
4410 adapter->tx_ring[i]->reg_idx = i;
4419 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4420 * @adapter: board private structure to initialize
4422 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4425 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4427 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4429 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4431 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4434 #ifdef CONFIG_IXGBE_DCB
4435 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4436 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4438 ixgbe_cache_ring_dcb(adapter);
4439 /* find out queues in TC for FCoE */
4440 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4441 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4443 * In 82599, the number of Tx queues for each traffic
4444 * class for both 8-TC and 4-TC modes are:
4445 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4446 * 8 TCs: 32 32 16 16 8 8 8 8
4447 * 4 TCs: 64 64 32 32
4448 * We have max 8 queues for FCoE, where 8 the is
4449 * FCoE redirection table size. If TC for FCoE is
4450 * less than or equal to TC3, we have enough queues
4451 * to add max of 8 queues for FCoE, so we start FCoE
4452 * Tx queue from the next one, i.e., reg_idx + 1.
4453 * If TC for FCoE is above TC3, implying 8 TC mode,
4454 * and we need 8 for FCoE, we have to take all queues
4455 * in that traffic class for FCoE.
4457 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4460 #endif /* CONFIG_IXGBE_DCB */
4461 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4462 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4463 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4464 ixgbe_cache_ring_fdir(adapter);
4466 ixgbe_cache_ring_rss(adapter);
4468 fcoe_rx_i = f->mask;
4469 fcoe_tx_i = f->mask;
4471 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4472 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4473 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4478 #endif /* IXGBE_FCOE */
4480 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4481 * @adapter: board private structure to initialize
4483 * SR-IOV doesn't use any descriptor rings but changes the default if
4484 * no other mapping is used.
4487 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4489 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4490 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4491 if (adapter->num_vfs)
4498 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4499 * @adapter: board private structure to initialize
4501 * Once we know the feature-set enabled for the device, we'll cache
4502 * the register offset the descriptor ring is assigned to.
4504 * Note, the order the various feature calls is important. It must start with
4505 * the "most" features enabled at the same time, then trickle down to the
4506 * least amount of features turned on at once.
4508 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4510 /* start with default case */
4511 adapter->rx_ring[0]->reg_idx = 0;
4512 adapter->tx_ring[0]->reg_idx = 0;
4514 if (ixgbe_cache_ring_sriov(adapter))
4518 if (ixgbe_cache_ring_fcoe(adapter))
4521 #endif /* IXGBE_FCOE */
4522 #ifdef CONFIG_IXGBE_DCB
4523 if (ixgbe_cache_ring_dcb(adapter))
4527 if (ixgbe_cache_ring_fdir(adapter))
4530 if (ixgbe_cache_ring_rss(adapter))
4535 * ixgbe_alloc_queues - Allocate memory for all rings
4536 * @adapter: board private structure to initialize
4538 * We allocate one ring per queue at run-time since we don't know the
4539 * number of queues at compile-time. The polling_netdev array is
4540 * intended for Multiqueue, but should work fine with a single queue.
4542 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4546 int orig_node = adapter->node;
4548 for (i = 0; i < adapter->num_tx_queues; i++) {
4549 struct ixgbe_ring *ring = adapter->tx_ring[i];
4550 if (orig_node == -1) {
4551 int cur_node = next_online_node(adapter->node);
4552 if (cur_node == MAX_NUMNODES)
4553 cur_node = first_online_node;
4554 adapter->node = cur_node;
4556 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4559 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4561 goto err_tx_ring_allocation;
4562 ring->count = adapter->tx_ring_count;
4563 ring->queue_index = i;
4564 ring->dev = &adapter->pdev->dev;
4565 ring->netdev = adapter->netdev;
4566 ring->numa_node = adapter->node;
4568 adapter->tx_ring[i] = ring;
4571 /* Restore the adapter's original node */
4572 adapter->node = orig_node;
4574 rx_count = adapter->rx_ring_count;
4575 for (i = 0; i < adapter->num_rx_queues; i++) {
4576 struct ixgbe_ring *ring = adapter->rx_ring[i];
4577 if (orig_node == -1) {
4578 int cur_node = next_online_node(adapter->node);
4579 if (cur_node == MAX_NUMNODES)
4580 cur_node = first_online_node;
4581 adapter->node = cur_node;
4583 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4586 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4588 goto err_rx_ring_allocation;
4589 ring->count = rx_count;
4590 ring->queue_index = i;
4591 ring->dev = &adapter->pdev->dev;
4592 ring->netdev = adapter->netdev;
4593 ring->numa_node = adapter->node;
4595 adapter->rx_ring[i] = ring;
4598 /* Restore the adapter's original node */
4599 adapter->node = orig_node;
4601 ixgbe_cache_ring_register(adapter);
4605 err_rx_ring_allocation:
4606 for (i = 0; i < adapter->num_tx_queues; i++)
4607 kfree(adapter->tx_ring[i]);
4608 err_tx_ring_allocation:
4613 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4614 * @adapter: board private structure to initialize
4616 * Attempt to configure the interrupts using the best available
4617 * capabilities of the hardware and the kernel.
4619 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4621 struct ixgbe_hw *hw = &adapter->hw;
4623 int vector, v_budget;
4626 * It's easy to be greedy for MSI-X vectors, but it really
4627 * doesn't do us much good if we have a lot more vectors
4628 * than CPU's. So let's be conservative and only ask for
4629 * (roughly) the same number of vectors as there are CPU's.
4631 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4632 (int)num_online_cpus()) + NON_Q_VECTORS;
4635 * At the same time, hardware can only support a maximum of
4636 * hw.mac->max_msix_vectors vectors. With features
4637 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4638 * descriptor queues supported by our device. Thus, we cap it off in
4639 * those rare cases where the cpu count also exceeds our vector limit.
4641 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4643 /* A failure in MSI-X entry allocation isn't fatal, but it does
4644 * mean we disable MSI-X capabilities of the adapter. */
4645 adapter->msix_entries = kcalloc(v_budget,
4646 sizeof(struct msix_entry), GFP_KERNEL);
4647 if (adapter->msix_entries) {
4648 for (vector = 0; vector < v_budget; vector++)
4649 adapter->msix_entries[vector].entry = vector;
4651 ixgbe_acquire_msix_vectors(adapter, v_budget);
4653 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4657 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4658 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4659 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4660 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4661 adapter->atr_sample_rate = 0;
4662 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4663 ixgbe_disable_sriov(adapter);
4665 err = ixgbe_set_num_queues(adapter);
4669 err = pci_enable_msi(adapter->pdev);
4671 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4673 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4674 "Unable to allocate MSI interrupt, "
4675 "falling back to legacy. Error: %d\n", err);
4685 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4686 * @adapter: board private structure to initialize
4688 * We allocate one q_vector per queue interrupt. If allocation fails we
4691 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4693 int q_idx, num_q_vectors;
4694 struct ixgbe_q_vector *q_vector;
4696 int (*poll)(struct napi_struct *, int);
4698 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4699 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4700 napi_vectors = adapter->num_rx_queues;
4701 poll = &ixgbe_clean_rxtx_many;
4708 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4709 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4710 GFP_KERNEL, adapter->node);
4712 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4716 q_vector->adapter = adapter;
4717 if (q_vector->txr_count && !q_vector->rxr_count)
4718 q_vector->eitr = adapter->tx_eitr_param;
4720 q_vector->eitr = adapter->rx_eitr_param;
4721 q_vector->v_idx = q_idx;
4722 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4723 adapter->q_vector[q_idx] = q_vector;
4731 q_vector = adapter->q_vector[q_idx];
4732 netif_napi_del(&q_vector->napi);
4734 adapter->q_vector[q_idx] = NULL;
4740 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4741 * @adapter: board private structure to initialize
4743 * This function frees the memory allocated to the q_vectors. In addition if
4744 * NAPI is enabled it will delete any references to the NAPI struct prior
4745 * to freeing the q_vector.
4747 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4749 int q_idx, num_q_vectors;
4751 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4752 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4756 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4757 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4758 adapter->q_vector[q_idx] = NULL;
4759 netif_napi_del(&q_vector->napi);
4764 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4766 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4767 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4768 pci_disable_msix(adapter->pdev);
4769 kfree(adapter->msix_entries);
4770 adapter->msix_entries = NULL;
4771 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4772 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4773 pci_disable_msi(adapter->pdev);
4778 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4779 * @adapter: board private structure to initialize
4781 * We determine which interrupt scheme to use based on...
4782 * - Kernel support (MSI, MSI-X)
4783 * - which can be user-defined (via MODULE_PARAM)
4784 * - Hardware queue count (num_*_queues)
4785 * - defined by miscellaneous hardware support/features (RSS, etc.)
4787 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4791 /* Number of supported queues */
4792 err = ixgbe_set_num_queues(adapter);
4796 err = ixgbe_set_interrupt_capability(adapter);
4798 e_dev_err("Unable to setup interrupt capabilities\n");
4799 goto err_set_interrupt;
4802 err = ixgbe_alloc_q_vectors(adapter);
4804 e_dev_err("Unable to allocate memory for queue vectors\n");
4805 goto err_alloc_q_vectors;
4808 err = ixgbe_alloc_queues(adapter);
4810 e_dev_err("Unable to allocate memory for queues\n");
4811 goto err_alloc_queues;
4814 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4815 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4816 adapter->num_rx_queues, adapter->num_tx_queues);
4818 set_bit(__IXGBE_DOWN, &adapter->state);
4823 ixgbe_free_q_vectors(adapter);
4824 err_alloc_q_vectors:
4825 ixgbe_reset_interrupt_capability(adapter);
4830 static void ring_free_rcu(struct rcu_head *head)
4832 kfree(container_of(head, struct ixgbe_ring, rcu));
4836 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4837 * @adapter: board private structure to clear interrupt scheme on
4839 * We go through and clear interrupt specific resources and reset the structure
4840 * to pre-load conditions
4842 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4846 for (i = 0; i < adapter->num_tx_queues; i++) {
4847 kfree(adapter->tx_ring[i]);
4848 adapter->tx_ring[i] = NULL;
4850 for (i = 0; i < adapter->num_rx_queues; i++) {
4851 struct ixgbe_ring *ring = adapter->rx_ring[i];
4853 /* ixgbe_get_stats64() might access this ring, we must wait
4854 * a grace period before freeing it.
4856 call_rcu(&ring->rcu, ring_free_rcu);
4857 adapter->rx_ring[i] = NULL;
4860 ixgbe_free_q_vectors(adapter);
4861 ixgbe_reset_interrupt_capability(adapter);
4865 * ixgbe_sfp_timer - worker thread to find a missing module
4866 * @data: pointer to our adapter struct
4868 static void ixgbe_sfp_timer(unsigned long data)
4870 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4873 * Do the sfp_timer outside of interrupt context due to the
4874 * delays that sfp+ detection requires
4876 schedule_work(&adapter->sfp_task);
4880 * ixgbe_sfp_task - worker thread to find a missing module
4881 * @work: pointer to work_struct containing our data
4883 static void ixgbe_sfp_task(struct work_struct *work)
4885 struct ixgbe_adapter *adapter = container_of(work,
4886 struct ixgbe_adapter,
4888 struct ixgbe_hw *hw = &adapter->hw;
4890 if ((hw->phy.type == ixgbe_phy_nl) &&
4891 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4892 s32 ret = hw->phy.ops.identify_sfp(hw);
4893 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4895 ret = hw->phy.ops.reset(hw);
4896 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4897 e_dev_err("failed to initialize because an unsupported "
4898 "SFP+ module type was detected.\n");
4899 e_dev_err("Reload the driver after installing a "
4900 "supported module.\n");
4901 unregister_netdev(adapter->netdev);
4903 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4905 /* don't need this routine any more */
4906 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4910 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4911 mod_timer(&adapter->sfp_timer,
4912 round_jiffies(jiffies + (2 * HZ)));
4916 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4917 * @adapter: board private structure to initialize
4919 * ixgbe_sw_init initializes the Adapter private data structure.
4920 * Fields are initialized based on PCI device information and
4921 * OS network device settings (MTU size).
4923 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4925 struct ixgbe_hw *hw = &adapter->hw;
4926 struct pci_dev *pdev = adapter->pdev;
4927 struct net_device *dev = adapter->netdev;
4929 #ifdef CONFIG_IXGBE_DCB
4931 struct tc_configuration *tc;
4933 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4935 /* PCI config space info */
4937 hw->vendor_id = pdev->vendor;
4938 hw->device_id = pdev->device;
4939 hw->revision_id = pdev->revision;
4940 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4941 hw->subsystem_device_id = pdev->subsystem_device;
4943 /* Set capability flags */
4944 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4945 adapter->ring_feature[RING_F_RSS].indices = rss;
4946 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4947 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4948 switch (hw->mac.type) {
4949 case ixgbe_mac_82598EB:
4950 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4951 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4952 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4954 case ixgbe_mac_82599EB:
4955 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4956 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4957 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4958 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4959 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4960 if (dev->features & NETIF_F_NTUPLE) {
4961 /* Flow Director perfect filter enabled */
4962 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4963 adapter->atr_sample_rate = 0;
4964 spin_lock_init(&adapter->fdir_perfect_lock);
4966 /* Flow Director hash filters enabled */
4967 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4968 adapter->atr_sample_rate = 20;
4970 adapter->ring_feature[RING_F_FDIR].indices =
4971 IXGBE_MAX_FDIR_INDICES;
4972 adapter->fdir_pballoc = 0;
4974 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4975 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4976 adapter->ring_feature[RING_F_FCOE].indices = 0;
4977 #ifdef CONFIG_IXGBE_DCB
4978 /* Default traffic class to use for FCoE */
4979 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4980 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4982 #endif /* IXGBE_FCOE */
4988 #ifdef CONFIG_IXGBE_DCB
4989 /* Configure DCB traffic classes */
4990 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4991 tc = &adapter->dcb_cfg.tc_config[j];
4992 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4993 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4994 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4995 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4996 tc->dcb_pfc = pfc_disabled;
4998 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4999 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5000 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5001 adapter->dcb_cfg.pfc_mode_enable = false;
5002 adapter->dcb_cfg.round_robin_enable = false;
5003 adapter->dcb_set_bitmap = 0x00;
5004 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5005 adapter->ring_feature[RING_F_DCB].indices);
5009 /* default flow control settings */
5010 hw->fc.requested_mode = ixgbe_fc_full;
5011 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5013 adapter->last_lfc_mode = hw->fc.current_mode;
5015 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5016 hw->fc.low_water = FC_LOW_WATER(max_frame);
5017 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5018 hw->fc.send_xon = true;
5019 hw->fc.disable_fc_autoneg = false;
5021 /* enable itr by default in dynamic mode */
5022 adapter->rx_itr_setting = 1;
5023 adapter->rx_eitr_param = 20000;
5024 adapter->tx_itr_setting = 1;
5025 adapter->tx_eitr_param = 10000;
5027 /* set defaults for eitr in MegaBytes */
5028 adapter->eitr_low = 10;
5029 adapter->eitr_high = 20;
5031 /* set default ring sizes */
5032 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5033 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5035 /* initialize eeprom parameters */
5036 if (ixgbe_init_eeprom_params_generic(hw)) {
5037 e_dev_err("EEPROM initialization failed\n");
5041 /* enable rx csum by default */
5042 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5044 /* get assigned NUMA node */
5045 adapter->node = dev_to_node(&pdev->dev);
5047 set_bit(__IXGBE_DOWN, &adapter->state);
5053 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5054 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5056 * Return 0 on success, negative on failure
5058 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5060 struct device *dev = tx_ring->dev;
5063 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5064 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
5065 if (!tx_ring->tx_buffer_info)
5066 tx_ring->tx_buffer_info = vmalloc(size);
5067 if (!tx_ring->tx_buffer_info)
5069 memset(tx_ring->tx_buffer_info, 0, size);
5071 /* round up to nearest 4K */
5072 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5073 tx_ring->size = ALIGN(tx_ring->size, 4096);
5075 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5076 &tx_ring->dma, GFP_KERNEL);
5080 tx_ring->next_to_use = 0;
5081 tx_ring->next_to_clean = 0;
5082 tx_ring->work_limit = tx_ring->count;
5086 vfree(tx_ring->tx_buffer_info);
5087 tx_ring->tx_buffer_info = NULL;
5088 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5093 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5094 * @adapter: board private structure
5096 * If this function returns with an error, then it's possible one or
5097 * more of the rings is populated (while the rest are not). It is the
5098 * callers duty to clean those orphaned rings.
5100 * Return 0 on success, negative on failure
5102 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5106 for (i = 0; i < adapter->num_tx_queues; i++) {
5107 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5110 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5118 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5119 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5121 * Returns 0 on success, negative on failure
5123 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5125 struct device *dev = rx_ring->dev;
5128 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5129 rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5130 if (!rx_ring->rx_buffer_info)
5131 rx_ring->rx_buffer_info = vmalloc(size);
5132 if (!rx_ring->rx_buffer_info)
5134 memset(rx_ring->rx_buffer_info, 0, size);
5136 /* Round up to nearest 4K */
5137 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5138 rx_ring->size = ALIGN(rx_ring->size, 4096);
5140 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5141 &rx_ring->dma, GFP_KERNEL);
5146 rx_ring->next_to_clean = 0;
5147 rx_ring->next_to_use = 0;
5151 vfree(rx_ring->rx_buffer_info);
5152 rx_ring->rx_buffer_info = NULL;
5153 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5158 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5159 * @adapter: board private structure
5161 * If this function returns with an error, then it's possible one or
5162 * more of the rings is populated (while the rest are not). It is the
5163 * callers duty to clean those orphaned rings.
5165 * Return 0 on success, negative on failure
5167 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5171 for (i = 0; i < adapter->num_rx_queues; i++) {
5172 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5175 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5183 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5184 * @tx_ring: Tx descriptor ring for a specific queue
5186 * Free all transmit software resources
5188 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5190 ixgbe_clean_tx_ring(tx_ring);
5192 vfree(tx_ring->tx_buffer_info);
5193 tx_ring->tx_buffer_info = NULL;
5195 /* if not set, then don't free */
5199 dma_free_coherent(tx_ring->dev, tx_ring->size,
5200 tx_ring->desc, tx_ring->dma);
5202 tx_ring->desc = NULL;
5206 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5207 * @adapter: board private structure
5209 * Free all transmit software resources
5211 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5215 for (i = 0; i < adapter->num_tx_queues; i++)
5216 if (adapter->tx_ring[i]->desc)
5217 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5221 * ixgbe_free_rx_resources - Free Rx Resources
5222 * @rx_ring: ring to clean the resources from
5224 * Free all receive software resources
5226 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5228 ixgbe_clean_rx_ring(rx_ring);
5230 vfree(rx_ring->rx_buffer_info);
5231 rx_ring->rx_buffer_info = NULL;
5233 /* if not set, then don't free */
5237 dma_free_coherent(rx_ring->dev, rx_ring->size,
5238 rx_ring->desc, rx_ring->dma);
5240 rx_ring->desc = NULL;
5244 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5245 * @adapter: board private structure
5247 * Free all receive software resources
5249 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5253 for (i = 0; i < adapter->num_rx_queues; i++)
5254 if (adapter->rx_ring[i]->desc)
5255 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5259 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5260 * @netdev: network interface device structure
5261 * @new_mtu: new value for maximum frame size
5263 * Returns 0 on success, negative on failure
5265 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5267 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5268 struct ixgbe_hw *hw = &adapter->hw;
5269 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5271 /* MTU < 68 is an error and causes problems on some kernels */
5272 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5275 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5276 /* must set new MTU before calling down or up */
5277 netdev->mtu = new_mtu;
5279 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5280 hw->fc.low_water = FC_LOW_WATER(max_frame);
5282 if (netif_running(netdev))
5283 ixgbe_reinit_locked(adapter);
5289 * ixgbe_open - Called when a network interface is made active
5290 * @netdev: network interface device structure
5292 * Returns 0 on success, negative value on failure
5294 * The open entry point is called when a network interface is made
5295 * active by the system (IFF_UP). At this point all resources needed
5296 * for transmit and receive operations are allocated, the interrupt
5297 * handler is registered with the OS, the watchdog timer is started,
5298 * and the stack is notified that the interface is ready.
5300 static int ixgbe_open(struct net_device *netdev)
5302 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5305 /* disallow open during test */
5306 if (test_bit(__IXGBE_TESTING, &adapter->state))
5309 netif_carrier_off(netdev);
5311 /* allocate transmit descriptors */
5312 err = ixgbe_setup_all_tx_resources(adapter);
5316 /* allocate receive descriptors */
5317 err = ixgbe_setup_all_rx_resources(adapter);
5321 ixgbe_configure(adapter);
5323 err = ixgbe_request_irq(adapter);
5327 err = ixgbe_up_complete(adapter);
5331 netif_tx_start_all_queues(netdev);
5336 ixgbe_release_hw_control(adapter);
5337 ixgbe_free_irq(adapter);
5340 ixgbe_free_all_rx_resources(adapter);
5342 ixgbe_free_all_tx_resources(adapter);
5343 ixgbe_reset(adapter);
5349 * ixgbe_close - Disables a network interface
5350 * @netdev: network interface device structure
5352 * Returns 0, this is not allowed to fail
5354 * The close entry point is called when an interface is de-activated
5355 * by the OS. The hardware is still under the drivers control, but
5356 * needs to be disabled. A global MAC reset is issued to stop the
5357 * hardware, and all transmit and receive resources are freed.
5359 static int ixgbe_close(struct net_device *netdev)
5361 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5363 ixgbe_down(adapter);
5364 ixgbe_free_irq(adapter);
5366 ixgbe_free_all_tx_resources(adapter);
5367 ixgbe_free_all_rx_resources(adapter);
5369 ixgbe_release_hw_control(adapter);
5375 static int ixgbe_resume(struct pci_dev *pdev)
5377 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5378 struct net_device *netdev = adapter->netdev;
5381 pci_set_power_state(pdev, PCI_D0);
5382 pci_restore_state(pdev);
5384 * pci_restore_state clears dev->state_saved so call
5385 * pci_save_state to restore it.
5387 pci_save_state(pdev);
5389 err = pci_enable_device_mem(pdev);
5391 e_dev_err("Cannot enable PCI device from suspend\n");
5394 pci_set_master(pdev);
5396 pci_wake_from_d3(pdev, false);
5398 err = ixgbe_init_interrupt_scheme(adapter);
5400 e_dev_err("Cannot initialize interrupts for device\n");
5404 ixgbe_reset(adapter);
5406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5408 if (netif_running(netdev)) {
5409 err = ixgbe_open(netdev);
5414 netif_device_attach(netdev);
5418 #endif /* CONFIG_PM */
5420 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5422 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5423 struct net_device *netdev = adapter->netdev;
5424 struct ixgbe_hw *hw = &adapter->hw;
5426 u32 wufc = adapter->wol;
5431 netif_device_detach(netdev);
5433 if (netif_running(netdev)) {
5434 ixgbe_down(adapter);
5435 ixgbe_free_irq(adapter);
5436 ixgbe_free_all_tx_resources(adapter);
5437 ixgbe_free_all_rx_resources(adapter);
5440 ixgbe_clear_interrupt_scheme(adapter);
5443 retval = pci_save_state(pdev);
5449 ixgbe_set_rx_mode(netdev);
5451 /* turn on all-multi mode if wake on multicast is enabled */
5452 if (wufc & IXGBE_WUFC_MC) {
5453 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5454 fctrl |= IXGBE_FCTRL_MPE;
5455 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5458 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5459 ctrl |= IXGBE_CTRL_GIO_DIS;
5460 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5462 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5464 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5465 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5468 switch (hw->mac.type) {
5469 case ixgbe_mac_82598EB:
5470 pci_wake_from_d3(pdev, false);
5472 case ixgbe_mac_82599EB:
5473 pci_wake_from_d3(pdev, !!wufc);
5479 *enable_wake = !!wufc;
5481 ixgbe_release_hw_control(adapter);
5483 pci_disable_device(pdev);
5489 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5494 retval = __ixgbe_shutdown(pdev, &wake);
5499 pci_prepare_to_sleep(pdev);
5501 pci_wake_from_d3(pdev, false);
5502 pci_set_power_state(pdev, PCI_D3hot);
5507 #endif /* CONFIG_PM */
5509 static void ixgbe_shutdown(struct pci_dev *pdev)
5513 __ixgbe_shutdown(pdev, &wake);
5515 if (system_state == SYSTEM_POWER_OFF) {
5516 pci_wake_from_d3(pdev, wake);
5517 pci_set_power_state(pdev, PCI_D3hot);
5522 * ixgbe_update_stats - Update the board statistics counters.
5523 * @adapter: board private structure
5525 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5527 struct net_device *netdev = adapter->netdev;
5528 struct ixgbe_hw *hw = &adapter->hw;
5529 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5531 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5532 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5533 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5534 u64 bytes = 0, packets = 0;
5536 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5537 test_bit(__IXGBE_RESETTING, &adapter->state))
5540 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5543 for (i = 0; i < 16; i++)
5544 adapter->hw_rx_no_dma_resources +=
5545 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5546 for (i = 0; i < adapter->num_rx_queues; i++) {
5547 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5548 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5550 adapter->rsc_total_count = rsc_count;
5551 adapter->rsc_total_flush = rsc_flush;
5554 for (i = 0; i < adapter->num_rx_queues; i++) {
5555 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5556 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5557 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5558 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5559 bytes += rx_ring->stats.bytes;
5560 packets += rx_ring->stats.packets;
5562 adapter->non_eop_descs = non_eop_descs;
5563 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5564 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5565 netdev->stats.rx_bytes = bytes;
5566 netdev->stats.rx_packets = packets;
5570 /* gather some stats to the adapter struct that are per queue */
5571 for (i = 0; i < adapter->num_tx_queues; i++) {
5572 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5573 restart_queue += tx_ring->tx_stats.restart_queue;
5574 tx_busy += tx_ring->tx_stats.tx_busy;
5575 bytes += tx_ring->stats.bytes;
5576 packets += tx_ring->stats.packets;
5578 adapter->restart_queue = restart_queue;
5579 adapter->tx_busy = tx_busy;
5580 netdev->stats.tx_bytes = bytes;
5581 netdev->stats.tx_packets = packets;
5583 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5584 for (i = 0; i < 8; i++) {
5585 /* for packet buffers not used, the register should read 0 */
5586 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5588 hwstats->mpc[i] += mpc;
5589 total_mpc += hwstats->mpc[i];
5590 if (hw->mac.type == ixgbe_mac_82598EB)
5591 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5592 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5593 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5594 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5595 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5596 switch (hw->mac.type) {
5597 case ixgbe_mac_82598EB:
5598 hwstats->pxonrxc[i] +=
5599 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5600 hwstats->pxoffrxc[i] +=
5601 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5603 case ixgbe_mac_82599EB:
5604 hwstats->pxonrxc[i] +=
5605 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5606 hwstats->pxoffrxc[i] +=
5607 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5612 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5613 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5615 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5616 /* work around hardware counting issue */
5617 hwstats->gprc -= missed_rx;
5619 /* 82598 hardware only has a 32 bit counter in the high register */
5620 switch (hw->mac.type) {
5621 case ixgbe_mac_82598EB:
5622 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5623 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5624 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5625 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5626 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5628 case ixgbe_mac_82599EB:
5629 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5630 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5631 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5632 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5633 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5634 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5635 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5636 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5637 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5638 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5640 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5641 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5642 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5643 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5644 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5645 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5646 #endif /* IXGBE_FCOE */
5651 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5652 hwstats->bprc += bprc;
5653 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5654 if (hw->mac.type == ixgbe_mac_82598EB)
5655 hwstats->mprc -= bprc;
5656 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5657 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5658 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5659 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5660 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5661 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5662 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5663 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5664 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5665 hwstats->lxontxc += lxon;
5666 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5667 hwstats->lxofftxc += lxoff;
5668 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5669 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5670 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5672 * 82598 errata - tx of flow control packets is included in tx counters
5674 xon_off_tot = lxon + lxoff;
5675 hwstats->gptc -= xon_off_tot;
5676 hwstats->mptc -= xon_off_tot;
5677 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5678 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5679 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5680 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5681 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5682 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5683 hwstats->ptc64 -= xon_off_tot;
5684 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5685 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5686 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5687 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5688 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5689 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5691 /* Fill out the OS statistics structure */
5692 netdev->stats.multicast = hwstats->mprc;
5695 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5696 netdev->stats.rx_dropped = 0;
5697 netdev->stats.rx_length_errors = hwstats->rlec;
5698 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5699 netdev->stats.rx_missed_errors = total_mpc;
5703 * ixgbe_watchdog - Timer Call-back
5704 * @data: pointer to adapter cast into an unsigned long
5706 static void ixgbe_watchdog(unsigned long data)
5708 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5709 struct ixgbe_hw *hw = &adapter->hw;
5714 * Do the watchdog outside of interrupt context due to the lovely
5715 * delays that some of the newer hardware requires
5718 if (test_bit(__IXGBE_DOWN, &adapter->state))
5719 goto watchdog_short_circuit;
5721 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5723 * for legacy and MSI interrupts don't set any bits
5724 * that are enabled for EIAM, because this operation
5725 * would set *both* EIMS and EICS for any bit in EIAM
5727 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5728 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5729 goto watchdog_reschedule;
5732 /* get one bit for every active tx/rx interrupt vector */
5733 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5734 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5735 if (qv->rxr_count || qv->txr_count)
5736 eics |= ((u64)1 << i);
5739 /* Cause software interrupt to ensure rx rings are cleaned */
5740 ixgbe_irq_rearm_queues(adapter, eics);
5742 watchdog_reschedule:
5743 /* Reset the timer */
5744 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5746 watchdog_short_circuit:
5747 schedule_work(&adapter->watchdog_task);
5751 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5752 * @work: pointer to work_struct containing our data
5754 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5756 struct ixgbe_adapter *adapter = container_of(work,
5757 struct ixgbe_adapter,
5758 multispeed_fiber_task);
5759 struct ixgbe_hw *hw = &adapter->hw;
5763 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5764 autoneg = hw->phy.autoneg_advertised;
5765 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5766 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5767 hw->mac.autotry_restart = false;
5768 if (hw->mac.ops.setup_link)
5769 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5770 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5771 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5775 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5776 * @work: pointer to work_struct containing our data
5778 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5780 struct ixgbe_adapter *adapter = container_of(work,
5781 struct ixgbe_adapter,
5782 sfp_config_module_task);
5783 struct ixgbe_hw *hw = &adapter->hw;
5786 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5788 /* Time for electrical oscillations to settle down */
5790 err = hw->phy.ops.identify_sfp(hw);
5792 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5793 e_dev_err("failed to initialize because an unsupported SFP+ "
5794 "module type was detected.\n");
5795 e_dev_err("Reload the driver after installing a supported "
5797 unregister_netdev(adapter->netdev);
5800 hw->mac.ops.setup_sfp(hw);
5802 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5803 /* This will also work for DA Twinax connections */
5804 schedule_work(&adapter->multispeed_fiber_task);
5805 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5809 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5810 * @work: pointer to work_struct containing our data
5812 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5814 struct ixgbe_adapter *adapter = container_of(work,
5815 struct ixgbe_adapter,
5817 struct ixgbe_hw *hw = &adapter->hw;
5820 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5821 for (i = 0; i < adapter->num_tx_queues; i++)
5822 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5823 &(adapter->tx_ring[i]->state));
5825 e_err(probe, "failed to finish FDIR re-initialization, "
5826 "ignored adding FDIR ATR filters\n");
5828 /* Done FDIR Re-initialization, enable transmits */
5829 netif_tx_start_all_queues(adapter->netdev);
5832 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5835 * ixgbe_watchdog_task - worker thread to bring link up
5836 * @work: pointer to work_struct containing our data
5838 static void ixgbe_watchdog_task(struct work_struct *work)
5840 struct ixgbe_adapter *adapter = container_of(work,
5841 struct ixgbe_adapter,
5843 struct net_device *netdev = adapter->netdev;
5844 struct ixgbe_hw *hw = &adapter->hw;
5848 struct ixgbe_ring *tx_ring;
5849 int some_tx_pending = 0;
5851 mutex_lock(&ixgbe_watchdog_lock);
5853 link_up = adapter->link_up;
5854 link_speed = adapter->link_speed;
5856 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5857 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5860 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5861 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5862 hw->mac.ops.fc_enable(hw, i);
5864 hw->mac.ops.fc_enable(hw, 0);
5867 hw->mac.ops.fc_enable(hw, 0);
5872 time_after(jiffies, (adapter->link_check_timeout +
5873 IXGBE_TRY_LINK_TIMEOUT))) {
5874 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5875 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5877 adapter->link_up = link_up;
5878 adapter->link_speed = link_speed;
5882 if (!netif_carrier_ok(netdev)) {
5883 bool flow_rx, flow_tx;
5885 switch (hw->mac.type) {
5886 case ixgbe_mac_82598EB: {
5887 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5888 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5889 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5890 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5893 case ixgbe_mac_82599EB: {
5894 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5895 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5896 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5897 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5906 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5907 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5909 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5910 "1 Gbps" : "unknown speed")),
5911 ((flow_rx && flow_tx) ? "RX/TX" :
5913 (flow_tx ? "TX" : "None"))));
5915 netif_carrier_on(netdev);
5917 /* Force detection of hung controller */
5918 for (i = 0; i < adapter->num_tx_queues; i++) {
5919 tx_ring = adapter->tx_ring[i];
5920 set_check_for_tx_hang(tx_ring);
5924 adapter->link_up = false;
5925 adapter->link_speed = 0;
5926 if (netif_carrier_ok(netdev)) {
5927 e_info(drv, "NIC Link is Down\n");
5928 netif_carrier_off(netdev);
5932 if (!netif_carrier_ok(netdev)) {
5933 for (i = 0; i < adapter->num_tx_queues; i++) {
5934 tx_ring = adapter->tx_ring[i];
5935 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5936 some_tx_pending = 1;
5941 if (some_tx_pending) {
5942 /* We've lost link, so the controller stops DMA,
5943 * but we've got queued Tx work that's never going
5944 * to get done, so reset controller to flush Tx.
5945 * (Do the reset outside of interrupt context).
5947 schedule_work(&adapter->reset_task);
5951 ixgbe_update_stats(adapter);
5952 mutex_unlock(&ixgbe_watchdog_lock);
5955 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5956 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5957 u32 tx_flags, u8 *hdr_len, __be16 protocol)
5959 struct ixgbe_adv_tx_context_desc *context_desc;
5962 struct ixgbe_tx_buffer *tx_buffer_info;
5963 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5964 u32 mss_l4len_idx, l4len;
5966 if (skb_is_gso(skb)) {
5967 if (skb_header_cloned(skb)) {
5968 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5972 l4len = tcp_hdrlen(skb);
5975 if (protocol == htons(ETH_P_IP)) {
5976 struct iphdr *iph = ip_hdr(skb);
5979 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5983 } else if (skb_is_gso_v6(skb)) {
5984 ipv6_hdr(skb)->payload_len = 0;
5985 tcp_hdr(skb)->check =
5986 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5987 &ipv6_hdr(skb)->daddr,
5991 i = tx_ring->next_to_use;
5993 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5994 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5996 /* VLAN MACLEN IPLEN */
5997 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5999 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6000 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6001 IXGBE_ADVTXD_MACLEN_SHIFT);
6002 *hdr_len += skb_network_offset(skb);
6004 (skb_transport_header(skb) - skb_network_header(skb));
6006 (skb_transport_header(skb) - skb_network_header(skb));
6007 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6008 context_desc->seqnum_seed = 0;
6010 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6011 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6012 IXGBE_ADVTXD_DTYP_CTXT);
6014 if (protocol == htons(ETH_P_IP))
6015 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6016 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6017 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6021 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6022 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6023 /* use index 1 for TSO */
6024 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6025 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6027 tx_buffer_info->time_stamp = jiffies;
6028 tx_buffer_info->next_to_watch = i;
6031 if (i == tx_ring->count)
6033 tx_ring->next_to_use = i;
6040 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6046 case cpu_to_be16(ETH_P_IP):
6047 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6048 switch (ip_hdr(skb)->protocol) {
6050 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6053 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6057 case cpu_to_be16(ETH_P_IPV6):
6058 /* XXX what about other V6 headers?? */
6059 switch (ipv6_hdr(skb)->nexthdr) {
6061 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6064 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6069 if (unlikely(net_ratelimit()))
6070 e_warn(probe, "partial checksum but proto=%x!\n",
6078 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6079 struct ixgbe_ring *tx_ring,
6080 struct sk_buff *skb, u32 tx_flags,
6083 struct ixgbe_adv_tx_context_desc *context_desc;
6085 struct ixgbe_tx_buffer *tx_buffer_info;
6086 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6088 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6089 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6090 i = tx_ring->next_to_use;
6091 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6092 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6094 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6096 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6097 vlan_macip_lens |= (skb_network_offset(skb) <<
6098 IXGBE_ADVTXD_MACLEN_SHIFT);
6099 if (skb->ip_summed == CHECKSUM_PARTIAL)
6100 vlan_macip_lens |= (skb_transport_header(skb) -
6101 skb_network_header(skb));
6103 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6104 context_desc->seqnum_seed = 0;
6106 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6107 IXGBE_ADVTXD_DTYP_CTXT);
6109 if (skb->ip_summed == CHECKSUM_PARTIAL)
6110 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6112 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6113 /* use index zero for tx checksum offload */
6114 context_desc->mss_l4len_idx = 0;
6116 tx_buffer_info->time_stamp = jiffies;
6117 tx_buffer_info->next_to_watch = i;
6120 if (i == tx_ring->count)
6122 tx_ring->next_to_use = i;
6130 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6131 struct ixgbe_ring *tx_ring,
6132 struct sk_buff *skb, u32 tx_flags,
6133 unsigned int first, const u8 hdr_len)
6135 struct device *dev = tx_ring->dev;
6136 struct ixgbe_tx_buffer *tx_buffer_info;
6138 unsigned int total = skb->len;
6139 unsigned int offset = 0, size, count = 0, i;
6140 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6142 unsigned int bytecount = skb->len;
6145 i = tx_ring->next_to_use;
6147 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6148 /* excluding fcoe_crc_eof for FCoE */
6149 total -= sizeof(struct fcoe_crc_eof);
6151 len = min(skb_headlen(skb), total);
6153 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6154 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6156 tx_buffer_info->length = size;
6157 tx_buffer_info->mapped_as_page = false;
6158 tx_buffer_info->dma = dma_map_single(dev,
6160 size, DMA_TO_DEVICE);
6161 if (dma_mapping_error(dev, tx_buffer_info->dma))
6163 tx_buffer_info->time_stamp = jiffies;
6164 tx_buffer_info->next_to_watch = i;
6173 if (i == tx_ring->count)
6178 for (f = 0; f < nr_frags; f++) {
6179 struct skb_frag_struct *frag;
6181 frag = &skb_shinfo(skb)->frags[f];
6182 len = min((unsigned int)frag->size, total);
6183 offset = frag->page_offset;
6187 if (i == tx_ring->count)
6190 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6191 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6193 tx_buffer_info->length = size;
6194 tx_buffer_info->dma = dma_map_page(dev,
6198 tx_buffer_info->mapped_as_page = true;
6199 if (dma_mapping_error(dev, tx_buffer_info->dma))
6201 tx_buffer_info->time_stamp = jiffies;
6202 tx_buffer_info->next_to_watch = i;
6213 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6214 gso_segs = skb_shinfo(skb)->gso_segs;
6216 /* adjust for FCoE Sequence Offload */
6217 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6218 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6219 skb_shinfo(skb)->gso_size);
6220 #endif /* IXGBE_FCOE */
6221 bytecount += (gso_segs - 1) * hdr_len;
6223 /* multiply data chunks by size of headers */
6224 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6225 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6226 tx_ring->tx_buffer_info[i].skb = skb;
6227 tx_ring->tx_buffer_info[first].next_to_watch = i;
6232 e_dev_err("TX DMA map failed\n");
6234 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6235 tx_buffer_info->dma = 0;
6236 tx_buffer_info->time_stamp = 0;
6237 tx_buffer_info->next_to_watch = 0;
6241 /* clear timestamp and dma mappings for remaining portion of packet */
6244 i += tx_ring->count;
6246 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6247 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6253 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6254 int tx_flags, int count, u32 paylen, u8 hdr_len)
6256 union ixgbe_adv_tx_desc *tx_desc = NULL;
6257 struct ixgbe_tx_buffer *tx_buffer_info;
6258 u32 olinfo_status = 0, cmd_type_len = 0;
6260 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6262 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6264 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6266 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6267 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6269 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6270 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6272 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6273 IXGBE_ADVTXD_POPTS_SHIFT;
6275 /* use index 1 context for tso */
6276 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6277 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6278 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6279 IXGBE_ADVTXD_POPTS_SHIFT;
6281 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6282 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6283 IXGBE_ADVTXD_POPTS_SHIFT;
6285 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6286 olinfo_status |= IXGBE_ADVTXD_CC;
6287 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6288 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6289 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6292 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6294 i = tx_ring->next_to_use;
6296 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6297 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6298 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6299 tx_desc->read.cmd_type_len =
6300 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6301 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6303 if (i == tx_ring->count)
6307 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6310 * Force memory writes to complete before letting h/w
6311 * know there are new descriptors to fetch. (Only
6312 * applicable for weak-ordered memory model archs,
6317 tx_ring->next_to_use = i;
6318 writel(i, tx_ring->tail);
6321 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6322 u8 queue, u32 tx_flags, __be16 protocol)
6324 struct ixgbe_atr_input atr_input;
6325 struct iphdr *iph = ip_hdr(skb);
6326 struct ethhdr *eth = (struct ethhdr *)skb->data;
6330 /* Right now, we support IPv4 w/ TCP only */
6331 if (protocol != htons(ETH_P_IP) ||
6332 iph->protocol != IPPROTO_TCP)
6335 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6337 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6338 IXGBE_TX_FLAGS_VLAN_SHIFT;
6342 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6343 ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6344 ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6345 ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6346 ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6347 /* src and dst are inverted, think how the receiver sees them */
6348 ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6349 ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6351 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6352 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6355 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6357 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6358 /* Herbert's original patch had:
6359 * smp_mb__after_netif_stop_queue();
6360 * but since that doesn't exist yet, just open code it. */
6363 /* We need to check again in a case another CPU has just
6364 * made room available. */
6365 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6368 /* A reprieve! - use start_queue because it doesn't call schedule */
6369 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6370 ++tx_ring->tx_stats.restart_queue;
6374 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6376 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6378 return __ixgbe_maybe_stop_tx(tx_ring, size);
6381 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6383 struct ixgbe_adapter *adapter = netdev_priv(dev);
6384 int txq = smp_processor_id();
6388 protocol = vlan_get_protocol(skb);
6390 if ((protocol == htons(ETH_P_FCOE)) ||
6391 (protocol == htons(ETH_P_FIP))) {
6392 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6393 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6394 txq += adapter->ring_feature[RING_F_FCOE].mask;
6396 #ifdef CONFIG_IXGBE_DCB
6397 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6398 txq = adapter->fcoe.up;
6405 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6406 while (unlikely(txq >= dev->real_num_tx_queues))
6407 txq -= dev->real_num_tx_queues;
6411 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6412 if (skb->priority == TC_PRIO_CONTROL)
6413 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6415 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6420 return skb_tx_hash(dev, skb);
6423 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6424 struct ixgbe_adapter *adapter,
6425 struct ixgbe_ring *tx_ring)
6427 struct net_device *netdev = tx_ring->netdev;
6428 struct netdev_queue *txq;
6430 unsigned int tx_flags = 0;
6437 protocol = vlan_get_protocol(skb);
6439 if (vlan_tx_tag_present(skb)) {
6440 tx_flags |= vlan_tx_tag_get(skb);
6441 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6442 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6443 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6445 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6446 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6447 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6448 skb->priority != TC_PRIO_CONTROL) {
6449 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6450 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6451 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6455 /* for FCoE with DCB, we force the priority to what
6456 * was specified by the switch */
6457 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6458 (protocol == htons(ETH_P_FCOE) ||
6459 protocol == htons(ETH_P_FIP))) {
6460 #ifdef CONFIG_IXGBE_DCB
6461 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6462 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6463 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6464 tx_flags |= ((adapter->fcoe.up << 13)
6465 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6468 /* flag for FCoE offloads */
6469 if (protocol == htons(ETH_P_FCOE))
6470 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6474 /* four things can cause us to need a context descriptor */
6475 if (skb_is_gso(skb) ||
6476 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6477 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6478 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6481 count += TXD_USE_COUNT(skb_headlen(skb));
6482 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6483 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6485 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6486 tx_ring->tx_stats.tx_busy++;
6487 return NETDEV_TX_BUSY;
6490 first = tx_ring->next_to_use;
6491 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6493 /* setup tx offload for FCoE */
6494 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6496 dev_kfree_skb_any(skb);
6497 return NETDEV_TX_OK;
6500 tx_flags |= IXGBE_TX_FLAGS_FSO;
6501 #endif /* IXGBE_FCOE */
6503 if (protocol == htons(ETH_P_IP))
6504 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6505 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6508 dev_kfree_skb_any(skb);
6509 return NETDEV_TX_OK;
6513 tx_flags |= IXGBE_TX_FLAGS_TSO;
6514 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6516 (skb->ip_summed == CHECKSUM_PARTIAL))
6517 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6520 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6522 /* add the ATR filter if ATR is on */
6523 if (tx_ring->atr_sample_rate) {
6524 ++tx_ring->atr_count;
6525 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6526 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6528 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6529 tx_flags, protocol);
6530 tx_ring->atr_count = 0;
6533 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6534 txq->tx_bytes += skb->len;
6536 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6537 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6540 dev_kfree_skb_any(skb);
6541 tx_ring->tx_buffer_info[first].time_stamp = 0;
6542 tx_ring->next_to_use = first;
6545 return NETDEV_TX_OK;
6548 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6550 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6551 struct ixgbe_ring *tx_ring;
6553 tx_ring = adapter->tx_ring[skb->queue_mapping];
6554 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6558 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6559 * @netdev: network interface device structure
6560 * @p: pointer to an address structure
6562 * Returns 0 on success, negative on failure
6564 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6567 struct ixgbe_hw *hw = &adapter->hw;
6568 struct sockaddr *addr = p;
6570 if (!is_valid_ether_addr(addr->sa_data))
6571 return -EADDRNOTAVAIL;
6573 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6574 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6576 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6583 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6585 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6586 struct ixgbe_hw *hw = &adapter->hw;
6590 if (prtad != hw->phy.mdio.prtad)
6592 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6598 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6599 u16 addr, u16 value)
6601 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6602 struct ixgbe_hw *hw = &adapter->hw;
6604 if (prtad != hw->phy.mdio.prtad)
6606 return hw->phy.ops.write_reg(hw, addr, devad, value);
6609 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6611 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6613 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6617 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6619 * @netdev: network interface device structure
6621 * Returns non-zero on failure
6623 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6626 struct ixgbe_adapter *adapter = netdev_priv(dev);
6627 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6629 if (is_valid_ether_addr(mac->san_addr)) {
6631 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6638 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6640 * @netdev: network interface device structure
6642 * Returns non-zero on failure
6644 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6647 struct ixgbe_adapter *adapter = netdev_priv(dev);
6648 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6650 if (is_valid_ether_addr(mac->san_addr)) {
6652 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6658 #ifdef CONFIG_NET_POLL_CONTROLLER
6660 * Polling 'interrupt' - used by things like netconsole to send skbs
6661 * without having to re-enable interrupts. It's not called while
6662 * the interrupt routine is executing.
6664 static void ixgbe_netpoll(struct net_device *netdev)
6666 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6669 /* if interface is down do nothing */
6670 if (test_bit(__IXGBE_DOWN, &adapter->state))
6673 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6675 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6676 for (i = 0; i < num_q_vectors; i++) {
6677 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6678 ixgbe_msix_clean_many(0, q_vector);
6681 ixgbe_intr(adapter->pdev->irq, netdev);
6683 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6687 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6688 struct rtnl_link_stats64 *stats)
6690 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6693 /* accurate rx/tx bytes/packets stats */
6694 dev_txq_stats_fold(netdev, stats);
6696 for (i = 0; i < adapter->num_rx_queues; i++) {
6697 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6703 start = u64_stats_fetch_begin_bh(&ring->syncp);
6704 packets = ring->stats.packets;
6705 bytes = ring->stats.bytes;
6706 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6707 stats->rx_packets += packets;
6708 stats->rx_bytes += bytes;
6712 /* following stats updated by ixgbe_watchdog_task() */
6713 stats->multicast = netdev->stats.multicast;
6714 stats->rx_errors = netdev->stats.rx_errors;
6715 stats->rx_length_errors = netdev->stats.rx_length_errors;
6716 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6717 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6722 static const struct net_device_ops ixgbe_netdev_ops = {
6723 .ndo_open = ixgbe_open,
6724 .ndo_stop = ixgbe_close,
6725 .ndo_start_xmit = ixgbe_xmit_frame,
6726 .ndo_select_queue = ixgbe_select_queue,
6727 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6728 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6729 .ndo_validate_addr = eth_validate_addr,
6730 .ndo_set_mac_address = ixgbe_set_mac,
6731 .ndo_change_mtu = ixgbe_change_mtu,
6732 .ndo_tx_timeout = ixgbe_tx_timeout,
6733 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6734 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6735 .ndo_do_ioctl = ixgbe_ioctl,
6736 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6737 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6738 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6739 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6740 .ndo_get_stats64 = ixgbe_get_stats64,
6741 #ifdef CONFIG_NET_POLL_CONTROLLER
6742 .ndo_poll_controller = ixgbe_netpoll,
6745 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6746 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6747 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6748 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6749 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6750 #endif /* IXGBE_FCOE */
6753 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6754 const struct ixgbe_info *ii)
6756 #ifdef CONFIG_PCI_IOV
6757 struct ixgbe_hw *hw = &adapter->hw;
6760 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6763 /* The 82599 supports up to 64 VFs per physical function
6764 * but this implementation limits allocation to 63 so that
6765 * basic networking resources are still available to the
6768 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6769 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6770 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6772 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6775 /* If call to enable VFs succeeded then allocate memory
6776 * for per VF control structures.
6779 kcalloc(adapter->num_vfs,
6780 sizeof(struct vf_data_storage), GFP_KERNEL);
6781 if (adapter->vfinfo) {
6782 /* Now that we're sure SR-IOV is enabled
6783 * and memory allocated set up the mailbox parameters
6785 ixgbe_init_mbx_params_pf(hw);
6786 memcpy(&hw->mbx.ops, ii->mbx_ops,
6787 sizeof(hw->mbx.ops));
6789 /* Disable RSC when in SR-IOV mode */
6790 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6791 IXGBE_FLAG2_RSC_ENABLED);
6796 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6797 "SRIOV disabled\n");
6798 pci_disable_sriov(adapter->pdev);
6801 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6802 adapter->num_vfs = 0;
6803 #endif /* CONFIG_PCI_IOV */
6807 * ixgbe_probe - Device Initialization Routine
6808 * @pdev: PCI device information struct
6809 * @ent: entry in ixgbe_pci_tbl
6811 * Returns 0 on success, negative on failure
6813 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6814 * The OS initialization, configuring of the adapter private structure,
6815 * and a hardware reset occur.
6817 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6818 const struct pci_device_id *ent)
6820 struct net_device *netdev;
6821 struct ixgbe_adapter *adapter = NULL;
6822 struct ixgbe_hw *hw;
6823 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6824 static int cards_found;
6825 int i, err, pci_using_dac;
6826 unsigned int indices = num_possible_cpus();
6832 /* Catch broken hardware that put the wrong VF device ID in
6833 * the PCIe SR-IOV capability.
6835 if (pdev->is_virtfn) {
6836 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6837 pci_name(pdev), pdev->vendor, pdev->device);
6841 err = pci_enable_device_mem(pdev);
6845 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6846 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6849 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6851 err = dma_set_coherent_mask(&pdev->dev,
6855 "No usable DMA configuration, aborting\n");
6862 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6863 IORESOURCE_MEM), ixgbe_driver_name);
6866 "pci_request_selected_regions failed 0x%x\n", err);
6870 pci_enable_pcie_error_reporting(pdev);
6872 pci_set_master(pdev);
6873 pci_save_state(pdev);
6875 if (ii->mac == ixgbe_mac_82598EB)
6876 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6878 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6880 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6882 indices += min_t(unsigned int, num_possible_cpus(),
6883 IXGBE_MAX_FCOE_INDICES);
6885 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6888 goto err_alloc_etherdev;
6891 SET_NETDEV_DEV(netdev, &pdev->dev);
6893 adapter = netdev_priv(netdev);
6894 pci_set_drvdata(pdev, adapter);
6896 adapter->netdev = netdev;
6897 adapter->pdev = pdev;
6900 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6902 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6903 pci_resource_len(pdev, 0));
6909 for (i = 1; i <= 5; i++) {
6910 if (pci_resource_len(pdev, i) == 0)
6914 netdev->netdev_ops = &ixgbe_netdev_ops;
6915 ixgbe_set_ethtool_ops(netdev);
6916 netdev->watchdog_timeo = 5 * HZ;
6917 strcpy(netdev->name, pci_name(pdev));
6919 adapter->bd_number = cards_found;
6922 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6923 hw->mac.type = ii->mac;
6926 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6927 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6928 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6929 if (!(eec & (1 << 8)))
6930 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6933 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6934 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6935 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6936 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6937 hw->phy.mdio.mmds = 0;
6938 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6939 hw->phy.mdio.dev = netdev;
6940 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6941 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6943 /* set up this timer and work struct before calling get_invariants
6944 * which might start the timer
6946 init_timer(&adapter->sfp_timer);
6947 adapter->sfp_timer.function = ixgbe_sfp_timer;
6948 adapter->sfp_timer.data = (unsigned long) adapter;
6950 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6952 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6953 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6955 /* a new SFP+ module arrival, called from GPI SDP2 context */
6956 INIT_WORK(&adapter->sfp_config_module_task,
6957 ixgbe_sfp_config_module_task);
6959 ii->get_invariants(hw);
6961 /* setup the private structure */
6962 err = ixgbe_sw_init(adapter);
6966 /* Make it possible the adapter to be woken up via WOL */
6967 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6968 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6971 * If there is a fan on this device and it has failed log the
6974 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6975 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6976 if (esdp & IXGBE_ESDP_SDP1)
6977 e_crit(probe, "Fan has stopped, replace the adapter\n");
6980 /* reset_hw fills in the perm_addr as well */
6981 hw->phy.reset_if_overtemp = true;
6982 err = hw->mac.ops.reset_hw(hw);
6983 hw->phy.reset_if_overtemp = false;
6984 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6985 hw->mac.type == ixgbe_mac_82598EB) {
6987 * Start a kernel thread to watch for a module to arrive.
6988 * Only do this for 82598, since 82599 will generate
6989 * interrupts on module arrival.
6991 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6992 mod_timer(&adapter->sfp_timer,
6993 round_jiffies(jiffies + (2 * HZ)));
6995 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6996 e_dev_err("failed to initialize because an unsupported SFP+ "
6997 "module type was detected.\n");
6998 e_dev_err("Reload the driver after installing a supported "
7002 e_dev_err("HW Init failed: %d\n", err);
7006 ixgbe_probe_vf(adapter, ii);
7008 netdev->features = NETIF_F_SG |
7010 NETIF_F_HW_VLAN_TX |
7011 NETIF_F_HW_VLAN_RX |
7012 NETIF_F_HW_VLAN_FILTER;
7014 netdev->features |= NETIF_F_IPV6_CSUM;
7015 netdev->features |= NETIF_F_TSO;
7016 netdev->features |= NETIF_F_TSO6;
7017 netdev->features |= NETIF_F_GRO;
7019 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7020 netdev->features |= NETIF_F_SCTP_CSUM;
7022 netdev->vlan_features |= NETIF_F_TSO;
7023 netdev->vlan_features |= NETIF_F_TSO6;
7024 netdev->vlan_features |= NETIF_F_IP_CSUM;
7025 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7026 netdev->vlan_features |= NETIF_F_SG;
7028 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7029 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7030 IXGBE_FLAG_DCB_ENABLED);
7031 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7032 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7034 #ifdef CONFIG_IXGBE_DCB
7035 netdev->dcbnl_ops = &dcbnl_ops;
7039 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7040 if (hw->mac.ops.get_device_caps) {
7041 hw->mac.ops.get_device_caps(hw, &device_caps);
7042 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7043 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7046 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7047 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7048 netdev->vlan_features |= NETIF_F_FSO;
7049 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7051 #endif /* IXGBE_FCOE */
7052 if (pci_using_dac) {
7053 netdev->features |= NETIF_F_HIGHDMA;
7054 netdev->vlan_features |= NETIF_F_HIGHDMA;
7057 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7058 netdev->features |= NETIF_F_LRO;
7060 /* make sure the EEPROM is good */
7061 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7062 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7067 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7068 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7070 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7071 e_dev_err("invalid MAC address\n");
7076 /* power down the optics */
7077 if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
7078 hw->mac.ops.disable_tx_laser(hw);
7080 init_timer(&adapter->watchdog_timer);
7081 adapter->watchdog_timer.function = ixgbe_watchdog;
7082 adapter->watchdog_timer.data = (unsigned long)adapter;
7084 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7085 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7087 err = ixgbe_init_interrupt_scheme(adapter);
7091 switch (pdev->device) {
7092 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7093 /* All except this subdevice support WOL */
7094 if (pdev->subsystem_device ==
7095 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
7099 case IXGBE_DEV_ID_82599_KX4:
7100 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7101 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7107 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7109 /* pick up the PCI bus settings for reporting later */
7110 hw->mac.ops.get_bus_info(hw);
7112 /* print bus type/speed/width info */
7113 e_dev_info("(PCI Express:%s:%s) %pM\n",
7114 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7115 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7117 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7118 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7119 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7122 ixgbe_read_pba_num_generic(hw, &part_num);
7123 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7124 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7125 "PBA No: %06x-%03x\n",
7126 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7127 (part_num >> 8), (part_num & 0xff));
7129 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7130 hw->mac.type, hw->phy.type,
7131 (part_num >> 8), (part_num & 0xff));
7133 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7134 e_dev_warn("PCI-Express bandwidth available for this card is "
7135 "not sufficient for optimal performance.\n");
7136 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7140 /* save off EEPROM version number */
7141 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7143 /* reset the hardware with the new settings */
7144 err = hw->mac.ops.start_hw(hw);
7146 if (err == IXGBE_ERR_EEPROM_VERSION) {
7147 /* We are running on a pre-production device, log a warning */
7148 e_dev_warn("This device is a pre-production adapter/LOM. "
7149 "Please be aware there may be issues associated "
7150 "with your hardware. If you are experiencing "
7151 "problems please contact your Intel or hardware "
7152 "representative who provided you with this "
7155 strcpy(netdev->name, "eth%d");
7156 err = register_netdev(netdev);
7160 /* carrier off reporting is important to ethtool even BEFORE open */
7161 netif_carrier_off(netdev);
7163 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7164 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7165 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7167 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7168 INIT_WORK(&adapter->check_overtemp_task,
7169 ixgbe_check_overtemp_task);
7170 #ifdef CONFIG_IXGBE_DCA
7171 if (dca_add_requester(&pdev->dev) == 0) {
7172 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7173 ixgbe_setup_dca(adapter);
7176 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7177 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7178 for (i = 0; i < adapter->num_vfs; i++)
7179 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7182 /* add san mac addr to netdev */
7183 ixgbe_add_sanmac_netdev(netdev);
7185 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7190 ixgbe_release_hw_control(adapter);
7191 ixgbe_clear_interrupt_scheme(adapter);
7194 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7195 ixgbe_disable_sriov(adapter);
7196 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7197 del_timer_sync(&adapter->sfp_timer);
7198 cancel_work_sync(&adapter->sfp_task);
7199 cancel_work_sync(&adapter->multispeed_fiber_task);
7200 cancel_work_sync(&adapter->sfp_config_module_task);
7201 iounmap(hw->hw_addr);
7203 free_netdev(netdev);
7205 pci_release_selected_regions(pdev,
7206 pci_select_bars(pdev, IORESOURCE_MEM));
7209 pci_disable_device(pdev);
7214 * ixgbe_remove - Device Removal Routine
7215 * @pdev: PCI device information struct
7217 * ixgbe_remove is called by the PCI subsystem to alert the driver
7218 * that it should release a PCI device. The could be caused by a
7219 * Hot-Plug event, or because the driver is going to be removed from
7222 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7224 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7225 struct net_device *netdev = adapter->netdev;
7227 set_bit(__IXGBE_DOWN, &adapter->state);
7228 /* clear the module not found bit to make sure the worker won't
7231 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7232 del_timer_sync(&adapter->watchdog_timer);
7234 del_timer_sync(&adapter->sfp_timer);
7235 cancel_work_sync(&adapter->watchdog_task);
7236 cancel_work_sync(&adapter->sfp_task);
7237 cancel_work_sync(&adapter->multispeed_fiber_task);
7238 cancel_work_sync(&adapter->sfp_config_module_task);
7239 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7240 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7241 cancel_work_sync(&adapter->fdir_reinit_task);
7242 flush_scheduled_work();
7244 #ifdef CONFIG_IXGBE_DCA
7245 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7246 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7247 dca_remove_requester(&pdev->dev);
7248 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7253 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7254 ixgbe_cleanup_fcoe(adapter);
7256 #endif /* IXGBE_FCOE */
7258 /* remove the added san mac */
7259 ixgbe_del_sanmac_netdev(netdev);
7261 if (netdev->reg_state == NETREG_REGISTERED)
7262 unregister_netdev(netdev);
7264 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7265 ixgbe_disable_sriov(adapter);
7267 ixgbe_clear_interrupt_scheme(adapter);
7269 ixgbe_release_hw_control(adapter);
7271 iounmap(adapter->hw.hw_addr);
7272 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7275 e_dev_info("complete\n");
7277 free_netdev(netdev);
7279 pci_disable_pcie_error_reporting(pdev);
7281 pci_disable_device(pdev);
7285 * ixgbe_io_error_detected - called when PCI error is detected
7286 * @pdev: Pointer to PCI device
7287 * @state: The current pci connection state
7289 * This function is called after a PCI bus error affecting
7290 * this device has been detected.
7292 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7293 pci_channel_state_t state)
7295 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7296 struct net_device *netdev = adapter->netdev;
7298 netif_device_detach(netdev);
7300 if (state == pci_channel_io_perm_failure)
7301 return PCI_ERS_RESULT_DISCONNECT;
7303 if (netif_running(netdev))
7304 ixgbe_down(adapter);
7305 pci_disable_device(pdev);
7307 /* Request a slot reset. */
7308 return PCI_ERS_RESULT_NEED_RESET;
7312 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7313 * @pdev: Pointer to PCI device
7315 * Restart the card from scratch, as if from a cold-boot.
7317 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7319 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7320 pci_ers_result_t result;
7323 if (pci_enable_device_mem(pdev)) {
7324 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7325 result = PCI_ERS_RESULT_DISCONNECT;
7327 pci_set_master(pdev);
7328 pci_restore_state(pdev);
7329 pci_save_state(pdev);
7331 pci_wake_from_d3(pdev, false);
7333 ixgbe_reset(adapter);
7334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7335 result = PCI_ERS_RESULT_RECOVERED;
7338 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7340 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7341 "failed 0x%0x\n", err);
7342 /* non-fatal, continue */
7349 * ixgbe_io_resume - called when traffic can start flowing again.
7350 * @pdev: Pointer to PCI device
7352 * This callback is called when the error recovery driver tells us that
7353 * its OK to resume normal operation.
7355 static void ixgbe_io_resume(struct pci_dev *pdev)
7357 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7358 struct net_device *netdev = adapter->netdev;
7360 if (netif_running(netdev)) {
7361 if (ixgbe_up(adapter)) {
7362 e_info(probe, "ixgbe_up failed after reset\n");
7367 netif_device_attach(netdev);
7370 static struct pci_error_handlers ixgbe_err_handler = {
7371 .error_detected = ixgbe_io_error_detected,
7372 .slot_reset = ixgbe_io_slot_reset,
7373 .resume = ixgbe_io_resume,
7376 static struct pci_driver ixgbe_driver = {
7377 .name = ixgbe_driver_name,
7378 .id_table = ixgbe_pci_tbl,
7379 .probe = ixgbe_probe,
7380 .remove = __devexit_p(ixgbe_remove),
7382 .suspend = ixgbe_suspend,
7383 .resume = ixgbe_resume,
7385 .shutdown = ixgbe_shutdown,
7386 .err_handler = &ixgbe_err_handler
7390 * ixgbe_init_module - Driver Registration Routine
7392 * ixgbe_init_module is the first routine called when the driver is
7393 * loaded. All it does is register with the PCI subsystem.
7395 static int __init ixgbe_init_module(void)
7398 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7399 pr_info("%s\n", ixgbe_copyright);
7401 #ifdef CONFIG_IXGBE_DCA
7402 dca_register_notify(&dca_notifier);
7405 ret = pci_register_driver(&ixgbe_driver);
7409 module_init(ixgbe_init_module);
7412 * ixgbe_exit_module - Driver Exit Cleanup Routine
7414 * ixgbe_exit_module is called just before the driver is removed
7417 static void __exit ixgbe_exit_module(void)
7419 #ifdef CONFIG_IXGBE_DCA
7420 dca_unregister_notify(&dca_notifier);
7422 pci_unregister_driver(&ixgbe_driver);
7423 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7426 #ifdef CONFIG_IXGBE_DCA
7427 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7432 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7433 __ixgbe_notify_dca);
7435 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7438 #endif /* CONFIG_IXGBE_DCA */
7441 * ixgbe_get_hw_dev return device
7442 * used by hardware layer to print debugging information
7444 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7446 struct ixgbe_adapter *adapter = hw->back;
7447 return adapter->netdev;
7450 module_exit(ixgbe_exit_module);