drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 135                  "per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172         if (adapter->vfinfo)
 173                 kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 printk(KERN_ERR "%-15s ", rname);
 293                 for (j = 0; j < 8; j++)
 294                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 295                 printk(KERN_CONT "\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 printk(KERN_INFO "Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 328                 netdev->name,
 329                 netdev->state,
 330                 netdev->trans_start,
 331                 netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         printk(KERN_INFO " Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 348                 "leng ntw timestamp\n");
 349         for (n = 0; n < adapter->num_tx_queues; n++) {
 350                 tx_ring = adapter->tx_ring[n];
 351                 tx_buffer_info =
 352                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 353                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 354                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 355                            (u64)tx_buffer_info->dma,
 356                            tx_buffer_info->length,
 357                            tx_buffer_info->next_to_watch,
 358                            (u64)tx_buffer_info->time_stamp);
 359         }
 360
 361         /* Print TX Rings */
 362         if (!netif_msg_tx_done(adapter))
 363                 goto rx_ring_summary;
 364
 365         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 366
 367         /* Transmit Descriptor Formats
 368          *
 369          * Advanced Transmit Descriptor
 370          *   +--------------------------------------------------------------+
 371          * 0 |         Buffer Address [63:0]                                |
 372          *   +--------------------------------------------------------------+
 373          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 374          *   +--------------------------------------------------------------+
 375          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 376          */
 377
 378         for (n = 0; n < adapter->num_tx_queues; n++) {
 379                 tx_ring = adapter->tx_ring[n];
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 382                 printk(KERN_INFO "------------------------------------\n");
 383                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 384                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 385                         "leng  ntw timestamp        bi->skb\n");
 386
 387                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 388                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 389                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 390                         u0 = (struct my_u0 *)tx_desc;
 391                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 392                                 " %04X  %3X %016llX %p", i,
 393                                 le64_to_cpu(u0->a),
 394                                 le64_to_cpu(u0->b),
 395                                 (u64)tx_buffer_info->dma,
 396                                 tx_buffer_info->length,
 397                                 tx_buffer_info->next_to_watch,
 398                                 (u64)tx_buffer_info->time_stamp,
 399                                 tx_buffer_info->skb);
 400                         if (i == tx_ring->next_to_use &&
 401                                 i == tx_ring->next_to_clean)
 402                                 printk(KERN_CONT " NTC/U\n");
 403                         else if (i == tx_ring->next_to_use)
 404                                 printk(KERN_CONT " NTU\n");
 405                         else if (i == tx_ring->next_to_clean)
 406                                 printk(KERN_CONT " NTC\n");
 407                         else
 408                                 printk(KERN_CONT "\n");
 409
 410                         if (netif_msg_pktdata(adapter) &&
 411                                 tx_buffer_info->dma != 0)
 412                                 print_hex_dump(KERN_INFO, "",
 413                                         DUMP_PREFIX_ADDRESS, 16, 1,
 414                                         phys_to_virt(tx_buffer_info->dma),
 415                                         tx_buffer_info->length, true);
 416                 }
 417         }
 418
 419         /* Print RX Rings Summary */
 420 rx_ring_summary:
 421         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 422         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 423         for (n = 0; n < adapter->num_rx_queues; n++) {
 424                 rx_ring = adapter->rx_ring[n];
 425                 printk(KERN_INFO "%5d %5X %5X\n", n,
 426                            rx_ring->next_to_use, rx_ring->next_to_clean);
 427         }
 428
 429         /* Print RX Rings */
 430         if (!netif_msg_rx_status(adapter))
 431                 goto exit;
 432
 433         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 434
 435         /* Advanced Receive Descriptor (Read) Format
 436          *    63                                           1        0
 437          *    +-----------------------------------------------------+
 438          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 439          *    +----------------------------------------------+------+
 440          *  8 |       Header Buffer Address [63:1]           |  DD  |
 441          *    +-----------------------------------------------------+
 442          *
 443          *
 444          * Advanced Receive Descriptor (Write-Back) Format
 445          *
 446          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 447          *   +------------------------------------------------------+
 448          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 449          *   | Checksum   Ident  |   |           |    | Type | Type |
 450          *   +------------------------------------------------------+
 451          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 452          *   +------------------------------------------------------+
 453          *   63       48 47    32 31            20 19               0
 454          */
 455         for (n = 0; n < adapter->num_rx_queues; n++) {
 456                 rx_ring = adapter->rx_ring[n];
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 459                 printk(KERN_INFO "------------------------------------\n");
 460                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 461                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 462                         "<-- Adv Rx Read format\n");
 463                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 464                         "[vl er S cks ln] ---------------- [bi->skb] "
 465                         "<-- Adv Rx Write-Back format\n");
 466
 467                 for (i = 0; i < rx_ring->count; i++) {
 468                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 469                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 470                         u0 = (struct my_u0 *)rx_desc;
 471                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 472                         if (staterr & IXGBE_RXD_STAT_DD) {
 473                                 /* Descriptor Done */
 474                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 475                                         "%016llX ---------------- %p", i,
 476                                         le64_to_cpu(u0->a),
 477                                         le64_to_cpu(u0->b),
 478                                         rx_buffer_info->skb);
 479                         } else {
 480                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 481                                         "%016llX %016llX %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         (u64)rx_buffer_info->dma,
 485                                         rx_buffer_info->skb);
 486
 487                                 if (netif_msg_pktdata(adapter)) {
 488                                         print_hex_dump(KERN_INFO, "",
 489                                            DUMP_PREFIX_ADDRESS, 16, 1,
 490                                            phys_to_virt(rx_buffer_info->dma),
 491                                            rx_ring->rx_buf_len, true);
 492
 493                                         if (rx_ring->rx_buf_len
 494                                                 < IXGBE_RXBUFFER_2048)
 495                                                 print_hex_dump(KERN_INFO, "",
 496                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 497                                                   phys_to_virt(
 498                                                     rx_buffer_info->page_dma +
 499                                                     rx_buffer_info->page_offset
 500                                                   ),
 501                                                   PAGE_SIZE/2, true);
 502                                 }
 503                         }
 504
 505                         if (i == rx_ring->next_to_use)
 506                                 printk(KERN_CONT " NTU\n");
 507                         else if (i == rx_ring->next_to_clean)
 508                                 printk(KERN_CONT " NTC\n");
 509                         else
 510                                 printk(KERN_CONT "\n");
 511
 512                 }
 513         }
 514
 515 exit:
 516         return;
 517 }
 518
 519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 520 {
 521         u32 ctrl_ext;
 522
 523         /* Let firmware take over control of h/w */
 524         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 526                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 527 }
 528
 529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 530 {
 531         u32 ctrl_ext;
 532
 533         /* Let firmware know the driver has taken over */
 534         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 536                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 537 }
 538
 539 /*
 540  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 541  * @adapter: pointer to adapter struct
 542  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 543  * @queue: queue to map the corresponding interrupt to
 544  * @msix_vector: the vector to map to the corresponding queue
 545  *
 546  */
 547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 548                            u8 queue, u8 msix_vector)
 549 {
 550         u32 ivar, index;
 551         struct ixgbe_hw *hw = &adapter->hw;
 552         switch (hw->mac.type) {
 553         case ixgbe_mac_82598EB:
 554                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 555                 if (direction == -1)
 556                         direction = 0;
 557                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 558                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 559                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 560                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 561                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 562                 break;
 563         case ixgbe_mac_82599EB:
 564                 if (direction == -1) {
 565                         /* other causes */
 566                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 567                         index = ((queue & 1) * 8);
 568                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 569                         ivar &= ~(0xFF << index);
 570                         ivar |= (msix_vector << index);
 571                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 572                         break;
 573                 } else {
 574                         /* tx or rx causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((16 * (queue & 1)) + (8 * direction));
 577                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 581                         break;
 582                 }
 583         default:
 584                 break;
 585         }
 586 }
 587
 588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 589                                           u64 qmask)
 590 {
 591         u32 mask;
 592
 593         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596         } else {
 597                 mask = (qmask & 0xFFFFFFFF);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 599                 mask = (qmask >> 32);
 600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 601         }
 602 }
 603
 604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 605                                              struct ixgbe_tx_buffer
 606                                              *tx_buffer_info)
 607 {
 608         if (tx_buffer_info->dma) {
 609                 if (tx_buffer_info->mapped_as_page)
 610                         dma_unmap_page(&adapter->pdev->dev,
 611                                        tx_buffer_info->dma,
 612                                        tx_buffer_info->length,
 613                                        DMA_TO_DEVICE);
 614                 else
 615                         dma_unmap_single(&adapter->pdev->dev,
 616                                          tx_buffer_info->dma,
 617                                          tx_buffer_info->length,
 618                                          DMA_TO_DEVICE);
 619                 tx_buffer_info->dma = 0;
 620         }
 621         if (tx_buffer_info->skb) {
 622                 dev_kfree_skb_any(tx_buffer_info->skb);
 623                 tx_buffer_info->skb = NULL;
 624         }
 625         tx_buffer_info->time_stamp = 0;
 626         /* tx_buffer_info must be completely set up in the transmit path */
 627 }
 628
 629 /**
 630  * ixgbe_tx_xon_state - check the tx ring xon state
 631  * @adapter: the ixgbe adapter
 632  * @tx_ring: the corresponding tx_ring
 633  *
 634  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 635  * corresponding TC of this tx_ring when checking TFCS.
 636  *
 637  * Returns : true if in xon state (currently not paused)
 638  */
 639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 640                                       struct ixgbe_ring *tx_ring)
 641 {
 642         u32 txoff = IXGBE_TFCS_TXOFF;
 643
 644 #ifdef CONFIG_IXGBE_DCB
 645         if (adapter->dcb_cfg.pfc_mode_enable) {
 646                 int tc;
 647                 int reg_idx = tx_ring->reg_idx;
 648                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 649
 650                 switch (adapter->hw.mac.type) {
 651                 case ixgbe_mac_82598EB:
 652                         tc = reg_idx >> 2;
 653                         txoff = IXGBE_TFCS_TXOFF0;
 654                         break;
 655                 case ixgbe_mac_82599EB:
 656                         tc = 0;
 657                         txoff = IXGBE_TFCS_TXOFF;
 658                         if (dcb_i == 8) {
 659                                 /* TC0, TC1 */
 660                                 tc = reg_idx >> 5;
 661                                 if (tc == 2) /* TC2, TC3 */
 662                                         tc += (reg_idx - 64) >> 4;
 663                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 664                                         tc += 1 + ((reg_idx - 96) >> 3);
 665                         } else if (dcb_i == 4) {
 666                                 /* TC0, TC1 */
 667                                 tc = reg_idx >> 6;
 668                                 if (tc == 1) {
 669                                         tc += (reg_idx - 64) >> 5;
 670                                         if (tc == 2) /* TC2, TC3 */
 671                                                 tc += (reg_idx - 96) >> 4;
 672                                 }
 673                         }
 674                         break;
 675                 default:
 676                         tc = 0;
 677                 }
 678                 txoff <<= tc;
 679         }
 680 #endif
 681         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 682 }
 683
 684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 685                                        struct ixgbe_ring *tx_ring,
 686                                        unsigned int eop)
 687 {
 688         struct ixgbe_hw *hw = &adapter->hw;
 689
 690         /* Detect a transmit hang in hardware, this serializes the
 691          * check with the clearing of time_stamp and movement of eop */
 692         adapter->detect_tx_hung = false;
 693         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 694             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 695             ixgbe_tx_xon_state(adapter, tx_ring)) {
 696                 /* detected Tx unit hang */
 697                 union ixgbe_adv_tx_desc *tx_desc;
 698                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 699                 e_err(drv, "Detected Tx Unit Hang\n"
 700                       "  Tx Queue             <%d>\n"
 701                       "  TDH, TDT             <%x>, <%x>\n"
 702                       "  next_to_use          <%x>\n"
 703                       "  next_to_clean        <%x>\n"
 704                       "tx_buffer_info[next_to_clean]\n"
 705                       "  time_stamp           <%lx>\n"
 706                       "  jiffies              <%lx>\n",
 707                       tx_ring->queue_index,
 708                       IXGBE_READ_REG(hw, tx_ring->head),
 709                       IXGBE_READ_REG(hw, tx_ring->tail),
 710                       tx_ring->next_to_use, eop,
 711                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 712                 return true;
 713         }
 714
 715         return false;
 716 }
 717
 718 #define IXGBE_MAX_TXD_PWR       14
 719 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 720
 721 /* Tx Descriptors needed, worst case */
 722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 723                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 725         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 726
 727 static void ixgbe_tx_timeout(struct net_device *netdev);
 728
 729 /**
 730  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 731  * @q_vector: structure containing interrupt and ring information
 732  * @tx_ring: tx ring to clean
 733  **/
 734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 735                                struct ixgbe_ring *tx_ring)
 736 {
 737         struct ixgbe_adapter *adapter = q_vector->adapter;
 738         struct net_device *netdev = adapter->netdev;
 739         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 740         struct ixgbe_tx_buffer *tx_buffer_info;
 741         unsigned int i, eop, count = 0;
 742         unsigned int total_bytes = 0, total_packets = 0;
 743
 744         i = tx_ring->next_to_clean;
 745         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 746         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 747
 748         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 749                (count < tx_ring->work_limit)) {
 750                 bool cleaned = false;
 751                 rmb(); /* read buffer_info after eop_desc */
 752                 for ( ; !cleaned; count++) {
 753                         struct sk_buff *skb;
 754                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 755                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 756                         cleaned = (i == eop);
 757                         skb = tx_buffer_info->skb;
 758
 759                         if (cleaned && skb) {
 760                                 unsigned int segs, bytecount;
 761                                 unsigned int hlen = skb_headlen(skb);
 762
 763                                 /* gso_segs is currently only valid for tcp */
 764                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 765 #ifdef IXGBE_FCOE
 766                                 /* adjust for FCoE Sequence Offload */
 767                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 768                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 769                                     skb_is_gso(skb)) {
 770                                         hlen = skb_transport_offset(skb) +
 771                                                 sizeof(struct fc_frame_header) +
 772                                                 sizeof(struct fcoe_crc_eof);
 773                                         segs = DIV_ROUND_UP(skb->len - hlen,
 774                                                 skb_shinfo(skb)->gso_size);
 775                                 }
 776 #endif /* IXGBE_FCOE */
 777                                 /* multiply data chunks by size of headers */
 778                                 bytecount = ((segs - 1) * hlen) + skb->len;
 779                                 total_packets += segs;
 780                                 total_bytes += bytecount;
 781                         }
 782
 783                         ixgbe_unmap_and_free_tx_resource(adapter,
 784                                                          tx_buffer_info);
 785
 786                         tx_desc->wb.status = 0;
 787
 788                         i++;
 789                         if (i == tx_ring->count)
 790                                 i = 0;
 791                 }
 792
 793                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 794                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 795         }
 796
 797         tx_ring->next_to_clean = i;
 798
 799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 800         if (unlikely(count && netif_carrier_ok(netdev) &&
 801                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 802                 /* Make sure that anybody stopping the queue after this
 803                  * sees the new next_to_clean.
 804                  */
 805                 smp_mb();
 806                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 807                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 808                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 809                         ++tx_ring->restart_queue;
 810                 }
 811         }
 812
 813         if (adapter->detect_tx_hung) {
 814                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 815                         /* schedule immediate reset if we believe we hung */
 816                         e_info(probe, "tx hang %d detected, resetting "
 817                                "adapter\n", adapter->tx_timeout_count + 1);
 818                         ixgbe_tx_timeout(adapter->netdev);
 819                 }
 820         }
 821
 822         /* re-arm the interrupt */
 823         if (count >= tx_ring->work_limit)
 824                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 825
 826         tx_ring->total_bytes += total_bytes;
 827         tx_ring->total_packets += total_packets;
 828         tx_ring->stats.packets += total_packets;
 829         tx_ring->stats.bytes += total_bytes;
 830         return (count < tx_ring->work_limit);
 831 }
 832
 833 #ifdef CONFIG_IXGBE_DCA
 834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 835                                 struct ixgbe_ring *rx_ring)
 836 {
 837         u32 rxctrl;
 838         int cpu = get_cpu();
 839         int q = rx_ring->reg_idx;
 840
 841         if (rx_ring->cpu != cpu) {
 842                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 843                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 844                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 845                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 846                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 847                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 848                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 849                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 850                 }
 851                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 852                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 853                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 854                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 855                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 856                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 857                 rx_ring->cpu = cpu;
 858         }
 859         put_cpu();
 860 }
 861
 862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 863                                 struct ixgbe_ring *tx_ring)
 864 {
 865         u32 txctrl;
 866         int cpu = get_cpu();
 867         int q = tx_ring->reg_idx;
 868         struct ixgbe_hw *hw = &adapter->hw;
 869
 870         if (tx_ring->cpu != cpu) {
 871                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 872                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 873                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 874                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 875                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 876                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 877                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 878                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 879                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 880                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 881                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 882                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 883                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 884                 }
 885                 tx_ring->cpu = cpu;
 886         }
 887         put_cpu();
 888 }
 889
 890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 891 {
 892         int i;
 893
 894         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 895                 return;
 896
 897         /* always use CB2 mode, difference is masked in the CB driver */
 898         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 899
 900         for (i = 0; i < adapter->num_tx_queues; i++) {
 901                 adapter->tx_ring[i]->cpu = -1;
 902                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 903         }
 904         for (i = 0; i < adapter->num_rx_queues; i++) {
 905                 adapter->rx_ring[i]->cpu = -1;
 906                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 907         }
 908 }
 909
 910 static int __ixgbe_notify_dca(struct device *dev, void *data)
 911 {
 912         struct net_device *netdev = dev_get_drvdata(dev);
 913         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 914         unsigned long event = *(unsigned long *)data;
 915
 916         switch (event) {
 917         case DCA_PROVIDER_ADD:
 918                 /* if we're already enabled, don't do it again */
 919                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 920                         break;
 921                 if (dca_add_requester(dev) == 0) {
 922                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 923                         ixgbe_setup_dca(adapter);
 924                         break;
 925                 }
 926                 /* Fall Through since DCA is disabled. */
 927         case DCA_PROVIDER_REMOVE:
 928                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 929                         dca_remove_requester(dev);
 930                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 931                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 932                 }
 933                 break;
 934         }
 935
 936         return 0;
 937 }
 938
 939 #endif /* CONFIG_IXGBE_DCA */
 940 /**
 941  * ixgbe_receive_skb - Send a completed packet up the stack
 942  * @adapter: board private structure
 943  * @skb: packet to send up
 944  * @status: hardware indication of status of receive
 945  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 946  * @rx_desc: rx descriptor
 947  **/
 948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 949                               struct sk_buff *skb, u8 status,
 950                               struct ixgbe_ring *ring,
 951                               union ixgbe_adv_rx_desc *rx_desc)
 952 {
 953         struct ixgbe_adapter *adapter = q_vector->adapter;
 954         struct napi_struct *napi = &q_vector->napi;
 955         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 956         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 957
 958         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 959                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 960                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 961                 else
 962                         napi_gro_receive(napi, skb);
 963         } else {
 964                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 965                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 966                 else
 967                         netif_rx(skb);
 968         }
 969 }
 970
 971 /**
 972  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 973  * @adapter: address of board private structure
 974  * @status_err: hardware indication of status of receive
 975  * @skb: skb currently being received and modified
 976  **/
 977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 978                                      union ixgbe_adv_rx_desc *rx_desc,
 979                                      struct sk_buff *skb)
 980 {
 981         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 982
 983         skb->ip_summed = CHECKSUM_NONE;
 984
 985         /* Rx csum disabled */
 986         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 987                 return;
 988
 989         /* if IP and error */
 990         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 991             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 992                 adapter->hw_csum_rx_error++;
 993                 return;
 994         }
 995
 996         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 997                 return;
 998
 999         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002                 /*
1003                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1004                  * checksum errors.
1005                  */
1006                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008                         return;
1009
1010                 adapter->hw_csum_rx_error++;
1011                 return;
1012         }
1013
1014         /* It must be a TCP or UDP packet with a valid checksum */
1015         skb->ip_summed = CHECKSUM_UNNECESSARY;
1016 }
1017
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019                                          struct ixgbe_ring *rx_ring, u32 val)
1020 {
1021         /*
1022          * Force memory writes to complete before letting h/w
1023          * know there are new descriptors to fetch.  (Only
1024          * applicable for weak-ordered memory model archs,
1025          * such as IA-64).
1026          */
1027         wmb();
1028         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029 }
1030
1031 /**
1032  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033  * @adapter: address of board private structure
1034  **/
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036                                    struct ixgbe_ring *rx_ring,
1037                                    int cleaned_count)
1038 {
1039         struct net_device *netdev = adapter->netdev;
1040         struct pci_dev *pdev = adapter->pdev;
1041         union ixgbe_adv_rx_desc *rx_desc;
1042         struct ixgbe_rx_buffer *bi;
1043         unsigned int i;
1044         unsigned int bufsz = rx_ring->rx_buf_len;
1045
1046         i = rx_ring->next_to_use;
1047         bi = &rx_ring->rx_buffer_info[i];
1048
1049         while (cleaned_count--) {
1050                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
1052                 if (!bi->page_dma &&
1053                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1054                         if (!bi->page) {
1055                                 bi->page = netdev_alloc_page(netdev);
1056                                 if (!bi->page) {
1057                                         adapter->alloc_rx_page_failed++;
1058                                         goto no_buffers;
1059                                 }
1060                                 bi->page_offset = 0;
1061                         } else {
1062                                 /* use a half page if we're re-using */
1063                                 bi->page_offset ^= (PAGE_SIZE / 2);
1064                         }
1065
1066                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1067                                                     bi->page_offset,
1068                                                     (PAGE_SIZE / 2),
1069                                                     DMA_FROM_DEVICE);
1070                 }
1071
1072                 if (!bi->skb) {
1073                         struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074                                                                         bufsz);
1075                         bi->skb = skb;
1076
1077                         if (!skb) {
1078                                 adapter->alloc_rx_buff_failed++;
1079                                 goto no_buffers;
1080                         }
1081                         /* initialize queue mapping */
1082                         skb_record_rx_queue(skb, rx_ring->queue_index);
1083                 }
1084
1085                 if (!bi->dma) {
1086                         bi->dma = dma_map_single(&pdev->dev,
1087                                                  bi->skb->data,
1088                                                  rx_ring->rx_buf_len,
1089                                                  DMA_FROM_DEVICE);
1090                 }
1091                 /* Refresh the desc even if buffer_addrs didn't change because
1092                  * each write-back erases this info. */
1093                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096                 } else {
1097                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098                 }
1099
1100                 i++;
1101                 if (i == rx_ring->count)
1102                         i = 0;
1103                 bi = &rx_ring->rx_buffer_info[i];
1104         }
1105
1106 no_buffers:
1107         if (rx_ring->next_to_use != i) {
1108                 rx_ring->next_to_use = i;
1109                 if (i-- == 0)
1110                         i = (rx_ring->count - 1);
1111
1112                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113         }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129                 IXGBE_RXDADV_RSCCNT_MASK) >>
1130                 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135  * @skb: pointer to the last skb in the rsc queue
1136  * @count: pointer to number of packets coalesced in this context
1137  *
1138  * This function changes a queue full of hw rsc buffers into a completed
1139  * packet.  It uses the ->prev pointers to find the first packet and then
1140  * turns it into the frag list owner.
1141  **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143                                                         u64 *count)
1144 {
1145         unsigned int frag_list_size = 0;
1146
1147         while (skb->prev) {
1148                 struct sk_buff *prev = skb->prev;
1149                 frag_list_size += skb->len;
1150                 skb->prev = NULL;
1151                 skb = prev;
1152                 *count += 1;
1153         }
1154
1155         skb_shinfo(skb)->frag_list = skb->next;
1156         skb->next = NULL;
1157         skb->len += frag_list_size;
1158         skb->data_len += frag_list_size;
1159         skb->truesize += frag_list_size;
1160         return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164         dma_addr_t dma;
1165         bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171                                struct ixgbe_ring *rx_ring,
1172                                int *work_done, int work_to_do)
1173 {
1174         struct ixgbe_adapter *adapter = q_vector->adapter;
1175         struct net_device *netdev = adapter->netdev;
1176         struct pci_dev *pdev = adapter->pdev;
1177         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179         struct sk_buff *skb;
1180         unsigned int i, rsc_count = 0;
1181         u32 len, staterr;
1182         u16 hdr_info;
1183         bool cleaned = false;
1184         int cleaned_count = 0;
1185         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187         int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190         i = rx_ring->next_to_clean;
1191         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195         while (staterr & IXGBE_RXD_STAT_DD) {
1196                 u32 upper_len = 0;
1197                 if (*work_done >= work_to_do)
1198                         break;
1199                 (*work_done)++;
1200
1201                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207                         if ((len > IXGBE_RX_HDR_SIZE) ||
1208                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209                                 len = IXGBE_RX_HDR_SIZE;
1210                 } else {
1211                         len = le16_to_cpu(rx_desc->wb.upper.length);
1212                 }
1213
1214                 cleaned = true;
1215                 skb = rx_buffer_info->skb;
1216                 prefetch(skb->data);
1217                 rx_buffer_info->skb = NULL;
1218
1219                 if (rx_buffer_info->dma) {
1220                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222                                  (!(skb->prev))) {
1223                                 /*
1224                                  * When HWRSC is enabled, delay unmapping
1225                                  * of the first packet. It carries the
1226                                  * header information, HW may still
1227                                  * access the header after the writeback.
1228                                  * Only unmap it when EOP is reached
1229                                  */
1230                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232                         } else {
1233                                 dma_unmap_single(&pdev->dev,
1234                                                  rx_buffer_info->dma,
1235                                                  rx_ring->rx_buf_len,
1236                                                  DMA_FROM_DEVICE);
1237                         }
1238                         rx_buffer_info->dma = 0;
1239                         skb_put(skb, len);
1240                 }
1241
1242                 if (upper_len) {
1243                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245                         rx_buffer_info->page_dma = 0;
1246                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247                                            rx_buffer_info->page,
1248                                            rx_buffer_info->page_offset,
1249                                            upper_len);
1250
1251                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252                             (page_count(rx_buffer_info->page) != 1))
1253                                 rx_buffer_info->page = NULL;
1254                         else
1255                                 get_page(rx_buffer_info->page);
1256
1257                         skb->len += upper_len;
1258                         skb->data_len += upper_len;
1259                         skb->truesize += upper_len;
1260                 }
1261
1262                 i++;
1263                 if (i == rx_ring->count)
1264                         i = 0;
1265
1266                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267                 prefetch(next_rxd);
1268                 cleaned_count++;
1269
1270                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273                 if (rsc_count) {
1274                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275                                      IXGBE_RXDADV_NEXTP_SHIFT;
1276                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1277                 } else {
1278                         next_buffer = &rx_ring->rx_buffer_info[i];
1279                 }
1280
1281                 if (staterr & IXGBE_RXD_STAT_EOP) {
1282                         if (skb->prev)
1283                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286                                         dma_unmap_single(&pdev->dev,
1287                                                          IXGBE_RSC_CB(skb)->dma,
1288                                                          rx_ring->rx_buf_len,
1289                                                          DMA_FROM_DEVICE);
1290                                         IXGBE_RSC_CB(skb)->dma = 0;
1291                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1292                                 }
1293                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295                                 else
1296                                         rx_ring->rsc_count++;
1297                                 rx_ring->rsc_flush++;
1298                         }
1299                         rx_ring->stats.packets++;
1300                         rx_ring->stats.bytes += skb->len;
1301                 } else {
1302                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303                                 rx_buffer_info->skb = next_buffer->skb;
1304                                 rx_buffer_info->dma = next_buffer->dma;
1305                                 next_buffer->skb = skb;
1306                                 next_buffer->dma = 0;
1307                         } else {
1308                                 skb->next = next_buffer->skb;
1309                                 skb->next->prev = skb;
1310                         }
1311                         rx_ring->non_eop_descs++;
1312                         goto next_desc;
1313                 }
1314
1315                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316                         dev_kfree_skb_irq(skb);
1317                         goto next_desc;
1318                 }
1319
1320                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322                 /* probably a little skewed due to removing CRC */
1323                 total_rx_bytes += skb->len;
1324                 total_rx_packets++;
1325
1326                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331                         if (!ddp_bytes)
1332                                 goto next_desc;
1333                 }
1334 #endif /* IXGBE_FCOE */
1335                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338                 rx_desc->wb.upper.status_error = 0;
1339
1340                 /* return some buffers to hardware, one at a time is too slow */
1341                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343                         cleaned_count = 0;
1344                 }
1345
1346                 /* use prefetched values */
1347                 rx_desc = next_rxd;
1348                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351         }
1352
1353         rx_ring->next_to_clean = i;
1354         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356         if (cleaned_count)
1357                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360         /* include DDPed FCoE data */
1361         if (ddp_bytes > 0) {
1362                 unsigned int mss;
1363
1364                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365                         sizeof(struct fc_frame_header) -
1366                         sizeof(struct fcoe_crc_eof);
1367                 if (mss > 512)
1368                         mss &= ~511;
1369                 total_rx_bytes += ddp_bytes;
1370                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371         }
1372 #endif /* IXGBE_FCOE */
1373
1374         rx_ring->total_packets += total_rx_packets;
1375         rx_ring->total_bytes += total_rx_bytes;
1376         netdev->stats.rx_bytes += total_rx_bytes;
1377         netdev->stats.rx_packets += total_rx_packets;
1378
1379         return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384  * ixgbe_configure_msix - Configure MSI-X hardware
1385  * @adapter: board private structure
1386  *
1387  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388  * interrupts.
1389  **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392         struct ixgbe_q_vector *q_vector;
1393         int i, j, q_vectors, v_idx, r_idx;
1394         u32 mask;
1395
1396         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398         /*
1399          * Populate the IVAR table and set the ITR values to the
1400          * corresponding register.
1401          */
1402         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403                 q_vector = adapter->q_vector[v_idx];
1404                 /* XXX for_each_set_bit(...) */
1405                 r_idx = find_first_bit(q_vector->rxr_idx,
1406                                        adapter->num_rx_queues);
1407
1408                 for (i = 0; i < q_vector->rxr_count; i++) {
1409                         j = adapter->rx_ring[r_idx]->reg_idx;
1410                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1411                         r_idx = find_next_bit(q_vector->rxr_idx,
1412                                               adapter->num_rx_queues,
1413                                               r_idx + 1);
1414                 }
1415                 r_idx = find_first_bit(q_vector->txr_idx,
1416                                        adapter->num_tx_queues);
1417
1418                 for (i = 0; i < q_vector->txr_count; i++) {
1419                         j = adapter->tx_ring[r_idx]->reg_idx;
1420                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1421                         r_idx = find_next_bit(q_vector->txr_idx,
1422                                               adapter->num_tx_queues,
1423                                               r_idx + 1);
1424                 }
1425
1426                 if (q_vector->txr_count && !q_vector->rxr_count)
1427                         /* tx only */
1428                         q_vector->eitr = adapter->tx_eitr_param;
1429                 else if (q_vector->rxr_count)
1430                         /* rx or mixed */
1431                         q_vector->eitr = adapter->rx_eitr_param;
1432
1433                 ixgbe_write_eitr(q_vector);
1434         }
1435
1436         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438                                v_idx);
1439         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
1443         /* set up to autoclear timer, and the vectors */
1444         mask = IXGBE_EIMS_ENABLE_MASK;
1445         if (adapter->num_vfs)
1446                 mask &= ~(IXGBE_EIMS_OTHER |
1447                           IXGBE_EIMS_MAILBOX |
1448                           IXGBE_EIMS_LSC);
1449         else
1450                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1452 }
1453
1454 enum latency_range {
1455         lowest_latency = 0,
1456         low_latency = 1,
1457         bulk_latency = 2,
1458         latency_invalid = 255
1459 };
1460
1461 /**
1462  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463  * @adapter: pointer to adapter
1464  * @eitr: eitr setting (ints per sec) to give last timeslice
1465  * @itr_setting: current throttle rate in ints/second
1466  * @packets: the number of packets during this measurement interval
1467  * @bytes: the number of bytes during this measurement interval
1468  *
1469  *      Stores a new ITR value based on packets and byte
1470  *      counts during the last interrupt.  The advantage of per interrupt
1471  *      computation is faster updates and more accurate ITR for the current
1472  *      traffic pattern.  Constants in this function were computed
1473  *      based on theoretical maximum wire speed and thresholds were set based
1474  *      on testing data as well as attempting to minimize response time
1475  *      while increasing bulk throughput.
1476  *      this functionality is controlled by the InterruptThrottleRate module
1477  *      parameter (see ixgbe_param.c)
1478  **/
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480                            u32 eitr, u8 itr_setting,
1481                            int packets, int bytes)
1482 {
1483         unsigned int retval = itr_setting;
1484         u32 timepassed_us;
1485         u64 bytes_perint;
1486
1487         if (packets == 0)
1488                 goto update_itr_done;
1489
1490
1491         /* simple throttlerate management
1492          *    0-20MB/s lowest (100000 ints/s)
1493          *   20-100MB/s low   (20000 ints/s)
1494          *  100-1249MB/s bulk (8000 ints/s)
1495          */
1496         /* what was last interrupt timeslice? */
1497         timepassed_us = 1000000/eitr;
1498         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500         switch (itr_setting) {
1501         case lowest_latency:
1502                 if (bytes_perint > adapter->eitr_low)
1503                         retval = low_latency;
1504                 break;
1505         case low_latency:
1506                 if (bytes_perint > adapter->eitr_high)
1507                         retval = bulk_latency;
1508                 else if (bytes_perint <= adapter->eitr_low)
1509                         retval = lowest_latency;
1510                 break;
1511         case bulk_latency:
1512                 if (bytes_perint <= adapter->eitr_high)
1513                         retval = low_latency;
1514                 break;
1515         }
1516
1517 update_itr_done:
1518         return retval;
1519 }
1520
1521 /**
1522  * ixgbe_write_eitr - write EITR register in hardware specific way
1523  * @q_vector: structure containing interrupt and ring information
1524  *
1525  * This function is made to be called by ethtool and by the driver
1526  * when it needs to update EITR registers at runtime.  Hardware
1527  * specific quirks/differences are taken care of here.
1528  */
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1530 {
1531         struct ixgbe_adapter *adapter = q_vector->adapter;
1532         struct ixgbe_hw *hw = &adapter->hw;
1533         int v_idx = q_vector->v_idx;
1534         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
1536         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537                 /* must write high and low 16 bits to reset counter */
1538                 itr_reg |= (itr_reg << 16);
1539         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1540                 /*
1541                  * 82599 can support a value of zero, so allow it for
1542                  * max interrupt rate, but there is an errata where it can
1543                  * not be zero with RSC
1544                  */
1545                 if (itr_reg == 8 &&
1546                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547                         itr_reg = 0;
1548
1549                 /*
1550                  * set the WDIS bit to not clear the timer bits and cause an
1551                  * immediate assertion of the interrupt
1552                  */
1553                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554         }
1555         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556 }
1557
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559 {
1560         struct ixgbe_adapter *adapter = q_vector->adapter;
1561         u32 new_itr;
1562         u8 current_itr, ret_itr;
1563         int i, r_idx;
1564         struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567         for (i = 0; i < q_vector->txr_count; i++) {
1568                 tx_ring = adapter->tx_ring[r_idx];
1569                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1570                                            q_vector->tx_itr,
1571                                            tx_ring->total_packets,
1572                                            tx_ring->total_bytes);
1573                 /* if the result for this queue would decrease interrupt
1574                  * rate for this vector then use that result */
1575                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576                                     q_vector->tx_itr - 1 : ret_itr);
1577                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1578                                       r_idx + 1);
1579         }
1580
1581         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582         for (i = 0; i < q_vector->rxr_count; i++) {
1583                 rx_ring = adapter->rx_ring[r_idx];
1584                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585                                            q_vector->rx_itr,
1586                                            rx_ring->total_packets,
1587                                            rx_ring->total_bytes);
1588                 /* if the result for this queue would decrease interrupt
1589                  * rate for this vector then use that result */
1590                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591                                     q_vector->rx_itr - 1 : ret_itr);
1592                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1593                                       r_idx + 1);
1594         }
1595
1596         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1597
1598         switch (current_itr) {
1599         /* counts and packets in update_itr are dependent on these numbers */
1600         case lowest_latency:
1601                 new_itr = 100000;
1602                 break;
1603         case low_latency:
1604                 new_itr = 20000; /* aka hwitr = ~200 */
1605                 break;
1606         case bulk_latency:
1607         default:
1608                 new_itr = 8000;
1609                 break;
1610         }
1611
1612         if (new_itr != q_vector->eitr) {
1613                 /* do an exponential smoothing */
1614                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1615
1616                 /* save the algorithm value here, not the smoothed one */
1617                 q_vector->eitr = new_itr;
1618
1619                 ixgbe_write_eitr(q_vector);
1620         }
1621 }
1622
1623 /**
1624  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625  * @work: pointer to work_struct containing our data
1626  **/
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1628 {
1629         struct ixgbe_adapter *adapter = container_of(work,
1630                                                      struct ixgbe_adapter,
1631                                                      check_overtemp_task);
1632         struct ixgbe_hw *hw = &adapter->hw;
1633         u32 eicr = adapter->interrupt_event;
1634
1635         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636                 switch (hw->device_id) {
1637                 case IXGBE_DEV_ID_82599_T3_LOM: {
1638                         u32 autoneg;
1639                         bool link_up = false;
1640
1641                         if (hw->mac.ops.check_link)
1642                                 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644                         if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645                             (eicr & IXGBE_EICR_LSC))
1646                                 /* Check if this is due to overtemp */
1647                                 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648                                         break;
1649                         }
1650                         return;
1651                 default:
1652                         if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653                                 return;
1654                         break;
1655                 }
1656                 e_crit(drv, "Network adapter has been stopped because it has "
1657                        "over heated. Restart the computer. If the problem "
1658                        "persists, power off the system and replace the "
1659                        "adapter\n");
1660                 /* write to clear the interrupt */
1661                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662         }
1663 }
1664
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666 {
1667         struct ixgbe_hw *hw = &adapter->hw;
1668
1669         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670             (eicr & IXGBE_EICR_GPI_SDP1)) {
1671                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1672                 /* write to clear the interrupt */
1673                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674         }
1675 }
1676
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678 {
1679         struct ixgbe_hw *hw = &adapter->hw;
1680
1681         if (eicr & IXGBE_EICR_GPI_SDP1) {
1682                 /* Clear the interrupt */
1683                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684                 schedule_work(&adapter->multispeed_fiber_task);
1685         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686                 /* Clear the interrupt */
1687                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688                 schedule_work(&adapter->sfp_config_module_task);
1689         } else {
1690                 /* Interrupt isn't for us... */
1691                 return;
1692         }
1693 }
1694
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696 {
1697         struct ixgbe_hw *hw = &adapter->hw;
1698
1699         adapter->lsc_int++;
1700         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701         adapter->link_check_timeout = jiffies;
1702         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704                 IXGBE_WRITE_FLUSH(hw);
1705                 schedule_work(&adapter->watchdog_task);
1706         }
1707 }
1708
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         u32 eicr;
1715
1716         /*
1717          * Workaround for Silicon errata.  Use clear-by-write instead
1718          * of clear-by-read.  Reading with EICS will return the
1719          * interrupt causes without clearing, which later be done
1720          * with the write to EICR.
1721          */
1722         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1724
1725         if (eicr & IXGBE_EICR_LSC)
1726                 ixgbe_check_lsc(adapter);
1727
1728         if (eicr & IXGBE_EICR_MAILBOX)
1729                 ixgbe_msg_task(adapter);
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB)
1732                 ixgbe_check_fan_failure(adapter, eicr);
1733
1734         if (hw->mac.type == ixgbe_mac_82599EB) {
1735                 ixgbe_check_sfp_event(adapter, eicr);
1736                 adapter->interrupt_event = eicr;
1737                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739                         schedule_work(&adapter->check_overtemp_task);
1740
1741                 /* Handle Flow Director Full threshold interrupt */
1742                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743                         int i;
1744                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745                         /* Disable transmits before FDIR Re-initialization */
1746                         netif_tx_stop_all_queues(netdev);
1747                         for (i = 0; i < adapter->num_tx_queues; i++) {
1748                                 struct ixgbe_ring *tx_ring =
1749                                                             adapter->tx_ring[i];
1750                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751                                                        &tx_ring->reinit_state))
1752                                         schedule_work(&adapter->fdir_reinit_task);
1753                         }
1754                 }
1755         }
1756         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1758
1759         return IRQ_HANDLED;
1760 }
1761
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763                                            u64 qmask)
1764 {
1765         u32 mask;
1766
1767         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770         } else {
1771                 mask = (qmask & 0xFFFFFFFF);
1772                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773                 mask = (qmask >> 32);
1774                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775         }
1776         /* skip the flush */
1777 }
1778
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780                                             u64 qmask)
1781 {
1782         u32 mask;
1783
1784         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787         } else {
1788                 mask = (qmask & 0xFFFFFFFF);
1789                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790                 mask = (qmask >> 32);
1791                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792         }
1793         /* skip the flush */
1794 }
1795
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797 {
1798         struct ixgbe_q_vector *q_vector = data;
1799         struct ixgbe_adapter  *adapter = q_vector->adapter;
1800         struct ixgbe_ring     *tx_ring;
1801         int i, r_idx;
1802
1803         if (!q_vector->txr_count)
1804                 return IRQ_HANDLED;
1805
1806         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807         for (i = 0; i < q_vector->txr_count; i++) {
1808                 tx_ring = adapter->tx_ring[r_idx];
1809                 tx_ring->total_bytes = 0;
1810                 tx_ring->total_packets = 0;
1811                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1812                                       r_idx + 1);
1813         }
1814
1815         /* EIAM disabled interrupts (on this vector) for us */
1816         napi_schedule(&q_vector->napi);
1817
1818         return IRQ_HANDLED;
1819 }
1820
1821 /**
1822  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823  * @irq: unused
1824  * @data: pointer to our q_vector struct for this interrupt vector
1825  **/
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827 {
1828         struct ixgbe_q_vector *q_vector = data;
1829         struct ixgbe_adapter  *adapter = q_vector->adapter;
1830         struct ixgbe_ring  *rx_ring;
1831         int r_idx;
1832         int i;
1833
1834         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835         for (i = 0;  i < q_vector->rxr_count; i++) {
1836                 rx_ring = adapter->rx_ring[r_idx];
1837                 rx_ring->total_bytes = 0;
1838                 rx_ring->total_packets = 0;
1839                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840                                       r_idx + 1);
1841         }
1842
1843         if (!q_vector->rxr_count)
1844                 return IRQ_HANDLED;
1845
1846         /* disable interrupts on this vector only */
1847         /* EIAM disabled interrupts (on this vector) for us */
1848         napi_schedule(&q_vector->napi);
1849
1850         return IRQ_HANDLED;
1851 }
1852
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854 {
1855         struct ixgbe_q_vector *q_vector = data;
1856         struct ixgbe_adapter  *adapter = q_vector->adapter;
1857         struct ixgbe_ring  *ring;
1858         int r_idx;
1859         int i;
1860
1861         if (!q_vector->txr_count && !q_vector->rxr_count)
1862                 return IRQ_HANDLED;
1863
1864         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865         for (i = 0; i < q_vector->txr_count; i++) {
1866                 ring = adapter->tx_ring[r_idx];
1867                 ring->total_bytes = 0;
1868                 ring->total_packets = 0;
1869                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870                                       r_idx + 1);
1871         }
1872
1873         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874         for (i = 0; i < q_vector->rxr_count; i++) {
1875                 ring = adapter->rx_ring[r_idx];
1876                 ring->total_bytes = 0;
1877                 ring->total_packets = 0;
1878                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879                                       r_idx + 1);
1880         }
1881
1882         /* EIAM disabled interrupts (on this vector) for us */
1883         napi_schedule(&q_vector->napi);
1884
1885         return IRQ_HANDLED;
1886 }
1887
1888 /**
1889  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890  * @napi: napi struct with our devices info in it
1891  * @budget: amount of work driver is allowed to do this pass, in packets
1892  *
1893  * This function is optimized for cleaning one queue only on a single
1894  * q_vector!!!
1895  **/
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897 {
1898         struct ixgbe_q_vector *q_vector =
1899                                container_of(napi, struct ixgbe_q_vector, napi);
1900         struct ixgbe_adapter *adapter = q_vector->adapter;
1901         struct ixgbe_ring *rx_ring = NULL;
1902         int work_done = 0;
1903         long r_idx;
1904
1905         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906         rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909                 ixgbe_update_rx_dca(adapter, rx_ring);
1910 #endif
1911
1912         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1913
1914         /* If all Rx work done, exit the polling mode */
1915         if (work_done < budget) {
1916                 napi_complete(napi);
1917                 if (adapter->rx_itr_setting & 1)
1918                         ixgbe_set_itr_msix(q_vector);
1919                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920                         ixgbe_irq_enable_queues(adapter,
1921                                                 ((u64)1 << q_vector->v_idx));
1922         }
1923
1924         return work_done;
1925 }
1926
1927 /**
1928  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929  * @napi: napi struct with our devices info in it
1930  * @budget: amount of work driver is allowed to do this pass, in packets
1931  *
1932  * This function will clean more than one rx queue associated with a
1933  * q_vector.
1934  **/
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1936 {
1937         struct ixgbe_q_vector *q_vector =
1938                                container_of(napi, struct ixgbe_q_vector, napi);
1939         struct ixgbe_adapter *adapter = q_vector->adapter;
1940         struct ixgbe_ring *ring = NULL;
1941         int work_done = 0, i;
1942         long r_idx;
1943         bool tx_clean_complete = true;
1944
1945         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946         for (i = 0; i < q_vector->txr_count; i++) {
1947                 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950                         ixgbe_update_tx_dca(adapter, ring);
1951 #endif
1952                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954                                       r_idx + 1);
1955         }
1956
1957         /* attempt to distribute budget to each queue fairly, but don't allow
1958          * the budget to go below 1 because we'll exit polling */
1959         budget /= (q_vector->rxr_count ?: 1);
1960         budget = max(budget, 1);
1961         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962         for (i = 0; i < q_vector->rxr_count; i++) {
1963                 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966                         ixgbe_update_rx_dca(adapter, ring);
1967 #endif
1968                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970                                       r_idx + 1);
1971         }
1972
1973         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974         ring = adapter->rx_ring[r_idx];
1975         /* If all Rx work done, exit the polling mode */
1976         if (work_done < budget) {
1977                 napi_complete(napi);
1978                 if (adapter->rx_itr_setting & 1)
1979                         ixgbe_set_itr_msix(q_vector);
1980                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981                         ixgbe_irq_enable_queues(adapter,
1982                                                 ((u64)1 << q_vector->v_idx));
1983                 return 0;
1984         }
1985
1986         return work_done;
1987 }
1988
1989 /**
1990  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991  * @napi: napi struct with our devices info in it
1992  * @budget: amount of work driver is allowed to do this pass, in packets
1993  *
1994  * This function is optimized for cleaning one queue only on a single
1995  * q_vector!!!
1996  **/
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998 {
1999         struct ixgbe_q_vector *q_vector =
2000                                container_of(napi, struct ixgbe_q_vector, napi);
2001         struct ixgbe_adapter *adapter = q_vector->adapter;
2002         struct ixgbe_ring *tx_ring = NULL;
2003         int work_done = 0;
2004         long r_idx;
2005
2006         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007         tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010                 ixgbe_update_tx_dca(adapter, tx_ring);
2011 #endif
2012
2013         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014                 work_done = budget;
2015
2016         /* If all Tx work done, exit the polling mode */
2017         if (work_done < budget) {
2018                 napi_complete(napi);
2019                 if (adapter->tx_itr_setting & 1)
2020                         ixgbe_set_itr_msix(q_vector);
2021                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023         }
2024
2025         return work_done;
2026 }
2027
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2029                                      int r_idx)
2030 {
2031         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033         set_bit(r_idx, q_vector->rxr_idx);
2034         q_vector->rxr_count++;
2035 }
2036
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2038                                      int t_idx)
2039 {
2040         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042         set_bit(t_idx, q_vector->txr_idx);
2043         q_vector->txr_count++;
2044 }
2045
2046 /**
2047  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048  * @adapter: board private structure to initialize
2049  * @vectors: allotted vector count for descriptor rings
2050  *
2051  * This function maps descriptor rings to the queue-specific vectors
2052  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2053  * one vector per ring/queue, but on a constrained vector budget, we
2054  * group the rings as "efficiently" as possible.  You would add new
2055  * mapping configurations in here.
2056  **/
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2058                                       int vectors)
2059 {
2060         int v_start = 0;
2061         int rxr_idx = 0, txr_idx = 0;
2062         int rxr_remaining = adapter->num_rx_queues;
2063         int txr_remaining = adapter->num_tx_queues;
2064         int i, j;
2065         int rqpv, tqpv;
2066         int err = 0;
2067
2068         /* No mapping required if MSI-X is disabled. */
2069         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070                 goto out;
2071
2072         /*
2073          * The ideal configuration...
2074          * We have enough vectors to map one per queue.
2075          */
2076         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2079
2080                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081                         map_vector_to_txq(adapter, v_start, txr_idx);
2082
2083                 goto out;
2084         }
2085
2086         /*
2087          * If we don't have enough vectors for a 1-to-1
2088          * mapping, we'll have to group them so there are
2089          * multiple queues per vector.
2090          */
2091         /* Re-adjusting *qpv takes care of the remainder. */
2092         for (i = v_start; i < vectors; i++) {
2093                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094                 for (j = 0; j < rqpv; j++) {
2095                         map_vector_to_rxq(adapter, i, rxr_idx);
2096                         rxr_idx++;
2097                         rxr_remaining--;
2098                 }
2099         }
2100         for (i = v_start; i < vectors; i++) {
2101                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102                 for (j = 0; j < tqpv; j++) {
2103                         map_vector_to_txq(adapter, i, txr_idx);
2104                         txr_idx++;
2105                         txr_remaining--;
2106                 }
2107         }
2108
2109 out:
2110         return err;
2111 }
2112
2113 /**
2114  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115  * @adapter: board private structure
2116  *
2117  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118  * interrupts from the kernel.
2119  **/
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121 {
2122         struct net_device *netdev = adapter->netdev;
2123         irqreturn_t (*handler)(int, void *);
2124         int i, vector, q_vectors, err;
2125         int ri=0, ti=0;
2126
2127         /* Decrement for Other and TCP Timer vectors */
2128         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130         /* Map the Tx/Rx rings to the vectors we were allotted. */
2131         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132         if (err)
2133                 goto out;
2134
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137                          &ixgbe_msix_clean_many)
2138         for (vector = 0; vector < q_vectors; vector++) {
2139                 handler = SET_HANDLER(adapter->q_vector[vector]);
2140
2141                 if(handler == &ixgbe_msix_clean_rx) {
2142                         sprintf(adapter->name[vector], "%s-%s-%d",
2143                                 netdev->name, "rx", ri++);
2144                 }
2145                 else if(handler == &ixgbe_msix_clean_tx) {
2146                         sprintf(adapter->name[vector], "%s-%s-%d",
2147                                 netdev->name, "tx", ti++);
2148                 }
2149                 else
2150                         sprintf(adapter->name[vector], "%s-%s-%d",
2151                                 netdev->name, "TxRx", vector);
2152
2153                 err = request_irq(adapter->msix_entries[vector].vector,
2154                                   handler, 0, adapter->name[vector],
2155                                   adapter->q_vector[vector]);
2156                 if (err) {
2157                         e_err(probe, "request_irq failed for MSIX interrupt "
2158                               "Error: %d\n", err);
2159                         goto free_queue_irqs;
2160                 }
2161         }
2162
2163         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164         err = request_irq(adapter->msix_entries[vector].vector,
2165                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2166         if (err) {
2167                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2168                 goto free_queue_irqs;
2169         }
2170
2171         return 0;
2172
2173 free_queue_irqs:
2174         for (i = vector - 1; i >= 0; i--)
2175                 free_irq(adapter->msix_entries[--vector].vector,
2176                          adapter->q_vector[i]);
2177         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178         pci_disable_msix(adapter->pdev);
2179         kfree(adapter->msix_entries);
2180         adapter->msix_entries = NULL;
2181 out:
2182         return err;
2183 }
2184
2185 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186 {
2187         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2188         u8 current_itr;
2189         u32 new_itr = q_vector->eitr;
2190         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2192
2193         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2194                                             q_vector->tx_itr,
2195                                             tx_ring->total_packets,
2196                                             tx_ring->total_bytes);
2197         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2198                                             q_vector->rx_itr,
2199                                             rx_ring->total_packets,
2200                                             rx_ring->total_bytes);
2201
2202         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2203
2204         switch (current_itr) {
2205         /* counts and packets in update_itr are dependent on these numbers */
2206         case lowest_latency:
2207                 new_itr = 100000;
2208                 break;
2209         case low_latency:
2210                 new_itr = 20000; /* aka hwitr = ~200 */
2211                 break;
2212         case bulk_latency:
2213                 new_itr = 8000;
2214                 break;
2215         default:
2216                 break;
2217         }
2218
2219         if (new_itr != q_vector->eitr) {
2220                 /* do an exponential smoothing */
2221                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2222
2223                 /* save the algorithm value here, not the smoothed one */
2224                 q_vector->eitr = new_itr;
2225
2226                 ixgbe_write_eitr(q_vector);
2227         }
2228 }
2229
2230 /**
2231  * ixgbe_irq_enable - Enable default interrupt generation settings
2232  * @adapter: board private structure
2233  **/
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235 {
2236         u32 mask;
2237
2238         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240                 mask |= IXGBE_EIMS_GPI_SDP0;
2241         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242                 mask |= IXGBE_EIMS_GPI_SDP1;
2243         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2244                 mask |= IXGBE_EIMS_ECC;
2245                 mask |= IXGBE_EIMS_GPI_SDP1;
2246                 mask |= IXGBE_EIMS_GPI_SDP2;
2247                 if (adapter->num_vfs)
2248                         mask |= IXGBE_EIMS_MAILBOX;
2249         }
2250         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252                 mask |= IXGBE_EIMS_FLOW_DIR;
2253
2254         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2255         ixgbe_irq_enable_queues(adapter, ~0);
2256         IXGBE_WRITE_FLUSH(&adapter->hw);
2257
2258         if (adapter->num_vfs > 32) {
2259                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261         }
2262 }
2263
2264 /**
2265  * ixgbe_intr - legacy mode Interrupt Handler
2266  * @irq: interrupt number
2267  * @data: pointer to a network interface device structure
2268  **/
2269 static irqreturn_t ixgbe_intr(int irq, void *data)
2270 {
2271         struct net_device *netdev = data;
2272         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273         struct ixgbe_hw *hw = &adapter->hw;
2274         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2275         u32 eicr;
2276
2277         /*
2278          * Workaround for silicon errata.  Mask the interrupts
2279          * before the read of EICR.
2280          */
2281         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
2283         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284          * therefore no explict interrupt disable is necessary */
2285         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2286         if (!eicr) {
2287                 /* shared interrupt alert!
2288                  * make sure interrupts are enabled because the read will
2289                  * have disabled interrupts due to EIAM */
2290                 ixgbe_irq_enable(adapter);
2291                 return IRQ_NONE;        /* Not our interrupt */
2292         }
2293
2294         if (eicr & IXGBE_EICR_LSC)
2295                 ixgbe_check_lsc(adapter);
2296
2297         if (hw->mac.type == ixgbe_mac_82599EB)
2298                 ixgbe_check_sfp_event(adapter, eicr);
2299
2300         ixgbe_check_fan_failure(adapter, eicr);
2301         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303                 schedule_work(&adapter->check_overtemp_task);
2304
2305         if (napi_schedule_prep(&(q_vector->napi))) {
2306                 adapter->tx_ring[0]->total_packets = 0;
2307                 adapter->tx_ring[0]->total_bytes = 0;
2308                 adapter->rx_ring[0]->total_packets = 0;
2309                 adapter->rx_ring[0]->total_bytes = 0;
2310                 /* would disable interrupts here but EIAM disabled it */
2311                 __napi_schedule(&(q_vector->napi));
2312         }
2313
2314         return IRQ_HANDLED;
2315 }
2316
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318 {
2319         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321         for (i = 0; i < q_vectors; i++) {
2322                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2323                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325                 q_vector->rxr_count = 0;
2326                 q_vector->txr_count = 0;
2327         }
2328 }
2329
2330 /**
2331  * ixgbe_request_irq - initialize interrupts
2332  * @adapter: board private structure
2333  *
2334  * Attempts to configure interrupts using the best available
2335  * capabilities of the hardware and kernel.
2336  **/
2337 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2338 {
2339         struct net_device *netdev = adapter->netdev;
2340         int err;
2341
2342         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343                 err = ixgbe_request_msix_irqs(adapter);
2344         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2345                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2346                                   netdev->name, netdev);
2347         } else {
2348                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2349                                   netdev->name, netdev);
2350         }
2351
2352         if (err)
2353                 e_err(probe, "request_irq failed, Error %d\n", err);
2354
2355         return err;
2356 }
2357
2358 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359 {
2360         struct net_device *netdev = adapter->netdev;
2361
2362         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2363                 int i, q_vectors;
2364
2365                 q_vectors = adapter->num_msix_vectors;
2366
2367                 i = q_vectors - 1;
2368                 free_irq(adapter->msix_entries[i].vector, netdev);
2369
2370                 i--;
2371                 for (; i >= 0; i--) {
2372                         free_irq(adapter->msix_entries[i].vector,
2373                                  adapter->q_vector[i]);
2374                 }
2375
2376                 ixgbe_reset_q_vectors(adapter);
2377         } else {
2378                 free_irq(adapter->pdev->irq, netdev);
2379         }
2380 }
2381
2382 /**
2383  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384  * @adapter: board private structure
2385  **/
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387 {
2388         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390         } else {
2391                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2393                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2394                 if (adapter->num_vfs > 32)
2395                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2396         }
2397         IXGBE_WRITE_FLUSH(&adapter->hw);
2398         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399                 int i;
2400                 for (i = 0; i < adapter->num_msix_vectors; i++)
2401                         synchronize_irq(adapter->msix_entries[i].vector);
2402         } else {
2403                 synchronize_irq(adapter->pdev->irq);
2404         }
2405 }
2406
2407 /**
2408  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409  *
2410  **/
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412 {
2413         struct ixgbe_hw *hw = &adapter->hw;
2414
2415         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2416                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2417
2418         ixgbe_set_ivar(adapter, 0, 0, 0);
2419         ixgbe_set_ivar(adapter, 1, 0, 0);
2420
2421         map_vector_to_rxq(adapter, 0, 0);
2422         map_vector_to_txq(adapter, 0, 0);
2423
2424         e_info(hw, "Legacy interrupt IVAR setup done\n");
2425 }
2426
2427 /**
2428  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429  * @adapter: board private structure
2430  * @ring: structure containing ring specific data
2431  *
2432  * Configure the Tx descriptor ring after a reset.
2433  **/
2434  static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435                                      struct ixgbe_ring *ring)
2436 {
2437         struct ixgbe_hw *hw = &adapter->hw;
2438         u64 tdba = ring->dma;
2439         u16 reg_idx = ring->reg_idx;
2440
2441         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2442                         (tdba & DMA_BIT_MASK(32)));
2443         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2444         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2445                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2446         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2447         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2448         ring->head = IXGBE_TDH(reg_idx);
2449         ring->tail = IXGBE_TDT(reg_idx);
2450
2451 }
2452
2453 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2454 {
2455         struct ixgbe_hw *hw = &adapter->hw;
2456         u32 rttdcs;
2457         u32 mask;
2458
2459         if (hw->mac.type == ixgbe_mac_82598EB)
2460                 return;
2461
2462         /* disable the arbiter while setting MTQC */
2463         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2464         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2465         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2466
2467         /* set transmit pool layout */
2468         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2469         switch (adapter->flags & mask) {
2470
2471         case (IXGBE_FLAG_SRIOV_ENABLED):
2472                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2473                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2474                 break;
2475
2476         case (IXGBE_FLAG_DCB_ENABLED):
2477                 /* We enable 8 traffic classes, DCB only */
2478                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2479                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2480                 break;
2481
2482         default:
2483                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2484                 break;
2485         }
2486
2487         /* re-enable the arbiter */
2488         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2489         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2490 }
2491
2492 /**
2493  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2494  * @adapter: board private structure
2495  *
2496  * Configure the Tx unit of the MAC after a reset.
2497  **/
2498 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2499 {
2500         u32 i;
2501
2502         /* Setup the HW Tx Head and Tail descriptor pointers */
2503         for (i = 0; i < adapter->num_tx_queues; i++)
2504                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2505
2506         ixgbe_setup_mtqc(adapter);
2507 }
2508
2509 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2510
2511 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2512                                    struct ixgbe_ring *rx_ring)
2513 {
2514         u32 srrctl;
2515         int index;
2516         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2517
2518         index = rx_ring->reg_idx;
2519         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2520                 unsigned long mask;
2521                 mask = (unsigned long) feature[RING_F_RSS].mask;
2522                 index = index & mask;
2523         }
2524         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2525
2526         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2527         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2528
2529         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2530                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2531
2532         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2533 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2534                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535 #else
2536                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2537 #endif
2538                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2539         } else {
2540                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2541                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2542                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2543         }
2544
2545         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2546 }
2547
2548 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2549 {
2550         struct ixgbe_hw *hw = &adapter->hw;
2551         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2552                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2553                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2554         u32 mrqc = 0, reta = 0;
2555         u32 rxcsum;
2556         int i, j;
2557         int mask;
2558
2559         /* Fill out hash function seeds */
2560         for (i = 0; i < 10; i++)
2561                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563         /* Fill out redirection table */
2564         for (i = 0, j = 0; i < 128; i++, j++) {
2565                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2566                         j = 0;
2567                 /* reta = 4-byte sliding window of
2568                  * 0x00..(indices-1)(indices-1)00..etc. */
2569                 reta = (reta << 8) | (j * 0x11);
2570                 if ((i & 3) == 3)
2571                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572         }
2573
2574         /* Disable indicating checksum in descriptor, enables RSS hash */
2575         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576         rxcsum |= IXGBE_RXCSUM_PCSD;
2577         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2580                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2581         else
2582                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2583 #ifdef CONFIG_IXGBE_DCB
2584                                          | IXGBE_FLAG_DCB_ENABLED
2585 #endif
2586                                          | IXGBE_FLAG_SRIOV_ENABLED
2587                                         );
2588
2589         switch (mask) {
2590         case (IXGBE_FLAG_RSS_ENABLED):
2591                 mrqc = IXGBE_MRQC_RSSEN;
2592                 break;
2593         case (IXGBE_FLAG_SRIOV_ENABLED):
2594                 mrqc = IXGBE_MRQC_VMDQEN;
2595                 break;
2596 #ifdef CONFIG_IXGBE_DCB
2597         case (IXGBE_FLAG_DCB_ENABLED):
2598                 mrqc = IXGBE_MRQC_RT8TCEN;
2599                 break;
2600 #endif /* CONFIG_IXGBE_DCB */
2601         default:
2602                 break;
2603         }
2604
2605         /* Perform hash on these packet types */
2606         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2607               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608               | IXGBE_MRQC_RSS_FIELD_IPV6
2609               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2610
2611         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2612 }
2613
2614 /**
2615  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616  * @adapter:    address of board private structure
2617  * @index:      index of ring to set
2618  **/
2619 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2620                                    struct ixgbe_ring *ring)
2621 {
2622         struct ixgbe_hw *hw = &adapter->hw;
2623         u32 rscctrl;
2624         int rx_buf_len;
2625         u16 reg_idx = ring->reg_idx;
2626
2627         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2628                 return;
2629
2630         rx_buf_len = ring->rx_buf_len;
2631         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2632         rscctrl |= IXGBE_RSCCTL_RSCEN;
2633         /*
2634          * we must limit the number of descriptors so that the
2635          * total size of max desc * buf_len is not greater
2636          * than 65535
2637          */
2638         if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2639 #if (MAX_SKB_FRAGS > 16)
2640                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2641 #elif (MAX_SKB_FRAGS > 8)
2642                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2643 #elif (MAX_SKB_FRAGS > 4)
2644                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2645 #else
2646                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2647 #endif
2648         } else {
2649                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2650                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2651                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2652                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2653                 else
2654                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2655         }
2656         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2657 }
2658
2659 static void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2660                                     struct ixgbe_ring *ring)
2661 {
2662         struct ixgbe_hw *hw = &adapter->hw;
2663         u64 rdba = ring->dma;
2664         u16 reg_idx = ring->reg_idx;
2665
2666         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2667         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2668         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2669                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2670         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2671         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2672         ring->head = IXGBE_RDH(reg_idx);
2673         ring->tail = IXGBE_RDT(reg_idx);
2674 }
2675
2676 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2677 {
2678         struct ixgbe_hw *hw = &adapter->hw;
2679         int p;
2680
2681         /* PSRTYPE must be initialized in non 82598 adapters */
2682         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2683                       IXGBE_PSRTYPE_UDPHDR |
2684                       IXGBE_PSRTYPE_IPV4HDR |
2685                       IXGBE_PSRTYPE_L2HDR |
2686                       IXGBE_PSRTYPE_IPV6HDR;
2687
2688         if (hw->mac.type == ixgbe_mac_82598EB)
2689                 return;
2690
2691         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2692                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2693
2694         for (p = 0; p < adapter->num_rx_pools; p++)
2695                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2696                                 psrtype);
2697 }
2698
2699 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2700 {
2701         struct ixgbe_hw *hw = &adapter->hw;
2702         u32 gcr_ext;
2703         u32 vt_reg_bits;
2704         u32 reg_offset, vf_shift;
2705         u32 vmdctl;
2706
2707         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2708                 return;
2709
2710         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2711         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2712         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2713         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2714
2715         vf_shift = adapter->num_vfs % 32;
2716         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2717
2718         /* Enable only the PF's pool for Tx/Rx */
2719         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2720         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2721         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2722         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2723         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2724
2725         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2726         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2727
2728         /*
2729          * Set up VF register offsets for selected VT Mode,
2730          * i.e. 32 or 64 VFs for SR-IOV
2731          */
2732         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2733         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2734         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2735         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2736
2737         /* enable Tx loopback for VF/PF communication */
2738         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2739 }
2740
2741 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2742 {
2743         struct ixgbe_hw *hw = &adapter->hw;
2744         struct net_device *netdev = adapter->netdev;
2745         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2746         int rx_buf_len;
2747         struct ixgbe_ring *rx_ring;
2748         int i;
2749         u32 mhadd, hlreg0;
2750
2751         /* Decide whether to use packet split mode or not */
2752         /* Do not use packet split if we're in SR-IOV Mode */
2753         if (!adapter->num_vfs)
2754                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2755
2756         /* Set the RX buffer length according to the mode */
2757         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2758                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2759         } else {
2760                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2761                     (netdev->mtu <= ETH_DATA_LEN))
2762                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2763                 else
2764                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2765         }
2766
2767 #ifdef IXGBE_FCOE
2768         /* adjust max frame to be able to do baby jumbo for FCoE */
2769         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2770             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2771                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2772
2773 #endif /* IXGBE_FCOE */
2774         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2775         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2776                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2777                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2778
2779                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2780         }
2781
2782         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2783         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2784         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2785         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2786
2787         /*
2788          * Setup the HW Rx Head and Tail Descriptor Pointers and
2789          * the Base and Length of the Rx Descriptor Ring
2790          */
2791         for (i = 0; i < adapter->num_rx_queues; i++) {
2792                 rx_ring = adapter->rx_ring[i];
2793                 rx_ring->rx_buf_len = rx_buf_len;
2794
2795                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2796                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2797                 else
2798                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2799
2800 #ifdef IXGBE_FCOE
2801                 if (netdev->features & NETIF_F_FCOE_MTU)
2802                 {
2803                         struct ixgbe_ring_feature *f;
2804                         f = &adapter->ring_feature[RING_F_FCOE];
2805                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2806                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2807                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2808                                         rx_ring->rx_buf_len =
2809                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2810                         }
2811                 }
2812 #endif /* IXGBE_FCOE */
2813         }
2814
2815 }
2816
2817 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2818 {
2819         struct ixgbe_hw *hw = &adapter->hw;
2820         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2821
2822         switch (hw->mac.type) {
2823         case ixgbe_mac_82598EB:
2824                 /*
2825                  * For VMDq support of different descriptor types or
2826                  * buffer sizes through the use of multiple SRRCTL
2827                  * registers, RDRXCTL.MVMEN must be set to 1
2828                  *
2829                  * also, the manual doesn't mention it clearly but DCA hints
2830                  * will only use queue 0's tags unless this bit is set.  Side
2831                  * effects of setting this bit are only that SRRCTL must be
2832                  * fully programmed [0..15]
2833                  */
2834                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2835                 break;
2836         case ixgbe_mac_82599EB:
2837                 /* Disable RSC for ACK packets */
2838                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2839                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2840                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2841                 /* hardware requires some bits to be set by default */
2842                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2843                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2844                 break;
2845         default:
2846                 /* We should do nothing since we don't know this hardware */
2847                 return;
2848         }
2849
2850         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2851 }
2852
2853 /**
2854  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2855  * @adapter: board private structure
2856  *
2857  * Configure the Rx unit of the MAC after a reset.
2858  **/
2859 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2860 {
2861         struct ixgbe_hw *hw = &adapter->hw;
2862         struct ixgbe_ring *rx_ring;
2863         int i;
2864         u32 rxctrl;
2865
2866         /* disable receives while setting up the descriptors */
2867         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2868         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2869
2870         ixgbe_setup_psrtype(adapter);
2871         ixgbe_setup_rdrxctl(adapter);
2872
2873         /* Program MRQC for the distribution of queues */
2874         ixgbe_setup_mrqc(adapter);
2875         ixgbe_configure_virtualization(adapter);
2876
2877         /* set_rx_buffer_len must be called before ring initialization */
2878         ixgbe_set_rx_buffer_len(adapter);
2879
2880         /*
2881          * Setup the HW Rx Head and Tail Descriptor Pointers and
2882          * the Base and Length of the Rx Descriptor Ring
2883          */
2884         for (i = 0; i < adapter->num_rx_queues; i++) {
2885                 rx_ring = adapter->rx_ring[i];
2886                 ixgbe_configure_rx_ring(adapter, rx_ring);
2887                 ixgbe_configure_srrctl(adapter, rx_ring);
2888                 ixgbe_configure_rscctl(adapter, rx_ring);
2889         }
2890
2891 }
2892
2893 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2894 {
2895         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2896         struct ixgbe_hw *hw = &adapter->hw;
2897         int pool_ndx = adapter->num_vfs;
2898
2899         /* add VID to filter table */
2900         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2901 }
2902
2903 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2904 {
2905         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2906         struct ixgbe_hw *hw = &adapter->hw;
2907         int pool_ndx = adapter->num_vfs;
2908
2909         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2910                 ixgbe_irq_disable(adapter);
2911
2912         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2913
2914         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2915                 ixgbe_irq_enable(adapter);
2916
2917         /* remove VID from filter table */
2918         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2919 }
2920
2921 /**
2922  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2923  * @adapter: driver data
2924  */
2925 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2926 {
2927         struct ixgbe_hw *hw = &adapter->hw;
2928         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2929         int i, j;
2930
2931         switch (hw->mac.type) {
2932         case ixgbe_mac_82598EB:
2933                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2934 #ifdef CONFIG_IXGBE_DCB
2935                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2936                         vlnctrl &= ~IXGBE_VLNCTRL_VME;
2937 #endif
2938                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2939                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2940                 break;
2941         case ixgbe_mac_82599EB:
2942                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2943                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2944                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2945 #ifdef CONFIG_IXGBE_DCB
2946                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2947                         break;
2948 #endif
2949                 for (i = 0; i < adapter->num_rx_queues; i++) {
2950                         j = adapter->rx_ring[i]->reg_idx;
2951                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2952                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2953                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2954                 }
2955                 break;
2956         default:
2957                 break;
2958         }
2959 }
2960
2961 /**
2962  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2963  * @adapter: driver data
2964  */
2965 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2966 {
2967         struct ixgbe_hw *hw = &adapter->hw;
2968         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2969         int i, j;
2970
2971         switch (hw->mac.type) {
2972         case ixgbe_mac_82598EB:
2973                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2974                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2975                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2976                 break;
2977         case ixgbe_mac_82599EB:
2978                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2979                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2980                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2981                 for (i = 0; i < adapter->num_rx_queues; i++) {
2982                         j = adapter->rx_ring[i]->reg_idx;
2983                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2984                         vlnctrl |= IXGBE_RXDCTL_VME;
2985                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2986                 }
2987                 break;
2988         default:
2989                 break;
2990         }
2991 }
2992
2993 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2994                                    struct vlan_group *grp)
2995 {
2996         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2997
2998         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2999                 ixgbe_irq_disable(adapter);
3000         adapter->vlgrp = grp;
3001
3002         /*
3003          * For a DCB driver, always enable VLAN tag stripping so we can
3004          * still receive traffic from a DCB-enabled host even if we're
3005          * not in DCB mode.
3006          */
3007         ixgbe_vlan_filter_enable(adapter);
3008
3009         ixgbe_vlan_rx_add_vid(netdev, 0);
3010
3011         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3012                 ixgbe_irq_enable(adapter);
3013 }
3014
3015 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3016 {
3017         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3018
3019         if (adapter->vlgrp) {
3020                 u16 vid;
3021                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3022                         if (!vlan_group_get_device(adapter->vlgrp, vid))
3023                                 continue;
3024                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3025                 }
3026         }
3027 }
3028
3029 /**
3030  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3031  * @netdev: network interface device structure
3032  *
3033  * Writes unicast address list to the RAR table.
3034  * Returns: -ENOMEM on failure/insufficient address space
3035  *                0 on no addresses written
3036  *                X on writing X addresses to the RAR table
3037  **/
3038 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3039 {
3040         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3041         struct ixgbe_hw *hw = &adapter->hw;
3042         unsigned int vfn = adapter->num_vfs;
3043         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3044         int count = 0;
3045
3046         /* return ENOMEM indicating insufficient memory for addresses */
3047         if (netdev_uc_count(netdev) > rar_entries)
3048                 return -ENOMEM;
3049
3050         if (!netdev_uc_empty(netdev) && rar_entries) {
3051                 struct netdev_hw_addr *ha;
3052                 /* return error if we do not support writing to RAR table */
3053                 if (!hw->mac.ops.set_rar)
3054                         return -ENOMEM;
3055
3056                 netdev_for_each_uc_addr(ha, netdev) {
3057                         if (!rar_entries)
3058                                 break;
3059                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3060                                             vfn, IXGBE_RAH_AV);
3061                         count++;
3062                 }
3063         }
3064         /* write the addresses in reverse order to avoid write combining */
3065         for (; rar_entries > 0 ; rar_entries--)
3066                 hw->mac.ops.clear_rar(hw, rar_entries);
3067
3068         return count;
3069 }
3070
3071 /**
3072  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3073  * @netdev: network interface device structure
3074  *
3075  * The set_rx_method entry point is called whenever the unicast/multicast
3076  * address list or the network interface flags are updated.  This routine is
3077  * responsible for configuring the hardware for proper unicast, multicast and
3078  * promiscuous mode.
3079  **/
3080 void ixgbe_set_rx_mode(struct net_device *netdev)
3081 {
3082         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3083         struct ixgbe_hw *hw = &adapter->hw;
3084         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3085         int count;
3086
3087         /* Check for Promiscuous and All Multicast modes */
3088
3089         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3090
3091         /* set all bits that we expect to always be set */
3092         fctrl |= IXGBE_FCTRL_BAM;
3093         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3094         fctrl |= IXGBE_FCTRL_PMCF;
3095
3096         /* clear the bits we are changing the status of */
3097         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3098
3099         if (netdev->flags & IFF_PROMISC) {
3100                 hw->addr_ctrl.user_set_promisc = true;
3101                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3102                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3103                 /* don't hardware filter vlans in promisc mode */
3104                 ixgbe_vlan_filter_disable(adapter);
3105         } else {
3106                 if (netdev->flags & IFF_ALLMULTI) {
3107                         fctrl |= IXGBE_FCTRL_MPE;
3108                         vmolr |= IXGBE_VMOLR_MPE;
3109                 } else {
3110                         /*
3111                          * Write addresses to the MTA, if the attempt fails
3112                          * then we should just turn on promiscous mode so
3113                          * that we can at least receive multicast traffic
3114                          */
3115                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3116                         vmolr |= IXGBE_VMOLR_ROMPE;
3117                 }
3118                 ixgbe_vlan_filter_enable(adapter);
3119                 hw->addr_ctrl.user_set_promisc = false;
3120                 /*
3121                  * Write addresses to available RAR registers, if there is not
3122                  * sufficient space to store all the addresses then enable
3123                  * unicast promiscous mode
3124                  */
3125                 count = ixgbe_write_uc_addr_list(netdev);
3126                 if (count < 0) {
3127                         fctrl |= IXGBE_FCTRL_UPE;
3128                         vmolr |= IXGBE_VMOLR_ROPE;
3129                 }
3130         }
3131
3132         if (adapter->num_vfs) {
3133                 ixgbe_restore_vf_multicasts(adapter);
3134                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3135                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3136                            IXGBE_VMOLR_ROPE);
3137                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3138         }
3139
3140         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3141 }
3142
3143 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3144 {
3145         int q_idx;
3146         struct ixgbe_q_vector *q_vector;
3147         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3148
3149         /* legacy and MSI only use one vector */
3150         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3151                 q_vectors = 1;
3152
3153         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3154                 struct napi_struct *napi;
3155                 q_vector = adapter->q_vector[q_idx];
3156                 napi = &q_vector->napi;
3157                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3158                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3159                                 if (q_vector->txr_count == 1)
3160                                         napi->poll = &ixgbe_clean_txonly;
3161                                 else if (q_vector->rxr_count == 1)
3162                                         napi->poll = &ixgbe_clean_rxonly;
3163                         }
3164                 }
3165
3166                 napi_enable(napi);
3167         }
3168 }
3169
3170 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3171 {
3172         int q_idx;
3173         struct ixgbe_q_vector *q_vector;
3174         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3175
3176         /* legacy and MSI only use one vector */
3177         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3178                 q_vectors = 1;
3179
3180         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3181                 q_vector = adapter->q_vector[q_idx];
3182                 napi_disable(&q_vector->napi);
3183         }
3184 }
3185
3186 #ifdef CONFIG_IXGBE_DCB
3187 /*
3188  * ixgbe_configure_dcb - Configure DCB hardware
3189  * @adapter: ixgbe adapter struct
3190  *
3191  * This is called by the driver on open to configure the DCB hardware.
3192  * This is also called by the gennetlink interface when reconfiguring
3193  * the DCB state.
3194  */
3195 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3196 {
3197         struct ixgbe_hw *hw = &adapter->hw;
3198         u32 txdctl;
3199         int i, j;
3200
3201         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3202                 if (hw->mac.type == ixgbe_mac_82598EB)
3203                         netif_set_gso_max_size(adapter->netdev, 65536);
3204                 return;
3205         }
3206
3207         if (hw->mac.type == ixgbe_mac_82598EB)
3208                 netif_set_gso_max_size(adapter->netdev, 32768);
3209
3210         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3211         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3212         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3213
3214         /* reconfigure the hardware */
3215         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3216
3217         for (i = 0; i < adapter->num_tx_queues; i++) {
3218                 j = adapter->tx_ring[i]->reg_idx;
3219                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3220                 /* PThresh workaround for Tx hang with DFP enabled. */
3221                 txdctl |= 32;
3222                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3223         }
3224         /* Enable VLAN tag insert/strip */
3225         ixgbe_vlan_filter_enable(adapter);
3226
3227         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3228 }
3229
3230 #endif
3231 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3232 {
3233         struct net_device *netdev = adapter->netdev;
3234         struct ixgbe_hw *hw = &adapter->hw;
3235         int i;
3236
3237         ixgbe_set_rx_mode(netdev);
3238
3239         ixgbe_restore_vlan(adapter);
3240 #ifdef CONFIG_IXGBE_DCB
3241         ixgbe_configure_dcb(adapter);
3242 #endif
3243
3244 #ifdef IXGBE_FCOE
3245         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3246                 ixgbe_configure_fcoe(adapter);
3247
3248 #endif /* IXGBE_FCOE */
3249         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3250                 for (i = 0; i < adapter->num_tx_queues; i++)
3251                         adapter->tx_ring[i]->atr_sample_rate =
3252                                                        adapter->atr_sample_rate;
3253                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3254         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3255                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3256         }
3257
3258         ixgbe_configure_tx(adapter);
3259         ixgbe_configure_rx(adapter);
3260         for (i = 0; i < adapter->num_rx_queues; i++)
3261                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3262                                        (adapter->rx_ring[i]->count - 1));
3263 }
3264
3265 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3266 {
3267         switch (hw->phy.type) {
3268         case ixgbe_phy_sfp_avago:
3269         case ixgbe_phy_sfp_ftl:
3270         case ixgbe_phy_sfp_intel:
3271         case ixgbe_phy_sfp_unknown:
3272         case ixgbe_phy_sfp_passive_tyco:
3273         case ixgbe_phy_sfp_passive_unknown:
3274         case ixgbe_phy_sfp_active_unknown:
3275         case ixgbe_phy_sfp_ftl_active:
3276                 return true;
3277         default:
3278                 return false;
3279         }
3280 }
3281
3282 /**
3283  * ixgbe_sfp_link_config - set up SFP+ link
3284  * @adapter: pointer to private adapter struct
3285  **/
3286 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3287 {
3288         struct ixgbe_hw *hw = &adapter->hw;
3289
3290                 if (hw->phy.multispeed_fiber) {
3291                         /*
3292                          * In multispeed fiber setups, the device may not have
3293                          * had a physical connection when the driver loaded.
3294                          * If that's the case, the initial link configuration
3295                          * couldn't get the MAC into 10G or 1G mode, so we'll
3296                          * never have a link status change interrupt fire.
3297                          * We need to try and force an autonegotiation
3298                          * session, then bring up link.
3299                          */
3300                         hw->mac.ops.setup_sfp(hw);
3301                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3302                                 schedule_work(&adapter->multispeed_fiber_task);
3303                 } else {
3304                         /*
3305                          * Direct Attach Cu and non-multispeed fiber modules
3306                          * still need to be configured properly prior to
3307                          * attempting link.
3308                          */
3309                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3310                                 schedule_work(&adapter->sfp_config_module_task);
3311                 }
3312 }
3313
3314 /**
3315  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3316  * @hw: pointer to private hardware struct
3317  *
3318  * Returns 0 on success, negative on failure
3319  **/
3320 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3321 {
3322         u32 autoneg;
3323         bool negotiation, link_up = false;
3324         u32 ret = IXGBE_ERR_LINK_SETUP;
3325
3326         if (hw->mac.ops.check_link)
3327                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3328
3329         if (ret)
3330                 goto link_cfg_out;
3331
3332         if (hw->mac.ops.get_link_capabilities)
3333                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3334         if (ret)
3335                 goto link_cfg_out;
3336
3337         if (hw->mac.ops.setup_link)
3338                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3339 link_cfg_out:
3340         return ret;
3341 }
3342
3343 #define IXGBE_MAX_RX_DESC_POLL 10
3344 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3345                                               int rxr)
3346 {
3347         int j = adapter->rx_ring[rxr]->reg_idx;
3348         int k;
3349
3350         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3351                 if (IXGBE_READ_REG(&adapter->hw,
3352                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3353                         break;
3354                 else
3355                         msleep(1);
3356         }
3357         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3358                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3359                       "the polling period\n", rxr);
3360         }
3361         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3362                               (adapter->rx_ring[rxr]->count - 1));
3363 }
3364
3365 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3366 {
3367         struct ixgbe_hw *hw = &adapter->hw;
3368         int i, j = 0;
3369         int num_rx_rings = adapter->num_rx_queues;
3370         int err;
3371         u32 txdctl, rxdctl;
3372         u32 dmatxctl;
3373         u32 gpie;
3374         u32 ctrl_ext;
3375
3376         ixgbe_get_hw_control(adapter);
3377
3378         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3379             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3380                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3381                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3382                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3383                 } else {
3384                         /* MSI only */
3385                         gpie = 0;
3386                 }
3387                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3388                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3389                         gpie |= IXGBE_GPIE_VTMODE_64;
3390                 }
3391                 /* XXX: to interrupt immediately for EICS writes, enable this */
3392                 /* gpie |= IXGBE_GPIE_EIMEN; */
3393                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3394         }
3395
3396         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3397                 /*
3398                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3399                  * this saves a register write for every interrupt
3400                  */
3401                 switch (hw->mac.type) {
3402                 case ixgbe_mac_82598EB:
3403                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3404                         break;
3405                 default:
3406                 case ixgbe_mac_82599EB:
3407                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3408                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3409                         break;
3410                 }
3411         } else {
3412                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3413                  * specifically only auto mask tx and rx interrupts */
3414                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3415         }
3416
3417         /* Enable Thermal over heat sensor interrupt */
3418         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3419                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3420                 gpie |= IXGBE_SDP0_GPIEN;
3421                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3422         }
3423
3424         /* Enable fan failure interrupt if media type is copper */
3425         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3426                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3427                 gpie |= IXGBE_SDP1_GPIEN;
3428                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3429         }
3430
3431         if (hw->mac.type == ixgbe_mac_82599EB) {
3432                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3433                 gpie |= IXGBE_SDP1_GPIEN;
3434                 gpie |= IXGBE_SDP2_GPIEN;
3435                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3436         }
3437
3438         if (hw->mac.type == ixgbe_mac_82599EB) {
3439                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3440                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3441                 dmatxctl |= IXGBE_DMATXCTL_TE;
3442                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3443         }
3444         for (i = 0; i < adapter->num_tx_queues; i++) {
3445                 j = adapter->tx_ring[i]->reg_idx;
3446                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3447                 if (adapter->rx_itr_setting == 0) {
3448                         /* cannot set wthresh when itr==0 */
3449                         txdctl &= ~0x007F0000;
3450                 } else {
3451                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3452                         txdctl |= (8 << 16);
3453                 }
3454                 txdctl |= IXGBE_TXDCTL_ENABLE;
3455                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3456                 if (hw->mac.type == ixgbe_mac_82599EB) {
3457                         int wait_loop = 10;
3458                         /* poll for Tx Enable ready */
3459                         do {
3460                                 msleep(1);
3461                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3462                         } while (--wait_loop &&
3463                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3464                         if (!wait_loop)
3465                                 e_err(drv, "Could not enable Tx Queue %d\n", j);
3466                 }
3467         }
3468
3469         for (i = 0; i < num_rx_rings; i++) {
3470                 j = adapter->rx_ring[i]->reg_idx;
3471                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3472                 /* enable PTHRESH=32 descriptors (half the internal cache)
3473                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3474                  * this also removes a pesky rx_no_buffer_count increment */
3475                 rxdctl |= 0x0020;
3476                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3477                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3478                 if (hw->mac.type == ixgbe_mac_82599EB)
3479                         ixgbe_rx_desc_queue_enable(adapter, i);
3480         }
3481         /* enable all receives */
3482         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3483         if (hw->mac.type == ixgbe_mac_82598EB)
3484                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3485         else
3486                 rxdctl |= IXGBE_RXCTRL_RXEN;
3487         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3488
3489         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3490                 ixgbe_configure_msix(adapter);
3491         else
3492                 ixgbe_configure_msi_and_legacy(adapter);
3493
3494         /* enable the optics */
3495         if (hw->phy.multispeed_fiber)
3496                 hw->mac.ops.enable_tx_laser(hw);
3497
3498         clear_bit(__IXGBE_DOWN, &adapter->state);
3499         ixgbe_napi_enable_all(adapter);
3500
3501         /* clear any pending interrupts, may auto mask */
3502         IXGBE_READ_REG(hw, IXGBE_EICR);
3503
3504         ixgbe_irq_enable(adapter);
3505
3506         /*
3507          * If this adapter has a fan, check to see if we had a failure
3508          * before we enabled the interrupt.
3509          */
3510         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3511                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3512                 if (esdp & IXGBE_ESDP_SDP1)
3513                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3514         }
3515
3516         /*
3517          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3518          * arrived before interrupts were enabled but after probe.  Such
3519          * devices wouldn't have their type identified yet. We need to
3520          * kick off the SFP+ module setup first, then try to bring up link.
3521          * If we're not hot-pluggable SFP+, we just need to configure link
3522          * and bring it up.
3523          */
3524         if (hw->phy.type == ixgbe_phy_unknown) {
3525                 err = hw->phy.ops.identify(hw);
3526                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3527                         /*
3528                          * Take the device down and schedule the sfp tasklet
3529                          * which will unregister_netdev and log it.
3530                          */
3531                         ixgbe_down(adapter);
3532                         schedule_work(&adapter->sfp_config_module_task);
3533                         return err;
3534                 }
3535         }
3536
3537         if (ixgbe_is_sfp(hw)) {
3538                 ixgbe_sfp_link_config(adapter);
3539         } else {
3540                 err = ixgbe_non_sfp_link_config(hw);
3541                 if (err)
3542                         e_err(probe, "link_config FAILED %d\n", err);
3543         }
3544
3545         for (i = 0; i < adapter->num_tx_queues; i++)
3546                 set_bit(__IXGBE_FDIR_INIT_DONE,
3547                         &(adapter->tx_ring[i]->reinit_state));
3548
3549         /* enable transmits */
3550         netif_tx_start_all_queues(adapter->netdev);
3551
3552         /* bring the link up in the watchdog, this could race with our first
3553          * link up interrupt but shouldn't be a problem */
3554         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3555         adapter->link_check_timeout = jiffies;
3556         mod_timer(&adapter->watchdog_timer, jiffies);
3557
3558         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3559         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3560         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3561         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3562
3563         return 0;
3564 }
3565
3566 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3567 {
3568         WARN_ON(in_interrupt());
3569         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3570                 msleep(1);
3571         ixgbe_down(adapter);
3572         /*
3573          * If SR-IOV enabled then wait a bit before bringing the adapter
3574          * back up to give the VFs time to respond to the reset.  The
3575          * two second wait is based upon the watchdog timer cycle in
3576          * the VF driver.
3577          */
3578         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3579                 msleep(2000);
3580         ixgbe_up(adapter);
3581         clear_bit(__IXGBE_RESETTING, &adapter->state);
3582 }
3583
3584 int ixgbe_up(struct ixgbe_adapter *adapter)
3585 {
3586         /* hardware has been reset, we need to reload some things */
3587         ixgbe_configure(adapter);
3588
3589         return ixgbe_up_complete(adapter);
3590 }
3591
3592 void ixgbe_reset(struct ixgbe_adapter *adapter)
3593 {
3594         struct ixgbe_hw *hw = &adapter->hw;
3595         int err;
3596
3597         err = hw->mac.ops.init_hw(hw);
3598         switch (err) {
3599         case 0:
3600         case IXGBE_ERR_SFP_NOT_PRESENT:
3601                 break;
3602         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3603                 e_dev_err("master disable timed out\n");
3604                 break;
3605         case IXGBE_ERR_EEPROM_VERSION:
3606                 /* We are running on a pre-production device, log a warning */
3607                 e_dev_warn("This device is a pre-production adapter/LOM. "
3608                            "Please be aware there may be issuesassociated with "
3609                            "your hardware.  If you are experiencing problems "
3610                            "please contact your Intel or hardware "
3611                            "representative who provided you with this "
3612                            "hardware.\n");
3613                 break;
3614         default:
3615                 e_dev_err("Hardware Error: %d\n", err);
3616         }
3617
3618         /* reprogram the RAR[0] in case user changed it. */
3619         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3620                             IXGBE_RAH_AV);
3621 }
3622
3623 /**
3624  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3625  * @adapter: board private structure
3626  * @rx_ring: ring to free buffers from
3627  **/
3628 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3629                                 struct ixgbe_ring *rx_ring)
3630 {
3631         struct pci_dev *pdev = adapter->pdev;
3632         unsigned long size;
3633         unsigned int i;
3634
3635         /* Free all the Rx ring sk_buffs */
3636
3637         for (i = 0; i < rx_ring->count; i++) {
3638                 struct ixgbe_rx_buffer *rx_buffer_info;
3639
3640                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3641                 if (rx_buffer_info->dma) {
3642                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3643                                          rx_ring->rx_buf_len,
3644                                          DMA_FROM_DEVICE);
3645                         rx_buffer_info->dma = 0;
3646                 }
3647                 if (rx_buffer_info->skb) {
3648                         struct sk_buff *skb = rx_buffer_info->skb;
3649                         rx_buffer_info->skb = NULL;
3650                         do {
3651                                 struct sk_buff *this = skb;
3652                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3653                                         dma_unmap_single(&pdev->dev,
3654                                                          IXGBE_RSC_CB(this)->dma,
3655                                                          rx_ring->rx_buf_len,
3656                                                          DMA_FROM_DEVICE);
3657                                         IXGBE_RSC_CB(this)->dma = 0;
3658                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3659                                 }
3660                                 skb = skb->prev;
3661                                 dev_kfree_skb(this);
3662                         } while (skb);
3663                 }
3664                 if (!rx_buffer_info->page)
3665                         continue;
3666                 if (rx_buffer_info->page_dma) {
3667                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3668                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3669                         rx_buffer_info->page_dma = 0;
3670                 }
3671                 put_page(rx_buffer_info->page);
3672                 rx_buffer_info->page = NULL;
3673                 rx_buffer_info->page_offset = 0;
3674         }
3675
3676         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3677         memset(rx_ring->rx_buffer_info, 0, size);
3678
3679         /* Zero out the descriptor ring */
3680         memset(rx_ring->desc, 0, rx_ring->size);
3681
3682         rx_ring->next_to_clean = 0;
3683         rx_ring->next_to_use = 0;
3684
3685         if (rx_ring->head)
3686                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3687         if (rx_ring->tail)
3688                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3689 }
3690
3691 /**
3692  * ixgbe_clean_tx_ring - Free Tx Buffers
3693  * @adapter: board private structure
3694  * @tx_ring: ring to be cleaned
3695  **/
3696 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3697                                 struct ixgbe_ring *tx_ring)
3698 {
3699         struct ixgbe_tx_buffer *tx_buffer_info;
3700         unsigned long size;
3701         unsigned int i;
3702
3703         /* Free all the Tx ring sk_buffs */
3704
3705         for (i = 0; i < tx_ring->count; i++) {
3706                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3707                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3708         }
3709
3710         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3711         memset(tx_ring->tx_buffer_info, 0, size);
3712
3713         /* Zero out the descriptor ring */
3714         memset(tx_ring->desc, 0, tx_ring->size);
3715
3716         tx_ring->next_to_use = 0;
3717         tx_ring->next_to_clean = 0;
3718
3719         if (tx_ring->head)
3720                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3721         if (tx_ring->tail)
3722                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3723 }
3724
3725 /**
3726  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3727  * @adapter: board private structure
3728  **/
3729 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3730 {
3731         int i;
3732
3733         for (i = 0; i < adapter->num_rx_queues; i++)
3734                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3735 }
3736
3737 /**
3738  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3739  * @adapter: board private structure
3740  **/
3741 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3742 {
3743         int i;
3744
3745         for (i = 0; i < adapter->num_tx_queues; i++)
3746                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3747 }
3748
3749 void ixgbe_down(struct ixgbe_adapter *adapter)
3750 {
3751         struct net_device *netdev = adapter->netdev;
3752         struct ixgbe_hw *hw = &adapter->hw;
3753         u32 rxctrl;
3754         u32 txdctl;
3755         int i, j;
3756
3757         /* signal that we are down to the interrupt handler */
3758         set_bit(__IXGBE_DOWN, &adapter->state);
3759
3760         /* disable receive for all VFs and wait one second */
3761         if (adapter->num_vfs) {
3762                 /* ping all the active vfs to let them know we are going down */
3763                 ixgbe_ping_all_vfs(adapter);
3764
3765                 /* Disable all VFTE/VFRE TX/RX */
3766                 ixgbe_disable_tx_rx(adapter);
3767
3768                 /* Mark all the VFs as inactive */
3769                 for (i = 0 ; i < adapter->num_vfs; i++)
3770                         adapter->vfinfo[i].clear_to_send = 0;
3771         }
3772
3773         /* disable receives */
3774         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3775         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3776
3777         IXGBE_WRITE_FLUSH(hw);
3778         msleep(10);
3779
3780         netif_tx_stop_all_queues(netdev);
3781
3782         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3783         del_timer_sync(&adapter->sfp_timer);
3784         del_timer_sync(&adapter->watchdog_timer);
3785         cancel_work_sync(&adapter->watchdog_task);
3786
3787         netif_carrier_off(netdev);
3788         netif_tx_disable(netdev);
3789
3790         ixgbe_irq_disable(adapter);
3791
3792         ixgbe_napi_disable_all(adapter);
3793
3794         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3795             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3796                 cancel_work_sync(&adapter->fdir_reinit_task);
3797
3798         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3799                 cancel_work_sync(&adapter->check_overtemp_task);
3800
3801         /* disable transmits in the hardware now that interrupts are off */
3802         for (i = 0; i < adapter->num_tx_queues; i++) {
3803                 j = adapter->tx_ring[i]->reg_idx;
3804                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3805                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3806                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3807         }
3808         /* Disable the Tx DMA engine on 82599 */
3809         if (hw->mac.type == ixgbe_mac_82599EB)
3810                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3811                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3812                                  ~IXGBE_DMATXCTL_TE));
3813
3814         /* power down the optics */
3815         if (hw->phy.multispeed_fiber)
3816                 hw->mac.ops.disable_tx_laser(hw);
3817
3818         /* clear n-tuple filters that are cached */
3819         ethtool_ntuple_flush(netdev);
3820
3821         if (!pci_channel_offline(adapter->pdev))
3822                 ixgbe_reset(adapter);
3823         ixgbe_clean_all_tx_rings(adapter);
3824         ixgbe_clean_all_rx_rings(adapter);
3825
3826 #ifdef CONFIG_IXGBE_DCA
3827         /* since we reset the hardware DCA settings were cleared */
3828         ixgbe_setup_dca(adapter);
3829 #endif
3830 }
3831
3832 /**
3833  * ixgbe_poll - NAPI Rx polling callback
3834  * @napi: structure for representing this polling device
3835  * @budget: how many packets driver is allowed to clean
3836  *
3837  * This function is used for legacy and MSI, NAPI mode
3838  **/
3839 static int ixgbe_poll(struct napi_struct *napi, int budget)
3840 {
3841         struct ixgbe_q_vector *q_vector =
3842                                 container_of(napi, struct ixgbe_q_vector, napi);
3843         struct ixgbe_adapter *adapter = q_vector->adapter;
3844         int tx_clean_complete, work_done = 0;
3845
3846 #ifdef CONFIG_IXGBE_DCA
3847         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3848                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3849                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3850         }
3851 #endif
3852
3853         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3854         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3855
3856         if (!tx_clean_complete)
3857                 work_done = budget;
3858
3859         /* If budget not fully consumed, exit the polling mode */
3860         if (work_done < budget) {
3861                 napi_complete(napi);
3862                 if (adapter->rx_itr_setting & 1)
3863                         ixgbe_set_itr(adapter);
3864                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3865                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3866         }
3867         return work_done;
3868 }
3869
3870 /**
3871  * ixgbe_tx_timeout - Respond to a Tx Hang
3872  * @netdev: network interface device structure
3873  **/
3874 static void ixgbe_tx_timeout(struct net_device *netdev)
3875 {
3876         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3877
3878         /* Do the reset outside of interrupt context */
3879         schedule_work(&adapter->reset_task);
3880 }
3881
3882 static void ixgbe_reset_task(struct work_struct *work)
3883 {
3884         struct ixgbe_adapter *adapter;
3885         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3886
3887         /* If we're already down or resetting, just bail */
3888         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3889             test_bit(__IXGBE_RESETTING, &adapter->state))
3890                 return;
3891
3892         adapter->tx_timeout_count++;
3893
3894         ixgbe_dump(adapter);
3895         netdev_err(adapter->netdev, "Reset adapter\n");
3896         ixgbe_reinit_locked(adapter);
3897 }
3898
3899 #ifdef CONFIG_IXGBE_DCB
3900 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3901 {
3902         bool ret = false;
3903         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3904
3905         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3906                 return ret;
3907
3908         f->mask = 0x7 << 3;
3909         adapter->num_rx_queues = f->indices;
3910         adapter->num_tx_queues = f->indices;
3911         ret = true;
3912
3913         return ret;
3914 }
3915 #endif
3916
3917 /**
3918  * ixgbe_set_rss_queues: Allocate queues for RSS
3919  * @adapter: board private structure to initialize
3920  *
3921  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3922  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3923  *
3924  **/
3925 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3926 {
3927         bool ret = false;
3928         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3929
3930         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3931                 f->mask = 0xF;
3932                 adapter->num_rx_queues = f->indices;
3933                 adapter->num_tx_queues = f->indices;
3934                 ret = true;
3935         } else {
3936                 ret = false;
3937         }
3938
3939         return ret;
3940 }
3941
3942 /**
3943  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3944  * @adapter: board private structure to initialize
3945  *
3946  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3947  * to the original CPU that initiated the Tx session.  This runs in addition
3948  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3949  * Rx load across CPUs using RSS.
3950  *
3951  **/
3952 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3953 {
3954         bool ret = false;
3955         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3956
3957         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3958         f_fdir->mask = 0;
3959
3960         /* Flow Director must have RSS enabled */
3961         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3962             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3963              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3964                 adapter->num_tx_queues = f_fdir->indices;
3965                 adapter->num_rx_queues = f_fdir->indices;
3966                 ret = true;
3967         } else {
3968                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3969                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3970         }
3971         return ret;
3972 }
3973
3974 #ifdef IXGBE_FCOE
3975 /**
3976  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3977  * @adapter: board private structure to initialize
3978  *
3979  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3980  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3981  * rx queues out of the max number of rx queues, instead, it is used as the
3982  * index of the first rx queue used by FCoE.
3983  *
3984  **/
3985 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3986 {
3987         bool ret = false;
3988         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3989
3990         f->indices = min((int)num_online_cpus(), f->indices);
3991         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3992                 adapter->num_rx_queues = 1;
3993                 adapter->num_tx_queues = 1;
3994 #ifdef CONFIG_IXGBE_DCB
3995                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3996                         e_info(probe, "FCoE enabled with DCB\n");
3997                         ixgbe_set_dcb_queues(adapter);
3998                 }
3999 #endif
4000                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4001                         e_info(probe, "FCoE enabled with RSS\n");
4002                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4003                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4004                                 ixgbe_set_fdir_queues(adapter);
4005                         else
4006                                 ixgbe_set_rss_queues(adapter);
4007                 }
4008                 /* adding FCoE rx rings to the end */
4009                 f->mask = adapter->num_rx_queues;
4010                 adapter->num_rx_queues += f->indices;
4011                 adapter->num_tx_queues += f->indices;
4012
4013                 ret = true;
4014         }
4015
4016         return ret;
4017 }
4018
4019 #endif /* IXGBE_FCOE */
4020 /**
4021  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4022  * @adapter: board private structure to initialize
4023  *
4024  * IOV doesn't actually use anything, so just NAK the
4025  * request for now and let the other queue routines
4026  * figure out what to do.
4027  */
4028 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4029 {
4030         return false;
4031 }
4032
4033 /*
4034  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4035  * @adapter: board private structure to initialize
4036  *
4037  * This is the top level queue allocation routine.  The order here is very
4038  * important, starting with the "most" number of features turned on at once,
4039  * and ending with the smallest set of features.  This way large combinations
4040  * can be allocated if they're turned on, and smaller combinations are the
4041  * fallthrough conditions.
4042  *
4043  **/
4044 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4045 {
4046         /* Start with base case */
4047         adapter->num_rx_queues = 1;
4048         adapter->num_tx_queues = 1;
4049         adapter->num_rx_pools = adapter->num_rx_queues;
4050         adapter->num_rx_queues_per_pool = 1;
4051
4052         if (ixgbe_set_sriov_queues(adapter))
4053                 return;
4054
4055 #ifdef IXGBE_FCOE
4056         if (ixgbe_set_fcoe_queues(adapter))
4057                 goto done;
4058
4059 #endif /* IXGBE_FCOE */
4060 #ifdef CONFIG_IXGBE_DCB
4061         if (ixgbe_set_dcb_queues(adapter))
4062                 goto done;
4063
4064 #endif
4065         if (ixgbe_set_fdir_queues(adapter))
4066                 goto done;
4067
4068         if (ixgbe_set_rss_queues(adapter))
4069                 goto done;
4070
4071         /* fallback to base case */
4072         adapter->num_rx_queues = 1;
4073         adapter->num_tx_queues = 1;
4074
4075 done:
4076         /* Notify the stack of the (possibly) reduced Tx Queue count. */
4077         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4078 }
4079
4080 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4081                                        int vectors)
4082 {
4083         int err, vector_threshold;
4084
4085         /* We'll want at least 3 (vector_threshold):
4086          * 1) TxQ[0] Cleanup
4087          * 2) RxQ[0] Cleanup
4088          * 3) Other (Link Status Change, etc.)
4089          * 4) TCP Timer (optional)
4090          */
4091         vector_threshold = MIN_MSIX_COUNT;
4092
4093         /* The more we get, the more we will assign to Tx/Rx Cleanup
4094          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4095          * Right now, we simply care about how many we'll get; we'll
4096          * set them up later while requesting irq's.
4097          */
4098         while (vectors >= vector_threshold) {
4099                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4100                                       vectors);
4101                 if (!err) /* Success in acquiring all requested vectors. */
4102                         break;
4103                 else if (err < 0)
4104                         vectors = 0; /* Nasty failure, quit now */
4105                 else /* err == number of vectors we should try again with */
4106                         vectors = err;
4107         }
4108
4109         if (vectors < vector_threshold) {
4110                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4111                  * This just means we'll go with either a single MSI
4112                  * vector or fall back to legacy interrupts.
4113                  */
4114                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4115                              "Unable to allocate MSI-X interrupts\n");
4116                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4117                 kfree(adapter->msix_entries);
4118                 adapter->msix_entries = NULL;
4119         } else {
4120                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4121                 /*
4122                  * Adjust for only the vectors we'll use, which is minimum
4123                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4124                  * vectors we were allocated.
4125                  */
4126                 adapter->num_msix_vectors = min(vectors,
4127                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4128         }
4129 }
4130
4131 /**
4132  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4133  * @adapter: board private structure to initialize
4134  *
4135  * Cache the descriptor ring offsets for RSS to the assigned rings.
4136  *
4137  **/
4138 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4139 {
4140         int i;
4141         bool ret = false;
4142
4143         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4144                 for (i = 0; i < adapter->num_rx_queues; i++)
4145                         adapter->rx_ring[i]->reg_idx = i;
4146                 for (i = 0; i < adapter->num_tx_queues; i++)
4147                         adapter->tx_ring[i]->reg_idx = i;
4148                 ret = true;
4149         } else {
4150                 ret = false;
4151         }
4152
4153         return ret;
4154 }
4155
4156 #ifdef CONFIG_IXGBE_DCB
4157 /**
4158  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4159  * @adapter: board private structure to initialize
4160  *
4161  * Cache the descriptor ring offsets for DCB to the assigned rings.
4162  *
4163  **/
4164 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4165 {
4166         int i;
4167         bool ret = false;
4168         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4169
4170         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4171                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4172                         /* the number of queues is assumed to be symmetric */
4173                         for (i = 0; i < dcb_i; i++) {
4174                                 adapter->rx_ring[i]->reg_idx = i << 3;
4175                                 adapter->tx_ring[i]->reg_idx = i << 2;
4176                         }
4177                         ret = true;
4178                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4179                         if (dcb_i == 8) {
4180                                 /*
4181                                  * Tx TC0 starts at: descriptor queue 0
4182                                  * Tx TC1 starts at: descriptor queue 32
4183                                  * Tx TC2 starts at: descriptor queue 64
4184                                  * Tx TC3 starts at: descriptor queue 80
4185                                  * Tx TC4 starts at: descriptor queue 96
4186                                  * Tx TC5 starts at: descriptor queue 104
4187                                  * Tx TC6 starts at: descriptor queue 112
4188                                  * Tx TC7 starts at: descriptor queue 120
4189                                  *
4190                                  * Rx TC0-TC7 are offset by 16 queues each
4191                                  */
4192                                 for (i = 0; i < 3; i++) {
4193                                         adapter->tx_ring[i]->reg_idx = i << 5;
4194                                         adapter->rx_ring[i]->reg_idx = i << 4;
4195                                 }
4196                                 for ( ; i < 5; i++) {
4197                                         adapter->tx_ring[i]->reg_idx =
4198                                                                  ((i + 2) << 4);
4199                                         adapter->rx_ring[i]->reg_idx = i << 4;
4200                                 }
4201                                 for ( ; i < dcb_i; i++) {
4202                                         adapter->tx_ring[i]->reg_idx =
4203                                                                  ((i + 8) << 3);
4204                                         adapter->rx_ring[i]->reg_idx = i << 4;
4205                                 }
4206
4207                                 ret = true;
4208                         } else if (dcb_i == 4) {
4209                                 /*
4210                                  * Tx TC0 starts at: descriptor queue 0
4211                                  * Tx TC1 starts at: descriptor queue 64
4212                                  * Tx TC2 starts at: descriptor queue 96
4213                                  * Tx TC3 starts at: descriptor queue 112
4214                                  *
4215                                  * Rx TC0-TC3 are offset by 32 queues each
4216                                  */
4217                                 adapter->tx_ring[0]->reg_idx = 0;
4218                                 adapter->tx_ring[1]->reg_idx = 64;
4219                                 adapter->tx_ring[2]->reg_idx = 96;
4220                                 adapter->tx_ring[3]->reg_idx = 112;
4221                                 for (i = 0 ; i < dcb_i; i++)
4222                                         adapter->rx_ring[i]->reg_idx = i << 5;
4223
4224                                 ret = true;
4225                         } else {
4226                                 ret = false;
4227                         }
4228                 } else {
4229                         ret = false;
4230                 }
4231         } else {
4232                 ret = false;
4233         }
4234
4235         return ret;
4236 }
4237 #endif
4238
4239 /**
4240  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4241  * @adapter: board private structure to initialize
4242  *
4243  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4244  *
4245  **/
4246 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4247 {
4248         int i;
4249         bool ret = false;
4250
4251         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4252             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4253              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4254                 for (i = 0; i < adapter->num_rx_queues; i++)
4255                         adapter->rx_ring[i]->reg_idx = i;
4256                 for (i = 0; i < adapter->num_tx_queues; i++)
4257                         adapter->tx_ring[i]->reg_idx = i;
4258                 ret = true;
4259         }
4260
4261         return ret;
4262 }
4263
4264 #ifdef IXGBE_FCOE
4265 /**
4266  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4267  * @adapter: board private structure to initialize
4268  *
4269  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4270  *
4271  */
4272 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4273 {
4274         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4275         bool ret = false;
4276         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4277
4278         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4279 #ifdef CONFIG_IXGBE_DCB
4280                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4281                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4282
4283                         ixgbe_cache_ring_dcb(adapter);
4284                         /* find out queues in TC for FCoE */
4285                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4286                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4287                         /*
4288                          * In 82599, the number of Tx queues for each traffic
4289                          * class for both 8-TC and 4-TC modes are:
4290                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4291                          * 8 TCs:  32  32  16  16   8   8   8   8
4292                          * 4 TCs:  64  64  32  32
4293                          * We have max 8 queues for FCoE, where 8 the is
4294                          * FCoE redirection table size. If TC for FCoE is
4295                          * less than or equal to TC3, we have enough queues
4296                          * to add max of 8 queues for FCoE, so we start FCoE
4297                          * tx descriptor from the next one, i.e., reg_idx + 1.
4298                          * If TC for FCoE is above TC3, implying 8 TC mode,
4299                          * and we need 8 for FCoE, we have to take all queues
4300                          * in that traffic class for FCoE.
4301                          */
4302                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4303                                 fcoe_tx_i--;
4304                 }
4305 #endif /* CONFIG_IXGBE_DCB */
4306                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4307                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4308                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4309                                 ixgbe_cache_ring_fdir(adapter);
4310                         else
4311                                 ixgbe_cache_ring_rss(adapter);
4312
4313                         fcoe_rx_i = f->mask;
4314                         fcoe_tx_i = f->mask;
4315                 }
4316                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4317                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4318                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4319                 }
4320                 ret = true;
4321         }
4322         return ret;
4323 }
4324
4325 #endif /* IXGBE_FCOE */
4326 /**
4327  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4328  * @adapter: board private structure to initialize
4329  *
4330  * SR-IOV doesn't use any descriptor rings but changes the default if
4331  * no other mapping is used.
4332  *
4333  */
4334 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4335 {
4336         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4337         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4338         if (adapter->num_vfs)
4339                 return true;
4340         else
4341                 return false;
4342 }
4343
4344 /**
4345  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4346  * @adapter: board private structure to initialize
4347  *
4348  * Once we know the feature-set enabled for the device, we'll cache
4349  * the register offset the descriptor ring is assigned to.
4350  *
4351  * Note, the order the various feature calls is important.  It must start with
4352  * the "most" features enabled at the same time, then trickle down to the
4353  * least amount of features turned on at once.
4354  **/
4355 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4356 {
4357         /* start with default case */
4358         adapter->rx_ring[0]->reg_idx = 0;
4359         adapter->tx_ring[0]->reg_idx = 0;
4360
4361         if (ixgbe_cache_ring_sriov(adapter))
4362                 return;
4363
4364 #ifdef IXGBE_FCOE
4365         if (ixgbe_cache_ring_fcoe(adapter))
4366                 return;
4367
4368 #endif /* IXGBE_FCOE */
4369 #ifdef CONFIG_IXGBE_DCB
4370         if (ixgbe_cache_ring_dcb(adapter))
4371                 return;
4372
4373 #endif
4374         if (ixgbe_cache_ring_fdir(adapter))
4375                 return;
4376
4377         if (ixgbe_cache_ring_rss(adapter))
4378                 return;
4379 }
4380
4381 /**
4382  * ixgbe_alloc_queues - Allocate memory for all rings
4383  * @adapter: board private structure to initialize
4384  *
4385  * We allocate one ring per queue at run-time since we don't know the
4386  * number of queues at compile-time.  The polling_netdev array is
4387  * intended for Multiqueue, but should work fine with a single queue.
4388  **/
4389 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4390 {
4391         int i;
4392         int orig_node = adapter->node;
4393
4394         for (i = 0; i < adapter->num_tx_queues; i++) {
4395                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4396                 if (orig_node == -1) {
4397                         int cur_node = next_online_node(adapter->node);
4398                         if (cur_node == MAX_NUMNODES)
4399                                 cur_node = first_online_node;
4400                         adapter->node = cur_node;
4401                 }
4402                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4403                                     adapter->node);
4404                 if (!ring)
4405                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4406                 if (!ring)
4407                         goto err_tx_ring_allocation;
4408                 ring->count = adapter->tx_ring_count;
4409                 ring->queue_index = i;
4410                 ring->numa_node = adapter->node;
4411
4412                 adapter->tx_ring[i] = ring;
4413         }
4414
4415         /* Restore the adapter's original node */
4416         adapter->node = orig_node;
4417
4418         for (i = 0; i < adapter->num_rx_queues; i++) {
4419                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4420                 if (orig_node == -1) {
4421                         int cur_node = next_online_node(adapter->node);
4422                         if (cur_node == MAX_NUMNODES)
4423                                 cur_node = first_online_node;
4424                         adapter->node = cur_node;
4425                 }
4426                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4427                                     adapter->node);
4428                 if (!ring)
4429                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4430                 if (!ring)
4431                         goto err_rx_ring_allocation;
4432                 ring->count = adapter->rx_ring_count;
4433                 ring->queue_index = i;
4434                 ring->numa_node = adapter->node;
4435
4436                 adapter->rx_ring[i] = ring;
4437         }
4438
4439         /* Restore the adapter's original node */
4440         adapter->node = orig_node;
4441
4442         ixgbe_cache_ring_register(adapter);
4443
4444         return 0;
4445
4446 err_rx_ring_allocation:
4447         for (i = 0; i < adapter->num_tx_queues; i++)
4448                 kfree(adapter->tx_ring[i]);
4449 err_tx_ring_allocation:
4450         return -ENOMEM;
4451 }
4452
4453 /**
4454  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4455  * @adapter: board private structure to initialize
4456  *
4457  * Attempt to configure the interrupts using the best available
4458  * capabilities of the hardware and the kernel.
4459  **/
4460 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4461 {
4462         struct ixgbe_hw *hw = &adapter->hw;
4463         int err = 0;
4464         int vector, v_budget;
4465
4466         /*
4467          * It's easy to be greedy for MSI-X vectors, but it really
4468          * doesn't do us much good if we have a lot more vectors
4469          * than CPU's.  So let's be conservative and only ask for
4470          * (roughly) the same number of vectors as there are CPU's.
4471          */
4472         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4473                        (int)num_online_cpus()) + NON_Q_VECTORS;
4474
4475         /*
4476          * At the same time, hardware can only support a maximum of
4477          * hw.mac->max_msix_vectors vectors.  With features
4478          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4479          * descriptor queues supported by our device.  Thus, we cap it off in
4480          * those rare cases where the cpu count also exceeds our vector limit.
4481          */
4482         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4483
4484         /* A failure in MSI-X entry allocation isn't fatal, but it does
4485          * mean we disable MSI-X capabilities of the adapter. */
4486         adapter->msix_entries = kcalloc(v_budget,
4487                                         sizeof(struct msix_entry), GFP_KERNEL);
4488         if (adapter->msix_entries) {
4489                 for (vector = 0; vector < v_budget; vector++)
4490                         adapter->msix_entries[vector].entry = vector;
4491
4492                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4493
4494                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4495                         goto out;
4496         }
4497
4498         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4499         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4500         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4501         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4502         adapter->atr_sample_rate = 0;
4503         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4504                 ixgbe_disable_sriov(adapter);
4505
4506         ixgbe_set_num_queues(adapter);
4507
4508         err = pci_enable_msi(adapter->pdev);
4509         if (!err) {
4510                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4511         } else {
4512                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4513                              "Unable to allocate MSI interrupt, "
4514                              "falling back to legacy.  Error: %d\n", err);
4515                 /* reset err */
4516                 err = 0;
4517         }
4518
4519 out:
4520         return err;
4521 }
4522
4523 /**
4524  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4525  * @adapter: board private structure to initialize
4526  *
4527  * We allocate one q_vector per queue interrupt.  If allocation fails we
4528  * return -ENOMEM.
4529  **/
4530 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4531 {
4532         int q_idx, num_q_vectors;
4533         struct ixgbe_q_vector *q_vector;
4534         int napi_vectors;
4535         int (*poll)(struct napi_struct *, int);
4536
4537         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4538                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4539                 napi_vectors = adapter->num_rx_queues;
4540                 poll = &ixgbe_clean_rxtx_many;
4541         } else {
4542                 num_q_vectors = 1;
4543                 napi_vectors = 1;
4544                 poll = &ixgbe_poll;
4545         }
4546
4547         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4548                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4549                                         GFP_KERNEL, adapter->node);
4550                 if (!q_vector)
4551                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4552                                            GFP_KERNEL);
4553                 if (!q_vector)
4554                         goto err_out;
4555                 q_vector->adapter = adapter;
4556                 if (q_vector->txr_count && !q_vector->rxr_count)
4557                         q_vector->eitr = adapter->tx_eitr_param;
4558                 else
4559                         q_vector->eitr = adapter->rx_eitr_param;
4560                 q_vector->v_idx = q_idx;
4561                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4562                 adapter->q_vector[q_idx] = q_vector;
4563         }
4564
4565         return 0;
4566
4567 err_out:
4568         while (q_idx) {
4569                 q_idx--;
4570                 q_vector = adapter->q_vector[q_idx];
4571                 netif_napi_del(&q_vector->napi);
4572                 kfree(q_vector);
4573                 adapter->q_vector[q_idx] = NULL;
4574         }
4575         return -ENOMEM;
4576 }
4577
4578 /**
4579  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4580  * @adapter: board private structure to initialize
4581  *
4582  * This function frees the memory allocated to the q_vectors.  In addition if
4583  * NAPI is enabled it will delete any references to the NAPI struct prior
4584  * to freeing the q_vector.
4585  **/
4586 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4587 {
4588         int q_idx, num_q_vectors;
4589
4590         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4591                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4592         else
4593                 num_q_vectors = 1;
4594
4595         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4596                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4597                 adapter->q_vector[q_idx] = NULL;
4598                 netif_napi_del(&q_vector->napi);
4599                 kfree(q_vector);
4600         }
4601 }
4602
4603 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4604 {
4605         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4606                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4607                 pci_disable_msix(adapter->pdev);
4608                 kfree(adapter->msix_entries);
4609                 adapter->msix_entries = NULL;
4610         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4611                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4612                 pci_disable_msi(adapter->pdev);
4613         }
4614 }
4615
4616 /**
4617  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4618  * @adapter: board private structure to initialize
4619  *
4620  * We determine which interrupt scheme to use based on...
4621  * - Kernel support (MSI, MSI-X)
4622  *   - which can be user-defined (via MODULE_PARAM)
4623  * - Hardware queue count (num_*_queues)
4624  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4625  **/
4626 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4627 {
4628         int err;
4629
4630         /* Number of supported queues */
4631         ixgbe_set_num_queues(adapter);
4632
4633         err = ixgbe_set_interrupt_capability(adapter);
4634         if (err) {
4635                 e_dev_err("Unable to setup interrupt capabilities\n");
4636                 goto err_set_interrupt;
4637         }
4638
4639         err = ixgbe_alloc_q_vectors(adapter);
4640         if (err) {
4641                 e_dev_err("Unable to allocate memory for queue vectors\n");
4642                 goto err_alloc_q_vectors;
4643         }
4644
4645         err = ixgbe_alloc_queues(adapter);
4646         if (err) {
4647                 e_dev_err("Unable to allocate memory for queues\n");
4648                 goto err_alloc_queues;
4649         }
4650
4651         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4652                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4653                    adapter->num_rx_queues, adapter->num_tx_queues);
4654
4655         set_bit(__IXGBE_DOWN, &adapter->state);
4656
4657         return 0;
4658
4659 err_alloc_queues:
4660         ixgbe_free_q_vectors(adapter);
4661 err_alloc_q_vectors:
4662         ixgbe_reset_interrupt_capability(adapter);
4663 err_set_interrupt:
4664         return err;
4665 }
4666
4667 /**
4668  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4669  * @adapter: board private structure to clear interrupt scheme on
4670  *
4671  * We go through and clear interrupt specific resources and reset the structure
4672  * to pre-load conditions
4673  **/
4674 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4675 {
4676         int i;
4677
4678         for (i = 0; i < adapter->num_tx_queues; i++) {
4679                 kfree(adapter->tx_ring[i]);
4680                 adapter->tx_ring[i] = NULL;
4681         }
4682         for (i = 0; i < adapter->num_rx_queues; i++) {
4683                 kfree(adapter->rx_ring[i]);
4684                 adapter->rx_ring[i] = NULL;
4685         }
4686
4687         ixgbe_free_q_vectors(adapter);
4688         ixgbe_reset_interrupt_capability(adapter);
4689 }
4690
4691 /**
4692  * ixgbe_sfp_timer - worker thread to find a missing module
4693  * @data: pointer to our adapter struct
4694  **/
4695 static void ixgbe_sfp_timer(unsigned long data)
4696 {
4697         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4698
4699         /*
4700          * Do the sfp_timer outside of interrupt context due to the
4701          * delays that sfp+ detection requires
4702          */
4703         schedule_work(&adapter->sfp_task);
4704 }
4705
4706 /**
4707  * ixgbe_sfp_task - worker thread to find a missing module
4708  * @work: pointer to work_struct containing our data
4709  **/
4710 static void ixgbe_sfp_task(struct work_struct *work)
4711 {
4712         struct ixgbe_adapter *adapter = container_of(work,
4713                                                      struct ixgbe_adapter,
4714                                                      sfp_task);
4715         struct ixgbe_hw *hw = &adapter->hw;
4716
4717         if ((hw->phy.type == ixgbe_phy_nl) &&
4718             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4719                 s32 ret = hw->phy.ops.identify_sfp(hw);
4720                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4721                         goto reschedule;
4722                 ret = hw->phy.ops.reset(hw);
4723                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4724                         e_dev_err("failed to initialize because an unsupported "
4725                                   "SFP+ module type was detected.\n");
4726                         e_dev_err("Reload the driver after installing a "
4727                                   "supported module.\n");
4728                         unregister_netdev(adapter->netdev);
4729                 } else {
4730                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4731                 }
4732                 /* don't need this routine any more */
4733                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4734         }
4735         return;
4736 reschedule:
4737         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4738                 mod_timer(&adapter->sfp_timer,
4739                           round_jiffies(jiffies + (2 * HZ)));
4740 }
4741
4742 /**
4743  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4744  * @adapter: board private structure to initialize
4745  *
4746  * ixgbe_sw_init initializes the Adapter private data structure.
4747  * Fields are initialized based on PCI device information and
4748  * OS network device settings (MTU size).
4749  **/
4750 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4751 {
4752         struct ixgbe_hw *hw = &adapter->hw;
4753         struct pci_dev *pdev = adapter->pdev;
4754         struct net_device *dev = adapter->netdev;
4755         unsigned int rss;
4756 #ifdef CONFIG_IXGBE_DCB
4757         int j;
4758         struct tc_configuration *tc;
4759 #endif
4760
4761         /* PCI config space info */
4762
4763         hw->vendor_id = pdev->vendor;
4764         hw->device_id = pdev->device;
4765         hw->revision_id = pdev->revision;
4766         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4767         hw->subsystem_device_id = pdev->subsystem_device;
4768
4769         /* Set capability flags */
4770         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4771         adapter->ring_feature[RING_F_RSS].indices = rss;
4772         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4773         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4774         if (hw->mac.type == ixgbe_mac_82598EB) {
4775                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4776                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4777                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4778         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4779                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4780                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4781                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4782                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4783                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4784                 if (dev->features & NETIF_F_NTUPLE) {
4785                         /* Flow Director perfect filter enabled */
4786                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4787                         adapter->atr_sample_rate = 0;
4788                         spin_lock_init(&adapter->fdir_perfect_lock);
4789                 } else {
4790                         /* Flow Director hash filters enabled */
4791                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4792                         adapter->atr_sample_rate = 20;
4793                 }
4794                 adapter->ring_feature[RING_F_FDIR].indices =
4795                                                          IXGBE_MAX_FDIR_INDICES;
4796                 adapter->fdir_pballoc = 0;
4797 #ifdef IXGBE_FCOE
4798                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4799                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4800                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4801 #ifdef CONFIG_IXGBE_DCB
4802                 /* Default traffic class to use for FCoE */
4803                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4804                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4805 #endif
4806 #endif /* IXGBE_FCOE */
4807         }
4808
4809 #ifdef CONFIG_IXGBE_DCB
4810         /* Configure DCB traffic classes */
4811         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4812                 tc = &adapter->dcb_cfg.tc_config[j];
4813                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4814                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4815                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4816                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4817                 tc->dcb_pfc = pfc_disabled;
4818         }
4819         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4820         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4821         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4822         adapter->dcb_cfg.pfc_mode_enable = false;
4823         adapter->dcb_cfg.round_robin_enable = false;
4824         adapter->dcb_set_bitmap = 0x00;
4825         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4826                            adapter->ring_feature[RING_F_DCB].indices);
4827
4828 #endif
4829
4830         /* default flow control settings */
4831         hw->fc.requested_mode = ixgbe_fc_full;
4832         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4833 #ifdef CONFIG_DCB
4834         adapter->last_lfc_mode = hw->fc.current_mode;
4835 #endif
4836         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4837         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4838         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4839         hw->fc.send_xon = true;
4840         hw->fc.disable_fc_autoneg = false;
4841
4842         /* enable itr by default in dynamic mode */
4843         adapter->rx_itr_setting = 1;
4844         adapter->rx_eitr_param = 20000;
4845         adapter->tx_itr_setting = 1;
4846         adapter->tx_eitr_param = 10000;
4847
4848         /* set defaults for eitr in MegaBytes */
4849         adapter->eitr_low = 10;
4850         adapter->eitr_high = 20;
4851
4852         /* set default ring sizes */
4853         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4854         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4855
4856         /* initialize eeprom parameters */
4857         if (ixgbe_init_eeprom_params_generic(hw)) {
4858                 e_dev_err("EEPROM initialization failed\n");
4859                 return -EIO;
4860         }
4861
4862         /* enable rx csum by default */
4863         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4864
4865         /* get assigned NUMA node */
4866         adapter->node = dev_to_node(&pdev->dev);
4867
4868         set_bit(__IXGBE_DOWN, &adapter->state);
4869
4870         return 0;
4871 }
4872
4873 /**
4874  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4875  * @adapter: board private structure
4876  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4877  *
4878  * Return 0 on success, negative on failure
4879  **/
4880 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4881                              struct ixgbe_ring *tx_ring)
4882 {
4883         struct pci_dev *pdev = adapter->pdev;
4884         int size;
4885
4886         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4887         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4888         if (!tx_ring->tx_buffer_info)
4889                 tx_ring->tx_buffer_info = vmalloc(size);
4890         if (!tx_ring->tx_buffer_info)
4891                 goto err;
4892         memset(tx_ring->tx_buffer_info, 0, size);
4893
4894         /* round up to nearest 4K */
4895         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4896         tx_ring->size = ALIGN(tx_ring->size, 4096);
4897
4898         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4899                                            &tx_ring->dma, GFP_KERNEL);
4900         if (!tx_ring->desc)
4901                 goto err;
4902
4903         tx_ring->next_to_use = 0;
4904         tx_ring->next_to_clean = 0;
4905         tx_ring->work_limit = tx_ring->count;
4906         return 0;
4907
4908 err:
4909         vfree(tx_ring->tx_buffer_info);
4910         tx_ring->tx_buffer_info = NULL;
4911         e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4912         return -ENOMEM;
4913 }
4914
4915 /**
4916  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4917  * @adapter: board private structure
4918  *
4919  * If this function returns with an error, then it's possible one or
4920  * more of the rings is populated (while the rest are not).  It is the
4921  * callers duty to clean those orphaned rings.
4922  *
4923  * Return 0 on success, negative on failure
4924  **/
4925 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4926 {
4927         int i, err = 0;
4928
4929         for (i = 0; i < adapter->num_tx_queues; i++) {
4930                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4931                 if (!err)
4932                         continue;
4933                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4934                 break;
4935         }
4936
4937         return err;
4938 }
4939
4940 /**
4941  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4942  * @adapter: board private structure
4943  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4944  *
4945  * Returns 0 on success, negative on failure
4946  **/
4947 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4948                              struct ixgbe_ring *rx_ring)
4949 {
4950         struct pci_dev *pdev = adapter->pdev;
4951         int size;
4952
4953         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4954         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4955         if (!rx_ring->rx_buffer_info)
4956                 rx_ring->rx_buffer_info = vmalloc(size);
4957         if (!rx_ring->rx_buffer_info) {
4958                 e_err(probe, "vmalloc allocation failed for the Rx "
4959                       "descriptor ring\n");
4960                 goto alloc_failed;
4961         }
4962         memset(rx_ring->rx_buffer_info, 0, size);
4963
4964         /* Round up to nearest 4K */
4965         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4966         rx_ring->size = ALIGN(rx_ring->size, 4096);
4967
4968         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4969                                            &rx_ring->dma, GFP_KERNEL);
4970
4971         if (!rx_ring->desc) {
4972                 e_err(probe, "Memory allocation failed for the Rx "
4973                       "descriptor ring\n");
4974                 vfree(rx_ring->rx_buffer_info);
4975                 goto alloc_failed;
4976         }
4977
4978         rx_ring->next_to_clean = 0;
4979         rx_ring->next_to_use = 0;
4980
4981         return 0;
4982
4983 alloc_failed:
4984         return -ENOMEM;
4985 }
4986
4987 /**
4988  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4989  * @adapter: board private structure
4990  *
4991  * If this function returns with an error, then it's possible one or
4992  * more of the rings is populated (while the rest are not).  It is the
4993  * callers duty to clean those orphaned rings.
4994  *
4995  * Return 0 on success, negative on failure
4996  **/
4997
4998 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4999 {
5000         int i, err = 0;
5001
5002         for (i = 0; i < adapter->num_rx_queues; i++) {
5003                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
5004                 if (!err)
5005                         continue;
5006                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5007                 break;
5008         }
5009
5010         return err;
5011 }
5012
5013 /**
5014  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5015  * @adapter: board private structure
5016  * @tx_ring: Tx descriptor ring for a specific queue
5017  *
5018  * Free all transmit software resources
5019  **/
5020 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5021                              struct ixgbe_ring *tx_ring)
5022 {
5023         struct pci_dev *pdev = adapter->pdev;
5024
5025         ixgbe_clean_tx_ring(adapter, tx_ring);
5026
5027         vfree(tx_ring->tx_buffer_info);
5028         tx_ring->tx_buffer_info = NULL;
5029
5030         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5031                           tx_ring->dma);
5032
5033         tx_ring->desc = NULL;
5034 }
5035
5036 /**
5037  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5038  * @adapter: board private structure
5039  *
5040  * Free all transmit software resources
5041  **/
5042 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5043 {
5044         int i;
5045
5046         for (i = 0; i < adapter->num_tx_queues; i++)
5047                 if (adapter->tx_ring[i]->desc)
5048                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5049 }
5050
5051 /**
5052  * ixgbe_free_rx_resources - Free Rx Resources
5053  * @adapter: board private structure
5054  * @rx_ring: ring to clean the resources from
5055  *
5056  * Free all receive software resources
5057  **/
5058 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5059                              struct ixgbe_ring *rx_ring)
5060 {
5061         struct pci_dev *pdev = adapter->pdev;
5062
5063         ixgbe_clean_rx_ring(adapter, rx_ring);
5064
5065         vfree(rx_ring->rx_buffer_info);
5066         rx_ring->rx_buffer_info = NULL;
5067
5068         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5069                           rx_ring->dma);
5070
5071         rx_ring->desc = NULL;
5072 }
5073
5074 /**
5075  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5076  * @adapter: board private structure
5077  *
5078  * Free all receive software resources
5079  **/
5080 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5081 {
5082         int i;
5083
5084         for (i = 0; i < adapter->num_rx_queues; i++)
5085                 if (adapter->rx_ring[i]->desc)
5086                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5087 }
5088
5089 /**
5090  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5091  * @netdev: network interface device structure
5092  * @new_mtu: new value for maximum frame size
5093  *
5094  * Returns 0 on success, negative on failure
5095  **/
5096 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5097 {
5098         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5099         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5100
5101         /* MTU < 68 is an error and causes problems on some kernels */
5102         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5103                 return -EINVAL;
5104
5105         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5106         /* must set new MTU before calling down or up */
5107         netdev->mtu = new_mtu;
5108
5109         if (netif_running(netdev))
5110                 ixgbe_reinit_locked(adapter);
5111
5112         return 0;
5113 }
5114
5115 /**
5116  * ixgbe_open - Called when a network interface is made active
5117  * @netdev: network interface device structure
5118  *
5119  * Returns 0 on success, negative value on failure
5120  *
5121  * The open entry point is called when a network interface is made
5122  * active by the system (IFF_UP).  At this point all resources needed
5123  * for transmit and receive operations are allocated, the interrupt
5124  * handler is registered with the OS, the watchdog timer is started,
5125  * and the stack is notified that the interface is ready.
5126  **/
5127 static int ixgbe_open(struct net_device *netdev)
5128 {
5129         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5130         int err;
5131
5132         /* disallow open during test */
5133         if (test_bit(__IXGBE_TESTING, &adapter->state))
5134                 return -EBUSY;
5135
5136         netif_carrier_off(netdev);
5137
5138         /* allocate transmit descriptors */
5139         err = ixgbe_setup_all_tx_resources(adapter);
5140         if (err)
5141                 goto err_setup_tx;
5142
5143         /* allocate receive descriptors */
5144         err = ixgbe_setup_all_rx_resources(adapter);
5145         if (err)
5146                 goto err_setup_rx;
5147
5148         ixgbe_configure(adapter);
5149
5150         err = ixgbe_request_irq(adapter);
5151         if (err)
5152                 goto err_req_irq;
5153
5154         err = ixgbe_up_complete(adapter);
5155         if (err)
5156                 goto err_up;
5157
5158         netif_tx_start_all_queues(netdev);
5159
5160         return 0;
5161
5162 err_up:
5163         ixgbe_release_hw_control(adapter);
5164         ixgbe_free_irq(adapter);
5165 err_req_irq:
5166 err_setup_rx:
5167         ixgbe_free_all_rx_resources(adapter);
5168 err_setup_tx:
5169         ixgbe_free_all_tx_resources(adapter);
5170         ixgbe_reset(adapter);
5171
5172         return err;
5173 }
5174
5175 /**
5176  * ixgbe_close - Disables a network interface
5177  * @netdev: network interface device structure
5178  *
5179  * Returns 0, this is not allowed to fail
5180  *
5181  * The close entry point is called when an interface is de-activated
5182  * by the OS.  The hardware is still under the drivers control, but
5183  * needs to be disabled.  A global MAC reset is issued to stop the
5184  * hardware, and all transmit and receive resources are freed.
5185  **/
5186 static int ixgbe_close(struct net_device *netdev)
5187 {
5188         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5189
5190         ixgbe_down(adapter);
5191         ixgbe_free_irq(adapter);
5192
5193         ixgbe_free_all_tx_resources(adapter);
5194         ixgbe_free_all_rx_resources(adapter);
5195
5196         ixgbe_release_hw_control(adapter);
5197
5198         return 0;
5199 }
5200
5201 #ifdef CONFIG_PM
5202 static int ixgbe_resume(struct pci_dev *pdev)
5203 {
5204         struct net_device *netdev = pci_get_drvdata(pdev);
5205         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5206         u32 err;
5207
5208         pci_set_power_state(pdev, PCI_D0);
5209         pci_restore_state(pdev);
5210         /*
5211          * pci_restore_state clears dev->state_saved so call
5212          * pci_save_state to restore it.
5213          */
5214         pci_save_state(pdev);
5215
5216         err = pci_enable_device_mem(pdev);
5217         if (err) {
5218                 e_dev_err("Cannot enable PCI device from suspend\n");
5219                 return err;
5220         }
5221         pci_set_master(pdev);
5222
5223         pci_wake_from_d3(pdev, false);
5224
5225         err = ixgbe_init_interrupt_scheme(adapter);
5226         if (err) {
5227                 e_dev_err("Cannot initialize interrupts for device\n");
5228                 return err;
5229         }
5230
5231         ixgbe_reset(adapter);
5232
5233         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5234
5235         if (netif_running(netdev)) {
5236                 err = ixgbe_open(adapter->netdev);
5237                 if (err)
5238                         return err;
5239         }
5240
5241         netif_device_attach(netdev);
5242
5243         return 0;
5244 }
5245 #endif /* CONFIG_PM */
5246
5247 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5248 {
5249         struct net_device *netdev = pci_get_drvdata(pdev);
5250         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5251         struct ixgbe_hw *hw = &adapter->hw;
5252         u32 ctrl, fctrl;
5253         u32 wufc = adapter->wol;
5254 #ifdef CONFIG_PM
5255         int retval = 0;
5256 #endif
5257
5258         netif_device_detach(netdev);
5259
5260         if (netif_running(netdev)) {
5261                 ixgbe_down(adapter);
5262                 ixgbe_free_irq(adapter);
5263                 ixgbe_free_all_tx_resources(adapter);
5264                 ixgbe_free_all_rx_resources(adapter);
5265         }
5266
5267 #ifdef CONFIG_PM
5268         retval = pci_save_state(pdev);
5269         if (retval)
5270                 return retval;
5271
5272 #endif
5273         if (wufc) {
5274                 ixgbe_set_rx_mode(netdev);
5275
5276                 /* turn on all-multi mode if wake on multicast is enabled */
5277                 if (wufc & IXGBE_WUFC_MC) {
5278                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5279                         fctrl |= IXGBE_FCTRL_MPE;
5280                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5281                 }
5282
5283                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5284                 ctrl |= IXGBE_CTRL_GIO_DIS;
5285                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5286
5287                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5288         } else {
5289                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5290                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5291         }
5292
5293         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5294                 pci_wake_from_d3(pdev, true);
5295         else
5296                 pci_wake_from_d3(pdev, false);
5297
5298         *enable_wake = !!wufc;
5299
5300         ixgbe_clear_interrupt_scheme(adapter);
5301
5302         ixgbe_release_hw_control(adapter);
5303
5304         pci_disable_device(pdev);
5305
5306         return 0;
5307 }
5308
5309 #ifdef CONFIG_PM
5310 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5311 {
5312         int retval;
5313         bool wake;
5314
5315         retval = __ixgbe_shutdown(pdev, &wake);
5316         if (retval)
5317                 return retval;
5318
5319         if (wake) {
5320                 pci_prepare_to_sleep(pdev);
5321         } else {
5322                 pci_wake_from_d3(pdev, false);
5323                 pci_set_power_state(pdev, PCI_D3hot);
5324         }
5325
5326         return 0;
5327 }
5328 #endif /* CONFIG_PM */
5329
5330 static void ixgbe_shutdown(struct pci_dev *pdev)
5331 {
5332         bool wake;
5333
5334         __ixgbe_shutdown(pdev, &wake);
5335
5336         if (system_state == SYSTEM_POWER_OFF) {
5337                 pci_wake_from_d3(pdev, wake);
5338                 pci_set_power_state(pdev, PCI_D3hot);
5339         }
5340 }
5341
5342 /**
5343  * ixgbe_update_stats - Update the board statistics counters.
5344  * @adapter: board private structure
5345  **/
5346 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5347 {
5348         struct net_device *netdev = adapter->netdev;
5349         struct ixgbe_hw *hw = &adapter->hw;
5350         u64 total_mpc = 0;
5351         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5352         u64 non_eop_descs = 0, restart_queue = 0;
5353
5354         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5355             test_bit(__IXGBE_RESETTING, &adapter->state))
5356                 return;
5357
5358         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5359                 u64 rsc_count = 0;
5360                 u64 rsc_flush = 0;
5361                 for (i = 0; i < 16; i++)
5362                         adapter->hw_rx_no_dma_resources +=
5363                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5364                 for (i = 0; i < adapter->num_rx_queues; i++) {
5365                         rsc_count += adapter->rx_ring[i]->rsc_count;
5366                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5367                 }
5368                 adapter->rsc_total_count = rsc_count;
5369                 adapter->rsc_total_flush = rsc_flush;
5370         }
5371
5372         /* gather some stats to the adapter struct that are per queue */
5373         for (i = 0; i < adapter->num_tx_queues; i++)
5374                 restart_queue += adapter->tx_ring[i]->restart_queue;
5375         adapter->restart_queue = restart_queue;
5376
5377         for (i = 0; i < adapter->num_rx_queues; i++)
5378                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5379         adapter->non_eop_descs = non_eop_descs;
5380
5381         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5382         for (i = 0; i < 8; i++) {
5383                 /* for packet buffers not used, the register should read 0 */
5384                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5385                 missed_rx += mpc;
5386                 adapter->stats.mpc[i] += mpc;
5387                 total_mpc += adapter->stats.mpc[i];
5388                 if (hw->mac.type == ixgbe_mac_82598EB)
5389                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5390                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5391                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5392                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5393                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5394                 if (hw->mac.type == ixgbe_mac_82599EB) {
5395                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5396                                                             IXGBE_PXONRXCNT(i));
5397                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5398                                                            IXGBE_PXOFFRXCNT(i));
5399                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5400                 } else {
5401                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5402                                                               IXGBE_PXONRXC(i));
5403                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5404                                                              IXGBE_PXOFFRXC(i));
5405                 }
5406                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5407                                                             IXGBE_PXONTXC(i));
5408                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5409                                                              IXGBE_PXOFFTXC(i));
5410         }
5411         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5412         /* work around hardware counting issue */
5413         adapter->stats.gprc -= missed_rx;
5414
5415         /* 82598 hardware only has a 32 bit counter in the high register */
5416         if (hw->mac.type == ixgbe_mac_82599EB) {
5417                 u64 tmp;
5418                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5419                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5420                 adapter->stats.gorc += (tmp << 32);
5421                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5422                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5423                 adapter->stats.gotc += (tmp << 32);
5424                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5425                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5426                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5427                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5428                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5429                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5430 #ifdef IXGBE_FCOE
5431                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5432                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5433                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5434                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5435                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5436                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5437 #endif /* IXGBE_FCOE */
5438         } else {
5439                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5440                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5441                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5442                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5443                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5444         }
5445         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5446         adapter->stats.bprc += bprc;
5447         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5448         if (hw->mac.type == ixgbe_mac_82598EB)
5449                 adapter->stats.mprc -= bprc;
5450         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5451         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5452         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5453         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5454         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5455         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5456         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5457         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5458         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5459         adapter->stats.lxontxc += lxon;
5460         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5461         adapter->stats.lxofftxc += lxoff;
5462         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5463         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5464         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5465         /*
5466          * 82598 errata - tx of flow control packets is included in tx counters
5467          */
5468         xon_off_tot = lxon + lxoff;
5469         adapter->stats.gptc -= xon_off_tot;
5470         adapter->stats.mptc -= xon_off_tot;
5471         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5472         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5473         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5474         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5475         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5476         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5477         adapter->stats.ptc64 -= xon_off_tot;
5478         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5479         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5480         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5481         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5482         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5483         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5484
5485         /* Fill out the OS statistics structure */
5486         netdev->stats.multicast = adapter->stats.mprc;
5487
5488         /* Rx Errors */
5489         netdev->stats.rx_errors = adapter->stats.crcerrs +
5490                                        adapter->stats.rlec;
5491         netdev->stats.rx_dropped = 0;
5492         netdev->stats.rx_length_errors = adapter->stats.rlec;
5493         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5494         netdev->stats.rx_missed_errors = total_mpc;
5495 }
5496
5497 /**
5498  * ixgbe_watchdog - Timer Call-back
5499  * @data: pointer to adapter cast into an unsigned long
5500  **/
5501 static void ixgbe_watchdog(unsigned long data)
5502 {
5503         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5504         struct ixgbe_hw *hw = &adapter->hw;
5505         u64 eics = 0;
5506         int i;
5507
5508         /*
5509          *  Do the watchdog outside of interrupt context due to the lovely
5510          * delays that some of the newer hardware requires
5511          */
5512
5513         if (test_bit(__IXGBE_DOWN, &adapter->state))
5514                 goto watchdog_short_circuit;
5515
5516         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5517                 /*
5518                  * for legacy and MSI interrupts don't set any bits
5519                  * that are enabled for EIAM, because this operation
5520                  * would set *both* EIMS and EICS for any bit in EIAM
5521                  */
5522                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5523                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5524                 goto watchdog_reschedule;
5525         }
5526
5527         /* get one bit for every active tx/rx interrupt vector */
5528         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5529                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5530                 if (qv->rxr_count || qv->txr_count)
5531                         eics |= ((u64)1 << i);
5532         }
5533
5534         /* Cause software interrupt to ensure rx rings are cleaned */
5535         ixgbe_irq_rearm_queues(adapter, eics);
5536
5537 watchdog_reschedule:
5538         /* Reset the timer */
5539         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5540
5541 watchdog_short_circuit:
5542         schedule_work(&adapter->watchdog_task);
5543 }
5544
5545 /**
5546  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5547  * @work: pointer to work_struct containing our data
5548  **/
5549 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5550 {
5551         struct ixgbe_adapter *adapter = container_of(work,
5552                                                      struct ixgbe_adapter,
5553                                                      multispeed_fiber_task);
5554         struct ixgbe_hw *hw = &adapter->hw;
5555         u32 autoneg;
5556         bool negotiation;
5557
5558         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5559         autoneg = hw->phy.autoneg_advertised;
5560         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5561                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5562         hw->mac.autotry_restart = false;
5563         if (hw->mac.ops.setup_link)
5564                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5565         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5566         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5567 }
5568
5569 /**
5570  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5571  * @work: pointer to work_struct containing our data
5572  **/
5573 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5574 {
5575         struct ixgbe_adapter *adapter = container_of(work,
5576                                                      struct ixgbe_adapter,
5577                                                      sfp_config_module_task);
5578         struct ixgbe_hw *hw = &adapter->hw;
5579         u32 err;
5580
5581         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5582
5583         /* Time for electrical oscillations to settle down */
5584         msleep(100);
5585         err = hw->phy.ops.identify_sfp(hw);
5586
5587         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5588                 e_dev_err("failed to initialize because an unsupported SFP+ "
5589                           "module type was detected.\n");
5590                 e_dev_err("Reload the driver after installing a supported "
5591                           "module.\n");
5592                 unregister_netdev(adapter->netdev);
5593                 return;
5594         }
5595         hw->mac.ops.setup_sfp(hw);
5596
5597         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5598                 /* This will also work for DA Twinax connections */
5599                 schedule_work(&adapter->multispeed_fiber_task);
5600         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5601 }
5602
5603 /**
5604  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5605  * @work: pointer to work_struct containing our data
5606  **/
5607 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5608 {
5609         struct ixgbe_adapter *adapter = container_of(work,
5610                                                      struct ixgbe_adapter,
5611                                                      fdir_reinit_task);
5612         struct ixgbe_hw *hw = &adapter->hw;
5613         int i;
5614
5615         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5616                 for (i = 0; i < adapter->num_tx_queues; i++)
5617                         set_bit(__IXGBE_FDIR_INIT_DONE,
5618                                 &(adapter->tx_ring[i]->reinit_state));
5619         } else {
5620                 e_err(probe, "failed to finish FDIR re-initialization, "
5621                       "ignored adding FDIR ATR filters\n");
5622         }
5623         /* Done FDIR Re-initialization, enable transmits */
5624         netif_tx_start_all_queues(adapter->netdev);
5625 }
5626
5627 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5628
5629 /**
5630  * ixgbe_watchdog_task - worker thread to bring link up
5631  * @work: pointer to work_struct containing our data
5632  **/
5633 static void ixgbe_watchdog_task(struct work_struct *work)
5634 {
5635         struct ixgbe_adapter *adapter = container_of(work,
5636                                                      struct ixgbe_adapter,
5637                                                      watchdog_task);
5638         struct net_device *netdev = adapter->netdev;
5639         struct ixgbe_hw *hw = &adapter->hw;
5640         u32 link_speed;
5641         bool link_up;
5642         int i;
5643         struct ixgbe_ring *tx_ring;
5644         int some_tx_pending = 0;
5645
5646         mutex_lock(&ixgbe_watchdog_lock);
5647
5648         link_up = adapter->link_up;
5649         link_speed = adapter->link_speed;
5650
5651         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5652                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5653                 if (link_up) {
5654 #ifdef CONFIG_DCB
5655                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5656                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5657                                         hw->mac.ops.fc_enable(hw, i);
5658                         } else {
5659                                 hw->mac.ops.fc_enable(hw, 0);
5660                         }
5661 #else
5662                         hw->mac.ops.fc_enable(hw, 0);
5663 #endif
5664                 }
5665
5666                 if (link_up ||
5667                     time_after(jiffies, (adapter->link_check_timeout +
5668                                          IXGBE_TRY_LINK_TIMEOUT))) {
5669                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5670                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5671                 }
5672                 adapter->link_up = link_up;
5673                 adapter->link_speed = link_speed;
5674         }
5675
5676         if (link_up) {
5677                 if (!netif_carrier_ok(netdev)) {
5678                         bool flow_rx, flow_tx;
5679
5680                         if (hw->mac.type == ixgbe_mac_82599EB) {
5681                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5682                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5683                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5684                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5685                         } else {
5686                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5687                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5688                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5689                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5690                         }
5691
5692                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5693                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5694                                "10 Gbps" :
5695                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5696                                "1 Gbps" : "unknown speed")),
5697                                ((flow_rx && flow_tx) ? "RX/TX" :
5698                                (flow_rx ? "RX" :
5699                                (flow_tx ? "TX" : "None"))));
5700
5701                         netif_carrier_on(netdev);
5702                 } else {
5703                         /* Force detection of hung controller */
5704                         adapter->detect_tx_hung = true;
5705                 }
5706         } else {
5707                 adapter->link_up = false;
5708                 adapter->link_speed = 0;
5709                 if (netif_carrier_ok(netdev)) {
5710                         e_info(drv, "NIC Link is Down\n");
5711                         netif_carrier_off(netdev);
5712                 }
5713         }
5714
5715         if (!netif_carrier_ok(netdev)) {
5716                 for (i = 0; i < adapter->num_tx_queues; i++) {
5717                         tx_ring = adapter->tx_ring[i];
5718                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5719                                 some_tx_pending = 1;
5720                                 break;
5721                         }
5722                 }
5723
5724                 if (some_tx_pending) {
5725                         /* We've lost link, so the controller stops DMA,
5726                          * but we've got queued Tx work that's never going
5727                          * to get done, so reset controller to flush Tx.
5728                          * (Do the reset outside of interrupt context).
5729                          */
5730                          schedule_work(&adapter->reset_task);
5731                 }
5732         }
5733
5734         ixgbe_update_stats(adapter);
5735         mutex_unlock(&ixgbe_watchdog_lock);
5736 }
5737
5738 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5739                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5740                      u32 tx_flags, u8 *hdr_len)
5741 {
5742         struct ixgbe_adv_tx_context_desc *context_desc;
5743         unsigned int i;
5744         int err;
5745         struct ixgbe_tx_buffer *tx_buffer_info;
5746         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5747         u32 mss_l4len_idx, l4len;
5748
5749         if (skb_is_gso(skb)) {
5750                 if (skb_header_cloned(skb)) {
5751                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5752                         if (err)
5753                                 return err;
5754                 }
5755                 l4len = tcp_hdrlen(skb);
5756                 *hdr_len += l4len;
5757
5758                 if (skb->protocol == htons(ETH_P_IP)) {
5759                         struct iphdr *iph = ip_hdr(skb);
5760                         iph->tot_len = 0;
5761                         iph->check = 0;
5762                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5763                                                                  iph->daddr, 0,
5764                                                                  IPPROTO_TCP,
5765                                                                  0);
5766                 } else if (skb_is_gso_v6(skb)) {
5767                         ipv6_hdr(skb)->payload_len = 0;
5768                         tcp_hdr(skb)->check =
5769                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5770                                              &ipv6_hdr(skb)->daddr,
5771                                              0, IPPROTO_TCP, 0);
5772                 }
5773
5774                 i = tx_ring->next_to_use;
5775
5776                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5777                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5778
5779                 /* VLAN MACLEN IPLEN */
5780                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5781                         vlan_macip_lens |=
5782                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5783                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5784                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5785                 *hdr_len += skb_network_offset(skb);
5786                 vlan_macip_lens |=
5787                     (skb_transport_header(skb) - skb_network_header(skb));
5788                 *hdr_len +=
5789                     (skb_transport_header(skb) - skb_network_header(skb));
5790                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5791                 context_desc->seqnum_seed = 0;
5792
5793                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5794                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5795                                    IXGBE_ADVTXD_DTYP_CTXT);
5796
5797                 if (skb->protocol == htons(ETH_P_IP))
5798                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5799                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5800                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5801
5802                 /* MSS L4LEN IDX */
5803                 mss_l4len_idx =
5804                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5805                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5806                 /* use index 1 for TSO */
5807                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5808                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5809
5810                 tx_buffer_info->time_stamp = jiffies;
5811                 tx_buffer_info->next_to_watch = i;
5812
5813                 i++;
5814                 if (i == tx_ring->count)
5815                         i = 0;
5816                 tx_ring->next_to_use = i;
5817
5818                 return true;
5819         }
5820         return false;
5821 }
5822
5823 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5824                           struct ixgbe_ring *tx_ring,
5825                           struct sk_buff *skb, u32 tx_flags)
5826 {
5827         struct ixgbe_adv_tx_context_desc *context_desc;
5828         unsigned int i;
5829         struct ixgbe_tx_buffer *tx_buffer_info;
5830         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5831
5832         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5833             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5834                 i = tx_ring->next_to_use;
5835                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5836                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5837
5838                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5839                         vlan_macip_lens |=
5840                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5841                 vlan_macip_lens |= (skb_network_offset(skb) <<
5842                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5843                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5844                         vlan_macip_lens |= (skb_transport_header(skb) -
5845                                             skb_network_header(skb));
5846
5847                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5848                 context_desc->seqnum_seed = 0;
5849
5850                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5851                                     IXGBE_ADVTXD_DTYP_CTXT);
5852
5853                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5854                         __be16 protocol;
5855
5856                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5857                                 const struct vlan_ethhdr *vhdr =
5858                                         (const struct vlan_ethhdr *)skb->data;
5859
5860                                 protocol = vhdr->h_vlan_encapsulated_proto;
5861                         } else {
5862                                 protocol = skb->protocol;
5863                         }
5864
5865                         switch (protocol) {
5866                         case cpu_to_be16(ETH_P_IP):
5867                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5868                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5869                                         type_tucmd_mlhl |=
5870                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5871                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5872                                         type_tucmd_mlhl |=
5873                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5874                                 break;
5875                         case cpu_to_be16(ETH_P_IPV6):
5876                                 /* XXX what about other V6 headers?? */
5877                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5878                                         type_tucmd_mlhl |=
5879                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5880                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5881                                         type_tucmd_mlhl |=
5882                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5883                                 break;
5884                         default:
5885                                 if (unlikely(net_ratelimit())) {
5886                                         e_warn(probe, "partial checksum "
5887                                                "but proto=%x!\n",
5888                                                skb->protocol);
5889                                 }
5890                                 break;
5891                         }
5892                 }
5893
5894                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5895                 /* use index zero for tx checksum offload */
5896                 context_desc->mss_l4len_idx = 0;
5897
5898                 tx_buffer_info->time_stamp = jiffies;
5899                 tx_buffer_info->next_to_watch = i;
5900
5901                 i++;
5902                 if (i == tx_ring->count)
5903                         i = 0;
5904                 tx_ring->next_to_use = i;
5905
5906                 return true;
5907         }
5908
5909         return false;
5910 }
5911
5912 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5913                         struct ixgbe_ring *tx_ring,
5914                         struct sk_buff *skb, u32 tx_flags,
5915                         unsigned int first)
5916 {
5917         struct pci_dev *pdev = adapter->pdev;
5918         struct ixgbe_tx_buffer *tx_buffer_info;
5919         unsigned int len;
5920         unsigned int total = skb->len;
5921         unsigned int offset = 0, size, count = 0, i;
5922         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5923         unsigned int f;
5924
5925         i = tx_ring->next_to_use;
5926
5927         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5928                 /* excluding fcoe_crc_eof for FCoE */
5929                 total -= sizeof(struct fcoe_crc_eof);
5930
5931         len = min(skb_headlen(skb), total);
5932         while (len) {
5933                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5934                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5935
5936                 tx_buffer_info->length = size;
5937                 tx_buffer_info->mapped_as_page = false;
5938                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5939                                                      skb->data + offset,
5940                                                      size, DMA_TO_DEVICE);
5941                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5942                         goto dma_error;
5943                 tx_buffer_info->time_stamp = jiffies;
5944                 tx_buffer_info->next_to_watch = i;
5945
5946                 len -= size;
5947                 total -= size;
5948                 offset += size;
5949                 count++;
5950
5951                 if (len) {
5952                         i++;
5953                         if (i == tx_ring->count)
5954                                 i = 0;
5955                 }
5956         }
5957
5958         for (f = 0; f < nr_frags; f++) {
5959                 struct skb_frag_struct *frag;
5960
5961                 frag = &skb_shinfo(skb)->frags[f];
5962                 len = min((unsigned int)frag->size, total);
5963                 offset = frag->page_offset;
5964
5965                 while (len) {
5966                         i++;
5967                         if (i == tx_ring->count)
5968                                 i = 0;
5969
5970                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5971                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5972
5973                         tx_buffer_info->length = size;
5974                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5975                                                            frag->page,
5976                                                            offset, size,
5977                                                            DMA_TO_DEVICE);
5978                         tx_buffer_info->mapped_as_page = true;
5979                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5980                                 goto dma_error;
5981                         tx_buffer_info->time_stamp = jiffies;
5982                         tx_buffer_info->next_to_watch = i;
5983
5984                         len -= size;
5985                         total -= size;
5986                         offset += size;
5987                         count++;
5988                 }
5989                 if (total == 0)
5990                         break;
5991         }
5992
5993         tx_ring->tx_buffer_info[i].skb = skb;
5994         tx_ring->tx_buffer_info[first].next_to_watch = i;
5995
5996         return count;
5997
5998 dma_error:
5999         e_dev_err("TX DMA map failed\n");
6000
6001         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6002         tx_buffer_info->dma = 0;
6003         tx_buffer_info->time_stamp = 0;
6004         tx_buffer_info->next_to_watch = 0;
6005         if (count)
6006                 count--;
6007
6008         /* clear timestamp and dma mappings for remaining portion of packet */
6009         while (count--) {
6010                 if (i==0)
6011                         i += tx_ring->count;
6012                 i--;
6013                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6014                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6015         }
6016
6017         return 0;
6018 }
6019
6020 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6021                            struct ixgbe_ring *tx_ring,
6022                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6023 {
6024         union ixgbe_adv_tx_desc *tx_desc = NULL;
6025         struct ixgbe_tx_buffer *tx_buffer_info;
6026         u32 olinfo_status = 0, cmd_type_len = 0;
6027         unsigned int i;
6028         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6029
6030         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6031
6032         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6033
6034         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6035                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6036
6037         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6038                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6039
6040                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6041                                  IXGBE_ADVTXD_POPTS_SHIFT;
6042
6043                 /* use index 1 context for tso */
6044                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6045                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6046                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6047                                          IXGBE_ADVTXD_POPTS_SHIFT;
6048
6049         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6050                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6051                                  IXGBE_ADVTXD_POPTS_SHIFT;
6052
6053         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6054                 olinfo_status |= IXGBE_ADVTXD_CC;
6055                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6056                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6057                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6058         }
6059
6060         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6061
6062         i = tx_ring->next_to_use;
6063         while (count--) {
6064                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6065                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6066                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6067                 tx_desc->read.cmd_type_len =
6068                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6069                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6070                 i++;
6071                 if (i == tx_ring->count)
6072                         i = 0;
6073         }
6074
6075         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6076
6077         /*
6078          * Force memory writes to complete before letting h/w
6079          * know there are new descriptors to fetch.  (Only
6080          * applicable for weak-ordered memory model archs,
6081          * such as IA-64).
6082          */
6083         wmb();
6084
6085         tx_ring->next_to_use = i;
6086         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6087 }
6088
6089 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6090                       int queue, u32 tx_flags)
6091 {
6092         struct ixgbe_atr_input atr_input;
6093         struct tcphdr *th;
6094         struct iphdr *iph = ip_hdr(skb);
6095         struct ethhdr *eth = (struct ethhdr *)skb->data;
6096         u16 vlan_id, src_port, dst_port, flex_bytes;
6097         u32 src_ipv4_addr, dst_ipv4_addr;
6098         u8 l4type = 0;
6099
6100         /* Right now, we support IPv4 only */
6101         if (skb->protocol != htons(ETH_P_IP))
6102                 return;
6103         /* check if we're UDP or TCP */
6104         if (iph->protocol == IPPROTO_TCP) {
6105                 th = tcp_hdr(skb);
6106                 src_port = th->source;
6107                 dst_port = th->dest;
6108                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6109                 /* l4type IPv4 type is 0, no need to assign */
6110         } else {
6111                 /* Unsupported L4 header, just bail here */
6112                 return;
6113         }
6114
6115         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6116
6117         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6118                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6119         src_ipv4_addr = iph->saddr;
6120         dst_ipv4_addr = iph->daddr;
6121         flex_bytes = eth->h_proto;
6122
6123         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6124         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6125         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6126         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6127         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6128         /* src and dst are inverted, think how the receiver sees them */
6129         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6130         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6131
6132         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6133         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6134 }
6135
6136 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6137                                  struct ixgbe_ring *tx_ring, int size)
6138 {
6139         netif_stop_subqueue(netdev, tx_ring->queue_index);
6140         /* Herbert's original patch had:
6141          *  smp_mb__after_netif_stop_queue();
6142          * but since that doesn't exist yet, just open code it. */
6143         smp_mb();
6144
6145         /* We need to check again in a case another CPU has just
6146          * made room available. */
6147         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6148                 return -EBUSY;
6149
6150         /* A reprieve! - use start_queue because it doesn't call schedule */
6151         netif_start_subqueue(netdev, tx_ring->queue_index);
6152         ++tx_ring->restart_queue;
6153         return 0;
6154 }
6155
6156 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6157                               struct ixgbe_ring *tx_ring, int size)
6158 {
6159         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6160                 return 0;
6161         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6162 }
6163
6164 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6165 {
6166         struct ixgbe_adapter *adapter = netdev_priv(dev);
6167         int txq = smp_processor_id();
6168
6169 #ifdef IXGBE_FCOE
6170         if ((skb->protocol == htons(ETH_P_FCOE)) ||
6171             (skb->protocol == htons(ETH_P_FIP))) {
6172                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6173                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6174                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6175                         return txq;
6176 #ifdef CONFIG_IXGBE_DCB
6177                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6178                         txq = adapter->fcoe.up;
6179                         return txq;
6180 #endif
6181                 }
6182         }
6183 #endif
6184
6185         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6186                 while (unlikely(txq >= dev->real_num_tx_queues))
6187                         txq -= dev->real_num_tx_queues;
6188                 return txq;
6189         }
6190
6191         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6192                 if (skb->priority == TC_PRIO_CONTROL)
6193                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6194                 else
6195                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6196                                >> 13;
6197                 return txq;
6198         }
6199
6200         return skb_tx_hash(dev, skb);
6201 }
6202
6203 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6204                                     struct net_device *netdev)
6205 {
6206         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6207         struct ixgbe_ring *tx_ring;
6208         struct netdev_queue *txq;
6209         unsigned int first;
6210         unsigned int tx_flags = 0;
6211         u8 hdr_len = 0;
6212         int tso;
6213         int count = 0;
6214         unsigned int f;
6215
6216         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6217                 tx_flags |= vlan_tx_tag_get(skb);
6218                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6219                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6220                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6221                 }
6222                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6223                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6224         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6225                    skb->priority != TC_PRIO_CONTROL) {
6226                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6227                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6228                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6229         }
6230
6231         tx_ring = adapter->tx_ring[skb->queue_mapping];
6232
6233 #ifdef IXGBE_FCOE
6234         /* for FCoE with DCB, we force the priority to what
6235          * was specified by the switch */
6236         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6237             (skb->protocol == htons(ETH_P_FCOE) ||
6238              skb->protocol == htons(ETH_P_FIP))) {
6239 #ifdef CONFIG_IXGBE_DCB
6240                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6241                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6242                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6243                         tx_flags |= ((adapter->fcoe.up << 13)
6244                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6245                 }
6246 #endif
6247                 /* flag for FCoE offloads */
6248                 if (skb->protocol == htons(ETH_P_FCOE))
6249                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6250         }
6251 #endif
6252
6253         /* four things can cause us to need a context descriptor */
6254         if (skb_is_gso(skb) ||
6255             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6256             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6257             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6258                 count++;
6259
6260         count += TXD_USE_COUNT(skb_headlen(skb));
6261         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6262                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6263
6264         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6265                 adapter->tx_busy++;
6266                 return NETDEV_TX_BUSY;
6267         }
6268
6269         first = tx_ring->next_to_use;
6270         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6271 #ifdef IXGBE_FCOE
6272                 /* setup tx offload for FCoE */
6273                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6274                 if (tso < 0) {
6275                         dev_kfree_skb_any(skb);
6276                         return NETDEV_TX_OK;
6277                 }
6278                 if (tso)
6279                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6280 #endif /* IXGBE_FCOE */
6281         } else {
6282                 if (skb->protocol == htons(ETH_P_IP))
6283                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6284                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6285                 if (tso < 0) {
6286                         dev_kfree_skb_any(skb);
6287                         return NETDEV_TX_OK;
6288                 }
6289
6290                 if (tso)
6291                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6292                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6293                          (skb->ip_summed == CHECKSUM_PARTIAL))
6294                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6295         }
6296
6297         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6298         if (count) {
6299                 /* add the ATR filter if ATR is on */
6300                 if (tx_ring->atr_sample_rate) {
6301                         ++tx_ring->atr_count;
6302                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6303                              test_bit(__IXGBE_FDIR_INIT_DONE,
6304                                       &tx_ring->reinit_state)) {
6305                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6306                                           tx_flags);
6307                                 tx_ring->atr_count = 0;
6308                         }
6309                 }
6310                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6311                 txq->tx_bytes += skb->len;
6312                 txq->tx_packets++;
6313                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6314                                hdr_len);
6315                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6316
6317         } else {
6318                 dev_kfree_skb_any(skb);
6319                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6320                 tx_ring->next_to_use = first;
6321         }
6322
6323         return NETDEV_TX_OK;
6324 }
6325
6326 /**
6327  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6328  * @netdev: network interface device structure
6329  * @p: pointer to an address structure
6330  *
6331  * Returns 0 on success, negative on failure
6332  **/
6333 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6334 {
6335         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6336         struct ixgbe_hw *hw = &adapter->hw;
6337         struct sockaddr *addr = p;
6338
6339         if (!is_valid_ether_addr(addr->sa_data))
6340                 return -EADDRNOTAVAIL;
6341
6342         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6343         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6344
6345         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6346                             IXGBE_RAH_AV);
6347
6348         return 0;
6349 }
6350
6351 static int
6352 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6353 {
6354         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6355         struct ixgbe_hw *hw = &adapter->hw;
6356         u16 value;
6357         int rc;
6358
6359         if (prtad != hw->phy.mdio.prtad)
6360                 return -EINVAL;
6361         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6362         if (!rc)
6363                 rc = value;
6364         return rc;
6365 }
6366
6367 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6368                             u16 addr, u16 value)
6369 {
6370         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6371         struct ixgbe_hw *hw = &adapter->hw;
6372
6373         if (prtad != hw->phy.mdio.prtad)
6374                 return -EINVAL;
6375         return hw->phy.ops.write_reg(hw, addr, devad, value);
6376 }
6377
6378 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6379 {
6380         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6381
6382         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6383 }
6384
6385 /**
6386  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6387  * netdev->dev_addrs
6388  * @netdev: network interface device structure
6389  *
6390  * Returns non-zero on failure
6391  **/
6392 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6393 {
6394         int err = 0;
6395         struct ixgbe_adapter *adapter = netdev_priv(dev);
6396         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6397
6398         if (is_valid_ether_addr(mac->san_addr)) {
6399                 rtnl_lock();
6400                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6401                 rtnl_unlock();
6402         }
6403         return err;
6404 }
6405
6406 /**
6407  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6408  * netdev->dev_addrs
6409  * @netdev: network interface device structure
6410  *
6411  * Returns non-zero on failure
6412  **/
6413 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6414 {
6415         int err = 0;
6416         struct ixgbe_adapter *adapter = netdev_priv(dev);
6417         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6418
6419         if (is_valid_ether_addr(mac->san_addr)) {
6420                 rtnl_lock();
6421                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6422                 rtnl_unlock();
6423         }
6424         return err;
6425 }
6426
6427 #ifdef CONFIG_NET_POLL_CONTROLLER
6428 /*
6429  * Polling 'interrupt' - used by things like netconsole to send skbs
6430  * without having to re-enable interrupts. It's not called while
6431  * the interrupt routine is executing.
6432  */
6433 static void ixgbe_netpoll(struct net_device *netdev)
6434 {
6435         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6436         int i;
6437
6438         /* if interface is down do nothing */
6439         if (test_bit(__IXGBE_DOWN, &adapter->state))
6440                 return;
6441
6442         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6443         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6444                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6445                 for (i = 0; i < num_q_vectors; i++) {
6446                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6447                         ixgbe_msix_clean_many(0, q_vector);
6448                 }
6449         } else {
6450                 ixgbe_intr(adapter->pdev->irq, netdev);
6451         }
6452         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6453 }
6454 #endif
6455
6456 static const struct net_device_ops ixgbe_netdev_ops = {
6457         .ndo_open               = ixgbe_open,
6458         .ndo_stop               = ixgbe_close,
6459         .ndo_start_xmit         = ixgbe_xmit_frame,
6460         .ndo_select_queue       = ixgbe_select_queue,
6461         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6462         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6463         .ndo_validate_addr      = eth_validate_addr,
6464         .ndo_set_mac_address    = ixgbe_set_mac,
6465         .ndo_change_mtu         = ixgbe_change_mtu,
6466         .ndo_tx_timeout         = ixgbe_tx_timeout,
6467         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6468         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6469         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6470         .ndo_do_ioctl           = ixgbe_ioctl,
6471         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6472         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6473         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6474         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6475 #ifdef CONFIG_NET_POLL_CONTROLLER
6476         .ndo_poll_controller    = ixgbe_netpoll,
6477 #endif
6478 #ifdef IXGBE_FCOE
6479         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6480         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6481         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6482         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6483         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6484 #endif /* IXGBE_FCOE */
6485 };
6486
6487 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6488                            const struct ixgbe_info *ii)
6489 {
6490 #ifdef CONFIG_PCI_IOV
6491         struct ixgbe_hw *hw = &adapter->hw;
6492         int err;
6493
6494         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6495                 return;
6496
6497         /* The 82599 supports up to 64 VFs per physical function
6498          * but this implementation limits allocation to 63 so that
6499          * basic networking resources are still available to the
6500          * physical function
6501          */
6502         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6503         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6504         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6505         if (err) {
6506                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6507                 goto err_novfs;
6508         }
6509         /* If call to enable VFs succeeded then allocate memory
6510          * for per VF control structures.
6511          */
6512         adapter->vfinfo =
6513                 kcalloc(adapter->num_vfs,
6514                         sizeof(struct vf_data_storage), GFP_KERNEL);
6515         if (adapter->vfinfo) {
6516                 /* Now that we're sure SR-IOV is enabled
6517                  * and memory allocated set up the mailbox parameters
6518                  */
6519                 ixgbe_init_mbx_params_pf(hw);
6520                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6521                        sizeof(hw->mbx.ops));
6522
6523                 /* Disable RSC when in SR-IOV mode */
6524                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6525                                      IXGBE_FLAG2_RSC_ENABLED);
6526                 return;
6527         }
6528
6529         /* Oh oh */
6530         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6531               "SRIOV disabled\n");
6532         pci_disable_sriov(adapter->pdev);
6533
6534 err_novfs:
6535         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6536         adapter->num_vfs = 0;
6537 #endif /* CONFIG_PCI_IOV */
6538 }
6539
6540 /**
6541  * ixgbe_probe - Device Initialization Routine
6542  * @pdev: PCI device information struct
6543  * @ent: entry in ixgbe_pci_tbl
6544  *
6545  * Returns 0 on success, negative on failure
6546  *
6547  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6548  * The OS initialization, configuring of the adapter private structure,
6549  * and a hardware reset occur.
6550  **/
6551 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6552                                  const struct pci_device_id *ent)
6553 {
6554         struct net_device *netdev;
6555         struct ixgbe_adapter *adapter = NULL;
6556         struct ixgbe_hw *hw;
6557         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6558         static int cards_found;
6559         int i, err, pci_using_dac;
6560         unsigned int indices = num_possible_cpus();
6561 #ifdef IXGBE_FCOE
6562         u16 device_caps;
6563 #endif
6564         u32 part_num, eec;
6565
6566         /* Catch broken hardware that put the wrong VF device ID in
6567          * the PCIe SR-IOV capability.
6568          */
6569         if (pdev->is_virtfn) {
6570                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6571                      pci_name(pdev), pdev->vendor, pdev->device);
6572                 return -EINVAL;
6573         }
6574
6575         err = pci_enable_device_mem(pdev);
6576         if (err)
6577                 return err;
6578
6579         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6580             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6581                 pci_using_dac = 1;
6582         } else {
6583                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6584                 if (err) {
6585                         err = dma_set_coherent_mask(&pdev->dev,
6586                                                     DMA_BIT_MASK(32));
6587                         if (err) {
6588                                 dev_err(&pdev->dev,
6589                                         "No usable DMA configuration, aborting\n");
6590                                 goto err_dma;
6591                         }
6592                 }
6593                 pci_using_dac = 0;
6594         }
6595
6596         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6597                                            IORESOURCE_MEM), ixgbe_driver_name);
6598         if (err) {
6599                 dev_err(&pdev->dev,
6600                         "pci_request_selected_regions failed 0x%x\n", err);
6601                 goto err_pci_reg;
6602         }
6603
6604         pci_enable_pcie_error_reporting(pdev);
6605
6606         pci_set_master(pdev);
6607         pci_save_state(pdev);
6608
6609         if (ii->mac == ixgbe_mac_82598EB)
6610                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6611         else
6612                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6613
6614         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6615 #ifdef IXGBE_FCOE
6616         indices += min_t(unsigned int, num_possible_cpus(),
6617                          IXGBE_MAX_FCOE_INDICES);
6618 #endif
6619         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6620         if (!netdev) {
6621                 err = -ENOMEM;
6622                 goto err_alloc_etherdev;
6623         }
6624
6625         SET_NETDEV_DEV(netdev, &pdev->dev);
6626
6627         pci_set_drvdata(pdev, netdev);
6628         adapter = netdev_priv(netdev);
6629
6630         adapter->netdev = netdev;
6631         adapter->pdev = pdev;
6632         hw = &adapter->hw;
6633         hw->back = adapter;
6634         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6635
6636         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6637                               pci_resource_len(pdev, 0));
6638         if (!hw->hw_addr) {
6639                 err = -EIO;
6640                 goto err_ioremap;
6641         }
6642
6643         for (i = 1; i <= 5; i++) {
6644                 if (pci_resource_len(pdev, i) == 0)
6645                         continue;
6646         }
6647
6648         netdev->netdev_ops = &ixgbe_netdev_ops;
6649         ixgbe_set_ethtool_ops(netdev);
6650         netdev->watchdog_timeo = 5 * HZ;
6651         strcpy(netdev->name, pci_name(pdev));
6652
6653         adapter->bd_number = cards_found;
6654
6655         /* Setup hw api */
6656         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6657         hw->mac.type  = ii->mac;
6658
6659         /* EEPROM */
6660         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6661         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6662         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6663         if (!(eec & (1 << 8)))
6664                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6665
6666         /* PHY */
6667         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6668         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6669         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6670         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6671         hw->phy.mdio.mmds = 0;
6672         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6673         hw->phy.mdio.dev = netdev;
6674         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6675         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6676
6677         /* set up this timer and work struct before calling get_invariants
6678          * which might start the timer
6679          */
6680         init_timer(&adapter->sfp_timer);
6681         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6682         adapter->sfp_timer.data = (unsigned long) adapter;
6683
6684         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6685
6686         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6687         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6688
6689         /* a new SFP+ module arrival, called from GPI SDP2 context */
6690         INIT_WORK(&adapter->sfp_config_module_task,
6691                   ixgbe_sfp_config_module_task);
6692
6693         ii->get_invariants(hw);
6694
6695         /* setup the private structure */
6696         err = ixgbe_sw_init(adapter);
6697         if (err)
6698                 goto err_sw_init;
6699
6700         /* Make it possible the adapter to be woken up via WOL */
6701         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6702                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6703
6704         /*
6705          * If there is a fan on this device and it has failed log the
6706          * failure.
6707          */
6708         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6709                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6710                 if (esdp & IXGBE_ESDP_SDP1)
6711                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6712         }
6713
6714         /* reset_hw fills in the perm_addr as well */
6715         hw->phy.reset_if_overtemp = true;
6716         err = hw->mac.ops.reset_hw(hw);
6717         hw->phy.reset_if_overtemp = false;
6718         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6719             hw->mac.type == ixgbe_mac_82598EB) {
6720                 /*
6721                  * Start a kernel thread to watch for a module to arrive.
6722                  * Only do this for 82598, since 82599 will generate
6723                  * interrupts on module arrival.
6724                  */
6725                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6726                 mod_timer(&adapter->sfp_timer,
6727                           round_jiffies(jiffies + (2 * HZ)));
6728                 err = 0;
6729         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6730                 e_dev_err("failed to initialize because an unsupported SFP+ "
6731                           "module type was detected.\n");
6732                 e_dev_err("Reload the driver after installing a supported "
6733                           "module.\n");
6734                 goto err_sw_init;
6735         } else if (err) {
6736                 e_dev_err("HW Init failed: %d\n", err);
6737                 goto err_sw_init;
6738         }
6739
6740         ixgbe_probe_vf(adapter, ii);
6741
6742         netdev->features = NETIF_F_SG |
6743                            NETIF_F_IP_CSUM |
6744                            NETIF_F_HW_VLAN_TX |
6745                            NETIF_F_HW_VLAN_RX |
6746                            NETIF_F_HW_VLAN_FILTER;
6747
6748         netdev->features |= NETIF_F_IPV6_CSUM;
6749         netdev->features |= NETIF_F_TSO;
6750         netdev->features |= NETIF_F_TSO6;
6751         netdev->features |= NETIF_F_GRO;
6752
6753         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6754                 netdev->features |= NETIF_F_SCTP_CSUM;
6755
6756         netdev->vlan_features |= NETIF_F_TSO;
6757         netdev->vlan_features |= NETIF_F_TSO6;
6758         netdev->vlan_features |= NETIF_F_IP_CSUM;
6759         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6760         netdev->vlan_features |= NETIF_F_SG;
6761
6762         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6763                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6764                                     IXGBE_FLAG_DCB_ENABLED);
6765         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6766                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6767
6768 #ifdef CONFIG_IXGBE_DCB
6769         netdev->dcbnl_ops = &dcbnl_ops;
6770 #endif
6771
6772 #ifdef IXGBE_FCOE
6773         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6774                 if (hw->mac.ops.get_device_caps) {
6775                         hw->mac.ops.get_device_caps(hw, &device_caps);
6776                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6777                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6778                 }
6779         }
6780         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6781                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6782                 netdev->vlan_features |= NETIF_F_FSO;
6783                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6784         }
6785 #endif /* IXGBE_FCOE */
6786         if (pci_using_dac)
6787                 netdev->features |= NETIF_F_HIGHDMA;
6788
6789         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6790                 netdev->features |= NETIF_F_LRO;
6791
6792         /* make sure the EEPROM is good */
6793         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6794                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6795                 err = -EIO;
6796                 goto err_eeprom;
6797         }
6798
6799         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6800         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6801
6802         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6803                 e_dev_err("invalid MAC address\n");
6804                 err = -EIO;
6805                 goto err_eeprom;
6806         }
6807
6808         /* power down the optics */
6809         if (hw->phy.multispeed_fiber)
6810                 hw->mac.ops.disable_tx_laser(hw);
6811
6812         init_timer(&adapter->watchdog_timer);
6813         adapter->watchdog_timer.function = &ixgbe_watchdog;
6814         adapter->watchdog_timer.data = (unsigned long)adapter;
6815
6816         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6817         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6818
6819         err = ixgbe_init_interrupt_scheme(adapter);
6820         if (err)
6821                 goto err_sw_init;
6822
6823         switch (pdev->device) {
6824         case IXGBE_DEV_ID_82599_KX4:
6825                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6826                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6827                 break;
6828         default:
6829                 adapter->wol = 0;
6830                 break;
6831         }
6832         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6833
6834         /* pick up the PCI bus settings for reporting later */
6835         hw->mac.ops.get_bus_info(hw);
6836
6837         /* print bus type/speed/width info */
6838         e_dev_info("(PCI Express:%s:%s) %pM\n",
6839                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6840                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6841                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6842                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6843                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6844                  "Unknown"),
6845                 netdev->dev_addr);
6846         ixgbe_read_pba_num_generic(hw, &part_num);
6847         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6848                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6849                            "PBA No: %06x-%03x\n",
6850                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6851                            (part_num >> 8), (part_num & 0xff));
6852         else
6853                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6854                            hw->mac.type, hw->phy.type,
6855                            (part_num >> 8), (part_num & 0xff));
6856
6857         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6858                 e_dev_warn("PCI-Express bandwidth available for this card is "
6859                            "not sufficient for optimal performance.\n");
6860                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6861                            "is required.\n");
6862         }
6863
6864         /* save off EEPROM version number */
6865         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6866
6867         /* reset the hardware with the new settings */
6868         err = hw->mac.ops.start_hw(hw);
6869
6870         if (err == IXGBE_ERR_EEPROM_VERSION) {
6871                 /* We are running on a pre-production device, log a warning */
6872                 e_dev_warn("This device is a pre-production adapter/LOM. "
6873                            "Please be aware there may be issues associated "
6874                            "with your hardware.  If you are experiencing "
6875                            "problems please contact your Intel or hardware "
6876                            "representative who provided you with this "
6877                            "hardware.\n");
6878         }
6879         strcpy(netdev->name, "eth%d");
6880         err = register_netdev(netdev);
6881         if (err)
6882                 goto err_register;
6883
6884         /* carrier off reporting is important to ethtool even BEFORE open */
6885         netif_carrier_off(netdev);
6886
6887         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6888             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6889                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6890
6891         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6892                 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6893 #ifdef CONFIG_IXGBE_DCA
6894         if (dca_add_requester(&pdev->dev) == 0) {
6895                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6896                 ixgbe_setup_dca(adapter);
6897         }
6898 #endif
6899         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6900                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6901                 for (i = 0; i < adapter->num_vfs; i++)
6902                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6903         }
6904
6905         /* add san mac addr to netdev */
6906         ixgbe_add_sanmac_netdev(netdev);
6907
6908         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6909         cards_found++;
6910         return 0;
6911
6912 err_register:
6913         ixgbe_release_hw_control(adapter);
6914         ixgbe_clear_interrupt_scheme(adapter);
6915 err_sw_init:
6916 err_eeprom:
6917         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6918                 ixgbe_disable_sriov(adapter);
6919         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6920         del_timer_sync(&adapter->sfp_timer);
6921         cancel_work_sync(&adapter->sfp_task);
6922         cancel_work_sync(&adapter->multispeed_fiber_task);
6923         cancel_work_sync(&adapter->sfp_config_module_task);
6924         iounmap(hw->hw_addr);
6925 err_ioremap:
6926         free_netdev(netdev);
6927 err_alloc_etherdev:
6928         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6929                                      IORESOURCE_MEM));
6930 err_pci_reg:
6931 err_dma:
6932         pci_disable_device(pdev);
6933         return err;
6934 }
6935
6936 /**
6937  * ixgbe_remove - Device Removal Routine
6938  * @pdev: PCI device information struct
6939  *
6940  * ixgbe_remove is called by the PCI subsystem to alert the driver
6941  * that it should release a PCI device.  The could be caused by a
6942  * Hot-Plug event, or because the driver is going to be removed from
6943  * memory.
6944  **/
6945 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6946 {
6947         struct net_device *netdev = pci_get_drvdata(pdev);
6948         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6949
6950         set_bit(__IXGBE_DOWN, &adapter->state);
6951         /* clear the module not found bit to make sure the worker won't
6952          * reschedule
6953          */
6954         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6955         del_timer_sync(&adapter->watchdog_timer);
6956
6957         del_timer_sync(&adapter->sfp_timer);
6958         cancel_work_sync(&adapter->watchdog_task);
6959         cancel_work_sync(&adapter->sfp_task);
6960         cancel_work_sync(&adapter->multispeed_fiber_task);
6961         cancel_work_sync(&adapter->sfp_config_module_task);
6962         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6963             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6964                 cancel_work_sync(&adapter->fdir_reinit_task);
6965         flush_scheduled_work();
6966
6967 #ifdef CONFIG_IXGBE_DCA
6968         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6969                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6970                 dca_remove_requester(&pdev->dev);
6971                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6972         }
6973
6974 #endif
6975 #ifdef IXGBE_FCOE
6976         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6977                 ixgbe_cleanup_fcoe(adapter);
6978
6979 #endif /* IXGBE_FCOE */
6980
6981         /* remove the added san mac */
6982         ixgbe_del_sanmac_netdev(netdev);
6983
6984         if (netdev->reg_state == NETREG_REGISTERED)
6985                 unregister_netdev(netdev);
6986
6987         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6988                 ixgbe_disable_sriov(adapter);
6989
6990         ixgbe_clear_interrupt_scheme(adapter);
6991
6992         ixgbe_release_hw_control(adapter);
6993
6994         iounmap(adapter->hw.hw_addr);
6995         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6996                                      IORESOURCE_MEM));
6997
6998         e_dev_info("complete\n");
6999
7000         free_netdev(netdev);
7001
7002         pci_disable_pcie_error_reporting(pdev);
7003
7004         pci_disable_device(pdev);
7005 }
7006
7007 /**
7008  * ixgbe_io_error_detected - called when PCI error is detected
7009  * @pdev: Pointer to PCI device
7010  * @state: The current pci connection state
7011  *
7012  * This function is called after a PCI bus error affecting
7013  * this device has been detected.
7014  */
7015 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7016                                                 pci_channel_state_t state)
7017 {
7018         struct net_device *netdev = pci_get_drvdata(pdev);
7019         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7020
7021         netif_device_detach(netdev);
7022
7023         if (state == pci_channel_io_perm_failure)
7024                 return PCI_ERS_RESULT_DISCONNECT;
7025
7026         if (netif_running(netdev))
7027                 ixgbe_down(adapter);
7028         pci_disable_device(pdev);
7029
7030         /* Request a slot reset. */
7031         return PCI_ERS_RESULT_NEED_RESET;
7032 }
7033
7034 /**
7035  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7036  * @pdev: Pointer to PCI device
7037  *
7038  * Restart the card from scratch, as if from a cold-boot.
7039  */
7040 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7041 {
7042         struct net_device *netdev = pci_get_drvdata(pdev);
7043         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7044         pci_ers_result_t result;
7045         int err;
7046
7047         if (pci_enable_device_mem(pdev)) {
7048                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7049                 result = PCI_ERS_RESULT_DISCONNECT;
7050         } else {
7051                 pci_set_master(pdev);
7052                 pci_restore_state(pdev);
7053                 pci_save_state(pdev);
7054
7055                 pci_wake_from_d3(pdev, false);
7056
7057                 ixgbe_reset(adapter);
7058                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7059                 result = PCI_ERS_RESULT_RECOVERED;
7060         }
7061
7062         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7063         if (err) {
7064                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7065                           "failed 0x%0x\n", err);
7066                 /* non-fatal, continue */
7067         }
7068
7069         return result;
7070 }
7071
7072 /**
7073  * ixgbe_io_resume - called when traffic can start flowing again.
7074  * @pdev: Pointer to PCI device
7075  *
7076  * This callback is called when the error recovery driver tells us that
7077  * its OK to resume normal operation.
7078  */
7079 static void ixgbe_io_resume(struct pci_dev *pdev)
7080 {
7081         struct net_device *netdev = pci_get_drvdata(pdev);
7082         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7083
7084         if (netif_running(netdev)) {
7085                 if (ixgbe_up(adapter)) {
7086                         e_info(probe, "ixgbe_up failed after reset\n");
7087                         return;
7088                 }
7089         }
7090
7091         netif_device_attach(netdev);
7092 }
7093
7094 static struct pci_error_handlers ixgbe_err_handler = {
7095         .error_detected = ixgbe_io_error_detected,
7096         .slot_reset = ixgbe_io_slot_reset,
7097         .resume = ixgbe_io_resume,
7098 };
7099
7100 static struct pci_driver ixgbe_driver = {
7101         .name     = ixgbe_driver_name,
7102         .id_table = ixgbe_pci_tbl,
7103         .probe    = ixgbe_probe,
7104         .remove   = __devexit_p(ixgbe_remove),
7105 #ifdef CONFIG_PM
7106         .suspend  = ixgbe_suspend,
7107         .resume   = ixgbe_resume,
7108 #endif
7109         .shutdown = ixgbe_shutdown,
7110         .err_handler = &ixgbe_err_handler
7111 };
7112
7113 /**
7114  * ixgbe_init_module - Driver Registration Routine
7115  *
7116  * ixgbe_init_module is the first routine called when the driver is
7117  * loaded. All it does is register with the PCI subsystem.
7118  **/
7119 static int __init ixgbe_init_module(void)
7120 {
7121         int ret;
7122         pr_info("%s - version %s\n", ixgbe_driver_string,
7123                    ixgbe_driver_version);
7124         pr_info("%s\n", ixgbe_copyright);
7125
7126 #ifdef CONFIG_IXGBE_DCA
7127         dca_register_notify(&dca_notifier);
7128 #endif
7129
7130         ret = pci_register_driver(&ixgbe_driver);
7131         return ret;
7132 }
7133
7134 module_init(ixgbe_init_module);
7135
7136 /**
7137  * ixgbe_exit_module - Driver Exit Cleanup Routine
7138  *
7139  * ixgbe_exit_module is called just before the driver is removed
7140  * from memory.
7141  **/
7142 static void __exit ixgbe_exit_module(void)
7143 {
7144 #ifdef CONFIG_IXGBE_DCA
7145         dca_unregister_notify(&dca_notifier);
7146 #endif
7147         pci_unregister_driver(&ixgbe_driver);
7148 }
7149
7150 #ifdef CONFIG_IXGBE_DCA
7151 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7152                             void *p)
7153 {
7154         int ret_val;
7155
7156         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7157                                          __ixgbe_notify_dca);
7158
7159         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7160 }
7161
7162 #endif /* CONFIG_IXGBE_DCA */
7163
7164 /**
7165  * ixgbe_get_hw_dev return device
7166  * used by hardware layer to print debugging information
7167  **/
7168 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7169 {
7170         struct ixgbe_adapter *adapter = hw->back;
7171         return adapter->netdev;
7172 }
7173
7174 module_exit(ixgbe_exit_module);
7175
7176 /* ixgbe_main.c */