drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 135                  "per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172         if (adapter->vfinfo)
 173                 kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 printk(KERN_ERR "%-15s ", rname);
 293                 for (j = 0; j < 8; j++)
 294                         printk(KERN_CONT "%08x ", regs[i*8+j]);
 295                 printk(KERN_CONT "\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 printk(KERN_INFO "Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
 328                 netdev->name,
 329                 netdev->state,
 330                 netdev->trans_start,
 331                 netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         printk(KERN_INFO " Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ] "
 348                 "leng ntw timestamp\n");
 349         for (n = 0; n < adapter->num_tx_queues; n++) {
 350                 tx_ring = adapter->tx_ring[n];
 351                 tx_buffer_info =
 352                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 353                 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
 354                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 355                            (u64)tx_buffer_info->dma,
 356                            tx_buffer_info->length,
 357                            tx_buffer_info->next_to_watch,
 358                            (u64)tx_buffer_info->time_stamp);
 359         }
 360
 361         /* Print TX Rings */
 362         if (!netif_msg_tx_done(adapter))
 363                 goto rx_ring_summary;
 364
 365         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 366
 367         /* Transmit Descriptor Formats
 368          *
 369          * Advanced Transmit Descriptor
 370          *   +--------------------------------------------------------------+
 371          * 0 |         Buffer Address [63:0]                                |
 372          *   +--------------------------------------------------------------+
 373          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 374          *   +--------------------------------------------------------------+
 375          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 376          */
 377
 378         for (n = 0; n < adapter->num_tx_queues; n++) {
 379                 tx_ring = adapter->tx_ring[n];
 380                 printk(KERN_INFO "------------------------------------\n");
 381                 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 382                 printk(KERN_INFO "------------------------------------\n");
 383                 printk(KERN_INFO "T [desc]     [address 63:0  ] "
 384                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 385                         "leng  ntw timestamp        bi->skb\n");
 386
 387                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 388                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 389                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 390                         u0 = (struct my_u0 *)tx_desc;
 391                         printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
 392                                 " %04X  %3X %016llX %p", i,
 393                                 le64_to_cpu(u0->a),
 394                                 le64_to_cpu(u0->b),
 395                                 (u64)tx_buffer_info->dma,
 396                                 tx_buffer_info->length,
 397                                 tx_buffer_info->next_to_watch,
 398                                 (u64)tx_buffer_info->time_stamp,
 399                                 tx_buffer_info->skb);
 400                         if (i == tx_ring->next_to_use &&
 401                                 i == tx_ring->next_to_clean)
 402                                 printk(KERN_CONT " NTC/U\n");
 403                         else if (i == tx_ring->next_to_use)
 404                                 printk(KERN_CONT " NTU\n");
 405                         else if (i == tx_ring->next_to_clean)
 406                                 printk(KERN_CONT " NTC\n");
 407                         else
 408                                 printk(KERN_CONT "\n");
 409
 410                         if (netif_msg_pktdata(adapter) &&
 411                                 tx_buffer_info->dma != 0)
 412                                 print_hex_dump(KERN_INFO, "",
 413                                         DUMP_PREFIX_ADDRESS, 16, 1,
 414                                         phys_to_virt(tx_buffer_info->dma),
 415                                         tx_buffer_info->length, true);
 416                 }
 417         }
 418
 419         /* Print RX Rings Summary */
 420 rx_ring_summary:
 421         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 422         printk(KERN_INFO "Queue [NTU] [NTC]\n");
 423         for (n = 0; n < adapter->num_rx_queues; n++) {
 424                 rx_ring = adapter->rx_ring[n];
 425                 printk(KERN_INFO "%5d %5X %5X\n", n,
 426                            rx_ring->next_to_use, rx_ring->next_to_clean);
 427         }
 428
 429         /* Print RX Rings */
 430         if (!netif_msg_rx_status(adapter))
 431                 goto exit;
 432
 433         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 434
 435         /* Advanced Receive Descriptor (Read) Format
 436          *    63                                           1        0
 437          *    +-----------------------------------------------------+
 438          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 439          *    +----------------------------------------------+------+
 440          *  8 |       Header Buffer Address [63:1]           |  DD  |
 441          *    +-----------------------------------------------------+
 442          *
 443          *
 444          * Advanced Receive Descriptor (Write-Back) Format
 445          *
 446          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 447          *   +------------------------------------------------------+
 448          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 449          *   | Checksum   Ident  |   |           |    | Type | Type |
 450          *   +------------------------------------------------------+
 451          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 452          *   +------------------------------------------------------+
 453          *   63       48 47    32 31            20 19               0
 454          */
 455         for (n = 0; n < adapter->num_rx_queues; n++) {
 456                 rx_ring = adapter->rx_ring[n];
 457                 printk(KERN_INFO "------------------------------------\n");
 458                 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 459                 printk(KERN_INFO "------------------------------------\n");
 460                 printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
 461                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 462                         "<-- Adv Rx Read format\n");
 463                 printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
 464                         "[vl er S cks ln] ---------------- [bi->skb] "
 465                         "<-- Adv Rx Write-Back format\n");
 466
 467                 for (i = 0; i < rx_ring->count; i++) {
 468                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 469                         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 470                         u0 = (struct my_u0 *)rx_desc;
 471                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 472                         if (staterr & IXGBE_RXD_STAT_DD) {
 473                                 /* Descriptor Done */
 474                                 printk(KERN_INFO "RWB[0x%03X]     %016llX "
 475                                         "%016llX ---------------- %p", i,
 476                                         le64_to_cpu(u0->a),
 477                                         le64_to_cpu(u0->b),
 478                                         rx_buffer_info->skb);
 479                         } else {
 480                                 printk(KERN_INFO "R  [0x%03X]     %016llX "
 481                                         "%016llX %016llX %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         (u64)rx_buffer_info->dma,
 485                                         rx_buffer_info->skb);
 486
 487                                 if (netif_msg_pktdata(adapter)) {
 488                                         print_hex_dump(KERN_INFO, "",
 489                                            DUMP_PREFIX_ADDRESS, 16, 1,
 490                                            phys_to_virt(rx_buffer_info->dma),
 491                                            rx_ring->rx_buf_len, true);
 492
 493                                         if (rx_ring->rx_buf_len
 494                                                 < IXGBE_RXBUFFER_2048)
 495                                                 print_hex_dump(KERN_INFO, "",
 496                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 497                                                   phys_to_virt(
 498                                                     rx_buffer_info->page_dma +
 499                                                     rx_buffer_info->page_offset
 500                                                   ),
 501                                                   PAGE_SIZE/2, true);
 502                                 }
 503                         }
 504
 505                         if (i == rx_ring->next_to_use)
 506                                 printk(KERN_CONT " NTU\n");
 507                         else if (i == rx_ring->next_to_clean)
 508                                 printk(KERN_CONT " NTC\n");
 509                         else
 510                                 printk(KERN_CONT "\n");
 511
 512                 }
 513         }
 514
 515 exit:
 516         return;
 517 }
 518
 519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 520 {
 521         u32 ctrl_ext;
 522
 523         /* Let firmware take over control of h/w */
 524         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 525         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 526                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 527 }
 528
 529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 530 {
 531         u32 ctrl_ext;
 532
 533         /* Let firmware know the driver has taken over */
 534         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 536                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 537 }
 538
 539 /*
 540  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 541  * @adapter: pointer to adapter struct
 542  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 543  * @queue: queue to map the corresponding interrupt to
 544  * @msix_vector: the vector to map to the corresponding queue
 545  *
 546  */
 547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 548                            u8 queue, u8 msix_vector)
 549 {
 550         u32 ivar, index;
 551         struct ixgbe_hw *hw = &adapter->hw;
 552         switch (hw->mac.type) {
 553         case ixgbe_mac_82598EB:
 554                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 555                 if (direction == -1)
 556                         direction = 0;
 557                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 558                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 559                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 560                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 561                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 562                 break;
 563         case ixgbe_mac_82599EB:
 564                 if (direction == -1) {
 565                         /* other causes */
 566                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 567                         index = ((queue & 1) * 8);
 568                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 569                         ivar &= ~(0xFF << index);
 570                         ivar |= (msix_vector << index);
 571                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 572                         break;
 573                 } else {
 574                         /* tx or rx causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((16 * (queue & 1)) + (8 * direction));
 577                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 581                         break;
 582                 }
 583         default:
 584                 break;
 585         }
 586 }
 587
 588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 589                                           u64 qmask)
 590 {
 591         u32 mask;
 592
 593         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596         } else {
 597                 mask = (qmask & 0xFFFFFFFF);
 598                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 599                 mask = (qmask >> 32);
 600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 601         }
 602 }
 603
 604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 605                                              struct ixgbe_tx_buffer
 606                                              *tx_buffer_info)
 607 {
 608         if (tx_buffer_info->dma) {
 609                 if (tx_buffer_info->mapped_as_page)
 610                         dma_unmap_page(&adapter->pdev->dev,
 611                                        tx_buffer_info->dma,
 612                                        tx_buffer_info->length,
 613                                        DMA_TO_DEVICE);
 614                 else
 615                         dma_unmap_single(&adapter->pdev->dev,
 616                                          tx_buffer_info->dma,
 617                                          tx_buffer_info->length,
 618                                          DMA_TO_DEVICE);
 619                 tx_buffer_info->dma = 0;
 620         }
 621         if (tx_buffer_info->skb) {
 622                 dev_kfree_skb_any(tx_buffer_info->skb);
 623                 tx_buffer_info->skb = NULL;
 624         }
 625         tx_buffer_info->time_stamp = 0;
 626         /* tx_buffer_info must be completely set up in the transmit path */
 627 }
 628
 629 /**
 630  * ixgbe_tx_xon_state - check the tx ring xon state
 631  * @adapter: the ixgbe adapter
 632  * @tx_ring: the corresponding tx_ring
 633  *
 634  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 635  * corresponding TC of this tx_ring when checking TFCS.
 636  *
 637  * Returns : true if in xon state (currently not paused)
 638  */
 639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 640                                       struct ixgbe_ring *tx_ring)
 641 {
 642         u32 txoff = IXGBE_TFCS_TXOFF;
 643
 644 #ifdef CONFIG_IXGBE_DCB
 645         if (adapter->dcb_cfg.pfc_mode_enable) {
 646                 int tc;
 647                 int reg_idx = tx_ring->reg_idx;
 648                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 649
 650                 switch (adapter->hw.mac.type) {
 651                 case ixgbe_mac_82598EB:
 652                         tc = reg_idx >> 2;
 653                         txoff = IXGBE_TFCS_TXOFF0;
 654                         break;
 655                 case ixgbe_mac_82599EB:
 656                         tc = 0;
 657                         txoff = IXGBE_TFCS_TXOFF;
 658                         if (dcb_i == 8) {
 659                                 /* TC0, TC1 */
 660                                 tc = reg_idx >> 5;
 661                                 if (tc == 2) /* TC2, TC3 */
 662                                         tc += (reg_idx - 64) >> 4;
 663                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 664                                         tc += 1 + ((reg_idx - 96) >> 3);
 665                         } else if (dcb_i == 4) {
 666                                 /* TC0, TC1 */
 667                                 tc = reg_idx >> 6;
 668                                 if (tc == 1) {
 669                                         tc += (reg_idx - 64) >> 5;
 670                                         if (tc == 2) /* TC2, TC3 */
 671                                                 tc += (reg_idx - 96) >> 4;
 672                                 }
 673                         }
 674                         break;
 675                 default:
 676                         tc = 0;
 677                 }
 678                 txoff <<= tc;
 679         }
 680 #endif
 681         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 682 }
 683
 684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 685                                        struct ixgbe_ring *tx_ring,
 686                                        unsigned int eop)
 687 {
 688         struct ixgbe_hw *hw = &adapter->hw;
 689
 690         /* Detect a transmit hang in hardware, this serializes the
 691          * check with the clearing of time_stamp and movement of eop */
 692         adapter->detect_tx_hung = false;
 693         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 694             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 695             ixgbe_tx_xon_state(adapter, tx_ring)) {
 696                 /* detected Tx unit hang */
 697                 union ixgbe_adv_tx_desc *tx_desc;
 698                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 699                 e_err(drv, "Detected Tx Unit Hang\n"
 700                       "  Tx Queue             <%d>\n"
 701                       "  TDH, TDT             <%x>, <%x>\n"
 702                       "  next_to_use          <%x>\n"
 703                       "  next_to_clean        <%x>\n"
 704                       "tx_buffer_info[next_to_clean]\n"
 705                       "  time_stamp           <%lx>\n"
 706                       "  jiffies              <%lx>\n",
 707                       tx_ring->queue_index,
 708                       IXGBE_READ_REG(hw, tx_ring->head),
 709                       IXGBE_READ_REG(hw, tx_ring->tail),
 710                       tx_ring->next_to_use, eop,
 711                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 712                 return true;
 713         }
 714
 715         return false;
 716 }
 717
 718 #define IXGBE_MAX_TXD_PWR       14
 719 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 720
 721 /* Tx Descriptors needed, worst case */
 722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 723                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 725         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 726
 727 static void ixgbe_tx_timeout(struct net_device *netdev);
 728
 729 /**
 730  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 731  * @q_vector: structure containing interrupt and ring information
 732  * @tx_ring: tx ring to clean
 733  **/
 734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 735                                struct ixgbe_ring *tx_ring)
 736 {
 737         struct ixgbe_adapter *adapter = q_vector->adapter;
 738         struct net_device *netdev = adapter->netdev;
 739         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 740         struct ixgbe_tx_buffer *tx_buffer_info;
 741         unsigned int i, eop, count = 0;
 742         unsigned int total_bytes = 0, total_packets = 0;
 743
 744         i = tx_ring->next_to_clean;
 745         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 746         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 747
 748         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 749                (count < tx_ring->work_limit)) {
 750                 bool cleaned = false;
 751                 rmb(); /* read buffer_info after eop_desc */
 752                 for ( ; !cleaned; count++) {
 753                         struct sk_buff *skb;
 754                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 755                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 756                         cleaned = (i == eop);
 757                         skb = tx_buffer_info->skb;
 758
 759                         if (cleaned && skb) {
 760                                 unsigned int segs, bytecount;
 761                                 unsigned int hlen = skb_headlen(skb);
 762
 763                                 /* gso_segs is currently only valid for tcp */
 764                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 765 #ifdef IXGBE_FCOE
 766                                 /* adjust for FCoE Sequence Offload */
 767                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 768                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 769                                     skb_is_gso(skb)) {
 770                                         hlen = skb_transport_offset(skb) +
 771                                                 sizeof(struct fc_frame_header) +
 772                                                 sizeof(struct fcoe_crc_eof);
 773                                         segs = DIV_ROUND_UP(skb->len - hlen,
 774                                                 skb_shinfo(skb)->gso_size);
 775                                 }
 776 #endif /* IXGBE_FCOE */
 777                                 /* multiply data chunks by size of headers */
 778                                 bytecount = ((segs - 1) * hlen) + skb->len;
 779                                 total_packets += segs;
 780                                 total_bytes += bytecount;
 781                         }
 782
 783                         ixgbe_unmap_and_free_tx_resource(adapter,
 784                                                          tx_buffer_info);
 785
 786                         tx_desc->wb.status = 0;
 787
 788                         i++;
 789                         if (i == tx_ring->count)
 790                                 i = 0;
 791                 }
 792
 793                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 794                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 795         }
 796
 797         tx_ring->next_to_clean = i;
 798
 799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 800         if (unlikely(count && netif_carrier_ok(netdev) &&
 801                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 802                 /* Make sure that anybody stopping the queue after this
 803                  * sees the new next_to_clean.
 804                  */
 805                 smp_mb();
 806                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 807                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 808                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 809                         ++tx_ring->restart_queue;
 810                 }
 811         }
 812
 813         if (adapter->detect_tx_hung) {
 814                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 815                         /* schedule immediate reset if we believe we hung */
 816                         e_info(probe, "tx hang %d detected, resetting "
 817                                "adapter\n", adapter->tx_timeout_count + 1);
 818                         ixgbe_tx_timeout(adapter->netdev);
 819                 }
 820         }
 821
 822         /* re-arm the interrupt */
 823         if (count >= tx_ring->work_limit)
 824                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 825
 826         tx_ring->total_bytes += total_bytes;
 827         tx_ring->total_packets += total_packets;
 828         tx_ring->stats.packets += total_packets;
 829         tx_ring->stats.bytes += total_bytes;
 830         return (count < tx_ring->work_limit);
 831 }
 832
 833 #ifdef CONFIG_IXGBE_DCA
 834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 835                                 struct ixgbe_ring *rx_ring)
 836 {
 837         u32 rxctrl;
 838         int cpu = get_cpu();
 839         int q = rx_ring->reg_idx;
 840
 841         if (rx_ring->cpu != cpu) {
 842                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 843                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 844                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 845                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 846                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 847                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 848                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 849                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 850                 }
 851                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 852                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 853                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 854                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 855                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 856                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 857                 rx_ring->cpu = cpu;
 858         }
 859         put_cpu();
 860 }
 861
 862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 863                                 struct ixgbe_ring *tx_ring)
 864 {
 865         u32 txctrl;
 866         int cpu = get_cpu();
 867         int q = tx_ring->reg_idx;
 868         struct ixgbe_hw *hw = &adapter->hw;
 869
 870         if (tx_ring->cpu != cpu) {
 871                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 872                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 873                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 874                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 875                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 876                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 877                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 878                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 879                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 880                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 881                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 882                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 883                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 884                 }
 885                 tx_ring->cpu = cpu;
 886         }
 887         put_cpu();
 888 }
 889
 890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 891 {
 892         int i;
 893
 894         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 895                 return;
 896
 897         /* always use CB2 mode, difference is masked in the CB driver */
 898         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 899
 900         for (i = 0; i < adapter->num_tx_queues; i++) {
 901                 adapter->tx_ring[i]->cpu = -1;
 902                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 903         }
 904         for (i = 0; i < adapter->num_rx_queues; i++) {
 905                 adapter->rx_ring[i]->cpu = -1;
 906                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 907         }
 908 }
 909
 910 static int __ixgbe_notify_dca(struct device *dev, void *data)
 911 {
 912         struct net_device *netdev = dev_get_drvdata(dev);
 913         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 914         unsigned long event = *(unsigned long *)data;
 915
 916         switch (event) {
 917         case DCA_PROVIDER_ADD:
 918                 /* if we're already enabled, don't do it again */
 919                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 920                         break;
 921                 if (dca_add_requester(dev) == 0) {
 922                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 923                         ixgbe_setup_dca(adapter);
 924                         break;
 925                 }
 926                 /* Fall Through since DCA is disabled. */
 927         case DCA_PROVIDER_REMOVE:
 928                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 929                         dca_remove_requester(dev);
 930                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 931                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 932                 }
 933                 break;
 934         }
 935
 936         return 0;
 937 }
 938
 939 #endif /* CONFIG_IXGBE_DCA */
 940 /**
 941  * ixgbe_receive_skb - Send a completed packet up the stack
 942  * @adapter: board private structure
 943  * @skb: packet to send up
 944  * @status: hardware indication of status of receive
 945  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 946  * @rx_desc: rx descriptor
 947  **/
 948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 949                               struct sk_buff *skb, u8 status,
 950                               struct ixgbe_ring *ring,
 951                               union ixgbe_adv_rx_desc *rx_desc)
 952 {
 953         struct ixgbe_adapter *adapter = q_vector->adapter;
 954         struct napi_struct *napi = &q_vector->napi;
 955         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 956         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 957
 958         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 959                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 960                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 961                 else
 962                         napi_gro_receive(napi, skb);
 963         } else {
 964                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 965                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 966                 else
 967                         netif_rx(skb);
 968         }
 969 }
 970
 971 /**
 972  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 973  * @adapter: address of board private structure
 974  * @status_err: hardware indication of status of receive
 975  * @skb: skb currently being received and modified
 976  **/
 977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 978                                      union ixgbe_adv_rx_desc *rx_desc,
 979                                      struct sk_buff *skb)
 980 {
 981         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 982
 983         skb->ip_summed = CHECKSUM_NONE;
 984
 985         /* Rx csum disabled */
 986         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 987                 return;
 988
 989         /* if IP and error */
 990         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 991             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 992                 adapter->hw_csum_rx_error++;
 993                 return;
 994         }
 995
 996         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 997                 return;
 998
 999         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002                 /*
1003                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1004                  * checksum errors.
1005                  */
1006                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008                         return;
1009
1010                 adapter->hw_csum_rx_error++;
1011                 return;
1012         }
1013
1014         /* It must be a TCP or UDP packet with a valid checksum */
1015         skb->ip_summed = CHECKSUM_UNNECESSARY;
1016 }
1017
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019                                          struct ixgbe_ring *rx_ring, u32 val)
1020 {
1021         /*
1022          * Force memory writes to complete before letting h/w
1023          * know there are new descriptors to fetch.  (Only
1024          * applicable for weak-ordered memory model archs,
1025          * such as IA-64).
1026          */
1027         wmb();
1028         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029 }
1030
1031 /**
1032  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033  * @adapter: address of board private structure
1034  **/
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036                                    struct ixgbe_ring *rx_ring,
1037                                    int cleaned_count)
1038 {
1039         struct net_device *netdev = adapter->netdev;
1040         struct pci_dev *pdev = adapter->pdev;
1041         union ixgbe_adv_rx_desc *rx_desc;
1042         struct ixgbe_rx_buffer *bi;
1043         unsigned int i;
1044         unsigned int bufsz = rx_ring->rx_buf_len;
1045
1046         i = rx_ring->next_to_use;
1047         bi = &rx_ring->rx_buffer_info[i];
1048
1049         while (cleaned_count--) {
1050                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
1052                 if (!bi->page_dma &&
1053                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1054                         if (!bi->page) {
1055                                 bi->page = netdev_alloc_page(netdev);
1056                                 if (!bi->page) {
1057                                         adapter->alloc_rx_page_failed++;
1058                                         goto no_buffers;
1059                                 }
1060                                 bi->page_offset = 0;
1061                         } else {
1062                                 /* use a half page if we're re-using */
1063                                 bi->page_offset ^= (PAGE_SIZE / 2);
1064                         }
1065
1066                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1067                                                     bi->page_offset,
1068                                                     (PAGE_SIZE / 2),
1069                                                     DMA_FROM_DEVICE);
1070                 }
1071
1072                 if (!bi->skb) {
1073                         struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074                                                                         bufsz);
1075                         bi->skb = skb;
1076
1077                         if (!skb) {
1078                                 adapter->alloc_rx_buff_failed++;
1079                                 goto no_buffers;
1080                         }
1081                         /* initialize queue mapping */
1082                         skb_record_rx_queue(skb, rx_ring->queue_index);
1083                 }
1084
1085                 if (!bi->dma) {
1086                         bi->dma = dma_map_single(&pdev->dev,
1087                                                  bi->skb->data,
1088                                                  rx_ring->rx_buf_len,
1089                                                  DMA_FROM_DEVICE);
1090                 }
1091                 /* Refresh the desc even if buffer_addrs didn't change because
1092                  * each write-back erases this info. */
1093                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096                 } else {
1097                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098                 }
1099
1100                 i++;
1101                 if (i == rx_ring->count)
1102                         i = 0;
1103                 bi = &rx_ring->rx_buffer_info[i];
1104         }
1105
1106 no_buffers:
1107         if (rx_ring->next_to_use != i) {
1108                 rx_ring->next_to_use = i;
1109                 if (i-- == 0)
1110                         i = (rx_ring->count - 1);
1111
1112                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113         }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129                 IXGBE_RXDADV_RSCCNT_MASK) >>
1130                 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135  * @skb: pointer to the last skb in the rsc queue
1136  * @count: pointer to number of packets coalesced in this context
1137  *
1138  * This function changes a queue full of hw rsc buffers into a completed
1139  * packet.  It uses the ->prev pointers to find the first packet and then
1140  * turns it into the frag list owner.
1141  **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143                                                         u64 *count)
1144 {
1145         unsigned int frag_list_size = 0;
1146
1147         while (skb->prev) {
1148                 struct sk_buff *prev = skb->prev;
1149                 frag_list_size += skb->len;
1150                 skb->prev = NULL;
1151                 skb = prev;
1152                 *count += 1;
1153         }
1154
1155         skb_shinfo(skb)->frag_list = skb->next;
1156         skb->next = NULL;
1157         skb->len += frag_list_size;
1158         skb->data_len += frag_list_size;
1159         skb->truesize += frag_list_size;
1160         return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164         dma_addr_t dma;
1165         bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171                                struct ixgbe_ring *rx_ring,
1172                                int *work_done, int work_to_do)
1173 {
1174         struct ixgbe_adapter *adapter = q_vector->adapter;
1175         struct net_device *netdev = adapter->netdev;
1176         struct pci_dev *pdev = adapter->pdev;
1177         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179         struct sk_buff *skb;
1180         unsigned int i, rsc_count = 0;
1181         u32 len, staterr;
1182         u16 hdr_info;
1183         bool cleaned = false;
1184         int cleaned_count = 0;
1185         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187         int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190         i = rx_ring->next_to_clean;
1191         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195         while (staterr & IXGBE_RXD_STAT_DD) {
1196                 u32 upper_len = 0;
1197                 if (*work_done >= work_to_do)
1198                         break;
1199                 (*work_done)++;
1200
1201                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207                         if ((len > IXGBE_RX_HDR_SIZE) ||
1208                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209                                 len = IXGBE_RX_HDR_SIZE;
1210                 } else {
1211                         len = le16_to_cpu(rx_desc->wb.upper.length);
1212                 }
1213
1214                 cleaned = true;
1215                 skb = rx_buffer_info->skb;
1216                 prefetch(skb->data);
1217                 rx_buffer_info->skb = NULL;
1218
1219                 if (rx_buffer_info->dma) {
1220                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222                                  (!(skb->prev))) {
1223                                 /*
1224                                  * When HWRSC is enabled, delay unmapping
1225                                  * of the first packet. It carries the
1226                                  * header information, HW may still
1227                                  * access the header after the writeback.
1228                                  * Only unmap it when EOP is reached
1229                                  */
1230                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232                         } else {
1233                                 dma_unmap_single(&pdev->dev,
1234                                                  rx_buffer_info->dma,
1235                                                  rx_ring->rx_buf_len,
1236                                                  DMA_FROM_DEVICE);
1237                         }
1238                         rx_buffer_info->dma = 0;
1239                         skb_put(skb, len);
1240                 }
1241
1242                 if (upper_len) {
1243                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245                         rx_buffer_info->page_dma = 0;
1246                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247                                            rx_buffer_info->page,
1248                                            rx_buffer_info->page_offset,
1249                                            upper_len);
1250
1251                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252                             (page_count(rx_buffer_info->page) != 1))
1253                                 rx_buffer_info->page = NULL;
1254                         else
1255                                 get_page(rx_buffer_info->page);
1256
1257                         skb->len += upper_len;
1258                         skb->data_len += upper_len;
1259                         skb->truesize += upper_len;
1260                 }
1261
1262                 i++;
1263                 if (i == rx_ring->count)
1264                         i = 0;
1265
1266                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267                 prefetch(next_rxd);
1268                 cleaned_count++;
1269
1270                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273                 if (rsc_count) {
1274                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275                                      IXGBE_RXDADV_NEXTP_SHIFT;
1276                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1277                 } else {
1278                         next_buffer = &rx_ring->rx_buffer_info[i];
1279                 }
1280
1281                 if (staterr & IXGBE_RXD_STAT_EOP) {
1282                         if (skb->prev)
1283                                 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286                                         dma_unmap_single(&pdev->dev,
1287                                                          IXGBE_RSC_CB(skb)->dma,
1288                                                          rx_ring->rx_buf_len,
1289                                                          DMA_FROM_DEVICE);
1290                                         IXGBE_RSC_CB(skb)->dma = 0;
1291                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1292                                 }
1293                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294                                         rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295                                 else
1296                                         rx_ring->rsc_count++;
1297                                 rx_ring->rsc_flush++;
1298                         }
1299                         rx_ring->stats.packets++;
1300                         rx_ring->stats.bytes += skb->len;
1301                 } else {
1302                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303                                 rx_buffer_info->skb = next_buffer->skb;
1304                                 rx_buffer_info->dma = next_buffer->dma;
1305                                 next_buffer->skb = skb;
1306                                 next_buffer->dma = 0;
1307                         } else {
1308                                 skb->next = next_buffer->skb;
1309                                 skb->next->prev = skb;
1310                         }
1311                         rx_ring->non_eop_descs++;
1312                         goto next_desc;
1313                 }
1314
1315                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316                         dev_kfree_skb_irq(skb);
1317                         goto next_desc;
1318                 }
1319
1320                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322                 /* probably a little skewed due to removing CRC */
1323                 total_rx_bytes += skb->len;
1324                 total_rx_packets++;
1325
1326                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331                         if (!ddp_bytes)
1332                                 goto next_desc;
1333                 }
1334 #endif /* IXGBE_FCOE */
1335                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338                 rx_desc->wb.upper.status_error = 0;
1339
1340                 /* return some buffers to hardware, one at a time is too slow */
1341                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343                         cleaned_count = 0;
1344                 }
1345
1346                 /* use prefetched values */
1347                 rx_desc = next_rxd;
1348                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351         }
1352
1353         rx_ring->next_to_clean = i;
1354         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356         if (cleaned_count)
1357                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360         /* include DDPed FCoE data */
1361         if (ddp_bytes > 0) {
1362                 unsigned int mss;
1363
1364                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365                         sizeof(struct fc_frame_header) -
1366                         sizeof(struct fcoe_crc_eof);
1367                 if (mss > 512)
1368                         mss &= ~511;
1369                 total_rx_bytes += ddp_bytes;
1370                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371         }
1372 #endif /* IXGBE_FCOE */
1373
1374         rx_ring->total_packets += total_rx_packets;
1375         rx_ring->total_bytes += total_rx_bytes;
1376         netdev->stats.rx_bytes += total_rx_bytes;
1377         netdev->stats.rx_packets += total_rx_packets;
1378
1379         return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384  * ixgbe_configure_msix - Configure MSI-X hardware
1385  * @adapter: board private structure
1386  *
1387  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388  * interrupts.
1389  **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392         struct ixgbe_q_vector *q_vector;
1393         int i, j, q_vectors, v_idx, r_idx;
1394         u32 mask;
1395
1396         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398         /*
1399          * Populate the IVAR table and set the ITR values to the
1400          * corresponding register.
1401          */
1402         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403                 q_vector = adapter->q_vector[v_idx];
1404                 /* XXX for_each_set_bit(...) */
1405                 r_idx = find_first_bit(q_vector->rxr_idx,
1406                                        adapter->num_rx_queues);
1407
1408                 for (i = 0; i < q_vector->rxr_count; i++) {
1409                         j = adapter->rx_ring[r_idx]->reg_idx;
1410                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1411                         r_idx = find_next_bit(q_vector->rxr_idx,
1412                                               adapter->num_rx_queues,
1413                                               r_idx + 1);
1414                 }
1415                 r_idx = find_first_bit(q_vector->txr_idx,
1416                                        adapter->num_tx_queues);
1417
1418                 for (i = 0; i < q_vector->txr_count; i++) {
1419                         j = adapter->tx_ring[r_idx]->reg_idx;
1420                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1421                         r_idx = find_next_bit(q_vector->txr_idx,
1422                                               adapter->num_tx_queues,
1423                                               r_idx + 1);
1424                 }
1425
1426                 if (q_vector->txr_count && !q_vector->rxr_count)
1427                         /* tx only */
1428                         q_vector->eitr = adapter->tx_eitr_param;
1429                 else if (q_vector->rxr_count)
1430                         /* rx or mixed */
1431                         q_vector->eitr = adapter->rx_eitr_param;
1432
1433                 ixgbe_write_eitr(q_vector);
1434         }
1435
1436         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438                                v_idx);
1439         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
1443         /* set up to autoclear timer, and the vectors */
1444         mask = IXGBE_EIMS_ENABLE_MASK;
1445         if (adapter->num_vfs)
1446                 mask &= ~(IXGBE_EIMS_OTHER |
1447                           IXGBE_EIMS_MAILBOX |
1448                           IXGBE_EIMS_LSC);
1449         else
1450                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1452 }
1453
1454 enum latency_range {
1455         lowest_latency = 0,
1456         low_latency = 1,
1457         bulk_latency = 2,
1458         latency_invalid = 255
1459 };
1460
1461 /**
1462  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463  * @adapter: pointer to adapter
1464  * @eitr: eitr setting (ints per sec) to give last timeslice
1465  * @itr_setting: current throttle rate in ints/second
1466  * @packets: the number of packets during this measurement interval
1467  * @bytes: the number of bytes during this measurement interval
1468  *
1469  *      Stores a new ITR value based on packets and byte
1470  *      counts during the last interrupt.  The advantage of per interrupt
1471  *      computation is faster updates and more accurate ITR for the current
1472  *      traffic pattern.  Constants in this function were computed
1473  *      based on theoretical maximum wire speed and thresholds were set based
1474  *      on testing data as well as attempting to minimize response time
1475  *      while increasing bulk throughput.
1476  *      this functionality is controlled by the InterruptThrottleRate module
1477  *      parameter (see ixgbe_param.c)
1478  **/
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480                            u32 eitr, u8 itr_setting,
1481                            int packets, int bytes)
1482 {
1483         unsigned int retval = itr_setting;
1484         u32 timepassed_us;
1485         u64 bytes_perint;
1486
1487         if (packets == 0)
1488                 goto update_itr_done;
1489
1490
1491         /* simple throttlerate management
1492          *    0-20MB/s lowest (100000 ints/s)
1493          *   20-100MB/s low   (20000 ints/s)
1494          *  100-1249MB/s bulk (8000 ints/s)
1495          */
1496         /* what was last interrupt timeslice? */
1497         timepassed_us = 1000000/eitr;
1498         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500         switch (itr_setting) {
1501         case lowest_latency:
1502                 if (bytes_perint > adapter->eitr_low)
1503                         retval = low_latency;
1504                 break;
1505         case low_latency:
1506                 if (bytes_perint > adapter->eitr_high)
1507                         retval = bulk_latency;
1508                 else if (bytes_perint <= adapter->eitr_low)
1509                         retval = lowest_latency;
1510                 break;
1511         case bulk_latency:
1512                 if (bytes_perint <= adapter->eitr_high)
1513                         retval = low_latency;
1514                 break;
1515         }
1516
1517 update_itr_done:
1518         return retval;
1519 }
1520
1521 /**
1522  * ixgbe_write_eitr - write EITR register in hardware specific way
1523  * @q_vector: structure containing interrupt and ring information
1524  *
1525  * This function is made to be called by ethtool and by the driver
1526  * when it needs to update EITR registers at runtime.  Hardware
1527  * specific quirks/differences are taken care of here.
1528  */
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1530 {
1531         struct ixgbe_adapter *adapter = q_vector->adapter;
1532         struct ixgbe_hw *hw = &adapter->hw;
1533         int v_idx = q_vector->v_idx;
1534         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
1536         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537                 /* must write high and low 16 bits to reset counter */
1538                 itr_reg |= (itr_reg << 16);
1539         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1540                 /*
1541                  * 82599 can support a value of zero, so allow it for
1542                  * max interrupt rate, but there is an errata where it can
1543                  * not be zero with RSC
1544                  */
1545                 if (itr_reg == 8 &&
1546                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547                         itr_reg = 0;
1548
1549                 /*
1550                  * set the WDIS bit to not clear the timer bits and cause an
1551                  * immediate assertion of the interrupt
1552                  */
1553                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554         }
1555         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556 }
1557
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559 {
1560         struct ixgbe_adapter *adapter = q_vector->adapter;
1561         u32 new_itr;
1562         u8 current_itr, ret_itr;
1563         int i, r_idx;
1564         struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567         for (i = 0; i < q_vector->txr_count; i++) {
1568                 tx_ring = adapter->tx_ring[r_idx];
1569                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1570                                            q_vector->tx_itr,
1571                                            tx_ring->total_packets,
1572                                            tx_ring->total_bytes);
1573                 /* if the result for this queue would decrease interrupt
1574                  * rate for this vector then use that result */
1575                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576                                     q_vector->tx_itr - 1 : ret_itr);
1577                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1578                                       r_idx + 1);
1579         }
1580
1581         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582         for (i = 0; i < q_vector->rxr_count; i++) {
1583                 rx_ring = adapter->rx_ring[r_idx];
1584                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585                                            q_vector->rx_itr,
1586                                            rx_ring->total_packets,
1587                                            rx_ring->total_bytes);
1588                 /* if the result for this queue would decrease interrupt
1589                  * rate for this vector then use that result */
1590                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591                                     q_vector->rx_itr - 1 : ret_itr);
1592                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1593                                       r_idx + 1);
1594         }
1595
1596         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1597
1598         switch (current_itr) {
1599         /* counts and packets in update_itr are dependent on these numbers */
1600         case lowest_latency:
1601                 new_itr = 100000;
1602                 break;
1603         case low_latency:
1604                 new_itr = 20000; /* aka hwitr = ~200 */
1605                 break;
1606         case bulk_latency:
1607         default:
1608                 new_itr = 8000;
1609                 break;
1610         }
1611
1612         if (new_itr != q_vector->eitr) {
1613                 /* do an exponential smoothing */
1614                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1615
1616                 /* save the algorithm value here, not the smoothed one */
1617                 q_vector->eitr = new_itr;
1618
1619                 ixgbe_write_eitr(q_vector);
1620         }
1621 }
1622
1623 /**
1624  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625  * @work: pointer to work_struct containing our data
1626  **/
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1628 {
1629         struct ixgbe_adapter *adapter = container_of(work,
1630                                                      struct ixgbe_adapter,
1631                                                      check_overtemp_task);
1632         struct ixgbe_hw *hw = &adapter->hw;
1633         u32 eicr = adapter->interrupt_event;
1634
1635         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636                 switch (hw->device_id) {
1637                 case IXGBE_DEV_ID_82599_T3_LOM: {
1638                         u32 autoneg;
1639                         bool link_up = false;
1640
1641                         if (hw->mac.ops.check_link)
1642                                 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644                         if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645                             (eicr & IXGBE_EICR_LSC))
1646                                 /* Check if this is due to overtemp */
1647                                 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648                                         break;
1649                         }
1650                         return;
1651                 default:
1652                         if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653                                 return;
1654                         break;
1655                 }
1656                 e_crit(drv, "Network adapter has been stopped because it has "
1657                        "over heated. Restart the computer. If the problem "
1658                        "persists, power off the system and replace the "
1659                        "adapter\n");
1660                 /* write to clear the interrupt */
1661                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662         }
1663 }
1664
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666 {
1667         struct ixgbe_hw *hw = &adapter->hw;
1668
1669         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670             (eicr & IXGBE_EICR_GPI_SDP1)) {
1671                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1672                 /* write to clear the interrupt */
1673                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674         }
1675 }
1676
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678 {
1679         struct ixgbe_hw *hw = &adapter->hw;
1680
1681         if (eicr & IXGBE_EICR_GPI_SDP1) {
1682                 /* Clear the interrupt */
1683                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684                 schedule_work(&adapter->multispeed_fiber_task);
1685         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686                 /* Clear the interrupt */
1687                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688                 schedule_work(&adapter->sfp_config_module_task);
1689         } else {
1690                 /* Interrupt isn't for us... */
1691                 return;
1692         }
1693 }
1694
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696 {
1697         struct ixgbe_hw *hw = &adapter->hw;
1698
1699         adapter->lsc_int++;
1700         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701         adapter->link_check_timeout = jiffies;
1702         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704                 IXGBE_WRITE_FLUSH(hw);
1705                 schedule_work(&adapter->watchdog_task);
1706         }
1707 }
1708
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         u32 eicr;
1715
1716         /*
1717          * Workaround for Silicon errata.  Use clear-by-write instead
1718          * of clear-by-read.  Reading with EICS will return the
1719          * interrupt causes without clearing, which later be done
1720          * with the write to EICR.
1721          */
1722         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1724
1725         if (eicr & IXGBE_EICR_LSC)
1726                 ixgbe_check_lsc(adapter);
1727
1728         if (eicr & IXGBE_EICR_MAILBOX)
1729                 ixgbe_msg_task(adapter);
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB)
1732                 ixgbe_check_fan_failure(adapter, eicr);
1733
1734         if (hw->mac.type == ixgbe_mac_82599EB) {
1735                 ixgbe_check_sfp_event(adapter, eicr);
1736                 adapter->interrupt_event = eicr;
1737                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739                         schedule_work(&adapter->check_overtemp_task);
1740
1741                 /* Handle Flow Director Full threshold interrupt */
1742                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743                         int i;
1744                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745                         /* Disable transmits before FDIR Re-initialization */
1746                         netif_tx_stop_all_queues(netdev);
1747                         for (i = 0; i < adapter->num_tx_queues; i++) {
1748                                 struct ixgbe_ring *tx_ring =
1749                                                             adapter->tx_ring[i];
1750                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751                                                        &tx_ring->reinit_state))
1752                                         schedule_work(&adapter->fdir_reinit_task);
1753                         }
1754                 }
1755         }
1756         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1758
1759         return IRQ_HANDLED;
1760 }
1761
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763                                            u64 qmask)
1764 {
1765         u32 mask;
1766
1767         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770         } else {
1771                 mask = (qmask & 0xFFFFFFFF);
1772                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773                 mask = (qmask >> 32);
1774                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775         }
1776         /* skip the flush */
1777 }
1778
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780                                             u64 qmask)
1781 {
1782         u32 mask;
1783
1784         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787         } else {
1788                 mask = (qmask & 0xFFFFFFFF);
1789                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790                 mask = (qmask >> 32);
1791                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792         }
1793         /* skip the flush */
1794 }
1795
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797 {
1798         struct ixgbe_q_vector *q_vector = data;
1799         struct ixgbe_adapter  *adapter = q_vector->adapter;
1800         struct ixgbe_ring     *tx_ring;
1801         int i, r_idx;
1802
1803         if (!q_vector->txr_count)
1804                 return IRQ_HANDLED;
1805
1806         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807         for (i = 0; i < q_vector->txr_count; i++) {
1808                 tx_ring = adapter->tx_ring[r_idx];
1809                 tx_ring->total_bytes = 0;
1810                 tx_ring->total_packets = 0;
1811                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1812                                       r_idx + 1);
1813         }
1814
1815         /* EIAM disabled interrupts (on this vector) for us */
1816         napi_schedule(&q_vector->napi);
1817
1818         return IRQ_HANDLED;
1819 }
1820
1821 /**
1822  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823  * @irq: unused
1824  * @data: pointer to our q_vector struct for this interrupt vector
1825  **/
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827 {
1828         struct ixgbe_q_vector *q_vector = data;
1829         struct ixgbe_adapter  *adapter = q_vector->adapter;
1830         struct ixgbe_ring  *rx_ring;
1831         int r_idx;
1832         int i;
1833
1834         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835         for (i = 0;  i < q_vector->rxr_count; i++) {
1836                 rx_ring = adapter->rx_ring[r_idx];
1837                 rx_ring->total_bytes = 0;
1838                 rx_ring->total_packets = 0;
1839                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840                                       r_idx + 1);
1841         }
1842
1843         if (!q_vector->rxr_count)
1844                 return IRQ_HANDLED;
1845
1846         /* disable interrupts on this vector only */
1847         /* EIAM disabled interrupts (on this vector) for us */
1848         napi_schedule(&q_vector->napi);
1849
1850         return IRQ_HANDLED;
1851 }
1852
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854 {
1855         struct ixgbe_q_vector *q_vector = data;
1856         struct ixgbe_adapter  *adapter = q_vector->adapter;
1857         struct ixgbe_ring  *ring;
1858         int r_idx;
1859         int i;
1860
1861         if (!q_vector->txr_count && !q_vector->rxr_count)
1862                 return IRQ_HANDLED;
1863
1864         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865         for (i = 0; i < q_vector->txr_count; i++) {
1866                 ring = adapter->tx_ring[r_idx];
1867                 ring->total_bytes = 0;
1868                 ring->total_packets = 0;
1869                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870                                       r_idx + 1);
1871         }
1872
1873         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874         for (i = 0; i < q_vector->rxr_count; i++) {
1875                 ring = adapter->rx_ring[r_idx];
1876                 ring->total_bytes = 0;
1877                 ring->total_packets = 0;
1878                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879                                       r_idx + 1);
1880         }
1881
1882         /* EIAM disabled interrupts (on this vector) for us */
1883         napi_schedule(&q_vector->napi);
1884
1885         return IRQ_HANDLED;
1886 }
1887
1888 /**
1889  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890  * @napi: napi struct with our devices info in it
1891  * @budget: amount of work driver is allowed to do this pass, in packets
1892  *
1893  * This function is optimized for cleaning one queue only on a single
1894  * q_vector!!!
1895  **/
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897 {
1898         struct ixgbe_q_vector *q_vector =
1899                                container_of(napi, struct ixgbe_q_vector, napi);
1900         struct ixgbe_adapter *adapter = q_vector->adapter;
1901         struct ixgbe_ring *rx_ring = NULL;
1902         int work_done = 0;
1903         long r_idx;
1904
1905         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906         rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909                 ixgbe_update_rx_dca(adapter, rx_ring);
1910 #endif
1911
1912         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1913
1914         /* If all Rx work done, exit the polling mode */
1915         if (work_done < budget) {
1916                 napi_complete(napi);
1917                 if (adapter->rx_itr_setting & 1)
1918                         ixgbe_set_itr_msix(q_vector);
1919                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920                         ixgbe_irq_enable_queues(adapter,
1921                                                 ((u64)1 << q_vector->v_idx));
1922         }
1923
1924         return work_done;
1925 }
1926
1927 /**
1928  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929  * @napi: napi struct with our devices info in it
1930  * @budget: amount of work driver is allowed to do this pass, in packets
1931  *
1932  * This function will clean more than one rx queue associated with a
1933  * q_vector.
1934  **/
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1936 {
1937         struct ixgbe_q_vector *q_vector =
1938                                container_of(napi, struct ixgbe_q_vector, napi);
1939         struct ixgbe_adapter *adapter = q_vector->adapter;
1940         struct ixgbe_ring *ring = NULL;
1941         int work_done = 0, i;
1942         long r_idx;
1943         bool tx_clean_complete = true;
1944
1945         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946         for (i = 0; i < q_vector->txr_count; i++) {
1947                 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950                         ixgbe_update_tx_dca(adapter, ring);
1951 #endif
1952                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954                                       r_idx + 1);
1955         }
1956
1957         /* attempt to distribute budget to each queue fairly, but don't allow
1958          * the budget to go below 1 because we'll exit polling */
1959         budget /= (q_vector->rxr_count ?: 1);
1960         budget = max(budget, 1);
1961         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962         for (i = 0; i < q_vector->rxr_count; i++) {
1963                 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966                         ixgbe_update_rx_dca(adapter, ring);
1967 #endif
1968                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970                                       r_idx + 1);
1971         }
1972
1973         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974         ring = adapter->rx_ring[r_idx];
1975         /* If all Rx work done, exit the polling mode */
1976         if (work_done < budget) {
1977                 napi_complete(napi);
1978                 if (adapter->rx_itr_setting & 1)
1979                         ixgbe_set_itr_msix(q_vector);
1980                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981                         ixgbe_irq_enable_queues(adapter,
1982                                                 ((u64)1 << q_vector->v_idx));
1983                 return 0;
1984         }
1985
1986         return work_done;
1987 }
1988
1989 /**
1990  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991  * @napi: napi struct with our devices info in it
1992  * @budget: amount of work driver is allowed to do this pass, in packets
1993  *
1994  * This function is optimized for cleaning one queue only on a single
1995  * q_vector!!!
1996  **/
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998 {
1999         struct ixgbe_q_vector *q_vector =
2000                                container_of(napi, struct ixgbe_q_vector, napi);
2001         struct ixgbe_adapter *adapter = q_vector->adapter;
2002         struct ixgbe_ring *tx_ring = NULL;
2003         int work_done = 0;
2004         long r_idx;
2005
2006         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007         tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010                 ixgbe_update_tx_dca(adapter, tx_ring);
2011 #endif
2012
2013         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014                 work_done = budget;
2015
2016         /* If all Tx work done, exit the polling mode */
2017         if (work_done < budget) {
2018                 napi_complete(napi);
2019                 if (adapter->tx_itr_setting & 1)
2020                         ixgbe_set_itr_msix(q_vector);
2021                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023         }
2024
2025         return work_done;
2026 }
2027
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2029                                      int r_idx)
2030 {
2031         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033         set_bit(r_idx, q_vector->rxr_idx);
2034         q_vector->rxr_count++;
2035 }
2036
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2038                                      int t_idx)
2039 {
2040         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042         set_bit(t_idx, q_vector->txr_idx);
2043         q_vector->txr_count++;
2044 }
2045
2046 /**
2047  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048  * @adapter: board private structure to initialize
2049  * @vectors: allotted vector count for descriptor rings
2050  *
2051  * This function maps descriptor rings to the queue-specific vectors
2052  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2053  * one vector per ring/queue, but on a constrained vector budget, we
2054  * group the rings as "efficiently" as possible.  You would add new
2055  * mapping configurations in here.
2056  **/
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2058                                       int vectors)
2059 {
2060         int v_start = 0;
2061         int rxr_idx = 0, txr_idx = 0;
2062         int rxr_remaining = adapter->num_rx_queues;
2063         int txr_remaining = adapter->num_tx_queues;
2064         int i, j;
2065         int rqpv, tqpv;
2066         int err = 0;
2067
2068         /* No mapping required if MSI-X is disabled. */
2069         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070                 goto out;
2071
2072         /*
2073          * The ideal configuration...
2074          * We have enough vectors to map one per queue.
2075          */
2076         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2079
2080                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081                         map_vector_to_txq(adapter, v_start, txr_idx);
2082
2083                 goto out;
2084         }
2085
2086         /*
2087          * If we don't have enough vectors for a 1-to-1
2088          * mapping, we'll have to group them so there are
2089          * multiple queues per vector.
2090          */
2091         /* Re-adjusting *qpv takes care of the remainder. */
2092         for (i = v_start; i < vectors; i++) {
2093                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094                 for (j = 0; j < rqpv; j++) {
2095                         map_vector_to_rxq(adapter, i, rxr_idx);
2096                         rxr_idx++;
2097                         rxr_remaining--;
2098                 }
2099         }
2100         for (i = v_start; i < vectors; i++) {
2101                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102                 for (j = 0; j < tqpv; j++) {
2103                         map_vector_to_txq(adapter, i, txr_idx);
2104                         txr_idx++;
2105                         txr_remaining--;
2106                 }
2107         }
2108
2109 out:
2110         return err;
2111 }
2112
2113 /**
2114  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115  * @adapter: board private structure
2116  *
2117  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118  * interrupts from the kernel.
2119  **/
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121 {
2122         struct net_device *netdev = adapter->netdev;
2123         irqreturn_t (*handler)(int, void *);
2124         int i, vector, q_vectors, err;
2125         int ri=0, ti=0;
2126
2127         /* Decrement for Other and TCP Timer vectors */
2128         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130         /* Map the Tx/Rx rings to the vectors we were allotted. */
2131         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132         if (err)
2133                 goto out;
2134
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137                          &ixgbe_msix_clean_many)
2138         for (vector = 0; vector < q_vectors; vector++) {
2139                 handler = SET_HANDLER(adapter->q_vector[vector]);
2140
2141                 if(handler == &ixgbe_msix_clean_rx) {
2142                         sprintf(adapter->name[vector], "%s-%s-%d",
2143                                 netdev->name, "rx", ri++);
2144                 }
2145                 else if(handler == &ixgbe_msix_clean_tx) {
2146                         sprintf(adapter->name[vector], "%s-%s-%d",
2147                                 netdev->name, "tx", ti++);
2148                 }
2149                 else
2150                         sprintf(adapter->name[vector], "%s-%s-%d",
2151                                 netdev->name, "TxRx", vector);
2152
2153                 err = request_irq(adapter->msix_entries[vector].vector,
2154                                   handler, 0, adapter->name[vector],
2155                                   adapter->q_vector[vector]);
2156                 if (err) {
2157                         e_err(probe, "request_irq failed for MSIX interrupt "
2158                               "Error: %d\n", err);
2159                         goto free_queue_irqs;
2160                 }
2161         }
2162
2163         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164         err = request_irq(adapter->msix_entries[vector].vector,
2165                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2166         if (err) {
2167                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2168                 goto free_queue_irqs;
2169         }
2170
2171         return 0;
2172
2173 free_queue_irqs:
2174         for (i = vector - 1; i >= 0; i--)
2175                 free_irq(adapter->msix_entries[--vector].vector,
2176                          adapter->q_vector[i]);
2177         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178         pci_disable_msix(adapter->pdev);
2179         kfree(adapter->msix_entries);
2180         adapter->msix_entries = NULL;
2181 out:
2182         return err;
2183 }
2184
2185 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186 {
2187         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2188         u8 current_itr;
2189         u32 new_itr = q_vector->eitr;
2190         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2192
2193         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2194                                             q_vector->tx_itr,
2195                                             tx_ring->total_packets,
2196                                             tx_ring->total_bytes);
2197         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2198                                             q_vector->rx_itr,
2199                                             rx_ring->total_packets,
2200                                             rx_ring->total_bytes);
2201
2202         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2203
2204         switch (current_itr) {
2205         /* counts and packets in update_itr are dependent on these numbers */
2206         case lowest_latency:
2207                 new_itr = 100000;
2208                 break;
2209         case low_latency:
2210                 new_itr = 20000; /* aka hwitr = ~200 */
2211                 break;
2212         case bulk_latency:
2213                 new_itr = 8000;
2214                 break;
2215         default:
2216                 break;
2217         }
2218
2219         if (new_itr != q_vector->eitr) {
2220                 /* do an exponential smoothing */
2221                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2222
2223                 /* save the algorithm value here, not the smoothed one */
2224                 q_vector->eitr = new_itr;
2225
2226                 ixgbe_write_eitr(q_vector);
2227         }
2228 }
2229
2230 /**
2231  * ixgbe_irq_enable - Enable default interrupt generation settings
2232  * @adapter: board private structure
2233  **/
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235 {
2236         u32 mask;
2237
2238         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240                 mask |= IXGBE_EIMS_GPI_SDP0;
2241         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242                 mask |= IXGBE_EIMS_GPI_SDP1;
2243         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2244                 mask |= IXGBE_EIMS_ECC;
2245                 mask |= IXGBE_EIMS_GPI_SDP1;
2246                 mask |= IXGBE_EIMS_GPI_SDP2;
2247                 if (adapter->num_vfs)
2248                         mask |= IXGBE_EIMS_MAILBOX;
2249         }
2250         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252                 mask |= IXGBE_EIMS_FLOW_DIR;
2253
2254         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2255         ixgbe_irq_enable_queues(adapter, ~0);
2256         IXGBE_WRITE_FLUSH(&adapter->hw);
2257
2258         if (adapter->num_vfs > 32) {
2259                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261         }
2262 }
2263
2264 /**
2265  * ixgbe_intr - legacy mode Interrupt Handler
2266  * @irq: interrupt number
2267  * @data: pointer to a network interface device structure
2268  **/
2269 static irqreturn_t ixgbe_intr(int irq, void *data)
2270 {
2271         struct net_device *netdev = data;
2272         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273         struct ixgbe_hw *hw = &adapter->hw;
2274         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2275         u32 eicr;
2276
2277         /*
2278          * Workaround for silicon errata.  Mask the interrupts
2279          * before the read of EICR.
2280          */
2281         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
2283         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284          * therefore no explict interrupt disable is necessary */
2285         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2286         if (!eicr) {
2287                 /* shared interrupt alert!
2288                  * make sure interrupts are enabled because the read will
2289                  * have disabled interrupts due to EIAM */
2290                 ixgbe_irq_enable(adapter);
2291                 return IRQ_NONE;        /* Not our interrupt */
2292         }
2293
2294         if (eicr & IXGBE_EICR_LSC)
2295                 ixgbe_check_lsc(adapter);
2296
2297         if (hw->mac.type == ixgbe_mac_82599EB)
2298                 ixgbe_check_sfp_event(adapter, eicr);
2299
2300         ixgbe_check_fan_failure(adapter, eicr);
2301         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303                 schedule_work(&adapter->check_overtemp_task);
2304
2305         if (napi_schedule_prep(&(q_vector->napi))) {
2306                 adapter->tx_ring[0]->total_packets = 0;
2307                 adapter->tx_ring[0]->total_bytes = 0;
2308                 adapter->rx_ring[0]->total_packets = 0;
2309                 adapter->rx_ring[0]->total_bytes = 0;
2310                 /* would disable interrupts here but EIAM disabled it */
2311                 __napi_schedule(&(q_vector->napi));
2312         }
2313
2314         return IRQ_HANDLED;
2315 }
2316
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318 {
2319         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321         for (i = 0; i < q_vectors; i++) {
2322                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2323                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325                 q_vector->rxr_count = 0;
2326                 q_vector->txr_count = 0;
2327         }
2328 }
2329
2330 /**
2331  * ixgbe_request_irq - initialize interrupts
2332  * @adapter: board private structure
2333  *
2334  * Attempts to configure interrupts using the best available
2335  * capabilities of the hardware and kernel.
2336  **/
2337 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2338 {
2339         struct net_device *netdev = adapter->netdev;
2340         int err;
2341
2342         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343                 err = ixgbe_request_msix_irqs(adapter);
2344         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2345                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2346                                   netdev->name, netdev);
2347         } else {
2348                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2349                                   netdev->name, netdev);
2350         }
2351
2352         if (err)
2353                 e_err(probe, "request_irq failed, Error %d\n", err);
2354
2355         return err;
2356 }
2357
2358 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359 {
2360         struct net_device *netdev = adapter->netdev;
2361
2362         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2363                 int i, q_vectors;
2364
2365                 q_vectors = adapter->num_msix_vectors;
2366
2367                 i = q_vectors - 1;
2368                 free_irq(adapter->msix_entries[i].vector, netdev);
2369
2370                 i--;
2371                 for (; i >= 0; i--) {
2372                         free_irq(adapter->msix_entries[i].vector,
2373                                  adapter->q_vector[i]);
2374                 }
2375
2376                 ixgbe_reset_q_vectors(adapter);
2377         } else {
2378                 free_irq(adapter->pdev->irq, netdev);
2379         }
2380 }
2381
2382 /**
2383  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384  * @adapter: board private structure
2385  **/
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387 {
2388         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390         } else {
2391                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2393                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2394                 if (adapter->num_vfs > 32)
2395                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2396         }
2397         IXGBE_WRITE_FLUSH(&adapter->hw);
2398         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399                 int i;
2400                 for (i = 0; i < adapter->num_msix_vectors; i++)
2401                         synchronize_irq(adapter->msix_entries[i].vector);
2402         } else {
2403                 synchronize_irq(adapter->pdev->irq);
2404         }
2405 }
2406
2407 /**
2408  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409  *
2410  **/
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412 {
2413         struct ixgbe_hw *hw = &adapter->hw;
2414
2415         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2416                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2417
2418         ixgbe_set_ivar(adapter, 0, 0, 0);
2419         ixgbe_set_ivar(adapter, 1, 0, 0);
2420
2421         map_vector_to_rxq(adapter, 0, 0);
2422         map_vector_to_txq(adapter, 0, 0);
2423
2424         e_info(hw, "Legacy interrupt IVAR setup done\n");
2425 }
2426
2427 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2428 {
2429         struct ixgbe_hw *hw = &adapter->hw;
2430         u32 rttdcs;
2431         u32 mask;
2432
2433         if (hw->mac.type == ixgbe_mac_82598EB)
2434                 return;
2435
2436         /* disable the arbiter while setting MTQC */
2437         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2438         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2439         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2440
2441         /* set transmit pool layout */
2442         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2443         switch (adapter->flags & mask) {
2444
2445         case (IXGBE_FLAG_SRIOV_ENABLED):
2446                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2447                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2448                 break;
2449
2450         case (IXGBE_FLAG_DCB_ENABLED):
2451                 /* We enable 8 traffic classes, DCB only */
2452                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2453                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2454                 break;
2455
2456         default:
2457                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2458                 break;
2459         }
2460
2461         /* re-enable the arbiter */
2462         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2463         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2464 }
2465
2466 /**
2467  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2468  * @adapter: board private structure
2469  *
2470  * Configure the Tx unit of the MAC after a reset.
2471  **/
2472 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2473 {
2474         u64 tdba;
2475         struct ixgbe_hw *hw = &adapter->hw;
2476         u32 i, j, tdlen, txctrl;
2477
2478         /* Setup the HW Tx Head and Tail descriptor pointers */
2479         for (i = 0; i < adapter->num_tx_queues; i++) {
2480                 struct ixgbe_ring *ring = adapter->tx_ring[i];
2481                 j = ring->reg_idx;
2482                 tdba = ring->dma;
2483                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
2484                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
2485                                 (tdba & DMA_BIT_MASK(32)));
2486                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
2487                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
2488                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
2489                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
2490                 adapter->tx_ring[i]->head = IXGBE_TDH(j);
2491                 adapter->tx_ring[i]->tail = IXGBE_TDT(j);
2492                 /*
2493                  * Disable Tx Head Writeback RO bit, since this hoses
2494                  * bookkeeping if things aren't delivered in order.
2495                  */
2496                 switch (hw->mac.type) {
2497                 case ixgbe_mac_82598EB:
2498                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
2499                         break;
2500                 case ixgbe_mac_82599EB:
2501                 default:
2502                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
2503                         break;
2504                 }
2505                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2506                 switch (hw->mac.type) {
2507                 case ixgbe_mac_82598EB:
2508                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
2509                         break;
2510                 case ixgbe_mac_82599EB:
2511                 default:
2512                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
2513                         break;
2514                 }
2515         }
2516
2517         ixgbe_setup_mtqc(adapter);
2518 }
2519
2520 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2521
2522 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2523                                    struct ixgbe_ring *rx_ring)
2524 {
2525         u32 srrctl;
2526         int index;
2527         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2528
2529         index = rx_ring->reg_idx;
2530         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2531                 unsigned long mask;
2532                 mask = (unsigned long) feature[RING_F_RSS].mask;
2533                 index = index & mask;
2534         }
2535         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2536
2537         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2538         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2539
2540         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2541                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2542
2543         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2544 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2545                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2546 #else
2547                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2548 #endif
2549                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2550         } else {
2551                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2552                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2553                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2554         }
2555
2556         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2557 }
2558
2559 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2560 {
2561         u32 mrqc = 0;
2562         int mask;
2563
2564         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
2565                 return mrqc;
2566
2567         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2568 #ifdef CONFIG_IXGBE_DCB
2569                                  | IXGBE_FLAG_DCB_ENABLED
2570 #endif
2571                                  | IXGBE_FLAG_SRIOV_ENABLED
2572                                 );
2573
2574         switch (mask) {
2575         case (IXGBE_FLAG_RSS_ENABLED):
2576                 mrqc = IXGBE_MRQC_RSSEN;
2577                 break;
2578         case (IXGBE_FLAG_SRIOV_ENABLED):
2579                 mrqc = IXGBE_MRQC_VMDQEN;
2580                 break;
2581 #ifdef CONFIG_IXGBE_DCB
2582         case (IXGBE_FLAG_DCB_ENABLED):
2583                 mrqc = IXGBE_MRQC_RT8TCEN;
2584                 break;
2585 #endif /* CONFIG_IXGBE_DCB */
2586         default:
2587                 break;
2588         }
2589
2590         return mrqc;
2591 }
2592
2593 /**
2594  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2595  * @adapter:    address of board private structure
2596  * @index:      index of ring to set
2597  **/
2598 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index)
2599 {
2600         struct ixgbe_ring *rx_ring;
2601         struct ixgbe_hw *hw = &adapter->hw;
2602         int j;
2603         u32 rscctrl;
2604         int rx_buf_len;
2605
2606         rx_ring = adapter->rx_ring[index];
2607         j = rx_ring->reg_idx;
2608         rx_buf_len = rx_ring->rx_buf_len;
2609         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2610         rscctrl |= IXGBE_RSCCTL_RSCEN;
2611         /*
2612          * we must limit the number of descriptors so that the
2613          * total size of max desc * buf_len is not greater
2614          * than 65535
2615          */
2616         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2617 #if (MAX_SKB_FRAGS > 16)
2618                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2619 #elif (MAX_SKB_FRAGS > 8)
2620                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2621 #elif (MAX_SKB_FRAGS > 4)
2622                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2623 #else
2624                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2625 #endif
2626         } else {
2627                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2628                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2629                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2630                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2631                 else
2632                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2633         }
2634         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2635 }
2636
2637 /**
2638  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2639  * @adapter: board private structure
2640  *
2641  * Configure the Rx unit of the MAC after a reset.
2642  **/
2643 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2644 {
2645         u64 rdba;
2646         struct ixgbe_hw *hw = &adapter->hw;
2647         struct ixgbe_ring *rx_ring;
2648         struct net_device *netdev = adapter->netdev;
2649         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2650         int i, j;
2651         u32 rdlen, rxctrl, rxcsum;
2652         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2653                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2654                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2655         u32 fctrl, hlreg0;
2656         u32 reta = 0, mrqc = 0;
2657         u32 rdrxctl;
2658         int rx_buf_len;
2659
2660         /* Decide whether to use packet split mode or not */
2661         /* Do not use packet split if we're in SR-IOV Mode */
2662         if (!adapter->num_vfs)
2663                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2664
2665         /* Set the RX buffer length according to the mode */
2666         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2667                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2668                 if (hw->mac.type == ixgbe_mac_82599EB) {
2669                         /* PSRTYPE must be initialized in 82599 */
2670                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2671                                       IXGBE_PSRTYPE_UDPHDR |
2672                                       IXGBE_PSRTYPE_IPV4HDR |
2673                                       IXGBE_PSRTYPE_IPV6HDR |
2674                                       IXGBE_PSRTYPE_L2HDR;
2675                         IXGBE_WRITE_REG(hw,
2676                                         IXGBE_PSRTYPE(adapter->num_vfs),
2677                                         psrtype);
2678                 }
2679         } else {
2680                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2681                     (netdev->mtu <= ETH_DATA_LEN))
2682                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2683                 else
2684                         rx_buf_len = ALIGN(max_frame, 1024);
2685         }
2686
2687         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2688         fctrl |= IXGBE_FCTRL_BAM;
2689         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2690         fctrl |= IXGBE_FCTRL_PMCF;
2691         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2692
2693         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2694         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2695                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2696         else
2697                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2698 #ifdef IXGBE_FCOE
2699         if (netdev->features & NETIF_F_FCOE_MTU)
2700                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2701 #endif
2702         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2703
2704         rdlen = adapter->rx_ring[0]->count * sizeof(union ixgbe_adv_rx_desc);
2705         /* disable receives while setting up the descriptors */
2706         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2707         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2708
2709         /*
2710          * Setup the HW Rx Head and Tail Descriptor Pointers and
2711          * the Base and Length of the Rx Descriptor Ring
2712          */
2713         for (i = 0; i < adapter->num_rx_queues; i++) {
2714                 rx_ring = adapter->rx_ring[i];
2715                 rdba = rx_ring->dma;
2716                 j = rx_ring->reg_idx;
2717                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2718                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2719                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2720                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2721                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2722                 rx_ring->head = IXGBE_RDH(j);
2723                 rx_ring->tail = IXGBE_RDT(j);
2724                 rx_ring->rx_buf_len = rx_buf_len;
2725
2726                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2727                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2728                 else
2729                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2730
2731 #ifdef IXGBE_FCOE
2732                 if (netdev->features & NETIF_F_FCOE_MTU) {
2733                         struct ixgbe_ring_feature *f;
2734                         f = &adapter->ring_feature[RING_F_FCOE];
2735                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2736                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2737                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2738                                         rx_ring->rx_buf_len =
2739                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2740                         }
2741                 }
2742
2743 #endif /* IXGBE_FCOE */
2744                 ixgbe_configure_srrctl(adapter, rx_ring);
2745         }
2746
2747         if (hw->mac.type == ixgbe_mac_82598EB) {
2748                 /*
2749                  * For VMDq support of different descriptor types or
2750                  * buffer sizes through the use of multiple SRRCTL
2751                  * registers, RDRXCTL.MVMEN must be set to 1
2752                  *
2753                  * also, the manual doesn't mention it clearly but DCA hints
2754                  * will only use queue 0's tags unless this bit is set.  Side
2755                  * effects of setting this bit are only that SRRCTL must be
2756                  * fully programmed [0..15]
2757                  */
2758                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2759                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2760                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2761         }
2762
2763         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2764                 u32 vt_reg_bits;
2765                 u32 reg_offset, vf_shift;
2766                 u32 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2767                 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN
2768                         | IXGBE_VT_CTL_REPLEN;
2769                 vt_reg_bits |= (adapter->num_vfs <<
2770                                 IXGBE_VT_CTL_POOL_SHIFT);
2771                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2772                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, 0);
2773
2774                 vf_shift = adapter->num_vfs % 32;
2775                 reg_offset = adapter->num_vfs / 32;
2776                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), 0);
2777                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), 0);
2778                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), 0);
2779                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), 0);
2780                 /* Enable only the PF's pool for Tx/Rx */
2781                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2782                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2783                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2784                 ixgbe_set_vmolr(hw, adapter->num_vfs, true);
2785         }
2786
2787         /* Program MRQC for the distribution of queues */
2788         mrqc = ixgbe_setup_mrqc(adapter);
2789
2790         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2791                 /* Fill out redirection table */
2792                 for (i = 0, j = 0; i < 128; i++, j++) {
2793                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2794                                 j = 0;
2795                         /* reta = 4-byte sliding window of
2796                          * 0x00..(indices-1)(indices-1)00..etc. */
2797                         reta = (reta << 8) | (j * 0x11);
2798                         if ((i & 3) == 3)
2799                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2800                 }
2801
2802                 /* Fill out hash function seeds */
2803                 for (i = 0; i < 10; i++)
2804                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2805
2806                 if (hw->mac.type == ixgbe_mac_82598EB)
2807                         mrqc |= IXGBE_MRQC_RSSEN;
2808                     /* Perform hash on these packet types */
2809                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2810                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2811                       | IXGBE_MRQC_RSS_FIELD_IPV6
2812                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2813         }
2814         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2815
2816         if (adapter->num_vfs) {
2817                 u32 reg;
2818
2819                 /* Map PF MAC address in RAR Entry 0 to first pool
2820                  * following VFs */
2821                 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2822
2823                 /* Set up VF register offsets for selected VT Mode, i.e.
2824                  * 64 VFs for SR-IOV */
2825                 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2826                 reg |= IXGBE_GCR_EXT_SRIOV;
2827                 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);
2828         }
2829
2830         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2831
2832         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2833             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2834                 /* Disable indicating checksum in descriptor, enables
2835                  * RSS hash */
2836                 rxcsum |= IXGBE_RXCSUM_PCSD;
2837         }
2838         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2839                 /* Enable IPv4 payload checksum for UDP fragments
2840                  * if PCSD is not set */
2841                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2842         }
2843
2844         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2845
2846         if (hw->mac.type == ixgbe_mac_82599EB) {
2847                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2848                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2849                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2850                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2851         }
2852
2853         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2854                 /* Enable 82599 HW-RSC */
2855                 for (i = 0; i < adapter->num_rx_queues; i++)
2856                         ixgbe_configure_rscctl(adapter, i);
2857
2858                 /* Disable RSC for ACK packets */
2859                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2860                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2861         }
2862 }
2863
2864 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2865 {
2866         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2867         struct ixgbe_hw *hw = &adapter->hw;
2868         int pool_ndx = adapter->num_vfs;
2869
2870         /* add VID to filter table */
2871         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2872 }
2873
2874 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2875 {
2876         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2877         struct ixgbe_hw *hw = &adapter->hw;
2878         int pool_ndx = adapter->num_vfs;
2879
2880         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2881                 ixgbe_irq_disable(adapter);
2882
2883         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2884
2885         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2886                 ixgbe_irq_enable(adapter);
2887
2888         /* remove VID from filter table */
2889         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2890 }
2891
2892 /**
2893  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2894  * @adapter: driver data
2895  */
2896 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2897 {
2898         struct ixgbe_hw *hw = &adapter->hw;
2899         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2900         int i, j;
2901
2902         switch (hw->mac.type) {
2903         case ixgbe_mac_82598EB:
2904                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2905 #ifdef CONFIG_IXGBE_DCB
2906                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2907                         vlnctrl &= ~IXGBE_VLNCTRL_VME;
2908 #endif
2909                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2910                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2911                 break;
2912         case ixgbe_mac_82599EB:
2913                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2914                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2915                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2916 #ifdef CONFIG_IXGBE_DCB
2917                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2918                         break;
2919 #endif
2920                 for (i = 0; i < adapter->num_rx_queues; i++) {
2921                         j = adapter->rx_ring[i]->reg_idx;
2922                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2923                         vlnctrl &= ~IXGBE_RXDCTL_VME;
2924                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2925                 }
2926                 break;
2927         default:
2928                 break;
2929         }
2930 }
2931
2932 /**
2933  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2934  * @adapter: driver data
2935  */
2936 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2937 {
2938         struct ixgbe_hw *hw = &adapter->hw;
2939         u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2940         int i, j;
2941
2942         switch (hw->mac.type) {
2943         case ixgbe_mac_82598EB:
2944                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2945                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2946                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2947                 break;
2948         case ixgbe_mac_82599EB:
2949                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2950                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2951                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2952                 for (i = 0; i < adapter->num_rx_queues; i++) {
2953                         j = adapter->rx_ring[i]->reg_idx;
2954                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2955                         vlnctrl |= IXGBE_RXDCTL_VME;
2956                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2957                 }
2958                 break;
2959         default:
2960                 break;
2961         }
2962 }
2963
2964 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2965                                    struct vlan_group *grp)
2966 {
2967         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2968
2969         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2970                 ixgbe_irq_disable(adapter);
2971         adapter->vlgrp = grp;
2972
2973         /*
2974          * For a DCB driver, always enable VLAN tag stripping so we can
2975          * still receive traffic from a DCB-enabled host even if we're
2976          * not in DCB mode.
2977          */
2978         ixgbe_vlan_filter_enable(adapter);
2979
2980         ixgbe_vlan_rx_add_vid(netdev, 0);
2981
2982         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2983                 ixgbe_irq_enable(adapter);
2984 }
2985
2986 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2987 {
2988         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2989
2990         if (adapter->vlgrp) {
2991                 u16 vid;
2992                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2993                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2994                                 continue;
2995                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2996                 }
2997         }
2998 }
2999
3000 /**
3001  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3002  * @netdev: network interface device structure
3003  *
3004  * Writes unicast address list to the RAR table.
3005  * Returns: -ENOMEM on failure/insufficient address space
3006  *                0 on no addresses written
3007  *                X on writing X addresses to the RAR table
3008  **/
3009 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3010 {
3011         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3012         struct ixgbe_hw *hw = &adapter->hw;
3013         unsigned int vfn = adapter->num_vfs;
3014         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3015         int count = 0;
3016
3017         /* return ENOMEM indicating insufficient memory for addresses */
3018         if (netdev_uc_count(netdev) > rar_entries)
3019                 return -ENOMEM;
3020
3021         if (!netdev_uc_empty(netdev) && rar_entries) {
3022                 struct netdev_hw_addr *ha;
3023                 /* return error if we do not support writing to RAR table */
3024                 if (!hw->mac.ops.set_rar)
3025                         return -ENOMEM;
3026
3027                 netdev_for_each_uc_addr(ha, netdev) {
3028                         if (!rar_entries)
3029                                 break;
3030                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3031                                             vfn, IXGBE_RAH_AV);
3032                         count++;
3033                 }
3034         }
3035         /* write the addresses in reverse order to avoid write combining */
3036         for (; rar_entries > 0 ; rar_entries--)
3037                 hw->mac.ops.clear_rar(hw, rar_entries);
3038
3039         return count;
3040 }
3041
3042 /**
3043  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3044  * @netdev: network interface device structure
3045  *
3046  * The set_rx_method entry point is called whenever the unicast/multicast
3047  * address list or the network interface flags are updated.  This routine is
3048  * responsible for configuring the hardware for proper unicast, multicast and
3049  * promiscuous mode.
3050  **/
3051 void ixgbe_set_rx_mode(struct net_device *netdev)
3052 {
3053         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3054         struct ixgbe_hw *hw = &adapter->hw;
3055         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3056         int count;
3057
3058         /* Check for Promiscuous and All Multicast modes */
3059
3060         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3061
3062         /* clear the bits we are changing the status of */
3063         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3064
3065         if (netdev->flags & IFF_PROMISC) {
3066                 hw->addr_ctrl.user_set_promisc = true;
3067                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3068                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3069                 /* don't hardware filter vlans in promisc mode */
3070                 ixgbe_vlan_filter_disable(adapter);
3071         } else {
3072                 if (netdev->flags & IFF_ALLMULTI) {
3073                         fctrl |= IXGBE_FCTRL_MPE;
3074                         vmolr |= IXGBE_VMOLR_MPE;
3075                 } else {
3076                         /*
3077                          * Write addresses to the MTA, if the attempt fails
3078                          * then we should just turn on promiscous mode so
3079                          * that we can at least receive multicast traffic
3080                          */
3081                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3082                         vmolr |= IXGBE_VMOLR_ROMPE;
3083                 }
3084                 ixgbe_vlan_filter_enable(adapter);
3085                 hw->addr_ctrl.user_set_promisc = false;
3086                 /*
3087                  * Write addresses to available RAR registers, if there is not
3088                  * sufficient space to store all the addresses then enable
3089                  * unicast promiscous mode
3090                  */
3091                 count = ixgbe_write_uc_addr_list(netdev);
3092                 if (count < 0) {
3093                         fctrl |= IXGBE_FCTRL_UPE;
3094                         vmolr |= IXGBE_VMOLR_ROPE;
3095                 }
3096         }
3097
3098         if (adapter->num_vfs) {
3099                 ixgbe_restore_vf_multicasts(adapter);
3100                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3101                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3102                            IXGBE_VMOLR_ROPE);
3103                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3104         }
3105
3106         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3107 }
3108
3109 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3110 {
3111         int q_idx;
3112         struct ixgbe_q_vector *q_vector;
3113         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3114
3115         /* legacy and MSI only use one vector */
3116         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3117                 q_vectors = 1;
3118
3119         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3120                 struct napi_struct *napi;
3121                 q_vector = adapter->q_vector[q_idx];
3122                 napi = &q_vector->napi;
3123                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3124                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3125                                 if (q_vector->txr_count == 1)
3126                                         napi->poll = &ixgbe_clean_txonly;
3127                                 else if (q_vector->rxr_count == 1)
3128                                         napi->poll = &ixgbe_clean_rxonly;
3129                         }
3130                 }
3131
3132                 napi_enable(napi);
3133         }
3134 }
3135
3136 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3137 {
3138         int q_idx;
3139         struct ixgbe_q_vector *q_vector;
3140         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3141
3142         /* legacy and MSI only use one vector */
3143         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3144                 q_vectors = 1;
3145
3146         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3147                 q_vector = adapter->q_vector[q_idx];
3148                 napi_disable(&q_vector->napi);
3149         }
3150 }
3151
3152 #ifdef CONFIG_IXGBE_DCB
3153 /*
3154  * ixgbe_configure_dcb - Configure DCB hardware
3155  * @adapter: ixgbe adapter struct
3156  *
3157  * This is called by the driver on open to configure the DCB hardware.
3158  * This is also called by the gennetlink interface when reconfiguring
3159  * the DCB state.
3160  */
3161 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3162 {
3163         struct ixgbe_hw *hw = &adapter->hw;
3164         u32 txdctl;
3165         int i, j;
3166
3167         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3168                 if (hw->mac.type == ixgbe_mac_82598EB)
3169                         netif_set_gso_max_size(adapter->netdev, 65536);
3170                 return;
3171         }
3172
3173         if (hw->mac.type == ixgbe_mac_82598EB)
3174                 netif_set_gso_max_size(adapter->netdev, 32768);
3175
3176         ixgbe_dcb_check_config(&adapter->dcb_cfg);
3177         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3178         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3179
3180         /* reconfigure the hardware */
3181         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3182
3183         for (i = 0; i < adapter->num_tx_queues; i++) {
3184                 j = adapter->tx_ring[i]->reg_idx;
3185                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3186                 /* PThresh workaround for Tx hang with DFP enabled. */
3187                 txdctl |= 32;
3188                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3189         }
3190         /* Enable VLAN tag insert/strip */
3191         ixgbe_vlan_filter_enable(adapter);
3192
3193         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3194 }
3195
3196 #endif
3197 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3198 {
3199         struct net_device *netdev = adapter->netdev;
3200         struct ixgbe_hw *hw = &adapter->hw;
3201         int i;
3202
3203         ixgbe_set_rx_mode(netdev);
3204
3205         ixgbe_restore_vlan(adapter);
3206 #ifdef CONFIG_IXGBE_DCB
3207         ixgbe_configure_dcb(adapter);
3208 #endif
3209
3210 #ifdef IXGBE_FCOE
3211         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3212                 ixgbe_configure_fcoe(adapter);
3213
3214 #endif /* IXGBE_FCOE */
3215         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3216                 for (i = 0; i < adapter->num_tx_queues; i++)
3217                         adapter->tx_ring[i]->atr_sample_rate =
3218                                                        adapter->atr_sample_rate;
3219                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3220         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3221                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3222         }
3223
3224         ixgbe_configure_tx(adapter);
3225         ixgbe_configure_rx(adapter);
3226         for (i = 0; i < adapter->num_rx_queues; i++)
3227                 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3228                                        (adapter->rx_ring[i]->count - 1));
3229 }
3230
3231 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3232 {
3233         switch (hw->phy.type) {
3234         case ixgbe_phy_sfp_avago:
3235         case ixgbe_phy_sfp_ftl:
3236         case ixgbe_phy_sfp_intel:
3237         case ixgbe_phy_sfp_unknown:
3238         case ixgbe_phy_sfp_passive_tyco:
3239         case ixgbe_phy_sfp_passive_unknown:
3240         case ixgbe_phy_sfp_active_unknown:
3241         case ixgbe_phy_sfp_ftl_active:
3242                 return true;
3243         default:
3244                 return false;
3245         }
3246 }
3247
3248 /**
3249  * ixgbe_sfp_link_config - set up SFP+ link
3250  * @adapter: pointer to private adapter struct
3251  **/
3252 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3253 {
3254         struct ixgbe_hw *hw = &adapter->hw;
3255
3256                 if (hw->phy.multispeed_fiber) {
3257                         /*
3258                          * In multispeed fiber setups, the device may not have
3259                          * had a physical connection when the driver loaded.
3260                          * If that's the case, the initial link configuration
3261                          * couldn't get the MAC into 10G or 1G mode, so we'll
3262                          * never have a link status change interrupt fire.
3263                          * We need to try and force an autonegotiation
3264                          * session, then bring up link.
3265                          */
3266                         hw->mac.ops.setup_sfp(hw);
3267                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3268                                 schedule_work(&adapter->multispeed_fiber_task);
3269                 } else {
3270                         /*
3271                          * Direct Attach Cu and non-multispeed fiber modules
3272                          * still need to be configured properly prior to
3273                          * attempting link.
3274                          */
3275                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3276                                 schedule_work(&adapter->sfp_config_module_task);
3277                 }
3278 }
3279
3280 /**
3281  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3282  * @hw: pointer to private hardware struct
3283  *
3284  * Returns 0 on success, negative on failure
3285  **/
3286 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3287 {
3288         u32 autoneg;
3289         bool negotiation, link_up = false;
3290         u32 ret = IXGBE_ERR_LINK_SETUP;
3291
3292         if (hw->mac.ops.check_link)
3293                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3294
3295         if (ret)
3296                 goto link_cfg_out;
3297
3298         if (hw->mac.ops.get_link_capabilities)
3299                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3300         if (ret)
3301                 goto link_cfg_out;
3302
3303         if (hw->mac.ops.setup_link)
3304                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3305 link_cfg_out:
3306         return ret;
3307 }
3308
3309 #define IXGBE_MAX_RX_DESC_POLL 10
3310 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3311                                               int rxr)
3312 {
3313         int j = adapter->rx_ring[rxr]->reg_idx;
3314         int k;
3315
3316         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3317                 if (IXGBE_READ_REG(&adapter->hw,
3318                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3319                         break;
3320                 else
3321                         msleep(1);
3322         }
3323         if (k >= IXGBE_MAX_RX_DESC_POLL) {
3324                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3325                       "the polling period\n", rxr);
3326         }
3327         ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3328                               (adapter->rx_ring[rxr]->count - 1));
3329 }
3330
3331 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3332 {
3333         struct net_device *netdev = adapter->netdev;
3334         struct ixgbe_hw *hw = &adapter->hw;
3335         int i, j = 0;
3336         int num_rx_rings = adapter->num_rx_queues;
3337         int err;
3338         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3339         u32 txdctl, rxdctl, mhadd;
3340         u32 dmatxctl;
3341         u32 gpie;
3342         u32 ctrl_ext;
3343
3344         ixgbe_get_hw_control(adapter);
3345
3346         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
3347             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
3348                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3349                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
3350                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
3351                 } else {
3352                         /* MSI only */
3353                         gpie = 0;
3354                 }
3355                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3356                         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3357                         gpie |= IXGBE_GPIE_VTMODE_64;
3358                 }
3359                 /* XXX: to interrupt immediately for EICS writes, enable this */
3360                 /* gpie |= IXGBE_GPIE_EIMEN; */
3361                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3362         }
3363
3364         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3365                 /*
3366                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3367                  * this saves a register write for every interrupt
3368                  */
3369                 switch (hw->mac.type) {
3370                 case ixgbe_mac_82598EB:
3371                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3372                         break;
3373                 default:
3374                 case ixgbe_mac_82599EB:
3375                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3376                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3377                         break;
3378                 }
3379         } else {
3380                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3381                  * specifically only auto mask tx and rx interrupts */
3382                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3383         }
3384
3385         /* Enable Thermal over heat sensor interrupt */
3386         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3387                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3388                 gpie |= IXGBE_SDP0_GPIEN;
3389                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3390         }
3391
3392         /* Enable fan failure interrupt if media type is copper */
3393         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3394                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3395                 gpie |= IXGBE_SDP1_GPIEN;
3396                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3397         }
3398
3399         if (hw->mac.type == ixgbe_mac_82599EB) {
3400                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3401                 gpie |= IXGBE_SDP1_GPIEN;
3402                 gpie |= IXGBE_SDP2_GPIEN;
3403                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3404         }
3405
3406 #ifdef IXGBE_FCOE
3407         /* adjust max frame to be able to do baby jumbo for FCoE */
3408         if ((netdev->features & NETIF_F_FCOE_MTU) &&
3409             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3410                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3411
3412 #endif /* IXGBE_FCOE */
3413         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3414         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3415                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3416                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3417
3418                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3419         }
3420
3421         if (hw->mac.type == ixgbe_mac_82599EB) {
3422                 /* DMATXCTL.EN must be set after all Tx queue config is done */
3423                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3424                 dmatxctl |= IXGBE_DMATXCTL_TE;
3425                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3426         }
3427         for (i = 0; i < adapter->num_tx_queues; i++) {
3428                 j = adapter->tx_ring[i]->reg_idx;
3429                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3430                 if (adapter->rx_itr_setting == 0) {
3431                         /* cannot set wthresh when itr==0 */
3432                         txdctl &= ~0x007F0000;
3433                 } else {
3434                         /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3435                         txdctl |= (8 << 16);
3436                 }
3437                 txdctl |= IXGBE_TXDCTL_ENABLE;
3438                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3439                 if (hw->mac.type == ixgbe_mac_82599EB) {
3440                         int wait_loop = 10;
3441                         /* poll for Tx Enable ready */
3442                         do {
3443                                 msleep(1);
3444                                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3445                         } while (--wait_loop &&
3446                                  !(txdctl & IXGBE_TXDCTL_ENABLE));
3447                         if (!wait_loop)
3448                                 e_err(drv, "Could not enable Tx Queue %d\n", j);
3449                 }
3450         }
3451
3452         for (i = 0; i < num_rx_rings; i++) {
3453                 j = adapter->rx_ring[i]->reg_idx;
3454                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3455                 /* enable PTHRESH=32 descriptors (half the internal cache)
3456                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
3457                  * this also removes a pesky rx_no_buffer_count increment */
3458                 rxdctl |= 0x0020;
3459                 rxdctl |= IXGBE_RXDCTL_ENABLE;
3460                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3461                 if (hw->mac.type == ixgbe_mac_82599EB)
3462                         ixgbe_rx_desc_queue_enable(adapter, i);
3463         }
3464         /* enable all receives */
3465         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3466         if (hw->mac.type == ixgbe_mac_82598EB)
3467                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3468         else
3469                 rxdctl |= IXGBE_RXCTRL_RXEN;
3470         hw->mac.ops.enable_rx_dma(hw, rxdctl);
3471
3472         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3473                 ixgbe_configure_msix(adapter);
3474         else
3475                 ixgbe_configure_msi_and_legacy(adapter);
3476
3477         /* enable the optics */
3478         if (hw->phy.multispeed_fiber)
3479                 hw->mac.ops.enable_tx_laser(hw);
3480
3481         clear_bit(__IXGBE_DOWN, &adapter->state);
3482         ixgbe_napi_enable_all(adapter);
3483
3484         /* clear any pending interrupts, may auto mask */
3485         IXGBE_READ_REG(hw, IXGBE_EICR);
3486
3487         ixgbe_irq_enable(adapter);
3488
3489         /*
3490          * If this adapter has a fan, check to see if we had a failure
3491          * before we enabled the interrupt.
3492          */
3493         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3494                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3495                 if (esdp & IXGBE_ESDP_SDP1)
3496                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3497         }
3498
3499         /*
3500          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3501          * arrived before interrupts were enabled but after probe.  Such
3502          * devices wouldn't have their type identified yet. We need to
3503          * kick off the SFP+ module setup first, then try to bring up link.
3504          * If we're not hot-pluggable SFP+, we just need to configure link
3505          * and bring it up.
3506          */
3507         if (hw->phy.type == ixgbe_phy_unknown) {
3508                 err = hw->phy.ops.identify(hw);
3509                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3510                         /*
3511                          * Take the device down and schedule the sfp tasklet
3512                          * which will unregister_netdev and log it.
3513                          */
3514                         ixgbe_down(adapter);
3515                         schedule_work(&adapter->sfp_config_module_task);
3516                         return err;
3517                 }
3518         }
3519
3520         if (ixgbe_is_sfp(hw)) {
3521                 ixgbe_sfp_link_config(adapter);
3522         } else {
3523                 err = ixgbe_non_sfp_link_config(hw);
3524                 if (err)
3525                         e_err(probe, "link_config FAILED %d\n", err);
3526         }
3527
3528         for (i = 0; i < adapter->num_tx_queues; i++)
3529                 set_bit(__IXGBE_FDIR_INIT_DONE,
3530                         &(adapter->tx_ring[i]->reinit_state));
3531
3532         /* enable transmits */
3533         netif_tx_start_all_queues(netdev);
3534
3535         /* bring the link up in the watchdog, this could race with our first
3536          * link up interrupt but shouldn't be a problem */
3537         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3538         adapter->link_check_timeout = jiffies;
3539         mod_timer(&adapter->watchdog_timer, jiffies);
3540
3541         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3542         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3543         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3544         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3545
3546         return 0;
3547 }
3548
3549 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3550 {
3551         WARN_ON(in_interrupt());
3552         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3553                 msleep(1);
3554         ixgbe_down(adapter);
3555         /*
3556          * If SR-IOV enabled then wait a bit before bringing the adapter
3557          * back up to give the VFs time to respond to the reset.  The
3558          * two second wait is based upon the watchdog timer cycle in
3559          * the VF driver.
3560          */
3561         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3562                 msleep(2000);
3563         ixgbe_up(adapter);
3564         clear_bit(__IXGBE_RESETTING, &adapter->state);
3565 }
3566
3567 int ixgbe_up(struct ixgbe_adapter *adapter)
3568 {
3569         /* hardware has been reset, we need to reload some things */
3570         ixgbe_configure(adapter);
3571
3572         return ixgbe_up_complete(adapter);
3573 }
3574
3575 void ixgbe_reset(struct ixgbe_adapter *adapter)
3576 {
3577         struct ixgbe_hw *hw = &adapter->hw;
3578         int err;
3579
3580         err = hw->mac.ops.init_hw(hw);
3581         switch (err) {
3582         case 0:
3583         case IXGBE_ERR_SFP_NOT_PRESENT:
3584                 break;
3585         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3586                 e_dev_err("master disable timed out\n");
3587                 break;
3588         case IXGBE_ERR_EEPROM_VERSION:
3589                 /* We are running on a pre-production device, log a warning */
3590                 e_dev_warn("This device is a pre-production adapter/LOM. "
3591                            "Please be aware there may be issuesassociated with "
3592                            "your hardware.  If you are experiencing problems "
3593                            "please contact your Intel or hardware "
3594                            "representative who provided you with this "
3595                            "hardware.\n");
3596                 break;
3597         default:
3598                 e_dev_err("Hardware Error: %d\n", err);
3599         }
3600
3601         /* reprogram the RAR[0] in case user changed it. */
3602         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3603                             IXGBE_RAH_AV);
3604 }
3605
3606 /**
3607  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3608  * @adapter: board private structure
3609  * @rx_ring: ring to free buffers from
3610  **/
3611 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3612                                 struct ixgbe_ring *rx_ring)
3613 {
3614         struct pci_dev *pdev = adapter->pdev;
3615         unsigned long size;
3616         unsigned int i;
3617
3618         /* Free all the Rx ring sk_buffs */
3619
3620         for (i = 0; i < rx_ring->count; i++) {
3621                 struct ixgbe_rx_buffer *rx_buffer_info;
3622
3623                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3624                 if (rx_buffer_info->dma) {
3625                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3626                                          rx_ring->rx_buf_len,
3627                                          DMA_FROM_DEVICE);
3628                         rx_buffer_info->dma = 0;
3629                 }
3630                 if (rx_buffer_info->skb) {
3631                         struct sk_buff *skb = rx_buffer_info->skb;
3632                         rx_buffer_info->skb = NULL;
3633                         do {
3634                                 struct sk_buff *this = skb;
3635                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3636                                         dma_unmap_single(&pdev->dev,
3637                                                          IXGBE_RSC_CB(this)->dma,
3638                                                          rx_ring->rx_buf_len,
3639                                                          DMA_FROM_DEVICE);
3640                                         IXGBE_RSC_CB(this)->dma = 0;
3641                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3642                                 }
3643                                 skb = skb->prev;
3644                                 dev_kfree_skb(this);
3645                         } while (skb);
3646                 }
3647                 if (!rx_buffer_info->page)
3648                         continue;
3649                 if (rx_buffer_info->page_dma) {
3650                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3651                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3652                         rx_buffer_info->page_dma = 0;
3653                 }
3654                 put_page(rx_buffer_info->page);
3655                 rx_buffer_info->page = NULL;
3656                 rx_buffer_info->page_offset = 0;
3657         }
3658
3659         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3660         memset(rx_ring->rx_buffer_info, 0, size);
3661
3662         /* Zero out the descriptor ring */
3663         memset(rx_ring->desc, 0, rx_ring->size);
3664
3665         rx_ring->next_to_clean = 0;
3666         rx_ring->next_to_use = 0;
3667
3668         if (rx_ring->head)
3669                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3670         if (rx_ring->tail)
3671                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3672 }
3673
3674 /**
3675  * ixgbe_clean_tx_ring - Free Tx Buffers
3676  * @adapter: board private structure
3677  * @tx_ring: ring to be cleaned
3678  **/
3679 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3680                                 struct ixgbe_ring *tx_ring)
3681 {
3682         struct ixgbe_tx_buffer *tx_buffer_info;
3683         unsigned long size;
3684         unsigned int i;
3685
3686         /* Free all the Tx ring sk_buffs */
3687
3688         for (i = 0; i < tx_ring->count; i++) {
3689                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3690                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3691         }
3692
3693         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3694         memset(tx_ring->tx_buffer_info, 0, size);
3695
3696         /* Zero out the descriptor ring */
3697         memset(tx_ring->desc, 0, tx_ring->size);
3698
3699         tx_ring->next_to_use = 0;
3700         tx_ring->next_to_clean = 0;
3701
3702         if (tx_ring->head)
3703                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3704         if (tx_ring->tail)
3705                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3706 }
3707
3708 /**
3709  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3710  * @adapter: board private structure
3711  **/
3712 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3713 {
3714         int i;
3715
3716         for (i = 0; i < adapter->num_rx_queues; i++)
3717                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3718 }
3719
3720 /**
3721  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3722  * @adapter: board private structure
3723  **/
3724 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3725 {
3726         int i;
3727
3728         for (i = 0; i < adapter->num_tx_queues; i++)
3729                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3730 }
3731
3732 void ixgbe_down(struct ixgbe_adapter *adapter)
3733 {
3734         struct net_device *netdev = adapter->netdev;
3735         struct ixgbe_hw *hw = &adapter->hw;
3736         u32 rxctrl;
3737         u32 txdctl;
3738         int i, j;
3739
3740         /* signal that we are down to the interrupt handler */
3741         set_bit(__IXGBE_DOWN, &adapter->state);
3742
3743         /* disable receive for all VFs and wait one second */
3744         if (adapter->num_vfs) {
3745                 /* ping all the active vfs to let them know we are going down */
3746                 ixgbe_ping_all_vfs(adapter);
3747
3748                 /* Disable all VFTE/VFRE TX/RX */
3749                 ixgbe_disable_tx_rx(adapter);
3750
3751                 /* Mark all the VFs as inactive */
3752                 for (i = 0 ; i < adapter->num_vfs; i++)
3753                         adapter->vfinfo[i].clear_to_send = 0;
3754         }
3755
3756         /* disable receives */
3757         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3758         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3759
3760         IXGBE_WRITE_FLUSH(hw);
3761         msleep(10);
3762
3763         netif_tx_stop_all_queues(netdev);
3764
3765         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3766         del_timer_sync(&adapter->sfp_timer);
3767         del_timer_sync(&adapter->watchdog_timer);
3768         cancel_work_sync(&adapter->watchdog_task);
3769
3770         netif_carrier_off(netdev);
3771         netif_tx_disable(netdev);
3772
3773         ixgbe_irq_disable(adapter);
3774
3775         ixgbe_napi_disable_all(adapter);
3776
3777         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3778             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3779                 cancel_work_sync(&adapter->fdir_reinit_task);
3780
3781         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3782                 cancel_work_sync(&adapter->check_overtemp_task);
3783
3784         /* disable transmits in the hardware now that interrupts are off */
3785         for (i = 0; i < adapter->num_tx_queues; i++) {
3786                 j = adapter->tx_ring[i]->reg_idx;
3787                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3788                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3789                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3790         }
3791         /* Disable the Tx DMA engine on 82599 */
3792         if (hw->mac.type == ixgbe_mac_82599EB)
3793                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3794                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3795                                  ~IXGBE_DMATXCTL_TE));
3796
3797         /* power down the optics */
3798         if (hw->phy.multispeed_fiber)
3799                 hw->mac.ops.disable_tx_laser(hw);
3800
3801         /* clear n-tuple filters that are cached */
3802         ethtool_ntuple_flush(netdev);
3803
3804         if (!pci_channel_offline(adapter->pdev))
3805                 ixgbe_reset(adapter);
3806         ixgbe_clean_all_tx_rings(adapter);
3807         ixgbe_clean_all_rx_rings(adapter);
3808
3809 #ifdef CONFIG_IXGBE_DCA
3810         /* since we reset the hardware DCA settings were cleared */
3811         ixgbe_setup_dca(adapter);
3812 #endif
3813 }
3814
3815 /**
3816  * ixgbe_poll - NAPI Rx polling callback
3817  * @napi: structure for representing this polling device
3818  * @budget: how many packets driver is allowed to clean
3819  *
3820  * This function is used for legacy and MSI, NAPI mode
3821  **/
3822 static int ixgbe_poll(struct napi_struct *napi, int budget)
3823 {
3824         struct ixgbe_q_vector *q_vector =
3825                                 container_of(napi, struct ixgbe_q_vector, napi);
3826         struct ixgbe_adapter *adapter = q_vector->adapter;
3827         int tx_clean_complete, work_done = 0;
3828
3829 #ifdef CONFIG_IXGBE_DCA
3830         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3831                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3832                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3833         }
3834 #endif
3835
3836         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3837         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3838
3839         if (!tx_clean_complete)
3840                 work_done = budget;
3841
3842         /* If budget not fully consumed, exit the polling mode */
3843         if (work_done < budget) {
3844                 napi_complete(napi);
3845                 if (adapter->rx_itr_setting & 1)
3846                         ixgbe_set_itr(adapter);
3847                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3848                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3849         }
3850         return work_done;
3851 }
3852
3853 /**
3854  * ixgbe_tx_timeout - Respond to a Tx Hang
3855  * @netdev: network interface device structure
3856  **/
3857 static void ixgbe_tx_timeout(struct net_device *netdev)
3858 {
3859         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3860
3861         /* Do the reset outside of interrupt context */
3862         schedule_work(&adapter->reset_task);
3863 }
3864
3865 static void ixgbe_reset_task(struct work_struct *work)
3866 {
3867         struct ixgbe_adapter *adapter;
3868         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3869
3870         /* If we're already down or resetting, just bail */
3871         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3872             test_bit(__IXGBE_RESETTING, &adapter->state))
3873                 return;
3874
3875         adapter->tx_timeout_count++;
3876
3877         ixgbe_dump(adapter);
3878         netdev_err(adapter->netdev, "Reset adapter\n");
3879         ixgbe_reinit_locked(adapter);
3880 }
3881
3882 #ifdef CONFIG_IXGBE_DCB
3883 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3884 {
3885         bool ret = false;
3886         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3887
3888         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3889                 return ret;
3890
3891         f->mask = 0x7 << 3;
3892         adapter->num_rx_queues = f->indices;
3893         adapter->num_tx_queues = f->indices;
3894         ret = true;
3895
3896         return ret;
3897 }
3898 #endif
3899
3900 /**
3901  * ixgbe_set_rss_queues: Allocate queues for RSS
3902  * @adapter: board private structure to initialize
3903  *
3904  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3905  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3906  *
3907  **/
3908 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3909 {
3910         bool ret = false;
3911         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3912
3913         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3914                 f->mask = 0xF;
3915                 adapter->num_rx_queues = f->indices;
3916                 adapter->num_tx_queues = f->indices;
3917                 ret = true;
3918         } else {
3919                 ret = false;
3920         }
3921
3922         return ret;
3923 }
3924
3925 /**
3926  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3927  * @adapter: board private structure to initialize
3928  *
3929  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3930  * to the original CPU that initiated the Tx session.  This runs in addition
3931  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3932  * Rx load across CPUs using RSS.
3933  *
3934  **/
3935 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3936 {
3937         bool ret = false;
3938         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3939
3940         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3941         f_fdir->mask = 0;
3942
3943         /* Flow Director must have RSS enabled */
3944         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3945             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3946              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3947                 adapter->num_tx_queues = f_fdir->indices;
3948                 adapter->num_rx_queues = f_fdir->indices;
3949                 ret = true;
3950         } else {
3951                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3952                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3953         }
3954         return ret;
3955 }
3956
3957 #ifdef IXGBE_FCOE
3958 /**
3959  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3960  * @adapter: board private structure to initialize
3961  *
3962  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3963  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3964  * rx queues out of the max number of rx queues, instead, it is used as the
3965  * index of the first rx queue used by FCoE.
3966  *
3967  **/
3968 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3969 {
3970         bool ret = false;
3971         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3972
3973         f->indices = min((int)num_online_cpus(), f->indices);
3974         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3975                 adapter->num_rx_queues = 1;
3976                 adapter->num_tx_queues = 1;
3977 #ifdef CONFIG_IXGBE_DCB
3978                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3979                         e_info(probe, "FCoE enabled with DCB\n");
3980                         ixgbe_set_dcb_queues(adapter);
3981                 }
3982 #endif
3983                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3984                         e_info(probe, "FCoE enabled with RSS\n");
3985                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3986                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3987                                 ixgbe_set_fdir_queues(adapter);
3988                         else
3989                                 ixgbe_set_rss_queues(adapter);
3990                 }
3991                 /* adding FCoE rx rings to the end */
3992                 f->mask = adapter->num_rx_queues;
3993                 adapter->num_rx_queues += f->indices;
3994                 adapter->num_tx_queues += f->indices;
3995
3996                 ret = true;
3997         }
3998
3999         return ret;
4000 }
4001
4002 #endif /* IXGBE_FCOE */
4003 /**
4004  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4005  * @adapter: board private structure to initialize
4006  *
4007  * IOV doesn't actually use anything, so just NAK the
4008  * request for now and let the other queue routines
4009  * figure out what to do.
4010  */
4011 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4012 {
4013         return false;
4014 }
4015
4016 /*
4017  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4018  * @adapter: board private structure to initialize
4019  *
4020  * This is the top level queue allocation routine.  The order here is very
4021  * important, starting with the "most" number of features turned on at once,
4022  * and ending with the smallest set of features.  This way large combinations
4023  * can be allocated if they're turned on, and smaller combinations are the
4024  * fallthrough conditions.
4025  *
4026  **/
4027 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4028 {
4029         /* Start with base case */
4030         adapter->num_rx_queues = 1;
4031         adapter->num_tx_queues = 1;
4032         adapter->num_rx_pools = adapter->num_rx_queues;
4033         adapter->num_rx_queues_per_pool = 1;
4034
4035         if (ixgbe_set_sriov_queues(adapter))
4036                 return;
4037
4038 #ifdef IXGBE_FCOE
4039         if (ixgbe_set_fcoe_queues(adapter))
4040                 goto done;
4041
4042 #endif /* IXGBE_FCOE */
4043 #ifdef CONFIG_IXGBE_DCB
4044         if (ixgbe_set_dcb_queues(adapter))
4045                 goto done;
4046
4047 #endif
4048         if (ixgbe_set_fdir_queues(adapter))
4049                 goto done;
4050
4051         if (ixgbe_set_rss_queues(adapter))
4052                 goto done;
4053
4054         /* fallback to base case */
4055         adapter->num_rx_queues = 1;
4056         adapter->num_tx_queues = 1;
4057
4058 done:
4059         /* Notify the stack of the (possibly) reduced Tx Queue count. */
4060         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4061 }
4062
4063 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4064                                        int vectors)
4065 {
4066         int err, vector_threshold;
4067
4068         /* We'll want at least 3 (vector_threshold):
4069          * 1) TxQ[0] Cleanup
4070          * 2) RxQ[0] Cleanup
4071          * 3) Other (Link Status Change, etc.)
4072          * 4) TCP Timer (optional)
4073          */
4074         vector_threshold = MIN_MSIX_COUNT;
4075
4076         /* The more we get, the more we will assign to Tx/Rx Cleanup
4077          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4078          * Right now, we simply care about how many we'll get; we'll
4079          * set them up later while requesting irq's.
4080          */
4081         while (vectors >= vector_threshold) {
4082                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4083                                       vectors);
4084                 if (!err) /* Success in acquiring all requested vectors. */
4085                         break;
4086                 else if (err < 0)
4087                         vectors = 0; /* Nasty failure, quit now */
4088                 else /* err == number of vectors we should try again with */
4089                         vectors = err;
4090         }
4091
4092         if (vectors < vector_threshold) {
4093                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4094                  * This just means we'll go with either a single MSI
4095                  * vector or fall back to legacy interrupts.
4096                  */
4097                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4098                              "Unable to allocate MSI-X interrupts\n");
4099                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4100                 kfree(adapter->msix_entries);
4101                 adapter->msix_entries = NULL;
4102         } else {
4103                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4104                 /*
4105                  * Adjust for only the vectors we'll use, which is minimum
4106                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4107                  * vectors we were allocated.
4108                  */
4109                 adapter->num_msix_vectors = min(vectors,
4110                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4111         }
4112 }
4113
4114 /**
4115  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4116  * @adapter: board private structure to initialize
4117  *
4118  * Cache the descriptor ring offsets for RSS to the assigned rings.
4119  *
4120  **/
4121 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4122 {
4123         int i;
4124         bool ret = false;
4125
4126         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4127                 for (i = 0; i < adapter->num_rx_queues; i++)
4128                         adapter->rx_ring[i]->reg_idx = i;
4129                 for (i = 0; i < adapter->num_tx_queues; i++)
4130                         adapter->tx_ring[i]->reg_idx = i;
4131                 ret = true;
4132         } else {
4133                 ret = false;
4134         }
4135
4136         return ret;
4137 }
4138
4139 #ifdef CONFIG_IXGBE_DCB
4140 /**
4141  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4142  * @adapter: board private structure to initialize
4143  *
4144  * Cache the descriptor ring offsets for DCB to the assigned rings.
4145  *
4146  **/
4147 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4148 {
4149         int i;
4150         bool ret = false;
4151         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4152
4153         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4154                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4155                         /* the number of queues is assumed to be symmetric */
4156                         for (i = 0; i < dcb_i; i++) {
4157                                 adapter->rx_ring[i]->reg_idx = i << 3;
4158                                 adapter->tx_ring[i]->reg_idx = i << 2;
4159                         }
4160                         ret = true;
4161                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4162                         if (dcb_i == 8) {
4163                                 /*
4164                                  * Tx TC0 starts at: descriptor queue 0
4165                                  * Tx TC1 starts at: descriptor queue 32
4166                                  * Tx TC2 starts at: descriptor queue 64
4167                                  * Tx TC3 starts at: descriptor queue 80
4168                                  * Tx TC4 starts at: descriptor queue 96
4169                                  * Tx TC5 starts at: descriptor queue 104
4170                                  * Tx TC6 starts at: descriptor queue 112
4171                                  * Tx TC7 starts at: descriptor queue 120
4172                                  *
4173                                  * Rx TC0-TC7 are offset by 16 queues each
4174                                  */
4175                                 for (i = 0; i < 3; i++) {
4176                                         adapter->tx_ring[i]->reg_idx = i << 5;
4177                                         adapter->rx_ring[i]->reg_idx = i << 4;
4178                                 }
4179                                 for ( ; i < 5; i++) {
4180                                         adapter->tx_ring[i]->reg_idx =
4181                                                                  ((i + 2) << 4);
4182                                         adapter->rx_ring[i]->reg_idx = i << 4;
4183                                 }
4184                                 for ( ; i < dcb_i; i++) {
4185                                         adapter->tx_ring[i]->reg_idx =
4186                                                                  ((i + 8) << 3);
4187                                         adapter->rx_ring[i]->reg_idx = i << 4;
4188                                 }
4189
4190                                 ret = true;
4191                         } else if (dcb_i == 4) {
4192                                 /*
4193                                  * Tx TC0 starts at: descriptor queue 0
4194                                  * Tx TC1 starts at: descriptor queue 64
4195                                  * Tx TC2 starts at: descriptor queue 96
4196                                  * Tx TC3 starts at: descriptor queue 112
4197                                  *
4198                                  * Rx TC0-TC3 are offset by 32 queues each
4199                                  */
4200                                 adapter->tx_ring[0]->reg_idx = 0;
4201                                 adapter->tx_ring[1]->reg_idx = 64;
4202                                 adapter->tx_ring[2]->reg_idx = 96;
4203                                 adapter->tx_ring[3]->reg_idx = 112;
4204                                 for (i = 0 ; i < dcb_i; i++)
4205                                         adapter->rx_ring[i]->reg_idx = i << 5;
4206
4207                                 ret = true;
4208                         } else {
4209                                 ret = false;
4210                         }
4211                 } else {
4212                         ret = false;
4213                 }
4214         } else {
4215                 ret = false;
4216         }
4217
4218         return ret;
4219 }
4220 #endif
4221
4222 /**
4223  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4224  * @adapter: board private structure to initialize
4225  *
4226  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4227  *
4228  **/
4229 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4230 {
4231         int i;
4232         bool ret = false;
4233
4234         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4235             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4236              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4237                 for (i = 0; i < adapter->num_rx_queues; i++)
4238                         adapter->rx_ring[i]->reg_idx = i;
4239                 for (i = 0; i < adapter->num_tx_queues; i++)
4240                         adapter->tx_ring[i]->reg_idx = i;
4241                 ret = true;
4242         }
4243
4244         return ret;
4245 }
4246
4247 #ifdef IXGBE_FCOE
4248 /**
4249  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4250  * @adapter: board private structure to initialize
4251  *
4252  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4253  *
4254  */
4255 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4256 {
4257         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4258         bool ret = false;
4259         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4260
4261         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4262 #ifdef CONFIG_IXGBE_DCB
4263                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4264                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4265
4266                         ixgbe_cache_ring_dcb(adapter);
4267                         /* find out queues in TC for FCoE */
4268                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4269                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4270                         /*
4271                          * In 82599, the number of Tx queues for each traffic
4272                          * class for both 8-TC and 4-TC modes are:
4273                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4274                          * 8 TCs:  32  32  16  16   8   8   8   8
4275                          * 4 TCs:  64  64  32  32
4276                          * We have max 8 queues for FCoE, where 8 the is
4277                          * FCoE redirection table size. If TC for FCoE is
4278                          * less than or equal to TC3, we have enough queues
4279                          * to add max of 8 queues for FCoE, so we start FCoE
4280                          * tx descriptor from the next one, i.e., reg_idx + 1.
4281                          * If TC for FCoE is above TC3, implying 8 TC mode,
4282                          * and we need 8 for FCoE, we have to take all queues
4283                          * in that traffic class for FCoE.
4284                          */
4285                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4286                                 fcoe_tx_i--;
4287                 }
4288 #endif /* CONFIG_IXGBE_DCB */
4289                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4290                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4291                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4292                                 ixgbe_cache_ring_fdir(adapter);
4293                         else
4294                                 ixgbe_cache_ring_rss(adapter);
4295
4296                         fcoe_rx_i = f->mask;
4297                         fcoe_tx_i = f->mask;
4298                 }
4299                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4300                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4301                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4302                 }
4303                 ret = true;
4304         }
4305         return ret;
4306 }
4307
4308 #endif /* IXGBE_FCOE */
4309 /**
4310  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4311  * @adapter: board private structure to initialize
4312  *
4313  * SR-IOV doesn't use any descriptor rings but changes the default if
4314  * no other mapping is used.
4315  *
4316  */
4317 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4318 {
4319         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4320         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4321         if (adapter->num_vfs)
4322                 return true;
4323         else
4324                 return false;
4325 }
4326
4327 /**
4328  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4329  * @adapter: board private structure to initialize
4330  *
4331  * Once we know the feature-set enabled for the device, we'll cache
4332  * the register offset the descriptor ring is assigned to.
4333  *
4334  * Note, the order the various feature calls is important.  It must start with
4335  * the "most" features enabled at the same time, then trickle down to the
4336  * least amount of features turned on at once.
4337  **/
4338 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4339 {
4340         /* start with default case */
4341         adapter->rx_ring[0]->reg_idx = 0;
4342         adapter->tx_ring[0]->reg_idx = 0;
4343
4344         if (ixgbe_cache_ring_sriov(adapter))
4345                 return;
4346
4347 #ifdef IXGBE_FCOE
4348         if (ixgbe_cache_ring_fcoe(adapter))
4349                 return;
4350
4351 #endif /* IXGBE_FCOE */
4352 #ifdef CONFIG_IXGBE_DCB
4353         if (ixgbe_cache_ring_dcb(adapter))
4354                 return;
4355
4356 #endif
4357         if (ixgbe_cache_ring_fdir(adapter))
4358                 return;
4359
4360         if (ixgbe_cache_ring_rss(adapter))
4361                 return;
4362 }
4363
4364 /**
4365  * ixgbe_alloc_queues - Allocate memory for all rings
4366  * @adapter: board private structure to initialize
4367  *
4368  * We allocate one ring per queue at run-time since we don't know the
4369  * number of queues at compile-time.  The polling_netdev array is
4370  * intended for Multiqueue, but should work fine with a single queue.
4371  **/
4372 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4373 {
4374         int i;
4375         int orig_node = adapter->node;
4376
4377         for (i = 0; i < adapter->num_tx_queues; i++) {
4378                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4379                 if (orig_node == -1) {
4380                         int cur_node = next_online_node(adapter->node);
4381                         if (cur_node == MAX_NUMNODES)
4382                                 cur_node = first_online_node;
4383                         adapter->node = cur_node;
4384                 }
4385                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4386                                     adapter->node);
4387                 if (!ring)
4388                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4389                 if (!ring)
4390                         goto err_tx_ring_allocation;
4391                 ring->count = adapter->tx_ring_count;
4392                 ring->queue_index = i;
4393                 ring->numa_node = adapter->node;
4394
4395                 adapter->tx_ring[i] = ring;
4396         }
4397
4398         /* Restore the adapter's original node */
4399         adapter->node = orig_node;
4400
4401         for (i = 0; i < adapter->num_rx_queues; i++) {
4402                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4403                 if (orig_node == -1) {
4404                         int cur_node = next_online_node(adapter->node);
4405                         if (cur_node == MAX_NUMNODES)
4406                                 cur_node = first_online_node;
4407                         adapter->node = cur_node;
4408                 }
4409                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4410                                     adapter->node);
4411                 if (!ring)
4412                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4413                 if (!ring)
4414                         goto err_rx_ring_allocation;
4415                 ring->count = adapter->rx_ring_count;
4416                 ring->queue_index = i;
4417                 ring->numa_node = adapter->node;
4418
4419                 adapter->rx_ring[i] = ring;
4420         }
4421
4422         /* Restore the adapter's original node */
4423         adapter->node = orig_node;
4424
4425         ixgbe_cache_ring_register(adapter);
4426
4427         return 0;
4428
4429 err_rx_ring_allocation:
4430         for (i = 0; i < adapter->num_tx_queues; i++)
4431                 kfree(adapter->tx_ring[i]);
4432 err_tx_ring_allocation:
4433         return -ENOMEM;
4434 }
4435
4436 /**
4437  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4438  * @adapter: board private structure to initialize
4439  *
4440  * Attempt to configure the interrupts using the best available
4441  * capabilities of the hardware and the kernel.
4442  **/
4443 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4444 {
4445         struct ixgbe_hw *hw = &adapter->hw;
4446         int err = 0;
4447         int vector, v_budget;
4448
4449         /*
4450          * It's easy to be greedy for MSI-X vectors, but it really
4451          * doesn't do us much good if we have a lot more vectors
4452          * than CPU's.  So let's be conservative and only ask for
4453          * (roughly) the same number of vectors as there are CPU's.
4454          */
4455         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4456                        (int)num_online_cpus()) + NON_Q_VECTORS;
4457
4458         /*
4459          * At the same time, hardware can only support a maximum of
4460          * hw.mac->max_msix_vectors vectors.  With features
4461          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4462          * descriptor queues supported by our device.  Thus, we cap it off in
4463          * those rare cases where the cpu count also exceeds our vector limit.
4464          */
4465         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4466
4467         /* A failure in MSI-X entry allocation isn't fatal, but it does
4468          * mean we disable MSI-X capabilities of the adapter. */
4469         adapter->msix_entries = kcalloc(v_budget,
4470                                         sizeof(struct msix_entry), GFP_KERNEL);
4471         if (adapter->msix_entries) {
4472                 for (vector = 0; vector < v_budget; vector++)
4473                         adapter->msix_entries[vector].entry = vector;
4474
4475                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4476
4477                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4478                         goto out;
4479         }
4480
4481         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4482         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4483         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4484         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4485         adapter->atr_sample_rate = 0;
4486         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4487                 ixgbe_disable_sriov(adapter);
4488
4489         ixgbe_set_num_queues(adapter);
4490
4491         err = pci_enable_msi(adapter->pdev);
4492         if (!err) {
4493                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4494         } else {
4495                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4496                              "Unable to allocate MSI interrupt, "
4497                              "falling back to legacy.  Error: %d\n", err);
4498                 /* reset err */
4499                 err = 0;
4500         }
4501
4502 out:
4503         return err;
4504 }
4505
4506 /**
4507  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4508  * @adapter: board private structure to initialize
4509  *
4510  * We allocate one q_vector per queue interrupt.  If allocation fails we
4511  * return -ENOMEM.
4512  **/
4513 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4514 {
4515         int q_idx, num_q_vectors;
4516         struct ixgbe_q_vector *q_vector;
4517         int napi_vectors;
4518         int (*poll)(struct napi_struct *, int);
4519
4520         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4521                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4522                 napi_vectors = adapter->num_rx_queues;
4523                 poll = &ixgbe_clean_rxtx_many;
4524         } else {
4525                 num_q_vectors = 1;
4526                 napi_vectors = 1;
4527                 poll = &ixgbe_poll;
4528         }
4529
4530         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4531                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4532                                         GFP_KERNEL, adapter->node);
4533                 if (!q_vector)
4534                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4535                                            GFP_KERNEL);
4536                 if (!q_vector)
4537                         goto err_out;
4538                 q_vector->adapter = adapter;
4539                 if (q_vector->txr_count && !q_vector->rxr_count)
4540                         q_vector->eitr = adapter->tx_eitr_param;
4541                 else
4542                         q_vector->eitr = adapter->rx_eitr_param;
4543                 q_vector->v_idx = q_idx;
4544                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4545                 adapter->q_vector[q_idx] = q_vector;
4546         }
4547
4548         return 0;
4549
4550 err_out:
4551         while (q_idx) {
4552                 q_idx--;
4553                 q_vector = adapter->q_vector[q_idx];
4554                 netif_napi_del(&q_vector->napi);
4555                 kfree(q_vector);
4556                 adapter->q_vector[q_idx] = NULL;
4557         }
4558         return -ENOMEM;
4559 }
4560
4561 /**
4562  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4563  * @adapter: board private structure to initialize
4564  *
4565  * This function frees the memory allocated to the q_vectors.  In addition if
4566  * NAPI is enabled it will delete any references to the NAPI struct prior
4567  * to freeing the q_vector.
4568  **/
4569 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4570 {
4571         int q_idx, num_q_vectors;
4572
4573         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4574                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4575         else
4576                 num_q_vectors = 1;
4577
4578         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4579                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4580                 adapter->q_vector[q_idx] = NULL;
4581                 netif_napi_del(&q_vector->napi);
4582                 kfree(q_vector);
4583         }
4584 }
4585
4586 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4587 {
4588         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4589                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4590                 pci_disable_msix(adapter->pdev);
4591                 kfree(adapter->msix_entries);
4592                 adapter->msix_entries = NULL;
4593         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4594                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4595                 pci_disable_msi(adapter->pdev);
4596         }
4597 }
4598
4599 /**
4600  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4601  * @adapter: board private structure to initialize
4602  *
4603  * We determine which interrupt scheme to use based on...
4604  * - Kernel support (MSI, MSI-X)
4605  *   - which can be user-defined (via MODULE_PARAM)
4606  * - Hardware queue count (num_*_queues)
4607  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4608  **/
4609 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4610 {
4611         int err;
4612
4613         /* Number of supported queues */
4614         ixgbe_set_num_queues(adapter);
4615
4616         err = ixgbe_set_interrupt_capability(adapter);
4617         if (err) {
4618                 e_dev_err("Unable to setup interrupt capabilities\n");
4619                 goto err_set_interrupt;
4620         }
4621
4622         err = ixgbe_alloc_q_vectors(adapter);
4623         if (err) {
4624                 e_dev_err("Unable to allocate memory for queue vectors\n");
4625                 goto err_alloc_q_vectors;
4626         }
4627
4628         err = ixgbe_alloc_queues(adapter);
4629         if (err) {
4630                 e_dev_err("Unable to allocate memory for queues\n");
4631                 goto err_alloc_queues;
4632         }
4633
4634         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4635                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4636                    adapter->num_rx_queues, adapter->num_tx_queues);
4637
4638         set_bit(__IXGBE_DOWN, &adapter->state);
4639
4640         return 0;
4641
4642 err_alloc_queues:
4643         ixgbe_free_q_vectors(adapter);
4644 err_alloc_q_vectors:
4645         ixgbe_reset_interrupt_capability(adapter);
4646 err_set_interrupt:
4647         return err;
4648 }
4649
4650 /**
4651  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4652  * @adapter: board private structure to clear interrupt scheme on
4653  *
4654  * We go through and clear interrupt specific resources and reset the structure
4655  * to pre-load conditions
4656  **/
4657 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4658 {
4659         int i;
4660
4661         for (i = 0; i < adapter->num_tx_queues; i++) {
4662                 kfree(adapter->tx_ring[i]);
4663                 adapter->tx_ring[i] = NULL;
4664         }
4665         for (i = 0; i < adapter->num_rx_queues; i++) {
4666                 kfree(adapter->rx_ring[i]);
4667                 adapter->rx_ring[i] = NULL;
4668         }
4669
4670         ixgbe_free_q_vectors(adapter);
4671         ixgbe_reset_interrupt_capability(adapter);
4672 }
4673
4674 /**
4675  * ixgbe_sfp_timer - worker thread to find a missing module
4676  * @data: pointer to our adapter struct
4677  **/
4678 static void ixgbe_sfp_timer(unsigned long data)
4679 {
4680         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4681
4682         /*
4683          * Do the sfp_timer outside of interrupt context due to the
4684          * delays that sfp+ detection requires
4685          */
4686         schedule_work(&adapter->sfp_task);
4687 }
4688
4689 /**
4690  * ixgbe_sfp_task - worker thread to find a missing module
4691  * @work: pointer to work_struct containing our data
4692  **/
4693 static void ixgbe_sfp_task(struct work_struct *work)
4694 {
4695         struct ixgbe_adapter *adapter = container_of(work,
4696                                                      struct ixgbe_adapter,
4697                                                      sfp_task);
4698         struct ixgbe_hw *hw = &adapter->hw;
4699
4700         if ((hw->phy.type == ixgbe_phy_nl) &&
4701             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4702                 s32 ret = hw->phy.ops.identify_sfp(hw);
4703                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4704                         goto reschedule;
4705                 ret = hw->phy.ops.reset(hw);
4706                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4707                         e_dev_err("failed to initialize because an unsupported "
4708                                   "SFP+ module type was detected.\n");
4709                         e_dev_err("Reload the driver after installing a "
4710                                   "supported module.\n");
4711                         unregister_netdev(adapter->netdev);
4712                 } else {
4713                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4714                 }
4715                 /* don't need this routine any more */
4716                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4717         }
4718         return;
4719 reschedule:
4720         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4721                 mod_timer(&adapter->sfp_timer,
4722                           round_jiffies(jiffies + (2 * HZ)));
4723 }
4724
4725 /**
4726  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4727  * @adapter: board private structure to initialize
4728  *
4729  * ixgbe_sw_init initializes the Adapter private data structure.
4730  * Fields are initialized based on PCI device information and
4731  * OS network device settings (MTU size).
4732  **/
4733 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4734 {
4735         struct ixgbe_hw *hw = &adapter->hw;
4736         struct pci_dev *pdev = adapter->pdev;
4737         struct net_device *dev = adapter->netdev;
4738         unsigned int rss;
4739 #ifdef CONFIG_IXGBE_DCB
4740         int j;
4741         struct tc_configuration *tc;
4742 #endif
4743
4744         /* PCI config space info */
4745
4746         hw->vendor_id = pdev->vendor;
4747         hw->device_id = pdev->device;
4748         hw->revision_id = pdev->revision;
4749         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4750         hw->subsystem_device_id = pdev->subsystem_device;
4751
4752         /* Set capability flags */
4753         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4754         adapter->ring_feature[RING_F_RSS].indices = rss;
4755         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4756         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4757         if (hw->mac.type == ixgbe_mac_82598EB) {
4758                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4759                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4760                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4761         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4762                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4763                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4764                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4765                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4766                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4767                 if (dev->features & NETIF_F_NTUPLE) {
4768                         /* Flow Director perfect filter enabled */
4769                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4770                         adapter->atr_sample_rate = 0;
4771                         spin_lock_init(&adapter->fdir_perfect_lock);
4772                 } else {
4773                         /* Flow Director hash filters enabled */
4774                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4775                         adapter->atr_sample_rate = 20;
4776                 }
4777                 adapter->ring_feature[RING_F_FDIR].indices =
4778                                                          IXGBE_MAX_FDIR_INDICES;
4779                 adapter->fdir_pballoc = 0;
4780 #ifdef IXGBE_FCOE
4781                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4782                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4783                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4784 #ifdef CONFIG_IXGBE_DCB
4785                 /* Default traffic class to use for FCoE */
4786                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4787                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4788 #endif
4789 #endif /* IXGBE_FCOE */
4790         }
4791
4792 #ifdef CONFIG_IXGBE_DCB
4793         /* Configure DCB traffic classes */
4794         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4795                 tc = &adapter->dcb_cfg.tc_config[j];
4796                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4797                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4798                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4799                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4800                 tc->dcb_pfc = pfc_disabled;
4801         }
4802         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4803         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4804         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4805         adapter->dcb_cfg.pfc_mode_enable = false;
4806         adapter->dcb_cfg.round_robin_enable = false;
4807         adapter->dcb_set_bitmap = 0x00;
4808         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4809                            adapter->ring_feature[RING_F_DCB].indices);
4810
4811 #endif
4812
4813         /* default flow control settings */
4814         hw->fc.requested_mode = ixgbe_fc_full;
4815         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4816 #ifdef CONFIG_DCB
4817         adapter->last_lfc_mode = hw->fc.current_mode;
4818 #endif
4819         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4820         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4821         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4822         hw->fc.send_xon = true;
4823         hw->fc.disable_fc_autoneg = false;
4824
4825         /* enable itr by default in dynamic mode */
4826         adapter->rx_itr_setting = 1;
4827         adapter->rx_eitr_param = 20000;
4828         adapter->tx_itr_setting = 1;
4829         adapter->tx_eitr_param = 10000;
4830
4831         /* set defaults for eitr in MegaBytes */
4832         adapter->eitr_low = 10;
4833         adapter->eitr_high = 20;
4834
4835         /* set default ring sizes */
4836         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4837         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4838
4839         /* initialize eeprom parameters */
4840         if (ixgbe_init_eeprom_params_generic(hw)) {
4841                 e_dev_err("EEPROM initialization failed\n");
4842                 return -EIO;
4843         }
4844
4845         /* enable rx csum by default */
4846         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4847
4848         /* get assigned NUMA node */
4849         adapter->node = dev_to_node(&pdev->dev);
4850
4851         set_bit(__IXGBE_DOWN, &adapter->state);
4852
4853         return 0;
4854 }
4855
4856 /**
4857  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4858  * @adapter: board private structure
4859  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4860  *
4861  * Return 0 on success, negative on failure
4862  **/
4863 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4864                              struct ixgbe_ring *tx_ring)
4865 {
4866         struct pci_dev *pdev = adapter->pdev;
4867         int size;
4868
4869         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4870         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4871         if (!tx_ring->tx_buffer_info)
4872                 tx_ring->tx_buffer_info = vmalloc(size);
4873         if (!tx_ring->tx_buffer_info)
4874                 goto err;
4875         memset(tx_ring->tx_buffer_info, 0, size);
4876
4877         /* round up to nearest 4K */
4878         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4879         tx_ring->size = ALIGN(tx_ring->size, 4096);
4880
4881         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4882                                            &tx_ring->dma, GFP_KERNEL);
4883         if (!tx_ring->desc)
4884                 goto err;
4885
4886         tx_ring->next_to_use = 0;
4887         tx_ring->next_to_clean = 0;
4888         tx_ring->work_limit = tx_ring->count;
4889         return 0;
4890
4891 err:
4892         vfree(tx_ring->tx_buffer_info);
4893         tx_ring->tx_buffer_info = NULL;
4894         e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4895         return -ENOMEM;
4896 }
4897
4898 /**
4899  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4900  * @adapter: board private structure
4901  *
4902  * If this function returns with an error, then it's possible one or
4903  * more of the rings is populated (while the rest are not).  It is the
4904  * callers duty to clean those orphaned rings.
4905  *
4906  * Return 0 on success, negative on failure
4907  **/
4908 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4909 {
4910         int i, err = 0;
4911
4912         for (i = 0; i < adapter->num_tx_queues; i++) {
4913                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4914                 if (!err)
4915                         continue;
4916                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4917                 break;
4918         }
4919
4920         return err;
4921 }
4922
4923 /**
4924  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4925  * @adapter: board private structure
4926  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4927  *
4928  * Returns 0 on success, negative on failure
4929  **/
4930 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4931                              struct ixgbe_ring *rx_ring)
4932 {
4933         struct pci_dev *pdev = adapter->pdev;
4934         int size;
4935
4936         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4937         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4938         if (!rx_ring->rx_buffer_info)
4939                 rx_ring->rx_buffer_info = vmalloc(size);
4940         if (!rx_ring->rx_buffer_info) {
4941                 e_err(probe, "vmalloc allocation failed for the Rx "
4942                       "descriptor ring\n");
4943                 goto alloc_failed;
4944         }
4945         memset(rx_ring->rx_buffer_info, 0, size);
4946
4947         /* Round up to nearest 4K */
4948         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4949         rx_ring->size = ALIGN(rx_ring->size, 4096);
4950
4951         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4952                                            &rx_ring->dma, GFP_KERNEL);
4953
4954         if (!rx_ring->desc) {
4955                 e_err(probe, "Memory allocation failed for the Rx "
4956                       "descriptor ring\n");
4957                 vfree(rx_ring->rx_buffer_info);
4958                 goto alloc_failed;
4959         }
4960
4961         rx_ring->next_to_clean = 0;
4962         rx_ring->next_to_use = 0;
4963
4964         return 0;
4965
4966 alloc_failed:
4967         return -ENOMEM;
4968 }
4969
4970 /**
4971  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4972  * @adapter: board private structure
4973  *
4974  * If this function returns with an error, then it's possible one or
4975  * more of the rings is populated (while the rest are not).  It is the
4976  * callers duty to clean those orphaned rings.
4977  *
4978  * Return 0 on success, negative on failure
4979  **/
4980
4981 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4982 {
4983         int i, err = 0;
4984
4985         for (i = 0; i < adapter->num_rx_queues; i++) {
4986                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4987                 if (!err)
4988                         continue;
4989                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4990                 break;
4991         }
4992
4993         return err;
4994 }
4995
4996 /**
4997  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4998  * @adapter: board private structure
4999  * @tx_ring: Tx descriptor ring for a specific queue
5000  *
5001  * Free all transmit software resources
5002  **/
5003 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5004                              struct ixgbe_ring *tx_ring)
5005 {
5006         struct pci_dev *pdev = adapter->pdev;
5007
5008         ixgbe_clean_tx_ring(adapter, tx_ring);
5009
5010         vfree(tx_ring->tx_buffer_info);
5011         tx_ring->tx_buffer_info = NULL;
5012
5013         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5014                           tx_ring->dma);
5015
5016         tx_ring->desc = NULL;
5017 }
5018
5019 /**
5020  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5021  * @adapter: board private structure
5022  *
5023  * Free all transmit software resources
5024  **/
5025 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5026 {
5027         int i;
5028
5029         for (i = 0; i < adapter->num_tx_queues; i++)
5030                 if (adapter->tx_ring[i]->desc)
5031                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5032 }
5033
5034 /**
5035  * ixgbe_free_rx_resources - Free Rx Resources
5036  * @adapter: board private structure
5037  * @rx_ring: ring to clean the resources from
5038  *
5039  * Free all receive software resources
5040  **/
5041 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5042                              struct ixgbe_ring *rx_ring)
5043 {
5044         struct pci_dev *pdev = adapter->pdev;
5045
5046         ixgbe_clean_rx_ring(adapter, rx_ring);
5047
5048         vfree(rx_ring->rx_buffer_info);
5049         rx_ring->rx_buffer_info = NULL;
5050
5051         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5052                           rx_ring->dma);
5053
5054         rx_ring->desc = NULL;
5055 }
5056
5057 /**
5058  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5059  * @adapter: board private structure
5060  *
5061  * Free all receive software resources
5062  **/
5063 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5064 {
5065         int i;
5066
5067         for (i = 0; i < adapter->num_rx_queues; i++)
5068                 if (adapter->rx_ring[i]->desc)
5069                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5070 }
5071
5072 /**
5073  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5074  * @netdev: network interface device structure
5075  * @new_mtu: new value for maximum frame size
5076  *
5077  * Returns 0 on success, negative on failure
5078  **/
5079 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5080 {
5081         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5082         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5083
5084         /* MTU < 68 is an error and causes problems on some kernels */
5085         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5086                 return -EINVAL;
5087
5088         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5089         /* must set new MTU before calling down or up */
5090         netdev->mtu = new_mtu;
5091
5092         if (netif_running(netdev))
5093                 ixgbe_reinit_locked(adapter);
5094
5095         return 0;
5096 }
5097
5098 /**
5099  * ixgbe_open - Called when a network interface is made active
5100  * @netdev: network interface device structure
5101  *
5102  * Returns 0 on success, negative value on failure
5103  *
5104  * The open entry point is called when a network interface is made
5105  * active by the system (IFF_UP).  At this point all resources needed
5106  * for transmit and receive operations are allocated, the interrupt
5107  * handler is registered with the OS, the watchdog timer is started,
5108  * and the stack is notified that the interface is ready.
5109  **/
5110 static int ixgbe_open(struct net_device *netdev)
5111 {
5112         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5113         int err;
5114
5115         /* disallow open during test */
5116         if (test_bit(__IXGBE_TESTING, &adapter->state))
5117                 return -EBUSY;
5118
5119         netif_carrier_off(netdev);
5120
5121         /* allocate transmit descriptors */
5122         err = ixgbe_setup_all_tx_resources(adapter);
5123         if (err)
5124                 goto err_setup_tx;
5125
5126         /* allocate receive descriptors */
5127         err = ixgbe_setup_all_rx_resources(adapter);
5128         if (err)
5129                 goto err_setup_rx;
5130
5131         ixgbe_configure(adapter);
5132
5133         err = ixgbe_request_irq(adapter);
5134         if (err)
5135                 goto err_req_irq;
5136
5137         err = ixgbe_up_complete(adapter);
5138         if (err)
5139                 goto err_up;
5140
5141         netif_tx_start_all_queues(netdev);
5142
5143         return 0;
5144
5145 err_up:
5146         ixgbe_release_hw_control(adapter);
5147         ixgbe_free_irq(adapter);
5148 err_req_irq:
5149 err_setup_rx:
5150         ixgbe_free_all_rx_resources(adapter);
5151 err_setup_tx:
5152         ixgbe_free_all_tx_resources(adapter);
5153         ixgbe_reset(adapter);
5154
5155         return err;
5156 }
5157
5158 /**
5159  * ixgbe_close - Disables a network interface
5160  * @netdev: network interface device structure
5161  *
5162  * Returns 0, this is not allowed to fail
5163  *
5164  * The close entry point is called when an interface is de-activated
5165  * by the OS.  The hardware is still under the drivers control, but
5166  * needs to be disabled.  A global MAC reset is issued to stop the
5167  * hardware, and all transmit and receive resources are freed.
5168  **/
5169 static int ixgbe_close(struct net_device *netdev)
5170 {
5171         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5172
5173         ixgbe_down(adapter);
5174         ixgbe_free_irq(adapter);
5175
5176         ixgbe_free_all_tx_resources(adapter);
5177         ixgbe_free_all_rx_resources(adapter);
5178
5179         ixgbe_release_hw_control(adapter);
5180
5181         return 0;
5182 }
5183
5184 #ifdef CONFIG_PM
5185 static int ixgbe_resume(struct pci_dev *pdev)
5186 {
5187         struct net_device *netdev = pci_get_drvdata(pdev);
5188         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5189         u32 err;
5190
5191         pci_set_power_state(pdev, PCI_D0);
5192         pci_restore_state(pdev);
5193         /*
5194          * pci_restore_state clears dev->state_saved so call
5195          * pci_save_state to restore it.
5196          */
5197         pci_save_state(pdev);
5198
5199         err = pci_enable_device_mem(pdev);
5200         if (err) {
5201                 e_dev_err("Cannot enable PCI device from suspend\n");
5202                 return err;
5203         }
5204         pci_set_master(pdev);
5205
5206         pci_wake_from_d3(pdev, false);
5207
5208         err = ixgbe_init_interrupt_scheme(adapter);
5209         if (err) {
5210                 e_dev_err("Cannot initialize interrupts for device\n");
5211                 return err;
5212         }
5213
5214         ixgbe_reset(adapter);
5215
5216         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5217
5218         if (netif_running(netdev)) {
5219                 err = ixgbe_open(adapter->netdev);
5220                 if (err)
5221                         return err;
5222         }
5223
5224         netif_device_attach(netdev);
5225
5226         return 0;
5227 }
5228 #endif /* CONFIG_PM */
5229
5230 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5231 {
5232         struct net_device *netdev = pci_get_drvdata(pdev);
5233         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5234         struct ixgbe_hw *hw = &adapter->hw;
5235         u32 ctrl, fctrl;
5236         u32 wufc = adapter->wol;
5237 #ifdef CONFIG_PM
5238         int retval = 0;
5239 #endif
5240
5241         netif_device_detach(netdev);
5242
5243         if (netif_running(netdev)) {
5244                 ixgbe_down(adapter);
5245                 ixgbe_free_irq(adapter);
5246                 ixgbe_free_all_tx_resources(adapter);
5247                 ixgbe_free_all_rx_resources(adapter);
5248         }
5249
5250 #ifdef CONFIG_PM
5251         retval = pci_save_state(pdev);
5252         if (retval)
5253                 return retval;
5254
5255 #endif
5256         if (wufc) {
5257                 ixgbe_set_rx_mode(netdev);
5258
5259                 /* turn on all-multi mode if wake on multicast is enabled */
5260                 if (wufc & IXGBE_WUFC_MC) {
5261                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5262                         fctrl |= IXGBE_FCTRL_MPE;
5263                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5264                 }
5265
5266                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5267                 ctrl |= IXGBE_CTRL_GIO_DIS;
5268                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5269
5270                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5271         } else {
5272                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5273                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5274         }
5275
5276         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5277                 pci_wake_from_d3(pdev, true);
5278         else
5279                 pci_wake_from_d3(pdev, false);
5280
5281         *enable_wake = !!wufc;
5282
5283         ixgbe_clear_interrupt_scheme(adapter);
5284
5285         ixgbe_release_hw_control(adapter);
5286
5287         pci_disable_device(pdev);
5288
5289         return 0;
5290 }
5291
5292 #ifdef CONFIG_PM
5293 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5294 {
5295         int retval;
5296         bool wake;
5297
5298         retval = __ixgbe_shutdown(pdev, &wake);
5299         if (retval)
5300                 return retval;
5301
5302         if (wake) {
5303                 pci_prepare_to_sleep(pdev);
5304         } else {
5305                 pci_wake_from_d3(pdev, false);
5306                 pci_set_power_state(pdev, PCI_D3hot);
5307         }
5308
5309         return 0;
5310 }
5311 #endif /* CONFIG_PM */
5312
5313 static void ixgbe_shutdown(struct pci_dev *pdev)
5314 {
5315         bool wake;
5316
5317         __ixgbe_shutdown(pdev, &wake);
5318
5319         if (system_state == SYSTEM_POWER_OFF) {
5320                 pci_wake_from_d3(pdev, wake);
5321                 pci_set_power_state(pdev, PCI_D3hot);
5322         }
5323 }
5324
5325 /**
5326  * ixgbe_update_stats - Update the board statistics counters.
5327  * @adapter: board private structure
5328  **/
5329 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5330 {
5331         struct net_device *netdev = adapter->netdev;
5332         struct ixgbe_hw *hw = &adapter->hw;
5333         u64 total_mpc = 0;
5334         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5335         u64 non_eop_descs = 0, restart_queue = 0;
5336
5337         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5338             test_bit(__IXGBE_RESETTING, &adapter->state))
5339                 return;
5340
5341         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5342                 u64 rsc_count = 0;
5343                 u64 rsc_flush = 0;
5344                 for (i = 0; i < 16; i++)
5345                         adapter->hw_rx_no_dma_resources +=
5346                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5347                 for (i = 0; i < adapter->num_rx_queues; i++) {
5348                         rsc_count += adapter->rx_ring[i]->rsc_count;
5349                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5350                 }
5351                 adapter->rsc_total_count = rsc_count;
5352                 adapter->rsc_total_flush = rsc_flush;
5353         }
5354
5355         /* gather some stats to the adapter struct that are per queue */
5356         for (i = 0; i < adapter->num_tx_queues; i++)
5357                 restart_queue += adapter->tx_ring[i]->restart_queue;
5358         adapter->restart_queue = restart_queue;
5359
5360         for (i = 0; i < adapter->num_rx_queues; i++)
5361                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5362         adapter->non_eop_descs = non_eop_descs;
5363
5364         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5365         for (i = 0; i < 8; i++) {
5366                 /* for packet buffers not used, the register should read 0 */
5367                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5368                 missed_rx += mpc;
5369                 adapter->stats.mpc[i] += mpc;
5370                 total_mpc += adapter->stats.mpc[i];
5371                 if (hw->mac.type == ixgbe_mac_82598EB)
5372                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5373                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5374                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5375                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5376                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5377                 if (hw->mac.type == ixgbe_mac_82599EB) {
5378                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5379                                                             IXGBE_PXONRXCNT(i));
5380                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5381                                                            IXGBE_PXOFFRXCNT(i));
5382                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5383                 } else {
5384                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5385                                                               IXGBE_PXONRXC(i));
5386                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5387                                                              IXGBE_PXOFFRXC(i));
5388                 }
5389                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5390                                                             IXGBE_PXONTXC(i));
5391                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5392                                                              IXGBE_PXOFFTXC(i));
5393         }
5394         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5395         /* work around hardware counting issue */
5396         adapter->stats.gprc -= missed_rx;
5397
5398         /* 82598 hardware only has a 32 bit counter in the high register */
5399         if (hw->mac.type == ixgbe_mac_82599EB) {
5400                 u64 tmp;
5401                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5402                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5403                 adapter->stats.gorc += (tmp << 32);
5404                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5405                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5406                 adapter->stats.gotc += (tmp << 32);
5407                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5408                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5409                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5410                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5411                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5412                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5413 #ifdef IXGBE_FCOE
5414                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5415                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5416                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5417                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5418                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5419                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5420 #endif /* IXGBE_FCOE */
5421         } else {
5422                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5423                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5424                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5425                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5426                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5427         }
5428         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5429         adapter->stats.bprc += bprc;
5430         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5431         if (hw->mac.type == ixgbe_mac_82598EB)
5432                 adapter->stats.mprc -= bprc;
5433         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5434         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5435         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5436         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5437         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5438         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5439         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5440         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5441         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5442         adapter->stats.lxontxc += lxon;
5443         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5444         adapter->stats.lxofftxc += lxoff;
5445         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5446         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5447         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5448         /*
5449          * 82598 errata - tx of flow control packets is included in tx counters
5450          */
5451         xon_off_tot = lxon + lxoff;
5452         adapter->stats.gptc -= xon_off_tot;
5453         adapter->stats.mptc -= xon_off_tot;
5454         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5455         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5456         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5457         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5458         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5459         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5460         adapter->stats.ptc64 -= xon_off_tot;
5461         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5462         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5463         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5464         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5465         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5466         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5467
5468         /* Fill out the OS statistics structure */
5469         netdev->stats.multicast = adapter->stats.mprc;
5470
5471         /* Rx Errors */
5472         netdev->stats.rx_errors = adapter->stats.crcerrs +
5473                                        adapter->stats.rlec;
5474         netdev->stats.rx_dropped = 0;
5475         netdev->stats.rx_length_errors = adapter->stats.rlec;
5476         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5477         netdev->stats.rx_missed_errors = total_mpc;
5478 }
5479
5480 /**
5481  * ixgbe_watchdog - Timer Call-back
5482  * @data: pointer to adapter cast into an unsigned long
5483  **/
5484 static void ixgbe_watchdog(unsigned long data)
5485 {
5486         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5487         struct ixgbe_hw *hw = &adapter->hw;
5488         u64 eics = 0;
5489         int i;
5490
5491         /*
5492          *  Do the watchdog outside of interrupt context due to the lovely
5493          * delays that some of the newer hardware requires
5494          */
5495
5496         if (test_bit(__IXGBE_DOWN, &adapter->state))
5497                 goto watchdog_short_circuit;
5498
5499         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5500                 /*
5501                  * for legacy and MSI interrupts don't set any bits
5502                  * that are enabled for EIAM, because this operation
5503                  * would set *both* EIMS and EICS for any bit in EIAM
5504                  */
5505                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5506                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5507                 goto watchdog_reschedule;
5508         }
5509
5510         /* get one bit for every active tx/rx interrupt vector */
5511         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5512                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5513                 if (qv->rxr_count || qv->txr_count)
5514                         eics |= ((u64)1 << i);
5515         }
5516
5517         /* Cause software interrupt to ensure rx rings are cleaned */
5518         ixgbe_irq_rearm_queues(adapter, eics);
5519
5520 watchdog_reschedule:
5521         /* Reset the timer */
5522         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5523
5524 watchdog_short_circuit:
5525         schedule_work(&adapter->watchdog_task);
5526 }
5527
5528 /**
5529  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5530  * @work: pointer to work_struct containing our data
5531  **/
5532 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5533 {
5534         struct ixgbe_adapter *adapter = container_of(work,
5535                                                      struct ixgbe_adapter,
5536                                                      multispeed_fiber_task);
5537         struct ixgbe_hw *hw = &adapter->hw;
5538         u32 autoneg;
5539         bool negotiation;
5540
5541         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5542         autoneg = hw->phy.autoneg_advertised;
5543         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5544                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5545         hw->mac.autotry_restart = false;
5546         if (hw->mac.ops.setup_link)
5547                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5548         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5549         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5550 }
5551
5552 /**
5553  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5554  * @work: pointer to work_struct containing our data
5555  **/
5556 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5557 {
5558         struct ixgbe_adapter *adapter = container_of(work,
5559                                                      struct ixgbe_adapter,
5560                                                      sfp_config_module_task);
5561         struct ixgbe_hw *hw = &adapter->hw;
5562         u32 err;
5563
5564         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5565
5566         /* Time for electrical oscillations to settle down */
5567         msleep(100);
5568         err = hw->phy.ops.identify_sfp(hw);
5569
5570         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5571                 e_dev_err("failed to initialize because an unsupported SFP+ "
5572                           "module type was detected.\n");
5573                 e_dev_err("Reload the driver after installing a supported "
5574                           "module.\n");
5575                 unregister_netdev(adapter->netdev);
5576                 return;
5577         }
5578         hw->mac.ops.setup_sfp(hw);
5579
5580         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5581                 /* This will also work for DA Twinax connections */
5582                 schedule_work(&adapter->multispeed_fiber_task);
5583         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5584 }
5585
5586 /**
5587  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5588  * @work: pointer to work_struct containing our data
5589  **/
5590 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5591 {
5592         struct ixgbe_adapter *adapter = container_of(work,
5593                                                      struct ixgbe_adapter,
5594                                                      fdir_reinit_task);
5595         struct ixgbe_hw *hw = &adapter->hw;
5596         int i;
5597
5598         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5599                 for (i = 0; i < adapter->num_tx_queues; i++)
5600                         set_bit(__IXGBE_FDIR_INIT_DONE,
5601                                 &(adapter->tx_ring[i]->reinit_state));
5602         } else {
5603                 e_err(probe, "failed to finish FDIR re-initialization, "
5604                       "ignored adding FDIR ATR filters\n");
5605         }
5606         /* Done FDIR Re-initialization, enable transmits */
5607         netif_tx_start_all_queues(adapter->netdev);
5608 }
5609
5610 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5611
5612 /**
5613  * ixgbe_watchdog_task - worker thread to bring link up
5614  * @work: pointer to work_struct containing our data
5615  **/
5616 static void ixgbe_watchdog_task(struct work_struct *work)
5617 {
5618         struct ixgbe_adapter *adapter = container_of(work,
5619                                                      struct ixgbe_adapter,
5620                                                      watchdog_task);
5621         struct net_device *netdev = adapter->netdev;
5622         struct ixgbe_hw *hw = &adapter->hw;
5623         u32 link_speed;
5624         bool link_up;
5625         int i;
5626         struct ixgbe_ring *tx_ring;
5627         int some_tx_pending = 0;
5628
5629         mutex_lock(&ixgbe_watchdog_lock);
5630
5631         link_up = adapter->link_up;
5632         link_speed = adapter->link_speed;
5633
5634         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5635                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5636                 if (link_up) {
5637 #ifdef CONFIG_DCB
5638                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5639                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5640                                         hw->mac.ops.fc_enable(hw, i);
5641                         } else {
5642                                 hw->mac.ops.fc_enable(hw, 0);
5643                         }
5644 #else
5645                         hw->mac.ops.fc_enable(hw, 0);
5646 #endif
5647                 }
5648
5649                 if (link_up ||
5650                     time_after(jiffies, (adapter->link_check_timeout +
5651                                          IXGBE_TRY_LINK_TIMEOUT))) {
5652                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5653                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5654                 }
5655                 adapter->link_up = link_up;
5656                 adapter->link_speed = link_speed;
5657         }
5658
5659         if (link_up) {
5660                 if (!netif_carrier_ok(netdev)) {
5661                         bool flow_rx, flow_tx;
5662
5663                         if (hw->mac.type == ixgbe_mac_82599EB) {
5664                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5665                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5666                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5667                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5668                         } else {
5669                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5670                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5671                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5672                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5673                         }
5674
5675                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5676                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5677                                "10 Gbps" :
5678                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5679                                "1 Gbps" : "unknown speed")),
5680                                ((flow_rx && flow_tx) ? "RX/TX" :
5681                                (flow_rx ? "RX" :
5682                                (flow_tx ? "TX" : "None"))));
5683
5684                         netif_carrier_on(netdev);
5685                 } else {
5686                         /* Force detection of hung controller */
5687                         adapter->detect_tx_hung = true;
5688                 }
5689         } else {
5690                 adapter->link_up = false;
5691                 adapter->link_speed = 0;
5692                 if (netif_carrier_ok(netdev)) {
5693                         e_info(drv, "NIC Link is Down\n");
5694                         netif_carrier_off(netdev);
5695                 }
5696         }
5697
5698         if (!netif_carrier_ok(netdev)) {
5699                 for (i = 0; i < adapter->num_tx_queues; i++) {
5700                         tx_ring = adapter->tx_ring[i];
5701                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5702                                 some_tx_pending = 1;
5703                                 break;
5704                         }
5705                 }
5706
5707                 if (some_tx_pending) {
5708                         /* We've lost link, so the controller stops DMA,
5709                          * but we've got queued Tx work that's never going
5710                          * to get done, so reset controller to flush Tx.
5711                          * (Do the reset outside of interrupt context).
5712                          */
5713                          schedule_work(&adapter->reset_task);
5714                 }
5715         }
5716
5717         ixgbe_update_stats(adapter);
5718         mutex_unlock(&ixgbe_watchdog_lock);
5719 }
5720
5721 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5722                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5723                      u32 tx_flags, u8 *hdr_len)
5724 {
5725         struct ixgbe_adv_tx_context_desc *context_desc;
5726         unsigned int i;
5727         int err;
5728         struct ixgbe_tx_buffer *tx_buffer_info;
5729         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5730         u32 mss_l4len_idx, l4len;
5731
5732         if (skb_is_gso(skb)) {
5733                 if (skb_header_cloned(skb)) {
5734                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5735                         if (err)
5736                                 return err;
5737                 }
5738                 l4len = tcp_hdrlen(skb);
5739                 *hdr_len += l4len;
5740
5741                 if (skb->protocol == htons(ETH_P_IP)) {
5742                         struct iphdr *iph = ip_hdr(skb);
5743                         iph->tot_len = 0;
5744                         iph->check = 0;
5745                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5746                                                                  iph->daddr, 0,
5747                                                                  IPPROTO_TCP,
5748                                                                  0);
5749                 } else if (skb_is_gso_v6(skb)) {
5750                         ipv6_hdr(skb)->payload_len = 0;
5751                         tcp_hdr(skb)->check =
5752                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5753                                              &ipv6_hdr(skb)->daddr,
5754                                              0, IPPROTO_TCP, 0);
5755                 }
5756
5757                 i = tx_ring->next_to_use;
5758
5759                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5760                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5761
5762                 /* VLAN MACLEN IPLEN */
5763                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5764                         vlan_macip_lens |=
5765                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5766                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5767                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5768                 *hdr_len += skb_network_offset(skb);
5769                 vlan_macip_lens |=
5770                     (skb_transport_header(skb) - skb_network_header(skb));
5771                 *hdr_len +=
5772                     (skb_transport_header(skb) - skb_network_header(skb));
5773                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5774                 context_desc->seqnum_seed = 0;
5775
5776                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5777                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5778                                    IXGBE_ADVTXD_DTYP_CTXT);
5779
5780                 if (skb->protocol == htons(ETH_P_IP))
5781                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5782                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5783                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5784
5785                 /* MSS L4LEN IDX */
5786                 mss_l4len_idx =
5787                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5788                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5789                 /* use index 1 for TSO */
5790                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5791                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5792
5793                 tx_buffer_info->time_stamp = jiffies;
5794                 tx_buffer_info->next_to_watch = i;
5795
5796                 i++;
5797                 if (i == tx_ring->count)
5798                         i = 0;
5799                 tx_ring->next_to_use = i;
5800
5801                 return true;
5802         }
5803         return false;
5804 }
5805
5806 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5807                           struct ixgbe_ring *tx_ring,
5808                           struct sk_buff *skb, u32 tx_flags)
5809 {
5810         struct ixgbe_adv_tx_context_desc *context_desc;
5811         unsigned int i;
5812         struct ixgbe_tx_buffer *tx_buffer_info;
5813         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5814
5815         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5816             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5817                 i = tx_ring->next_to_use;
5818                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5819                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5820
5821                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5822                         vlan_macip_lens |=
5823                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5824                 vlan_macip_lens |= (skb_network_offset(skb) <<
5825                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5826                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5827                         vlan_macip_lens |= (skb_transport_header(skb) -
5828                                             skb_network_header(skb));
5829
5830                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5831                 context_desc->seqnum_seed = 0;
5832
5833                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5834                                     IXGBE_ADVTXD_DTYP_CTXT);
5835
5836                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5837                         __be16 protocol;
5838
5839                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5840                                 const struct vlan_ethhdr *vhdr =
5841                                         (const struct vlan_ethhdr *)skb->data;
5842
5843                                 protocol = vhdr->h_vlan_encapsulated_proto;
5844                         } else {
5845                                 protocol = skb->protocol;
5846                         }
5847
5848                         switch (protocol) {
5849                         case cpu_to_be16(ETH_P_IP):
5850                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5851                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5852                                         type_tucmd_mlhl |=
5853                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5854                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5855                                         type_tucmd_mlhl |=
5856                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5857                                 break;
5858                         case cpu_to_be16(ETH_P_IPV6):
5859                                 /* XXX what about other V6 headers?? */
5860                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5861                                         type_tucmd_mlhl |=
5862                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5863                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5864                                         type_tucmd_mlhl |=
5865                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5866                                 break;
5867                         default:
5868                                 if (unlikely(net_ratelimit())) {
5869                                         e_warn(probe, "partial checksum "
5870                                                "but proto=%x!\n",
5871                                                skb->protocol);
5872                                 }
5873                                 break;
5874                         }
5875                 }
5876
5877                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5878                 /* use index zero for tx checksum offload */
5879                 context_desc->mss_l4len_idx = 0;
5880
5881                 tx_buffer_info->time_stamp = jiffies;
5882                 tx_buffer_info->next_to_watch = i;
5883
5884                 i++;
5885                 if (i == tx_ring->count)
5886                         i = 0;
5887                 tx_ring->next_to_use = i;
5888
5889                 return true;
5890         }
5891
5892         return false;
5893 }
5894
5895 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5896                         struct ixgbe_ring *tx_ring,
5897                         struct sk_buff *skb, u32 tx_flags,
5898                         unsigned int first)
5899 {
5900         struct pci_dev *pdev = adapter->pdev;
5901         struct ixgbe_tx_buffer *tx_buffer_info;
5902         unsigned int len;
5903         unsigned int total = skb->len;
5904         unsigned int offset = 0, size, count = 0, i;
5905         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5906         unsigned int f;
5907
5908         i = tx_ring->next_to_use;
5909
5910         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5911                 /* excluding fcoe_crc_eof for FCoE */
5912                 total -= sizeof(struct fcoe_crc_eof);
5913
5914         len = min(skb_headlen(skb), total);
5915         while (len) {
5916                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5917                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5918
5919                 tx_buffer_info->length = size;
5920                 tx_buffer_info->mapped_as_page = false;
5921                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5922                                                      skb->data + offset,
5923                                                      size, DMA_TO_DEVICE);
5924                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5925                         goto dma_error;
5926                 tx_buffer_info->time_stamp = jiffies;
5927                 tx_buffer_info->next_to_watch = i;
5928
5929                 len -= size;
5930                 total -= size;
5931                 offset += size;
5932                 count++;
5933
5934                 if (len) {
5935                         i++;
5936                         if (i == tx_ring->count)
5937                                 i = 0;
5938                 }
5939         }
5940
5941         for (f = 0; f < nr_frags; f++) {
5942                 struct skb_frag_struct *frag;
5943
5944                 frag = &skb_shinfo(skb)->frags[f];
5945                 len = min((unsigned int)frag->size, total);
5946                 offset = frag->page_offset;
5947
5948                 while (len) {
5949                         i++;
5950                         if (i == tx_ring->count)
5951                                 i = 0;
5952
5953                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5954                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5955
5956                         tx_buffer_info->length = size;
5957                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5958                                                            frag->page,
5959                                                            offset, size,
5960                                                            DMA_TO_DEVICE);
5961                         tx_buffer_info->mapped_as_page = true;
5962                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5963                                 goto dma_error;
5964                         tx_buffer_info->time_stamp = jiffies;
5965                         tx_buffer_info->next_to_watch = i;
5966
5967                         len -= size;
5968                         total -= size;
5969                         offset += size;
5970                         count++;
5971                 }
5972                 if (total == 0)
5973                         break;
5974         }
5975
5976         tx_ring->tx_buffer_info[i].skb = skb;
5977         tx_ring->tx_buffer_info[first].next_to_watch = i;
5978
5979         return count;
5980
5981 dma_error:
5982         e_dev_err("TX DMA map failed\n");
5983
5984         /* clear timestamp and dma mappings for failed tx_buffer_info map */
5985         tx_buffer_info->dma = 0;
5986         tx_buffer_info->time_stamp = 0;
5987         tx_buffer_info->next_to_watch = 0;
5988         if (count)
5989                 count--;
5990
5991         /* clear timestamp and dma mappings for remaining portion of packet */
5992         while (count--) {
5993                 if (i==0)
5994                         i += tx_ring->count;
5995                 i--;
5996                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5997                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
5998         }
5999
6000         return 0;
6001 }
6002
6003 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6004                            struct ixgbe_ring *tx_ring,
6005                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6006 {
6007         union ixgbe_adv_tx_desc *tx_desc = NULL;
6008         struct ixgbe_tx_buffer *tx_buffer_info;
6009         u32 olinfo_status = 0, cmd_type_len = 0;
6010         unsigned int i;
6011         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6012
6013         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6014
6015         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6016
6017         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6018                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6019
6020         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6021                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6022
6023                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6024                                  IXGBE_ADVTXD_POPTS_SHIFT;
6025
6026                 /* use index 1 context for tso */
6027                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6028                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6029                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6030                                          IXGBE_ADVTXD_POPTS_SHIFT;
6031
6032         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6033                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6034                                  IXGBE_ADVTXD_POPTS_SHIFT;
6035
6036         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6037                 olinfo_status |= IXGBE_ADVTXD_CC;
6038                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6039                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6040                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6041         }
6042
6043         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6044
6045         i = tx_ring->next_to_use;
6046         while (count--) {
6047                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6048                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6049                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6050                 tx_desc->read.cmd_type_len =
6051                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6052                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6053                 i++;
6054                 if (i == tx_ring->count)
6055                         i = 0;
6056         }
6057
6058         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6059
6060         /*
6061          * Force memory writes to complete before letting h/w
6062          * know there are new descriptors to fetch.  (Only
6063          * applicable for weak-ordered memory model archs,
6064          * such as IA-64).
6065          */
6066         wmb();
6067
6068         tx_ring->next_to_use = i;
6069         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6070 }
6071
6072 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6073                       int queue, u32 tx_flags)
6074 {
6075         struct ixgbe_atr_input atr_input;
6076         struct tcphdr *th;
6077         struct iphdr *iph = ip_hdr(skb);
6078         struct ethhdr *eth = (struct ethhdr *)skb->data;
6079         u16 vlan_id, src_port, dst_port, flex_bytes;
6080         u32 src_ipv4_addr, dst_ipv4_addr;
6081         u8 l4type = 0;
6082
6083         /* Right now, we support IPv4 only */
6084         if (skb->protocol != htons(ETH_P_IP))
6085                 return;
6086         /* check if we're UDP or TCP */
6087         if (iph->protocol == IPPROTO_TCP) {
6088                 th = tcp_hdr(skb);
6089                 src_port = th->source;
6090                 dst_port = th->dest;
6091                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6092                 /* l4type IPv4 type is 0, no need to assign */
6093         } else {
6094                 /* Unsupported L4 header, just bail here */
6095                 return;
6096         }
6097
6098         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6099
6100         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6101                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6102         src_ipv4_addr = iph->saddr;
6103         dst_ipv4_addr = iph->daddr;
6104         flex_bytes = eth->h_proto;
6105
6106         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6107         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6108         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6109         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6110         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6111         /* src and dst are inverted, think how the receiver sees them */
6112         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6113         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6114
6115         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6116         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6117 }
6118
6119 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6120                                  struct ixgbe_ring *tx_ring, int size)
6121 {
6122         netif_stop_subqueue(netdev, tx_ring->queue_index);
6123         /* Herbert's original patch had:
6124          *  smp_mb__after_netif_stop_queue();
6125          * but since that doesn't exist yet, just open code it. */
6126         smp_mb();
6127
6128         /* We need to check again in a case another CPU has just
6129          * made room available. */
6130         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6131                 return -EBUSY;
6132
6133         /* A reprieve! - use start_queue because it doesn't call schedule */
6134         netif_start_subqueue(netdev, tx_ring->queue_index);
6135         ++tx_ring->restart_queue;
6136         return 0;
6137 }
6138
6139 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6140                               struct ixgbe_ring *tx_ring, int size)
6141 {
6142         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6143                 return 0;
6144         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6145 }
6146
6147 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6148 {
6149         struct ixgbe_adapter *adapter = netdev_priv(dev);
6150         int txq = smp_processor_id();
6151
6152 #ifdef IXGBE_FCOE
6153         if ((skb->protocol == htons(ETH_P_FCOE)) ||
6154             (skb->protocol == htons(ETH_P_FIP))) {
6155                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6156                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6157                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6158                         return txq;
6159 #ifdef CONFIG_IXGBE_DCB
6160                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6161                         txq = adapter->fcoe.up;
6162                         return txq;
6163 #endif
6164                 }
6165         }
6166 #endif
6167
6168         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6169                 while (unlikely(txq >= dev->real_num_tx_queues))
6170                         txq -= dev->real_num_tx_queues;
6171                 return txq;
6172         }
6173
6174         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6175                 if (skb->priority == TC_PRIO_CONTROL)
6176                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6177                 else
6178                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6179                                >> 13;
6180                 return txq;
6181         }
6182
6183         return skb_tx_hash(dev, skb);
6184 }
6185
6186 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6187                                     struct net_device *netdev)
6188 {
6189         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6190         struct ixgbe_ring *tx_ring;
6191         struct netdev_queue *txq;
6192         unsigned int first;
6193         unsigned int tx_flags = 0;
6194         u8 hdr_len = 0;
6195         int tso;
6196         int count = 0;
6197         unsigned int f;
6198
6199         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6200                 tx_flags |= vlan_tx_tag_get(skb);
6201                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6202                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6203                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6204                 }
6205                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6206                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6207         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6208                    skb->priority != TC_PRIO_CONTROL) {
6209                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6210                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6211                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6212         }
6213
6214         tx_ring = adapter->tx_ring[skb->queue_mapping];
6215
6216 #ifdef IXGBE_FCOE
6217         /* for FCoE with DCB, we force the priority to what
6218          * was specified by the switch */
6219         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6220             (skb->protocol == htons(ETH_P_FCOE) ||
6221              skb->protocol == htons(ETH_P_FIP))) {
6222 #ifdef CONFIG_IXGBE_DCB
6223                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6224                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6225                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6226                         tx_flags |= ((adapter->fcoe.up << 13)
6227                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6228                 }
6229 #endif
6230                 /* flag for FCoE offloads */
6231                 if (skb->protocol == htons(ETH_P_FCOE))
6232                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6233         }
6234 #endif
6235
6236         /* four things can cause us to need a context descriptor */
6237         if (skb_is_gso(skb) ||
6238             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6239             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6240             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6241                 count++;
6242
6243         count += TXD_USE_COUNT(skb_headlen(skb));
6244         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6245                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6246
6247         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6248                 adapter->tx_busy++;
6249                 return NETDEV_TX_BUSY;
6250         }
6251
6252         first = tx_ring->next_to_use;
6253         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6254 #ifdef IXGBE_FCOE
6255                 /* setup tx offload for FCoE */
6256                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6257                 if (tso < 0) {
6258                         dev_kfree_skb_any(skb);
6259                         return NETDEV_TX_OK;
6260                 }
6261                 if (tso)
6262                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6263 #endif /* IXGBE_FCOE */
6264         } else {
6265                 if (skb->protocol == htons(ETH_P_IP))
6266                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6267                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6268                 if (tso < 0) {
6269                         dev_kfree_skb_any(skb);
6270                         return NETDEV_TX_OK;
6271                 }
6272
6273                 if (tso)
6274                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6275                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6276                          (skb->ip_summed == CHECKSUM_PARTIAL))
6277                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6278         }
6279
6280         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6281         if (count) {
6282                 /* add the ATR filter if ATR is on */
6283                 if (tx_ring->atr_sample_rate) {
6284                         ++tx_ring->atr_count;
6285                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6286                              test_bit(__IXGBE_FDIR_INIT_DONE,
6287                                       &tx_ring->reinit_state)) {
6288                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6289                                           tx_flags);
6290                                 tx_ring->atr_count = 0;
6291                         }
6292                 }
6293                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6294                 txq->tx_bytes += skb->len;
6295                 txq->tx_packets++;
6296                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6297                                hdr_len);
6298                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6299
6300         } else {
6301                 dev_kfree_skb_any(skb);
6302                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6303                 tx_ring->next_to_use = first;
6304         }
6305
6306         return NETDEV_TX_OK;
6307 }
6308
6309 /**
6310  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6311  * @netdev: network interface device structure
6312  * @p: pointer to an address structure
6313  *
6314  * Returns 0 on success, negative on failure
6315  **/
6316 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6317 {
6318         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6319         struct ixgbe_hw *hw = &adapter->hw;
6320         struct sockaddr *addr = p;
6321
6322         if (!is_valid_ether_addr(addr->sa_data))
6323                 return -EADDRNOTAVAIL;
6324
6325         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6326         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6327
6328         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6329                             IXGBE_RAH_AV);
6330
6331         return 0;
6332 }
6333
6334 static int
6335 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6336 {
6337         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6338         struct ixgbe_hw *hw = &adapter->hw;
6339         u16 value;
6340         int rc;
6341
6342         if (prtad != hw->phy.mdio.prtad)
6343                 return -EINVAL;
6344         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6345         if (!rc)
6346                 rc = value;
6347         return rc;
6348 }
6349
6350 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6351                             u16 addr, u16 value)
6352 {
6353         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6354         struct ixgbe_hw *hw = &adapter->hw;
6355
6356         if (prtad != hw->phy.mdio.prtad)
6357                 return -EINVAL;
6358         return hw->phy.ops.write_reg(hw, addr, devad, value);
6359 }
6360
6361 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6362 {
6363         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6364
6365         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6366 }
6367
6368 /**
6369  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6370  * netdev->dev_addrs
6371  * @netdev: network interface device structure
6372  *
6373  * Returns non-zero on failure
6374  **/
6375 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6376 {
6377         int err = 0;
6378         struct ixgbe_adapter *adapter = netdev_priv(dev);
6379         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6380
6381         if (is_valid_ether_addr(mac->san_addr)) {
6382                 rtnl_lock();
6383                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6384                 rtnl_unlock();
6385         }
6386         return err;
6387 }
6388
6389 /**
6390  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6391  * netdev->dev_addrs
6392  * @netdev: network interface device structure
6393  *
6394  * Returns non-zero on failure
6395  **/
6396 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6397 {
6398         int err = 0;
6399         struct ixgbe_adapter *adapter = netdev_priv(dev);
6400         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6401
6402         if (is_valid_ether_addr(mac->san_addr)) {
6403                 rtnl_lock();
6404                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6405                 rtnl_unlock();
6406         }
6407         return err;
6408 }
6409
6410 #ifdef CONFIG_NET_POLL_CONTROLLER
6411 /*
6412  * Polling 'interrupt' - used by things like netconsole to send skbs
6413  * without having to re-enable interrupts. It's not called while
6414  * the interrupt routine is executing.
6415  */
6416 static void ixgbe_netpoll(struct net_device *netdev)
6417 {
6418         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6419         int i;
6420
6421         /* if interface is down do nothing */
6422         if (test_bit(__IXGBE_DOWN, &adapter->state))
6423                 return;
6424
6425         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6426         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6427                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6428                 for (i = 0; i < num_q_vectors; i++) {
6429                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6430                         ixgbe_msix_clean_many(0, q_vector);
6431                 }
6432         } else {
6433                 ixgbe_intr(adapter->pdev->irq, netdev);
6434         }
6435         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6436 }
6437 #endif
6438
6439 static const struct net_device_ops ixgbe_netdev_ops = {
6440         .ndo_open               = ixgbe_open,
6441         .ndo_stop               = ixgbe_close,
6442         .ndo_start_xmit         = ixgbe_xmit_frame,
6443         .ndo_select_queue       = ixgbe_select_queue,
6444         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6445         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6446         .ndo_validate_addr      = eth_validate_addr,
6447         .ndo_set_mac_address    = ixgbe_set_mac,
6448         .ndo_change_mtu         = ixgbe_change_mtu,
6449         .ndo_tx_timeout         = ixgbe_tx_timeout,
6450         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
6451         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6452         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6453         .ndo_do_ioctl           = ixgbe_ioctl,
6454         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6455         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6456         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6457         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6458 #ifdef CONFIG_NET_POLL_CONTROLLER
6459         .ndo_poll_controller    = ixgbe_netpoll,
6460 #endif
6461 #ifdef IXGBE_FCOE
6462         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6463         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6464         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6465         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6466         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6467 #endif /* IXGBE_FCOE */
6468 };
6469
6470 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6471                            const struct ixgbe_info *ii)
6472 {
6473 #ifdef CONFIG_PCI_IOV
6474         struct ixgbe_hw *hw = &adapter->hw;
6475         int err;
6476
6477         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6478                 return;
6479
6480         /* The 82599 supports up to 64 VFs per physical function
6481          * but this implementation limits allocation to 63 so that
6482          * basic networking resources are still available to the
6483          * physical function
6484          */
6485         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6486         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6487         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6488         if (err) {
6489                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6490                 goto err_novfs;
6491         }
6492         /* If call to enable VFs succeeded then allocate memory
6493          * for per VF control structures.
6494          */
6495         adapter->vfinfo =
6496                 kcalloc(adapter->num_vfs,
6497                         sizeof(struct vf_data_storage), GFP_KERNEL);
6498         if (adapter->vfinfo) {
6499                 /* Now that we're sure SR-IOV is enabled
6500                  * and memory allocated set up the mailbox parameters
6501                  */
6502                 ixgbe_init_mbx_params_pf(hw);
6503                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6504                        sizeof(hw->mbx.ops));
6505
6506                 /* Disable RSC when in SR-IOV mode */
6507                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6508                                      IXGBE_FLAG2_RSC_ENABLED);
6509                 return;
6510         }
6511
6512         /* Oh oh */
6513         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6514               "SRIOV disabled\n");
6515         pci_disable_sriov(adapter->pdev);
6516
6517 err_novfs:
6518         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6519         adapter->num_vfs = 0;
6520 #endif /* CONFIG_PCI_IOV */
6521 }
6522
6523 /**
6524  * ixgbe_probe - Device Initialization Routine
6525  * @pdev: PCI device information struct
6526  * @ent: entry in ixgbe_pci_tbl
6527  *
6528  * Returns 0 on success, negative on failure
6529  *
6530  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6531  * The OS initialization, configuring of the adapter private structure,
6532  * and a hardware reset occur.
6533  **/
6534 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6535                                  const struct pci_device_id *ent)
6536 {
6537         struct net_device *netdev;
6538         struct ixgbe_adapter *adapter = NULL;
6539         struct ixgbe_hw *hw;
6540         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6541         static int cards_found;
6542         int i, err, pci_using_dac;
6543         unsigned int indices = num_possible_cpus();
6544 #ifdef IXGBE_FCOE
6545         u16 device_caps;
6546 #endif
6547         u32 part_num, eec;
6548
6549         /* Catch broken hardware that put the wrong VF device ID in
6550          * the PCIe SR-IOV capability.
6551          */
6552         if (pdev->is_virtfn) {
6553                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6554                      pci_name(pdev), pdev->vendor, pdev->device);
6555                 return -EINVAL;
6556         }
6557
6558         err = pci_enable_device_mem(pdev);
6559         if (err)
6560                 return err;
6561
6562         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6563             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6564                 pci_using_dac = 1;
6565         } else {
6566                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6567                 if (err) {
6568                         err = dma_set_coherent_mask(&pdev->dev,
6569                                                     DMA_BIT_MASK(32));
6570                         if (err) {
6571                                 dev_err(&pdev->dev,
6572                                         "No usable DMA configuration, aborting\n");
6573                                 goto err_dma;
6574                         }
6575                 }
6576                 pci_using_dac = 0;
6577         }
6578
6579         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6580                                            IORESOURCE_MEM), ixgbe_driver_name);
6581         if (err) {
6582                 dev_err(&pdev->dev,
6583                         "pci_request_selected_regions failed 0x%x\n", err);
6584                 goto err_pci_reg;
6585         }
6586
6587         pci_enable_pcie_error_reporting(pdev);
6588
6589         pci_set_master(pdev);
6590         pci_save_state(pdev);
6591
6592         if (ii->mac == ixgbe_mac_82598EB)
6593                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6594         else
6595                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6596
6597         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6598 #ifdef IXGBE_FCOE
6599         indices += min_t(unsigned int, num_possible_cpus(),
6600                          IXGBE_MAX_FCOE_INDICES);
6601 #endif
6602         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6603         if (!netdev) {
6604                 err = -ENOMEM;
6605                 goto err_alloc_etherdev;
6606         }
6607
6608         SET_NETDEV_DEV(netdev, &pdev->dev);
6609
6610         pci_set_drvdata(pdev, netdev);
6611         adapter = netdev_priv(netdev);
6612
6613         adapter->netdev = netdev;
6614         adapter->pdev = pdev;
6615         hw = &adapter->hw;
6616         hw->back = adapter;
6617         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6618
6619         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6620                               pci_resource_len(pdev, 0));
6621         if (!hw->hw_addr) {
6622                 err = -EIO;
6623                 goto err_ioremap;
6624         }
6625
6626         for (i = 1; i <= 5; i++) {
6627                 if (pci_resource_len(pdev, i) == 0)
6628                         continue;
6629         }
6630
6631         netdev->netdev_ops = &ixgbe_netdev_ops;
6632         ixgbe_set_ethtool_ops(netdev);
6633         netdev->watchdog_timeo = 5 * HZ;
6634         strcpy(netdev->name, pci_name(pdev));
6635
6636         adapter->bd_number = cards_found;
6637
6638         /* Setup hw api */
6639         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6640         hw->mac.type  = ii->mac;
6641
6642         /* EEPROM */
6643         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6644         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6645         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6646         if (!(eec & (1 << 8)))
6647                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6648
6649         /* PHY */
6650         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6651         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6652         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6653         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6654         hw->phy.mdio.mmds = 0;
6655         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6656         hw->phy.mdio.dev = netdev;
6657         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6658         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6659
6660         /* set up this timer and work struct before calling get_invariants
6661          * which might start the timer
6662          */
6663         init_timer(&adapter->sfp_timer);
6664         adapter->sfp_timer.function = &ixgbe_sfp_timer;
6665         adapter->sfp_timer.data = (unsigned long) adapter;
6666
6667         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6668
6669         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6670         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6671
6672         /* a new SFP+ module arrival, called from GPI SDP2 context */
6673         INIT_WORK(&adapter->sfp_config_module_task,
6674                   ixgbe_sfp_config_module_task);
6675
6676         ii->get_invariants(hw);
6677
6678         /* setup the private structure */
6679         err = ixgbe_sw_init(adapter);
6680         if (err)
6681                 goto err_sw_init;
6682
6683         /* Make it possible the adapter to be woken up via WOL */
6684         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6685                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6686
6687         /*
6688          * If there is a fan on this device and it has failed log the
6689          * failure.
6690          */
6691         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6692                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6693                 if (esdp & IXGBE_ESDP_SDP1)
6694                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6695         }
6696
6697         /* reset_hw fills in the perm_addr as well */
6698         hw->phy.reset_if_overtemp = true;
6699         err = hw->mac.ops.reset_hw(hw);
6700         hw->phy.reset_if_overtemp = false;
6701         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6702             hw->mac.type == ixgbe_mac_82598EB) {
6703                 /*
6704                  * Start a kernel thread to watch for a module to arrive.
6705                  * Only do this for 82598, since 82599 will generate
6706                  * interrupts on module arrival.
6707                  */
6708                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6709                 mod_timer(&adapter->sfp_timer,
6710                           round_jiffies(jiffies + (2 * HZ)));
6711                 err = 0;
6712         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6713                 e_dev_err("failed to initialize because an unsupported SFP+ "
6714                           "module type was detected.\n");
6715                 e_dev_err("Reload the driver after installing a supported "
6716                           "module.\n");
6717                 goto err_sw_init;
6718         } else if (err) {
6719                 e_dev_err("HW Init failed: %d\n", err);
6720                 goto err_sw_init;
6721         }
6722
6723         ixgbe_probe_vf(adapter, ii);
6724
6725         netdev->features = NETIF_F_SG |
6726                            NETIF_F_IP_CSUM |
6727                            NETIF_F_HW_VLAN_TX |
6728                            NETIF_F_HW_VLAN_RX |
6729                            NETIF_F_HW_VLAN_FILTER;
6730
6731         netdev->features |= NETIF_F_IPV6_CSUM;
6732         netdev->features |= NETIF_F_TSO;
6733         netdev->features |= NETIF_F_TSO6;
6734         netdev->features |= NETIF_F_GRO;
6735
6736         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6737                 netdev->features |= NETIF_F_SCTP_CSUM;
6738
6739         netdev->vlan_features |= NETIF_F_TSO;
6740         netdev->vlan_features |= NETIF_F_TSO6;
6741         netdev->vlan_features |= NETIF_F_IP_CSUM;
6742         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6743         netdev->vlan_features |= NETIF_F_SG;
6744
6745         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6746                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6747                                     IXGBE_FLAG_DCB_ENABLED);
6748         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6749                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6750
6751 #ifdef CONFIG_IXGBE_DCB
6752         netdev->dcbnl_ops = &dcbnl_ops;
6753 #endif
6754
6755 #ifdef IXGBE_FCOE
6756         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6757                 if (hw->mac.ops.get_device_caps) {
6758                         hw->mac.ops.get_device_caps(hw, &device_caps);
6759                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6760                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6761                 }
6762         }
6763         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6764                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6765                 netdev->vlan_features |= NETIF_F_FSO;
6766                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6767         }
6768 #endif /* IXGBE_FCOE */
6769         if (pci_using_dac)
6770                 netdev->features |= NETIF_F_HIGHDMA;
6771
6772         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6773                 netdev->features |= NETIF_F_LRO;
6774
6775         /* make sure the EEPROM is good */
6776         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6777                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6778                 err = -EIO;
6779                 goto err_eeprom;
6780         }
6781
6782         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6783         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6784
6785         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6786                 e_dev_err("invalid MAC address\n");
6787                 err = -EIO;
6788                 goto err_eeprom;
6789         }
6790
6791         /* power down the optics */
6792         if (hw->phy.multispeed_fiber)
6793                 hw->mac.ops.disable_tx_laser(hw);
6794
6795         init_timer(&adapter->watchdog_timer);
6796         adapter->watchdog_timer.function = &ixgbe_watchdog;
6797         adapter->watchdog_timer.data = (unsigned long)adapter;
6798
6799         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6800         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6801
6802         err = ixgbe_init_interrupt_scheme(adapter);
6803         if (err)
6804                 goto err_sw_init;
6805
6806         switch (pdev->device) {
6807         case IXGBE_DEV_ID_82599_KX4:
6808                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6809                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6810                 break;
6811         default:
6812                 adapter->wol = 0;
6813                 break;
6814         }
6815         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6816
6817         /* pick up the PCI bus settings for reporting later */
6818         hw->mac.ops.get_bus_info(hw);
6819
6820         /* print bus type/speed/width info */
6821         e_dev_info("(PCI Express:%s:%s) %pM\n",
6822                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6823                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6824                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6825                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6826                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6827                  "Unknown"),
6828                 netdev->dev_addr);
6829         ixgbe_read_pba_num_generic(hw, &part_num);
6830         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6831                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6832                            "PBA No: %06x-%03x\n",
6833                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6834                            (part_num >> 8), (part_num & 0xff));
6835         else
6836                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6837                            hw->mac.type, hw->phy.type,
6838                            (part_num >> 8), (part_num & 0xff));
6839
6840         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6841                 e_dev_warn("PCI-Express bandwidth available for this card is "
6842                            "not sufficient for optimal performance.\n");
6843                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6844                            "is required.\n");
6845         }
6846
6847         /* save off EEPROM version number */
6848         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6849
6850         /* reset the hardware with the new settings */
6851         err = hw->mac.ops.start_hw(hw);
6852
6853         if (err == IXGBE_ERR_EEPROM_VERSION) {
6854                 /* We are running on a pre-production device, log a warning */
6855                 e_dev_warn("This device is a pre-production adapter/LOM. "
6856                            "Please be aware there may be issues associated "
6857                            "with your hardware.  If you are experiencing "
6858                            "problems please contact your Intel or hardware "
6859                            "representative who provided you with this "
6860                            "hardware.\n");
6861         }
6862         strcpy(netdev->name, "eth%d");
6863         err = register_netdev(netdev);
6864         if (err)
6865                 goto err_register;
6866
6867         /* carrier off reporting is important to ethtool even BEFORE open */
6868         netif_carrier_off(netdev);
6869
6870         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6871             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6872                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6873
6874         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6875                 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6876 #ifdef CONFIG_IXGBE_DCA
6877         if (dca_add_requester(&pdev->dev) == 0) {
6878                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6879                 ixgbe_setup_dca(adapter);
6880         }
6881 #endif
6882         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6883                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6884                 for (i = 0; i < adapter->num_vfs; i++)
6885                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6886         }
6887
6888         /* add san mac addr to netdev */
6889         ixgbe_add_sanmac_netdev(netdev);
6890
6891         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6892         cards_found++;
6893         return 0;
6894
6895 err_register:
6896         ixgbe_release_hw_control(adapter);
6897         ixgbe_clear_interrupt_scheme(adapter);
6898 err_sw_init:
6899 err_eeprom:
6900         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6901                 ixgbe_disable_sriov(adapter);
6902         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6903         del_timer_sync(&adapter->sfp_timer);
6904         cancel_work_sync(&adapter->sfp_task);
6905         cancel_work_sync(&adapter->multispeed_fiber_task);
6906         cancel_work_sync(&adapter->sfp_config_module_task);
6907         iounmap(hw->hw_addr);
6908 err_ioremap:
6909         free_netdev(netdev);
6910 err_alloc_etherdev:
6911         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6912                                      IORESOURCE_MEM));
6913 err_pci_reg:
6914 err_dma:
6915         pci_disable_device(pdev);
6916         return err;
6917 }
6918
6919 /**
6920  * ixgbe_remove - Device Removal Routine
6921  * @pdev: PCI device information struct
6922  *
6923  * ixgbe_remove is called by the PCI subsystem to alert the driver
6924  * that it should release a PCI device.  The could be caused by a
6925  * Hot-Plug event, or because the driver is going to be removed from
6926  * memory.
6927  **/
6928 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6929 {
6930         struct net_device *netdev = pci_get_drvdata(pdev);
6931         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6932
6933         set_bit(__IXGBE_DOWN, &adapter->state);
6934         /* clear the module not found bit to make sure the worker won't
6935          * reschedule
6936          */
6937         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6938         del_timer_sync(&adapter->watchdog_timer);
6939
6940         del_timer_sync(&adapter->sfp_timer);
6941         cancel_work_sync(&adapter->watchdog_task);
6942         cancel_work_sync(&adapter->sfp_task);
6943         cancel_work_sync(&adapter->multispeed_fiber_task);
6944         cancel_work_sync(&adapter->sfp_config_module_task);
6945         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6946             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6947                 cancel_work_sync(&adapter->fdir_reinit_task);
6948         flush_scheduled_work();
6949
6950 #ifdef CONFIG_IXGBE_DCA
6951         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6952                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6953                 dca_remove_requester(&pdev->dev);
6954                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6955         }
6956
6957 #endif
6958 #ifdef IXGBE_FCOE
6959         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6960                 ixgbe_cleanup_fcoe(adapter);
6961
6962 #endif /* IXGBE_FCOE */
6963
6964         /* remove the added san mac */
6965         ixgbe_del_sanmac_netdev(netdev);
6966
6967         if (netdev->reg_state == NETREG_REGISTERED)
6968                 unregister_netdev(netdev);
6969
6970         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6971                 ixgbe_disable_sriov(adapter);
6972
6973         ixgbe_clear_interrupt_scheme(adapter);
6974
6975         ixgbe_release_hw_control(adapter);
6976
6977         iounmap(adapter->hw.hw_addr);
6978         pci_release_selected_regions(pdev, pci_select_bars(pdev,
6979                                      IORESOURCE_MEM));
6980
6981         e_dev_info("complete\n");
6982
6983         free_netdev(netdev);
6984
6985         pci_disable_pcie_error_reporting(pdev);
6986
6987         pci_disable_device(pdev);
6988 }
6989
6990 /**
6991  * ixgbe_io_error_detected - called when PCI error is detected
6992  * @pdev: Pointer to PCI device
6993  * @state: The current pci connection state
6994  *
6995  * This function is called after a PCI bus error affecting
6996  * this device has been detected.
6997  */
6998 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
6999                                                 pci_channel_state_t state)
7000 {
7001         struct net_device *netdev = pci_get_drvdata(pdev);
7002         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7003
7004         netif_device_detach(netdev);
7005
7006         if (state == pci_channel_io_perm_failure)
7007                 return PCI_ERS_RESULT_DISCONNECT;
7008
7009         if (netif_running(netdev))
7010                 ixgbe_down(adapter);
7011         pci_disable_device(pdev);
7012
7013         /* Request a slot reset. */
7014         return PCI_ERS_RESULT_NEED_RESET;
7015 }
7016
7017 /**
7018  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7019  * @pdev: Pointer to PCI device
7020  *
7021  * Restart the card from scratch, as if from a cold-boot.
7022  */
7023 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7024 {
7025         struct net_device *netdev = pci_get_drvdata(pdev);
7026         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7027         pci_ers_result_t result;
7028         int err;
7029
7030         if (pci_enable_device_mem(pdev)) {
7031                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7032                 result = PCI_ERS_RESULT_DISCONNECT;
7033         } else {
7034                 pci_set_master(pdev);
7035                 pci_restore_state(pdev);
7036                 pci_save_state(pdev);
7037
7038                 pci_wake_from_d3(pdev, false);
7039
7040                 ixgbe_reset(adapter);
7041                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7042                 result = PCI_ERS_RESULT_RECOVERED;
7043         }
7044
7045         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7046         if (err) {
7047                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7048                           "failed 0x%0x\n", err);
7049                 /* non-fatal, continue */
7050         }
7051
7052         return result;
7053 }
7054
7055 /**
7056  * ixgbe_io_resume - called when traffic can start flowing again.
7057  * @pdev: Pointer to PCI device
7058  *
7059  * This callback is called when the error recovery driver tells us that
7060  * its OK to resume normal operation.
7061  */
7062 static void ixgbe_io_resume(struct pci_dev *pdev)
7063 {
7064         struct net_device *netdev = pci_get_drvdata(pdev);
7065         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7066
7067         if (netif_running(netdev)) {
7068                 if (ixgbe_up(adapter)) {
7069                         e_info(probe, "ixgbe_up failed after reset\n");
7070                         return;
7071                 }
7072         }
7073
7074         netif_device_attach(netdev);
7075 }
7076
7077 static struct pci_error_handlers ixgbe_err_handler = {
7078         .error_detected = ixgbe_io_error_detected,
7079         .slot_reset = ixgbe_io_slot_reset,
7080         .resume = ixgbe_io_resume,
7081 };
7082
7083 static struct pci_driver ixgbe_driver = {
7084         .name     = ixgbe_driver_name,
7085         .id_table = ixgbe_pci_tbl,
7086         .probe    = ixgbe_probe,
7087         .remove   = __devexit_p(ixgbe_remove),
7088 #ifdef CONFIG_PM
7089         .suspend  = ixgbe_suspend,
7090         .resume   = ixgbe_resume,
7091 #endif
7092         .shutdown = ixgbe_shutdown,
7093         .err_handler = &ixgbe_err_handler
7094 };
7095
7096 /**
7097  * ixgbe_init_module - Driver Registration Routine
7098  *
7099  * ixgbe_init_module is the first routine called when the driver is
7100  * loaded. All it does is register with the PCI subsystem.
7101  **/
7102 static int __init ixgbe_init_module(void)
7103 {
7104         int ret;
7105         pr_info("%s - version %s\n", ixgbe_driver_string,
7106                    ixgbe_driver_version);
7107         pr_info("%s\n", ixgbe_copyright);
7108
7109 #ifdef CONFIG_IXGBE_DCA
7110         dca_register_notify(&dca_notifier);
7111 #endif
7112
7113         ret = pci_register_driver(&ixgbe_driver);
7114         return ret;
7115 }
7116
7117 module_init(ixgbe_init_module);
7118
7119 /**
7120  * ixgbe_exit_module - Driver Exit Cleanup Routine
7121  *
7122  * ixgbe_exit_module is called just before the driver is removed
7123  * from memory.
7124  **/
7125 static void __exit ixgbe_exit_module(void)
7126 {
7127 #ifdef CONFIG_IXGBE_DCA
7128         dca_unregister_notify(&dca_notifier);
7129 #endif
7130         pci_unregister_driver(&ixgbe_driver);
7131 }
7132
7133 #ifdef CONFIG_IXGBE_DCA
7134 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7135                             void *p)
7136 {
7137         int ret_val;
7138
7139         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7140                                          __ixgbe_notify_dca);
7141
7142         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7143 }
7144
7145 #endif /* CONFIG_IXGBE_DCA */
7146
7147 /**
7148  * ixgbe_get_hw_dev return device
7149  * used by hardware layer to print debugging information
7150  **/
7151 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7152 {
7153         struct ixgbe_adapter *adapter = hw->back;
7154         return adapter->netdev;
7155 }
7156
7157 module_exit(ixgbe_exit_module);
7158
7159 /* ixgbe_main.c */