drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.44-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  97          board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 101          board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 103          board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 105          board_82599 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 107          board_82599 },
 108
 109         /* required last entry */
 110         {0, }
 111 };
 112 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 113
 114 #ifdef CONFIG_IXGBE_DCA
 115 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 116                             void *p);
 117 static struct notifier_block dca_notifier = {
 118         .notifier_call = ixgbe_notify_dca,
 119         .next          = NULL,
 120         .priority      = 0
 121 };
 122 #endif
 123
 124 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 125 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 126 MODULE_LICENSE("GPL");
 127 MODULE_VERSION(DRV_VERSION);
 128
 129 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 130
 131 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 132 {
 133         u32 ctrl_ext;
 134
 135         /* Let firmware take over control of h/w */
 136         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 137         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 138                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 139 }
 140
 141 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 142 {
 143         u32 ctrl_ext;
 144
 145         /* Let firmware know the driver has taken over */
 146         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 147         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 148                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 149 }
 150
 151 /*
 152  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 153  * @adapter: pointer to adapter struct
 154  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 155  * @queue: queue to map the corresponding interrupt to
 156  * @msix_vector: the vector to map to the corresponding queue
 157  *
 158  */
 159 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 160                            u8 queue, u8 msix_vector)
 161 {
 162         u32 ivar, index;
 163         struct ixgbe_hw *hw = &adapter->hw;
 164         switch (hw->mac.type) {
 165         case ixgbe_mac_82598EB:
 166                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 167                 if (direction == -1)
 168                         direction = 0;
 169                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 170                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 171                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 172                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 173                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 174                 break;
 175         case ixgbe_mac_82599EB:
 176                 if (direction == -1) {
 177                         /* other causes */
 178                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 179                         index = ((queue & 1) * 8);
 180                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 181                         ivar &= ~(0xFF << index);
 182                         ivar |= (msix_vector << index);
 183                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 184                         break;
 185                 } else {
 186                         /* tx or rx causes */
 187                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 188                         index = ((16 * (queue & 1)) + (8 * direction));
 189                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 190                         ivar &= ~(0xFF << index);
 191                         ivar |= (msix_vector << index);
 192                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 193                         break;
 194                 }
 195         default:
 196                 break;
 197         }
 198 }
 199
 200 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 201                                           u64 qmask)
 202 {
 203         u32 mask;
 204
 205         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 206                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 207                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 208         } else {
 209                 mask = (qmask & 0xFFFFFFFF);
 210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 211                 mask = (qmask >> 32);
 212                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 213         }
 214 }
 215
 216 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 217                                              struct ixgbe_tx_buffer
 218                                              *tx_buffer_info)
 219 {
 220         tx_buffer_info->dma = 0;
 221         if (tx_buffer_info->skb) {
 222                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 223                               DMA_TO_DEVICE);
 224                 dev_kfree_skb_any(tx_buffer_info->skb);
 225                 tx_buffer_info->skb = NULL;
 226         }
 227         tx_buffer_info->time_stamp = 0;
 228         /* tx_buffer_info must be completely set up in the transmit path */
 229 }
 230
 231 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 232                                        struct ixgbe_ring *tx_ring,
 233                                        unsigned int eop)
 234 {
 235         struct ixgbe_hw *hw = &adapter->hw;
 236
 237         /* Detect a transmit hang in hardware, this serializes the
 238          * check with the clearing of time_stamp and movement of eop */
 239         adapter->detect_tx_hung = false;
 240         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 241             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 242             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 243                 /* detected Tx unit hang */
 244                 union ixgbe_adv_tx_desc *tx_desc;
 245                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 246                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 247                         "  Tx Queue             <%d>\n"
 248                         "  TDH, TDT             <%x>, <%x>\n"
 249                         "  next_to_use          <%x>\n"
 250                         "  next_to_clean        <%x>\n"
 251                         "tx_buffer_info[next_to_clean]\n"
 252                         "  time_stamp           <%lx>\n"
 253                         "  jiffies              <%lx>\n",
 254                         tx_ring->queue_index,
 255                         IXGBE_READ_REG(hw, tx_ring->head),
 256                         IXGBE_READ_REG(hw, tx_ring->tail),
 257                         tx_ring->next_to_use, eop,
 258                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 259                 return true;
 260         }
 261
 262         return false;
 263 }
 264
 265 #define IXGBE_MAX_TXD_PWR       14
 266 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 267
 268 /* Tx Descriptors needed, worst case */
 269 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 270                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 271 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 272         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 273
 274 static void ixgbe_tx_timeout(struct net_device *netdev);
 275
 276 /**
 277  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 278  * @q_vector: structure containing interrupt and ring information
 279  * @tx_ring: tx ring to clean
 280  **/
 281 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 282                                struct ixgbe_ring *tx_ring)
 283 {
 284         struct ixgbe_adapter *adapter = q_vector->adapter;
 285         struct net_device *netdev = adapter->netdev;
 286         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 287         struct ixgbe_tx_buffer *tx_buffer_info;
 288         unsigned int i, eop, count = 0;
 289         unsigned int total_bytes = 0, total_packets = 0;
 290
 291         i = tx_ring->next_to_clean;
 292         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 293         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 294
 295         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 296                (count < tx_ring->work_limit)) {
 297                 bool cleaned = false;
 298                 for ( ; !cleaned; count++) {
 299                         struct sk_buff *skb;
 300                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 301                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 302                         cleaned = (i == eop);
 303                         skb = tx_buffer_info->skb;
 304
 305                         if (cleaned && skb) {
 306                                 unsigned int segs, bytecount;
 307                                 unsigned int hlen = skb_headlen(skb);
 308
 309                                 /* gso_segs is currently only valid for tcp */
 310                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 311 #ifdef IXGBE_FCOE
 312                                 /* adjust for FCoE Sequence Offload */
 313                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 314                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 315                                     skb_is_gso(skb)) {
 316                                         hlen = skb_transport_offset(skb) +
 317                                                 sizeof(struct fc_frame_header) +
 318                                                 sizeof(struct fcoe_crc_eof);
 319                                         segs = DIV_ROUND_UP(skb->len - hlen,
 320                                                 skb_shinfo(skb)->gso_size);
 321                                 }
 322 #endif /* IXGBE_FCOE */
 323                                 /* multiply data chunks by size of headers */
 324                                 bytecount = ((segs - 1) * hlen) + skb->len;
 325                                 total_packets += segs;
 326                                 total_bytes += bytecount;
 327                         }
 328
 329                         ixgbe_unmap_and_free_tx_resource(adapter,
 330                                                          tx_buffer_info);
 331
 332                         tx_desc->wb.status = 0;
 333
 334                         i++;
 335                         if (i == tx_ring->count)
 336                                 i = 0;
 337                 }
 338
 339                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 340                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 341         }
 342
 343         tx_ring->next_to_clean = i;
 344
 345 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 346         if (unlikely(count && netif_carrier_ok(netdev) &&
 347                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 348                 /* Make sure that anybody stopping the queue after this
 349                  * sees the new next_to_clean.
 350                  */
 351                 smp_mb();
 352                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 353                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 354                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 355                         ++adapter->restart_queue;
 356                 }
 357         }
 358
 359         if (adapter->detect_tx_hung) {
 360                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 361                         /* schedule immediate reset if we believe we hung */
 362                         DPRINTK(PROBE, INFO,
 363                                 "tx hang %d detected, resetting adapter\n",
 364                                 adapter->tx_timeout_count + 1);
 365                         ixgbe_tx_timeout(adapter->netdev);
 366                 }
 367         }
 368
 369         /* re-arm the interrupt */
 370         if (count >= tx_ring->work_limit)
 371                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 372
 373         tx_ring->total_bytes += total_bytes;
 374         tx_ring->total_packets += total_packets;
 375         tx_ring->stats.packets += total_packets;
 376         tx_ring->stats.bytes += total_bytes;
 377         netdev->stats.tx_bytes += total_bytes;
 378         netdev->stats.tx_packets += total_packets;
 379         return (count < tx_ring->work_limit);
 380 }
 381
 382 #ifdef CONFIG_IXGBE_DCA
 383 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 384                                 struct ixgbe_ring *rx_ring)
 385 {
 386         u32 rxctrl;
 387         int cpu = get_cpu();
 388         int q = rx_ring - adapter->rx_ring;
 389
 390         if (rx_ring->cpu != cpu) {
 391                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 392                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 393                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 394                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 395                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 396                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 397                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 398                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 399                 }
 400                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 401                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 402                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 403                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 404                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 405                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 406                 rx_ring->cpu = cpu;
 407         }
 408         put_cpu();
 409 }
 410
 411 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 412                                 struct ixgbe_ring *tx_ring)
 413 {
 414         u32 txctrl;
 415         int cpu = get_cpu();
 416         int q = tx_ring - adapter->tx_ring;
 417
 418         if (tx_ring->cpu != cpu) {
 419                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 420                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 421                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 422                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 423                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 424                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 425                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 426                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 427                 }
 428                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 429                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 430                 tx_ring->cpu = cpu;
 431         }
 432         put_cpu();
 433 }
 434
 435 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 436 {
 437         int i;
 438
 439         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 440                 return;
 441
 442         /* always use CB2 mode, difference is masked in the CB driver */
 443         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 444
 445         for (i = 0; i < adapter->num_tx_queues; i++) {
 446                 adapter->tx_ring[i].cpu = -1;
 447                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 448         }
 449         for (i = 0; i < adapter->num_rx_queues; i++) {
 450                 adapter->rx_ring[i].cpu = -1;
 451                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 452         }
 453 }
 454
 455 static int __ixgbe_notify_dca(struct device *dev, void *data)
 456 {
 457         struct net_device *netdev = dev_get_drvdata(dev);
 458         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 459         unsigned long event = *(unsigned long *)data;
 460
 461         switch (event) {
 462         case DCA_PROVIDER_ADD:
 463                 /* if we're already enabled, don't do it again */
 464                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 465                         break;
 466                 if (dca_add_requester(dev) == 0) {
 467                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 468                         ixgbe_setup_dca(adapter);
 469                         break;
 470                 }
 471                 /* Fall Through since DCA is disabled. */
 472         case DCA_PROVIDER_REMOVE:
 473                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 474                         dca_remove_requester(dev);
 475                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 476                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 477                 }
 478                 break;
 479         }
 480
 481         return 0;
 482 }
 483
 484 #endif /* CONFIG_IXGBE_DCA */
 485 /**
 486  * ixgbe_receive_skb - Send a completed packet up the stack
 487  * @adapter: board private structure
 488  * @skb: packet to send up
 489  * @status: hardware indication of status of receive
 490  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 491  * @rx_desc: rx descriptor
 492  **/
 493 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 494                               struct sk_buff *skb, u8 status,
 495                               struct ixgbe_ring *ring,
 496                               union ixgbe_adv_rx_desc *rx_desc)
 497 {
 498         struct ixgbe_adapter *adapter = q_vector->adapter;
 499         struct napi_struct *napi = &q_vector->napi;
 500         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 501         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 502
 503         skb_record_rx_queue(skb, ring->queue_index);
 504         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 505                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 506                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 507                 else
 508                         napi_gro_receive(napi, skb);
 509         } else {
 510                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 511                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 512                 else
 513                         netif_rx(skb);
 514         }
 515 }
 516
 517 /**
 518  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 519  * @adapter: address of board private structure
 520  * @status_err: hardware indication of status of receive
 521  * @skb: skb currently being received and modified
 522  **/
 523 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 524                                      union ixgbe_adv_rx_desc *rx_desc,
 525                                      struct sk_buff *skb)
 526 {
 527         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 528
 529         skb->ip_summed = CHECKSUM_NONE;
 530
 531         /* Rx csum disabled */
 532         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 533                 return;
 534
 535         /* if IP and error */
 536         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 537             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 538                 adapter->hw_csum_rx_error++;
 539                 return;
 540         }
 541
 542         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 543                 return;
 544
 545         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 546                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 547
 548                 /*
 549                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 550                  * checksum errors.
 551                  */
 552                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 553                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 554                         return;
 555
 556                 adapter->hw_csum_rx_error++;
 557                 return;
 558         }
 559
 560         /* It must be a TCP or UDP packet with a valid checksum */
 561         skb->ip_summed = CHECKSUM_UNNECESSARY;
 562         adapter->hw_csum_rx_good++;
 563 }
 564
 565 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 566                                          struct ixgbe_ring *rx_ring, u32 val)
 567 {
 568         /*
 569          * Force memory writes to complete before letting h/w
 570          * know there are new descriptors to fetch.  (Only
 571          * applicable for weak-ordered memory model archs,
 572          * such as IA-64).
 573          */
 574         wmb();
 575         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 576 }
 577
 578 /**
 579  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 580  * @adapter: address of board private structure
 581  **/
 582 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 583                                    struct ixgbe_ring *rx_ring,
 584                                    int cleaned_count)
 585 {
 586         struct pci_dev *pdev = adapter->pdev;
 587         union ixgbe_adv_rx_desc *rx_desc;
 588         struct ixgbe_rx_buffer *bi;
 589         unsigned int i;
 590
 591         i = rx_ring->next_to_use;
 592         bi = &rx_ring->rx_buffer_info[i];
 593
 594         while (cleaned_count--) {
 595                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 596
 597                 if (!bi->page_dma &&
 598                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 599                         if (!bi->page) {
 600                                 bi->page = alloc_page(GFP_ATOMIC);
 601                                 if (!bi->page) {
 602                                         adapter->alloc_rx_page_failed++;
 603                                         goto no_buffers;
 604                                 }
 605                                 bi->page_offset = 0;
 606                         } else {
 607                                 /* use a half page if we're re-using */
 608                                 bi->page_offset ^= (PAGE_SIZE / 2);
 609                         }
 610
 611                         bi->page_dma = pci_map_page(pdev, bi->page,
 612                                                     bi->page_offset,
 613                                                     (PAGE_SIZE / 2),
 614                                                     PCI_DMA_FROMDEVICE);
 615                 }
 616
 617                 if (!bi->skb) {
 618                         struct sk_buff *skb;
 619                         skb = netdev_alloc_skb_ip_align(adapter->netdev,
 620                                                         rx_ring->rx_buf_len);
 621
 622                         if (!skb) {
 623                                 adapter->alloc_rx_buff_failed++;
 624                                 goto no_buffers;
 625                         }
 626
 627                         bi->skb = skb;
 628                         bi->dma = pci_map_single(pdev, skb->data,
 629                                                  rx_ring->rx_buf_len,
 630                                                  PCI_DMA_FROMDEVICE);
 631                 }
 632                 /* Refresh the desc even if buffer_addrs didn't change because
 633                  * each write-back erases this info. */
 634                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 635                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 636                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 637                 } else {
 638                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 639                 }
 640
 641                 i++;
 642                 if (i == rx_ring->count)
 643                         i = 0;
 644                 bi = &rx_ring->rx_buffer_info[i];
 645         }
 646
 647 no_buffers:
 648         if (rx_ring->next_to_use != i) {
 649                 rx_ring->next_to_use = i;
 650                 if (i-- == 0)
 651                         i = (rx_ring->count - 1);
 652
 653                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 654         }
 655 }
 656
 657 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 658 {
 659         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 660 }
 661
 662 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 663 {
 664         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 665 }
 666
 667 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 668 {
 669         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 670                 IXGBE_RXDADV_RSCCNT_MASK) >>
 671                 IXGBE_RXDADV_RSCCNT_SHIFT;
 672 }
 673
 674 /**
 675  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 676  * @skb: pointer to the last skb in the rsc queue
 677  *
 678  * This function changes a queue full of hw rsc buffers into a completed
 679  * packet.  It uses the ->prev pointers to find the first packet and then
 680  * turns it into the frag list owner.
 681  **/
 682 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 683 {
 684         unsigned int frag_list_size = 0;
 685
 686         while (skb->prev) {
 687                 struct sk_buff *prev = skb->prev;
 688                 frag_list_size += skb->len;
 689                 skb->prev = NULL;
 690                 skb = prev;
 691         }
 692
 693         skb_shinfo(skb)->frag_list = skb->next;
 694         skb->next = NULL;
 695         skb->len += frag_list_size;
 696         skb->data_len += frag_list_size;
 697         skb->truesize += frag_list_size;
 698         return skb;
 699 }
 700
 701 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 702                                struct ixgbe_ring *rx_ring,
 703                                int *work_done, int work_to_do)
 704 {
 705         struct ixgbe_adapter *adapter = q_vector->adapter;
 706         struct net_device *netdev = adapter->netdev;
 707         struct pci_dev *pdev = adapter->pdev;
 708         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 709         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 710         struct sk_buff *skb;
 711         unsigned int i, rsc_count = 0;
 712         u32 len, staterr;
 713         u16 hdr_info;
 714         bool cleaned = false;
 715         int cleaned_count = 0;
 716         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 717 #ifdef IXGBE_FCOE
 718         int ddp_bytes = 0;
 719 #endif /* IXGBE_FCOE */
 720
 721         i = rx_ring->next_to_clean;
 722         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 723         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 724         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 725
 726         while (staterr & IXGBE_RXD_STAT_DD) {
 727                 u32 upper_len = 0;
 728                 if (*work_done >= work_to_do)
 729                         break;
 730                 (*work_done)++;
 731
 732                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 733                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 734                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 735                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 736                         if (hdr_info & IXGBE_RXDADV_SPH)
 737                                 adapter->rx_hdr_split++;
 738                         if (len > IXGBE_RX_HDR_SIZE)
 739                                 len = IXGBE_RX_HDR_SIZE;
 740                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 741                 } else {
 742                         len = le16_to_cpu(rx_desc->wb.upper.length);
 743                 }
 744
 745                 cleaned = true;
 746                 skb = rx_buffer_info->skb;
 747                 prefetch(skb->data - NET_IP_ALIGN);
 748                 rx_buffer_info->skb = NULL;
 749
 750                 if (rx_buffer_info->dma) {
 751                         pci_unmap_single(pdev, rx_buffer_info->dma,
 752                                          rx_ring->rx_buf_len,
 753                                          PCI_DMA_FROMDEVICE);
 754                         rx_buffer_info->dma = 0;
 755                         skb_put(skb, len);
 756                 }
 757
 758                 if (upper_len) {
 759                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 760                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 761                         rx_buffer_info->page_dma = 0;
 762                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 763                                            rx_buffer_info->page,
 764                                            rx_buffer_info->page_offset,
 765                                            upper_len);
 766
 767                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 768                             (page_count(rx_buffer_info->page) != 1))
 769                                 rx_buffer_info->page = NULL;
 770                         else
 771                                 get_page(rx_buffer_info->page);
 772
 773                         skb->len += upper_len;
 774                         skb->data_len += upper_len;
 775                         skb->truesize += upper_len;
 776                 }
 777
 778                 i++;
 779                 if (i == rx_ring->count)
 780                         i = 0;
 781
 782                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 783                 prefetch(next_rxd);
 784                 cleaned_count++;
 785
 786                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 787                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 788
 789                 if (rsc_count) {
 790                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 791                                      IXGBE_RXDADV_NEXTP_SHIFT;
 792                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 793                         rx_ring->rsc_count += (rsc_count - 1);
 794                 } else {
 795                         next_buffer = &rx_ring->rx_buffer_info[i];
 796                 }
 797
 798                 if (staterr & IXGBE_RXD_STAT_EOP) {
 799                         if (skb->prev)
 800                                 skb = ixgbe_transform_rsc_queue(skb);
 801                         rx_ring->stats.packets++;
 802                         rx_ring->stats.bytes += skb->len;
 803                 } else {
 804                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 805                                 rx_buffer_info->skb = next_buffer->skb;
 806                                 rx_buffer_info->dma = next_buffer->dma;
 807                                 next_buffer->skb = skb;
 808                                 next_buffer->dma = 0;
 809                         } else {
 810                                 skb->next = next_buffer->skb;
 811                                 skb->next->prev = skb;
 812                         }
 813                         adapter->non_eop_descs++;
 814                         goto next_desc;
 815                 }
 816
 817                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 818                         dev_kfree_skb_irq(skb);
 819                         goto next_desc;
 820                 }
 821
 822                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 823
 824                 /* probably a little skewed due to removing CRC */
 825                 total_rx_bytes += skb->len;
 826                 total_rx_packets++;
 827
 828                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 829 #ifdef IXGBE_FCOE
 830                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 831                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 832                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 833                         if (!ddp_bytes)
 834                                 goto next_desc;
 835                 }
 836 #endif /* IXGBE_FCOE */
 837                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 838
 839 next_desc:
 840                 rx_desc->wb.upper.status_error = 0;
 841
 842                 /* return some buffers to hardware, one at a time is too slow */
 843                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 844                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 845                         cleaned_count = 0;
 846                 }
 847
 848                 /* use prefetched values */
 849                 rx_desc = next_rxd;
 850                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 851
 852                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 853         }
 854
 855         rx_ring->next_to_clean = i;
 856         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 857
 858         if (cleaned_count)
 859                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 860
 861 #ifdef IXGBE_FCOE
 862         /* include DDPed FCoE data */
 863         if (ddp_bytes > 0) {
 864                 unsigned int mss;
 865
 866                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 867                         sizeof(struct fc_frame_header) -
 868                         sizeof(struct fcoe_crc_eof);
 869                 if (mss > 512)
 870                         mss &= ~511;
 871                 total_rx_bytes += ddp_bytes;
 872                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 873         }
 874 #endif /* IXGBE_FCOE */
 875
 876         rx_ring->total_packets += total_rx_packets;
 877         rx_ring->total_bytes += total_rx_bytes;
 878         netdev->stats.rx_bytes += total_rx_bytes;
 879         netdev->stats.rx_packets += total_rx_packets;
 880
 881         return cleaned;
 882 }
 883
 884 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 885 /**
 886  * ixgbe_configure_msix - Configure MSI-X hardware
 887  * @adapter: board private structure
 888  *
 889  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 890  * interrupts.
 891  **/
 892 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 893 {
 894         struct ixgbe_q_vector *q_vector;
 895         int i, j, q_vectors, v_idx, r_idx;
 896         u32 mask;
 897
 898         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 899
 900         /*
 901          * Populate the IVAR table and set the ITR values to the
 902          * corresponding register.
 903          */
 904         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 905                 q_vector = adapter->q_vector[v_idx];
 906                 /* XXX for_each_bit(...) */
 907                 r_idx = find_first_bit(q_vector->rxr_idx,
 908                                        adapter->num_rx_queues);
 909
 910                 for (i = 0; i < q_vector->rxr_count; i++) {
 911                         j = adapter->rx_ring[r_idx].reg_idx;
 912                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 913                         r_idx = find_next_bit(q_vector->rxr_idx,
 914                                               adapter->num_rx_queues,
 915                                               r_idx + 1);
 916                 }
 917                 r_idx = find_first_bit(q_vector->txr_idx,
 918                                        adapter->num_tx_queues);
 919
 920                 for (i = 0; i < q_vector->txr_count; i++) {
 921                         j = adapter->tx_ring[r_idx].reg_idx;
 922                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 923                         r_idx = find_next_bit(q_vector->txr_idx,
 924                                               adapter->num_tx_queues,
 925                                               r_idx + 1);
 926                 }
 927
 928                 if (q_vector->txr_count && !q_vector->rxr_count)
 929                         /* tx only */
 930                         q_vector->eitr = adapter->tx_eitr_param;
 931                 else if (q_vector->rxr_count)
 932                         /* rx or mixed */
 933                         q_vector->eitr = adapter->rx_eitr_param;
 934
 935                 ixgbe_write_eitr(q_vector);
 936         }
 937
 938         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 939                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 940                                v_idx);
 941         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 942                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 943         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 944
 945         /* set up to autoclear timer, and the vectors */
 946         mask = IXGBE_EIMS_ENABLE_MASK;
 947         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 948         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 949 }
 950
 951 enum latency_range {
 952         lowest_latency = 0,
 953         low_latency = 1,
 954         bulk_latency = 2,
 955         latency_invalid = 255
 956 };
 957
 958 /**
 959  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 960  * @adapter: pointer to adapter
 961  * @eitr: eitr setting (ints per sec) to give last timeslice
 962  * @itr_setting: current throttle rate in ints/second
 963  * @packets: the number of packets during this measurement interval
 964  * @bytes: the number of bytes during this measurement interval
 965  *
 966  *      Stores a new ITR value based on packets and byte
 967  *      counts during the last interrupt.  The advantage of per interrupt
 968  *      computation is faster updates and more accurate ITR for the current
 969  *      traffic pattern.  Constants in this function were computed
 970  *      based on theoretical maximum wire speed and thresholds were set based
 971  *      on testing data as well as attempting to minimize response time
 972  *      while increasing bulk throughput.
 973  *      this functionality is controlled by the InterruptThrottleRate module
 974  *      parameter (see ixgbe_param.c)
 975  **/
 976 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 977                            u32 eitr, u8 itr_setting,
 978                            int packets, int bytes)
 979 {
 980         unsigned int retval = itr_setting;
 981         u32 timepassed_us;
 982         u64 bytes_perint;
 983
 984         if (packets == 0)
 985                 goto update_itr_done;
 986
 987
 988         /* simple throttlerate management
 989          *    0-20MB/s lowest (100000 ints/s)
 990          *   20-100MB/s low   (20000 ints/s)
 991          *  100-1249MB/s bulk (8000 ints/s)
 992          */
 993         /* what was last interrupt timeslice? */
 994         timepassed_us = 1000000/eitr;
 995         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 996
 997         switch (itr_setting) {
 998         case lowest_latency:
 999                 if (bytes_perint > adapter->eitr_low)
1000                         retval = low_latency;
1001                 break;
1002         case low_latency:
1003                 if (bytes_perint > adapter->eitr_high)
1004                         retval = bulk_latency;
1005                 else if (bytes_perint <= adapter->eitr_low)
1006                         retval = lowest_latency;
1007                 break;
1008         case bulk_latency:
1009                 if (bytes_perint <= adapter->eitr_high)
1010                         retval = low_latency;
1011                 break;
1012         }
1013
1014 update_itr_done:
1015         return retval;
1016 }
1017
1018 /**
1019  * ixgbe_write_eitr - write EITR register in hardware specific way
1020  * @q_vector: structure containing interrupt and ring information
1021  *
1022  * This function is made to be called by ethtool and by the driver
1023  * when it needs to update EITR registers at runtime.  Hardware
1024  * specific quirks/differences are taken care of here.
1025  */
1026 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1027 {
1028         struct ixgbe_adapter *adapter = q_vector->adapter;
1029         struct ixgbe_hw *hw = &adapter->hw;
1030         int v_idx = q_vector->v_idx;
1031         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1032
1033         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1034                 /* must write high and low 16 bits to reset counter */
1035                 itr_reg |= (itr_reg << 16);
1036         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1037                 /*
1038                  * set the WDIS bit to not clear the timer bits and cause an
1039                  * immediate assertion of the interrupt
1040                  */
1041                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1042         }
1043         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1044 }
1045
1046 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1047 {
1048         struct ixgbe_adapter *adapter = q_vector->adapter;
1049         u32 new_itr;
1050         u8 current_itr, ret_itr;
1051         int i, r_idx;
1052         struct ixgbe_ring *rx_ring, *tx_ring;
1053
1054         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1055         for (i = 0; i < q_vector->txr_count; i++) {
1056                 tx_ring = &(adapter->tx_ring[r_idx]);
1057                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1058                                            q_vector->tx_itr,
1059                                            tx_ring->total_packets,
1060                                            tx_ring->total_bytes);
1061                 /* if the result for this queue would decrease interrupt
1062                  * rate for this vector then use that result */
1063                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1064                                     q_vector->tx_itr - 1 : ret_itr);
1065                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1066                                       r_idx + 1);
1067         }
1068
1069         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1070         for (i = 0; i < q_vector->rxr_count; i++) {
1071                 rx_ring = &(adapter->rx_ring[r_idx]);
1072                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1073                                            q_vector->rx_itr,
1074                                            rx_ring->total_packets,
1075                                            rx_ring->total_bytes);
1076                 /* if the result for this queue would decrease interrupt
1077                  * rate for this vector then use that result */
1078                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1079                                     q_vector->rx_itr - 1 : ret_itr);
1080                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1081                                       r_idx + 1);
1082         }
1083
1084         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1085
1086         switch (current_itr) {
1087         /* counts and packets in update_itr are dependent on these numbers */
1088         case lowest_latency:
1089                 new_itr = 100000;
1090                 break;
1091         case low_latency:
1092                 new_itr = 20000; /* aka hwitr = ~200 */
1093                 break;
1094         case bulk_latency:
1095         default:
1096                 new_itr = 8000;
1097                 break;
1098         }
1099
1100         if (new_itr != q_vector->eitr) {
1101                 /* do an exponential smoothing */
1102                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1103
1104                 /* save the algorithm value here, not the smoothed one */
1105                 q_vector->eitr = new_itr;
1106
1107                 ixgbe_write_eitr(q_vector);
1108         }
1109
1110         return;
1111 }
1112
1113 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1114 {
1115         struct ixgbe_hw *hw = &adapter->hw;
1116
1117         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1118             (eicr & IXGBE_EICR_GPI_SDP1)) {
1119                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1120                 /* write to clear the interrupt */
1121                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1122         }
1123 }
1124
1125 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1126 {
1127         struct ixgbe_hw *hw = &adapter->hw;
1128
1129         if (eicr & IXGBE_EICR_GPI_SDP1) {
1130                 /* Clear the interrupt */
1131                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1132                 schedule_work(&adapter->multispeed_fiber_task);
1133         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1134                 /* Clear the interrupt */
1135                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1136                 schedule_work(&adapter->sfp_config_module_task);
1137         } else {
1138                 /* Interrupt isn't for us... */
1139                 return;
1140         }
1141 }
1142
1143 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1144 {
1145         struct ixgbe_hw *hw = &adapter->hw;
1146
1147         adapter->lsc_int++;
1148         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1149         adapter->link_check_timeout = jiffies;
1150         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1151                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1152                 schedule_work(&adapter->watchdog_task);
1153         }
1154 }
1155
1156 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1157 {
1158         struct net_device *netdev = data;
1159         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1160         struct ixgbe_hw *hw = &adapter->hw;
1161         u32 eicr;
1162
1163         /*
1164          * Workaround for Silicon errata.  Use clear-by-write instead
1165          * of clear-by-read.  Reading with EICS will return the
1166          * interrupt causes without clearing, which later be done
1167          * with the write to EICR.
1168          */
1169         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1170         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1171
1172         if (eicr & IXGBE_EICR_LSC)
1173                 ixgbe_check_lsc(adapter);
1174
1175         if (hw->mac.type == ixgbe_mac_82598EB)
1176                 ixgbe_check_fan_failure(adapter, eicr);
1177
1178         if (hw->mac.type == ixgbe_mac_82599EB) {
1179                 ixgbe_check_sfp_event(adapter, eicr);
1180
1181                 /* Handle Flow Director Full threshold interrupt */
1182                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1183                         int i;
1184                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1185                         /* Disable transmits before FDIR Re-initialization */
1186                         netif_tx_stop_all_queues(netdev);
1187                         for (i = 0; i < adapter->num_tx_queues; i++) {
1188                                 struct ixgbe_ring *tx_ring =
1189                                                            &adapter->tx_ring[i];
1190                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1191                                                        &tx_ring->reinit_state))
1192                                         schedule_work(&adapter->fdir_reinit_task);
1193                         }
1194                 }
1195         }
1196         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1197                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1198
1199         return IRQ_HANDLED;
1200 }
1201
1202 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1203                                            u64 qmask)
1204 {
1205         u32 mask;
1206
1207         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1208                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1209                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1210         } else {
1211                 mask = (qmask & 0xFFFFFFFF);
1212                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1213                 mask = (qmask >> 32);
1214                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1215         }
1216         /* skip the flush */
1217 }
1218
1219 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1220                                             u64 qmask)
1221 {
1222         u32 mask;
1223
1224         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1225                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1226                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1227         } else {
1228                 mask = (qmask & 0xFFFFFFFF);
1229                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1230                 mask = (qmask >> 32);
1231                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1232         }
1233         /* skip the flush */
1234 }
1235
1236 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1237 {
1238         struct ixgbe_q_vector *q_vector = data;
1239         struct ixgbe_adapter  *adapter = q_vector->adapter;
1240         struct ixgbe_ring     *tx_ring;
1241         int i, r_idx;
1242
1243         if (!q_vector->txr_count)
1244                 return IRQ_HANDLED;
1245
1246         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1247         for (i = 0; i < q_vector->txr_count; i++) {
1248                 tx_ring = &(adapter->tx_ring[r_idx]);
1249                 tx_ring->total_bytes = 0;
1250                 tx_ring->total_packets = 0;
1251                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1252                                       r_idx + 1);
1253         }
1254
1255         /* disable interrupts on this vector only */
1256         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1257         napi_schedule(&q_vector->napi);
1258
1259         return IRQ_HANDLED;
1260 }
1261
1262 /**
1263  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1264  * @irq: unused
1265  * @data: pointer to our q_vector struct for this interrupt vector
1266  **/
1267 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1268 {
1269         struct ixgbe_q_vector *q_vector = data;
1270         struct ixgbe_adapter  *adapter = q_vector->adapter;
1271         struct ixgbe_ring  *rx_ring;
1272         int r_idx;
1273         int i;
1274
1275         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1276         for (i = 0;  i < q_vector->rxr_count; i++) {
1277                 rx_ring = &(adapter->rx_ring[r_idx]);
1278                 rx_ring->total_bytes = 0;
1279                 rx_ring->total_packets = 0;
1280                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1281                                       r_idx + 1);
1282         }
1283
1284         if (!q_vector->rxr_count)
1285                 return IRQ_HANDLED;
1286
1287         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1288         rx_ring = &(adapter->rx_ring[r_idx]);
1289         /* disable interrupts on this vector only */
1290         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1291         napi_schedule(&q_vector->napi);
1292
1293         return IRQ_HANDLED;
1294 }
1295
1296 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1297 {
1298         struct ixgbe_q_vector *q_vector = data;
1299         struct ixgbe_adapter  *adapter = q_vector->adapter;
1300         struct ixgbe_ring  *ring;
1301         int r_idx;
1302         int i;
1303
1304         if (!q_vector->txr_count && !q_vector->rxr_count)
1305                 return IRQ_HANDLED;
1306
1307         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1308         for (i = 0; i < q_vector->txr_count; i++) {
1309                 ring = &(adapter->tx_ring[r_idx]);
1310                 ring->total_bytes = 0;
1311                 ring->total_packets = 0;
1312                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1313                                       r_idx + 1);
1314         }
1315
1316         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1317         for (i = 0; i < q_vector->rxr_count; i++) {
1318                 ring = &(adapter->rx_ring[r_idx]);
1319                 ring->total_bytes = 0;
1320                 ring->total_packets = 0;
1321                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1322                                       r_idx + 1);
1323         }
1324
1325         /* disable interrupts on this vector only */
1326         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1327         napi_schedule(&q_vector->napi);
1328
1329         return IRQ_HANDLED;
1330 }
1331
1332 /**
1333  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1334  * @napi: napi struct with our devices info in it
1335  * @budget: amount of work driver is allowed to do this pass, in packets
1336  *
1337  * This function is optimized for cleaning one queue only on a single
1338  * q_vector!!!
1339  **/
1340 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1341 {
1342         struct ixgbe_q_vector *q_vector =
1343                                container_of(napi, struct ixgbe_q_vector, napi);
1344         struct ixgbe_adapter *adapter = q_vector->adapter;
1345         struct ixgbe_ring *rx_ring = NULL;
1346         int work_done = 0;
1347         long r_idx;
1348
1349         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1350         rx_ring = &(adapter->rx_ring[r_idx]);
1351 #ifdef CONFIG_IXGBE_DCA
1352         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1353                 ixgbe_update_rx_dca(adapter, rx_ring);
1354 #endif
1355
1356         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1357
1358         /* If all Rx work done, exit the polling mode */
1359         if (work_done < budget) {
1360                 napi_complete(napi);
1361                 if (adapter->rx_itr_setting & 1)
1362                         ixgbe_set_itr_msix(q_vector);
1363                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1364                         ixgbe_irq_enable_queues(adapter,
1365                                                 ((u64)1 << q_vector->v_idx));
1366         }
1367
1368         return work_done;
1369 }
1370
1371 /**
1372  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1373  * @napi: napi struct with our devices info in it
1374  * @budget: amount of work driver is allowed to do this pass, in packets
1375  *
1376  * This function will clean more than one rx queue associated with a
1377  * q_vector.
1378  **/
1379 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1380 {
1381         struct ixgbe_q_vector *q_vector =
1382                                container_of(napi, struct ixgbe_q_vector, napi);
1383         struct ixgbe_adapter *adapter = q_vector->adapter;
1384         struct ixgbe_ring *ring = NULL;
1385         int work_done = 0, i;
1386         long r_idx;
1387         bool tx_clean_complete = true;
1388
1389         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1390         for (i = 0; i < q_vector->txr_count; i++) {
1391                 ring = &(adapter->tx_ring[r_idx]);
1392 #ifdef CONFIG_IXGBE_DCA
1393                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1394                         ixgbe_update_tx_dca(adapter, ring);
1395 #endif
1396                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1397                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1398                                       r_idx + 1);
1399         }
1400
1401         /* attempt to distribute budget to each queue fairly, but don't allow
1402          * the budget to go below 1 because we'll exit polling */
1403         budget /= (q_vector->rxr_count ?: 1);
1404         budget = max(budget, 1);
1405         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1406         for (i = 0; i < q_vector->rxr_count; i++) {
1407                 ring = &(adapter->rx_ring[r_idx]);
1408 #ifdef CONFIG_IXGBE_DCA
1409                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1410                         ixgbe_update_rx_dca(adapter, ring);
1411 #endif
1412                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1413                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1414                                       r_idx + 1);
1415         }
1416
1417         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1418         ring = &(adapter->rx_ring[r_idx]);
1419         /* If all Rx work done, exit the polling mode */
1420         if (work_done < budget) {
1421                 napi_complete(napi);
1422                 if (adapter->rx_itr_setting & 1)
1423                         ixgbe_set_itr_msix(q_vector);
1424                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1425                         ixgbe_irq_enable_queues(adapter,
1426                                                 ((u64)1 << q_vector->v_idx));
1427                 return 0;
1428         }
1429
1430         return work_done;
1431 }
1432
1433 /**
1434  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1435  * @napi: napi struct with our devices info in it
1436  * @budget: amount of work driver is allowed to do this pass, in packets
1437  *
1438  * This function is optimized for cleaning one queue only on a single
1439  * q_vector!!!
1440  **/
1441 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1442 {
1443         struct ixgbe_q_vector *q_vector =
1444                                container_of(napi, struct ixgbe_q_vector, napi);
1445         struct ixgbe_adapter *adapter = q_vector->adapter;
1446         struct ixgbe_ring *tx_ring = NULL;
1447         int work_done = 0;
1448         long r_idx;
1449
1450         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1451         tx_ring = &(adapter->tx_ring[r_idx]);
1452 #ifdef CONFIG_IXGBE_DCA
1453         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1454                 ixgbe_update_tx_dca(adapter, tx_ring);
1455 #endif
1456
1457         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1458                 work_done = budget;
1459
1460         /* If all Tx work done, exit the polling mode */
1461         if (work_done < budget) {
1462                 napi_complete(napi);
1463                 if (adapter->tx_itr_setting & 1)
1464                         ixgbe_set_itr_msix(q_vector);
1465                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1466                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1467         }
1468
1469         return work_done;
1470 }
1471
1472 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1473                                      int r_idx)
1474 {
1475         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1476
1477         set_bit(r_idx, q_vector->rxr_idx);
1478         q_vector->rxr_count++;
1479 }
1480
1481 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1482                                      int t_idx)
1483 {
1484         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1485
1486         set_bit(t_idx, q_vector->txr_idx);
1487         q_vector->txr_count++;
1488 }
1489
1490 /**
1491  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1492  * @adapter: board private structure to initialize
1493  * @vectors: allotted vector count for descriptor rings
1494  *
1495  * This function maps descriptor rings to the queue-specific vectors
1496  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1497  * one vector per ring/queue, but on a constrained vector budget, we
1498  * group the rings as "efficiently" as possible.  You would add new
1499  * mapping configurations in here.
1500  **/
1501 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1502                                       int vectors)
1503 {
1504         int v_start = 0;
1505         int rxr_idx = 0, txr_idx = 0;
1506         int rxr_remaining = adapter->num_rx_queues;
1507         int txr_remaining = adapter->num_tx_queues;
1508         int i, j;
1509         int rqpv, tqpv;
1510         int err = 0;
1511
1512         /* No mapping required if MSI-X is disabled. */
1513         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1514                 goto out;
1515
1516         /*
1517          * The ideal configuration...
1518          * We have enough vectors to map one per queue.
1519          */
1520         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1521                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1522                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1523
1524                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1525                         map_vector_to_txq(adapter, v_start, txr_idx);
1526
1527                 goto out;
1528         }
1529
1530         /*
1531          * If we don't have enough vectors for a 1-to-1
1532          * mapping, we'll have to group them so there are
1533          * multiple queues per vector.
1534          */
1535         /* Re-adjusting *qpv takes care of the remainder. */
1536         for (i = v_start; i < vectors; i++) {
1537                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1538                 for (j = 0; j < rqpv; j++) {
1539                         map_vector_to_rxq(adapter, i, rxr_idx);
1540                         rxr_idx++;
1541                         rxr_remaining--;
1542                 }
1543         }
1544         for (i = v_start; i < vectors; i++) {
1545                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1546                 for (j = 0; j < tqpv; j++) {
1547                         map_vector_to_txq(adapter, i, txr_idx);
1548                         txr_idx++;
1549                         txr_remaining--;
1550                 }
1551         }
1552
1553 out:
1554         return err;
1555 }
1556
1557 /**
1558  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1559  * @adapter: board private structure
1560  *
1561  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1562  * interrupts from the kernel.
1563  **/
1564 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1565 {
1566         struct net_device *netdev = adapter->netdev;
1567         irqreturn_t (*handler)(int, void *);
1568         int i, vector, q_vectors, err;
1569         int ri=0, ti=0;
1570
1571         /* Decrement for Other and TCP Timer vectors */
1572         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1573
1574         /* Map the Tx/Rx rings to the vectors we were allotted. */
1575         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1576         if (err)
1577                 goto out;
1578
1579 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1580                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1581                          &ixgbe_msix_clean_many)
1582         for (vector = 0; vector < q_vectors; vector++) {
1583                 handler = SET_HANDLER(adapter->q_vector[vector]);
1584
1585                 if(handler == &ixgbe_msix_clean_rx) {
1586                         sprintf(adapter->name[vector], "%s-%s-%d",
1587                                 netdev->name, "rx", ri++);
1588                 }
1589                 else if(handler == &ixgbe_msix_clean_tx) {
1590                         sprintf(adapter->name[vector], "%s-%s-%d",
1591                                 netdev->name, "tx", ti++);
1592                 }
1593                 else
1594                         sprintf(adapter->name[vector], "%s-%s-%d",
1595                                 netdev->name, "TxRx", vector);
1596
1597                 err = request_irq(adapter->msix_entries[vector].vector,
1598                                   handler, 0, adapter->name[vector],
1599                                   adapter->q_vector[vector]);
1600                 if (err) {
1601                         DPRINTK(PROBE, ERR,
1602                                 "request_irq failed for MSIX interrupt "
1603                                 "Error: %d\n", err);
1604                         goto free_queue_irqs;
1605                 }
1606         }
1607
1608         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1609         err = request_irq(adapter->msix_entries[vector].vector,
1610                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1611         if (err) {
1612                 DPRINTK(PROBE, ERR,
1613                         "request_irq for msix_lsc failed: %d\n", err);
1614                 goto free_queue_irqs;
1615         }
1616
1617         return 0;
1618
1619 free_queue_irqs:
1620         for (i = vector - 1; i >= 0; i--)
1621                 free_irq(adapter->msix_entries[--vector].vector,
1622                          adapter->q_vector[i]);
1623         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1624         pci_disable_msix(adapter->pdev);
1625         kfree(adapter->msix_entries);
1626         adapter->msix_entries = NULL;
1627 out:
1628         return err;
1629 }
1630
1631 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1632 {
1633         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1634         u8 current_itr;
1635         u32 new_itr = q_vector->eitr;
1636         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1637         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1638
1639         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1640                                             q_vector->tx_itr,
1641                                             tx_ring->total_packets,
1642                                             tx_ring->total_bytes);
1643         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1644                                             q_vector->rx_itr,
1645                                             rx_ring->total_packets,
1646                                             rx_ring->total_bytes);
1647
1648         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1649
1650         switch (current_itr) {
1651         /* counts and packets in update_itr are dependent on these numbers */
1652         case lowest_latency:
1653                 new_itr = 100000;
1654                 break;
1655         case low_latency:
1656                 new_itr = 20000; /* aka hwitr = ~200 */
1657                 break;
1658         case bulk_latency:
1659                 new_itr = 8000;
1660                 break;
1661         default:
1662                 break;
1663         }
1664
1665         if (new_itr != q_vector->eitr) {
1666                 /* do an exponential smoothing */
1667                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1668
1669                 /* save the algorithm value here, not the smoothed one */
1670                 q_vector->eitr = new_itr;
1671
1672                 ixgbe_write_eitr(q_vector);
1673         }
1674
1675         return;
1676 }
1677
1678 /**
1679  * ixgbe_irq_enable - Enable default interrupt generation settings
1680  * @adapter: board private structure
1681  **/
1682 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1683 {
1684         u32 mask;
1685
1686         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1687         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1688                 mask |= IXGBE_EIMS_GPI_SDP1;
1689         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1690                 mask |= IXGBE_EIMS_ECC;
1691                 mask |= IXGBE_EIMS_GPI_SDP1;
1692                 mask |= IXGBE_EIMS_GPI_SDP2;
1693         }
1694         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1695             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1696                 mask |= IXGBE_EIMS_FLOW_DIR;
1697
1698         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1699         ixgbe_irq_enable_queues(adapter, ~0);
1700         IXGBE_WRITE_FLUSH(&adapter->hw);
1701 }
1702
1703 /**
1704  * ixgbe_intr - legacy mode Interrupt Handler
1705  * @irq: interrupt number
1706  * @data: pointer to a network interface device structure
1707  **/
1708 static irqreturn_t ixgbe_intr(int irq, void *data)
1709 {
1710         struct net_device *netdev = data;
1711         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1712         struct ixgbe_hw *hw = &adapter->hw;
1713         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1714         u32 eicr;
1715
1716         /*
1717          * Workaround for silicon errata.  Mask the interrupts
1718          * before the read of EICR.
1719          */
1720         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1721
1722         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1723          * therefore no explict interrupt disable is necessary */
1724         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1725         if (!eicr) {
1726                 /* shared interrupt alert!
1727                  * make sure interrupts are enabled because the read will
1728                  * have disabled interrupts due to EIAM */
1729                 ixgbe_irq_enable(adapter);
1730                 return IRQ_NONE;        /* Not our interrupt */
1731         }
1732
1733         if (eicr & IXGBE_EICR_LSC)
1734                 ixgbe_check_lsc(adapter);
1735
1736         if (hw->mac.type == ixgbe_mac_82599EB)
1737                 ixgbe_check_sfp_event(adapter, eicr);
1738
1739         ixgbe_check_fan_failure(adapter, eicr);
1740
1741         if (napi_schedule_prep(&(q_vector->napi))) {
1742                 adapter->tx_ring[0].total_packets = 0;
1743                 adapter->tx_ring[0].total_bytes = 0;
1744                 adapter->rx_ring[0].total_packets = 0;
1745                 adapter->rx_ring[0].total_bytes = 0;
1746                 /* would disable interrupts here but EIAM disabled it */
1747                 __napi_schedule(&(q_vector->napi));
1748         }
1749
1750         return IRQ_HANDLED;
1751 }
1752
1753 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1754 {
1755         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1756
1757         for (i = 0; i < q_vectors; i++) {
1758                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1759                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1760                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1761                 q_vector->rxr_count = 0;
1762                 q_vector->txr_count = 0;
1763         }
1764 }
1765
1766 /**
1767  * ixgbe_request_irq - initialize interrupts
1768  * @adapter: board private structure
1769  *
1770  * Attempts to configure interrupts using the best available
1771  * capabilities of the hardware and kernel.
1772  **/
1773 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1774 {
1775         struct net_device *netdev = adapter->netdev;
1776         int err;
1777
1778         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1779                 err = ixgbe_request_msix_irqs(adapter);
1780         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1781                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1782                                   netdev->name, netdev);
1783         } else {
1784                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1785                                   netdev->name, netdev);
1786         }
1787
1788         if (err)
1789                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1790
1791         return err;
1792 }
1793
1794 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1795 {
1796         struct net_device *netdev = adapter->netdev;
1797
1798         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1799                 int i, q_vectors;
1800
1801                 q_vectors = adapter->num_msix_vectors;
1802
1803                 i = q_vectors - 1;
1804                 free_irq(adapter->msix_entries[i].vector, netdev);
1805
1806                 i--;
1807                 for (; i >= 0; i--) {
1808                         free_irq(adapter->msix_entries[i].vector,
1809                                  adapter->q_vector[i]);
1810                 }
1811
1812                 ixgbe_reset_q_vectors(adapter);
1813         } else {
1814                 free_irq(adapter->pdev->irq, netdev);
1815         }
1816 }
1817
1818 /**
1819  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1820  * @adapter: board private structure
1821  **/
1822 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1823 {
1824         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1825                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1826         } else {
1827                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1828                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1829                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1830         }
1831         IXGBE_WRITE_FLUSH(&adapter->hw);
1832         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1833                 int i;
1834                 for (i = 0; i < adapter->num_msix_vectors; i++)
1835                         synchronize_irq(adapter->msix_entries[i].vector);
1836         } else {
1837                 synchronize_irq(adapter->pdev->irq);
1838         }
1839 }
1840
1841 /**
1842  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1843  *
1844  **/
1845 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1846 {
1847         struct ixgbe_hw *hw = &adapter->hw;
1848
1849         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1850                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1851
1852         ixgbe_set_ivar(adapter, 0, 0, 0);
1853         ixgbe_set_ivar(adapter, 1, 0, 0);
1854
1855         map_vector_to_rxq(adapter, 0, 0);
1856         map_vector_to_txq(adapter, 0, 0);
1857
1858         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1859 }
1860
1861 /**
1862  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1863  * @adapter: board private structure
1864  *
1865  * Configure the Tx unit of the MAC after a reset.
1866  **/
1867 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1868 {
1869         u64 tdba;
1870         struct ixgbe_hw *hw = &adapter->hw;
1871         u32 i, j, tdlen, txctrl;
1872
1873         /* Setup the HW Tx Head and Tail descriptor pointers */
1874         for (i = 0; i < adapter->num_tx_queues; i++) {
1875                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1876                 j = ring->reg_idx;
1877                 tdba = ring->dma;
1878                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1879                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1880                                 (tdba & DMA_BIT_MASK(32)));
1881                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1882                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1883                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1884                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1885                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1886                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1887                 /*
1888                  * Disable Tx Head Writeback RO bit, since this hoses
1889                  * bookkeeping if things aren't delivered in order.
1890                  */
1891                 switch (hw->mac.type) {
1892                 case ixgbe_mac_82598EB:
1893                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1894                         break;
1895                 case ixgbe_mac_82599EB:
1896                 default:
1897                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1898                         break;
1899                 }
1900                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1901                 switch (hw->mac.type) {
1902                 case ixgbe_mac_82598EB:
1903                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1904                         break;
1905                 case ixgbe_mac_82599EB:
1906                 default:
1907                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1908                         break;
1909                 }
1910         }
1911         if (hw->mac.type == ixgbe_mac_82599EB) {
1912                 /* We enable 8 traffic classes, DCB only */
1913                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1914                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1915                                         IXGBE_MTQC_8TC_8TQ));
1916         }
1917 }
1918
1919 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1920
1921 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1922                                    struct ixgbe_ring *rx_ring)
1923 {
1924         u32 srrctl;
1925         int index;
1926         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1927
1928         index = rx_ring->reg_idx;
1929         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1930                 unsigned long mask;
1931                 mask = (unsigned long) feature[RING_F_RSS].mask;
1932                 index = index & mask;
1933         }
1934         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1935
1936         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1937         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1938
1939         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1940                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1941
1942         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1943 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1944                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1945 #else
1946                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1947 #endif
1948                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1949         } else {
1950                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1951                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1952                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1953         }
1954
1955         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1956 }
1957
1958 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1959 {
1960         u32 mrqc = 0;
1961         int mask;
1962
1963         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1964                 return mrqc;
1965
1966         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1967 #ifdef CONFIG_IXGBE_DCB
1968                                  | IXGBE_FLAG_DCB_ENABLED
1969 #endif
1970                                 );
1971
1972         switch (mask) {
1973         case (IXGBE_FLAG_RSS_ENABLED):
1974                 mrqc = IXGBE_MRQC_RSSEN;
1975                 break;
1976 #ifdef CONFIG_IXGBE_DCB
1977         case (IXGBE_FLAG_DCB_ENABLED):
1978                 mrqc = IXGBE_MRQC_RT8TCEN;
1979                 break;
1980 #endif /* CONFIG_IXGBE_DCB */
1981         default:
1982                 break;
1983         }
1984
1985         return mrqc;
1986 }
1987
1988 /**
1989  * ixgbe_configure_rscctl - enable RSC for the indicated ring
1990  * @adapter:    address of board private structure
1991  * @index:      index of ring to set
1992  * @rx_buf_len: rx buffer length
1993  **/
1994 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
1995                                    int rx_buf_len)
1996 {
1997         struct ixgbe_ring *rx_ring;
1998         struct ixgbe_hw *hw = &adapter->hw;
1999         int j;
2000         u32 rscctrl;
2001
2002         rx_ring = &adapter->rx_ring[index];
2003         j = rx_ring->reg_idx;
2004         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2005         rscctrl |= IXGBE_RSCCTL_RSCEN;
2006         /*
2007          * we must limit the number of descriptors so that the
2008          * total size of max desc * buf_len is not greater
2009          * than 65535
2010          */
2011         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2012 #if (MAX_SKB_FRAGS > 16)
2013                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2014 #elif (MAX_SKB_FRAGS > 8)
2015                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2016 #elif (MAX_SKB_FRAGS > 4)
2017                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2018 #else
2019                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2020 #endif
2021         } else {
2022                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2023                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2024                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2025                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2026                 else
2027                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2028         }
2029         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2030 }
2031
2032 /**
2033  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2034  * @adapter: board private structure
2035  *
2036  * Configure the Rx unit of the MAC after a reset.
2037  **/
2038 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2039 {
2040         u64 rdba;
2041         struct ixgbe_hw *hw = &adapter->hw;
2042         struct ixgbe_ring *rx_ring;
2043         struct net_device *netdev = adapter->netdev;
2044         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2045         int i, j;
2046         u32 rdlen, rxctrl, rxcsum;
2047         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2048                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2049                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2050         u32 fctrl, hlreg0;
2051         u32 reta = 0, mrqc = 0;
2052         u32 rdrxctl;
2053         int rx_buf_len;
2054
2055         /* Decide whether to use packet split mode or not */
2056         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2057
2058         /* Set the RX buffer length according to the mode */
2059         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2060                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2061                 if (hw->mac.type == ixgbe_mac_82599EB) {
2062                         /* PSRTYPE must be initialized in 82599 */
2063                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2064                                       IXGBE_PSRTYPE_UDPHDR |
2065                                       IXGBE_PSRTYPE_IPV4HDR |
2066                                       IXGBE_PSRTYPE_IPV6HDR |
2067                                       IXGBE_PSRTYPE_L2HDR;
2068                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2069                 }
2070         } else {
2071                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2072                     (netdev->mtu <= ETH_DATA_LEN))
2073                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2074                 else
2075                         rx_buf_len = ALIGN(max_frame, 1024);
2076         }
2077
2078         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2079         fctrl |= IXGBE_FCTRL_BAM;
2080         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2081         fctrl |= IXGBE_FCTRL_PMCF;
2082         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2083
2084         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2085         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2086                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2087         else
2088                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2089 #ifdef IXGBE_FCOE
2090         if (netdev->features & NETIF_F_FCOE_MTU)
2091                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2092 #endif
2093         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2094
2095         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2096         /* disable receives while setting up the descriptors */
2097         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2098         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2099
2100         /*
2101          * Setup the HW Rx Head and Tail Descriptor Pointers and
2102          * the Base and Length of the Rx Descriptor Ring
2103          */
2104         for (i = 0; i < adapter->num_rx_queues; i++) {
2105                 rx_ring = &adapter->rx_ring[i];
2106                 rdba = rx_ring->dma;
2107                 j = rx_ring->reg_idx;
2108                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2109                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2110                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2111                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2112                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2113                 rx_ring->head = IXGBE_RDH(j);
2114                 rx_ring->tail = IXGBE_RDT(j);
2115                 rx_ring->rx_buf_len = rx_buf_len;
2116
2117                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2118                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2119                 else
2120                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2121
2122 #ifdef IXGBE_FCOE
2123                 if (netdev->features & NETIF_F_FCOE_MTU) {
2124                         struct ixgbe_ring_feature *f;
2125                         f = &adapter->ring_feature[RING_F_FCOE];
2126                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2127                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2128                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2129                                         rx_ring->rx_buf_len =
2130                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2131                         }
2132                 }
2133
2134 #endif /* IXGBE_FCOE */
2135                 ixgbe_configure_srrctl(adapter, rx_ring);
2136         }
2137
2138         if (hw->mac.type == ixgbe_mac_82598EB) {
2139                 /*
2140                  * For VMDq support of different descriptor types or
2141                  * buffer sizes through the use of multiple SRRCTL
2142                  * registers, RDRXCTL.MVMEN must be set to 1
2143                  *
2144                  * also, the manual doesn't mention it clearly but DCA hints
2145                  * will only use queue 0's tags unless this bit is set.  Side
2146                  * effects of setting this bit are only that SRRCTL must be
2147                  * fully programmed [0..15]
2148                  */
2149                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2150                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2151                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2152         }
2153
2154         /* Program MRQC for the distribution of queues */
2155         mrqc = ixgbe_setup_mrqc(adapter);
2156
2157         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2158                 /* Fill out redirection table */
2159                 for (i = 0, j = 0; i < 128; i++, j++) {
2160                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2161                                 j = 0;
2162                         /* reta = 4-byte sliding window of
2163                          * 0x00..(indices-1)(indices-1)00..etc. */
2164                         reta = (reta << 8) | (j * 0x11);
2165                         if ((i & 3) == 3)
2166                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2167                 }
2168
2169                 /* Fill out hash function seeds */
2170                 for (i = 0; i < 10; i++)
2171                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2172
2173                 if (hw->mac.type == ixgbe_mac_82598EB)
2174                         mrqc |= IXGBE_MRQC_RSSEN;
2175                     /* Perform hash on these packet types */
2176                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2177                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2178                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2179                       | IXGBE_MRQC_RSS_FIELD_IPV6
2180                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2181                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2182         }
2183         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2184
2185         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2186
2187         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2188             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2189                 /* Disable indicating checksum in descriptor, enables
2190                  * RSS hash */
2191                 rxcsum |= IXGBE_RXCSUM_PCSD;
2192         }
2193         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2194                 /* Enable IPv4 payload checksum for UDP fragments
2195                  * if PCSD is not set */
2196                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2197         }
2198
2199         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2200
2201         if (hw->mac.type == ixgbe_mac_82599EB) {
2202                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2203                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2204                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2205                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2206         }
2207
2208         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2209                 /* Enable 82599 HW-RSC */
2210                 for (i = 0; i < adapter->num_rx_queues; i++)
2211                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2212
2213                 /* Disable RSC for ACK packets */
2214                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2215                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2216         }
2217 }
2218
2219 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2220 {
2221         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2222         struct ixgbe_hw *hw = &adapter->hw;
2223
2224         /* add VID to filter table */
2225         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2226 }
2227
2228 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2229 {
2230         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2231         struct ixgbe_hw *hw = &adapter->hw;
2232
2233         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2234                 ixgbe_irq_disable(adapter);
2235
2236         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2237
2238         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2239                 ixgbe_irq_enable(adapter);
2240
2241         /* remove VID from filter table */
2242         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2243 }
2244
2245 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2246                                    struct vlan_group *grp)
2247 {
2248         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2249         u32 ctrl;
2250         int i, j;
2251
2252         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2253                 ixgbe_irq_disable(adapter);
2254         adapter->vlgrp = grp;
2255
2256         /*
2257          * For a DCB driver, always enable VLAN tag stripping so we can
2258          * still receive traffic from a DCB-enabled host even if we're
2259          * not in DCB mode.
2260          */
2261         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2262         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2263                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2264                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2265                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2266         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2267                 ctrl |= IXGBE_VLNCTRL_VFE;
2268                 /* enable VLAN tag insert/strip */
2269                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2270                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2271                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2272                 for (i = 0; i < adapter->num_rx_queues; i++) {
2273                         j = adapter->rx_ring[i].reg_idx;
2274                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2275                         ctrl |= IXGBE_RXDCTL_VME;
2276                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2277                 }
2278         }
2279         ixgbe_vlan_rx_add_vid(netdev, 0);
2280
2281         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2282                 ixgbe_irq_enable(adapter);
2283 }
2284
2285 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2286 {
2287         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2288
2289         if (adapter->vlgrp) {
2290                 u16 vid;
2291                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2292                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2293                                 continue;
2294                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2295                 }
2296         }
2297 }
2298
2299 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2300 {
2301         struct dev_mc_list *mc_ptr;
2302         u8 *addr = *mc_addr_ptr;
2303         *vmdq = 0;
2304
2305         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2306         if (mc_ptr->next)
2307                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2308         else
2309                 *mc_addr_ptr = NULL;
2310
2311         return addr;
2312 }
2313
2314 /**
2315  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2316  * @netdev: network interface device structure
2317  *
2318  * The set_rx_method entry point is called whenever the unicast/multicast
2319  * address list or the network interface flags are updated.  This routine is
2320  * responsible for configuring the hardware for proper unicast, multicast and
2321  * promiscuous mode.
2322  **/
2323 static void ixgbe_set_rx_mode(struct net_device *netdev)
2324 {
2325         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2326         struct ixgbe_hw *hw = &adapter->hw;
2327         u32 fctrl, vlnctrl;
2328         u8 *addr_list = NULL;
2329         int addr_count = 0;
2330
2331         /* Check for Promiscuous and All Multicast modes */
2332
2333         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2334         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2335
2336         if (netdev->flags & IFF_PROMISC) {
2337                 hw->addr_ctrl.user_set_promisc = 1;
2338                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2339                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2340         } else {
2341                 if (netdev->flags & IFF_ALLMULTI) {
2342                         fctrl |= IXGBE_FCTRL_MPE;
2343                         fctrl &= ~IXGBE_FCTRL_UPE;
2344                 } else {
2345                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2346                 }
2347                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2348                 hw->addr_ctrl.user_set_promisc = 0;
2349         }
2350
2351         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2352         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2353
2354         /* reprogram secondary unicast list */
2355         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2356
2357         /* reprogram multicast list */
2358         addr_count = netdev->mc_count;
2359         if (addr_count)
2360                 addr_list = netdev->mc_list->dmi_addr;
2361         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2362                                         ixgbe_addr_list_itr);
2363 }
2364
2365 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2366 {
2367         int q_idx;
2368         struct ixgbe_q_vector *q_vector;
2369         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2370
2371         /* legacy and MSI only use one vector */
2372         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2373                 q_vectors = 1;
2374
2375         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2376                 struct napi_struct *napi;
2377                 q_vector = adapter->q_vector[q_idx];
2378                 napi = &q_vector->napi;
2379                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2380                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2381                                 if (q_vector->txr_count == 1)
2382                                         napi->poll = &ixgbe_clean_txonly;
2383                                 else if (q_vector->rxr_count == 1)
2384                                         napi->poll = &ixgbe_clean_rxonly;
2385                         }
2386                 }
2387
2388                 napi_enable(napi);
2389         }
2390 }
2391
2392 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2393 {
2394         int q_idx;
2395         struct ixgbe_q_vector *q_vector;
2396         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2397
2398         /* legacy and MSI only use one vector */
2399         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2400                 q_vectors = 1;
2401
2402         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2403                 q_vector = adapter->q_vector[q_idx];
2404                 napi_disable(&q_vector->napi);
2405         }
2406 }
2407
2408 #ifdef CONFIG_IXGBE_DCB
2409 /*
2410  * ixgbe_configure_dcb - Configure DCB hardware
2411  * @adapter: ixgbe adapter struct
2412  *
2413  * This is called by the driver on open to configure the DCB hardware.
2414  * This is also called by the gennetlink interface when reconfiguring
2415  * the DCB state.
2416  */
2417 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2418 {
2419         struct ixgbe_hw *hw = &adapter->hw;
2420         u32 txdctl, vlnctrl;
2421         int i, j;
2422
2423         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2424         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2425         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2426
2427         /* reconfigure the hardware */
2428         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2429
2430         for (i = 0; i < adapter->num_tx_queues; i++) {
2431                 j = adapter->tx_ring[i].reg_idx;
2432                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2433                 /* PThresh workaround for Tx hang with DFP enabled. */
2434                 txdctl |= 32;
2435                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2436         }
2437         /* Enable VLAN tag insert/strip */
2438         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2439         if (hw->mac.type == ixgbe_mac_82598EB) {
2440                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2441                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2442                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2443         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2444                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2445                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2446                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2447                 for (i = 0; i < adapter->num_rx_queues; i++) {
2448                         j = adapter->rx_ring[i].reg_idx;
2449                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2450                         vlnctrl |= IXGBE_RXDCTL_VME;
2451                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2452                 }
2453         }
2454         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2455 }
2456
2457 #endif
2458 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2459 {
2460         struct net_device *netdev = adapter->netdev;
2461         struct ixgbe_hw *hw = &adapter->hw;
2462         int i;
2463
2464         ixgbe_set_rx_mode(netdev);
2465
2466         ixgbe_restore_vlan(adapter);
2467 #ifdef CONFIG_IXGBE_DCB
2468         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2469                 netif_set_gso_max_size(netdev, 32768);
2470                 ixgbe_configure_dcb(adapter);
2471         } else {
2472                 netif_set_gso_max_size(netdev, 65536);
2473         }
2474 #else
2475         netif_set_gso_max_size(netdev, 65536);
2476 #endif
2477
2478 #ifdef IXGBE_FCOE
2479         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2480                 ixgbe_configure_fcoe(adapter);
2481
2482 #endif /* IXGBE_FCOE */
2483         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2484                 for (i = 0; i < adapter->num_tx_queues; i++)
2485                         adapter->tx_ring[i].atr_sample_rate =
2486                                                        adapter->atr_sample_rate;
2487                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2488         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2489                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2490         }
2491
2492         ixgbe_configure_tx(adapter);
2493         ixgbe_configure_rx(adapter);
2494         for (i = 0; i < adapter->num_rx_queues; i++)
2495                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2496                                        (adapter->rx_ring[i].count - 1));
2497 }
2498
2499 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2500 {
2501         switch (hw->phy.type) {
2502         case ixgbe_phy_sfp_avago:
2503         case ixgbe_phy_sfp_ftl:
2504         case ixgbe_phy_sfp_intel:
2505         case ixgbe_phy_sfp_unknown:
2506         case ixgbe_phy_tw_tyco:
2507         case ixgbe_phy_tw_unknown:
2508                 return true;
2509         default:
2510                 return false;
2511         }
2512 }
2513
2514 /**
2515  * ixgbe_sfp_link_config - set up SFP+ link
2516  * @adapter: pointer to private adapter struct
2517  **/
2518 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2519 {
2520         struct ixgbe_hw *hw = &adapter->hw;
2521
2522                 if (hw->phy.multispeed_fiber) {
2523                         /*
2524                          * In multispeed fiber setups, the device may not have
2525                          * had a physical connection when the driver loaded.
2526                          * If that's the case, the initial link configuration
2527                          * couldn't get the MAC into 10G or 1G mode, so we'll
2528                          * never have a link status change interrupt fire.
2529                          * We need to try and force an autonegotiation
2530                          * session, then bring up link.
2531                          */
2532                         hw->mac.ops.setup_sfp(hw);
2533                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2534                                 schedule_work(&adapter->multispeed_fiber_task);
2535                 } else {
2536                         /*
2537                          * Direct Attach Cu and non-multispeed fiber modules
2538                          * still need to be configured properly prior to
2539                          * attempting link.
2540                          */
2541                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2542                                 schedule_work(&adapter->sfp_config_module_task);
2543                 }
2544 }
2545
2546 /**
2547  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2548  * @hw: pointer to private hardware struct
2549  *
2550  * Returns 0 on success, negative on failure
2551  **/
2552 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2553 {
2554         u32 autoneg;
2555         bool negotiation, link_up = false;
2556         u32 ret = IXGBE_ERR_LINK_SETUP;
2557
2558         if (hw->mac.ops.check_link)
2559                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2560
2561         if (ret)
2562                 goto link_cfg_out;
2563
2564         if (hw->mac.ops.get_link_capabilities)
2565                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2566         if (ret)
2567                 goto link_cfg_out;
2568
2569         if (hw->mac.ops.setup_link)
2570                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2571 link_cfg_out:
2572         return ret;
2573 }
2574
2575 #define IXGBE_MAX_RX_DESC_POLL 10
2576 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2577                                               int rxr)
2578 {
2579         int j = adapter->rx_ring[rxr].reg_idx;
2580         int k;
2581
2582         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2583                 if (IXGBE_READ_REG(&adapter->hw,
2584                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2585                         break;
2586                 else
2587                         msleep(1);
2588         }
2589         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2590                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2591                         "not set within the polling period\n", rxr);
2592         }
2593         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2594                               (adapter->rx_ring[rxr].count - 1));
2595 }
2596
2597 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2598 {
2599         struct net_device *netdev = adapter->netdev;
2600         struct ixgbe_hw *hw = &adapter->hw;
2601         int i, j = 0;
2602         int num_rx_rings = adapter->num_rx_queues;
2603         int err;
2604         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2605         u32 txdctl, rxdctl, mhadd;
2606         u32 dmatxctl;
2607         u32 gpie;
2608
2609         ixgbe_get_hw_control(adapter);
2610
2611         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2612             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2613                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2614                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2615                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2616                 } else {
2617                         /* MSI only */
2618                         gpie = 0;
2619                 }
2620                 /* XXX: to interrupt immediately for EICS writes, enable this */
2621                 /* gpie |= IXGBE_GPIE_EIMEN; */
2622                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2623         }
2624
2625         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2626                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2627                  * specifically only auto mask tx and rx interrupts */
2628                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2629         }
2630
2631         /* Enable fan failure interrupt if media type is copper */
2632         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2633                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2634                 gpie |= IXGBE_SDP1_GPIEN;
2635                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2636         }
2637
2638         if (hw->mac.type == ixgbe_mac_82599EB) {
2639                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2640                 gpie |= IXGBE_SDP1_GPIEN;
2641                 gpie |= IXGBE_SDP2_GPIEN;
2642                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2643         }
2644
2645 #ifdef IXGBE_FCOE
2646         /* adjust max frame to be able to do baby jumbo for FCoE */
2647         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2648             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2649                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2650
2651 #endif /* IXGBE_FCOE */
2652         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2653         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2654                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2655                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2656
2657                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2658         }
2659
2660         for (i = 0; i < adapter->num_tx_queues; i++) {
2661                 j = adapter->tx_ring[i].reg_idx;
2662                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2663                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2664                 txdctl |= (8 << 16);
2665                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2666         }
2667
2668         if (hw->mac.type == ixgbe_mac_82599EB) {
2669                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2670                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2671                 dmatxctl |= IXGBE_DMATXCTL_TE;
2672                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2673         }
2674         for (i = 0; i < adapter->num_tx_queues; i++) {
2675                 j = adapter->tx_ring[i].reg_idx;
2676                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2677                 txdctl |= IXGBE_TXDCTL_ENABLE;
2678                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2679         }
2680
2681         for (i = 0; i < num_rx_rings; i++) {
2682                 j = adapter->rx_ring[i].reg_idx;
2683                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2684                 /* enable PTHRESH=32 descriptors (half the internal cache)
2685                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2686                  * this also removes a pesky rx_no_buffer_count increment */
2687                 rxdctl |= 0x0020;
2688                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2689                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2690                 if (hw->mac.type == ixgbe_mac_82599EB)
2691                         ixgbe_rx_desc_queue_enable(adapter, i);
2692         }
2693         /* enable all receives */
2694         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2695         if (hw->mac.type == ixgbe_mac_82598EB)
2696                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2697         else
2698                 rxdctl |= IXGBE_RXCTRL_RXEN;
2699         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2700
2701         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2702                 ixgbe_configure_msix(adapter);
2703         else
2704                 ixgbe_configure_msi_and_legacy(adapter);
2705
2706         clear_bit(__IXGBE_DOWN, &adapter->state);
2707         ixgbe_napi_enable_all(adapter);
2708
2709         /* clear any pending interrupts, may auto mask */
2710         IXGBE_READ_REG(hw, IXGBE_EICR);
2711
2712         ixgbe_irq_enable(adapter);
2713
2714         /*
2715          * If this adapter has a fan, check to see if we had a failure
2716          * before we enabled the interrupt.
2717          */
2718         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2719                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2720                 if (esdp & IXGBE_ESDP_SDP1)
2721                         DPRINTK(DRV, CRIT,
2722                                 "Fan has stopped, replace the adapter\n");
2723         }
2724
2725         /*
2726          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2727          * arrived before interrupts were enabled but after probe.  Such
2728          * devices wouldn't have their type identified yet. We need to
2729          * kick off the SFP+ module setup first, then try to bring up link.
2730          * If we're not hot-pluggable SFP+, we just need to configure link
2731          * and bring it up.
2732          */
2733         if (hw->phy.type == ixgbe_phy_unknown) {
2734                 err = hw->phy.ops.identify(hw);
2735                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2736                         /*
2737                          * Take the device down and schedule the sfp tasklet
2738                          * which will unregister_netdev and log it.
2739                          */
2740                         ixgbe_down(adapter);
2741                         schedule_work(&adapter->sfp_config_module_task);
2742                         return err;
2743                 }
2744         }
2745
2746         if (ixgbe_is_sfp(hw)) {
2747                 ixgbe_sfp_link_config(adapter);
2748         } else {
2749                 err = ixgbe_non_sfp_link_config(hw);
2750                 if (err)
2751                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2752         }
2753
2754         for (i = 0; i < adapter->num_tx_queues; i++)
2755                 set_bit(__IXGBE_FDIR_INIT_DONE,
2756                         &(adapter->tx_ring[i].reinit_state));
2757
2758         /* enable transmits */
2759         netif_tx_start_all_queues(netdev);
2760
2761         /* bring the link up in the watchdog, this could race with our first
2762          * link up interrupt but shouldn't be a problem */
2763         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2764         adapter->link_check_timeout = jiffies;
2765         mod_timer(&adapter->watchdog_timer, jiffies);
2766         return 0;
2767 }
2768
2769 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2770 {
2771         WARN_ON(in_interrupt());
2772         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2773                 msleep(1);
2774         ixgbe_down(adapter);
2775         ixgbe_up(adapter);
2776         clear_bit(__IXGBE_RESETTING, &adapter->state);
2777 }
2778
2779 int ixgbe_up(struct ixgbe_adapter *adapter)
2780 {
2781         /* hardware has been reset, we need to reload some things */
2782         ixgbe_configure(adapter);
2783
2784         return ixgbe_up_complete(adapter);
2785 }
2786
2787 void ixgbe_reset(struct ixgbe_adapter *adapter)
2788 {
2789         struct ixgbe_hw *hw = &adapter->hw;
2790         int err;
2791
2792         err = hw->mac.ops.init_hw(hw);
2793         switch (err) {
2794         case 0:
2795         case IXGBE_ERR_SFP_NOT_PRESENT:
2796                 break;
2797         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2798                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2799                 break;
2800         case IXGBE_ERR_EEPROM_VERSION:
2801                 /* We are running on a pre-production device, log a warning */
2802                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2803                          "adapter/LOM.  Please be aware there may be issues "
2804                          "associated with your hardware.  If you are "
2805                          "experiencing problems please contact your Intel or "
2806                          "hardware representative who provided you with this "
2807                          "hardware.\n");
2808                 break;
2809         default:
2810                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2811         }
2812
2813         /* reprogram the RAR[0] in case user changed it. */
2814         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2815 }
2816
2817 /**
2818  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2819  * @adapter: board private structure
2820  * @rx_ring: ring to free buffers from
2821  **/
2822 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2823                                 struct ixgbe_ring *rx_ring)
2824 {
2825         struct pci_dev *pdev = adapter->pdev;
2826         unsigned long size;
2827         unsigned int i;
2828
2829         /* Free all the Rx ring sk_buffs */
2830
2831         for (i = 0; i < rx_ring->count; i++) {
2832                 struct ixgbe_rx_buffer *rx_buffer_info;
2833
2834                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2835                 if (rx_buffer_info->dma) {
2836                         pci_unmap_single(pdev, rx_buffer_info->dma,
2837                                          rx_ring->rx_buf_len,
2838                                          PCI_DMA_FROMDEVICE);
2839                         rx_buffer_info->dma = 0;
2840                 }
2841                 if (rx_buffer_info->skb) {
2842                         struct sk_buff *skb = rx_buffer_info->skb;
2843                         rx_buffer_info->skb = NULL;
2844                         do {
2845                                 struct sk_buff *this = skb;
2846                                 skb = skb->prev;
2847                                 dev_kfree_skb(this);
2848                         } while (skb);
2849                 }
2850                 if (!rx_buffer_info->page)
2851                         continue;
2852                 if (rx_buffer_info->page_dma) {
2853                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2854                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2855                         rx_buffer_info->page_dma = 0;
2856                 }
2857                 put_page(rx_buffer_info->page);
2858                 rx_buffer_info->page = NULL;
2859                 rx_buffer_info->page_offset = 0;
2860         }
2861
2862         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2863         memset(rx_ring->rx_buffer_info, 0, size);
2864
2865         /* Zero out the descriptor ring */
2866         memset(rx_ring->desc, 0, rx_ring->size);
2867
2868         rx_ring->next_to_clean = 0;
2869         rx_ring->next_to_use = 0;
2870
2871         if (rx_ring->head)
2872                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2873         if (rx_ring->tail)
2874                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2875 }
2876
2877 /**
2878  * ixgbe_clean_tx_ring - Free Tx Buffers
2879  * @adapter: board private structure
2880  * @tx_ring: ring to be cleaned
2881  **/
2882 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2883                                 struct ixgbe_ring *tx_ring)
2884 {
2885         struct ixgbe_tx_buffer *tx_buffer_info;
2886         unsigned long size;
2887         unsigned int i;
2888
2889         /* Free all the Tx ring sk_buffs */
2890
2891         for (i = 0; i < tx_ring->count; i++) {
2892                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2893                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2894         }
2895
2896         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2897         memset(tx_ring->tx_buffer_info, 0, size);
2898
2899         /* Zero out the descriptor ring */
2900         memset(tx_ring->desc, 0, tx_ring->size);
2901
2902         tx_ring->next_to_use = 0;
2903         tx_ring->next_to_clean = 0;
2904
2905         if (tx_ring->head)
2906                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2907         if (tx_ring->tail)
2908                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2909 }
2910
2911 /**
2912  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2913  * @adapter: board private structure
2914  **/
2915 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2916 {
2917         int i;
2918
2919         for (i = 0; i < adapter->num_rx_queues; i++)
2920                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2921 }
2922
2923 /**
2924  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2925  * @adapter: board private structure
2926  **/
2927 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2928 {
2929         int i;
2930
2931         for (i = 0; i < adapter->num_tx_queues; i++)
2932                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2933 }
2934
2935 void ixgbe_down(struct ixgbe_adapter *adapter)
2936 {
2937         struct net_device *netdev = adapter->netdev;
2938         struct ixgbe_hw *hw = &adapter->hw;
2939         u32 rxctrl;
2940         u32 txdctl;
2941         int i, j;
2942
2943         /* signal that we are down to the interrupt handler */
2944         set_bit(__IXGBE_DOWN, &adapter->state);
2945
2946         /* disable receives */
2947         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2948         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2949
2950         netif_tx_disable(netdev);
2951
2952         IXGBE_WRITE_FLUSH(hw);
2953         msleep(10);
2954
2955         netif_tx_stop_all_queues(netdev);
2956
2957         ixgbe_irq_disable(adapter);
2958
2959         ixgbe_napi_disable_all(adapter);
2960
2961         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2962         del_timer_sync(&adapter->sfp_timer);
2963         del_timer_sync(&adapter->watchdog_timer);
2964         cancel_work_sync(&adapter->watchdog_task);
2965
2966         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2967             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2968                 cancel_work_sync(&adapter->fdir_reinit_task);
2969
2970         /* disable transmits in the hardware now that interrupts are off */
2971         for (i = 0; i < adapter->num_tx_queues; i++) {
2972                 j = adapter->tx_ring[i].reg_idx;
2973                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2974                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2975                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2976         }
2977         /* Disable the Tx DMA engine on 82599 */
2978         if (hw->mac.type == ixgbe_mac_82599EB)
2979                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2980                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2981                                  ~IXGBE_DMATXCTL_TE));
2982
2983         netif_carrier_off(netdev);
2984
2985         if (!pci_channel_offline(adapter->pdev))
2986                 ixgbe_reset(adapter);
2987         ixgbe_clean_all_tx_rings(adapter);
2988         ixgbe_clean_all_rx_rings(adapter);
2989
2990 #ifdef CONFIG_IXGBE_DCA
2991         /* since we reset the hardware DCA settings were cleared */
2992         ixgbe_setup_dca(adapter);
2993 #endif
2994 }
2995
2996 /**
2997  * ixgbe_poll - NAPI Rx polling callback
2998  * @napi: structure for representing this polling device
2999  * @budget: how many packets driver is allowed to clean
3000  *
3001  * This function is used for legacy and MSI, NAPI mode
3002  **/
3003 static int ixgbe_poll(struct napi_struct *napi, int budget)
3004 {
3005         struct ixgbe_q_vector *q_vector =
3006                                 container_of(napi, struct ixgbe_q_vector, napi);
3007         struct ixgbe_adapter *adapter = q_vector->adapter;
3008         int tx_clean_complete, work_done = 0;
3009
3010 #ifdef CONFIG_IXGBE_DCA
3011         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3012                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3013                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3014         }
3015 #endif
3016
3017         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3018         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3019
3020         if (!tx_clean_complete)
3021                 work_done = budget;
3022
3023         /* If budget not fully consumed, exit the polling mode */
3024         if (work_done < budget) {
3025                 napi_complete(napi);
3026                 if (adapter->rx_itr_setting & 1)
3027                         ixgbe_set_itr(adapter);
3028                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3029                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3030         }
3031         return work_done;
3032 }
3033
3034 /**
3035  * ixgbe_tx_timeout - Respond to a Tx Hang
3036  * @netdev: network interface device structure
3037  **/
3038 static void ixgbe_tx_timeout(struct net_device *netdev)
3039 {
3040         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3041
3042         /* Do the reset outside of interrupt context */
3043         schedule_work(&adapter->reset_task);
3044 }
3045
3046 static void ixgbe_reset_task(struct work_struct *work)
3047 {
3048         struct ixgbe_adapter *adapter;
3049         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3050
3051         /* If we're already down or resetting, just bail */
3052         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3053             test_bit(__IXGBE_RESETTING, &adapter->state))
3054                 return;
3055
3056         adapter->tx_timeout_count++;
3057
3058         ixgbe_reinit_locked(adapter);
3059 }
3060
3061 #ifdef CONFIG_IXGBE_DCB
3062 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3063 {
3064         bool ret = false;
3065         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3066
3067         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3068                 return ret;
3069
3070         f->mask = 0x7 << 3;
3071         adapter->num_rx_queues = f->indices;
3072         adapter->num_tx_queues = f->indices;
3073         ret = true;
3074
3075         return ret;
3076 }
3077 #endif
3078
3079 /**
3080  * ixgbe_set_rss_queues: Allocate queues for RSS
3081  * @adapter: board private structure to initialize
3082  *
3083  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3084  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3085  *
3086  **/
3087 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3088 {
3089         bool ret = false;
3090         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3091
3092         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3093                 f->mask = 0xF;
3094                 adapter->num_rx_queues = f->indices;
3095                 adapter->num_tx_queues = f->indices;
3096                 ret = true;
3097         } else {
3098                 ret = false;
3099         }
3100
3101         return ret;
3102 }
3103
3104 /**
3105  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3106  * @adapter: board private structure to initialize
3107  *
3108  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3109  * to the original CPU that initiated the Tx session.  This runs in addition
3110  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3111  * Rx load across CPUs using RSS.
3112  *
3113  **/
3114 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3115 {
3116         bool ret = false;
3117         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3118
3119         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3120         f_fdir->mask = 0;
3121
3122         /* Flow Director must have RSS enabled */
3123         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3124             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3125              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3126                 adapter->num_tx_queues = f_fdir->indices;
3127                 adapter->num_rx_queues = f_fdir->indices;
3128                 ret = true;
3129         } else {
3130                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3131                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3132         }
3133         return ret;
3134 }
3135
3136 #ifdef IXGBE_FCOE
3137 /**
3138  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3139  * @adapter: board private structure to initialize
3140  *
3141  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3142  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3143  * rx queues out of the max number of rx queues, instead, it is used as the
3144  * index of the first rx queue used by FCoE.
3145  *
3146  **/
3147 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3148 {
3149         bool ret = false;
3150         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3151
3152         f->indices = min((int)num_online_cpus(), f->indices);
3153         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3154                 adapter->num_rx_queues = 1;
3155                 adapter->num_tx_queues = 1;
3156 #ifdef CONFIG_IXGBE_DCB
3157                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3158                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3159                         ixgbe_set_dcb_queues(adapter);
3160                 }
3161 #endif
3162                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3163                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3164                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3165                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3166                                 ixgbe_set_fdir_queues(adapter);
3167                         else
3168                                 ixgbe_set_rss_queues(adapter);
3169                 }
3170                 /* adding FCoE rx rings to the end */
3171                 f->mask = adapter->num_rx_queues;
3172                 adapter->num_rx_queues += f->indices;
3173                 adapter->num_tx_queues += f->indices;
3174
3175                 ret = true;
3176         }
3177
3178         return ret;
3179 }
3180
3181 #endif /* IXGBE_FCOE */
3182 /*
3183  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3184  * @adapter: board private structure to initialize
3185  *
3186  * This is the top level queue allocation routine.  The order here is very
3187  * important, starting with the "most" number of features turned on at once,
3188  * and ending with the smallest set of features.  This way large combinations
3189  * can be allocated if they're turned on, and smaller combinations are the
3190  * fallthrough conditions.
3191  *
3192  **/
3193 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3194 {
3195 #ifdef IXGBE_FCOE
3196         if (ixgbe_set_fcoe_queues(adapter))
3197                 goto done;
3198
3199 #endif /* IXGBE_FCOE */
3200 #ifdef CONFIG_IXGBE_DCB
3201         if (ixgbe_set_dcb_queues(adapter))
3202                 goto done;
3203
3204 #endif
3205         if (ixgbe_set_fdir_queues(adapter))
3206                 goto done;
3207
3208         if (ixgbe_set_rss_queues(adapter))
3209                 goto done;
3210
3211         /* fallback to base case */
3212         adapter->num_rx_queues = 1;
3213         adapter->num_tx_queues = 1;
3214
3215 done:
3216         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3217         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3218 }
3219
3220 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3221                                        int vectors)
3222 {
3223         int err, vector_threshold;
3224
3225         /* We'll want at least 3 (vector_threshold):
3226          * 1) TxQ[0] Cleanup
3227          * 2) RxQ[0] Cleanup
3228          * 3) Other (Link Status Change, etc.)
3229          * 4) TCP Timer (optional)
3230          */
3231         vector_threshold = MIN_MSIX_COUNT;
3232
3233         /* The more we get, the more we will assign to Tx/Rx Cleanup
3234          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3235          * Right now, we simply care about how many we'll get; we'll
3236          * set them up later while requesting irq's.
3237          */
3238         while (vectors >= vector_threshold) {
3239                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3240                                       vectors);
3241                 if (!err) /* Success in acquiring all requested vectors. */
3242                         break;
3243                 else if (err < 0)
3244                         vectors = 0; /* Nasty failure, quit now */
3245                 else /* err == number of vectors we should try again with */
3246                         vectors = err;
3247         }
3248
3249         if (vectors < vector_threshold) {
3250                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3251                  * This just means we'll go with either a single MSI
3252                  * vector or fall back to legacy interrupts.
3253                  */
3254                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3255                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3256                 kfree(adapter->msix_entries);
3257                 adapter->msix_entries = NULL;
3258         } else {
3259                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3260                 /*
3261                  * Adjust for only the vectors we'll use, which is minimum
3262                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3263                  * vectors we were allocated.
3264                  */
3265                 adapter->num_msix_vectors = min(vectors,
3266                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3267         }
3268 }
3269
3270 /**
3271  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3272  * @adapter: board private structure to initialize
3273  *
3274  * Cache the descriptor ring offsets for RSS to the assigned rings.
3275  *
3276  **/
3277 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3278 {
3279         int i;
3280         bool ret = false;
3281
3282         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3283                 for (i = 0; i < adapter->num_rx_queues; i++)
3284                         adapter->rx_ring[i].reg_idx = i;
3285                 for (i = 0; i < adapter->num_tx_queues; i++)
3286                         adapter->tx_ring[i].reg_idx = i;
3287                 ret = true;
3288         } else {
3289                 ret = false;
3290         }
3291
3292         return ret;
3293 }
3294
3295 #ifdef CONFIG_IXGBE_DCB
3296 /**
3297  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3298  * @adapter: board private structure to initialize
3299  *
3300  * Cache the descriptor ring offsets for DCB to the assigned rings.
3301  *
3302  **/
3303 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3304 {
3305         int i;
3306         bool ret = false;
3307         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3308
3309         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3310                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3311                         /* the number of queues is assumed to be symmetric */
3312                         for (i = 0; i < dcb_i; i++) {
3313                                 adapter->rx_ring[i].reg_idx = i << 3;
3314                                 adapter->tx_ring[i].reg_idx = i << 2;
3315                         }
3316                         ret = true;
3317                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3318                         if (dcb_i == 8) {
3319                                 /*
3320                                  * Tx TC0 starts at: descriptor queue 0
3321                                  * Tx TC1 starts at: descriptor queue 32
3322                                  * Tx TC2 starts at: descriptor queue 64
3323                                  * Tx TC3 starts at: descriptor queue 80
3324                                  * Tx TC4 starts at: descriptor queue 96
3325                                  * Tx TC5 starts at: descriptor queue 104
3326                                  * Tx TC6 starts at: descriptor queue 112
3327                                  * Tx TC7 starts at: descriptor queue 120
3328                                  *
3329                                  * Rx TC0-TC7 are offset by 16 queues each
3330                                  */
3331                                 for (i = 0; i < 3; i++) {
3332                                         adapter->tx_ring[i].reg_idx = i << 5;
3333                                         adapter->rx_ring[i].reg_idx = i << 4;
3334                                 }
3335                                 for ( ; i < 5; i++) {
3336                                         adapter->tx_ring[i].reg_idx =
3337                                                                  ((i + 2) << 4);
3338                                         adapter->rx_ring[i].reg_idx = i << 4;
3339                                 }
3340                                 for ( ; i < dcb_i; i++) {
3341                                         adapter->tx_ring[i].reg_idx =
3342                                                                  ((i + 8) << 3);
3343                                         adapter->rx_ring[i].reg_idx = i << 4;
3344                                 }
3345
3346                                 ret = true;
3347                         } else if (dcb_i == 4) {
3348                                 /*
3349                                  * Tx TC0 starts at: descriptor queue 0
3350                                  * Tx TC1 starts at: descriptor queue 64
3351                                  * Tx TC2 starts at: descriptor queue 96
3352                                  * Tx TC3 starts at: descriptor queue 112
3353                                  *
3354                                  * Rx TC0-TC3 are offset by 32 queues each
3355                                  */
3356                                 adapter->tx_ring[0].reg_idx = 0;
3357                                 adapter->tx_ring[1].reg_idx = 64;
3358                                 adapter->tx_ring[2].reg_idx = 96;
3359                                 adapter->tx_ring[3].reg_idx = 112;
3360                                 for (i = 0 ; i < dcb_i; i++)
3361                                         adapter->rx_ring[i].reg_idx = i << 5;
3362
3363                                 ret = true;
3364                         } else {
3365                                 ret = false;
3366                         }
3367                 } else {
3368                         ret = false;
3369                 }
3370         } else {
3371                 ret = false;
3372         }
3373
3374         return ret;
3375 }
3376 #endif
3377
3378 /**
3379  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3380  * @adapter: board private structure to initialize
3381  *
3382  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3383  *
3384  **/
3385 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3386 {
3387         int i;
3388         bool ret = false;
3389
3390         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3391             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3392              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3393                 for (i = 0; i < adapter->num_rx_queues; i++)
3394                         adapter->rx_ring[i].reg_idx = i;
3395                 for (i = 0; i < adapter->num_tx_queues; i++)
3396                         adapter->tx_ring[i].reg_idx = i;
3397                 ret = true;
3398         }
3399
3400         return ret;
3401 }
3402
3403 #ifdef IXGBE_FCOE
3404 /**
3405  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3406  * @adapter: board private structure to initialize
3407  *
3408  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3409  *
3410  */
3411 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3412 {
3413         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3414         bool ret = false;
3415         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3416
3417         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3418 #ifdef CONFIG_IXGBE_DCB
3419                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3420                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3421
3422                         ixgbe_cache_ring_dcb(adapter);
3423                         /* find out queues in TC for FCoE */
3424                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3425                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3426                         /*
3427                          * In 82599, the number of Tx queues for each traffic
3428                          * class for both 8-TC and 4-TC modes are:
3429                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3430                          * 8 TCs:  32  32  16  16   8   8   8   8
3431                          * 4 TCs:  64  64  32  32
3432                          * We have max 8 queues for FCoE, where 8 the is
3433                          * FCoE redirection table size. If TC for FCoE is
3434                          * less than or equal to TC3, we have enough queues
3435                          * to add max of 8 queues for FCoE, so we start FCoE
3436                          * tx descriptor from the next one, i.e., reg_idx + 1.
3437                          * If TC for FCoE is above TC3, implying 8 TC mode,
3438                          * and we need 8 for FCoE, we have to take all queues
3439                          * in that traffic class for FCoE.
3440                          */
3441                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3442                                 fcoe_tx_i--;
3443                 }
3444 #endif /* CONFIG_IXGBE_DCB */
3445                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3446                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3447                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3448                                 ixgbe_cache_ring_fdir(adapter);
3449                         else
3450                                 ixgbe_cache_ring_rss(adapter);
3451
3452                         fcoe_rx_i = f->mask;
3453                         fcoe_tx_i = f->mask;
3454                 }
3455                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3456                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3457                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3458                 }
3459                 ret = true;
3460         }
3461         return ret;
3462 }
3463
3464 #endif /* IXGBE_FCOE */
3465 /**
3466  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3467  * @adapter: board private structure to initialize
3468  *
3469  * Once we know the feature-set enabled for the device, we'll cache
3470  * the register offset the descriptor ring is assigned to.
3471  *
3472  * Note, the order the various feature calls is important.  It must start with
3473  * the "most" features enabled at the same time, then trickle down to the
3474  * least amount of features turned on at once.
3475  **/
3476 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3477 {
3478         /* start with default case */
3479         adapter->rx_ring[0].reg_idx = 0;
3480         adapter->tx_ring[0].reg_idx = 0;
3481
3482 #ifdef IXGBE_FCOE
3483         if (ixgbe_cache_ring_fcoe(adapter))
3484                 return;
3485
3486 #endif /* IXGBE_FCOE */
3487 #ifdef CONFIG_IXGBE_DCB
3488         if (ixgbe_cache_ring_dcb(adapter))
3489                 return;
3490
3491 #endif
3492         if (ixgbe_cache_ring_fdir(adapter))
3493                 return;
3494
3495         if (ixgbe_cache_ring_rss(adapter))
3496                 return;
3497 }
3498
3499 /**
3500  * ixgbe_alloc_queues - Allocate memory for all rings
3501  * @adapter: board private structure to initialize
3502  *
3503  * We allocate one ring per queue at run-time since we don't know the
3504  * number of queues at compile-time.  The polling_netdev array is
3505  * intended for Multiqueue, but should work fine with a single queue.
3506  **/
3507 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3508 {
3509         int i;
3510
3511         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3512                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3513         if (!adapter->tx_ring)
3514                 goto err_tx_ring_allocation;
3515
3516         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3517                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3518         if (!adapter->rx_ring)
3519                 goto err_rx_ring_allocation;
3520
3521         for (i = 0; i < adapter->num_tx_queues; i++) {
3522                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3523                 adapter->tx_ring[i].queue_index = i;
3524         }
3525
3526         for (i = 0; i < adapter->num_rx_queues; i++) {
3527                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3528                 adapter->rx_ring[i].queue_index = i;
3529         }
3530
3531         ixgbe_cache_ring_register(adapter);
3532
3533         return 0;
3534
3535 err_rx_ring_allocation:
3536         kfree(adapter->tx_ring);
3537 err_tx_ring_allocation:
3538         return -ENOMEM;
3539 }
3540
3541 /**
3542  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3543  * @adapter: board private structure to initialize
3544  *
3545  * Attempt to configure the interrupts using the best available
3546  * capabilities of the hardware and the kernel.
3547  **/
3548 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3549 {
3550         struct ixgbe_hw *hw = &adapter->hw;
3551         int err = 0;
3552         int vector, v_budget;
3553
3554         /*
3555          * It's easy to be greedy for MSI-X vectors, but it really
3556          * doesn't do us much good if we have a lot more vectors
3557          * than CPU's.  So let's be conservative and only ask for
3558          * (roughly) twice the number of vectors as there are CPU's.
3559          */
3560         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3561                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3562
3563         /*
3564          * At the same time, hardware can only support a maximum of
3565          * hw.mac->max_msix_vectors vectors.  With features
3566          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3567          * descriptor queues supported by our device.  Thus, we cap it off in
3568          * those rare cases where the cpu count also exceeds our vector limit.
3569          */
3570         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3571
3572         /* A failure in MSI-X entry allocation isn't fatal, but it does
3573          * mean we disable MSI-X capabilities of the adapter. */
3574         adapter->msix_entries = kcalloc(v_budget,
3575                                         sizeof(struct msix_entry), GFP_KERNEL);
3576         if (adapter->msix_entries) {
3577                 for (vector = 0; vector < v_budget; vector++)
3578                         adapter->msix_entries[vector].entry = vector;
3579
3580                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3581
3582                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3583                         goto out;
3584         }
3585
3586         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3587         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3588         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3589         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3590         adapter->atr_sample_rate = 0;
3591         ixgbe_set_num_queues(adapter);
3592
3593         err = pci_enable_msi(adapter->pdev);
3594         if (!err) {
3595                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3596         } else {
3597                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3598                         "falling back to legacy.  Error: %d\n", err);
3599                 /* reset err */
3600                 err = 0;
3601         }
3602
3603 out:
3604         return err;
3605 }
3606
3607 /**
3608  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3609  * @adapter: board private structure to initialize
3610  *
3611  * We allocate one q_vector per queue interrupt.  If allocation fails we
3612  * return -ENOMEM.
3613  **/
3614 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3615 {
3616         int q_idx, num_q_vectors;
3617         struct ixgbe_q_vector *q_vector;
3618         int napi_vectors;
3619         int (*poll)(struct napi_struct *, int);
3620
3621         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3622                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3623                 napi_vectors = adapter->num_rx_queues;
3624                 poll = &ixgbe_clean_rxtx_many;
3625         } else {
3626                 num_q_vectors = 1;
3627                 napi_vectors = 1;
3628                 poll = &ixgbe_poll;
3629         }
3630
3631         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3632                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3633                 if (!q_vector)
3634                         goto err_out;
3635                 q_vector->adapter = adapter;
3636                 if (q_vector->txr_count && !q_vector->rxr_count)
3637                         q_vector->eitr = adapter->tx_eitr_param;
3638                 else
3639                         q_vector->eitr = adapter->rx_eitr_param;
3640                 q_vector->v_idx = q_idx;
3641                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3642                 adapter->q_vector[q_idx] = q_vector;
3643         }
3644
3645         return 0;
3646
3647 err_out:
3648         while (q_idx) {
3649                 q_idx--;
3650                 q_vector = adapter->q_vector[q_idx];
3651                 netif_napi_del(&q_vector->napi);
3652                 kfree(q_vector);
3653                 adapter->q_vector[q_idx] = NULL;
3654         }
3655         return -ENOMEM;
3656 }
3657
3658 /**
3659  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3660  * @adapter: board private structure to initialize
3661  *
3662  * This function frees the memory allocated to the q_vectors.  In addition if
3663  * NAPI is enabled it will delete any references to the NAPI struct prior
3664  * to freeing the q_vector.
3665  **/
3666 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3667 {
3668         int q_idx, num_q_vectors;
3669
3670         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3671                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3672         else
3673                 num_q_vectors = 1;
3674
3675         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3676                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3677                 adapter->q_vector[q_idx] = NULL;
3678                 netif_napi_del(&q_vector->napi);
3679                 kfree(q_vector);
3680         }
3681 }
3682
3683 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3684 {
3685         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3686                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3687                 pci_disable_msix(adapter->pdev);
3688                 kfree(adapter->msix_entries);
3689                 adapter->msix_entries = NULL;
3690         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3691                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3692                 pci_disable_msi(adapter->pdev);
3693         }
3694         return;
3695 }
3696
3697 /**
3698  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3699  * @adapter: board private structure to initialize
3700  *
3701  * We determine which interrupt scheme to use based on...
3702  * - Kernel support (MSI, MSI-X)
3703  *   - which can be user-defined (via MODULE_PARAM)
3704  * - Hardware queue count (num_*_queues)
3705  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3706  **/
3707 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3708 {
3709         int err;
3710
3711         /* Number of supported queues */
3712         ixgbe_set_num_queues(adapter);
3713
3714         err = ixgbe_set_interrupt_capability(adapter);
3715         if (err) {
3716                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3717                 goto err_set_interrupt;
3718         }
3719
3720         err = ixgbe_alloc_q_vectors(adapter);
3721         if (err) {
3722                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3723                         "vectors\n");
3724                 goto err_alloc_q_vectors;
3725         }
3726
3727         err = ixgbe_alloc_queues(adapter);
3728         if (err) {
3729                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3730                 goto err_alloc_queues;
3731         }
3732
3733         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3734                 "Tx Queue count = %u\n",
3735                 (adapter->num_rx_queues > 1) ? "Enabled" :
3736                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3737
3738         set_bit(__IXGBE_DOWN, &adapter->state);
3739
3740         return 0;
3741
3742 err_alloc_queues:
3743         ixgbe_free_q_vectors(adapter);
3744 err_alloc_q_vectors:
3745         ixgbe_reset_interrupt_capability(adapter);
3746 err_set_interrupt:
3747         return err;
3748 }
3749
3750 /**
3751  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3752  * @adapter: board private structure to clear interrupt scheme on
3753  *
3754  * We go through and clear interrupt specific resources and reset the structure
3755  * to pre-load conditions
3756  **/
3757 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3758 {
3759         kfree(adapter->tx_ring);
3760         kfree(adapter->rx_ring);
3761         adapter->tx_ring = NULL;
3762         adapter->rx_ring = NULL;
3763
3764         ixgbe_free_q_vectors(adapter);
3765         ixgbe_reset_interrupt_capability(adapter);
3766 }
3767
3768 /**
3769  * ixgbe_sfp_timer - worker thread to find a missing module
3770  * @data: pointer to our adapter struct
3771  **/
3772 static void ixgbe_sfp_timer(unsigned long data)
3773 {
3774         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3775
3776         /*
3777          * Do the sfp_timer outside of interrupt context due to the
3778          * delays that sfp+ detection requires
3779          */
3780         schedule_work(&adapter->sfp_task);
3781 }
3782
3783 /**
3784  * ixgbe_sfp_task - worker thread to find a missing module
3785  * @work: pointer to work_struct containing our data
3786  **/
3787 static void ixgbe_sfp_task(struct work_struct *work)
3788 {
3789         struct ixgbe_adapter *adapter = container_of(work,
3790                                                      struct ixgbe_adapter,
3791                                                      sfp_task);
3792         struct ixgbe_hw *hw = &adapter->hw;
3793
3794         if ((hw->phy.type == ixgbe_phy_nl) &&
3795             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3796                 s32 ret = hw->phy.ops.identify_sfp(hw);
3797                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3798                         goto reschedule;
3799                 ret = hw->phy.ops.reset(hw);
3800                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3801                         dev_err(&adapter->pdev->dev, "failed to initialize "
3802                                 "because an unsupported SFP+ module type "
3803                                 "was detected.\n"
3804                                 "Reload the driver after installing a "
3805                                 "supported module.\n");
3806                         unregister_netdev(adapter->netdev);
3807                 } else {
3808                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3809                                 hw->phy.sfp_type);
3810                 }
3811                 /* don't need this routine any more */
3812                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3813         }
3814         return;
3815 reschedule:
3816         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3817                 mod_timer(&adapter->sfp_timer,
3818                           round_jiffies(jiffies + (2 * HZ)));
3819 }
3820
3821 /**
3822  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3823  * @adapter: board private structure to initialize
3824  *
3825  * ixgbe_sw_init initializes the Adapter private data structure.
3826  * Fields are initialized based on PCI device information and
3827  * OS network device settings (MTU size).
3828  **/
3829 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3830 {
3831         struct ixgbe_hw *hw = &adapter->hw;
3832         struct pci_dev *pdev = adapter->pdev;
3833         unsigned int rss;
3834 #ifdef CONFIG_IXGBE_DCB
3835         int j;
3836         struct tc_configuration *tc;
3837 #endif
3838
3839         /* PCI config space info */
3840
3841         hw->vendor_id = pdev->vendor;
3842         hw->device_id = pdev->device;
3843         hw->revision_id = pdev->revision;
3844         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3845         hw->subsystem_device_id = pdev->subsystem_device;
3846
3847         /* Set capability flags */
3848         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3849         adapter->ring_feature[RING_F_RSS].indices = rss;
3850         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3851         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3852         if (hw->mac.type == ixgbe_mac_82598EB) {
3853                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3854                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3855                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3856         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3857                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3858                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3859                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3860                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3861                 adapter->ring_feature[RING_F_FDIR].indices =
3862                                                          IXGBE_MAX_FDIR_INDICES;
3863                 adapter->atr_sample_rate = 20;
3864                 adapter->fdir_pballoc = 0;
3865 #ifdef IXGBE_FCOE
3866                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3867                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3868                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3869                 /* Default traffic class to use for FCoE */
3870                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3871 #endif /* IXGBE_FCOE */
3872         }
3873
3874 #ifdef CONFIG_IXGBE_DCB
3875         /* Configure DCB traffic classes */
3876         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3877                 tc = &adapter->dcb_cfg.tc_config[j];
3878                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3879                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3880                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3881                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3882                 tc->dcb_pfc = pfc_disabled;
3883         }
3884         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3885         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3886         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3887         adapter->dcb_cfg.pfc_mode_enable = false;
3888         adapter->dcb_cfg.round_robin_enable = false;
3889         adapter->dcb_set_bitmap = 0x00;
3890         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3891                            adapter->ring_feature[RING_F_DCB].indices);
3892
3893 #endif
3894
3895         /* default flow control settings */
3896         hw->fc.requested_mode = ixgbe_fc_full;
3897         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3898 #ifdef CONFIG_DCB
3899         adapter->last_lfc_mode = hw->fc.current_mode;
3900 #endif
3901         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3902         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3903         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3904         hw->fc.send_xon = true;
3905         hw->fc.disable_fc_autoneg = false;
3906
3907         /* enable itr by default in dynamic mode */
3908         adapter->rx_itr_setting = 1;
3909         adapter->rx_eitr_param = 20000;
3910         adapter->tx_itr_setting = 1;
3911         adapter->tx_eitr_param = 10000;
3912
3913         /* set defaults for eitr in MegaBytes */
3914         adapter->eitr_low = 10;
3915         adapter->eitr_high = 20;
3916
3917         /* set default ring sizes */
3918         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3919         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3920
3921         /* initialize eeprom parameters */
3922         if (ixgbe_init_eeprom_params_generic(hw)) {
3923                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3924                 return -EIO;
3925         }
3926
3927         /* enable rx csum by default */
3928         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3929
3930         set_bit(__IXGBE_DOWN, &adapter->state);
3931
3932         return 0;
3933 }
3934
3935 /**
3936  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3937  * @adapter: board private structure
3938  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3939  *
3940  * Return 0 on success, negative on failure
3941  **/
3942 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3943                              struct ixgbe_ring *tx_ring)
3944 {
3945         struct pci_dev *pdev = adapter->pdev;
3946         int size;
3947
3948         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3949         tx_ring->tx_buffer_info = vmalloc(size);
3950         if (!tx_ring->tx_buffer_info)
3951                 goto err;
3952         memset(tx_ring->tx_buffer_info, 0, size);
3953
3954         /* round up to nearest 4K */
3955         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3956         tx_ring->size = ALIGN(tx_ring->size, 4096);
3957
3958         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3959                                              &tx_ring->dma);
3960         if (!tx_ring->desc)
3961                 goto err;
3962
3963         tx_ring->next_to_use = 0;
3964         tx_ring->next_to_clean = 0;
3965         tx_ring->work_limit = tx_ring->count;
3966         return 0;
3967
3968 err:
3969         vfree(tx_ring->tx_buffer_info);
3970         tx_ring->tx_buffer_info = NULL;
3971         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3972                             "descriptor ring\n");
3973         return -ENOMEM;
3974 }
3975
3976 /**
3977  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3978  * @adapter: board private structure
3979  *
3980  * If this function returns with an error, then it's possible one or
3981  * more of the rings is populated (while the rest are not).  It is the
3982  * callers duty to clean those orphaned rings.
3983  *
3984  * Return 0 on success, negative on failure
3985  **/
3986 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3987 {
3988         int i, err = 0;
3989
3990         for (i = 0; i < adapter->num_tx_queues; i++) {
3991                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3992                 if (!err)
3993                         continue;
3994                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3995                 break;
3996         }
3997
3998         return err;
3999 }
4000
4001 /**
4002  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4003  * @adapter: board private structure
4004  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4005  *
4006  * Returns 0 on success, negative on failure
4007  **/
4008 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4009                              struct ixgbe_ring *rx_ring)
4010 {
4011         struct pci_dev *pdev = adapter->pdev;
4012         int size;
4013
4014         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4015         rx_ring->rx_buffer_info = vmalloc(size);
4016         if (!rx_ring->rx_buffer_info) {
4017                 DPRINTK(PROBE, ERR,
4018                         "vmalloc allocation failed for the rx desc ring\n");
4019                 goto alloc_failed;
4020         }
4021         memset(rx_ring->rx_buffer_info, 0, size);
4022
4023         /* Round up to nearest 4K */
4024         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4025         rx_ring->size = ALIGN(rx_ring->size, 4096);
4026
4027         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4028
4029         if (!rx_ring->desc) {
4030                 DPRINTK(PROBE, ERR,
4031                         "Memory allocation failed for the rx desc ring\n");
4032                 vfree(rx_ring->rx_buffer_info);
4033                 goto alloc_failed;
4034         }
4035
4036         rx_ring->next_to_clean = 0;
4037         rx_ring->next_to_use = 0;
4038
4039         return 0;
4040
4041 alloc_failed:
4042         return -ENOMEM;
4043 }
4044
4045 /**
4046  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4047  * @adapter: board private structure
4048  *
4049  * If this function returns with an error, then it's possible one or
4050  * more of the rings is populated (while the rest are not).  It is the
4051  * callers duty to clean those orphaned rings.
4052  *
4053  * Return 0 on success, negative on failure
4054  **/
4055
4056 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4057 {
4058         int i, err = 0;
4059
4060         for (i = 0; i < adapter->num_rx_queues; i++) {
4061                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4062                 if (!err)
4063                         continue;
4064                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4065                 break;
4066         }
4067
4068         return err;
4069 }
4070
4071 /**
4072  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4073  * @adapter: board private structure
4074  * @tx_ring: Tx descriptor ring for a specific queue
4075  *
4076  * Free all transmit software resources
4077  **/
4078 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4079                              struct ixgbe_ring *tx_ring)
4080 {
4081         struct pci_dev *pdev = adapter->pdev;
4082
4083         ixgbe_clean_tx_ring(adapter, tx_ring);
4084
4085         vfree(tx_ring->tx_buffer_info);
4086         tx_ring->tx_buffer_info = NULL;
4087
4088         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4089
4090         tx_ring->desc = NULL;
4091 }
4092
4093 /**
4094  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4095  * @adapter: board private structure
4096  *
4097  * Free all transmit software resources
4098  **/
4099 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4100 {
4101         int i;
4102
4103         for (i = 0; i < adapter->num_tx_queues; i++)
4104                 if (adapter->tx_ring[i].desc)
4105                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4106 }
4107
4108 /**
4109  * ixgbe_free_rx_resources - Free Rx Resources
4110  * @adapter: board private structure
4111  * @rx_ring: ring to clean the resources from
4112  *
4113  * Free all receive software resources
4114  **/
4115 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4116                              struct ixgbe_ring *rx_ring)
4117 {
4118         struct pci_dev *pdev = adapter->pdev;
4119
4120         ixgbe_clean_rx_ring(adapter, rx_ring);
4121
4122         vfree(rx_ring->rx_buffer_info);
4123         rx_ring->rx_buffer_info = NULL;
4124
4125         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4126
4127         rx_ring->desc = NULL;
4128 }
4129
4130 /**
4131  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4132  * @adapter: board private structure
4133  *
4134  * Free all receive software resources
4135  **/
4136 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4137 {
4138         int i;
4139
4140         for (i = 0; i < adapter->num_rx_queues; i++)
4141                 if (adapter->rx_ring[i].desc)
4142                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4143 }
4144
4145 /**
4146  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4147  * @netdev: network interface device structure
4148  * @new_mtu: new value for maximum frame size
4149  *
4150  * Returns 0 on success, negative on failure
4151  **/
4152 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4153 {
4154         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4155         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4156
4157         /* MTU < 68 is an error and causes problems on some kernels */
4158         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4159                 return -EINVAL;
4160
4161         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4162                 netdev->mtu, new_mtu);
4163         /* must set new MTU before calling down or up */
4164         netdev->mtu = new_mtu;
4165
4166         if (netif_running(netdev))
4167                 ixgbe_reinit_locked(adapter);
4168
4169         return 0;
4170 }
4171
4172 /**
4173  * ixgbe_open - Called when a network interface is made active
4174  * @netdev: network interface device structure
4175  *
4176  * Returns 0 on success, negative value on failure
4177  *
4178  * The open entry point is called when a network interface is made
4179  * active by the system (IFF_UP).  At this point all resources needed
4180  * for transmit and receive operations are allocated, the interrupt
4181  * handler is registered with the OS, the watchdog timer is started,
4182  * and the stack is notified that the interface is ready.
4183  **/
4184 static int ixgbe_open(struct net_device *netdev)
4185 {
4186         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4187         int err;
4188
4189         /* disallow open during test */
4190         if (test_bit(__IXGBE_TESTING, &adapter->state))
4191                 return -EBUSY;
4192
4193         netif_carrier_off(netdev);
4194
4195         /* allocate transmit descriptors */
4196         err = ixgbe_setup_all_tx_resources(adapter);
4197         if (err)
4198                 goto err_setup_tx;
4199
4200         /* allocate receive descriptors */
4201         err = ixgbe_setup_all_rx_resources(adapter);
4202         if (err)
4203                 goto err_setup_rx;
4204
4205         ixgbe_configure(adapter);
4206
4207         err = ixgbe_request_irq(adapter);
4208         if (err)
4209                 goto err_req_irq;
4210
4211         err = ixgbe_up_complete(adapter);
4212         if (err)
4213                 goto err_up;
4214
4215         netif_tx_start_all_queues(netdev);
4216
4217         return 0;
4218
4219 err_up:
4220         ixgbe_release_hw_control(adapter);
4221         ixgbe_free_irq(adapter);
4222 err_req_irq:
4223 err_setup_rx:
4224         ixgbe_free_all_rx_resources(adapter);
4225 err_setup_tx:
4226         ixgbe_free_all_tx_resources(adapter);
4227         ixgbe_reset(adapter);
4228
4229         return err;
4230 }
4231
4232 /**
4233  * ixgbe_close - Disables a network interface
4234  * @netdev: network interface device structure
4235  *
4236  * Returns 0, this is not allowed to fail
4237  *
4238  * The close entry point is called when an interface is de-activated
4239  * by the OS.  The hardware is still under the drivers control, but
4240  * needs to be disabled.  A global MAC reset is issued to stop the
4241  * hardware, and all transmit and receive resources are freed.
4242  **/
4243 static int ixgbe_close(struct net_device *netdev)
4244 {
4245         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4246
4247         ixgbe_down(adapter);
4248         ixgbe_free_irq(adapter);
4249
4250         ixgbe_free_all_tx_resources(adapter);
4251         ixgbe_free_all_rx_resources(adapter);
4252
4253         ixgbe_release_hw_control(adapter);
4254
4255         return 0;
4256 }
4257
4258 #ifdef CONFIG_PM
4259 static int ixgbe_resume(struct pci_dev *pdev)
4260 {
4261         struct net_device *netdev = pci_get_drvdata(pdev);
4262         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4263         u32 err;
4264
4265         pci_set_power_state(pdev, PCI_D0);
4266         pci_restore_state(pdev);
4267
4268         err = pci_enable_device_mem(pdev);
4269         if (err) {
4270                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4271                                 "suspend\n");
4272                 return err;
4273         }
4274         pci_set_master(pdev);
4275
4276         pci_wake_from_d3(pdev, false);
4277
4278         err = ixgbe_init_interrupt_scheme(adapter);
4279         if (err) {
4280                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4281                                 "device\n");
4282                 return err;
4283         }
4284
4285         ixgbe_reset(adapter);
4286
4287         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4288
4289         if (netif_running(netdev)) {
4290                 err = ixgbe_open(adapter->netdev);
4291                 if (err)
4292                         return err;
4293         }
4294
4295         netif_device_attach(netdev);
4296
4297         return 0;
4298 }
4299 #endif /* CONFIG_PM */
4300
4301 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4302 {
4303         struct net_device *netdev = pci_get_drvdata(pdev);
4304         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4305         struct ixgbe_hw *hw = &adapter->hw;
4306         u32 ctrl, fctrl;
4307         u32 wufc = adapter->wol;
4308 #ifdef CONFIG_PM
4309         int retval = 0;
4310 #endif
4311
4312         netif_device_detach(netdev);
4313
4314         if (netif_running(netdev)) {
4315                 ixgbe_down(adapter);
4316                 ixgbe_free_irq(adapter);
4317                 ixgbe_free_all_tx_resources(adapter);
4318                 ixgbe_free_all_rx_resources(adapter);
4319         }
4320         ixgbe_clear_interrupt_scheme(adapter);
4321
4322 #ifdef CONFIG_PM
4323         retval = pci_save_state(pdev);
4324         if (retval)
4325                 return retval;
4326
4327 #endif
4328         if (wufc) {
4329                 ixgbe_set_rx_mode(netdev);
4330
4331                 /* turn on all-multi mode if wake on multicast is enabled */
4332                 if (wufc & IXGBE_WUFC_MC) {
4333                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4334                         fctrl |= IXGBE_FCTRL_MPE;
4335                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4336                 }
4337
4338                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4339                 ctrl |= IXGBE_CTRL_GIO_DIS;
4340                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4341
4342                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4343         } else {
4344                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4345                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4346         }
4347
4348         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4349                 pci_wake_from_d3(pdev, true);
4350         else
4351                 pci_wake_from_d3(pdev, false);
4352
4353         *enable_wake = !!wufc;
4354
4355         ixgbe_release_hw_control(adapter);
4356
4357         pci_disable_device(pdev);
4358
4359         return 0;
4360 }
4361
4362 #ifdef CONFIG_PM
4363 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4364 {
4365         int retval;
4366         bool wake;
4367
4368         retval = __ixgbe_shutdown(pdev, &wake);
4369         if (retval)
4370                 return retval;
4371
4372         if (wake) {
4373                 pci_prepare_to_sleep(pdev);
4374         } else {
4375                 pci_wake_from_d3(pdev, false);
4376                 pci_set_power_state(pdev, PCI_D3hot);
4377         }
4378
4379         return 0;
4380 }
4381 #endif /* CONFIG_PM */
4382
4383 static void ixgbe_shutdown(struct pci_dev *pdev)
4384 {
4385         bool wake;
4386
4387         __ixgbe_shutdown(pdev, &wake);
4388
4389         if (system_state == SYSTEM_POWER_OFF) {
4390                 pci_wake_from_d3(pdev, wake);
4391                 pci_set_power_state(pdev, PCI_D3hot);
4392         }
4393 }
4394
4395 /**
4396  * ixgbe_update_stats - Update the board statistics counters.
4397  * @adapter: board private structure
4398  **/
4399 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4400 {
4401         struct net_device *netdev = adapter->netdev;
4402         struct ixgbe_hw *hw = &adapter->hw;
4403         u64 total_mpc = 0;
4404         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4405
4406         if (hw->mac.type == ixgbe_mac_82599EB) {
4407                 u64 rsc_count = 0;
4408                 for (i = 0; i < 16; i++)
4409                         adapter->hw_rx_no_dma_resources +=
4410                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4411                 for (i = 0; i < adapter->num_rx_queues; i++)
4412                         rsc_count += adapter->rx_ring[i].rsc_count;
4413                 adapter->rsc_count = rsc_count;
4414         }
4415
4416         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4417         for (i = 0; i < 8; i++) {
4418                 /* for packet buffers not used, the register should read 0 */
4419                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4420                 missed_rx += mpc;
4421                 adapter->stats.mpc[i] += mpc;
4422                 total_mpc += adapter->stats.mpc[i];
4423                 if (hw->mac.type == ixgbe_mac_82598EB)
4424                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4425                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4426                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4427                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4428                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4429                 if (hw->mac.type == ixgbe_mac_82599EB) {
4430                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4431                                                             IXGBE_PXONRXCNT(i));
4432                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4433                                                            IXGBE_PXOFFRXCNT(i));
4434                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4435                 } else {
4436                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4437                                                               IXGBE_PXONRXC(i));
4438                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4439                                                              IXGBE_PXOFFRXC(i));
4440                 }
4441                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4442                                                             IXGBE_PXONTXC(i));
4443                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4444                                                              IXGBE_PXOFFTXC(i));
4445         }
4446         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4447         /* work around hardware counting issue */
4448         adapter->stats.gprc -= missed_rx;
4449
4450         /* 82598 hardware only has a 32 bit counter in the high register */
4451         if (hw->mac.type == ixgbe_mac_82599EB) {
4452                 u64 tmp;
4453                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4454                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4455                 adapter->stats.gorc += (tmp << 32);
4456                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4457                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4458                 adapter->stats.gotc += (tmp << 32);
4459                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4460                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4461                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4462                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4463                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4464                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4465 #ifdef IXGBE_FCOE
4466                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4467                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4468                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4469                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4470                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4471                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4472 #endif /* IXGBE_FCOE */
4473         } else {
4474                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4475                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4476                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4477                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4478                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4479         }
4480         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4481         adapter->stats.bprc += bprc;
4482         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4483         if (hw->mac.type == ixgbe_mac_82598EB)
4484                 adapter->stats.mprc -= bprc;
4485         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4486         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4487         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4488         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4489         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4490         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4491         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4492         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4493         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4494         adapter->stats.lxontxc += lxon;
4495         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4496         adapter->stats.lxofftxc += lxoff;
4497         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4498         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4499         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4500         /*
4501          * 82598 errata - tx of flow control packets is included in tx counters
4502          */
4503         xon_off_tot = lxon + lxoff;
4504         adapter->stats.gptc -= xon_off_tot;
4505         adapter->stats.mptc -= xon_off_tot;
4506         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4507         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4508         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4509         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4510         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4511         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4512         adapter->stats.ptc64 -= xon_off_tot;
4513         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4514         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4515         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4516         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4517         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4518         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4519
4520         /* Fill out the OS statistics structure */
4521         netdev->stats.multicast = adapter->stats.mprc;
4522
4523         /* Rx Errors */
4524         netdev->stats.rx_errors = adapter->stats.crcerrs +
4525                                        adapter->stats.rlec;
4526         netdev->stats.rx_dropped = 0;
4527         netdev->stats.rx_length_errors = adapter->stats.rlec;
4528         netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4529         netdev->stats.rx_missed_errors = total_mpc;
4530 }
4531
4532 /**
4533  * ixgbe_watchdog - Timer Call-back
4534  * @data: pointer to adapter cast into an unsigned long
4535  **/
4536 static void ixgbe_watchdog(unsigned long data)
4537 {
4538         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4539         struct ixgbe_hw *hw = &adapter->hw;
4540         u64 eics = 0;
4541         int i;
4542
4543         /*
4544          *  Do the watchdog outside of interrupt context due to the lovely
4545          * delays that some of the newer hardware requires
4546          */
4547
4548         if (test_bit(__IXGBE_DOWN, &adapter->state))
4549                 goto watchdog_short_circuit;
4550
4551         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4552                 /*
4553                  * for legacy and MSI interrupts don't set any bits
4554                  * that are enabled for EIAM, because this operation
4555                  * would set *both* EIMS and EICS for any bit in EIAM
4556                  */
4557                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4558                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4559                 goto watchdog_reschedule;
4560         }
4561
4562         /* get one bit for every active tx/rx interrupt vector */
4563         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4564                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4565                 if (qv->rxr_count || qv->txr_count)
4566                         eics |= ((u64)1 << i);
4567         }
4568
4569         /* Cause software interrupt to ensure rx rings are cleaned */
4570         ixgbe_irq_rearm_queues(adapter, eics);
4571
4572 watchdog_reschedule:
4573         /* Reset the timer */
4574         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4575
4576 watchdog_short_circuit:
4577         schedule_work(&adapter->watchdog_task);
4578 }
4579
4580 /**
4581  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4582  * @work: pointer to work_struct containing our data
4583  **/
4584 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4585 {
4586         struct ixgbe_adapter *adapter = container_of(work,
4587                                                      struct ixgbe_adapter,
4588                                                      multispeed_fiber_task);
4589         struct ixgbe_hw *hw = &adapter->hw;
4590         u32 autoneg;
4591         bool negotiation;
4592
4593         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4594         autoneg = hw->phy.autoneg_advertised;
4595         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4596                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4597         if (hw->mac.ops.setup_link)
4598                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4599         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4600         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4601 }
4602
4603 /**
4604  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4605  * @work: pointer to work_struct containing our data
4606  **/
4607 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4608 {
4609         struct ixgbe_adapter *adapter = container_of(work,
4610                                                      struct ixgbe_adapter,
4611                                                      sfp_config_module_task);
4612         struct ixgbe_hw *hw = &adapter->hw;
4613         u32 err;
4614
4615         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4616
4617         /* Time for electrical oscillations to settle down */
4618         msleep(100);
4619         err = hw->phy.ops.identify_sfp(hw);
4620
4621         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4622                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4623                         "an unsupported SFP+ module type was detected.\n"
4624                         "Reload the driver after installing a supported "
4625                         "module.\n");
4626                 unregister_netdev(adapter->netdev);
4627                 return;
4628         }
4629         hw->mac.ops.setup_sfp(hw);
4630
4631         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4632                 /* This will also work for DA Twinax connections */
4633                 schedule_work(&adapter->multispeed_fiber_task);
4634         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4635 }
4636
4637 /**
4638  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4639  * @work: pointer to work_struct containing our data
4640  **/
4641 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4642 {
4643         struct ixgbe_adapter *adapter = container_of(work,
4644                                                      struct ixgbe_adapter,
4645                                                      fdir_reinit_task);
4646         struct ixgbe_hw *hw = &adapter->hw;
4647         int i;
4648
4649         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4650                 for (i = 0; i < adapter->num_tx_queues; i++)
4651                         set_bit(__IXGBE_FDIR_INIT_DONE,
4652                                 &(adapter->tx_ring[i].reinit_state));
4653         } else {
4654                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4655                         "ignored adding FDIR ATR filters \n");
4656         }
4657         /* Done FDIR Re-initialization, enable transmits */
4658         netif_tx_start_all_queues(adapter->netdev);
4659 }
4660
4661 /**
4662  * ixgbe_watchdog_task - worker thread to bring link up
4663  * @work: pointer to work_struct containing our data
4664  **/
4665 static void ixgbe_watchdog_task(struct work_struct *work)
4666 {
4667         struct ixgbe_adapter *adapter = container_of(work,
4668                                                      struct ixgbe_adapter,
4669                                                      watchdog_task);
4670         struct net_device *netdev = adapter->netdev;
4671         struct ixgbe_hw *hw = &adapter->hw;
4672         u32 link_speed = adapter->link_speed;
4673         bool link_up = adapter->link_up;
4674         int i;
4675         struct ixgbe_ring *tx_ring;
4676         int some_tx_pending = 0;
4677
4678         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4679
4680         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4681                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4682                 if (link_up) {
4683 #ifdef CONFIG_DCB
4684                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4685                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4686                                         hw->mac.ops.fc_enable(hw, i);
4687                         } else {
4688                                 hw->mac.ops.fc_enable(hw, 0);
4689                         }
4690 #else
4691                         hw->mac.ops.fc_enable(hw, 0);
4692 #endif
4693                 }
4694
4695                 if (link_up ||
4696                     time_after(jiffies, (adapter->link_check_timeout +
4697                                          IXGBE_TRY_LINK_TIMEOUT))) {
4698                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4699                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4700                 }
4701                 adapter->link_up = link_up;
4702                 adapter->link_speed = link_speed;
4703         }
4704
4705         if (link_up) {
4706                 if (!netif_carrier_ok(netdev)) {
4707                         bool flow_rx, flow_tx;
4708
4709                         if (hw->mac.type == ixgbe_mac_82599EB) {
4710                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4711                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4712                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4713                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4714                         } else {
4715                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4716                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4717                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4718                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4719                         }
4720
4721                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4722                                "Flow Control: %s\n",
4723                                netdev->name,
4724                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4725                                 "10 Gbps" :
4726                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4727                                  "1 Gbps" : "unknown speed")),
4728                                ((flow_rx && flow_tx) ? "RX/TX" :
4729                                 (flow_rx ? "RX" :
4730                                 (flow_tx ? "TX" : "None"))));
4731
4732                         netif_carrier_on(netdev);
4733                 } else {
4734                         /* Force detection of hung controller */
4735                         adapter->detect_tx_hung = true;
4736                 }
4737         } else {
4738                 adapter->link_up = false;
4739                 adapter->link_speed = 0;
4740                 if (netif_carrier_ok(netdev)) {
4741                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4742                                netdev->name);
4743                         netif_carrier_off(netdev);
4744                 }
4745         }
4746
4747         if (!netif_carrier_ok(netdev)) {
4748                 for (i = 0; i < adapter->num_tx_queues; i++) {
4749                         tx_ring = &adapter->tx_ring[i];
4750                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4751                                 some_tx_pending = 1;
4752                                 break;
4753                         }
4754                 }
4755
4756                 if (some_tx_pending) {
4757                         /* We've lost link, so the controller stops DMA,
4758                          * but we've got queued Tx work that's never going
4759                          * to get done, so reset controller to flush Tx.
4760                          * (Do the reset outside of interrupt context).
4761                          */
4762                          schedule_work(&adapter->reset_task);
4763                 }
4764         }
4765
4766         ixgbe_update_stats(adapter);
4767         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4768 }
4769
4770 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4771                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4772                      u32 tx_flags, u8 *hdr_len)
4773 {
4774         struct ixgbe_adv_tx_context_desc *context_desc;
4775         unsigned int i;
4776         int err;
4777         struct ixgbe_tx_buffer *tx_buffer_info;
4778         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4779         u32 mss_l4len_idx, l4len;
4780
4781         if (skb_is_gso(skb)) {
4782                 if (skb_header_cloned(skb)) {
4783                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4784                         if (err)
4785                                 return err;
4786                 }
4787                 l4len = tcp_hdrlen(skb);
4788                 *hdr_len += l4len;
4789
4790                 if (skb->protocol == htons(ETH_P_IP)) {
4791                         struct iphdr *iph = ip_hdr(skb);
4792                         iph->tot_len = 0;
4793                         iph->check = 0;
4794                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4795                                                                  iph->daddr, 0,
4796                                                                  IPPROTO_TCP,
4797                                                                  0);
4798                         adapter->hw_tso_ctxt++;
4799                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4800                         ipv6_hdr(skb)->payload_len = 0;
4801                         tcp_hdr(skb)->check =
4802                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4803                                              &ipv6_hdr(skb)->daddr,
4804                                              0, IPPROTO_TCP, 0);
4805                         adapter->hw_tso6_ctxt++;
4806                 }
4807
4808                 i = tx_ring->next_to_use;
4809
4810                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4811                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4812
4813                 /* VLAN MACLEN IPLEN */
4814                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4815                         vlan_macip_lens |=
4816                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4817                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4818                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4819                 *hdr_len += skb_network_offset(skb);
4820                 vlan_macip_lens |=
4821                     (skb_transport_header(skb) - skb_network_header(skb));
4822                 *hdr_len +=
4823                     (skb_transport_header(skb) - skb_network_header(skb));
4824                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4825                 context_desc->seqnum_seed = 0;
4826
4827                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4828                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4829                                    IXGBE_ADVTXD_DTYP_CTXT);
4830
4831                 if (skb->protocol == htons(ETH_P_IP))
4832                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4833                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4834                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4835
4836                 /* MSS L4LEN IDX */
4837                 mss_l4len_idx =
4838                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4839                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4840                 /* use index 1 for TSO */
4841                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4842                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4843
4844                 tx_buffer_info->time_stamp = jiffies;
4845                 tx_buffer_info->next_to_watch = i;
4846
4847                 i++;
4848                 if (i == tx_ring->count)
4849                         i = 0;
4850                 tx_ring->next_to_use = i;
4851
4852                 return true;
4853         }
4854         return false;
4855 }
4856
4857 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4858                           struct ixgbe_ring *tx_ring,
4859                           struct sk_buff *skb, u32 tx_flags)
4860 {
4861         struct ixgbe_adv_tx_context_desc *context_desc;
4862         unsigned int i;
4863         struct ixgbe_tx_buffer *tx_buffer_info;
4864         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4865
4866         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4867             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4868                 i = tx_ring->next_to_use;
4869                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4870                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4871
4872                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4873                         vlan_macip_lens |=
4874                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4875                 vlan_macip_lens |= (skb_network_offset(skb) <<
4876                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4877                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4878                         vlan_macip_lens |= (skb_transport_header(skb) -
4879                                             skb_network_header(skb));
4880
4881                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4882                 context_desc->seqnum_seed = 0;
4883
4884                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4885                                     IXGBE_ADVTXD_DTYP_CTXT);
4886
4887                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4888                         switch (skb->protocol) {
4889                         case cpu_to_be16(ETH_P_IP):
4890                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4891                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4892                                         type_tucmd_mlhl |=
4893                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4894                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4895                                         type_tucmd_mlhl |=
4896                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4897                                 break;
4898                         case cpu_to_be16(ETH_P_IPV6):
4899                                 /* XXX what about other V6 headers?? */
4900                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4901                                         type_tucmd_mlhl |=
4902                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4903                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4904                                         type_tucmd_mlhl |=
4905                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4906                                 break;
4907                         default:
4908                                 if (unlikely(net_ratelimit())) {
4909                                         DPRINTK(PROBE, WARNING,
4910                                          "partial checksum but proto=%x!\n",
4911                                          skb->protocol);
4912                                 }
4913                                 break;
4914                         }
4915                 }
4916
4917                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4918                 /* use index zero for tx checksum offload */
4919                 context_desc->mss_l4len_idx = 0;
4920
4921                 tx_buffer_info->time_stamp = jiffies;
4922                 tx_buffer_info->next_to_watch = i;
4923
4924                 adapter->hw_csum_tx_good++;
4925                 i++;
4926                 if (i == tx_ring->count)
4927                         i = 0;
4928                 tx_ring->next_to_use = i;
4929
4930                 return true;
4931         }
4932
4933         return false;
4934 }
4935
4936 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4937                         struct ixgbe_ring *tx_ring,
4938                         struct sk_buff *skb, u32 tx_flags,
4939                         unsigned int first)
4940 {
4941         struct ixgbe_tx_buffer *tx_buffer_info;
4942         unsigned int len;
4943         unsigned int total = skb->len;
4944         unsigned int offset = 0, size, count = 0, i;
4945         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4946         unsigned int f;
4947         dma_addr_t *map;
4948
4949         i = tx_ring->next_to_use;
4950
4951         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4952                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4953                 return 0;
4954         }
4955
4956         map = skb_shinfo(skb)->dma_maps;
4957
4958         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4959                 /* excluding fcoe_crc_eof for FCoE */
4960                 total -= sizeof(struct fcoe_crc_eof);
4961
4962         len = min(skb_headlen(skb), total);
4963         while (len) {
4964                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4965                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4966
4967                 tx_buffer_info->length = size;
4968                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4969                 tx_buffer_info->time_stamp = jiffies;
4970                 tx_buffer_info->next_to_watch = i;
4971
4972                 len -= size;
4973                 total -= size;
4974                 offset += size;
4975                 count++;
4976
4977                 if (len) {
4978                         i++;
4979                         if (i == tx_ring->count)
4980                                 i = 0;
4981                 }
4982         }
4983
4984         for (f = 0; f < nr_frags; f++) {
4985                 struct skb_frag_struct *frag;
4986
4987                 frag = &skb_shinfo(skb)->frags[f];
4988                 len = min((unsigned int)frag->size, total);
4989                 offset = 0;
4990
4991                 while (len) {
4992                         i++;
4993                         if (i == tx_ring->count)
4994                                 i = 0;
4995
4996                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4997                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4998
4999                         tx_buffer_info->length = size;
5000                         tx_buffer_info->dma = map[f] + offset;
5001                         tx_buffer_info->time_stamp = jiffies;
5002                         tx_buffer_info->next_to_watch = i;
5003
5004                         len -= size;
5005                         total -= size;
5006                         offset += size;
5007                         count++;
5008                 }
5009                 if (total == 0)
5010                         break;
5011         }
5012
5013         tx_ring->tx_buffer_info[i].skb = skb;
5014         tx_ring->tx_buffer_info[first].next_to_watch = i;
5015
5016         return count;
5017 }
5018
5019 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5020                            struct ixgbe_ring *tx_ring,
5021                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5022 {
5023         union ixgbe_adv_tx_desc *tx_desc = NULL;
5024         struct ixgbe_tx_buffer *tx_buffer_info;
5025         u32 olinfo_status = 0, cmd_type_len = 0;
5026         unsigned int i;
5027         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5028
5029         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5030
5031         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5032
5033         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5034                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5035
5036         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5037                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5038
5039                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5040                                  IXGBE_ADVTXD_POPTS_SHIFT;
5041
5042                 /* use index 1 context for tso */
5043                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5044                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5045                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5046                                          IXGBE_ADVTXD_POPTS_SHIFT;
5047
5048         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5049                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5050                                  IXGBE_ADVTXD_POPTS_SHIFT;
5051
5052         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5053                 olinfo_status |= IXGBE_ADVTXD_CC;
5054                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5055                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5056                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5057         }
5058
5059         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5060
5061         i = tx_ring->next_to_use;
5062         while (count--) {
5063                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5064                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5065                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5066                 tx_desc->read.cmd_type_len =
5067                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5068                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5069                 i++;
5070                 if (i == tx_ring->count)
5071                         i = 0;
5072         }
5073
5074         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5075
5076         /*
5077          * Force memory writes to complete before letting h/w
5078          * know there are new descriptors to fetch.  (Only
5079          * applicable for weak-ordered memory model archs,
5080          * such as IA-64).
5081          */
5082         wmb();
5083
5084         tx_ring->next_to_use = i;
5085         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5086 }
5087
5088 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5089                       int queue, u32 tx_flags)
5090 {
5091         /* Right now, we support IPv4 only */
5092         struct ixgbe_atr_input atr_input;
5093         struct tcphdr *th;
5094         struct iphdr *iph = ip_hdr(skb);
5095         struct ethhdr *eth = (struct ethhdr *)skb->data;
5096         u16 vlan_id, src_port, dst_port, flex_bytes;
5097         u32 src_ipv4_addr, dst_ipv4_addr;
5098         u8 l4type = 0;
5099
5100         /* check if we're UDP or TCP */
5101         if (iph->protocol == IPPROTO_TCP) {
5102                 th = tcp_hdr(skb);
5103                 src_port = th->source;
5104                 dst_port = th->dest;
5105                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5106                 /* l4type IPv4 type is 0, no need to assign */
5107         } else {
5108                 /* Unsupported L4 header, just bail here */
5109                 return;
5110         }
5111
5112         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5113
5114         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5115                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5116         src_ipv4_addr = iph->saddr;
5117         dst_ipv4_addr = iph->daddr;
5118         flex_bytes = eth->h_proto;
5119
5120         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5121         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5122         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5123         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5124         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5125         /* src and dst are inverted, think how the receiver sees them */
5126         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5127         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5128
5129         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5130         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5131 }
5132
5133 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5134                                  struct ixgbe_ring *tx_ring, int size)
5135 {
5136         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5137
5138         netif_stop_subqueue(netdev, tx_ring->queue_index);
5139         /* Herbert's original patch had:
5140          *  smp_mb__after_netif_stop_queue();
5141          * but since that doesn't exist yet, just open code it. */
5142         smp_mb();
5143
5144         /* We need to check again in a case another CPU has just
5145          * made room available. */
5146         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5147                 return -EBUSY;
5148
5149         /* A reprieve! - use start_queue because it doesn't call schedule */
5150         netif_start_subqueue(netdev, tx_ring->queue_index);
5151         ++adapter->restart_queue;
5152         return 0;
5153 }
5154
5155 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5156                               struct ixgbe_ring *tx_ring, int size)
5157 {
5158         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5159                 return 0;
5160         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5161 }
5162
5163 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5164 {
5165         struct ixgbe_adapter *adapter = netdev_priv(dev);
5166
5167         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5168                 return smp_processor_id();
5169
5170         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5171                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5172
5173         return skb_tx_hash(dev, skb);
5174 }
5175
5176 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5177                                     struct net_device *netdev)
5178 {
5179         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5180         struct ixgbe_ring *tx_ring;
5181         unsigned int first;
5182         unsigned int tx_flags = 0;
5183         u8 hdr_len = 0;
5184         int r_idx = 0, tso;
5185         int count = 0;
5186         unsigned int f;
5187
5188         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5189                 tx_flags |= vlan_tx_tag_get(skb);
5190                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5191                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5192                         tx_flags |= (skb->queue_mapping << 13);
5193                 }
5194                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5195                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5196         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5197                 if (skb->priority != TC_PRIO_CONTROL) {
5198                         tx_flags |= (skb->queue_mapping << 13);
5199                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5200                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5201                 } else {
5202                         skb->queue_mapping =
5203                                 adapter->ring_feature[RING_F_DCB].indices-1;
5204                 }
5205         }
5206
5207         r_idx = skb->queue_mapping;
5208         tx_ring = &adapter->tx_ring[r_idx];
5209
5210         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5211             (skb->protocol == htons(ETH_P_FCOE))) {
5212                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5213 #ifdef IXGBE_FCOE
5214                 r_idx = smp_processor_id();
5215                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5216                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5217                 tx_ring = &adapter->tx_ring[r_idx];
5218 #endif
5219         }
5220         /* four things can cause us to need a context descriptor */
5221         if (skb_is_gso(skb) ||
5222             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5223             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5224             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5225                 count++;
5226
5227         count += TXD_USE_COUNT(skb_headlen(skb));
5228         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5229                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5230
5231         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5232                 adapter->tx_busy++;
5233                 return NETDEV_TX_BUSY;
5234         }
5235
5236         first = tx_ring->next_to_use;
5237         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5238 #ifdef IXGBE_FCOE
5239                 /* setup tx offload for FCoE */
5240                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5241                 if (tso < 0) {
5242                         dev_kfree_skb_any(skb);
5243                         return NETDEV_TX_OK;
5244                 }
5245                 if (tso)
5246                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5247 #endif /* IXGBE_FCOE */
5248         } else {
5249                 if (skb->protocol == htons(ETH_P_IP))
5250                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5251                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5252                 if (tso < 0) {
5253                         dev_kfree_skb_any(skb);
5254                         return NETDEV_TX_OK;
5255                 }
5256
5257                 if (tso)
5258                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5259                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5260                          (skb->ip_summed == CHECKSUM_PARTIAL))
5261                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5262         }
5263
5264         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5265         if (count) {
5266                 /* add the ATR filter if ATR is on */
5267                 if (tx_ring->atr_sample_rate) {
5268                         ++tx_ring->atr_count;
5269                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5270                              test_bit(__IXGBE_FDIR_INIT_DONE,
5271                                       &tx_ring->reinit_state)) {
5272                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5273                                           tx_flags);
5274                                 tx_ring->atr_count = 0;
5275                         }
5276                 }
5277                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5278                                hdr_len);
5279                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5280
5281         } else {
5282                 dev_kfree_skb_any(skb);
5283                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5284                 tx_ring->next_to_use = first;
5285         }
5286
5287         return NETDEV_TX_OK;
5288 }
5289
5290 /**
5291  * ixgbe_get_stats - Get System Network Statistics
5292  * @netdev: network interface device structure
5293  *
5294  * Returns the address of the device statistics structure.
5295  * The statistics are actually updated from the timer callback.
5296  **/
5297 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5298 {
5299         /* only return the current stats */
5300         return &netdev->stats;
5301 }
5302
5303 /**
5304  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5305  * @netdev: network interface device structure
5306  * @p: pointer to an address structure
5307  *
5308  * Returns 0 on success, negative on failure
5309  **/
5310 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5311 {
5312         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5313         struct ixgbe_hw *hw = &adapter->hw;
5314         struct sockaddr *addr = p;
5315
5316         if (!is_valid_ether_addr(addr->sa_data))
5317                 return -EADDRNOTAVAIL;
5318
5319         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5320         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5321
5322         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5323
5324         return 0;
5325 }
5326
5327 static int
5328 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5329 {
5330         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5331         struct ixgbe_hw *hw = &adapter->hw;
5332         u16 value;
5333         int rc;
5334
5335         if (prtad != hw->phy.mdio.prtad)
5336                 return -EINVAL;
5337         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5338         if (!rc)
5339                 rc = value;
5340         return rc;
5341 }
5342
5343 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5344                             u16 addr, u16 value)
5345 {
5346         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5347         struct ixgbe_hw *hw = &adapter->hw;
5348
5349         if (prtad != hw->phy.mdio.prtad)
5350                 return -EINVAL;
5351         return hw->phy.ops.write_reg(hw, addr, devad, value);
5352 }
5353
5354 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5355 {
5356         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5357
5358         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5359 }
5360
5361 /**
5362  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5363  * netdev->dev_addrs
5364  * @netdev: network interface device structure
5365  *
5366  * Returns non-zero on failure
5367  **/
5368 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5369 {
5370         int err = 0;
5371         struct ixgbe_adapter *adapter = netdev_priv(dev);
5372         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5373
5374         if (is_valid_ether_addr(mac->san_addr)) {
5375                 rtnl_lock();
5376                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5377                 rtnl_unlock();
5378         }
5379         return err;
5380 }
5381
5382 /**
5383  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5384  * netdev->dev_addrs
5385  * @netdev: network interface device structure
5386  *
5387  * Returns non-zero on failure
5388  **/
5389 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5390 {
5391         int err = 0;
5392         struct ixgbe_adapter *adapter = netdev_priv(dev);
5393         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5394
5395         if (is_valid_ether_addr(mac->san_addr)) {
5396                 rtnl_lock();
5397                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5398                 rtnl_unlock();
5399         }
5400         return err;
5401 }
5402
5403 #ifdef CONFIG_NET_POLL_CONTROLLER
5404 /*
5405  * Polling 'interrupt' - used by things like netconsole to send skbs
5406  * without having to re-enable interrupts. It's not called while
5407  * the interrupt routine is executing.
5408  */
5409 static void ixgbe_netpoll(struct net_device *netdev)
5410 {
5411         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5412         int i;
5413
5414         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5415         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5416                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5417                 for (i = 0; i < num_q_vectors; i++) {
5418                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5419                         ixgbe_msix_clean_many(0, q_vector);
5420                 }
5421         } else {
5422                 ixgbe_intr(adapter->pdev->irq, netdev);
5423         }
5424         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5425 }
5426 #endif
5427
5428 static const struct net_device_ops ixgbe_netdev_ops = {
5429         .ndo_open               = ixgbe_open,
5430         .ndo_stop               = ixgbe_close,
5431         .ndo_start_xmit         = ixgbe_xmit_frame,
5432         .ndo_select_queue       = ixgbe_select_queue,
5433         .ndo_get_stats          = ixgbe_get_stats,
5434         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5435         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5436         .ndo_validate_addr      = eth_validate_addr,
5437         .ndo_set_mac_address    = ixgbe_set_mac,
5438         .ndo_change_mtu         = ixgbe_change_mtu,
5439         .ndo_tx_timeout         = ixgbe_tx_timeout,
5440         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5441         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5442         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5443         .ndo_do_ioctl           = ixgbe_ioctl,
5444 #ifdef CONFIG_NET_POLL_CONTROLLER
5445         .ndo_poll_controller    = ixgbe_netpoll,
5446 #endif
5447 #ifdef IXGBE_FCOE
5448         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5449         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5450         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5451         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5452 #endif /* IXGBE_FCOE */
5453 };
5454
5455 /**
5456  * ixgbe_probe - Device Initialization Routine
5457  * @pdev: PCI device information struct
5458  * @ent: entry in ixgbe_pci_tbl
5459  *
5460  * Returns 0 on success, negative on failure
5461  *
5462  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5463  * The OS initialization, configuring of the adapter private structure,
5464  * and a hardware reset occur.
5465  **/
5466 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5467                                  const struct pci_device_id *ent)
5468 {
5469         struct net_device *netdev;
5470         struct ixgbe_adapter *adapter = NULL;
5471         struct ixgbe_hw *hw;
5472         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5473         static int cards_found;
5474         int i, err, pci_using_dac;
5475 #ifdef IXGBE_FCOE
5476         u16 device_caps;
5477 #endif
5478         u32 part_num, eec;
5479
5480         err = pci_enable_device_mem(pdev);
5481         if (err)
5482                 return err;
5483
5484         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5485             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5486                 pci_using_dac = 1;
5487         } else {
5488                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5489                 if (err) {
5490                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5491                         if (err) {
5492                                 dev_err(&pdev->dev, "No usable DMA "
5493                                         "configuration, aborting\n");
5494                                 goto err_dma;
5495                         }
5496                 }
5497                 pci_using_dac = 0;
5498         }
5499
5500         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5501                                            IORESOURCE_MEM), ixgbe_driver_name);
5502         if (err) {
5503                 dev_err(&pdev->dev,
5504                         "pci_request_selected_regions failed 0x%x\n", err);
5505                 goto err_pci_reg;
5506         }
5507
5508         pci_enable_pcie_error_reporting(pdev);
5509
5510         pci_set_master(pdev);
5511         pci_save_state(pdev);
5512
5513         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5514         if (!netdev) {
5515                 err = -ENOMEM;
5516                 goto err_alloc_etherdev;
5517         }
5518
5519         SET_NETDEV_DEV(netdev, &pdev->dev);
5520
5521         pci_set_drvdata(pdev, netdev);
5522         adapter = netdev_priv(netdev);
5523
5524         adapter->netdev = netdev;
5525         adapter->pdev = pdev;
5526         hw = &adapter->hw;
5527         hw->back = adapter;
5528         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5529
5530         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5531                               pci_resource_len(pdev, 0));
5532         if (!hw->hw_addr) {
5533                 err = -EIO;
5534                 goto err_ioremap;
5535         }
5536
5537         for (i = 1; i <= 5; i++) {
5538                 if (pci_resource_len(pdev, i) == 0)
5539                         continue;
5540         }
5541
5542         netdev->netdev_ops = &ixgbe_netdev_ops;
5543         ixgbe_set_ethtool_ops(netdev);
5544         netdev->watchdog_timeo = 5 * HZ;
5545         strcpy(netdev->name, pci_name(pdev));
5546
5547         adapter->bd_number = cards_found;
5548
5549         /* Setup hw api */
5550         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5551         hw->mac.type  = ii->mac;
5552
5553         /* EEPROM */
5554         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5555         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5556         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5557         if (!(eec & (1 << 8)))
5558                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5559
5560         /* PHY */
5561         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5562         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5563         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5564         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5565         hw->phy.mdio.mmds = 0;
5566         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5567         hw->phy.mdio.dev = netdev;
5568         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5569         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5570
5571         /* set up this timer and work struct before calling get_invariants
5572          * which might start the timer
5573          */
5574         init_timer(&adapter->sfp_timer);
5575         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5576         adapter->sfp_timer.data = (unsigned long) adapter;
5577
5578         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5579
5580         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5581         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5582
5583         /* a new SFP+ module arrival, called from GPI SDP2 context */
5584         INIT_WORK(&adapter->sfp_config_module_task,
5585                   ixgbe_sfp_config_module_task);
5586
5587         ii->get_invariants(hw);
5588
5589         /* setup the private structure */
5590         err = ixgbe_sw_init(adapter);
5591         if (err)
5592                 goto err_sw_init;
5593
5594         /*
5595          * If there is a fan on this device and it has failed log the
5596          * failure.
5597          */
5598         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5599                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5600                 if (esdp & IXGBE_ESDP_SDP1)
5601                         DPRINTK(PROBE, CRIT,
5602                                 "Fan has stopped, replace the adapter\n");
5603         }
5604
5605         /* reset_hw fills in the perm_addr as well */
5606         err = hw->mac.ops.reset_hw(hw);
5607         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5608             hw->mac.type == ixgbe_mac_82598EB) {
5609                 /*
5610                  * Start a kernel thread to watch for a module to arrive.
5611                  * Only do this for 82598, since 82599 will generate
5612                  * interrupts on module arrival.
5613                  */
5614                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5615                 mod_timer(&adapter->sfp_timer,
5616                           round_jiffies(jiffies + (2 * HZ)));
5617                 err = 0;
5618         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5619                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5620                         "an unsupported SFP+ module type was detected.\n"
5621                         "Reload the driver after installing a supported "
5622                         "module.\n");
5623                 goto err_sw_init;
5624         } else if (err) {
5625                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5626                 goto err_sw_init;
5627         }
5628
5629         netdev->features = NETIF_F_SG |
5630                            NETIF_F_IP_CSUM |
5631                            NETIF_F_HW_VLAN_TX |
5632                            NETIF_F_HW_VLAN_RX |
5633                            NETIF_F_HW_VLAN_FILTER;
5634
5635         netdev->features |= NETIF_F_IPV6_CSUM;
5636         netdev->features |= NETIF_F_TSO;
5637         netdev->features |= NETIF_F_TSO6;
5638         netdev->features |= NETIF_F_GRO;
5639
5640         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5641                 netdev->features |= NETIF_F_SCTP_CSUM;
5642
5643         netdev->vlan_features |= NETIF_F_TSO;
5644         netdev->vlan_features |= NETIF_F_TSO6;
5645         netdev->vlan_features |= NETIF_F_IP_CSUM;
5646         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5647         netdev->vlan_features |= NETIF_F_SG;
5648
5649         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5650                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5651
5652 #ifdef CONFIG_IXGBE_DCB
5653         netdev->dcbnl_ops = &dcbnl_ops;
5654 #endif
5655
5656 #ifdef IXGBE_FCOE
5657         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5658                 if (hw->mac.ops.get_device_caps) {
5659                         hw->mac.ops.get_device_caps(hw, &device_caps);
5660                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5661                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5662                 }
5663         }
5664 #endif /* IXGBE_FCOE */
5665         if (pci_using_dac)
5666                 netdev->features |= NETIF_F_HIGHDMA;
5667
5668         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5669                 netdev->features |= NETIF_F_LRO;
5670
5671         /* make sure the EEPROM is good */
5672         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5673                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5674                 err = -EIO;
5675                 goto err_eeprom;
5676         }
5677
5678         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5679         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5680
5681         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5682                 dev_err(&pdev->dev, "invalid MAC address\n");
5683                 err = -EIO;
5684                 goto err_eeprom;
5685         }
5686
5687         init_timer(&adapter->watchdog_timer);
5688         adapter->watchdog_timer.function = &ixgbe_watchdog;
5689         adapter->watchdog_timer.data = (unsigned long)adapter;
5690
5691         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5692         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5693
5694         err = ixgbe_init_interrupt_scheme(adapter);
5695         if (err)
5696                 goto err_sw_init;
5697
5698         switch (pdev->device) {
5699         case IXGBE_DEV_ID_82599_KX4:
5700                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5701                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5702                 /* Enable ACPI wakeup in GRC */
5703                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5704                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5705                 break;
5706         default:
5707                 adapter->wol = 0;
5708                 break;
5709         }
5710         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5711
5712         /* pick up the PCI bus settings for reporting later */
5713         hw->mac.ops.get_bus_info(hw);
5714
5715         /* print bus type/speed/width info */
5716         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5717                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5718                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5719                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5720                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5721                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5722                  "Unknown"),
5723                 netdev->dev_addr);
5724         ixgbe_read_pba_num_generic(hw, &part_num);
5725         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5726                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5727                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5728                          (part_num >> 8), (part_num & 0xff));
5729         else
5730                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5731                          hw->mac.type, hw->phy.type,
5732                          (part_num >> 8), (part_num & 0xff));
5733
5734         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5735                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5736                          "this card is not sufficient for optimal "
5737                          "performance.\n");
5738                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5739                          "PCI-Express slot is required.\n");
5740         }
5741
5742         /* save off EEPROM version number */
5743         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5744
5745         /* reset the hardware with the new settings */
5746         err = hw->mac.ops.start_hw(hw);
5747
5748         if (err == IXGBE_ERR_EEPROM_VERSION) {
5749                 /* We are running on a pre-production device, log a warning */
5750                 dev_warn(&pdev->dev, "This device is a pre-production "
5751                          "adapter/LOM.  Please be aware there may be issues "
5752                          "associated with your hardware.  If you are "
5753                          "experiencing problems please contact your Intel or "
5754                          "hardware representative who provided you with this "
5755                          "hardware.\n");
5756         }
5757         strcpy(netdev->name, "eth%d");
5758         err = register_netdev(netdev);
5759         if (err)
5760                 goto err_register;
5761
5762         /* carrier off reporting is important to ethtool even BEFORE open */
5763         netif_carrier_off(netdev);
5764
5765         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5766             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5767                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5768
5769 #ifdef CONFIG_IXGBE_DCA
5770         if (dca_add_requester(&pdev->dev) == 0) {
5771                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5772                 ixgbe_setup_dca(adapter);
5773         }
5774 #endif
5775         /* add san mac addr to netdev */
5776         ixgbe_add_sanmac_netdev(netdev);
5777
5778         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5779         cards_found++;
5780         return 0;
5781
5782 err_register:
5783         ixgbe_release_hw_control(adapter);
5784         ixgbe_clear_interrupt_scheme(adapter);
5785 err_sw_init:
5786 err_eeprom:
5787         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5788         del_timer_sync(&adapter->sfp_timer);
5789         cancel_work_sync(&adapter->sfp_task);
5790         cancel_work_sync(&adapter->multispeed_fiber_task);
5791         cancel_work_sync(&adapter->sfp_config_module_task);
5792         iounmap(hw->hw_addr);
5793 err_ioremap:
5794         free_netdev(netdev);
5795 err_alloc_etherdev:
5796         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5797                                      IORESOURCE_MEM));
5798 err_pci_reg:
5799 err_dma:
5800         pci_disable_device(pdev);
5801         return err;
5802 }
5803
5804 /**
5805  * ixgbe_remove - Device Removal Routine
5806  * @pdev: PCI device information struct
5807  *
5808  * ixgbe_remove is called by the PCI subsystem to alert the driver
5809  * that it should release a PCI device.  The could be caused by a
5810  * Hot-Plug event, or because the driver is going to be removed from
5811  * memory.
5812  **/
5813 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5814 {
5815         struct net_device *netdev = pci_get_drvdata(pdev);
5816         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5817
5818         set_bit(__IXGBE_DOWN, &adapter->state);
5819         /* clear the module not found bit to make sure the worker won't
5820          * reschedule
5821          */
5822         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5823         del_timer_sync(&adapter->watchdog_timer);
5824
5825         del_timer_sync(&adapter->sfp_timer);
5826         cancel_work_sync(&adapter->watchdog_task);
5827         cancel_work_sync(&adapter->sfp_task);
5828         cancel_work_sync(&adapter->multispeed_fiber_task);
5829         cancel_work_sync(&adapter->sfp_config_module_task);
5830         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5831             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5832                 cancel_work_sync(&adapter->fdir_reinit_task);
5833         flush_scheduled_work();
5834
5835 #ifdef CONFIG_IXGBE_DCA
5836         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5837                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5838                 dca_remove_requester(&pdev->dev);
5839                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5840         }
5841
5842 #endif
5843 #ifdef IXGBE_FCOE
5844         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5845                 ixgbe_cleanup_fcoe(adapter);
5846
5847 #endif /* IXGBE_FCOE */
5848
5849         /* remove the added san mac */
5850         ixgbe_del_sanmac_netdev(netdev);
5851
5852         if (netdev->reg_state == NETREG_REGISTERED)
5853                 unregister_netdev(netdev);
5854
5855         ixgbe_clear_interrupt_scheme(adapter);
5856
5857         ixgbe_release_hw_control(adapter);
5858
5859         iounmap(adapter->hw.hw_addr);
5860         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5861                                      IORESOURCE_MEM));
5862
5863         DPRINTK(PROBE, INFO, "complete\n");
5864
5865         free_netdev(netdev);
5866
5867         pci_disable_pcie_error_reporting(pdev);
5868
5869         pci_disable_device(pdev);
5870 }
5871
5872 /**
5873  * ixgbe_io_error_detected - called when PCI error is detected
5874  * @pdev: Pointer to PCI device
5875  * @state: The current pci connection state
5876  *
5877  * This function is called after a PCI bus error affecting
5878  * this device has been detected.
5879  */
5880 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5881                                                 pci_channel_state_t state)
5882 {
5883         struct net_device *netdev = pci_get_drvdata(pdev);
5884         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5885
5886         netif_device_detach(netdev);
5887
5888         if (state == pci_channel_io_perm_failure)
5889                 return PCI_ERS_RESULT_DISCONNECT;
5890
5891         if (netif_running(netdev))
5892                 ixgbe_down(adapter);
5893         pci_disable_device(pdev);
5894
5895         /* Request a slot reset. */
5896         return PCI_ERS_RESULT_NEED_RESET;
5897 }
5898
5899 /**
5900  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5901  * @pdev: Pointer to PCI device
5902  *
5903  * Restart the card from scratch, as if from a cold-boot.
5904  */
5905 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5906 {
5907         struct net_device *netdev = pci_get_drvdata(pdev);
5908         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5909         pci_ers_result_t result;
5910         int err;
5911
5912         if (pci_enable_device_mem(pdev)) {
5913                 DPRINTK(PROBE, ERR,
5914                         "Cannot re-enable PCI device after reset.\n");
5915                 result = PCI_ERS_RESULT_DISCONNECT;
5916         } else {
5917                 pci_set_master(pdev);
5918                 pci_restore_state(pdev);
5919
5920                 pci_wake_from_d3(pdev, false);
5921
5922                 ixgbe_reset(adapter);
5923                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5924                 result = PCI_ERS_RESULT_RECOVERED;
5925         }
5926
5927         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5928         if (err) {
5929                 dev_err(&pdev->dev,
5930                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5931                 /* non-fatal, continue */
5932         }
5933
5934         return result;
5935 }
5936
5937 /**
5938  * ixgbe_io_resume - called when traffic can start flowing again.
5939  * @pdev: Pointer to PCI device
5940  *
5941  * This callback is called when the error recovery driver tells us that
5942  * its OK to resume normal operation.
5943  */
5944 static void ixgbe_io_resume(struct pci_dev *pdev)
5945 {
5946         struct net_device *netdev = pci_get_drvdata(pdev);
5947         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5948
5949         if (netif_running(netdev)) {
5950                 if (ixgbe_up(adapter)) {
5951                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5952                         return;
5953                 }
5954         }
5955
5956         netif_device_attach(netdev);
5957 }
5958
5959 static struct pci_error_handlers ixgbe_err_handler = {
5960         .error_detected = ixgbe_io_error_detected,
5961         .slot_reset = ixgbe_io_slot_reset,
5962         .resume = ixgbe_io_resume,
5963 };
5964
5965 static struct pci_driver ixgbe_driver = {
5966         .name     = ixgbe_driver_name,
5967         .id_table = ixgbe_pci_tbl,
5968         .probe    = ixgbe_probe,
5969         .remove   = __devexit_p(ixgbe_remove),
5970 #ifdef CONFIG_PM
5971         .suspend  = ixgbe_suspend,
5972         .resume   = ixgbe_resume,
5973 #endif
5974         .shutdown = ixgbe_shutdown,
5975         .err_handler = &ixgbe_err_handler
5976 };
5977
5978 /**
5979  * ixgbe_init_module - Driver Registration Routine
5980  *
5981  * ixgbe_init_module is the first routine called when the driver is
5982  * loaded. All it does is register with the PCI subsystem.
5983  **/
5984 static int __init ixgbe_init_module(void)
5985 {
5986         int ret;
5987         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5988                ixgbe_driver_string, ixgbe_driver_version);
5989
5990         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5991
5992 #ifdef CONFIG_IXGBE_DCA
5993         dca_register_notify(&dca_notifier);
5994 #endif
5995
5996         ret = pci_register_driver(&ixgbe_driver);
5997         return ret;
5998 }
5999
6000 module_init(ixgbe_init_module);
6001
6002 /**
6003  * ixgbe_exit_module - Driver Exit Cleanup Routine
6004  *
6005  * ixgbe_exit_module is called just before the driver is removed
6006  * from memory.
6007  **/
6008 static void __exit ixgbe_exit_module(void)
6009 {
6010 #ifdef CONFIG_IXGBE_DCA
6011         dca_unregister_notify(&dca_notifier);
6012 #endif
6013         pci_unregister_driver(&ixgbe_driver);
6014 }
6015
6016 #ifdef CONFIG_IXGBE_DCA
6017 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6018                             void *p)
6019 {
6020         int ret_val;
6021
6022         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6023                                          __ixgbe_notify_dca);
6024
6025         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6026 }
6027
6028 #endif /* CONFIG_IXGBE_DCA */
6029 #ifdef DEBUG
6030 /**
6031  * ixgbe_get_hw_dev_name - return device name string
6032  * used by hardware layer to print debugging information
6033  **/
6034 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6035 {
6036         struct ixgbe_adapter *adapter = hw->back;
6037         return adapter->netdev->name;
6038 }
6039
6040 #endif
6041 module_exit(ixgbe_exit_module);
6042
6043 /* ixgbe_main.c */