1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
46 #include "ixgbe_common.h"
48 char ixgbe_driver_name[] = "ixgbe";
49 static const char ixgbe_driver_string[] =
50 "Intel(R) 10 Gigabit PCI Express Network Driver";
52 #define DRV_VERSION "2.0.37-k2"
53 const char ixgbe_driver_version[] = DRV_VERSION;
54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
57 [board_82598] = &ixgbe_82598_info,
58 [board_82599] = &ixgbe_82599_info,
61 /* ixgbe_pci_tbl - PCI Device ID Table
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
69 static struct pci_device_id ixgbe_pci_tbl[] = {
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
101 /* required last entry */
104 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
106 #ifdef CONFIG_IXGBE_DCA
107 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
109 static struct notifier_block dca_notifier = {
110 .notifier_call = ixgbe_notify_dca,
116 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
117 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
118 MODULE_LICENSE("GPL");
119 MODULE_VERSION(DRV_VERSION);
121 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
123 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
127 /* Let firmware take over control of h/w */
128 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
129 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
130 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
133 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
137 /* Let firmware know the driver has taken over */
138 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
139 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
140 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
144 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
145 * @adapter: pointer to adapter struct
146 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
147 * @queue: queue to map the corresponding interrupt to
148 * @msix_vector: the vector to map to the corresponding queue
151 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
152 u8 queue, u8 msix_vector)
155 struct ixgbe_hw *hw = &adapter->hw;
156 switch (hw->mac.type) {
157 case ixgbe_mac_82598EB:
158 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
161 index = (((direction * 64) + queue) >> 2) & 0x1F;
162 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
163 ivar &= ~(0xFF << (8 * (queue & 0x3)));
164 ivar |= (msix_vector << (8 * (queue & 0x3)));
165 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
167 case ixgbe_mac_82599EB:
168 if (direction == -1) {
170 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
171 index = ((queue & 1) * 8);
172 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
173 ivar &= ~(0xFF << index);
174 ivar |= (msix_vector << index);
175 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
178 /* tx or rx causes */
179 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
180 index = ((16 * (queue & 1)) + (8 * direction));
181 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
182 ivar &= ~(0xFF << index);
183 ivar |= (msix_vector << index);
184 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
192 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
197 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
198 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
201 mask = (qmask & 0xFFFFFFFF);
202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
203 mask = (qmask >> 32);
204 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
208 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
209 struct ixgbe_tx_buffer
212 tx_buffer_info->dma = 0;
213 if (tx_buffer_info->skb) {
214 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
216 dev_kfree_skb_any(tx_buffer_info->skb);
217 tx_buffer_info->skb = NULL;
219 tx_buffer_info->time_stamp = 0;
220 /* tx_buffer_info must be completely set up in the transmit path */
223 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
224 struct ixgbe_ring *tx_ring,
227 struct ixgbe_hw *hw = &adapter->hw;
229 /* Detect a transmit hang in hardware, this serializes the
230 * check with the clearing of time_stamp and movement of eop */
231 adapter->detect_tx_hung = false;
232 if (tx_ring->tx_buffer_info[eop].time_stamp &&
233 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
234 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
235 /* detected Tx unit hang */
236 union ixgbe_adv_tx_desc *tx_desc;
237 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
238 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
240 " TDH, TDT <%x>, <%x>\n"
241 " next_to_use <%x>\n"
242 " next_to_clean <%x>\n"
243 "tx_buffer_info[next_to_clean]\n"
244 " time_stamp <%lx>\n"
246 tx_ring->queue_index,
247 IXGBE_READ_REG(hw, tx_ring->head),
248 IXGBE_READ_REG(hw, tx_ring->tail),
249 tx_ring->next_to_use, eop,
250 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
257 #define IXGBE_MAX_TXD_PWR 14
258 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
260 /* Tx Descriptors needed, worst case */
261 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
262 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
263 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
264 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
266 static void ixgbe_tx_timeout(struct net_device *netdev);
269 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
270 * @q_vector: structure containing interrupt and ring information
271 * @tx_ring: tx ring to clean
273 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
274 struct ixgbe_ring *tx_ring)
276 struct ixgbe_adapter *adapter = q_vector->adapter;
277 struct net_device *netdev = adapter->netdev;
278 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
279 struct ixgbe_tx_buffer *tx_buffer_info;
280 unsigned int i, eop, count = 0;
281 unsigned int total_bytes = 0, total_packets = 0;
283 i = tx_ring->next_to_clean;
284 eop = tx_ring->tx_buffer_info[i].next_to_watch;
285 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
287 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
288 (count < tx_ring->work_limit)) {
289 bool cleaned = false;
290 for ( ; !cleaned; count++) {
292 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
293 tx_buffer_info = &tx_ring->tx_buffer_info[i];
294 cleaned = (i == eop);
295 skb = tx_buffer_info->skb;
297 if (cleaned && skb) {
298 unsigned int segs, bytecount;
299 unsigned int hlen = skb_headlen(skb);
301 /* gso_segs is currently only valid for tcp */
302 segs = skb_shinfo(skb)->gso_segs ?: 1;
304 /* adjust for FCoE Sequence Offload */
305 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
306 && (skb->protocol == htons(ETH_P_FCOE)) &&
308 hlen = skb_transport_offset(skb) +
309 sizeof(struct fc_frame_header) +
310 sizeof(struct fcoe_crc_eof);
311 segs = DIV_ROUND_UP(skb->len - hlen,
312 skb_shinfo(skb)->gso_size);
314 #endif /* IXGBE_FCOE */
315 /* multiply data chunks by size of headers */
316 bytecount = ((segs - 1) * hlen) + skb->len;
317 total_packets += segs;
318 total_bytes += bytecount;
321 ixgbe_unmap_and_free_tx_resource(adapter,
324 tx_desc->wb.status = 0;
327 if (i == tx_ring->count)
331 eop = tx_ring->tx_buffer_info[i].next_to_watch;
332 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
335 tx_ring->next_to_clean = i;
337 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
338 if (unlikely(count && netif_carrier_ok(netdev) &&
339 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
340 /* Make sure that anybody stopping the queue after this
341 * sees the new next_to_clean.
344 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
345 !test_bit(__IXGBE_DOWN, &adapter->state)) {
346 netif_wake_subqueue(netdev, tx_ring->queue_index);
347 ++adapter->restart_queue;
351 if (adapter->detect_tx_hung) {
352 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
353 /* schedule immediate reset if we believe we hung */
355 "tx hang %d detected, resetting adapter\n",
356 adapter->tx_timeout_count + 1);
357 ixgbe_tx_timeout(adapter->netdev);
361 /* re-arm the interrupt */
362 if (count >= tx_ring->work_limit)
363 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
365 tx_ring->total_bytes += total_bytes;
366 tx_ring->total_packets += total_packets;
367 tx_ring->stats.packets += total_packets;
368 tx_ring->stats.bytes += total_bytes;
369 adapter->net_stats.tx_bytes += total_bytes;
370 adapter->net_stats.tx_packets += total_packets;
371 return (count < tx_ring->work_limit);
374 #ifdef CONFIG_IXGBE_DCA
375 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
376 struct ixgbe_ring *rx_ring)
380 int q = rx_ring - adapter->rx_ring;
382 if (rx_ring->cpu != cpu) {
383 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
384 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
385 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
386 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
387 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
388 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
389 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
390 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
392 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
393 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
394 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
395 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
396 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
403 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
404 struct ixgbe_ring *tx_ring)
408 int q = tx_ring - adapter->tx_ring;
410 if (tx_ring->cpu != cpu) {
411 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
412 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
413 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
414 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
415 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
416 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
417 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
418 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
420 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
427 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
431 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
434 /* always use CB2 mode, difference is masked in the CB driver */
435 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
437 for (i = 0; i < adapter->num_tx_queues; i++) {
438 adapter->tx_ring[i].cpu = -1;
439 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
441 for (i = 0; i < adapter->num_rx_queues; i++) {
442 adapter->rx_ring[i].cpu = -1;
443 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
447 static int __ixgbe_notify_dca(struct device *dev, void *data)
449 struct net_device *netdev = dev_get_drvdata(dev);
450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
451 unsigned long event = *(unsigned long *)data;
454 case DCA_PROVIDER_ADD:
455 /* if we're already enabled, don't do it again */
456 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
458 if (dca_add_requester(dev) == 0) {
459 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
460 ixgbe_setup_dca(adapter);
463 /* Fall Through since DCA is disabled. */
464 case DCA_PROVIDER_REMOVE:
465 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
466 dca_remove_requester(dev);
467 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
476 #endif /* CONFIG_IXGBE_DCA */
478 * ixgbe_receive_skb - Send a completed packet up the stack
479 * @adapter: board private structure
480 * @skb: packet to send up
481 * @status: hardware indication of status of receive
482 * @rx_ring: rx descriptor ring (for a specific queue) to setup
483 * @rx_desc: rx descriptor
485 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
486 struct sk_buff *skb, u8 status,
487 struct ixgbe_ring *ring,
488 union ixgbe_adv_rx_desc *rx_desc)
490 struct ixgbe_adapter *adapter = q_vector->adapter;
491 struct napi_struct *napi = &q_vector->napi;
492 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
493 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
495 skb_record_rx_queue(skb, ring->queue_index);
496 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
497 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
498 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
500 napi_gro_receive(napi, skb);
502 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
503 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
510 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
511 * @adapter: address of board private structure
512 * @status_err: hardware indication of status of receive
513 * @skb: skb currently being received and modified
515 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
516 union ixgbe_adv_rx_desc *rx_desc,
519 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
521 skb->ip_summed = CHECKSUM_NONE;
523 /* Rx csum disabled */
524 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
527 /* if IP and error */
528 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
529 (status_err & IXGBE_RXDADV_ERR_IPE)) {
530 adapter->hw_csum_rx_error++;
534 if (!(status_err & IXGBE_RXD_STAT_L4CS))
537 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
538 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
541 * 82599 errata, UDP frames with a 0 checksum can be marked as
544 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
545 (adapter->hw.mac.type == ixgbe_mac_82599EB))
548 adapter->hw_csum_rx_error++;
552 /* It must be a TCP or UDP packet with a valid checksum */
553 skb->ip_summed = CHECKSUM_UNNECESSARY;
554 adapter->hw_csum_rx_good++;
557 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
558 struct ixgbe_ring *rx_ring, u32 val)
561 * Force memory writes to complete before letting h/w
562 * know there are new descriptors to fetch. (Only
563 * applicable for weak-ordered memory model archs,
567 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
571 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
572 * @adapter: address of board private structure
574 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
575 struct ixgbe_ring *rx_ring,
578 struct pci_dev *pdev = adapter->pdev;
579 union ixgbe_adv_rx_desc *rx_desc;
580 struct ixgbe_rx_buffer *bi;
583 i = rx_ring->next_to_use;
584 bi = &rx_ring->rx_buffer_info[i];
586 while (cleaned_count--) {
587 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
590 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
592 bi->page = alloc_page(GFP_ATOMIC);
594 adapter->alloc_rx_page_failed++;
599 /* use a half page if we're re-using */
600 bi->page_offset ^= (PAGE_SIZE / 2);
603 bi->page_dma = pci_map_page(pdev, bi->page,
611 skb = netdev_alloc_skb(adapter->netdev,
612 (rx_ring->rx_buf_len +
616 adapter->alloc_rx_buff_failed++;
621 * Make buffer alignment 2 beyond a 16 byte boundary
622 * this will result in a 16 byte aligned IP header after
623 * the 14 byte MAC header is removed
625 skb_reserve(skb, NET_IP_ALIGN);
628 bi->dma = pci_map_single(pdev, skb->data,
632 /* Refresh the desc even if buffer_addrs didn't change because
633 * each write-back erases this info. */
634 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
635 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
636 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
638 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
642 if (i == rx_ring->count)
644 bi = &rx_ring->rx_buffer_info[i];
648 if (rx_ring->next_to_use != i) {
649 rx_ring->next_to_use = i;
651 i = (rx_ring->count - 1);
653 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
657 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
659 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
662 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
664 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
667 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
669 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
670 IXGBE_RXDADV_RSCCNT_MASK) >>
671 IXGBE_RXDADV_RSCCNT_SHIFT;
675 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
676 * @skb: pointer to the last skb in the rsc queue
678 * This function changes a queue full of hw rsc buffers into a completed
679 * packet. It uses the ->prev pointers to find the first packet and then
680 * turns it into the frag list owner.
682 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
684 unsigned int frag_list_size = 0;
687 struct sk_buff *prev = skb->prev;
688 frag_list_size += skb->len;
693 skb_shinfo(skb)->frag_list = skb->next;
695 skb->len += frag_list_size;
696 skb->data_len += frag_list_size;
697 skb->truesize += frag_list_size;
701 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
702 struct ixgbe_ring *rx_ring,
703 int *work_done, int work_to_do)
705 struct ixgbe_adapter *adapter = q_vector->adapter;
706 struct pci_dev *pdev = adapter->pdev;
707 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
708 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
710 unsigned int i, rsc_count = 0;
713 bool cleaned = false;
714 int cleaned_count = 0;
715 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
718 #endif /* IXGBE_FCOE */
720 i = rx_ring->next_to_clean;
721 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
722 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
723 rx_buffer_info = &rx_ring->rx_buffer_info[i];
725 while (staterr & IXGBE_RXD_STAT_DD) {
727 if (*work_done >= work_to_do)
731 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
732 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
733 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
734 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
735 if (hdr_info & IXGBE_RXDADV_SPH)
736 adapter->rx_hdr_split++;
737 if (len > IXGBE_RX_HDR_SIZE)
738 len = IXGBE_RX_HDR_SIZE;
739 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
741 len = le16_to_cpu(rx_desc->wb.upper.length);
745 skb = rx_buffer_info->skb;
746 prefetch(skb->data - NET_IP_ALIGN);
747 rx_buffer_info->skb = NULL;
749 if (rx_buffer_info->dma) {
750 pci_unmap_single(pdev, rx_buffer_info->dma,
753 rx_buffer_info->dma = 0;
758 pci_unmap_page(pdev, rx_buffer_info->page_dma,
759 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
760 rx_buffer_info->page_dma = 0;
761 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762 rx_buffer_info->page,
763 rx_buffer_info->page_offset,
766 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
767 (page_count(rx_buffer_info->page) != 1))
768 rx_buffer_info->page = NULL;
770 get_page(rx_buffer_info->page);
772 skb->len += upper_len;
773 skb->data_len += upper_len;
774 skb->truesize += upper_len;
778 if (i == rx_ring->count)
781 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
785 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
786 rsc_count = ixgbe_get_rsc_count(rx_desc);
789 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
790 IXGBE_RXDADV_NEXTP_SHIFT;
791 next_buffer = &rx_ring->rx_buffer_info[nextp];
792 rx_ring->rsc_count += (rsc_count - 1);
794 next_buffer = &rx_ring->rx_buffer_info[i];
797 if (staterr & IXGBE_RXD_STAT_EOP) {
799 skb = ixgbe_transform_rsc_queue(skb);
800 rx_ring->stats.packets++;
801 rx_ring->stats.bytes += skb->len;
803 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
804 rx_buffer_info->skb = next_buffer->skb;
805 rx_buffer_info->dma = next_buffer->dma;
806 next_buffer->skb = skb;
807 next_buffer->dma = 0;
809 skb->next = next_buffer->skb;
810 skb->next->prev = skb;
812 adapter->non_eop_descs++;
816 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
817 dev_kfree_skb_irq(skb);
821 ixgbe_rx_checksum(adapter, rx_desc, skb);
823 /* probably a little skewed due to removing CRC */
824 total_rx_bytes += skb->len;
827 skb->protocol = eth_type_trans(skb, adapter->netdev);
829 /* if ddp, not passing to ULD unless for FCP_RSP or error */
830 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
831 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
835 #endif /* IXGBE_FCOE */
836 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
839 rx_desc->wb.upper.status_error = 0;
841 /* return some buffers to hardware, one at a time is too slow */
842 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
843 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
847 /* use prefetched values */
849 rx_buffer_info = &rx_ring->rx_buffer_info[i];
851 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
854 rx_ring->next_to_clean = i;
855 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
858 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
861 /* include DDPed FCoE data */
865 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
866 sizeof(struct fc_frame_header) -
867 sizeof(struct fcoe_crc_eof);
870 total_rx_bytes += ddp_bytes;
871 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
873 #endif /* IXGBE_FCOE */
875 rx_ring->total_packets += total_rx_packets;
876 rx_ring->total_bytes += total_rx_bytes;
877 adapter->net_stats.rx_bytes += total_rx_bytes;
878 adapter->net_stats.rx_packets += total_rx_packets;
883 static int ixgbe_clean_rxonly(struct napi_struct *, int);
885 * ixgbe_configure_msix - Configure MSI-X hardware
886 * @adapter: board private structure
888 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
891 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
893 struct ixgbe_q_vector *q_vector;
894 int i, j, q_vectors, v_idx, r_idx;
897 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
900 * Populate the IVAR table and set the ITR values to the
901 * corresponding register.
903 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
904 q_vector = adapter->q_vector[v_idx];
905 /* XXX for_each_bit(...) */
906 r_idx = find_first_bit(q_vector->rxr_idx,
907 adapter->num_rx_queues);
909 for (i = 0; i < q_vector->rxr_count; i++) {
910 j = adapter->rx_ring[r_idx].reg_idx;
911 ixgbe_set_ivar(adapter, 0, j, v_idx);
912 r_idx = find_next_bit(q_vector->rxr_idx,
913 adapter->num_rx_queues,
916 r_idx = find_first_bit(q_vector->txr_idx,
917 adapter->num_tx_queues);
919 for (i = 0; i < q_vector->txr_count; i++) {
920 j = adapter->tx_ring[r_idx].reg_idx;
921 ixgbe_set_ivar(adapter, 1, j, v_idx);
922 r_idx = find_next_bit(q_vector->txr_idx,
923 adapter->num_tx_queues,
927 /* if this is a tx only vector halve the interrupt rate */
928 if (q_vector->txr_count && !q_vector->rxr_count)
929 q_vector->eitr = (adapter->eitr_param >> 1);
930 else if (q_vector->rxr_count)
932 q_vector->eitr = adapter->eitr_param;
934 ixgbe_write_eitr(q_vector);
937 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
938 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
940 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
941 ixgbe_set_ivar(adapter, -1, 1, v_idx);
942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
944 /* set up to autoclear timer, and the vectors */
945 mask = IXGBE_EIMS_ENABLE_MASK;
946 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
954 latency_invalid = 255
958 * ixgbe_update_itr - update the dynamic ITR value based on statistics
959 * @adapter: pointer to adapter
960 * @eitr: eitr setting (ints per sec) to give last timeslice
961 * @itr_setting: current throttle rate in ints/second
962 * @packets: the number of packets during this measurement interval
963 * @bytes: the number of bytes during this measurement interval
965 * Stores a new ITR value based on packets and byte
966 * counts during the last interrupt. The advantage of per interrupt
967 * computation is faster updates and more accurate ITR for the current
968 * traffic pattern. Constants in this function were computed
969 * based on theoretical maximum wire speed and thresholds were set based
970 * on testing data as well as attempting to minimize response time
971 * while increasing bulk throughput.
972 * this functionality is controlled by the InterruptThrottleRate module
973 * parameter (see ixgbe_param.c)
975 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
976 u32 eitr, u8 itr_setting,
977 int packets, int bytes)
979 unsigned int retval = itr_setting;
984 goto update_itr_done;
987 /* simple throttlerate management
988 * 0-20MB/s lowest (100000 ints/s)
989 * 20-100MB/s low (20000 ints/s)
990 * 100-1249MB/s bulk (8000 ints/s)
992 /* what was last interrupt timeslice? */
993 timepassed_us = 1000000/eitr;
994 bytes_perint = bytes / timepassed_us; /* bytes/usec */
996 switch (itr_setting) {
998 if (bytes_perint > adapter->eitr_low)
999 retval = low_latency;
1002 if (bytes_perint > adapter->eitr_high)
1003 retval = bulk_latency;
1004 else if (bytes_perint <= adapter->eitr_low)
1005 retval = lowest_latency;
1008 if (bytes_perint <= adapter->eitr_high)
1009 retval = low_latency;
1018 * ixgbe_write_eitr - write EITR register in hardware specific way
1019 * @q_vector: structure containing interrupt and ring information
1021 * This function is made to be called by ethtool and by the driver
1022 * when it needs to update EITR registers at runtime. Hardware
1023 * specific quirks/differences are taken care of here.
1025 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1027 struct ixgbe_adapter *adapter = q_vector->adapter;
1028 struct ixgbe_hw *hw = &adapter->hw;
1029 int v_idx = q_vector->v_idx;
1030 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1032 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1033 /* must write high and low 16 bits to reset counter */
1034 itr_reg |= (itr_reg << 16);
1035 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1037 * set the WDIS bit to not clear the timer bits and cause an
1038 * immediate assertion of the interrupt
1040 itr_reg |= IXGBE_EITR_CNT_WDIS;
1042 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1045 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1047 struct ixgbe_adapter *adapter = q_vector->adapter;
1049 u8 current_itr, ret_itr;
1051 struct ixgbe_ring *rx_ring, *tx_ring;
1053 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1054 for (i = 0; i < q_vector->txr_count; i++) {
1055 tx_ring = &(adapter->tx_ring[r_idx]);
1056 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1058 tx_ring->total_packets,
1059 tx_ring->total_bytes);
1060 /* if the result for this queue would decrease interrupt
1061 * rate for this vector then use that result */
1062 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1063 q_vector->tx_itr - 1 : ret_itr);
1064 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1068 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1069 for (i = 0; i < q_vector->rxr_count; i++) {
1070 rx_ring = &(adapter->rx_ring[r_idx]);
1071 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1073 rx_ring->total_packets,
1074 rx_ring->total_bytes);
1075 /* if the result for this queue would decrease interrupt
1076 * rate for this vector then use that result */
1077 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1078 q_vector->rx_itr - 1 : ret_itr);
1079 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1083 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1085 switch (current_itr) {
1086 /* counts and packets in update_itr are dependent on these numbers */
1087 case lowest_latency:
1091 new_itr = 20000; /* aka hwitr = ~200 */
1099 if (new_itr != q_vector->eitr) {
1100 /* do an exponential smoothing */
1101 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1103 /* save the algorithm value here, not the smoothed one */
1104 q_vector->eitr = new_itr;
1106 ixgbe_write_eitr(q_vector);
1112 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1114 struct ixgbe_hw *hw = &adapter->hw;
1116 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1117 (eicr & IXGBE_EICR_GPI_SDP1)) {
1118 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1119 /* write to clear the interrupt */
1120 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1124 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1126 struct ixgbe_hw *hw = &adapter->hw;
1128 if (eicr & IXGBE_EICR_GPI_SDP1) {
1129 /* Clear the interrupt */
1130 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1131 schedule_work(&adapter->multispeed_fiber_task);
1132 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1133 /* Clear the interrupt */
1134 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1135 schedule_work(&adapter->sfp_config_module_task);
1137 /* Interrupt isn't for us... */
1142 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1144 struct ixgbe_hw *hw = &adapter->hw;
1147 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1148 adapter->link_check_timeout = jiffies;
1149 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1150 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1151 schedule_work(&adapter->watchdog_task);
1155 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1157 struct net_device *netdev = data;
1158 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1159 struct ixgbe_hw *hw = &adapter->hw;
1163 * Workaround for Silicon errata. Use clear-by-write instead
1164 * of clear-by-read. Reading with EICS will return the
1165 * interrupt causes without clearing, which later be done
1166 * with the write to EICR.
1168 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1169 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1171 if (eicr & IXGBE_EICR_LSC)
1172 ixgbe_check_lsc(adapter);
1174 if (hw->mac.type == ixgbe_mac_82598EB)
1175 ixgbe_check_fan_failure(adapter, eicr);
1177 if (hw->mac.type == ixgbe_mac_82599EB) {
1178 ixgbe_check_sfp_event(adapter, eicr);
1180 /* Handle Flow Director Full threshold interrupt */
1181 if (eicr & IXGBE_EICR_FLOW_DIR) {
1183 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1184 /* Disable transmits before FDIR Re-initialization */
1185 netif_tx_stop_all_queues(netdev);
1186 for (i = 0; i < adapter->num_tx_queues; i++) {
1187 struct ixgbe_ring *tx_ring =
1188 &adapter->tx_ring[i];
1189 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1190 &tx_ring->reinit_state))
1191 schedule_work(&adapter->fdir_reinit_task);
1195 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1196 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1201 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1206 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1207 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1210 mask = (qmask & 0xFFFFFFFF);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1212 mask = (qmask >> 32);
1213 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1215 /* skip the flush */
1218 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1223 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1224 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1225 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1227 mask = (qmask & 0xFFFFFFFF);
1228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1229 mask = (qmask >> 32);
1230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1232 /* skip the flush */
1235 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1237 struct ixgbe_q_vector *q_vector = data;
1238 struct ixgbe_adapter *adapter = q_vector->adapter;
1239 struct ixgbe_ring *tx_ring;
1242 if (!q_vector->txr_count)
1245 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1246 for (i = 0; i < q_vector->txr_count; i++) {
1247 tx_ring = &(adapter->tx_ring[r_idx]);
1248 tx_ring->total_bytes = 0;
1249 tx_ring->total_packets = 0;
1250 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1254 /* disable interrupts on this vector only */
1255 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1256 napi_schedule(&q_vector->napi);
1262 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1264 * @data: pointer to our q_vector struct for this interrupt vector
1266 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1268 struct ixgbe_q_vector *q_vector = data;
1269 struct ixgbe_adapter *adapter = q_vector->adapter;
1270 struct ixgbe_ring *rx_ring;
1274 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1275 for (i = 0; i < q_vector->rxr_count; i++) {
1276 rx_ring = &(adapter->rx_ring[r_idx]);
1277 rx_ring->total_bytes = 0;
1278 rx_ring->total_packets = 0;
1279 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1283 if (!q_vector->rxr_count)
1286 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1287 rx_ring = &(adapter->rx_ring[r_idx]);
1288 /* disable interrupts on this vector only */
1289 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1290 napi_schedule(&q_vector->napi);
1295 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1297 struct ixgbe_q_vector *q_vector = data;
1298 struct ixgbe_adapter *adapter = q_vector->adapter;
1299 struct ixgbe_ring *ring;
1303 if (!q_vector->txr_count && !q_vector->rxr_count)
1306 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1307 for (i = 0; i < q_vector->txr_count; i++) {
1308 ring = &(adapter->tx_ring[r_idx]);
1309 ring->total_bytes = 0;
1310 ring->total_packets = 0;
1311 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1315 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1316 for (i = 0; i < q_vector->rxr_count; i++) {
1317 ring = &(adapter->rx_ring[r_idx]);
1318 ring->total_bytes = 0;
1319 ring->total_packets = 0;
1320 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1324 /* disable interrupts on this vector only */
1325 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1326 napi_schedule(&q_vector->napi);
1332 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1333 * @napi: napi struct with our devices info in it
1334 * @budget: amount of work driver is allowed to do this pass, in packets
1336 * This function is optimized for cleaning one queue only on a single
1339 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1341 struct ixgbe_q_vector *q_vector =
1342 container_of(napi, struct ixgbe_q_vector, napi);
1343 struct ixgbe_adapter *adapter = q_vector->adapter;
1344 struct ixgbe_ring *rx_ring = NULL;
1348 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1349 rx_ring = &(adapter->rx_ring[r_idx]);
1350 #ifdef CONFIG_IXGBE_DCA
1351 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1352 ixgbe_update_rx_dca(adapter, rx_ring);
1355 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1357 /* If all Rx work done, exit the polling mode */
1358 if (work_done < budget) {
1359 napi_complete(napi);
1360 if (adapter->itr_setting & 1)
1361 ixgbe_set_itr_msix(q_vector);
1362 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1363 ixgbe_irq_enable_queues(adapter,
1364 ((u64)1 << q_vector->v_idx));
1371 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1372 * @napi: napi struct with our devices info in it
1373 * @budget: amount of work driver is allowed to do this pass, in packets
1375 * This function will clean more than one rx queue associated with a
1378 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1380 struct ixgbe_q_vector *q_vector =
1381 container_of(napi, struct ixgbe_q_vector, napi);
1382 struct ixgbe_adapter *adapter = q_vector->adapter;
1383 struct ixgbe_ring *ring = NULL;
1384 int work_done = 0, i;
1386 bool tx_clean_complete = true;
1388 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1389 for (i = 0; i < q_vector->txr_count; i++) {
1390 ring = &(adapter->tx_ring[r_idx]);
1391 #ifdef CONFIG_IXGBE_DCA
1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1393 ixgbe_update_tx_dca(adapter, ring);
1395 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1396 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1400 /* attempt to distribute budget to each queue fairly, but don't allow
1401 * the budget to go below 1 because we'll exit polling */
1402 budget /= (q_vector->rxr_count ?: 1);
1403 budget = max(budget, 1);
1404 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1405 for (i = 0; i < q_vector->rxr_count; i++) {
1406 ring = &(adapter->rx_ring[r_idx]);
1407 #ifdef CONFIG_IXGBE_DCA
1408 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1409 ixgbe_update_rx_dca(adapter, ring);
1411 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1412 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1416 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1417 ring = &(adapter->rx_ring[r_idx]);
1418 /* If all Rx work done, exit the polling mode */
1419 if (work_done < budget) {
1420 napi_complete(napi);
1421 if (adapter->itr_setting & 1)
1422 ixgbe_set_itr_msix(q_vector);
1423 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1424 ixgbe_irq_enable_queues(adapter,
1425 ((u64)1 << q_vector->v_idx));
1433 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1434 * @napi: napi struct with our devices info in it
1435 * @budget: amount of work driver is allowed to do this pass, in packets
1437 * This function is optimized for cleaning one queue only on a single
1440 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1442 struct ixgbe_q_vector *q_vector =
1443 container_of(napi, struct ixgbe_q_vector, napi);
1444 struct ixgbe_adapter *adapter = q_vector->adapter;
1445 struct ixgbe_ring *tx_ring = NULL;
1449 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1450 tx_ring = &(adapter->tx_ring[r_idx]);
1451 #ifdef CONFIG_IXGBE_DCA
1452 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1453 ixgbe_update_tx_dca(adapter, tx_ring);
1456 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1459 /* If all Rx work done, exit the polling mode */
1460 if (work_done < budget) {
1461 napi_complete(napi);
1462 if (adapter->itr_setting & 1)
1463 ixgbe_set_itr_msix(q_vector);
1464 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1465 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1471 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1474 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1476 set_bit(r_idx, q_vector->rxr_idx);
1477 q_vector->rxr_count++;
1480 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1483 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1485 set_bit(t_idx, q_vector->txr_idx);
1486 q_vector->txr_count++;
1490 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1491 * @adapter: board private structure to initialize
1492 * @vectors: allotted vector count for descriptor rings
1494 * This function maps descriptor rings to the queue-specific vectors
1495 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1496 * one vector per ring/queue, but on a constrained vector budget, we
1497 * group the rings as "efficiently" as possible. You would add new
1498 * mapping configurations in here.
1500 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1504 int rxr_idx = 0, txr_idx = 0;
1505 int rxr_remaining = adapter->num_rx_queues;
1506 int txr_remaining = adapter->num_tx_queues;
1511 /* No mapping required if MSI-X is disabled. */
1512 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1516 * The ideal configuration...
1517 * We have enough vectors to map one per queue.
1519 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1520 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1521 map_vector_to_rxq(adapter, v_start, rxr_idx);
1523 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1524 map_vector_to_txq(adapter, v_start, txr_idx);
1530 * If we don't have enough vectors for a 1-to-1
1531 * mapping, we'll have to group them so there are
1532 * multiple queues per vector.
1534 /* Re-adjusting *qpv takes care of the remainder. */
1535 for (i = v_start; i < vectors; i++) {
1536 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1537 for (j = 0; j < rqpv; j++) {
1538 map_vector_to_rxq(adapter, i, rxr_idx);
1543 for (i = v_start; i < vectors; i++) {
1544 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1545 for (j = 0; j < tqpv; j++) {
1546 map_vector_to_txq(adapter, i, txr_idx);
1557 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1558 * @adapter: board private structure
1560 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1561 * interrupts from the kernel.
1563 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1565 struct net_device *netdev = adapter->netdev;
1566 irqreturn_t (*handler)(int, void *);
1567 int i, vector, q_vectors, err;
1570 /* Decrement for Other and TCP Timer vectors */
1571 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1573 /* Map the Tx/Rx rings to the vectors we were allotted. */
1574 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1578 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1579 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1580 &ixgbe_msix_clean_many)
1581 for (vector = 0; vector < q_vectors; vector++) {
1582 handler = SET_HANDLER(adapter->q_vector[vector]);
1584 if(handler == &ixgbe_msix_clean_rx) {
1585 sprintf(adapter->name[vector], "%s-%s-%d",
1586 netdev->name, "rx", ri++);
1588 else if(handler == &ixgbe_msix_clean_tx) {
1589 sprintf(adapter->name[vector], "%s-%s-%d",
1590 netdev->name, "tx", ti++);
1593 sprintf(adapter->name[vector], "%s-%s-%d",
1594 netdev->name, "TxRx", vector);
1596 err = request_irq(adapter->msix_entries[vector].vector,
1597 handler, 0, adapter->name[vector],
1598 adapter->q_vector[vector]);
1601 "request_irq failed for MSIX interrupt "
1602 "Error: %d\n", err);
1603 goto free_queue_irqs;
1607 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1608 err = request_irq(adapter->msix_entries[vector].vector,
1609 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1612 "request_irq for msix_lsc failed: %d\n", err);
1613 goto free_queue_irqs;
1619 for (i = vector - 1; i >= 0; i--)
1620 free_irq(adapter->msix_entries[--vector].vector,
1621 adapter->q_vector[i]);
1622 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1623 pci_disable_msix(adapter->pdev);
1624 kfree(adapter->msix_entries);
1625 adapter->msix_entries = NULL;
1630 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1632 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1634 u32 new_itr = q_vector->eitr;
1635 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1636 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1638 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1640 tx_ring->total_packets,
1641 tx_ring->total_bytes);
1642 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1644 rx_ring->total_packets,
1645 rx_ring->total_bytes);
1647 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1649 switch (current_itr) {
1650 /* counts and packets in update_itr are dependent on these numbers */
1651 case lowest_latency:
1655 new_itr = 20000; /* aka hwitr = ~200 */
1664 if (new_itr != q_vector->eitr) {
1665 /* do an exponential smoothing */
1666 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1668 /* save the algorithm value here, not the smoothed one */
1669 q_vector->eitr = new_itr;
1671 ixgbe_write_eitr(q_vector);
1678 * ixgbe_irq_enable - Enable default interrupt generation settings
1679 * @adapter: board private structure
1681 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1685 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1687 mask |= IXGBE_EIMS_GPI_SDP1;
1688 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1689 mask |= IXGBE_EIMS_ECC;
1690 mask |= IXGBE_EIMS_GPI_SDP1;
1691 mask |= IXGBE_EIMS_GPI_SDP2;
1693 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1694 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1695 mask |= IXGBE_EIMS_FLOW_DIR;
1697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1698 ixgbe_irq_enable_queues(adapter, ~0);
1699 IXGBE_WRITE_FLUSH(&adapter->hw);
1703 * ixgbe_intr - legacy mode Interrupt Handler
1704 * @irq: interrupt number
1705 * @data: pointer to a network interface device structure
1707 static irqreturn_t ixgbe_intr(int irq, void *data)
1709 struct net_device *netdev = data;
1710 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1711 struct ixgbe_hw *hw = &adapter->hw;
1712 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1716 * Workaround for silicon errata. Mask the interrupts
1717 * before the read of EICR.
1719 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1721 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1722 * therefore no explict interrupt disable is necessary */
1723 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1725 /* shared interrupt alert!
1726 * make sure interrupts are enabled because the read will
1727 * have disabled interrupts due to EIAM */
1728 ixgbe_irq_enable(adapter);
1729 return IRQ_NONE; /* Not our interrupt */
1732 if (eicr & IXGBE_EICR_LSC)
1733 ixgbe_check_lsc(adapter);
1735 if (hw->mac.type == ixgbe_mac_82599EB)
1736 ixgbe_check_sfp_event(adapter, eicr);
1738 ixgbe_check_fan_failure(adapter, eicr);
1740 if (napi_schedule_prep(&(q_vector->napi))) {
1741 adapter->tx_ring[0].total_packets = 0;
1742 adapter->tx_ring[0].total_bytes = 0;
1743 adapter->rx_ring[0].total_packets = 0;
1744 adapter->rx_ring[0].total_bytes = 0;
1745 /* would disable interrupts here but EIAM disabled it */
1746 __napi_schedule(&(q_vector->napi));
1752 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1754 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1756 for (i = 0; i < q_vectors; i++) {
1757 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1758 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1759 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1760 q_vector->rxr_count = 0;
1761 q_vector->txr_count = 0;
1766 * ixgbe_request_irq - initialize interrupts
1767 * @adapter: board private structure
1769 * Attempts to configure interrupts using the best available
1770 * capabilities of the hardware and kernel.
1772 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1774 struct net_device *netdev = adapter->netdev;
1777 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1778 err = ixgbe_request_msix_irqs(adapter);
1779 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1780 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1781 netdev->name, netdev);
1783 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1784 netdev->name, netdev);
1788 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1793 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1795 struct net_device *netdev = adapter->netdev;
1797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1800 q_vectors = adapter->num_msix_vectors;
1803 free_irq(adapter->msix_entries[i].vector, netdev);
1806 for (; i >= 0; i--) {
1807 free_irq(adapter->msix_entries[i].vector,
1808 adapter->q_vector[i]);
1811 ixgbe_reset_q_vectors(adapter);
1813 free_irq(adapter->pdev->irq, netdev);
1818 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1819 * @adapter: board private structure
1821 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1823 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1830 IXGBE_WRITE_FLUSH(&adapter->hw);
1831 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1833 for (i = 0; i < adapter->num_msix_vectors; i++)
1834 synchronize_irq(adapter->msix_entries[i].vector);
1836 synchronize_irq(adapter->pdev->irq);
1841 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1844 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1846 struct ixgbe_hw *hw = &adapter->hw;
1848 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1849 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1851 ixgbe_set_ivar(adapter, 0, 0, 0);
1852 ixgbe_set_ivar(adapter, 1, 0, 0);
1854 map_vector_to_rxq(adapter, 0, 0);
1855 map_vector_to_txq(adapter, 0, 0);
1857 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1861 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1862 * @adapter: board private structure
1864 * Configure the Tx unit of the MAC after a reset.
1866 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1869 struct ixgbe_hw *hw = &adapter->hw;
1870 u32 i, j, tdlen, txctrl;
1872 /* Setup the HW Tx Head and Tail descriptor pointers */
1873 for (i = 0; i < adapter->num_tx_queues; i++) {
1874 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1877 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1878 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1879 (tdba & DMA_BIT_MASK(32)));
1880 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1881 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1882 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1883 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1884 adapter->tx_ring[i].head = IXGBE_TDH(j);
1885 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1886 /* Disable Tx Head Writeback RO bit, since this hoses
1887 * bookkeeping if things aren't delivered in order.
1889 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1890 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1891 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1893 if (hw->mac.type == ixgbe_mac_82599EB) {
1894 /* We enable 8 traffic classes, DCB only */
1895 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1896 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1897 IXGBE_MTQC_8TC_8TQ));
1901 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1903 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1904 struct ixgbe_ring *rx_ring)
1908 struct ixgbe_ring_feature *feature = adapter->ring_feature;
1910 index = rx_ring->reg_idx;
1911 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1913 mask = (unsigned long) feature[RING_F_RSS].mask;
1914 index = index & mask;
1916 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1918 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1919 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1921 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1922 IXGBE_SRRCTL_BSIZEHDR_MASK;
1924 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1925 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1926 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1928 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1930 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1932 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1933 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1934 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1937 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1940 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1945 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1948 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1949 #ifdef CONFIG_IXGBE_DCB
1950 | IXGBE_FLAG_DCB_ENABLED
1955 case (IXGBE_FLAG_RSS_ENABLED):
1956 mrqc = IXGBE_MRQC_RSSEN;
1958 #ifdef CONFIG_IXGBE_DCB
1959 case (IXGBE_FLAG_DCB_ENABLED):
1960 mrqc = IXGBE_MRQC_RT8TCEN;
1962 #endif /* CONFIG_IXGBE_DCB */
1971 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1972 * @adapter: board private structure
1974 * Configure the Rx unit of the MAC after a reset.
1976 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1979 struct ixgbe_hw *hw = &adapter->hw;
1980 struct ixgbe_ring *rx_ring;
1981 struct net_device *netdev = adapter->netdev;
1982 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1984 u32 rdlen, rxctrl, rxcsum;
1985 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1986 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1987 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1989 u32 reta = 0, mrqc = 0;
1994 /* Decide whether to use packet split mode or not */
1995 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1997 /* Set the RX buffer length according to the mode */
1998 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1999 rx_buf_len = IXGBE_RX_HDR_SIZE;
2000 if (hw->mac.type == ixgbe_mac_82599EB) {
2001 /* PSRTYPE must be initialized in 82599 */
2002 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2003 IXGBE_PSRTYPE_UDPHDR |
2004 IXGBE_PSRTYPE_IPV4HDR |
2005 IXGBE_PSRTYPE_IPV6HDR |
2006 IXGBE_PSRTYPE_L2HDR;
2007 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2010 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2011 (netdev->mtu <= ETH_DATA_LEN))
2012 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2014 rx_buf_len = ALIGN(max_frame, 1024);
2017 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2018 fctrl |= IXGBE_FCTRL_BAM;
2019 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2020 fctrl |= IXGBE_FCTRL_PMCF;
2021 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2023 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2024 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2025 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2027 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2029 if (netdev->features & NETIF_F_FCOE_MTU)
2030 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2032 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2034 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2035 /* disable receives while setting up the descriptors */
2036 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2037 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2040 * Setup the HW Rx Head and Tail Descriptor Pointers and
2041 * the Base and Length of the Rx Descriptor Ring
2043 for (i = 0; i < adapter->num_rx_queues; i++) {
2044 rx_ring = &adapter->rx_ring[i];
2045 rdba = rx_ring->dma;
2046 j = rx_ring->reg_idx;
2047 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2048 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2049 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2050 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2051 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2052 rx_ring->head = IXGBE_RDH(j);
2053 rx_ring->tail = IXGBE_RDT(j);
2054 rx_ring->rx_buf_len = rx_buf_len;
2056 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2057 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2060 if (netdev->features & NETIF_F_FCOE_MTU) {
2061 struct ixgbe_ring_feature *f;
2062 f = &adapter->ring_feature[RING_F_FCOE];
2063 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2064 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2065 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2066 rx_ring->rx_buf_len =
2067 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2071 #endif /* IXGBE_FCOE */
2072 ixgbe_configure_srrctl(adapter, rx_ring);
2075 if (hw->mac.type == ixgbe_mac_82598EB) {
2077 * For VMDq support of different descriptor types or
2078 * buffer sizes through the use of multiple SRRCTL
2079 * registers, RDRXCTL.MVMEN must be set to 1
2081 * also, the manual doesn't mention it clearly but DCA hints
2082 * will only use queue 0's tags unless this bit is set. Side
2083 * effects of setting this bit are only that SRRCTL must be
2084 * fully programmed [0..15]
2086 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2087 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2088 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2091 /* Program MRQC for the distribution of queues */
2092 mrqc = ixgbe_setup_mrqc(adapter);
2094 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2095 /* Fill out redirection table */
2096 for (i = 0, j = 0; i < 128; i++, j++) {
2097 if (j == adapter->ring_feature[RING_F_RSS].indices)
2099 /* reta = 4-byte sliding window of
2100 * 0x00..(indices-1)(indices-1)00..etc. */
2101 reta = (reta << 8) | (j * 0x11);
2103 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2106 /* Fill out hash function seeds */
2107 for (i = 0; i < 10; i++)
2108 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2110 if (hw->mac.type == ixgbe_mac_82598EB)
2111 mrqc |= IXGBE_MRQC_RSSEN;
2112 /* Perform hash on these packet types */
2113 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2114 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2115 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2116 | IXGBE_MRQC_RSS_FIELD_IPV6
2117 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2118 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2120 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2122 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2124 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2125 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2126 /* Disable indicating checksum in descriptor, enables
2128 rxcsum |= IXGBE_RXCSUM_PCSD;
2130 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2131 /* Enable IPv4 payload checksum for UDP fragments
2132 * if PCSD is not set */
2133 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2136 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2138 if (hw->mac.type == ixgbe_mac_82599EB) {
2139 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2140 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2141 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2142 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2145 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2146 /* Enable 82599 HW-RSC */
2147 for (i = 0; i < adapter->num_rx_queues; i++) {
2148 rx_ring = &adapter->rx_ring[i];
2149 j = rx_ring->reg_idx;
2150 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2151 rscctrl |= IXGBE_RSCCTL_RSCEN;
2153 * we must limit the number of descriptors so that the
2154 * total size of max desc * buf_len is not greater
2157 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2158 #if (MAX_SKB_FRAGS > 16)
2159 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2160 #elif (MAX_SKB_FRAGS > 8)
2161 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2162 #elif (MAX_SKB_FRAGS > 4)
2163 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2165 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2168 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2169 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2170 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2171 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2173 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2175 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2177 /* Disable RSC for ACK packets */
2178 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2179 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2183 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2186 struct ixgbe_hw *hw = &adapter->hw;
2188 /* add VID to filter table */
2189 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2192 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2195 struct ixgbe_hw *hw = &adapter->hw;
2197 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2198 ixgbe_irq_disable(adapter);
2200 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2202 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2203 ixgbe_irq_enable(adapter);
2205 /* remove VID from filter table */
2206 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2209 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2210 struct vlan_group *grp)
2212 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2216 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2217 ixgbe_irq_disable(adapter);
2218 adapter->vlgrp = grp;
2221 * For a DCB driver, always enable VLAN tag stripping so we can
2222 * still receive traffic from a DCB-enabled host even if we're
2225 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2226 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2227 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2228 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2230 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2231 ctrl |= IXGBE_VLNCTRL_VFE;
2232 /* enable VLAN tag insert/strip */
2233 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2234 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2236 for (i = 0; i < adapter->num_rx_queues; i++) {
2237 j = adapter->rx_ring[i].reg_idx;
2238 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2239 ctrl |= IXGBE_RXDCTL_VME;
2240 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2243 ixgbe_vlan_rx_add_vid(netdev, 0);
2245 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2246 ixgbe_irq_enable(adapter);
2249 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2251 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2253 if (adapter->vlgrp) {
2255 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2256 if (!vlan_group_get_device(adapter->vlgrp, vid))
2258 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2263 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2265 struct dev_mc_list *mc_ptr;
2266 u8 *addr = *mc_addr_ptr;
2269 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2271 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2273 *mc_addr_ptr = NULL;
2279 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2280 * @netdev: network interface device structure
2282 * The set_rx_method entry point is called whenever the unicast/multicast
2283 * address list or the network interface flags are updated. This routine is
2284 * responsible for configuring the hardware for proper unicast, multicast and
2287 static void ixgbe_set_rx_mode(struct net_device *netdev)
2289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2290 struct ixgbe_hw *hw = &adapter->hw;
2292 u8 *addr_list = NULL;
2295 /* Check for Promiscuous and All Multicast modes */
2297 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2298 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2300 if (netdev->flags & IFF_PROMISC) {
2301 hw->addr_ctrl.user_set_promisc = 1;
2302 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2303 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2305 if (netdev->flags & IFF_ALLMULTI) {
2306 fctrl |= IXGBE_FCTRL_MPE;
2307 fctrl &= ~IXGBE_FCTRL_UPE;
2309 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2311 vlnctrl |= IXGBE_VLNCTRL_VFE;
2312 hw->addr_ctrl.user_set_promisc = 0;
2315 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2316 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2318 /* reprogram secondary unicast list */
2319 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2321 /* reprogram multicast list */
2322 addr_count = netdev->mc_count;
2324 addr_list = netdev->mc_list->dmi_addr;
2325 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2326 ixgbe_addr_list_itr);
2329 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2332 struct ixgbe_q_vector *q_vector;
2333 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2335 /* legacy and MSI only use one vector */
2336 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2339 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2340 struct napi_struct *napi;
2341 q_vector = adapter->q_vector[q_idx];
2342 napi = &q_vector->napi;
2343 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2344 if (!q_vector->rxr_count || !q_vector->txr_count) {
2345 if (q_vector->txr_count == 1)
2346 napi->poll = &ixgbe_clean_txonly;
2347 else if (q_vector->rxr_count == 1)
2348 napi->poll = &ixgbe_clean_rxonly;
2356 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2359 struct ixgbe_q_vector *q_vector;
2360 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2362 /* legacy and MSI only use one vector */
2363 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2366 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2367 q_vector = adapter->q_vector[q_idx];
2368 napi_disable(&q_vector->napi);
2372 #ifdef CONFIG_IXGBE_DCB
2374 * ixgbe_configure_dcb - Configure DCB hardware
2375 * @adapter: ixgbe adapter struct
2377 * This is called by the driver on open to configure the DCB hardware.
2378 * This is also called by the gennetlink interface when reconfiguring
2381 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2383 struct ixgbe_hw *hw = &adapter->hw;
2384 u32 txdctl, vlnctrl;
2387 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2388 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2389 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2391 /* reconfigure the hardware */
2392 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2394 for (i = 0; i < adapter->num_tx_queues; i++) {
2395 j = adapter->tx_ring[i].reg_idx;
2396 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2397 /* PThresh workaround for Tx hang with DFP enabled. */
2399 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2401 /* Enable VLAN tag insert/strip */
2402 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2403 if (hw->mac.type == ixgbe_mac_82598EB) {
2404 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2405 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2406 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2407 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2408 vlnctrl |= IXGBE_VLNCTRL_VFE;
2409 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2410 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2411 for (i = 0; i < adapter->num_rx_queues; i++) {
2412 j = adapter->rx_ring[i].reg_idx;
2413 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2414 vlnctrl |= IXGBE_RXDCTL_VME;
2415 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2418 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2422 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2424 struct net_device *netdev = adapter->netdev;
2425 struct ixgbe_hw *hw = &adapter->hw;
2428 ixgbe_set_rx_mode(netdev);
2430 ixgbe_restore_vlan(adapter);
2431 #ifdef CONFIG_IXGBE_DCB
2432 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2433 netif_set_gso_max_size(netdev, 32768);
2434 ixgbe_configure_dcb(adapter);
2436 netif_set_gso_max_size(netdev, 65536);
2439 netif_set_gso_max_size(netdev, 65536);
2443 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2444 ixgbe_configure_fcoe(adapter);
2446 #endif /* IXGBE_FCOE */
2447 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2448 for (i = 0; i < adapter->num_tx_queues; i++)
2449 adapter->tx_ring[i].atr_sample_rate =
2450 adapter->atr_sample_rate;
2451 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2452 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2453 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2456 ixgbe_configure_tx(adapter);
2457 ixgbe_configure_rx(adapter);
2458 for (i = 0; i < adapter->num_rx_queues; i++)
2459 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2460 (adapter->rx_ring[i].count - 1));
2463 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2465 switch (hw->phy.type) {
2466 case ixgbe_phy_sfp_avago:
2467 case ixgbe_phy_sfp_ftl:
2468 case ixgbe_phy_sfp_intel:
2469 case ixgbe_phy_sfp_unknown:
2470 case ixgbe_phy_tw_tyco:
2471 case ixgbe_phy_tw_unknown:
2479 * ixgbe_sfp_link_config - set up SFP+ link
2480 * @adapter: pointer to private adapter struct
2482 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2484 struct ixgbe_hw *hw = &adapter->hw;
2486 if (hw->phy.multispeed_fiber) {
2488 * In multispeed fiber setups, the device may not have
2489 * had a physical connection when the driver loaded.
2490 * If that's the case, the initial link configuration
2491 * couldn't get the MAC into 10G or 1G mode, so we'll
2492 * never have a link status change interrupt fire.
2493 * We need to try and force an autonegotiation
2494 * session, then bring up link.
2496 hw->mac.ops.setup_sfp(hw);
2497 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2498 schedule_work(&adapter->multispeed_fiber_task);
2501 * Direct Attach Cu and non-multispeed fiber modules
2502 * still need to be configured properly prior to
2505 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2506 schedule_work(&adapter->sfp_config_module_task);
2511 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2512 * @hw: pointer to private hardware struct
2514 * Returns 0 on success, negative on failure
2516 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2519 bool negotiation, link_up = false;
2520 u32 ret = IXGBE_ERR_LINK_SETUP;
2522 if (hw->mac.ops.check_link)
2523 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2528 if (hw->mac.ops.get_link_capabilities)
2529 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2533 if (hw->mac.ops.setup_link)
2534 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2539 #define IXGBE_MAX_RX_DESC_POLL 10
2540 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2543 int j = adapter->rx_ring[rxr].reg_idx;
2546 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2547 if (IXGBE_READ_REG(&adapter->hw,
2548 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2553 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2554 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2555 "not set within the polling period\n", rxr);
2557 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2558 (adapter->rx_ring[rxr].count - 1));
2561 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2563 struct net_device *netdev = adapter->netdev;
2564 struct ixgbe_hw *hw = &adapter->hw;
2566 int num_rx_rings = adapter->num_rx_queues;
2568 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2569 u32 txdctl, rxdctl, mhadd;
2573 ixgbe_get_hw_control(adapter);
2575 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2576 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2578 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2579 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2584 /* XXX: to interrupt immediately for EICS writes, enable this */
2585 /* gpie |= IXGBE_GPIE_EIMEN; */
2586 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2589 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2590 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2591 * specifically only auto mask tx and rx interrupts */
2592 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2595 /* Enable fan failure interrupt if media type is copper */
2596 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2597 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2598 gpie |= IXGBE_SDP1_GPIEN;
2599 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2602 if (hw->mac.type == ixgbe_mac_82599EB) {
2603 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2604 gpie |= IXGBE_SDP1_GPIEN;
2605 gpie |= IXGBE_SDP2_GPIEN;
2606 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2610 /* adjust max frame to be able to do baby jumbo for FCoE */
2611 if ((netdev->features & NETIF_F_FCOE_MTU) &&
2612 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2613 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2615 #endif /* IXGBE_FCOE */
2616 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2617 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2618 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2619 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2621 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2624 for (i = 0; i < adapter->num_tx_queues; i++) {
2625 j = adapter->tx_ring[i].reg_idx;
2626 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2627 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2628 txdctl |= (8 << 16);
2629 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2632 if (hw->mac.type == ixgbe_mac_82599EB) {
2633 /* DMATXCTL.EN must be set after all Tx queue config is done */
2634 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2635 dmatxctl |= IXGBE_DMATXCTL_TE;
2636 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2638 for (i = 0; i < adapter->num_tx_queues; i++) {
2639 j = adapter->tx_ring[i].reg_idx;
2640 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2641 txdctl |= IXGBE_TXDCTL_ENABLE;
2642 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2645 for (i = 0; i < num_rx_rings; i++) {
2646 j = adapter->rx_ring[i].reg_idx;
2647 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2648 /* enable PTHRESH=32 descriptors (half the internal cache)
2649 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2650 * this also removes a pesky rx_no_buffer_count increment */
2652 rxdctl |= IXGBE_RXDCTL_ENABLE;
2653 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2654 if (hw->mac.type == ixgbe_mac_82599EB)
2655 ixgbe_rx_desc_queue_enable(adapter, i);
2657 /* enable all receives */
2658 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2659 if (hw->mac.type == ixgbe_mac_82598EB)
2660 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2662 rxdctl |= IXGBE_RXCTRL_RXEN;
2663 hw->mac.ops.enable_rx_dma(hw, rxdctl);
2665 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2666 ixgbe_configure_msix(adapter);
2668 ixgbe_configure_msi_and_legacy(adapter);
2670 clear_bit(__IXGBE_DOWN, &adapter->state);
2671 ixgbe_napi_enable_all(adapter);
2673 /* clear any pending interrupts, may auto mask */
2674 IXGBE_READ_REG(hw, IXGBE_EICR);
2676 ixgbe_irq_enable(adapter);
2679 * If this adapter has a fan, check to see if we had a failure
2680 * before we enabled the interrupt.
2682 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2683 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2684 if (esdp & IXGBE_ESDP_SDP1)
2686 "Fan has stopped, replace the adapter\n");
2690 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2691 * arrived before interrupts were enabled but after probe. Such
2692 * devices wouldn't have their type identified yet. We need to
2693 * kick off the SFP+ module setup first, then try to bring up link.
2694 * If we're not hot-pluggable SFP+, we just need to configure link
2697 if (hw->phy.type == ixgbe_phy_unknown) {
2698 err = hw->phy.ops.identify(hw);
2699 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2701 * Take the device down and schedule the sfp tasklet
2702 * which will unregister_netdev and log it.
2704 ixgbe_down(adapter);
2705 schedule_work(&adapter->sfp_config_module_task);
2710 if (ixgbe_is_sfp(hw)) {
2711 ixgbe_sfp_link_config(adapter);
2713 err = ixgbe_non_sfp_link_config(hw);
2715 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2718 for (i = 0; i < adapter->num_tx_queues; i++)
2719 set_bit(__IXGBE_FDIR_INIT_DONE,
2720 &(adapter->tx_ring[i].reinit_state));
2722 /* enable transmits */
2723 netif_tx_start_all_queues(netdev);
2725 /* bring the link up in the watchdog, this could race with our first
2726 * link up interrupt but shouldn't be a problem */
2727 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2728 adapter->link_check_timeout = jiffies;
2729 mod_timer(&adapter->watchdog_timer, jiffies);
2733 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2735 WARN_ON(in_interrupt());
2736 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2738 ixgbe_down(adapter);
2740 clear_bit(__IXGBE_RESETTING, &adapter->state);
2743 int ixgbe_up(struct ixgbe_adapter *adapter)
2745 /* hardware has been reset, we need to reload some things */
2746 ixgbe_configure(adapter);
2748 return ixgbe_up_complete(adapter);
2751 void ixgbe_reset(struct ixgbe_adapter *adapter)
2753 struct ixgbe_hw *hw = &adapter->hw;
2756 err = hw->mac.ops.init_hw(hw);
2759 case IXGBE_ERR_SFP_NOT_PRESENT:
2761 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2762 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2764 case IXGBE_ERR_EEPROM_VERSION:
2765 /* We are running on a pre-production device, log a warning */
2766 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2767 "adapter/LOM. Please be aware there may be issues "
2768 "associated with your hardware. If you are "
2769 "experiencing problems please contact your Intel or "
2770 "hardware representative who provided you with this "
2774 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2777 /* reprogram the RAR[0] in case user changed it. */
2778 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2782 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2783 * @adapter: board private structure
2784 * @rx_ring: ring to free buffers from
2786 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2787 struct ixgbe_ring *rx_ring)
2789 struct pci_dev *pdev = adapter->pdev;
2793 /* Free all the Rx ring sk_buffs */
2795 for (i = 0; i < rx_ring->count; i++) {
2796 struct ixgbe_rx_buffer *rx_buffer_info;
2798 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2799 if (rx_buffer_info->dma) {
2800 pci_unmap_single(pdev, rx_buffer_info->dma,
2801 rx_ring->rx_buf_len,
2802 PCI_DMA_FROMDEVICE);
2803 rx_buffer_info->dma = 0;
2805 if (rx_buffer_info->skb) {
2806 struct sk_buff *skb = rx_buffer_info->skb;
2807 rx_buffer_info->skb = NULL;
2809 struct sk_buff *this = skb;
2811 dev_kfree_skb(this);
2814 if (!rx_buffer_info->page)
2816 if (rx_buffer_info->page_dma) {
2817 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2818 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2819 rx_buffer_info->page_dma = 0;
2821 put_page(rx_buffer_info->page);
2822 rx_buffer_info->page = NULL;
2823 rx_buffer_info->page_offset = 0;
2826 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2827 memset(rx_ring->rx_buffer_info, 0, size);
2829 /* Zero out the descriptor ring */
2830 memset(rx_ring->desc, 0, rx_ring->size);
2832 rx_ring->next_to_clean = 0;
2833 rx_ring->next_to_use = 0;
2836 writel(0, adapter->hw.hw_addr + rx_ring->head);
2838 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2842 * ixgbe_clean_tx_ring - Free Tx Buffers
2843 * @adapter: board private structure
2844 * @tx_ring: ring to be cleaned
2846 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2847 struct ixgbe_ring *tx_ring)
2849 struct ixgbe_tx_buffer *tx_buffer_info;
2853 /* Free all the Tx ring sk_buffs */
2855 for (i = 0; i < tx_ring->count; i++) {
2856 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2857 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2860 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2861 memset(tx_ring->tx_buffer_info, 0, size);
2863 /* Zero out the descriptor ring */
2864 memset(tx_ring->desc, 0, tx_ring->size);
2866 tx_ring->next_to_use = 0;
2867 tx_ring->next_to_clean = 0;
2870 writel(0, adapter->hw.hw_addr + tx_ring->head);
2872 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2876 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2877 * @adapter: board private structure
2879 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2883 for (i = 0; i < adapter->num_rx_queues; i++)
2884 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2888 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2889 * @adapter: board private structure
2891 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2895 for (i = 0; i < adapter->num_tx_queues; i++)
2896 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2899 void ixgbe_down(struct ixgbe_adapter *adapter)
2901 struct net_device *netdev = adapter->netdev;
2902 struct ixgbe_hw *hw = &adapter->hw;
2907 /* signal that we are down to the interrupt handler */
2908 set_bit(__IXGBE_DOWN, &adapter->state);
2910 /* disable receives */
2911 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2912 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2914 netif_tx_disable(netdev);
2916 IXGBE_WRITE_FLUSH(hw);
2919 netif_tx_stop_all_queues(netdev);
2921 ixgbe_irq_disable(adapter);
2923 ixgbe_napi_disable_all(adapter);
2925 del_timer_sync(&adapter->watchdog_timer);
2926 cancel_work_sync(&adapter->watchdog_task);
2928 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2929 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2930 cancel_work_sync(&adapter->fdir_reinit_task);
2932 /* disable transmits in the hardware now that interrupts are off */
2933 for (i = 0; i < adapter->num_tx_queues; i++) {
2934 j = adapter->tx_ring[i].reg_idx;
2935 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2936 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2937 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2939 /* Disable the Tx DMA engine on 82599 */
2940 if (hw->mac.type == ixgbe_mac_82599EB)
2941 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2942 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2943 ~IXGBE_DMATXCTL_TE));
2945 netif_carrier_off(netdev);
2947 if (!pci_channel_offline(adapter->pdev))
2948 ixgbe_reset(adapter);
2949 ixgbe_clean_all_tx_rings(adapter);
2950 ixgbe_clean_all_rx_rings(adapter);
2952 #ifdef CONFIG_IXGBE_DCA
2953 /* since we reset the hardware DCA settings were cleared */
2954 ixgbe_setup_dca(adapter);
2959 * ixgbe_poll - NAPI Rx polling callback
2960 * @napi: structure for representing this polling device
2961 * @budget: how many packets driver is allowed to clean
2963 * This function is used for legacy and MSI, NAPI mode
2965 static int ixgbe_poll(struct napi_struct *napi, int budget)
2967 struct ixgbe_q_vector *q_vector =
2968 container_of(napi, struct ixgbe_q_vector, napi);
2969 struct ixgbe_adapter *adapter = q_vector->adapter;
2970 int tx_clean_complete, work_done = 0;
2972 #ifdef CONFIG_IXGBE_DCA
2973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2974 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2975 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2979 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2980 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2982 if (!tx_clean_complete)
2985 /* If budget not fully consumed, exit the polling mode */
2986 if (work_done < budget) {
2987 napi_complete(napi);
2988 if (adapter->itr_setting & 1)
2989 ixgbe_set_itr(adapter);
2990 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2991 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2997 * ixgbe_tx_timeout - Respond to a Tx Hang
2998 * @netdev: network interface device structure
3000 static void ixgbe_tx_timeout(struct net_device *netdev)
3002 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3004 /* Do the reset outside of interrupt context */
3005 schedule_work(&adapter->reset_task);
3008 static void ixgbe_reset_task(struct work_struct *work)
3010 struct ixgbe_adapter *adapter;
3011 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3013 /* If we're already down or resetting, just bail */
3014 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3015 test_bit(__IXGBE_RESETTING, &adapter->state))
3018 adapter->tx_timeout_count++;
3020 ixgbe_reinit_locked(adapter);
3023 #ifdef CONFIG_IXGBE_DCB
3024 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3027 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3029 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3033 adapter->num_rx_queues = f->indices;
3034 adapter->num_tx_queues = f->indices;
3042 * ixgbe_set_rss_queues: Allocate queues for RSS
3043 * @adapter: board private structure to initialize
3045 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3046 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3049 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3052 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3054 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3056 adapter->num_rx_queues = f->indices;
3057 adapter->num_tx_queues = f->indices;
3067 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3068 * @adapter: board private structure to initialize
3070 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3071 * to the original CPU that initiated the Tx session. This runs in addition
3072 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3073 * Rx load across CPUs using RSS.
3076 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3079 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3081 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3084 /* Flow Director must have RSS enabled */
3085 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3086 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3087 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3088 adapter->num_tx_queues = f_fdir->indices;
3089 adapter->num_rx_queues = f_fdir->indices;
3092 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3093 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3100 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3101 * @adapter: board private structure to initialize
3103 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3104 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3105 * rx queues out of the max number of rx queues, instead, it is used as the
3106 * index of the first rx queue used by FCoE.
3109 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3112 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3114 f->indices = min((int)num_online_cpus(), f->indices);
3115 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3116 #ifdef CONFIG_IXGBE_DCB
3117 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3118 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3119 ixgbe_set_dcb_queues(adapter);
3122 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3123 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3124 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3125 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3126 ixgbe_set_fdir_queues(adapter);
3128 ixgbe_set_rss_queues(adapter);
3130 /* adding FCoE rx rings to the end */
3131 f->mask = adapter->num_rx_queues;
3132 adapter->num_rx_queues += f->indices;
3133 if (adapter->num_tx_queues == 0)
3134 adapter->num_tx_queues = f->indices;
3142 #endif /* IXGBE_FCOE */
3144 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3145 * @adapter: board private structure to initialize
3147 * This is the top level queue allocation routine. The order here is very
3148 * important, starting with the "most" number of features turned on at once,
3149 * and ending with the smallest set of features. This way large combinations
3150 * can be allocated if they're turned on, and smaller combinations are the
3151 * fallthrough conditions.
3154 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3157 if (ixgbe_set_fcoe_queues(adapter))
3160 #endif /* IXGBE_FCOE */
3161 #ifdef CONFIG_IXGBE_DCB
3162 if (ixgbe_set_dcb_queues(adapter))
3166 if (ixgbe_set_fdir_queues(adapter))
3169 if (ixgbe_set_rss_queues(adapter))
3172 /* fallback to base case */
3173 adapter->num_rx_queues = 1;
3174 adapter->num_tx_queues = 1;
3177 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3178 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3181 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3184 int err, vector_threshold;
3186 /* We'll want at least 3 (vector_threshold):
3189 * 3) Other (Link Status Change, etc.)
3190 * 4) TCP Timer (optional)
3192 vector_threshold = MIN_MSIX_COUNT;
3194 /* The more we get, the more we will assign to Tx/Rx Cleanup
3195 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3196 * Right now, we simply care about how many we'll get; we'll
3197 * set them up later while requesting irq's.
3199 while (vectors >= vector_threshold) {
3200 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3202 if (!err) /* Success in acquiring all requested vectors. */
3205 vectors = 0; /* Nasty failure, quit now */
3206 else /* err == number of vectors we should try again with */
3210 if (vectors < vector_threshold) {
3211 /* Can't allocate enough MSI-X interrupts? Oh well.
3212 * This just means we'll go with either a single MSI
3213 * vector or fall back to legacy interrupts.
3215 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3216 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3217 kfree(adapter->msix_entries);
3218 adapter->msix_entries = NULL;
3220 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3222 * Adjust for only the vectors we'll use, which is minimum
3223 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3224 * vectors we were allocated.
3226 adapter->num_msix_vectors = min(vectors,
3227 adapter->max_msix_q_vectors + NON_Q_VECTORS);
3232 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3233 * @adapter: board private structure to initialize
3235 * Cache the descriptor ring offsets for RSS to the assigned rings.
3238 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3243 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3244 for (i = 0; i < adapter->num_rx_queues; i++)
3245 adapter->rx_ring[i].reg_idx = i;
3246 for (i = 0; i < adapter->num_tx_queues; i++)
3247 adapter->tx_ring[i].reg_idx = i;
3256 #ifdef CONFIG_IXGBE_DCB
3258 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3259 * @adapter: board private structure to initialize
3261 * Cache the descriptor ring offsets for DCB to the assigned rings.
3264 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3268 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3270 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3271 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3272 /* the number of queues is assumed to be symmetric */
3273 for (i = 0; i < dcb_i; i++) {
3274 adapter->rx_ring[i].reg_idx = i << 3;
3275 adapter->tx_ring[i].reg_idx = i << 2;
3278 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3281 * Tx TC0 starts at: descriptor queue 0
3282 * Tx TC1 starts at: descriptor queue 32
3283 * Tx TC2 starts at: descriptor queue 64
3284 * Tx TC3 starts at: descriptor queue 80
3285 * Tx TC4 starts at: descriptor queue 96
3286 * Tx TC5 starts at: descriptor queue 104
3287 * Tx TC6 starts at: descriptor queue 112
3288 * Tx TC7 starts at: descriptor queue 120
3290 * Rx TC0-TC7 are offset by 16 queues each
3292 for (i = 0; i < 3; i++) {
3293 adapter->tx_ring[i].reg_idx = i << 5;
3294 adapter->rx_ring[i].reg_idx = i << 4;
3296 for ( ; i < 5; i++) {
3297 adapter->tx_ring[i].reg_idx =
3299 adapter->rx_ring[i].reg_idx = i << 4;
3301 for ( ; i < dcb_i; i++) {
3302 adapter->tx_ring[i].reg_idx =
3304 adapter->rx_ring[i].reg_idx = i << 4;
3308 } else if (dcb_i == 4) {
3310 * Tx TC0 starts at: descriptor queue 0
3311 * Tx TC1 starts at: descriptor queue 64
3312 * Tx TC2 starts at: descriptor queue 96
3313 * Tx TC3 starts at: descriptor queue 112
3315 * Rx TC0-TC3 are offset by 32 queues each
3317 adapter->tx_ring[0].reg_idx = 0;
3318 adapter->tx_ring[1].reg_idx = 64;
3319 adapter->tx_ring[2].reg_idx = 96;
3320 adapter->tx_ring[3].reg_idx = 112;
3321 for (i = 0 ; i < dcb_i; i++)
3322 adapter->rx_ring[i].reg_idx = i << 5;
3340 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3341 * @adapter: board private structure to initialize
3343 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3346 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3351 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3352 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3353 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3354 for (i = 0; i < adapter->num_rx_queues; i++)
3355 adapter->rx_ring[i].reg_idx = i;
3356 for (i = 0; i < adapter->num_tx_queues; i++)
3357 adapter->tx_ring[i].reg_idx = i;
3366 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3367 * @adapter: board private structure to initialize
3369 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3372 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3376 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3378 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3379 #ifdef CONFIG_IXGBE_DCB
3380 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3381 ixgbe_cache_ring_dcb(adapter);
3382 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3384 #endif /* CONFIG_IXGBE_DCB */
3385 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3386 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3387 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3388 ixgbe_cache_ring_fdir(adapter);
3390 ixgbe_cache_ring_rss(adapter);
3394 for (i = 0; i < f->indices; i++, fcoe_i++)
3395 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3401 #endif /* IXGBE_FCOE */
3403 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3404 * @adapter: board private structure to initialize
3406 * Once we know the feature-set enabled for the device, we'll cache
3407 * the register offset the descriptor ring is assigned to.
3409 * Note, the order the various feature calls is important. It must start with
3410 * the "most" features enabled at the same time, then trickle down to the
3411 * least amount of features turned on at once.
3413 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3415 /* start with default case */
3416 adapter->rx_ring[0].reg_idx = 0;
3417 adapter->tx_ring[0].reg_idx = 0;
3420 if (ixgbe_cache_ring_fcoe(adapter))
3423 #endif /* IXGBE_FCOE */
3424 #ifdef CONFIG_IXGBE_DCB
3425 if (ixgbe_cache_ring_dcb(adapter))
3429 if (ixgbe_cache_ring_fdir(adapter))
3432 if (ixgbe_cache_ring_rss(adapter))
3437 * ixgbe_alloc_queues - Allocate memory for all rings
3438 * @adapter: board private structure to initialize
3440 * We allocate one ring per queue at run-time since we don't know the
3441 * number of queues at compile-time. The polling_netdev array is
3442 * intended for Multiqueue, but should work fine with a single queue.
3444 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3448 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3449 sizeof(struct ixgbe_ring), GFP_KERNEL);
3450 if (!adapter->tx_ring)
3451 goto err_tx_ring_allocation;
3453 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3454 sizeof(struct ixgbe_ring), GFP_KERNEL);
3455 if (!adapter->rx_ring)
3456 goto err_rx_ring_allocation;
3458 for (i = 0; i < adapter->num_tx_queues; i++) {
3459 adapter->tx_ring[i].count = adapter->tx_ring_count;
3460 adapter->tx_ring[i].queue_index = i;
3463 for (i = 0; i < adapter->num_rx_queues; i++) {
3464 adapter->rx_ring[i].count = adapter->rx_ring_count;
3465 adapter->rx_ring[i].queue_index = i;
3468 ixgbe_cache_ring_register(adapter);
3472 err_rx_ring_allocation:
3473 kfree(adapter->tx_ring);
3474 err_tx_ring_allocation:
3479 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3480 * @adapter: board private structure to initialize
3482 * Attempt to configure the interrupts using the best available
3483 * capabilities of the hardware and the kernel.
3485 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3487 struct ixgbe_hw *hw = &adapter->hw;
3489 int vector, v_budget;
3492 * It's easy to be greedy for MSI-X vectors, but it really
3493 * doesn't do us much good if we have a lot more vectors
3494 * than CPU's. So let's be conservative and only ask for
3495 * (roughly) twice the number of vectors as there are CPU's.
3497 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3498 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3501 * At the same time, hardware can only support a maximum of
3502 * hw.mac->max_msix_vectors vectors. With features
3503 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3504 * descriptor queues supported by our device. Thus, we cap it off in
3505 * those rare cases where the cpu count also exceeds our vector limit.
3507 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3509 /* A failure in MSI-X entry allocation isn't fatal, but it does
3510 * mean we disable MSI-X capabilities of the adapter. */
3511 adapter->msix_entries = kcalloc(v_budget,
3512 sizeof(struct msix_entry), GFP_KERNEL);
3513 if (adapter->msix_entries) {
3514 for (vector = 0; vector < v_budget; vector++)
3515 adapter->msix_entries[vector].entry = vector;
3517 ixgbe_acquire_msix_vectors(adapter, v_budget);
3519 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3523 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3524 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3525 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3526 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3527 adapter->atr_sample_rate = 0;
3528 ixgbe_set_num_queues(adapter);
3530 err = pci_enable_msi(adapter->pdev);
3532 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3534 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3535 "falling back to legacy. Error: %d\n", err);
3545 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3546 * @adapter: board private structure to initialize
3548 * We allocate one q_vector per queue interrupt. If allocation fails we
3551 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3553 int q_idx, num_q_vectors;
3554 struct ixgbe_q_vector *q_vector;
3556 int (*poll)(struct napi_struct *, int);
3558 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3559 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3560 napi_vectors = adapter->num_rx_queues;
3561 poll = &ixgbe_clean_rxtx_many;
3568 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3569 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3572 q_vector->adapter = adapter;
3573 q_vector->eitr = adapter->eitr_param;
3574 q_vector->v_idx = q_idx;
3575 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3576 adapter->q_vector[q_idx] = q_vector;
3584 q_vector = adapter->q_vector[q_idx];
3585 netif_napi_del(&q_vector->napi);
3587 adapter->q_vector[q_idx] = NULL;
3593 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3594 * @adapter: board private structure to initialize
3596 * This function frees the memory allocated to the q_vectors. In addition if
3597 * NAPI is enabled it will delete any references to the NAPI struct prior
3598 * to freeing the q_vector.
3600 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3602 int q_idx, num_q_vectors;
3604 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3605 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3609 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3610 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3611 adapter->q_vector[q_idx] = NULL;
3612 netif_napi_del(&q_vector->napi);
3617 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3619 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3620 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3621 pci_disable_msix(adapter->pdev);
3622 kfree(adapter->msix_entries);
3623 adapter->msix_entries = NULL;
3624 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3625 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3626 pci_disable_msi(adapter->pdev);
3632 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3633 * @adapter: board private structure to initialize
3635 * We determine which interrupt scheme to use based on...
3636 * - Kernel support (MSI, MSI-X)
3637 * - which can be user-defined (via MODULE_PARAM)
3638 * - Hardware queue count (num_*_queues)
3639 * - defined by miscellaneous hardware support/features (RSS, etc.)
3641 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3645 /* Number of supported queues */
3646 ixgbe_set_num_queues(adapter);
3648 err = ixgbe_set_interrupt_capability(adapter);
3650 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3651 goto err_set_interrupt;
3654 err = ixgbe_alloc_q_vectors(adapter);
3656 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3658 goto err_alloc_q_vectors;
3661 err = ixgbe_alloc_queues(adapter);
3663 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3664 goto err_alloc_queues;
3667 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3668 "Tx Queue count = %u\n",
3669 (adapter->num_rx_queues > 1) ? "Enabled" :
3670 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3672 set_bit(__IXGBE_DOWN, &adapter->state);
3677 ixgbe_free_q_vectors(adapter);
3678 err_alloc_q_vectors:
3679 ixgbe_reset_interrupt_capability(adapter);
3685 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3686 * @adapter: board private structure to clear interrupt scheme on
3688 * We go through and clear interrupt specific resources and reset the structure
3689 * to pre-load conditions
3691 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3693 kfree(adapter->tx_ring);
3694 kfree(adapter->rx_ring);
3695 adapter->tx_ring = NULL;
3696 adapter->rx_ring = NULL;
3698 ixgbe_free_q_vectors(adapter);
3699 ixgbe_reset_interrupt_capability(adapter);
3703 * ixgbe_sfp_timer - worker thread to find a missing module
3704 * @data: pointer to our adapter struct
3706 static void ixgbe_sfp_timer(unsigned long data)
3708 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3711 * Do the sfp_timer outside of interrupt context due to the
3712 * delays that sfp+ detection requires
3714 schedule_work(&adapter->sfp_task);
3718 * ixgbe_sfp_task - worker thread to find a missing module
3719 * @work: pointer to work_struct containing our data
3721 static void ixgbe_sfp_task(struct work_struct *work)
3723 struct ixgbe_adapter *adapter = container_of(work,
3724 struct ixgbe_adapter,
3726 struct ixgbe_hw *hw = &adapter->hw;
3728 if ((hw->phy.type == ixgbe_phy_nl) &&
3729 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3730 s32 ret = hw->phy.ops.identify_sfp(hw);
3731 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3733 ret = hw->phy.ops.reset(hw);
3734 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3735 dev_err(&adapter->pdev->dev, "failed to initialize "
3736 "because an unsupported SFP+ module type "
3738 "Reload the driver after installing a "
3739 "supported module.\n");
3740 unregister_netdev(adapter->netdev);
3742 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3745 /* don't need this routine any more */
3746 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3750 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3751 mod_timer(&adapter->sfp_timer,
3752 round_jiffies(jiffies + (2 * HZ)));
3756 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3757 * @adapter: board private structure to initialize
3759 * ixgbe_sw_init initializes the Adapter private data structure.
3760 * Fields are initialized based on PCI device information and
3761 * OS network device settings (MTU size).
3763 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3765 struct ixgbe_hw *hw = &adapter->hw;
3766 struct pci_dev *pdev = adapter->pdev;
3768 #ifdef CONFIG_IXGBE_DCB
3770 struct tc_configuration *tc;
3773 /* PCI config space info */
3775 hw->vendor_id = pdev->vendor;
3776 hw->device_id = pdev->device;
3777 hw->revision_id = pdev->revision;
3778 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3779 hw->subsystem_device_id = pdev->subsystem_device;
3781 /* Set capability flags */
3782 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3783 adapter->ring_feature[RING_F_RSS].indices = rss;
3784 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3785 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3786 if (hw->mac.type == ixgbe_mac_82598EB) {
3787 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3788 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3789 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3790 } else if (hw->mac.type == ixgbe_mac_82599EB) {
3791 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3792 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3793 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3794 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3795 adapter->ring_feature[RING_F_FDIR].indices =
3796 IXGBE_MAX_FDIR_INDICES;
3797 adapter->atr_sample_rate = 20;
3798 adapter->fdir_pballoc = 0;
3800 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3801 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3802 adapter->ring_feature[RING_F_FCOE].indices = 0;
3803 /* Default traffic class to use for FCoE */
3804 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3805 #endif /* IXGBE_FCOE */
3808 #ifdef CONFIG_IXGBE_DCB
3809 /* Configure DCB traffic classes */
3810 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3811 tc = &adapter->dcb_cfg.tc_config[j];
3812 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3813 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3814 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3815 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3816 tc->dcb_pfc = pfc_disabled;
3818 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3819 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3820 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3821 adapter->dcb_cfg.pfc_mode_enable = false;
3822 adapter->dcb_cfg.round_robin_enable = false;
3823 adapter->dcb_set_bitmap = 0x00;
3824 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3825 adapter->ring_feature[RING_F_DCB].indices);
3829 /* default flow control settings */
3830 hw->fc.requested_mode = ixgbe_fc_full;
3831 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
3833 adapter->last_lfc_mode = hw->fc.current_mode;
3835 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3836 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3837 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3838 hw->fc.send_xon = true;
3839 hw->fc.disable_fc_autoneg = false;
3841 /* enable itr by default in dynamic mode */
3842 adapter->itr_setting = 1;
3843 adapter->eitr_param = 20000;
3845 /* set defaults for eitr in MegaBytes */
3846 adapter->eitr_low = 10;
3847 adapter->eitr_high = 20;
3849 /* set default ring sizes */
3850 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3851 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3853 /* initialize eeprom parameters */
3854 if (ixgbe_init_eeprom_params_generic(hw)) {
3855 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3859 /* enable rx csum by default */
3860 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3862 set_bit(__IXGBE_DOWN, &adapter->state);
3868 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3869 * @adapter: board private structure
3870 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3872 * Return 0 on success, negative on failure
3874 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3875 struct ixgbe_ring *tx_ring)
3877 struct pci_dev *pdev = adapter->pdev;
3880 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3881 tx_ring->tx_buffer_info = vmalloc(size);
3882 if (!tx_ring->tx_buffer_info)
3884 memset(tx_ring->tx_buffer_info, 0, size);
3886 /* round up to nearest 4K */
3887 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3888 tx_ring->size = ALIGN(tx_ring->size, 4096);
3890 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3895 tx_ring->next_to_use = 0;
3896 tx_ring->next_to_clean = 0;
3897 tx_ring->work_limit = tx_ring->count;
3901 vfree(tx_ring->tx_buffer_info);
3902 tx_ring->tx_buffer_info = NULL;
3903 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3904 "descriptor ring\n");
3909 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3910 * @adapter: board private structure
3912 * If this function returns with an error, then it's possible one or
3913 * more of the rings is populated (while the rest are not). It is the
3914 * callers duty to clean those orphaned rings.
3916 * Return 0 on success, negative on failure
3918 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3922 for (i = 0; i < adapter->num_tx_queues; i++) {
3923 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3926 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3934 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3935 * @adapter: board private structure
3936 * @rx_ring: rx descriptor ring (for a specific queue) to setup
3938 * Returns 0 on success, negative on failure
3940 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3941 struct ixgbe_ring *rx_ring)
3943 struct pci_dev *pdev = adapter->pdev;
3946 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3947 rx_ring->rx_buffer_info = vmalloc(size);
3948 if (!rx_ring->rx_buffer_info) {
3950 "vmalloc allocation failed for the rx desc ring\n");
3953 memset(rx_ring->rx_buffer_info, 0, size);
3955 /* Round up to nearest 4K */
3956 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3957 rx_ring->size = ALIGN(rx_ring->size, 4096);
3959 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3961 if (!rx_ring->desc) {
3963 "Memory allocation failed for the rx desc ring\n");
3964 vfree(rx_ring->rx_buffer_info);
3968 rx_ring->next_to_clean = 0;
3969 rx_ring->next_to_use = 0;
3978 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3979 * @adapter: board private structure
3981 * If this function returns with an error, then it's possible one or
3982 * more of the rings is populated (while the rest are not). It is the
3983 * callers duty to clean those orphaned rings.
3985 * Return 0 on success, negative on failure
3988 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3992 for (i = 0; i < adapter->num_rx_queues; i++) {
3993 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3996 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4004 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4005 * @adapter: board private structure
4006 * @tx_ring: Tx descriptor ring for a specific queue
4008 * Free all transmit software resources
4010 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4011 struct ixgbe_ring *tx_ring)
4013 struct pci_dev *pdev = adapter->pdev;
4015 ixgbe_clean_tx_ring(adapter, tx_ring);
4017 vfree(tx_ring->tx_buffer_info);
4018 tx_ring->tx_buffer_info = NULL;
4020 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4022 tx_ring->desc = NULL;
4026 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4027 * @adapter: board private structure
4029 * Free all transmit software resources
4031 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4035 for (i = 0; i < adapter->num_tx_queues; i++)
4036 if (adapter->tx_ring[i].desc)
4037 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4041 * ixgbe_free_rx_resources - Free Rx Resources
4042 * @adapter: board private structure
4043 * @rx_ring: ring to clean the resources from
4045 * Free all receive software resources
4047 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4048 struct ixgbe_ring *rx_ring)
4050 struct pci_dev *pdev = adapter->pdev;
4052 ixgbe_clean_rx_ring(adapter, rx_ring);
4054 vfree(rx_ring->rx_buffer_info);
4055 rx_ring->rx_buffer_info = NULL;
4057 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4059 rx_ring->desc = NULL;
4063 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4064 * @adapter: board private structure
4066 * Free all receive software resources
4068 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4072 for (i = 0; i < adapter->num_rx_queues; i++)
4073 if (adapter->rx_ring[i].desc)
4074 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4078 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4079 * @netdev: network interface device structure
4080 * @new_mtu: new value for maximum frame size
4082 * Returns 0 on success, negative on failure
4084 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4087 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4089 /* MTU < 68 is an error and causes problems on some kernels */
4090 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4093 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4094 netdev->mtu, new_mtu);
4095 /* must set new MTU before calling down or up */
4096 netdev->mtu = new_mtu;
4098 if (netif_running(netdev))
4099 ixgbe_reinit_locked(adapter);
4105 * ixgbe_open - Called when a network interface is made active
4106 * @netdev: network interface device structure
4108 * Returns 0 on success, negative value on failure
4110 * The open entry point is called when a network interface is made
4111 * active by the system (IFF_UP). At this point all resources needed
4112 * for transmit and receive operations are allocated, the interrupt
4113 * handler is registered with the OS, the watchdog timer is started,
4114 * and the stack is notified that the interface is ready.
4116 static int ixgbe_open(struct net_device *netdev)
4118 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4121 /* disallow open during test */
4122 if (test_bit(__IXGBE_TESTING, &adapter->state))
4125 netif_carrier_off(netdev);
4127 /* allocate transmit descriptors */
4128 err = ixgbe_setup_all_tx_resources(adapter);
4132 /* allocate receive descriptors */
4133 err = ixgbe_setup_all_rx_resources(adapter);
4137 ixgbe_configure(adapter);
4139 err = ixgbe_request_irq(adapter);
4143 err = ixgbe_up_complete(adapter);
4147 netif_tx_start_all_queues(netdev);
4152 ixgbe_release_hw_control(adapter);
4153 ixgbe_free_irq(adapter);
4156 ixgbe_free_all_rx_resources(adapter);
4158 ixgbe_free_all_tx_resources(adapter);
4159 ixgbe_reset(adapter);
4165 * ixgbe_close - Disables a network interface
4166 * @netdev: network interface device structure
4168 * Returns 0, this is not allowed to fail
4170 * The close entry point is called when an interface is de-activated
4171 * by the OS. The hardware is still under the drivers control, but
4172 * needs to be disabled. A global MAC reset is issued to stop the
4173 * hardware, and all transmit and receive resources are freed.
4175 static int ixgbe_close(struct net_device *netdev)
4177 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4179 ixgbe_down(adapter);
4180 ixgbe_free_irq(adapter);
4182 ixgbe_free_all_tx_resources(adapter);
4183 ixgbe_free_all_rx_resources(adapter);
4185 ixgbe_release_hw_control(adapter);
4191 static int ixgbe_resume(struct pci_dev *pdev)
4193 struct net_device *netdev = pci_get_drvdata(pdev);
4194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4197 pci_set_power_state(pdev, PCI_D0);
4198 pci_restore_state(pdev);
4200 err = pci_enable_device_mem(pdev);
4202 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4206 pci_set_master(pdev);
4208 pci_wake_from_d3(pdev, false);
4210 err = ixgbe_init_interrupt_scheme(adapter);
4212 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4217 ixgbe_reset(adapter);
4219 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4221 if (netif_running(netdev)) {
4222 err = ixgbe_open(adapter->netdev);
4227 netif_device_attach(netdev);
4231 #endif /* CONFIG_PM */
4233 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4235 struct net_device *netdev = pci_get_drvdata(pdev);
4236 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4237 struct ixgbe_hw *hw = &adapter->hw;
4239 u32 wufc = adapter->wol;
4244 netif_device_detach(netdev);
4246 if (netif_running(netdev)) {
4247 ixgbe_down(adapter);
4248 ixgbe_free_irq(adapter);
4249 ixgbe_free_all_tx_resources(adapter);
4250 ixgbe_free_all_rx_resources(adapter);
4252 ixgbe_clear_interrupt_scheme(adapter);
4255 retval = pci_save_state(pdev);
4261 ixgbe_set_rx_mode(netdev);
4263 /* turn on all-multi mode if wake on multicast is enabled */
4264 if (wufc & IXGBE_WUFC_MC) {
4265 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4266 fctrl |= IXGBE_FCTRL_MPE;
4267 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4270 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4271 ctrl |= IXGBE_CTRL_GIO_DIS;
4272 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4274 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4276 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4277 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4280 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4281 pci_wake_from_d3(pdev, true);
4283 pci_wake_from_d3(pdev, false);
4285 *enable_wake = !!wufc;
4287 ixgbe_release_hw_control(adapter);
4289 pci_disable_device(pdev);
4295 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4300 retval = __ixgbe_shutdown(pdev, &wake);
4305 pci_prepare_to_sleep(pdev);
4307 pci_wake_from_d3(pdev, false);
4308 pci_set_power_state(pdev, PCI_D3hot);
4313 #endif /* CONFIG_PM */
4315 static void ixgbe_shutdown(struct pci_dev *pdev)
4319 __ixgbe_shutdown(pdev, &wake);
4321 if (system_state == SYSTEM_POWER_OFF) {
4322 pci_wake_from_d3(pdev, wake);
4323 pci_set_power_state(pdev, PCI_D3hot);
4328 * ixgbe_update_stats - Update the board statistics counters.
4329 * @adapter: board private structure
4331 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4333 struct ixgbe_hw *hw = &adapter->hw;
4335 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4337 if (hw->mac.type == ixgbe_mac_82599EB) {
4339 for (i = 0; i < 16; i++)
4340 adapter->hw_rx_no_dma_resources +=
4341 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4342 for (i = 0; i < adapter->num_rx_queues; i++)
4343 rsc_count += adapter->rx_ring[i].rsc_count;
4344 adapter->rsc_count = rsc_count;
4347 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4348 for (i = 0; i < 8; i++) {
4349 /* for packet buffers not used, the register should read 0 */
4350 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4352 adapter->stats.mpc[i] += mpc;
4353 total_mpc += adapter->stats.mpc[i];
4354 if (hw->mac.type == ixgbe_mac_82598EB)
4355 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4356 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4357 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4358 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4359 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4360 if (hw->mac.type == ixgbe_mac_82599EB) {
4361 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4362 IXGBE_PXONRXCNT(i));
4363 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4364 IXGBE_PXOFFRXCNT(i));
4365 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4367 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4369 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4372 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4374 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4377 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4378 /* work around hardware counting issue */
4379 adapter->stats.gprc -= missed_rx;
4381 /* 82598 hardware only has a 32 bit counter in the high register */
4382 if (hw->mac.type == ixgbe_mac_82599EB) {
4383 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4384 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4385 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4386 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4387 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4388 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4389 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4390 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4391 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4392 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4394 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4395 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4396 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4397 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4398 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4399 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4400 #endif /* IXGBE_FCOE */
4402 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4403 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4404 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4405 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4406 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4408 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4409 adapter->stats.bprc += bprc;
4410 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4411 if (hw->mac.type == ixgbe_mac_82598EB)
4412 adapter->stats.mprc -= bprc;
4413 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4414 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4415 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4416 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4417 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4418 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4419 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4420 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4421 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4422 adapter->stats.lxontxc += lxon;
4423 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4424 adapter->stats.lxofftxc += lxoff;
4425 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4426 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4427 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4429 * 82598 errata - tx of flow control packets is included in tx counters
4431 xon_off_tot = lxon + lxoff;
4432 adapter->stats.gptc -= xon_off_tot;
4433 adapter->stats.mptc -= xon_off_tot;
4434 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4435 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4436 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4437 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4438 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4439 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4440 adapter->stats.ptc64 -= xon_off_tot;
4441 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4442 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4443 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4444 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4445 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4446 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4448 /* Fill out the OS statistics structure */
4449 adapter->net_stats.multicast = adapter->stats.mprc;
4452 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4453 adapter->stats.rlec;
4454 adapter->net_stats.rx_dropped = 0;
4455 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4456 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4457 adapter->net_stats.rx_missed_errors = total_mpc;
4461 * ixgbe_watchdog - Timer Call-back
4462 * @data: pointer to adapter cast into an unsigned long
4464 static void ixgbe_watchdog(unsigned long data)
4466 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4467 struct ixgbe_hw *hw = &adapter->hw;
4472 * Do the watchdog outside of interrupt context due to the lovely
4473 * delays that some of the newer hardware requires
4476 if (test_bit(__IXGBE_DOWN, &adapter->state))
4477 goto watchdog_short_circuit;
4479 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4481 * for legacy and MSI interrupts don't set any bits
4482 * that are enabled for EIAM, because this operation
4483 * would set *both* EIMS and EICS for any bit in EIAM
4485 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4486 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4487 goto watchdog_reschedule;
4490 /* get one bit for every active tx/rx interrupt vector */
4491 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4492 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4493 if (qv->rxr_count || qv->txr_count)
4494 eics |= ((u64)1 << i);
4497 /* Cause software interrupt to ensure rx rings are cleaned */
4498 ixgbe_irq_rearm_queues(adapter, eics);
4500 watchdog_reschedule:
4501 /* Reset the timer */
4502 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4504 watchdog_short_circuit:
4505 schedule_work(&adapter->watchdog_task);
4509 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4510 * @work: pointer to work_struct containing our data
4512 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4514 struct ixgbe_adapter *adapter = container_of(work,
4515 struct ixgbe_adapter,
4516 multispeed_fiber_task);
4517 struct ixgbe_hw *hw = &adapter->hw;
4521 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4522 autoneg = hw->phy.autoneg_advertised;
4523 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4524 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4525 if (hw->mac.ops.setup_link)
4526 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4527 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4528 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4532 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4533 * @work: pointer to work_struct containing our data
4535 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4537 struct ixgbe_adapter *adapter = container_of(work,
4538 struct ixgbe_adapter,
4539 sfp_config_module_task);
4540 struct ixgbe_hw *hw = &adapter->hw;
4543 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4545 /* Time for electrical oscillations to settle down */
4547 err = hw->phy.ops.identify_sfp(hw);
4549 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4550 dev_err(&adapter->pdev->dev, "failed to initialize because "
4551 "an unsupported SFP+ module type was detected.\n"
4552 "Reload the driver after installing a supported "
4554 unregister_netdev(adapter->netdev);
4557 hw->mac.ops.setup_sfp(hw);
4559 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4560 /* This will also work for DA Twinax connections */
4561 schedule_work(&adapter->multispeed_fiber_task);
4562 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4566 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4567 * @work: pointer to work_struct containing our data
4569 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4571 struct ixgbe_adapter *adapter = container_of(work,
4572 struct ixgbe_adapter,
4574 struct ixgbe_hw *hw = &adapter->hw;
4577 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4578 for (i = 0; i < adapter->num_tx_queues; i++)
4579 set_bit(__IXGBE_FDIR_INIT_DONE,
4580 &(adapter->tx_ring[i].reinit_state));
4582 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4583 "ignored adding FDIR ATR filters \n");
4585 /* Done FDIR Re-initialization, enable transmits */
4586 netif_tx_start_all_queues(adapter->netdev);
4590 * ixgbe_watchdog_task - worker thread to bring link up
4591 * @work: pointer to work_struct containing our data
4593 static void ixgbe_watchdog_task(struct work_struct *work)
4595 struct ixgbe_adapter *adapter = container_of(work,
4596 struct ixgbe_adapter,
4598 struct net_device *netdev = adapter->netdev;
4599 struct ixgbe_hw *hw = &adapter->hw;
4600 u32 link_speed = adapter->link_speed;
4601 bool link_up = adapter->link_up;
4603 struct ixgbe_ring *tx_ring;
4604 int some_tx_pending = 0;
4606 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4608 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4609 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4612 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4613 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4614 hw->mac.ops.fc_enable(hw, i);
4616 hw->mac.ops.fc_enable(hw, 0);
4619 hw->mac.ops.fc_enable(hw, 0);
4624 time_after(jiffies, (adapter->link_check_timeout +
4625 IXGBE_TRY_LINK_TIMEOUT))) {
4626 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4627 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4629 adapter->link_up = link_up;
4630 adapter->link_speed = link_speed;
4634 if (!netif_carrier_ok(netdev)) {
4635 bool flow_rx, flow_tx;
4637 if (hw->mac.type == ixgbe_mac_82599EB) {
4638 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4639 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4640 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4641 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4643 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4644 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4645 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4646 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4649 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4650 "Flow Control: %s\n",
4652 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4654 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4655 "1 Gbps" : "unknown speed")),
4656 ((flow_rx && flow_tx) ? "RX/TX" :
4658 (flow_tx ? "TX" : "None"))));
4660 netif_carrier_on(netdev);
4662 /* Force detection of hung controller */
4663 adapter->detect_tx_hung = true;
4666 adapter->link_up = false;
4667 adapter->link_speed = 0;
4668 if (netif_carrier_ok(netdev)) {
4669 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4671 netif_carrier_off(netdev);
4675 if (!netif_carrier_ok(netdev)) {
4676 for (i = 0; i < adapter->num_tx_queues; i++) {
4677 tx_ring = &adapter->tx_ring[i];
4678 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4679 some_tx_pending = 1;
4684 if (some_tx_pending) {
4685 /* We've lost link, so the controller stops DMA,
4686 * but we've got queued Tx work that's never going
4687 * to get done, so reset controller to flush Tx.
4688 * (Do the reset outside of interrupt context).
4690 schedule_work(&adapter->reset_task);
4694 ixgbe_update_stats(adapter);
4695 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4698 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4699 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4700 u32 tx_flags, u8 *hdr_len)
4702 struct ixgbe_adv_tx_context_desc *context_desc;
4705 struct ixgbe_tx_buffer *tx_buffer_info;
4706 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4707 u32 mss_l4len_idx, l4len;
4709 if (skb_is_gso(skb)) {
4710 if (skb_header_cloned(skb)) {
4711 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4715 l4len = tcp_hdrlen(skb);
4718 if (skb->protocol == htons(ETH_P_IP)) {
4719 struct iphdr *iph = ip_hdr(skb);
4722 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4726 adapter->hw_tso_ctxt++;
4727 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4728 ipv6_hdr(skb)->payload_len = 0;
4729 tcp_hdr(skb)->check =
4730 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4731 &ipv6_hdr(skb)->daddr,
4733 adapter->hw_tso6_ctxt++;
4736 i = tx_ring->next_to_use;
4738 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4739 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4741 /* VLAN MACLEN IPLEN */
4742 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4744 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4745 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4746 IXGBE_ADVTXD_MACLEN_SHIFT);
4747 *hdr_len += skb_network_offset(skb);
4749 (skb_transport_header(skb) - skb_network_header(skb));
4751 (skb_transport_header(skb) - skb_network_header(skb));
4752 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4753 context_desc->seqnum_seed = 0;
4755 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4756 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4757 IXGBE_ADVTXD_DTYP_CTXT);
4759 if (skb->protocol == htons(ETH_P_IP))
4760 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4761 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4762 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4766 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4767 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4768 /* use index 1 for TSO */
4769 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4770 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4772 tx_buffer_info->time_stamp = jiffies;
4773 tx_buffer_info->next_to_watch = i;
4776 if (i == tx_ring->count)
4778 tx_ring->next_to_use = i;
4785 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4786 struct ixgbe_ring *tx_ring,
4787 struct sk_buff *skb, u32 tx_flags)
4789 struct ixgbe_adv_tx_context_desc *context_desc;
4791 struct ixgbe_tx_buffer *tx_buffer_info;
4792 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4794 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4795 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4796 i = tx_ring->next_to_use;
4797 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4798 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4800 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4802 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4803 vlan_macip_lens |= (skb_network_offset(skb) <<
4804 IXGBE_ADVTXD_MACLEN_SHIFT);
4805 if (skb->ip_summed == CHECKSUM_PARTIAL)
4806 vlan_macip_lens |= (skb_transport_header(skb) -
4807 skb_network_header(skb));
4809 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4810 context_desc->seqnum_seed = 0;
4812 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4813 IXGBE_ADVTXD_DTYP_CTXT);
4815 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4816 switch (skb->protocol) {
4817 case cpu_to_be16(ETH_P_IP):
4818 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4819 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4821 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4822 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4824 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4826 case cpu_to_be16(ETH_P_IPV6):
4827 /* XXX what about other V6 headers?? */
4828 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4830 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4831 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4833 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4836 if (unlikely(net_ratelimit())) {
4837 DPRINTK(PROBE, WARNING,
4838 "partial checksum but proto=%x!\n",
4845 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4846 /* use index zero for tx checksum offload */
4847 context_desc->mss_l4len_idx = 0;
4849 tx_buffer_info->time_stamp = jiffies;
4850 tx_buffer_info->next_to_watch = i;
4852 adapter->hw_csum_tx_good++;
4854 if (i == tx_ring->count)
4856 tx_ring->next_to_use = i;
4864 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4865 struct ixgbe_ring *tx_ring,
4866 struct sk_buff *skb, u32 tx_flags,
4869 struct ixgbe_tx_buffer *tx_buffer_info;
4871 unsigned int total = skb->len;
4872 unsigned int offset = 0, size, count = 0, i;
4873 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4877 i = tx_ring->next_to_use;
4879 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4880 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4884 map = skb_shinfo(skb)->dma_maps;
4886 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4887 /* excluding fcoe_crc_eof for FCoE */
4888 total -= sizeof(struct fcoe_crc_eof);
4890 len = min(skb_headlen(skb), total);
4892 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4893 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4895 tx_buffer_info->length = size;
4896 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4897 tx_buffer_info->time_stamp = jiffies;
4898 tx_buffer_info->next_to_watch = i;
4907 if (i == tx_ring->count)
4912 for (f = 0; f < nr_frags; f++) {
4913 struct skb_frag_struct *frag;
4915 frag = &skb_shinfo(skb)->frags[f];
4916 len = min((unsigned int)frag->size, total);
4921 if (i == tx_ring->count)
4924 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4925 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4927 tx_buffer_info->length = size;
4928 tx_buffer_info->dma = map[f] + offset;
4929 tx_buffer_info->time_stamp = jiffies;
4930 tx_buffer_info->next_to_watch = i;
4941 tx_ring->tx_buffer_info[i].skb = skb;
4942 tx_ring->tx_buffer_info[first].next_to_watch = i;
4947 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4948 struct ixgbe_ring *tx_ring,
4949 int tx_flags, int count, u32 paylen, u8 hdr_len)
4951 union ixgbe_adv_tx_desc *tx_desc = NULL;
4952 struct ixgbe_tx_buffer *tx_buffer_info;
4953 u32 olinfo_status = 0, cmd_type_len = 0;
4955 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4957 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4959 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4961 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4962 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4964 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4965 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4967 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4968 IXGBE_ADVTXD_POPTS_SHIFT;
4970 /* use index 1 context for tso */
4971 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4972 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4973 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4974 IXGBE_ADVTXD_POPTS_SHIFT;
4976 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4977 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4978 IXGBE_ADVTXD_POPTS_SHIFT;
4980 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4981 olinfo_status |= IXGBE_ADVTXD_CC;
4982 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4983 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4984 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4987 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4989 i = tx_ring->next_to_use;
4991 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4992 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4993 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4994 tx_desc->read.cmd_type_len =
4995 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4996 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4998 if (i == tx_ring->count)
5002 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5005 * Force memory writes to complete before letting h/w
5006 * know there are new descriptors to fetch. (Only
5007 * applicable for weak-ordered memory model archs,
5012 tx_ring->next_to_use = i;
5013 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5016 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5017 int queue, u32 tx_flags)
5019 /* Right now, we support IPv4 only */
5020 struct ixgbe_atr_input atr_input;
5023 struct iphdr *iph = ip_hdr(skb);
5024 struct ethhdr *eth = (struct ethhdr *)skb->data;
5025 u16 vlan_id, src_port, dst_port, flex_bytes;
5026 u32 src_ipv4_addr, dst_ipv4_addr;
5029 /* check if we're UDP or TCP */
5030 if (iph->protocol == IPPROTO_TCP) {
5032 src_port = th->source;
5033 dst_port = th->dest;
5034 l4type |= IXGBE_ATR_L4TYPE_TCP;
5035 /* l4type IPv4 type is 0, no need to assign */
5036 } else if(iph->protocol == IPPROTO_UDP) {
5038 src_port = uh->source;
5039 dst_port = uh->dest;
5040 l4type |= IXGBE_ATR_L4TYPE_UDP;
5041 /* l4type IPv4 type is 0, no need to assign */
5043 /* Unsupported L4 header, just bail here */
5047 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5049 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5050 IXGBE_TX_FLAGS_VLAN_SHIFT;
5051 src_ipv4_addr = iph->saddr;
5052 dst_ipv4_addr = iph->daddr;
5053 flex_bytes = eth->h_proto;
5055 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5056 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5057 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5058 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5059 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5060 /* src and dst are inverted, think how the receiver sees them */
5061 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5062 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5064 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5065 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5068 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5069 struct ixgbe_ring *tx_ring, int size)
5071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5073 netif_stop_subqueue(netdev, tx_ring->queue_index);
5074 /* Herbert's original patch had:
5075 * smp_mb__after_netif_stop_queue();
5076 * but since that doesn't exist yet, just open code it. */
5079 /* We need to check again in a case another CPU has just
5080 * made room available. */
5081 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5084 /* A reprieve! - use start_queue because it doesn't call schedule */
5085 netif_start_subqueue(netdev, tx_ring->queue_index);
5086 ++adapter->restart_queue;
5090 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5091 struct ixgbe_ring *tx_ring, int size)
5093 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5095 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5098 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5100 struct ixgbe_adapter *adapter = netdev_priv(dev);
5102 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5103 return smp_processor_id();
5105 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5106 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5108 return skb_tx_hash(dev, skb);
5111 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5112 struct net_device *netdev)
5114 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5115 struct ixgbe_ring *tx_ring;
5117 unsigned int tx_flags = 0;
5123 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5124 tx_flags |= vlan_tx_tag_get(skb);
5125 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5126 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5127 tx_flags |= (skb->queue_mapping << 13);
5129 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5130 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5131 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5132 if (skb->priority != TC_PRIO_CONTROL) {
5133 tx_flags |= (skb->queue_mapping << 13);
5134 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5135 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5137 skb->queue_mapping =
5138 adapter->ring_feature[RING_F_DCB].indices-1;
5142 r_idx = skb->queue_mapping;
5143 tx_ring = &adapter->tx_ring[r_idx];
5145 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5146 (skb->protocol == htons(ETH_P_FCOE)))
5147 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5149 /* four things can cause us to need a context descriptor */
5150 if (skb_is_gso(skb) ||
5151 (skb->ip_summed == CHECKSUM_PARTIAL) ||
5152 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5153 (tx_flags & IXGBE_TX_FLAGS_FCOE))
5156 count += TXD_USE_COUNT(skb_headlen(skb));
5157 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5158 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5160 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5162 return NETDEV_TX_BUSY;
5165 first = tx_ring->next_to_use;
5166 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5168 /* setup tx offload for FCoE */
5169 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5171 dev_kfree_skb_any(skb);
5172 return NETDEV_TX_OK;
5175 tx_flags |= IXGBE_TX_FLAGS_FSO;
5176 #endif /* IXGBE_FCOE */
5178 if (skb->protocol == htons(ETH_P_IP))
5179 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5180 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5182 dev_kfree_skb_any(skb);
5183 return NETDEV_TX_OK;
5187 tx_flags |= IXGBE_TX_FLAGS_TSO;
5188 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5189 (skb->ip_summed == CHECKSUM_PARTIAL))
5190 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5193 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5195 /* add the ATR filter if ATR is on */
5196 if (tx_ring->atr_sample_rate) {
5197 ++tx_ring->atr_count;
5198 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5199 test_bit(__IXGBE_FDIR_INIT_DONE,
5200 &tx_ring->reinit_state)) {
5201 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5203 tx_ring->atr_count = 0;
5206 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5208 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5211 dev_kfree_skb_any(skb);
5212 tx_ring->tx_buffer_info[first].time_stamp = 0;
5213 tx_ring->next_to_use = first;
5216 return NETDEV_TX_OK;
5220 * ixgbe_get_stats - Get System Network Statistics
5221 * @netdev: network interface device structure
5223 * Returns the address of the device statistics structure.
5224 * The statistics are actually updated from the timer callback.
5226 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5228 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5230 /* only return the current stats */
5231 return &adapter->net_stats;
5235 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5236 * @netdev: network interface device structure
5237 * @p: pointer to an address structure
5239 * Returns 0 on success, negative on failure
5241 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5243 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5244 struct ixgbe_hw *hw = &adapter->hw;
5245 struct sockaddr *addr = p;
5247 if (!is_valid_ether_addr(addr->sa_data))
5248 return -EADDRNOTAVAIL;
5250 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5251 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5253 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5259 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5261 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5262 struct ixgbe_hw *hw = &adapter->hw;
5266 if (prtad != hw->phy.mdio.prtad)
5268 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5274 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5275 u16 addr, u16 value)
5277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5278 struct ixgbe_hw *hw = &adapter->hw;
5280 if (prtad != hw->phy.mdio.prtad)
5282 return hw->phy.ops.write_reg(hw, addr, devad, value);
5285 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5287 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5289 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5293 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5295 * @netdev: network interface device structure
5297 * Returns non-zero on failure
5299 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5302 struct ixgbe_adapter *adapter = netdev_priv(dev);
5303 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5305 if (is_valid_ether_addr(mac->san_addr)) {
5307 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5314 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5316 * @netdev: network interface device structure
5318 * Returns non-zero on failure
5320 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5323 struct ixgbe_adapter *adapter = netdev_priv(dev);
5324 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5326 if (is_valid_ether_addr(mac->san_addr)) {
5328 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5334 #ifdef CONFIG_NET_POLL_CONTROLLER
5336 * Polling 'interrupt' - used by things like netconsole to send skbs
5337 * without having to re-enable interrupts. It's not called while
5338 * the interrupt routine is executing.
5340 static void ixgbe_netpoll(struct net_device *netdev)
5342 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5345 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5346 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5347 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5348 for (i = 0; i < num_q_vectors; i++) {
5349 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5350 ixgbe_msix_clean_many(0, q_vector);
5353 ixgbe_intr(adapter->pdev->irq, netdev);
5355 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5359 static const struct net_device_ops ixgbe_netdev_ops = {
5360 .ndo_open = ixgbe_open,
5361 .ndo_stop = ixgbe_close,
5362 .ndo_start_xmit = ixgbe_xmit_frame,
5363 .ndo_select_queue = ixgbe_select_queue,
5364 .ndo_get_stats = ixgbe_get_stats,
5365 .ndo_set_rx_mode = ixgbe_set_rx_mode,
5366 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5367 .ndo_validate_addr = eth_validate_addr,
5368 .ndo_set_mac_address = ixgbe_set_mac,
5369 .ndo_change_mtu = ixgbe_change_mtu,
5370 .ndo_tx_timeout = ixgbe_tx_timeout,
5371 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5372 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5373 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
5374 .ndo_do_ioctl = ixgbe_ioctl,
5375 #ifdef CONFIG_NET_POLL_CONTROLLER
5376 .ndo_poll_controller = ixgbe_netpoll,
5379 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5380 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5381 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5382 .ndo_fcoe_disable = ixgbe_fcoe_disable,
5383 #endif /* IXGBE_FCOE */
5387 * ixgbe_probe - Device Initialization Routine
5388 * @pdev: PCI device information struct
5389 * @ent: entry in ixgbe_pci_tbl
5391 * Returns 0 on success, negative on failure
5393 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5394 * The OS initialization, configuring of the adapter private structure,
5395 * and a hardware reset occur.
5397 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5398 const struct pci_device_id *ent)
5400 struct net_device *netdev;
5401 struct ixgbe_adapter *adapter = NULL;
5402 struct ixgbe_hw *hw;
5403 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5404 static int cards_found;
5405 int i, err, pci_using_dac;
5411 err = pci_enable_device_mem(pdev);
5415 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5416 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5419 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5421 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5423 dev_err(&pdev->dev, "No usable DMA "
5424 "configuration, aborting\n");
5431 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5432 IORESOURCE_MEM), ixgbe_driver_name);
5435 "pci_request_selected_regions failed 0x%x\n", err);
5439 err = pci_enable_pcie_error_reporting(pdev);
5441 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5443 /* non-fatal, continue */
5446 pci_set_master(pdev);
5447 pci_save_state(pdev);
5449 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5452 goto err_alloc_etherdev;
5455 SET_NETDEV_DEV(netdev, &pdev->dev);
5457 pci_set_drvdata(pdev, netdev);
5458 adapter = netdev_priv(netdev);
5460 adapter->netdev = netdev;
5461 adapter->pdev = pdev;
5464 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5466 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5467 pci_resource_len(pdev, 0));
5473 for (i = 1; i <= 5; i++) {
5474 if (pci_resource_len(pdev, i) == 0)
5478 netdev->netdev_ops = &ixgbe_netdev_ops;
5479 ixgbe_set_ethtool_ops(netdev);
5480 netdev->watchdog_timeo = 5 * HZ;
5481 strcpy(netdev->name, pci_name(pdev));
5483 adapter->bd_number = cards_found;
5486 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5487 hw->mac.type = ii->mac;
5490 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5491 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5492 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5493 if (!(eec & (1 << 8)))
5494 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5497 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5498 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5499 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5500 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5501 hw->phy.mdio.mmds = 0;
5502 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5503 hw->phy.mdio.dev = netdev;
5504 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5505 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5507 /* set up this timer and work struct before calling get_invariants
5508 * which might start the timer
5510 init_timer(&adapter->sfp_timer);
5511 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5512 adapter->sfp_timer.data = (unsigned long) adapter;
5514 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5516 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5517 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5519 /* a new SFP+ module arrival, called from GPI SDP2 context */
5520 INIT_WORK(&adapter->sfp_config_module_task,
5521 ixgbe_sfp_config_module_task);
5523 ii->get_invariants(hw);
5525 /* setup the private structure */
5526 err = ixgbe_sw_init(adapter);
5531 * If there is a fan on this device and it has failed log the
5534 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5535 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5536 if (esdp & IXGBE_ESDP_SDP1)
5537 DPRINTK(PROBE, CRIT,
5538 "Fan has stopped, replace the adapter\n");
5541 /* reset_hw fills in the perm_addr as well */
5542 err = hw->mac.ops.reset_hw(hw);
5543 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5544 hw->mac.type == ixgbe_mac_82598EB) {
5546 * Start a kernel thread to watch for a module to arrive.
5547 * Only do this for 82598, since 82599 will generate
5548 * interrupts on module arrival.
5550 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5551 mod_timer(&adapter->sfp_timer,
5552 round_jiffies(jiffies + (2 * HZ)));
5554 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5555 dev_err(&adapter->pdev->dev, "failed to initialize because "
5556 "an unsupported SFP+ module type was detected.\n"
5557 "Reload the driver after installing a supported "
5561 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5565 netdev->features = NETIF_F_SG |
5567 NETIF_F_HW_VLAN_TX |
5568 NETIF_F_HW_VLAN_RX |
5569 NETIF_F_HW_VLAN_FILTER;
5571 netdev->features |= NETIF_F_IPV6_CSUM;
5572 netdev->features |= NETIF_F_TSO;
5573 netdev->features |= NETIF_F_TSO6;
5574 netdev->features |= NETIF_F_GRO;
5576 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5577 netdev->features |= NETIF_F_SCTP_CSUM;
5579 netdev->vlan_features |= NETIF_F_TSO;
5580 netdev->vlan_features |= NETIF_F_TSO6;
5581 netdev->vlan_features |= NETIF_F_IP_CSUM;
5582 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5583 netdev->vlan_features |= NETIF_F_SG;
5585 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5586 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5588 #ifdef CONFIG_IXGBE_DCB
5589 netdev->dcbnl_ops = &dcbnl_ops;
5593 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5594 if (hw->mac.ops.get_device_caps) {
5595 hw->mac.ops.get_device_caps(hw, &device_caps);
5596 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5597 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5600 #endif /* IXGBE_FCOE */
5602 netdev->features |= NETIF_F_HIGHDMA;
5604 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5605 netdev->features |= NETIF_F_LRO;
5607 /* make sure the EEPROM is good */
5608 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5609 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5614 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5615 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5617 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5618 dev_err(&pdev->dev, "invalid MAC address\n");
5623 init_timer(&adapter->watchdog_timer);
5624 adapter->watchdog_timer.function = &ixgbe_watchdog;
5625 adapter->watchdog_timer.data = (unsigned long)adapter;
5627 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5628 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5630 err = ixgbe_init_interrupt_scheme(adapter);
5634 switch (pdev->device) {
5635 case IXGBE_DEV_ID_82599_KX4:
5636 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5637 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5638 /* Enable ACPI wakeup in GRC */
5639 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5640 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5646 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5648 /* pick up the PCI bus settings for reporting later */
5649 hw->mac.ops.get_bus_info(hw);
5651 /* print bus type/speed/width info */
5652 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5653 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5654 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5655 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5656 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5657 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5660 ixgbe_read_pba_num_generic(hw, &part_num);
5661 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5662 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5663 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5664 (part_num >> 8), (part_num & 0xff));
5666 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5667 hw->mac.type, hw->phy.type,
5668 (part_num >> 8), (part_num & 0xff));
5670 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5671 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5672 "this card is not sufficient for optimal "
5674 dev_warn(&pdev->dev, "For optimal performance a x8 "
5675 "PCI-Express slot is required.\n");
5678 /* save off EEPROM version number */
5679 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5681 /* reset the hardware with the new settings */
5682 err = hw->mac.ops.start_hw(hw);
5684 if (err == IXGBE_ERR_EEPROM_VERSION) {
5685 /* We are running on a pre-production device, log a warning */
5686 dev_warn(&pdev->dev, "This device is a pre-production "
5687 "adapter/LOM. Please be aware there may be issues "
5688 "associated with your hardware. If you are "
5689 "experiencing problems please contact your Intel or "
5690 "hardware representative who provided you with this "
5693 strcpy(netdev->name, "eth%d");
5694 err = register_netdev(netdev);
5698 /* carrier off reporting is important to ethtool even BEFORE open */
5699 netif_carrier_off(netdev);
5701 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5702 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5703 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5705 #ifdef CONFIG_IXGBE_DCA
5706 if (dca_add_requester(&pdev->dev) == 0) {
5707 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5708 ixgbe_setup_dca(adapter);
5711 /* add san mac addr to netdev */
5712 ixgbe_add_sanmac_netdev(netdev);
5714 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5719 ixgbe_release_hw_control(adapter);
5720 ixgbe_clear_interrupt_scheme(adapter);
5723 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5724 del_timer_sync(&adapter->sfp_timer);
5725 cancel_work_sync(&adapter->sfp_task);
5726 cancel_work_sync(&adapter->multispeed_fiber_task);
5727 cancel_work_sync(&adapter->sfp_config_module_task);
5728 iounmap(hw->hw_addr);
5730 free_netdev(netdev);
5732 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5736 pci_disable_device(pdev);
5741 * ixgbe_remove - Device Removal Routine
5742 * @pdev: PCI device information struct
5744 * ixgbe_remove is called by the PCI subsystem to alert the driver
5745 * that it should release a PCI device. The could be caused by a
5746 * Hot-Plug event, or because the driver is going to be removed from
5749 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5751 struct net_device *netdev = pci_get_drvdata(pdev);
5752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5755 set_bit(__IXGBE_DOWN, &adapter->state);
5756 /* clear the module not found bit to make sure the worker won't
5759 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5760 del_timer_sync(&adapter->watchdog_timer);
5762 del_timer_sync(&adapter->sfp_timer);
5763 cancel_work_sync(&adapter->watchdog_task);
5764 cancel_work_sync(&adapter->sfp_task);
5765 cancel_work_sync(&adapter->multispeed_fiber_task);
5766 cancel_work_sync(&adapter->sfp_config_module_task);
5767 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5768 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5769 cancel_work_sync(&adapter->fdir_reinit_task);
5770 flush_scheduled_work();
5772 #ifdef CONFIG_IXGBE_DCA
5773 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5774 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5775 dca_remove_requester(&pdev->dev);
5776 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5781 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5782 ixgbe_cleanup_fcoe(adapter);
5784 #endif /* IXGBE_FCOE */
5786 /* remove the added san mac */
5787 ixgbe_del_sanmac_netdev(netdev);
5789 if (netdev->reg_state == NETREG_REGISTERED)
5790 unregister_netdev(netdev);
5792 ixgbe_clear_interrupt_scheme(adapter);
5794 ixgbe_release_hw_control(adapter);
5796 iounmap(adapter->hw.hw_addr);
5797 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5800 DPRINTK(PROBE, INFO, "complete\n");
5802 free_netdev(netdev);
5804 err = pci_disable_pcie_error_reporting(pdev);
5807 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5809 pci_disable_device(pdev);
5813 * ixgbe_io_error_detected - called when PCI error is detected
5814 * @pdev: Pointer to PCI device
5815 * @state: The current pci connection state
5817 * This function is called after a PCI bus error affecting
5818 * this device has been detected.
5820 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5821 pci_channel_state_t state)
5823 struct net_device *netdev = pci_get_drvdata(pdev);
5824 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5826 netif_device_detach(netdev);
5828 if (state == pci_channel_io_perm_failure)
5829 return PCI_ERS_RESULT_DISCONNECT;
5831 if (netif_running(netdev))
5832 ixgbe_down(adapter);
5833 pci_disable_device(pdev);
5835 /* Request a slot reset. */
5836 return PCI_ERS_RESULT_NEED_RESET;
5840 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5841 * @pdev: Pointer to PCI device
5843 * Restart the card from scratch, as if from a cold-boot.
5845 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5847 struct net_device *netdev = pci_get_drvdata(pdev);
5848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5849 pci_ers_result_t result;
5852 if (pci_enable_device_mem(pdev)) {
5854 "Cannot re-enable PCI device after reset.\n");
5855 result = PCI_ERS_RESULT_DISCONNECT;
5857 pci_set_master(pdev);
5858 pci_restore_state(pdev);
5860 pci_wake_from_d3(pdev, false);
5862 ixgbe_reset(adapter);
5863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5864 result = PCI_ERS_RESULT_RECOVERED;
5867 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5870 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5871 /* non-fatal, continue */
5878 * ixgbe_io_resume - called when traffic can start flowing again.
5879 * @pdev: Pointer to PCI device
5881 * This callback is called when the error recovery driver tells us that
5882 * its OK to resume normal operation.
5884 static void ixgbe_io_resume(struct pci_dev *pdev)
5886 struct net_device *netdev = pci_get_drvdata(pdev);
5887 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5889 if (netif_running(netdev)) {
5890 if (ixgbe_up(adapter)) {
5891 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5896 netif_device_attach(netdev);
5899 static struct pci_error_handlers ixgbe_err_handler = {
5900 .error_detected = ixgbe_io_error_detected,
5901 .slot_reset = ixgbe_io_slot_reset,
5902 .resume = ixgbe_io_resume,
5905 static struct pci_driver ixgbe_driver = {
5906 .name = ixgbe_driver_name,
5907 .id_table = ixgbe_pci_tbl,
5908 .probe = ixgbe_probe,
5909 .remove = __devexit_p(ixgbe_remove),
5911 .suspend = ixgbe_suspend,
5912 .resume = ixgbe_resume,
5914 .shutdown = ixgbe_shutdown,
5915 .err_handler = &ixgbe_err_handler
5919 * ixgbe_init_module - Driver Registration Routine
5921 * ixgbe_init_module is the first routine called when the driver is
5922 * loaded. All it does is register with the PCI subsystem.
5924 static int __init ixgbe_init_module(void)
5927 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5928 ixgbe_driver_string, ixgbe_driver_version);
5930 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5932 #ifdef CONFIG_IXGBE_DCA
5933 dca_register_notify(&dca_notifier);
5936 ret = pci_register_driver(&ixgbe_driver);
5940 module_init(ixgbe_init_module);
5943 * ixgbe_exit_module - Driver Exit Cleanup Routine
5945 * ixgbe_exit_module is called just before the driver is removed
5948 static void __exit ixgbe_exit_module(void)
5950 #ifdef CONFIG_IXGBE_DCA
5951 dca_unregister_notify(&dca_notifier);
5953 pci_unregister_driver(&ixgbe_driver);
5956 #ifdef CONFIG_IXGBE_DCA
5957 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5962 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5963 __ixgbe_notify_dca);
5965 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5968 #endif /* CONFIG_IXGBE_DCA */
5971 * ixgbe_get_hw_dev_name - return device name string
5972 * used by hardware layer to print debugging information
5974 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5976 struct ixgbe_adapter *adapter = hw->back;
5977 return adapter->netdev->name;
5981 module_exit(ixgbe_exit_module);