drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.44-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  97          board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 101          board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 103          board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 105          board_82599 },
 106
 107         /* required last entry */
 108         {0, }
 109 };
 110 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 111
 112 #ifdef CONFIG_IXGBE_DCA
 113 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 114                             void *p);
 115 static struct notifier_block dca_notifier = {
 116         .notifier_call = ixgbe_notify_dca,
 117         .next          = NULL,
 118         .priority      = 0
 119 };
 120 #endif
 121
 122 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 123 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 124 MODULE_LICENSE("GPL");
 125 MODULE_VERSION(DRV_VERSION);
 126
 127 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 128
 129 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 130 {
 131         u32 ctrl_ext;
 132
 133         /* Let firmware take over control of h/w */
 134         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 135         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 136                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 137 }
 138
 139 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 140 {
 141         u32 ctrl_ext;
 142
 143         /* Let firmware know the driver has taken over */
 144         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 145         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 146                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 147 }
 148
 149 /*
 150  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 151  * @adapter: pointer to adapter struct
 152  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 153  * @queue: queue to map the corresponding interrupt to
 154  * @msix_vector: the vector to map to the corresponding queue
 155  *
 156  */
 157 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 158                            u8 queue, u8 msix_vector)
 159 {
 160         u32 ivar, index;
 161         struct ixgbe_hw *hw = &adapter->hw;
 162         switch (hw->mac.type) {
 163         case ixgbe_mac_82598EB:
 164                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 165                 if (direction == -1)
 166                         direction = 0;
 167                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 168                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 169                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 170                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 171                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 172                 break;
 173         case ixgbe_mac_82599EB:
 174                 if (direction == -1) {
 175                         /* other causes */
 176                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 177                         index = ((queue & 1) * 8);
 178                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 179                         ivar &= ~(0xFF << index);
 180                         ivar |= (msix_vector << index);
 181                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 182                         break;
 183                 } else {
 184                         /* tx or rx causes */
 185                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 186                         index = ((16 * (queue & 1)) + (8 * direction));
 187                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 188                         ivar &= ~(0xFF << index);
 189                         ivar |= (msix_vector << index);
 190                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 191                         break;
 192                 }
 193         default:
 194                 break;
 195         }
 196 }
 197
 198 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 199                                           u64 qmask)
 200 {
 201         u32 mask;
 202
 203         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 204                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 205                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 206         } else {
 207                 mask = (qmask & 0xFFFFFFFF);
 208                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 209                 mask = (qmask >> 32);
 210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 211         }
 212 }
 213
 214 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 215                                              struct ixgbe_tx_buffer
 216                                              *tx_buffer_info)
 217 {
 218         tx_buffer_info->dma = 0;
 219         if (tx_buffer_info->skb) {
 220                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 221                               DMA_TO_DEVICE);
 222                 dev_kfree_skb_any(tx_buffer_info->skb);
 223                 tx_buffer_info->skb = NULL;
 224         }
 225         tx_buffer_info->time_stamp = 0;
 226         /* tx_buffer_info must be completely set up in the transmit path */
 227 }
 228
 229 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 230                                        struct ixgbe_ring *tx_ring,
 231                                        unsigned int eop)
 232 {
 233         struct ixgbe_hw *hw = &adapter->hw;
 234
 235         /* Detect a transmit hang in hardware, this serializes the
 236          * check with the clearing of time_stamp and movement of eop */
 237         adapter->detect_tx_hung = false;
 238         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 239             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 240             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 241                 /* detected Tx unit hang */
 242                 union ixgbe_adv_tx_desc *tx_desc;
 243                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 244                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 245                         "  Tx Queue             <%d>\n"
 246                         "  TDH, TDT             <%x>, <%x>\n"
 247                         "  next_to_use          <%x>\n"
 248                         "  next_to_clean        <%x>\n"
 249                         "tx_buffer_info[next_to_clean]\n"
 250                         "  time_stamp           <%lx>\n"
 251                         "  jiffies              <%lx>\n",
 252                         tx_ring->queue_index,
 253                         IXGBE_READ_REG(hw, tx_ring->head),
 254                         IXGBE_READ_REG(hw, tx_ring->tail),
 255                         tx_ring->next_to_use, eop,
 256                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 257                 return true;
 258         }
 259
 260         return false;
 261 }
 262
 263 #define IXGBE_MAX_TXD_PWR       14
 264 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 265
 266 /* Tx Descriptors needed, worst case */
 267 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 268                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 269 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 270         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 271
 272 static void ixgbe_tx_timeout(struct net_device *netdev);
 273
 274 /**
 275  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 276  * @q_vector: structure containing interrupt and ring information
 277  * @tx_ring: tx ring to clean
 278  **/
 279 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 280                                struct ixgbe_ring *tx_ring)
 281 {
 282         struct ixgbe_adapter *adapter = q_vector->adapter;
 283         struct net_device *netdev = adapter->netdev;
 284         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 285         struct ixgbe_tx_buffer *tx_buffer_info;
 286         unsigned int i, eop, count = 0;
 287         unsigned int total_bytes = 0, total_packets = 0;
 288
 289         i = tx_ring->next_to_clean;
 290         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 291         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 292
 293         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 294                (count < tx_ring->work_limit)) {
 295                 bool cleaned = false;
 296                 for ( ; !cleaned; count++) {
 297                         struct sk_buff *skb;
 298                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 299                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 300                         cleaned = (i == eop);
 301                         skb = tx_buffer_info->skb;
 302
 303                         if (cleaned && skb) {
 304                                 unsigned int segs, bytecount;
 305                                 unsigned int hlen = skb_headlen(skb);
 306
 307                                 /* gso_segs is currently only valid for tcp */
 308                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 309 #ifdef IXGBE_FCOE
 310                                 /* adjust for FCoE Sequence Offload */
 311                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 312                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 313                                     skb_is_gso(skb)) {
 314                                         hlen = skb_transport_offset(skb) +
 315                                                 sizeof(struct fc_frame_header) +
 316                                                 sizeof(struct fcoe_crc_eof);
 317                                         segs = DIV_ROUND_UP(skb->len - hlen,
 318                                                 skb_shinfo(skb)->gso_size);
 319                                 }
 320 #endif /* IXGBE_FCOE */
 321                                 /* multiply data chunks by size of headers */
 322                                 bytecount = ((segs - 1) * hlen) + skb->len;
 323                                 total_packets += segs;
 324                                 total_bytes += bytecount;
 325                         }
 326
 327                         ixgbe_unmap_and_free_tx_resource(adapter,
 328                                                          tx_buffer_info);
 329
 330                         tx_desc->wb.status = 0;
 331
 332                         i++;
 333                         if (i == tx_ring->count)
 334                                 i = 0;
 335                 }
 336
 337                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 338                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 339         }
 340
 341         tx_ring->next_to_clean = i;
 342
 343 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 344         if (unlikely(count && netif_carrier_ok(netdev) &&
 345                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 346                 /* Make sure that anybody stopping the queue after this
 347                  * sees the new next_to_clean.
 348                  */
 349                 smp_mb();
 350                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 351                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 352                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 353                         ++adapter->restart_queue;
 354                 }
 355         }
 356
 357         if (adapter->detect_tx_hung) {
 358                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 359                         /* schedule immediate reset if we believe we hung */
 360                         DPRINTK(PROBE, INFO,
 361                                 "tx hang %d detected, resetting adapter\n",
 362                                 adapter->tx_timeout_count + 1);
 363                         ixgbe_tx_timeout(adapter->netdev);
 364                 }
 365         }
 366
 367         /* re-arm the interrupt */
 368         if (count >= tx_ring->work_limit)
 369                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 370
 371         tx_ring->total_bytes += total_bytes;
 372         tx_ring->total_packets += total_packets;
 373         tx_ring->stats.packets += total_packets;
 374         tx_ring->stats.bytes += total_bytes;
 375         adapter->net_stats.tx_bytes += total_bytes;
 376         adapter->net_stats.tx_packets += total_packets;
 377         return (count < tx_ring->work_limit);
 378 }
 379
 380 #ifdef CONFIG_IXGBE_DCA
 381 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 382                                 struct ixgbe_ring *rx_ring)
 383 {
 384         u32 rxctrl;
 385         int cpu = get_cpu();
 386         int q = rx_ring - adapter->rx_ring;
 387
 388         if (rx_ring->cpu != cpu) {
 389                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 390                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 391                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 392                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 393                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 394                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 395                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 396                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 397                 }
 398                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 399                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 400                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 401                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 402                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 403                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 404                 rx_ring->cpu = cpu;
 405         }
 406         put_cpu();
 407 }
 408
 409 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 410                                 struct ixgbe_ring *tx_ring)
 411 {
 412         u32 txctrl;
 413         int cpu = get_cpu();
 414         int q = tx_ring - adapter->tx_ring;
 415
 416         if (tx_ring->cpu != cpu) {
 417                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 418                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 419                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 420                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 421                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 422                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 423                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 424                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 425                 }
 426                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 427                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 428                 tx_ring->cpu = cpu;
 429         }
 430         put_cpu();
 431 }
 432
 433 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 434 {
 435         int i;
 436
 437         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 438                 return;
 439
 440         /* always use CB2 mode, difference is masked in the CB driver */
 441         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 442
 443         for (i = 0; i < adapter->num_tx_queues; i++) {
 444                 adapter->tx_ring[i].cpu = -1;
 445                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 446         }
 447         for (i = 0; i < adapter->num_rx_queues; i++) {
 448                 adapter->rx_ring[i].cpu = -1;
 449                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 450         }
 451 }
 452
 453 static int __ixgbe_notify_dca(struct device *dev, void *data)
 454 {
 455         struct net_device *netdev = dev_get_drvdata(dev);
 456         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 457         unsigned long event = *(unsigned long *)data;
 458
 459         switch (event) {
 460         case DCA_PROVIDER_ADD:
 461                 /* if we're already enabled, don't do it again */
 462                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 463                         break;
 464                 if (dca_add_requester(dev) == 0) {
 465                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 466                         ixgbe_setup_dca(adapter);
 467                         break;
 468                 }
 469                 /* Fall Through since DCA is disabled. */
 470         case DCA_PROVIDER_REMOVE:
 471                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 472                         dca_remove_requester(dev);
 473                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 474                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 475                 }
 476                 break;
 477         }
 478
 479         return 0;
 480 }
 481
 482 #endif /* CONFIG_IXGBE_DCA */
 483 /**
 484  * ixgbe_receive_skb - Send a completed packet up the stack
 485  * @adapter: board private structure
 486  * @skb: packet to send up
 487  * @status: hardware indication of status of receive
 488  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 489  * @rx_desc: rx descriptor
 490  **/
 491 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 492                               struct sk_buff *skb, u8 status,
 493                               struct ixgbe_ring *ring,
 494                               union ixgbe_adv_rx_desc *rx_desc)
 495 {
 496         struct ixgbe_adapter *adapter = q_vector->adapter;
 497         struct napi_struct *napi = &q_vector->napi;
 498         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 499         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 500
 501         skb_record_rx_queue(skb, ring->queue_index);
 502         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 503                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 504                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 505                 else
 506                         napi_gro_receive(napi, skb);
 507         } else {
 508                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 509                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 510                 else
 511                         netif_rx(skb);
 512         }
 513 }
 514
 515 /**
 516  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 517  * @adapter: address of board private structure
 518  * @status_err: hardware indication of status of receive
 519  * @skb: skb currently being received and modified
 520  **/
 521 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 522                                      union ixgbe_adv_rx_desc *rx_desc,
 523                                      struct sk_buff *skb)
 524 {
 525         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 526
 527         skb->ip_summed = CHECKSUM_NONE;
 528
 529         /* Rx csum disabled */
 530         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 531                 return;
 532
 533         /* if IP and error */
 534         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 535             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 536                 adapter->hw_csum_rx_error++;
 537                 return;
 538         }
 539
 540         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 541                 return;
 542
 543         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 544                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 545
 546                 /*
 547                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 548                  * checksum errors.
 549                  */
 550                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 551                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 552                         return;
 553
 554                 adapter->hw_csum_rx_error++;
 555                 return;
 556         }
 557
 558         /* It must be a TCP or UDP packet with a valid checksum */
 559         skb->ip_summed = CHECKSUM_UNNECESSARY;
 560         adapter->hw_csum_rx_good++;
 561 }
 562
 563 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 564                                          struct ixgbe_ring *rx_ring, u32 val)
 565 {
 566         /*
 567          * Force memory writes to complete before letting h/w
 568          * know there are new descriptors to fetch.  (Only
 569          * applicable for weak-ordered memory model archs,
 570          * such as IA-64).
 571          */
 572         wmb();
 573         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 574 }
 575
 576 /**
 577  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 578  * @adapter: address of board private structure
 579  **/
 580 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 581                                    struct ixgbe_ring *rx_ring,
 582                                    int cleaned_count)
 583 {
 584         struct pci_dev *pdev = adapter->pdev;
 585         union ixgbe_adv_rx_desc *rx_desc;
 586         struct ixgbe_rx_buffer *bi;
 587         unsigned int i;
 588
 589         i = rx_ring->next_to_use;
 590         bi = &rx_ring->rx_buffer_info[i];
 591
 592         while (cleaned_count--) {
 593                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 594
 595                 if (!bi->page_dma &&
 596                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 597                         if (!bi->page) {
 598                                 bi->page = alloc_page(GFP_ATOMIC);
 599                                 if (!bi->page) {
 600                                         adapter->alloc_rx_page_failed++;
 601                                         goto no_buffers;
 602                                 }
 603                                 bi->page_offset = 0;
 604                         } else {
 605                                 /* use a half page if we're re-using */
 606                                 bi->page_offset ^= (PAGE_SIZE / 2);
 607                         }
 608
 609                         bi->page_dma = pci_map_page(pdev, bi->page,
 610                                                     bi->page_offset,
 611                                                     (PAGE_SIZE / 2),
 612                                                     PCI_DMA_FROMDEVICE);
 613                 }
 614
 615                 if (!bi->skb) {
 616                         struct sk_buff *skb;
 617                         skb = netdev_alloc_skb(adapter->netdev,
 618                                                (rx_ring->rx_buf_len +
 619                                                 NET_IP_ALIGN));
 620
 621                         if (!skb) {
 622                                 adapter->alloc_rx_buff_failed++;
 623                                 goto no_buffers;
 624                         }
 625
 626                         /*
 627                          * Make buffer alignment 2 beyond a 16 byte boundary
 628                          * this will result in a 16 byte aligned IP header after
 629                          * the 14 byte MAC header is removed
 630                          */
 631                         skb_reserve(skb, NET_IP_ALIGN);
 632
 633                         bi->skb = skb;
 634                         bi->dma = pci_map_single(pdev, skb->data,
 635                                                  rx_ring->rx_buf_len,
 636                                                  PCI_DMA_FROMDEVICE);
 637                 }
 638                 /* Refresh the desc even if buffer_addrs didn't change because
 639                  * each write-back erases this info. */
 640                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 641                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 642                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 643                 } else {
 644                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 645                 }
 646
 647                 i++;
 648                 if (i == rx_ring->count)
 649                         i = 0;
 650                 bi = &rx_ring->rx_buffer_info[i];
 651         }
 652
 653 no_buffers:
 654         if (rx_ring->next_to_use != i) {
 655                 rx_ring->next_to_use = i;
 656                 if (i-- == 0)
 657                         i = (rx_ring->count - 1);
 658
 659                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 660         }
 661 }
 662
 663 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 664 {
 665         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 666 }
 667
 668 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 669 {
 670         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 671 }
 672
 673 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 674 {
 675         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 676                 IXGBE_RXDADV_RSCCNT_MASK) >>
 677                 IXGBE_RXDADV_RSCCNT_SHIFT;
 678 }
 679
 680 /**
 681  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 682  * @skb: pointer to the last skb in the rsc queue
 683  *
 684  * This function changes a queue full of hw rsc buffers into a completed
 685  * packet.  It uses the ->prev pointers to find the first packet and then
 686  * turns it into the frag list owner.
 687  **/
 688 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 689 {
 690         unsigned int frag_list_size = 0;
 691
 692         while (skb->prev) {
 693                 struct sk_buff *prev = skb->prev;
 694                 frag_list_size += skb->len;
 695                 skb->prev = NULL;
 696                 skb = prev;
 697         }
 698
 699         skb_shinfo(skb)->frag_list = skb->next;
 700         skb->next = NULL;
 701         skb->len += frag_list_size;
 702         skb->data_len += frag_list_size;
 703         skb->truesize += frag_list_size;
 704         return skb;
 705 }
 706
 707 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 708                                struct ixgbe_ring *rx_ring,
 709                                int *work_done, int work_to_do)
 710 {
 711         struct ixgbe_adapter *adapter = q_vector->adapter;
 712         struct pci_dev *pdev = adapter->pdev;
 713         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 714         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 715         struct sk_buff *skb;
 716         unsigned int i, rsc_count = 0;
 717         u32 len, staterr;
 718         u16 hdr_info;
 719         bool cleaned = false;
 720         int cleaned_count = 0;
 721         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 722 #ifdef IXGBE_FCOE
 723         int ddp_bytes = 0;
 724 #endif /* IXGBE_FCOE */
 725
 726         i = rx_ring->next_to_clean;
 727         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 728         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 729         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 730
 731         while (staterr & IXGBE_RXD_STAT_DD) {
 732                 u32 upper_len = 0;
 733                 if (*work_done >= work_to_do)
 734                         break;
 735                 (*work_done)++;
 736
 737                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 738                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 739                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 740                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 741                         if (hdr_info & IXGBE_RXDADV_SPH)
 742                                 adapter->rx_hdr_split++;
 743                         if (len > IXGBE_RX_HDR_SIZE)
 744                                 len = IXGBE_RX_HDR_SIZE;
 745                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 746                 } else {
 747                         len = le16_to_cpu(rx_desc->wb.upper.length);
 748                 }
 749
 750                 cleaned = true;
 751                 skb = rx_buffer_info->skb;
 752                 prefetch(skb->data - NET_IP_ALIGN);
 753                 rx_buffer_info->skb = NULL;
 754
 755                 if (rx_buffer_info->dma) {
 756                         pci_unmap_single(pdev, rx_buffer_info->dma,
 757                                          rx_ring->rx_buf_len,
 758                                          PCI_DMA_FROMDEVICE);
 759                         rx_buffer_info->dma = 0;
 760                         skb_put(skb, len);
 761                 }
 762
 763                 if (upper_len) {
 764                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 765                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 766                         rx_buffer_info->page_dma = 0;
 767                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 768                                            rx_buffer_info->page,
 769                                            rx_buffer_info->page_offset,
 770                                            upper_len);
 771
 772                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 773                             (page_count(rx_buffer_info->page) != 1))
 774                                 rx_buffer_info->page = NULL;
 775                         else
 776                                 get_page(rx_buffer_info->page);
 777
 778                         skb->len += upper_len;
 779                         skb->data_len += upper_len;
 780                         skb->truesize += upper_len;
 781                 }
 782
 783                 i++;
 784                 if (i == rx_ring->count)
 785                         i = 0;
 786
 787                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 788                 prefetch(next_rxd);
 789                 cleaned_count++;
 790
 791                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 792                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 793
 794                 if (rsc_count) {
 795                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 796                                      IXGBE_RXDADV_NEXTP_SHIFT;
 797                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 798                         rx_ring->rsc_count += (rsc_count - 1);
 799                 } else {
 800                         next_buffer = &rx_ring->rx_buffer_info[i];
 801                 }
 802
 803                 if (staterr & IXGBE_RXD_STAT_EOP) {
 804                         if (skb->prev)
 805                                 skb = ixgbe_transform_rsc_queue(skb);
 806                         rx_ring->stats.packets++;
 807                         rx_ring->stats.bytes += skb->len;
 808                 } else {
 809                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 810                                 rx_buffer_info->skb = next_buffer->skb;
 811                                 rx_buffer_info->dma = next_buffer->dma;
 812                                 next_buffer->skb = skb;
 813                                 next_buffer->dma = 0;
 814                         } else {
 815                                 skb->next = next_buffer->skb;
 816                                 skb->next->prev = skb;
 817                         }
 818                         adapter->non_eop_descs++;
 819                         goto next_desc;
 820                 }
 821
 822                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 823                         dev_kfree_skb_irq(skb);
 824                         goto next_desc;
 825                 }
 826
 827                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 828
 829                 /* probably a little skewed due to removing CRC */
 830                 total_rx_bytes += skb->len;
 831                 total_rx_packets++;
 832
 833                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 834 #ifdef IXGBE_FCOE
 835                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 836                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 837                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 838                         if (!ddp_bytes)
 839                                 goto next_desc;
 840                 }
 841 #endif /* IXGBE_FCOE */
 842                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 843
 844 next_desc:
 845                 rx_desc->wb.upper.status_error = 0;
 846
 847                 /* return some buffers to hardware, one at a time is too slow */
 848                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 849                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 850                         cleaned_count = 0;
 851                 }
 852
 853                 /* use prefetched values */
 854                 rx_desc = next_rxd;
 855                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 856
 857                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 858         }
 859
 860         rx_ring->next_to_clean = i;
 861         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 862
 863         if (cleaned_count)
 864                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 865
 866 #ifdef IXGBE_FCOE
 867         /* include DDPed FCoE data */
 868         if (ddp_bytes > 0) {
 869                 unsigned int mss;
 870
 871                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 872                         sizeof(struct fc_frame_header) -
 873                         sizeof(struct fcoe_crc_eof);
 874                 if (mss > 512)
 875                         mss &= ~511;
 876                 total_rx_bytes += ddp_bytes;
 877                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 878         }
 879 #endif /* IXGBE_FCOE */
 880
 881         rx_ring->total_packets += total_rx_packets;
 882         rx_ring->total_bytes += total_rx_bytes;
 883         adapter->net_stats.rx_bytes += total_rx_bytes;
 884         adapter->net_stats.rx_packets += total_rx_packets;
 885
 886         return cleaned;
 887 }
 888
 889 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 890 /**
 891  * ixgbe_configure_msix - Configure MSI-X hardware
 892  * @adapter: board private structure
 893  *
 894  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 895  * interrupts.
 896  **/
 897 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 898 {
 899         struct ixgbe_q_vector *q_vector;
 900         int i, j, q_vectors, v_idx, r_idx;
 901         u32 mask;
 902
 903         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 904
 905         /*
 906          * Populate the IVAR table and set the ITR values to the
 907          * corresponding register.
 908          */
 909         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 910                 q_vector = adapter->q_vector[v_idx];
 911                 /* XXX for_each_bit(...) */
 912                 r_idx = find_first_bit(q_vector->rxr_idx,
 913                                        adapter->num_rx_queues);
 914
 915                 for (i = 0; i < q_vector->rxr_count; i++) {
 916                         j = adapter->rx_ring[r_idx].reg_idx;
 917                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 918                         r_idx = find_next_bit(q_vector->rxr_idx,
 919                                               adapter->num_rx_queues,
 920                                               r_idx + 1);
 921                 }
 922                 r_idx = find_first_bit(q_vector->txr_idx,
 923                                        adapter->num_tx_queues);
 924
 925                 for (i = 0; i < q_vector->txr_count; i++) {
 926                         j = adapter->tx_ring[r_idx].reg_idx;
 927                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 928                         r_idx = find_next_bit(q_vector->txr_idx,
 929                                               adapter->num_tx_queues,
 930                                               r_idx + 1);
 931                 }
 932
 933                 if (q_vector->txr_count && !q_vector->rxr_count)
 934                         /* tx only */
 935                         q_vector->eitr = adapter->tx_eitr_param;
 936                 else if (q_vector->rxr_count)
 937                         /* rx or mixed */
 938                         q_vector->eitr = adapter->rx_eitr_param;
 939
 940                 ixgbe_write_eitr(q_vector);
 941         }
 942
 943         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 944                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 945                                v_idx);
 946         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 947                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 948         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 949
 950         /* set up to autoclear timer, and the vectors */
 951         mask = IXGBE_EIMS_ENABLE_MASK;
 952         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 953         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 954 }
 955
 956 enum latency_range {
 957         lowest_latency = 0,
 958         low_latency = 1,
 959         bulk_latency = 2,
 960         latency_invalid = 255
 961 };
 962
 963 /**
 964  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 965  * @adapter: pointer to adapter
 966  * @eitr: eitr setting (ints per sec) to give last timeslice
 967  * @itr_setting: current throttle rate in ints/second
 968  * @packets: the number of packets during this measurement interval
 969  * @bytes: the number of bytes during this measurement interval
 970  *
 971  *      Stores a new ITR value based on packets and byte
 972  *      counts during the last interrupt.  The advantage of per interrupt
 973  *      computation is faster updates and more accurate ITR for the current
 974  *      traffic pattern.  Constants in this function were computed
 975  *      based on theoretical maximum wire speed and thresholds were set based
 976  *      on testing data as well as attempting to minimize response time
 977  *      while increasing bulk throughput.
 978  *      this functionality is controlled by the InterruptThrottleRate module
 979  *      parameter (see ixgbe_param.c)
 980  **/
 981 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 982                            u32 eitr, u8 itr_setting,
 983                            int packets, int bytes)
 984 {
 985         unsigned int retval = itr_setting;
 986         u32 timepassed_us;
 987         u64 bytes_perint;
 988
 989         if (packets == 0)
 990                 goto update_itr_done;
 991
 992
 993         /* simple throttlerate management
 994          *    0-20MB/s lowest (100000 ints/s)
 995          *   20-100MB/s low   (20000 ints/s)
 996          *  100-1249MB/s bulk (8000 ints/s)
 997          */
 998         /* what was last interrupt timeslice? */
 999         timepassed_us = 1000000/eitr;
1000         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1001
1002         switch (itr_setting) {
1003         case lowest_latency:
1004                 if (bytes_perint > adapter->eitr_low)
1005                         retval = low_latency;
1006                 break;
1007         case low_latency:
1008                 if (bytes_perint > adapter->eitr_high)
1009                         retval = bulk_latency;
1010                 else if (bytes_perint <= adapter->eitr_low)
1011                         retval = lowest_latency;
1012                 break;
1013         case bulk_latency:
1014                 if (bytes_perint <= adapter->eitr_high)
1015                         retval = low_latency;
1016                 break;
1017         }
1018
1019 update_itr_done:
1020         return retval;
1021 }
1022
1023 /**
1024  * ixgbe_write_eitr - write EITR register in hardware specific way
1025  * @q_vector: structure containing interrupt and ring information
1026  *
1027  * This function is made to be called by ethtool and by the driver
1028  * when it needs to update EITR registers at runtime.  Hardware
1029  * specific quirks/differences are taken care of here.
1030  */
1031 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1032 {
1033         struct ixgbe_adapter *adapter = q_vector->adapter;
1034         struct ixgbe_hw *hw = &adapter->hw;
1035         int v_idx = q_vector->v_idx;
1036         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1037
1038         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1039                 /* must write high and low 16 bits to reset counter */
1040                 itr_reg |= (itr_reg << 16);
1041         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1042                 /*
1043                  * set the WDIS bit to not clear the timer bits and cause an
1044                  * immediate assertion of the interrupt
1045                  */
1046                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1047         }
1048         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1049 }
1050
1051 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1052 {
1053         struct ixgbe_adapter *adapter = q_vector->adapter;
1054         u32 new_itr;
1055         u8 current_itr, ret_itr;
1056         int i, r_idx;
1057         struct ixgbe_ring *rx_ring, *tx_ring;
1058
1059         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1060         for (i = 0; i < q_vector->txr_count; i++) {
1061                 tx_ring = &(adapter->tx_ring[r_idx]);
1062                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1063                                            q_vector->tx_itr,
1064                                            tx_ring->total_packets,
1065                                            tx_ring->total_bytes);
1066                 /* if the result for this queue would decrease interrupt
1067                  * rate for this vector then use that result */
1068                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1069                                     q_vector->tx_itr - 1 : ret_itr);
1070                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1071                                       r_idx + 1);
1072         }
1073
1074         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1075         for (i = 0; i < q_vector->rxr_count; i++) {
1076                 rx_ring = &(adapter->rx_ring[r_idx]);
1077                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1078                                            q_vector->rx_itr,
1079                                            rx_ring->total_packets,
1080                                            rx_ring->total_bytes);
1081                 /* if the result for this queue would decrease interrupt
1082                  * rate for this vector then use that result */
1083                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1084                                     q_vector->rx_itr - 1 : ret_itr);
1085                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1086                                       r_idx + 1);
1087         }
1088
1089         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1090
1091         switch (current_itr) {
1092         /* counts and packets in update_itr are dependent on these numbers */
1093         case lowest_latency:
1094                 new_itr = 100000;
1095                 break;
1096         case low_latency:
1097                 new_itr = 20000; /* aka hwitr = ~200 */
1098                 break;
1099         case bulk_latency:
1100         default:
1101                 new_itr = 8000;
1102                 break;
1103         }
1104
1105         if (new_itr != q_vector->eitr) {
1106                 /* do an exponential smoothing */
1107                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1108
1109                 /* save the algorithm value here, not the smoothed one */
1110                 q_vector->eitr = new_itr;
1111
1112                 ixgbe_write_eitr(q_vector);
1113         }
1114
1115         return;
1116 }
1117
1118 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1119 {
1120         struct ixgbe_hw *hw = &adapter->hw;
1121
1122         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1123             (eicr & IXGBE_EICR_GPI_SDP1)) {
1124                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1125                 /* write to clear the interrupt */
1126                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1127         }
1128 }
1129
1130 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1131 {
1132         struct ixgbe_hw *hw = &adapter->hw;
1133
1134         if (eicr & IXGBE_EICR_GPI_SDP1) {
1135                 /* Clear the interrupt */
1136                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1137                 schedule_work(&adapter->multispeed_fiber_task);
1138         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1139                 /* Clear the interrupt */
1140                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1141                 schedule_work(&adapter->sfp_config_module_task);
1142         } else {
1143                 /* Interrupt isn't for us... */
1144                 return;
1145         }
1146 }
1147
1148 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1149 {
1150         struct ixgbe_hw *hw = &adapter->hw;
1151
1152         adapter->lsc_int++;
1153         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1154         adapter->link_check_timeout = jiffies;
1155         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1156                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1157                 schedule_work(&adapter->watchdog_task);
1158         }
1159 }
1160
1161 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1162 {
1163         struct net_device *netdev = data;
1164         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1165         struct ixgbe_hw *hw = &adapter->hw;
1166         u32 eicr;
1167
1168         /*
1169          * Workaround for Silicon errata.  Use clear-by-write instead
1170          * of clear-by-read.  Reading with EICS will return the
1171          * interrupt causes without clearing, which later be done
1172          * with the write to EICR.
1173          */
1174         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1175         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1176
1177         if (eicr & IXGBE_EICR_LSC)
1178                 ixgbe_check_lsc(adapter);
1179
1180         if (hw->mac.type == ixgbe_mac_82598EB)
1181                 ixgbe_check_fan_failure(adapter, eicr);
1182
1183         if (hw->mac.type == ixgbe_mac_82599EB) {
1184                 ixgbe_check_sfp_event(adapter, eicr);
1185
1186                 /* Handle Flow Director Full threshold interrupt */
1187                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1188                         int i;
1189                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1190                         /* Disable transmits before FDIR Re-initialization */
1191                         netif_tx_stop_all_queues(netdev);
1192                         for (i = 0; i < adapter->num_tx_queues; i++) {
1193                                 struct ixgbe_ring *tx_ring =
1194                                                            &adapter->tx_ring[i];
1195                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1196                                                        &tx_ring->reinit_state))
1197                                         schedule_work(&adapter->fdir_reinit_task);
1198                         }
1199                 }
1200         }
1201         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1202                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1203
1204         return IRQ_HANDLED;
1205 }
1206
1207 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1208                                            u64 qmask)
1209 {
1210         u32 mask;
1211
1212         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1213                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1214                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1215         } else {
1216                 mask = (qmask & 0xFFFFFFFF);
1217                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1218                 mask = (qmask >> 32);
1219                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1220         }
1221         /* skip the flush */
1222 }
1223
1224 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1225                                             u64 qmask)
1226 {
1227         u32 mask;
1228
1229         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1230                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1231                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1232         } else {
1233                 mask = (qmask & 0xFFFFFFFF);
1234                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1235                 mask = (qmask >> 32);
1236                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1237         }
1238         /* skip the flush */
1239 }
1240
1241 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1242 {
1243         struct ixgbe_q_vector *q_vector = data;
1244         struct ixgbe_adapter  *adapter = q_vector->adapter;
1245         struct ixgbe_ring     *tx_ring;
1246         int i, r_idx;
1247
1248         if (!q_vector->txr_count)
1249                 return IRQ_HANDLED;
1250
1251         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1252         for (i = 0; i < q_vector->txr_count; i++) {
1253                 tx_ring = &(adapter->tx_ring[r_idx]);
1254                 tx_ring->total_bytes = 0;
1255                 tx_ring->total_packets = 0;
1256                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1257                                       r_idx + 1);
1258         }
1259
1260         /* disable interrupts on this vector only */
1261         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1262         napi_schedule(&q_vector->napi);
1263
1264         return IRQ_HANDLED;
1265 }
1266
1267 /**
1268  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1269  * @irq: unused
1270  * @data: pointer to our q_vector struct for this interrupt vector
1271  **/
1272 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1273 {
1274         struct ixgbe_q_vector *q_vector = data;
1275         struct ixgbe_adapter  *adapter = q_vector->adapter;
1276         struct ixgbe_ring  *rx_ring;
1277         int r_idx;
1278         int i;
1279
1280         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1281         for (i = 0;  i < q_vector->rxr_count; i++) {
1282                 rx_ring = &(adapter->rx_ring[r_idx]);
1283                 rx_ring->total_bytes = 0;
1284                 rx_ring->total_packets = 0;
1285                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1286                                       r_idx + 1);
1287         }
1288
1289         if (!q_vector->rxr_count)
1290                 return IRQ_HANDLED;
1291
1292         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1293         rx_ring = &(adapter->rx_ring[r_idx]);
1294         /* disable interrupts on this vector only */
1295         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1296         napi_schedule(&q_vector->napi);
1297
1298         return IRQ_HANDLED;
1299 }
1300
1301 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1302 {
1303         struct ixgbe_q_vector *q_vector = data;
1304         struct ixgbe_adapter  *adapter = q_vector->adapter;
1305         struct ixgbe_ring  *ring;
1306         int r_idx;
1307         int i;
1308
1309         if (!q_vector->txr_count && !q_vector->rxr_count)
1310                 return IRQ_HANDLED;
1311
1312         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1313         for (i = 0; i < q_vector->txr_count; i++) {
1314                 ring = &(adapter->tx_ring[r_idx]);
1315                 ring->total_bytes = 0;
1316                 ring->total_packets = 0;
1317                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1318                                       r_idx + 1);
1319         }
1320
1321         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1322         for (i = 0; i < q_vector->rxr_count; i++) {
1323                 ring = &(adapter->rx_ring[r_idx]);
1324                 ring->total_bytes = 0;
1325                 ring->total_packets = 0;
1326                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1327                                       r_idx + 1);
1328         }
1329
1330         /* disable interrupts on this vector only */
1331         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1332         napi_schedule(&q_vector->napi);
1333
1334         return IRQ_HANDLED;
1335 }
1336
1337 /**
1338  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1339  * @napi: napi struct with our devices info in it
1340  * @budget: amount of work driver is allowed to do this pass, in packets
1341  *
1342  * This function is optimized for cleaning one queue only on a single
1343  * q_vector!!!
1344  **/
1345 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1346 {
1347         struct ixgbe_q_vector *q_vector =
1348                                container_of(napi, struct ixgbe_q_vector, napi);
1349         struct ixgbe_adapter *adapter = q_vector->adapter;
1350         struct ixgbe_ring *rx_ring = NULL;
1351         int work_done = 0;
1352         long r_idx;
1353
1354         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1355         rx_ring = &(adapter->rx_ring[r_idx]);
1356 #ifdef CONFIG_IXGBE_DCA
1357         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1358                 ixgbe_update_rx_dca(adapter, rx_ring);
1359 #endif
1360
1361         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1362
1363         /* If all Rx work done, exit the polling mode */
1364         if (work_done < budget) {
1365                 napi_complete(napi);
1366                 if (adapter->rx_itr_setting & 1)
1367                         ixgbe_set_itr_msix(q_vector);
1368                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1369                         ixgbe_irq_enable_queues(adapter,
1370                                                 ((u64)1 << q_vector->v_idx));
1371         }
1372
1373         return work_done;
1374 }
1375
1376 /**
1377  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1378  * @napi: napi struct with our devices info in it
1379  * @budget: amount of work driver is allowed to do this pass, in packets
1380  *
1381  * This function will clean more than one rx queue associated with a
1382  * q_vector.
1383  **/
1384 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1385 {
1386         struct ixgbe_q_vector *q_vector =
1387                                container_of(napi, struct ixgbe_q_vector, napi);
1388         struct ixgbe_adapter *adapter = q_vector->adapter;
1389         struct ixgbe_ring *ring = NULL;
1390         int work_done = 0, i;
1391         long r_idx;
1392         bool tx_clean_complete = true;
1393
1394         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1395         for (i = 0; i < q_vector->txr_count; i++) {
1396                 ring = &(adapter->tx_ring[r_idx]);
1397 #ifdef CONFIG_IXGBE_DCA
1398                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1399                         ixgbe_update_tx_dca(adapter, ring);
1400 #endif
1401                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1402                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1403                                       r_idx + 1);
1404         }
1405
1406         /* attempt to distribute budget to each queue fairly, but don't allow
1407          * the budget to go below 1 because we'll exit polling */
1408         budget /= (q_vector->rxr_count ?: 1);
1409         budget = max(budget, 1);
1410         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1411         for (i = 0; i < q_vector->rxr_count; i++) {
1412                 ring = &(adapter->rx_ring[r_idx]);
1413 #ifdef CONFIG_IXGBE_DCA
1414                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1415                         ixgbe_update_rx_dca(adapter, ring);
1416 #endif
1417                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1418                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1419                                       r_idx + 1);
1420         }
1421
1422         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1423         ring = &(adapter->rx_ring[r_idx]);
1424         /* If all Rx work done, exit the polling mode */
1425         if (work_done < budget) {
1426                 napi_complete(napi);
1427                 if (adapter->rx_itr_setting & 1)
1428                         ixgbe_set_itr_msix(q_vector);
1429                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1430                         ixgbe_irq_enable_queues(adapter,
1431                                                 ((u64)1 << q_vector->v_idx));
1432                 return 0;
1433         }
1434
1435         return work_done;
1436 }
1437
1438 /**
1439  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1440  * @napi: napi struct with our devices info in it
1441  * @budget: amount of work driver is allowed to do this pass, in packets
1442  *
1443  * This function is optimized for cleaning one queue only on a single
1444  * q_vector!!!
1445  **/
1446 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1447 {
1448         struct ixgbe_q_vector *q_vector =
1449                                container_of(napi, struct ixgbe_q_vector, napi);
1450         struct ixgbe_adapter *adapter = q_vector->adapter;
1451         struct ixgbe_ring *tx_ring = NULL;
1452         int work_done = 0;
1453         long r_idx;
1454
1455         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1456         tx_ring = &(adapter->tx_ring[r_idx]);
1457 #ifdef CONFIG_IXGBE_DCA
1458         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1459                 ixgbe_update_tx_dca(adapter, tx_ring);
1460 #endif
1461
1462         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1463                 work_done = budget;
1464
1465         /* If all Tx work done, exit the polling mode */
1466         if (work_done < budget) {
1467                 napi_complete(napi);
1468                 if (adapter->tx_itr_setting & 1)
1469                         ixgbe_set_itr_msix(q_vector);
1470                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1471                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1472         }
1473
1474         return work_done;
1475 }
1476
1477 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1478                                      int r_idx)
1479 {
1480         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1481
1482         set_bit(r_idx, q_vector->rxr_idx);
1483         q_vector->rxr_count++;
1484 }
1485
1486 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1487                                      int t_idx)
1488 {
1489         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1490
1491         set_bit(t_idx, q_vector->txr_idx);
1492         q_vector->txr_count++;
1493 }
1494
1495 /**
1496  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1497  * @adapter: board private structure to initialize
1498  * @vectors: allotted vector count for descriptor rings
1499  *
1500  * This function maps descriptor rings to the queue-specific vectors
1501  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1502  * one vector per ring/queue, but on a constrained vector budget, we
1503  * group the rings as "efficiently" as possible.  You would add new
1504  * mapping configurations in here.
1505  **/
1506 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1507                                       int vectors)
1508 {
1509         int v_start = 0;
1510         int rxr_idx = 0, txr_idx = 0;
1511         int rxr_remaining = adapter->num_rx_queues;
1512         int txr_remaining = adapter->num_tx_queues;
1513         int i, j;
1514         int rqpv, tqpv;
1515         int err = 0;
1516
1517         /* No mapping required if MSI-X is disabled. */
1518         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1519                 goto out;
1520
1521         /*
1522          * The ideal configuration...
1523          * We have enough vectors to map one per queue.
1524          */
1525         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1526                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1527                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1528
1529                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1530                         map_vector_to_txq(adapter, v_start, txr_idx);
1531
1532                 goto out;
1533         }
1534
1535         /*
1536          * If we don't have enough vectors for a 1-to-1
1537          * mapping, we'll have to group them so there are
1538          * multiple queues per vector.
1539          */
1540         /* Re-adjusting *qpv takes care of the remainder. */
1541         for (i = v_start; i < vectors; i++) {
1542                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1543                 for (j = 0; j < rqpv; j++) {
1544                         map_vector_to_rxq(adapter, i, rxr_idx);
1545                         rxr_idx++;
1546                         rxr_remaining--;
1547                 }
1548         }
1549         for (i = v_start; i < vectors; i++) {
1550                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1551                 for (j = 0; j < tqpv; j++) {
1552                         map_vector_to_txq(adapter, i, txr_idx);
1553                         txr_idx++;
1554                         txr_remaining--;
1555                 }
1556         }
1557
1558 out:
1559         return err;
1560 }
1561
1562 /**
1563  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1564  * @adapter: board private structure
1565  *
1566  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1567  * interrupts from the kernel.
1568  **/
1569 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1570 {
1571         struct net_device *netdev = adapter->netdev;
1572         irqreturn_t (*handler)(int, void *);
1573         int i, vector, q_vectors, err;
1574         int ri=0, ti=0;
1575
1576         /* Decrement for Other and TCP Timer vectors */
1577         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1578
1579         /* Map the Tx/Rx rings to the vectors we were allotted. */
1580         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1581         if (err)
1582                 goto out;
1583
1584 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1585                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1586                          &ixgbe_msix_clean_many)
1587         for (vector = 0; vector < q_vectors; vector++) {
1588                 handler = SET_HANDLER(adapter->q_vector[vector]);
1589
1590                 if(handler == &ixgbe_msix_clean_rx) {
1591                         sprintf(adapter->name[vector], "%s-%s-%d",
1592                                 netdev->name, "rx", ri++);
1593                 }
1594                 else if(handler == &ixgbe_msix_clean_tx) {
1595                         sprintf(adapter->name[vector], "%s-%s-%d",
1596                                 netdev->name, "tx", ti++);
1597                 }
1598                 else
1599                         sprintf(adapter->name[vector], "%s-%s-%d",
1600                                 netdev->name, "TxRx", vector);
1601
1602                 err = request_irq(adapter->msix_entries[vector].vector,
1603                                   handler, 0, adapter->name[vector],
1604                                   adapter->q_vector[vector]);
1605                 if (err) {
1606                         DPRINTK(PROBE, ERR,
1607                                 "request_irq failed for MSIX interrupt "
1608                                 "Error: %d\n", err);
1609                         goto free_queue_irqs;
1610                 }
1611         }
1612
1613         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1614         err = request_irq(adapter->msix_entries[vector].vector,
1615                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1616         if (err) {
1617                 DPRINTK(PROBE, ERR,
1618                         "request_irq for msix_lsc failed: %d\n", err);
1619                 goto free_queue_irqs;
1620         }
1621
1622         return 0;
1623
1624 free_queue_irqs:
1625         for (i = vector - 1; i >= 0; i--)
1626                 free_irq(adapter->msix_entries[--vector].vector,
1627                          adapter->q_vector[i]);
1628         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1629         pci_disable_msix(adapter->pdev);
1630         kfree(adapter->msix_entries);
1631         adapter->msix_entries = NULL;
1632 out:
1633         return err;
1634 }
1635
1636 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1637 {
1638         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1639         u8 current_itr;
1640         u32 new_itr = q_vector->eitr;
1641         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1642         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1643
1644         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1645                                             q_vector->tx_itr,
1646                                             tx_ring->total_packets,
1647                                             tx_ring->total_bytes);
1648         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1649                                             q_vector->rx_itr,
1650                                             rx_ring->total_packets,
1651                                             rx_ring->total_bytes);
1652
1653         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1654
1655         switch (current_itr) {
1656         /* counts and packets in update_itr are dependent on these numbers */
1657         case lowest_latency:
1658                 new_itr = 100000;
1659                 break;
1660         case low_latency:
1661                 new_itr = 20000; /* aka hwitr = ~200 */
1662                 break;
1663         case bulk_latency:
1664                 new_itr = 8000;
1665                 break;
1666         default:
1667                 break;
1668         }
1669
1670         if (new_itr != q_vector->eitr) {
1671                 /* do an exponential smoothing */
1672                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1673
1674                 /* save the algorithm value here, not the smoothed one */
1675                 q_vector->eitr = new_itr;
1676
1677                 ixgbe_write_eitr(q_vector);
1678         }
1679
1680         return;
1681 }
1682
1683 /**
1684  * ixgbe_irq_enable - Enable default interrupt generation settings
1685  * @adapter: board private structure
1686  **/
1687 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1688 {
1689         u32 mask;
1690
1691         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1692         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1693                 mask |= IXGBE_EIMS_GPI_SDP1;
1694         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1695                 mask |= IXGBE_EIMS_ECC;
1696                 mask |= IXGBE_EIMS_GPI_SDP1;
1697                 mask |= IXGBE_EIMS_GPI_SDP2;
1698         }
1699         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1700             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1701                 mask |= IXGBE_EIMS_FLOW_DIR;
1702
1703         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1704         ixgbe_irq_enable_queues(adapter, ~0);
1705         IXGBE_WRITE_FLUSH(&adapter->hw);
1706 }
1707
1708 /**
1709  * ixgbe_intr - legacy mode Interrupt Handler
1710  * @irq: interrupt number
1711  * @data: pointer to a network interface device structure
1712  **/
1713 static irqreturn_t ixgbe_intr(int irq, void *data)
1714 {
1715         struct net_device *netdev = data;
1716         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1717         struct ixgbe_hw *hw = &adapter->hw;
1718         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1719         u32 eicr;
1720
1721         /*
1722          * Workaround for silicon errata.  Mask the interrupts
1723          * before the read of EICR.
1724          */
1725         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1726
1727         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1728          * therefore no explict interrupt disable is necessary */
1729         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1730         if (!eicr) {
1731                 /* shared interrupt alert!
1732                  * make sure interrupts are enabled because the read will
1733                  * have disabled interrupts due to EIAM */
1734                 ixgbe_irq_enable(adapter);
1735                 return IRQ_NONE;        /* Not our interrupt */
1736         }
1737
1738         if (eicr & IXGBE_EICR_LSC)
1739                 ixgbe_check_lsc(adapter);
1740
1741         if (hw->mac.type == ixgbe_mac_82599EB)
1742                 ixgbe_check_sfp_event(adapter, eicr);
1743
1744         ixgbe_check_fan_failure(adapter, eicr);
1745
1746         if (napi_schedule_prep(&(q_vector->napi))) {
1747                 adapter->tx_ring[0].total_packets = 0;
1748                 adapter->tx_ring[0].total_bytes = 0;
1749                 adapter->rx_ring[0].total_packets = 0;
1750                 adapter->rx_ring[0].total_bytes = 0;
1751                 /* would disable interrupts here but EIAM disabled it */
1752                 __napi_schedule(&(q_vector->napi));
1753         }
1754
1755         return IRQ_HANDLED;
1756 }
1757
1758 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1759 {
1760         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1761
1762         for (i = 0; i < q_vectors; i++) {
1763                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1764                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1765                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1766                 q_vector->rxr_count = 0;
1767                 q_vector->txr_count = 0;
1768         }
1769 }
1770
1771 /**
1772  * ixgbe_request_irq - initialize interrupts
1773  * @adapter: board private structure
1774  *
1775  * Attempts to configure interrupts using the best available
1776  * capabilities of the hardware and kernel.
1777  **/
1778 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1779 {
1780         struct net_device *netdev = adapter->netdev;
1781         int err;
1782
1783         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1784                 err = ixgbe_request_msix_irqs(adapter);
1785         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1786                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1787                                   netdev->name, netdev);
1788         } else {
1789                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1790                                   netdev->name, netdev);
1791         }
1792
1793         if (err)
1794                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1795
1796         return err;
1797 }
1798
1799 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1800 {
1801         struct net_device *netdev = adapter->netdev;
1802
1803         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1804                 int i, q_vectors;
1805
1806                 q_vectors = adapter->num_msix_vectors;
1807
1808                 i = q_vectors - 1;
1809                 free_irq(adapter->msix_entries[i].vector, netdev);
1810
1811                 i--;
1812                 for (; i >= 0; i--) {
1813                         free_irq(adapter->msix_entries[i].vector,
1814                                  adapter->q_vector[i]);
1815                 }
1816
1817                 ixgbe_reset_q_vectors(adapter);
1818         } else {
1819                 free_irq(adapter->pdev->irq, netdev);
1820         }
1821 }
1822
1823 /**
1824  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1825  * @adapter: board private structure
1826  **/
1827 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1828 {
1829         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1830                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1831         } else {
1832                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1833                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1834                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1835         }
1836         IXGBE_WRITE_FLUSH(&adapter->hw);
1837         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1838                 int i;
1839                 for (i = 0; i < adapter->num_msix_vectors; i++)
1840                         synchronize_irq(adapter->msix_entries[i].vector);
1841         } else {
1842                 synchronize_irq(adapter->pdev->irq);
1843         }
1844 }
1845
1846 /**
1847  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1848  *
1849  **/
1850 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1851 {
1852         struct ixgbe_hw *hw = &adapter->hw;
1853
1854         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1855                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
1856
1857         ixgbe_set_ivar(adapter, 0, 0, 0);
1858         ixgbe_set_ivar(adapter, 1, 0, 0);
1859
1860         map_vector_to_rxq(adapter, 0, 0);
1861         map_vector_to_txq(adapter, 0, 0);
1862
1863         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1864 }
1865
1866 /**
1867  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1868  * @adapter: board private structure
1869  *
1870  * Configure the Tx unit of the MAC after a reset.
1871  **/
1872 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1873 {
1874         u64 tdba;
1875         struct ixgbe_hw *hw = &adapter->hw;
1876         u32 i, j, tdlen, txctrl;
1877
1878         /* Setup the HW Tx Head and Tail descriptor pointers */
1879         for (i = 0; i < adapter->num_tx_queues; i++) {
1880                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1881                 j = ring->reg_idx;
1882                 tdba = ring->dma;
1883                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1884                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1885                                 (tdba & DMA_BIT_MASK(32)));
1886                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1887                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1888                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1889                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1890                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1891                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1892                 /*
1893                  * Disable Tx Head Writeback RO bit, since this hoses
1894                  * bookkeeping if things aren't delivered in order.
1895                  */
1896                 switch (hw->mac.type) {
1897                 case ixgbe_mac_82598EB:
1898                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1899                         break;
1900                 case ixgbe_mac_82599EB:
1901                 default:
1902                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1903                         break;
1904                 }
1905                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1906                 switch (hw->mac.type) {
1907                 case ixgbe_mac_82598EB:
1908                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1909                         break;
1910                 case ixgbe_mac_82599EB:
1911                 default:
1912                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1913                         break;
1914                 }
1915         }
1916         if (hw->mac.type == ixgbe_mac_82599EB) {
1917                 /* We enable 8 traffic classes, DCB only */
1918                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1919                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1920                                         IXGBE_MTQC_8TC_8TQ));
1921         }
1922 }
1923
1924 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1925
1926 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1927                                    struct ixgbe_ring *rx_ring)
1928 {
1929         u32 srrctl;
1930         int index;
1931         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1932
1933         index = rx_ring->reg_idx;
1934         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1935                 unsigned long mask;
1936                 mask = (unsigned long) feature[RING_F_RSS].mask;
1937                 index = index & mask;
1938         }
1939         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1940
1941         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1942         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1943
1944         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1945                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1946
1947         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1948 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1949                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1950 #else
1951                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1952 #endif
1953                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1954         } else {
1955                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1956                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1957                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1958         }
1959
1960         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1961 }
1962
1963 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1964 {
1965         u32 mrqc = 0;
1966         int mask;
1967
1968         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1969                 return mrqc;
1970
1971         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1972 #ifdef CONFIG_IXGBE_DCB
1973                                  | IXGBE_FLAG_DCB_ENABLED
1974 #endif
1975                                 );
1976
1977         switch (mask) {
1978         case (IXGBE_FLAG_RSS_ENABLED):
1979                 mrqc = IXGBE_MRQC_RSSEN;
1980                 break;
1981 #ifdef CONFIG_IXGBE_DCB
1982         case (IXGBE_FLAG_DCB_ENABLED):
1983                 mrqc = IXGBE_MRQC_RT8TCEN;
1984                 break;
1985 #endif /* CONFIG_IXGBE_DCB */
1986         default:
1987                 break;
1988         }
1989
1990         return mrqc;
1991 }
1992
1993 /**
1994  * ixgbe_configure_rscctl - enable RSC for the indicated ring
1995  * @adapter:    address of board private structure
1996  * @index:      index of ring to set
1997  * @rx_buf_len: rx buffer length
1998  **/
1999 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
2000                                    int rx_buf_len)
2001 {
2002         struct ixgbe_ring *rx_ring;
2003         struct ixgbe_hw *hw = &adapter->hw;
2004         int j;
2005         u32 rscctrl;
2006
2007         rx_ring = &adapter->rx_ring[index];
2008         j = rx_ring->reg_idx;
2009         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2010         rscctrl |= IXGBE_RSCCTL_RSCEN;
2011         /*
2012          * we must limit the number of descriptors so that the
2013          * total size of max desc * buf_len is not greater
2014          * than 65535
2015          */
2016         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2017 #if (MAX_SKB_FRAGS > 16)
2018                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2019 #elif (MAX_SKB_FRAGS > 8)
2020                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2021 #elif (MAX_SKB_FRAGS > 4)
2022                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2023 #else
2024                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2025 #endif
2026         } else {
2027                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2028                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2029                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2030                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2031                 else
2032                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2033         }
2034         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2035 }
2036
2037 /**
2038  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2039  * @adapter: board private structure
2040  *
2041  * Configure the Rx unit of the MAC after a reset.
2042  **/
2043 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2044 {
2045         u64 rdba;
2046         struct ixgbe_hw *hw = &adapter->hw;
2047         struct ixgbe_ring *rx_ring;
2048         struct net_device *netdev = adapter->netdev;
2049         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2050         int i, j;
2051         u32 rdlen, rxctrl, rxcsum;
2052         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2053                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2054                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2055         u32 fctrl, hlreg0;
2056         u32 reta = 0, mrqc = 0;
2057         u32 rdrxctl;
2058         int rx_buf_len;
2059
2060         /* Decide whether to use packet split mode or not */
2061         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2062
2063         /* Set the RX buffer length according to the mode */
2064         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2065                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2066                 if (hw->mac.type == ixgbe_mac_82599EB) {
2067                         /* PSRTYPE must be initialized in 82599 */
2068                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2069                                       IXGBE_PSRTYPE_UDPHDR |
2070                                       IXGBE_PSRTYPE_IPV4HDR |
2071                                       IXGBE_PSRTYPE_IPV6HDR |
2072                                       IXGBE_PSRTYPE_L2HDR;
2073                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2074                 }
2075         } else {
2076                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2077                     (netdev->mtu <= ETH_DATA_LEN))
2078                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2079                 else
2080                         rx_buf_len = ALIGN(max_frame, 1024);
2081         }
2082
2083         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2084         fctrl |= IXGBE_FCTRL_BAM;
2085         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2086         fctrl |= IXGBE_FCTRL_PMCF;
2087         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2088
2089         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2090         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2091                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2092         else
2093                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2094 #ifdef IXGBE_FCOE
2095         if (netdev->features & NETIF_F_FCOE_MTU)
2096                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2097 #endif
2098         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2099
2100         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2101         /* disable receives while setting up the descriptors */
2102         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2103         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2104
2105         /*
2106          * Setup the HW Rx Head and Tail Descriptor Pointers and
2107          * the Base and Length of the Rx Descriptor Ring
2108          */
2109         for (i = 0; i < adapter->num_rx_queues; i++) {
2110                 rx_ring = &adapter->rx_ring[i];
2111                 rdba = rx_ring->dma;
2112                 j = rx_ring->reg_idx;
2113                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2114                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2115                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2116                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2117                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2118                 rx_ring->head = IXGBE_RDH(j);
2119                 rx_ring->tail = IXGBE_RDT(j);
2120                 rx_ring->rx_buf_len = rx_buf_len;
2121
2122                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2123                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2124                 else
2125                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2126
2127 #ifdef IXGBE_FCOE
2128                 if (netdev->features & NETIF_F_FCOE_MTU) {
2129                         struct ixgbe_ring_feature *f;
2130                         f = &adapter->ring_feature[RING_F_FCOE];
2131                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2132                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2133                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2134                                         rx_ring->rx_buf_len =
2135                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2136                         }
2137                 }
2138
2139 #endif /* IXGBE_FCOE */
2140                 ixgbe_configure_srrctl(adapter, rx_ring);
2141         }
2142
2143         if (hw->mac.type == ixgbe_mac_82598EB) {
2144                 /*
2145                  * For VMDq support of different descriptor types or
2146                  * buffer sizes through the use of multiple SRRCTL
2147                  * registers, RDRXCTL.MVMEN must be set to 1
2148                  *
2149                  * also, the manual doesn't mention it clearly but DCA hints
2150                  * will only use queue 0's tags unless this bit is set.  Side
2151                  * effects of setting this bit are only that SRRCTL must be
2152                  * fully programmed [0..15]
2153                  */
2154                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2155                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2156                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2157         }
2158
2159         /* Program MRQC for the distribution of queues */
2160         mrqc = ixgbe_setup_mrqc(adapter);
2161
2162         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2163                 /* Fill out redirection table */
2164                 for (i = 0, j = 0; i < 128; i++, j++) {
2165                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2166                                 j = 0;
2167                         /* reta = 4-byte sliding window of
2168                          * 0x00..(indices-1)(indices-1)00..etc. */
2169                         reta = (reta << 8) | (j * 0x11);
2170                         if ((i & 3) == 3)
2171                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2172                 }
2173
2174                 /* Fill out hash function seeds */
2175                 for (i = 0; i < 10; i++)
2176                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2177
2178                 if (hw->mac.type == ixgbe_mac_82598EB)
2179                         mrqc |= IXGBE_MRQC_RSSEN;
2180                     /* Perform hash on these packet types */
2181                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2182                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2183                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2184                       | IXGBE_MRQC_RSS_FIELD_IPV6
2185                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2186                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2187         }
2188         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2189
2190         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2191
2192         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2193             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2194                 /* Disable indicating checksum in descriptor, enables
2195                  * RSS hash */
2196                 rxcsum |= IXGBE_RXCSUM_PCSD;
2197         }
2198         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2199                 /* Enable IPv4 payload checksum for UDP fragments
2200                  * if PCSD is not set */
2201                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2202         }
2203
2204         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2205
2206         if (hw->mac.type == ixgbe_mac_82599EB) {
2207                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2208                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2209                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2210                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2211         }
2212
2213         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2214                 /* Enable 82599 HW-RSC */
2215                 for (i = 0; i < adapter->num_rx_queues; i++)
2216                         ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2217
2218                 /* Disable RSC for ACK packets */
2219                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2220                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2221         }
2222 }
2223
2224 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2225 {
2226         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2227         struct ixgbe_hw *hw = &adapter->hw;
2228
2229         /* add VID to filter table */
2230         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2231 }
2232
2233 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2234 {
2235         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2236         struct ixgbe_hw *hw = &adapter->hw;
2237
2238         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2239                 ixgbe_irq_disable(adapter);
2240
2241         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2242
2243         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2244                 ixgbe_irq_enable(adapter);
2245
2246         /* remove VID from filter table */
2247         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2248 }
2249
2250 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2251                                    struct vlan_group *grp)
2252 {
2253         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2254         u32 ctrl;
2255         int i, j;
2256
2257         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2258                 ixgbe_irq_disable(adapter);
2259         adapter->vlgrp = grp;
2260
2261         /*
2262          * For a DCB driver, always enable VLAN tag stripping so we can
2263          * still receive traffic from a DCB-enabled host even if we're
2264          * not in DCB mode.
2265          */
2266         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2267         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2268                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2269                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2270                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2271         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2272                 ctrl |= IXGBE_VLNCTRL_VFE;
2273                 /* enable VLAN tag insert/strip */
2274                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2275                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2276                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2277                 for (i = 0; i < adapter->num_rx_queues; i++) {
2278                         j = adapter->rx_ring[i].reg_idx;
2279                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2280                         ctrl |= IXGBE_RXDCTL_VME;
2281                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2282                 }
2283         }
2284         ixgbe_vlan_rx_add_vid(netdev, 0);
2285
2286         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2287                 ixgbe_irq_enable(adapter);
2288 }
2289
2290 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2291 {
2292         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2293
2294         if (adapter->vlgrp) {
2295                 u16 vid;
2296                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2297                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2298                                 continue;
2299                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2300                 }
2301         }
2302 }
2303
2304 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2305 {
2306         struct dev_mc_list *mc_ptr;
2307         u8 *addr = *mc_addr_ptr;
2308         *vmdq = 0;
2309
2310         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2311         if (mc_ptr->next)
2312                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2313         else
2314                 *mc_addr_ptr = NULL;
2315
2316         return addr;
2317 }
2318
2319 /**
2320  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2321  * @netdev: network interface device structure
2322  *
2323  * The set_rx_method entry point is called whenever the unicast/multicast
2324  * address list or the network interface flags are updated.  This routine is
2325  * responsible for configuring the hardware for proper unicast, multicast and
2326  * promiscuous mode.
2327  **/
2328 static void ixgbe_set_rx_mode(struct net_device *netdev)
2329 {
2330         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2331         struct ixgbe_hw *hw = &adapter->hw;
2332         u32 fctrl, vlnctrl;
2333         u8 *addr_list = NULL;
2334         int addr_count = 0;
2335
2336         /* Check for Promiscuous and All Multicast modes */
2337
2338         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2339         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2340
2341         if (netdev->flags & IFF_PROMISC) {
2342                 hw->addr_ctrl.user_set_promisc = 1;
2343                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2344                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2345         } else {
2346                 if (netdev->flags & IFF_ALLMULTI) {
2347                         fctrl |= IXGBE_FCTRL_MPE;
2348                         fctrl &= ~IXGBE_FCTRL_UPE;
2349                 } else {
2350                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2351                 }
2352                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2353                 hw->addr_ctrl.user_set_promisc = 0;
2354         }
2355
2356         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2357         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2358
2359         /* reprogram secondary unicast list */
2360         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2361
2362         /* reprogram multicast list */
2363         addr_count = netdev->mc_count;
2364         if (addr_count)
2365                 addr_list = netdev->mc_list->dmi_addr;
2366         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2367                                         ixgbe_addr_list_itr);
2368 }
2369
2370 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2371 {
2372         int q_idx;
2373         struct ixgbe_q_vector *q_vector;
2374         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2375
2376         /* legacy and MSI only use one vector */
2377         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2378                 q_vectors = 1;
2379
2380         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2381                 struct napi_struct *napi;
2382                 q_vector = adapter->q_vector[q_idx];
2383                 napi = &q_vector->napi;
2384                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2385                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2386                                 if (q_vector->txr_count == 1)
2387                                         napi->poll = &ixgbe_clean_txonly;
2388                                 else if (q_vector->rxr_count == 1)
2389                                         napi->poll = &ixgbe_clean_rxonly;
2390                         }
2391                 }
2392
2393                 napi_enable(napi);
2394         }
2395 }
2396
2397 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2398 {
2399         int q_idx;
2400         struct ixgbe_q_vector *q_vector;
2401         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2402
2403         /* legacy and MSI only use one vector */
2404         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2405                 q_vectors = 1;
2406
2407         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2408                 q_vector = adapter->q_vector[q_idx];
2409                 napi_disable(&q_vector->napi);
2410         }
2411 }
2412
2413 #ifdef CONFIG_IXGBE_DCB
2414 /*
2415  * ixgbe_configure_dcb - Configure DCB hardware
2416  * @adapter: ixgbe adapter struct
2417  *
2418  * This is called by the driver on open to configure the DCB hardware.
2419  * This is also called by the gennetlink interface when reconfiguring
2420  * the DCB state.
2421  */
2422 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2423 {
2424         struct ixgbe_hw *hw = &adapter->hw;
2425         u32 txdctl, vlnctrl;
2426         int i, j;
2427
2428         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2429         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2430         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2431
2432         /* reconfigure the hardware */
2433         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2434
2435         for (i = 0; i < adapter->num_tx_queues; i++) {
2436                 j = adapter->tx_ring[i].reg_idx;
2437                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2438                 /* PThresh workaround for Tx hang with DFP enabled. */
2439                 txdctl |= 32;
2440                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2441         }
2442         /* Enable VLAN tag insert/strip */
2443         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2444         if (hw->mac.type == ixgbe_mac_82598EB) {
2445                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2446                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2447                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2448         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2449                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2450                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2451                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2452                 for (i = 0; i < adapter->num_rx_queues; i++) {
2453                         j = adapter->rx_ring[i].reg_idx;
2454                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2455                         vlnctrl |= IXGBE_RXDCTL_VME;
2456                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2457                 }
2458         }
2459         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2460 }
2461
2462 #endif
2463 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2464 {
2465         struct net_device *netdev = adapter->netdev;
2466         struct ixgbe_hw *hw = &adapter->hw;
2467         int i;
2468
2469         ixgbe_set_rx_mode(netdev);
2470
2471         ixgbe_restore_vlan(adapter);
2472 #ifdef CONFIG_IXGBE_DCB
2473         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2474                 if (hw->mac.type == ixgbe_mac_82598EB)
2475                         netif_set_gso_max_size(netdev, 32768);
2476                 else
2477                         netif_set_gso_max_size(netdev, 65536);
2478                 ixgbe_configure_dcb(adapter);
2479         } else {
2480                 netif_set_gso_max_size(netdev, 65536);
2481         }
2482 #else
2483         netif_set_gso_max_size(netdev, 65536);
2484 #endif
2485
2486 #ifdef IXGBE_FCOE
2487         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2488                 ixgbe_configure_fcoe(adapter);
2489
2490 #endif /* IXGBE_FCOE */
2491         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2492                 for (i = 0; i < adapter->num_tx_queues; i++)
2493                         adapter->tx_ring[i].atr_sample_rate =
2494                                                        adapter->atr_sample_rate;
2495                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2496         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2497                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2498         }
2499
2500         ixgbe_configure_tx(adapter);
2501         ixgbe_configure_rx(adapter);
2502         for (i = 0; i < adapter->num_rx_queues; i++)
2503                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2504                                        (adapter->rx_ring[i].count - 1));
2505 }
2506
2507 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2508 {
2509         switch (hw->phy.type) {
2510         case ixgbe_phy_sfp_avago:
2511         case ixgbe_phy_sfp_ftl:
2512         case ixgbe_phy_sfp_intel:
2513         case ixgbe_phy_sfp_unknown:
2514         case ixgbe_phy_tw_tyco:
2515         case ixgbe_phy_tw_unknown:
2516                 return true;
2517         default:
2518                 return false;
2519         }
2520 }
2521
2522 /**
2523  * ixgbe_sfp_link_config - set up SFP+ link
2524  * @adapter: pointer to private adapter struct
2525  **/
2526 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2527 {
2528         struct ixgbe_hw *hw = &adapter->hw;
2529
2530                 if (hw->phy.multispeed_fiber) {
2531                         /*
2532                          * In multispeed fiber setups, the device may not have
2533                          * had a physical connection when the driver loaded.
2534                          * If that's the case, the initial link configuration
2535                          * couldn't get the MAC into 10G or 1G mode, so we'll
2536                          * never have a link status change interrupt fire.
2537                          * We need to try and force an autonegotiation
2538                          * session, then bring up link.
2539                          */
2540                         hw->mac.ops.setup_sfp(hw);
2541                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2542                                 schedule_work(&adapter->multispeed_fiber_task);
2543                 } else {
2544                         /*
2545                          * Direct Attach Cu and non-multispeed fiber modules
2546                          * still need to be configured properly prior to
2547                          * attempting link.
2548                          */
2549                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2550                                 schedule_work(&adapter->sfp_config_module_task);
2551                 }
2552 }
2553
2554 /**
2555  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2556  * @hw: pointer to private hardware struct
2557  *
2558  * Returns 0 on success, negative on failure
2559  **/
2560 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2561 {
2562         u32 autoneg;
2563         bool negotiation, link_up = false;
2564         u32 ret = IXGBE_ERR_LINK_SETUP;
2565
2566         if (hw->mac.ops.check_link)
2567                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2568
2569         if (ret)
2570                 goto link_cfg_out;
2571
2572         if (hw->mac.ops.get_link_capabilities)
2573                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2574         if (ret)
2575                 goto link_cfg_out;
2576
2577         if (hw->mac.ops.setup_link)
2578                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2579 link_cfg_out:
2580         return ret;
2581 }
2582
2583 #define IXGBE_MAX_RX_DESC_POLL 10
2584 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2585                                               int rxr)
2586 {
2587         int j = adapter->rx_ring[rxr].reg_idx;
2588         int k;
2589
2590         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2591                 if (IXGBE_READ_REG(&adapter->hw,
2592                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2593                         break;
2594                 else
2595                         msleep(1);
2596         }
2597         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2598                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2599                         "not set within the polling period\n", rxr);
2600         }
2601         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2602                               (adapter->rx_ring[rxr].count - 1));
2603 }
2604
2605 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2606 {
2607         struct net_device *netdev = adapter->netdev;
2608         struct ixgbe_hw *hw = &adapter->hw;
2609         int i, j = 0;
2610         int num_rx_rings = adapter->num_rx_queues;
2611         int err;
2612         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2613         u32 txdctl, rxdctl, mhadd;
2614         u32 dmatxctl;
2615         u32 gpie;
2616
2617         ixgbe_get_hw_control(adapter);
2618
2619         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2620             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2621                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2622                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2623                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2624                 } else {
2625                         /* MSI only */
2626                         gpie = 0;
2627                 }
2628                 /* XXX: to interrupt immediately for EICS writes, enable this */
2629                 /* gpie |= IXGBE_GPIE_EIMEN; */
2630                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2631         }
2632
2633         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2634                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2635                  * specifically only auto mask tx and rx interrupts */
2636                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2637         }
2638
2639         /* Enable fan failure interrupt if media type is copper */
2640         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2641                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2642                 gpie |= IXGBE_SDP1_GPIEN;
2643                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2644         }
2645
2646         if (hw->mac.type == ixgbe_mac_82599EB) {
2647                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2648                 gpie |= IXGBE_SDP1_GPIEN;
2649                 gpie |= IXGBE_SDP2_GPIEN;
2650                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2651         }
2652
2653 #ifdef IXGBE_FCOE
2654         /* adjust max frame to be able to do baby jumbo for FCoE */
2655         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2656             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2657                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2658
2659 #endif /* IXGBE_FCOE */
2660         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2661         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2662                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2663                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2664
2665                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2666         }
2667
2668         for (i = 0; i < adapter->num_tx_queues; i++) {
2669                 j = adapter->tx_ring[i].reg_idx;
2670                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2671                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2672                 txdctl |= (8 << 16);
2673                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2674         }
2675
2676         if (hw->mac.type == ixgbe_mac_82599EB) {
2677                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2678                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2679                 dmatxctl |= IXGBE_DMATXCTL_TE;
2680                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2681         }
2682         for (i = 0; i < adapter->num_tx_queues; i++) {
2683                 j = adapter->tx_ring[i].reg_idx;
2684                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2685                 txdctl |= IXGBE_TXDCTL_ENABLE;
2686                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2687         }
2688
2689         for (i = 0; i < num_rx_rings; i++) {
2690                 j = adapter->rx_ring[i].reg_idx;
2691                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2692                 /* enable PTHRESH=32 descriptors (half the internal cache)
2693                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2694                  * this also removes a pesky rx_no_buffer_count increment */
2695                 rxdctl |= 0x0020;
2696                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2697                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2698                 if (hw->mac.type == ixgbe_mac_82599EB)
2699                         ixgbe_rx_desc_queue_enable(adapter, i);
2700         }
2701         /* enable all receives */
2702         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2703         if (hw->mac.type == ixgbe_mac_82598EB)
2704                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2705         else
2706                 rxdctl |= IXGBE_RXCTRL_RXEN;
2707         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2708
2709         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2710                 ixgbe_configure_msix(adapter);
2711         else
2712                 ixgbe_configure_msi_and_legacy(adapter);
2713
2714         clear_bit(__IXGBE_DOWN, &adapter->state);
2715         ixgbe_napi_enable_all(adapter);
2716
2717         /* clear any pending interrupts, may auto mask */
2718         IXGBE_READ_REG(hw, IXGBE_EICR);
2719
2720         ixgbe_irq_enable(adapter);
2721
2722         /*
2723          * If this adapter has a fan, check to see if we had a failure
2724          * before we enabled the interrupt.
2725          */
2726         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2727                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2728                 if (esdp & IXGBE_ESDP_SDP1)
2729                         DPRINTK(DRV, CRIT,
2730                                 "Fan has stopped, replace the adapter\n");
2731         }
2732
2733         /*
2734          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2735          * arrived before interrupts were enabled but after probe.  Such
2736          * devices wouldn't have their type identified yet. We need to
2737          * kick off the SFP+ module setup first, then try to bring up link.
2738          * If we're not hot-pluggable SFP+, we just need to configure link
2739          * and bring it up.
2740          */
2741         if (hw->phy.type == ixgbe_phy_unknown) {
2742                 err = hw->phy.ops.identify(hw);
2743                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2744                         /*
2745                          * Take the device down and schedule the sfp tasklet
2746                          * which will unregister_netdev and log it.
2747                          */
2748                         ixgbe_down(adapter);
2749                         schedule_work(&adapter->sfp_config_module_task);
2750                         return err;
2751                 }
2752         }
2753
2754         if (ixgbe_is_sfp(hw)) {
2755                 ixgbe_sfp_link_config(adapter);
2756         } else {
2757                 err = ixgbe_non_sfp_link_config(hw);
2758                 if (err)
2759                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2760         }
2761
2762         for (i = 0; i < adapter->num_tx_queues; i++)
2763                 set_bit(__IXGBE_FDIR_INIT_DONE,
2764                         &(adapter->tx_ring[i].reinit_state));
2765
2766         /* enable transmits */
2767         netif_tx_start_all_queues(netdev);
2768
2769         /* bring the link up in the watchdog, this could race with our first
2770          * link up interrupt but shouldn't be a problem */
2771         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2772         adapter->link_check_timeout = jiffies;
2773         mod_timer(&adapter->watchdog_timer, jiffies);
2774         return 0;
2775 }
2776
2777 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2778 {
2779         WARN_ON(in_interrupt());
2780         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2781                 msleep(1);
2782         ixgbe_down(adapter);
2783         ixgbe_up(adapter);
2784         clear_bit(__IXGBE_RESETTING, &adapter->state);
2785 }
2786
2787 int ixgbe_up(struct ixgbe_adapter *adapter)
2788 {
2789         /* hardware has been reset, we need to reload some things */
2790         ixgbe_configure(adapter);
2791
2792         return ixgbe_up_complete(adapter);
2793 }
2794
2795 void ixgbe_reset(struct ixgbe_adapter *adapter)
2796 {
2797         struct ixgbe_hw *hw = &adapter->hw;
2798         int err;
2799
2800         err = hw->mac.ops.init_hw(hw);
2801         switch (err) {
2802         case 0:
2803         case IXGBE_ERR_SFP_NOT_PRESENT:
2804                 break;
2805         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2806                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2807                 break;
2808         case IXGBE_ERR_EEPROM_VERSION:
2809                 /* We are running on a pre-production device, log a warning */
2810                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2811                          "adapter/LOM.  Please be aware there may be issues "
2812                          "associated with your hardware.  If you are "
2813                          "experiencing problems please contact your Intel or "
2814                          "hardware representative who provided you with this "
2815                          "hardware.\n");
2816                 break;
2817         default:
2818                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2819         }
2820
2821         /* reprogram the RAR[0] in case user changed it. */
2822         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2823 }
2824
2825 /**
2826  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2827  * @adapter: board private structure
2828  * @rx_ring: ring to free buffers from
2829  **/
2830 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2831                                 struct ixgbe_ring *rx_ring)
2832 {
2833         struct pci_dev *pdev = adapter->pdev;
2834         unsigned long size;
2835         unsigned int i;
2836
2837         /* Free all the Rx ring sk_buffs */
2838
2839         for (i = 0; i < rx_ring->count; i++) {
2840                 struct ixgbe_rx_buffer *rx_buffer_info;
2841
2842                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2843                 if (rx_buffer_info->dma) {
2844                         pci_unmap_single(pdev, rx_buffer_info->dma,
2845                                          rx_ring->rx_buf_len,
2846                                          PCI_DMA_FROMDEVICE);
2847                         rx_buffer_info->dma = 0;
2848                 }
2849                 if (rx_buffer_info->skb) {
2850                         struct sk_buff *skb = rx_buffer_info->skb;
2851                         rx_buffer_info->skb = NULL;
2852                         do {
2853                                 struct sk_buff *this = skb;
2854                                 skb = skb->prev;
2855                                 dev_kfree_skb(this);
2856                         } while (skb);
2857                 }
2858                 if (!rx_buffer_info->page)
2859                         continue;
2860                 if (rx_buffer_info->page_dma) {
2861                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2862                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2863                         rx_buffer_info->page_dma = 0;
2864                 }
2865                 put_page(rx_buffer_info->page);
2866                 rx_buffer_info->page = NULL;
2867                 rx_buffer_info->page_offset = 0;
2868         }
2869
2870         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2871         memset(rx_ring->rx_buffer_info, 0, size);
2872
2873         /* Zero out the descriptor ring */
2874         memset(rx_ring->desc, 0, rx_ring->size);
2875
2876         rx_ring->next_to_clean = 0;
2877         rx_ring->next_to_use = 0;
2878
2879         if (rx_ring->head)
2880                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2881         if (rx_ring->tail)
2882                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2883 }
2884
2885 /**
2886  * ixgbe_clean_tx_ring - Free Tx Buffers
2887  * @adapter: board private structure
2888  * @tx_ring: ring to be cleaned
2889  **/
2890 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2891                                 struct ixgbe_ring *tx_ring)
2892 {
2893         struct ixgbe_tx_buffer *tx_buffer_info;
2894         unsigned long size;
2895         unsigned int i;
2896
2897         /* Free all the Tx ring sk_buffs */
2898
2899         for (i = 0; i < tx_ring->count; i++) {
2900                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2901                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2902         }
2903
2904         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2905         memset(tx_ring->tx_buffer_info, 0, size);
2906
2907         /* Zero out the descriptor ring */
2908         memset(tx_ring->desc, 0, tx_ring->size);
2909
2910         tx_ring->next_to_use = 0;
2911         tx_ring->next_to_clean = 0;
2912
2913         if (tx_ring->head)
2914                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2915         if (tx_ring->tail)
2916                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2917 }
2918
2919 /**
2920  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2921  * @adapter: board private structure
2922  **/
2923 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2924 {
2925         int i;
2926
2927         for (i = 0; i < adapter->num_rx_queues; i++)
2928                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2929 }
2930
2931 /**
2932  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2933  * @adapter: board private structure
2934  **/
2935 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2936 {
2937         int i;
2938
2939         for (i = 0; i < adapter->num_tx_queues; i++)
2940                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2941 }
2942
2943 void ixgbe_down(struct ixgbe_adapter *adapter)
2944 {
2945         struct net_device *netdev = adapter->netdev;
2946         struct ixgbe_hw *hw = &adapter->hw;
2947         u32 rxctrl;
2948         u32 txdctl;
2949         int i, j;
2950
2951         /* signal that we are down to the interrupt handler */
2952         set_bit(__IXGBE_DOWN, &adapter->state);
2953
2954         /* disable receives */
2955         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2956         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2957
2958         netif_tx_disable(netdev);
2959
2960         IXGBE_WRITE_FLUSH(hw);
2961         msleep(10);
2962
2963         netif_tx_stop_all_queues(netdev);
2964
2965         ixgbe_irq_disable(adapter);
2966
2967         ixgbe_napi_disable_all(adapter);
2968
2969         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2970         del_timer_sync(&adapter->sfp_timer);
2971         del_timer_sync(&adapter->watchdog_timer);
2972         cancel_work_sync(&adapter->watchdog_task);
2973
2974         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2975             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2976                 cancel_work_sync(&adapter->fdir_reinit_task);
2977
2978         /* disable transmits in the hardware now that interrupts are off */
2979         for (i = 0; i < adapter->num_tx_queues; i++) {
2980                 j = adapter->tx_ring[i].reg_idx;
2981                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2982                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2983                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2984         }
2985         /* Disable the Tx DMA engine on 82599 */
2986         if (hw->mac.type == ixgbe_mac_82599EB)
2987                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2988                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2989                                  ~IXGBE_DMATXCTL_TE));
2990
2991         netif_carrier_off(netdev);
2992
2993         if (!pci_channel_offline(adapter->pdev))
2994                 ixgbe_reset(adapter);
2995         ixgbe_clean_all_tx_rings(adapter);
2996         ixgbe_clean_all_rx_rings(adapter);
2997
2998 #ifdef CONFIG_IXGBE_DCA
2999         /* since we reset the hardware DCA settings were cleared */
3000         ixgbe_setup_dca(adapter);
3001 #endif
3002 }
3003
3004 /**
3005  * ixgbe_poll - NAPI Rx polling callback
3006  * @napi: structure for representing this polling device
3007  * @budget: how many packets driver is allowed to clean
3008  *
3009  * This function is used for legacy and MSI, NAPI mode
3010  **/
3011 static int ixgbe_poll(struct napi_struct *napi, int budget)
3012 {
3013         struct ixgbe_q_vector *q_vector =
3014                                 container_of(napi, struct ixgbe_q_vector, napi);
3015         struct ixgbe_adapter *adapter = q_vector->adapter;
3016         int tx_clean_complete, work_done = 0;
3017
3018 #ifdef CONFIG_IXGBE_DCA
3019         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3020                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3021                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3022         }
3023 #endif
3024
3025         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
3026         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
3027
3028         if (!tx_clean_complete)
3029                 work_done = budget;
3030
3031         /* If budget not fully consumed, exit the polling mode */
3032         if (work_done < budget) {
3033                 napi_complete(napi);
3034                 if (adapter->rx_itr_setting & 1)
3035                         ixgbe_set_itr(adapter);
3036                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3037                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3038         }
3039         return work_done;
3040 }
3041
3042 /**
3043  * ixgbe_tx_timeout - Respond to a Tx Hang
3044  * @netdev: network interface device structure
3045  **/
3046 static void ixgbe_tx_timeout(struct net_device *netdev)
3047 {
3048         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3049
3050         /* Do the reset outside of interrupt context */
3051         schedule_work(&adapter->reset_task);
3052 }
3053
3054 static void ixgbe_reset_task(struct work_struct *work)
3055 {
3056         struct ixgbe_adapter *adapter;
3057         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3058
3059         /* If we're already down or resetting, just bail */
3060         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3061             test_bit(__IXGBE_RESETTING, &adapter->state))
3062                 return;
3063
3064         adapter->tx_timeout_count++;
3065
3066         ixgbe_reinit_locked(adapter);
3067 }
3068
3069 #ifdef CONFIG_IXGBE_DCB
3070 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3071 {
3072         bool ret = false;
3073         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3074
3075         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3076                 return ret;
3077
3078         f->mask = 0x7 << 3;
3079         adapter->num_rx_queues = f->indices;
3080         adapter->num_tx_queues = f->indices;
3081         ret = true;
3082
3083         return ret;
3084 }
3085 #endif
3086
3087 /**
3088  * ixgbe_set_rss_queues: Allocate queues for RSS
3089  * @adapter: board private structure to initialize
3090  *
3091  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3092  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3093  *
3094  **/
3095 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3096 {
3097         bool ret = false;
3098         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3099
3100         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3101                 f->mask = 0xF;
3102                 adapter->num_rx_queues = f->indices;
3103                 adapter->num_tx_queues = f->indices;
3104                 ret = true;
3105         } else {
3106                 ret = false;
3107         }
3108
3109         return ret;
3110 }
3111
3112 /**
3113  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3114  * @adapter: board private structure to initialize
3115  *
3116  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3117  * to the original CPU that initiated the Tx session.  This runs in addition
3118  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3119  * Rx load across CPUs using RSS.
3120  *
3121  **/
3122 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3123 {
3124         bool ret = false;
3125         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3126
3127         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3128         f_fdir->mask = 0;
3129
3130         /* Flow Director must have RSS enabled */
3131         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3132             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3133              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3134                 adapter->num_tx_queues = f_fdir->indices;
3135                 adapter->num_rx_queues = f_fdir->indices;
3136                 ret = true;
3137         } else {
3138                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3139                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3140         }
3141         return ret;
3142 }
3143
3144 #ifdef IXGBE_FCOE
3145 /**
3146  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3147  * @adapter: board private structure to initialize
3148  *
3149  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3150  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3151  * rx queues out of the max number of rx queues, instead, it is used as the
3152  * index of the first rx queue used by FCoE.
3153  *
3154  **/
3155 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3156 {
3157         bool ret = false;
3158         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3159
3160         f->indices = min((int)num_online_cpus(), f->indices);
3161         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3162                 adapter->num_rx_queues = 1;
3163                 adapter->num_tx_queues = 1;
3164 #ifdef CONFIG_IXGBE_DCB
3165                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3166                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3167                         ixgbe_set_dcb_queues(adapter);
3168                 }
3169 #endif
3170                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3171                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3172                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3173                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3174                                 ixgbe_set_fdir_queues(adapter);
3175                         else
3176                                 ixgbe_set_rss_queues(adapter);
3177                 }
3178                 /* adding FCoE rx rings to the end */
3179                 f->mask = adapter->num_rx_queues;
3180                 adapter->num_rx_queues += f->indices;
3181                 adapter->num_tx_queues += f->indices;
3182
3183                 ret = true;
3184         }
3185
3186         return ret;
3187 }
3188
3189 #endif /* IXGBE_FCOE */
3190 /*
3191  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3192  * @adapter: board private structure to initialize
3193  *
3194  * This is the top level queue allocation routine.  The order here is very
3195  * important, starting with the "most" number of features turned on at once,
3196  * and ending with the smallest set of features.  This way large combinations
3197  * can be allocated if they're turned on, and smaller combinations are the
3198  * fallthrough conditions.
3199  *
3200  **/
3201 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3202 {
3203 #ifdef IXGBE_FCOE
3204         if (ixgbe_set_fcoe_queues(adapter))
3205                 goto done;
3206
3207 #endif /* IXGBE_FCOE */
3208 #ifdef CONFIG_IXGBE_DCB
3209         if (ixgbe_set_dcb_queues(adapter))
3210                 goto done;
3211
3212 #endif
3213         if (ixgbe_set_fdir_queues(adapter))
3214                 goto done;
3215
3216         if (ixgbe_set_rss_queues(adapter))
3217                 goto done;
3218
3219         /* fallback to base case */
3220         adapter->num_rx_queues = 1;
3221         adapter->num_tx_queues = 1;
3222
3223 done:
3224         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3225         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3226 }
3227
3228 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3229                                        int vectors)
3230 {
3231         int err, vector_threshold;
3232
3233         /* We'll want at least 3 (vector_threshold):
3234          * 1) TxQ[0] Cleanup
3235          * 2) RxQ[0] Cleanup
3236          * 3) Other (Link Status Change, etc.)
3237          * 4) TCP Timer (optional)
3238          */
3239         vector_threshold = MIN_MSIX_COUNT;
3240
3241         /* The more we get, the more we will assign to Tx/Rx Cleanup
3242          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3243          * Right now, we simply care about how many we'll get; we'll
3244          * set them up later while requesting irq's.
3245          */
3246         while (vectors >= vector_threshold) {
3247                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3248                                       vectors);
3249                 if (!err) /* Success in acquiring all requested vectors. */
3250                         break;
3251                 else if (err < 0)
3252                         vectors = 0; /* Nasty failure, quit now */
3253                 else /* err == number of vectors we should try again with */
3254                         vectors = err;
3255         }
3256
3257         if (vectors < vector_threshold) {
3258                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3259                  * This just means we'll go with either a single MSI
3260                  * vector or fall back to legacy interrupts.
3261                  */
3262                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3263                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3264                 kfree(adapter->msix_entries);
3265                 adapter->msix_entries = NULL;
3266         } else {
3267                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3268                 /*
3269                  * Adjust for only the vectors we'll use, which is minimum
3270                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3271                  * vectors we were allocated.
3272                  */
3273                 adapter->num_msix_vectors = min(vectors,
3274                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3275         }
3276 }
3277
3278 /**
3279  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3280  * @adapter: board private structure to initialize
3281  *
3282  * Cache the descriptor ring offsets for RSS to the assigned rings.
3283  *
3284  **/
3285 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3286 {
3287         int i;
3288         bool ret = false;
3289
3290         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3291                 for (i = 0; i < adapter->num_rx_queues; i++)
3292                         adapter->rx_ring[i].reg_idx = i;
3293                 for (i = 0; i < adapter->num_tx_queues; i++)
3294                         adapter->tx_ring[i].reg_idx = i;
3295                 ret = true;
3296         } else {
3297                 ret = false;
3298         }
3299
3300         return ret;
3301 }
3302
3303 #ifdef CONFIG_IXGBE_DCB
3304 /**
3305  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3306  * @adapter: board private structure to initialize
3307  *
3308  * Cache the descriptor ring offsets for DCB to the assigned rings.
3309  *
3310  **/
3311 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3312 {
3313         int i;
3314         bool ret = false;
3315         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3316
3317         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3318                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3319                         /* the number of queues is assumed to be symmetric */
3320                         for (i = 0; i < dcb_i; i++) {
3321                                 adapter->rx_ring[i].reg_idx = i << 3;
3322                                 adapter->tx_ring[i].reg_idx = i << 2;
3323                         }
3324                         ret = true;
3325                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3326                         if (dcb_i == 8) {
3327                                 /*
3328                                  * Tx TC0 starts at: descriptor queue 0
3329                                  * Tx TC1 starts at: descriptor queue 32
3330                                  * Tx TC2 starts at: descriptor queue 64
3331                                  * Tx TC3 starts at: descriptor queue 80
3332                                  * Tx TC4 starts at: descriptor queue 96
3333                                  * Tx TC5 starts at: descriptor queue 104
3334                                  * Tx TC6 starts at: descriptor queue 112
3335                                  * Tx TC7 starts at: descriptor queue 120
3336                                  *
3337                                  * Rx TC0-TC7 are offset by 16 queues each
3338                                  */
3339                                 for (i = 0; i < 3; i++) {
3340                                         adapter->tx_ring[i].reg_idx = i << 5;
3341                                         adapter->rx_ring[i].reg_idx = i << 4;
3342                                 }
3343                                 for ( ; i < 5; i++) {
3344                                         adapter->tx_ring[i].reg_idx =
3345                                                                  ((i + 2) << 4);
3346                                         adapter->rx_ring[i].reg_idx = i << 4;
3347                                 }
3348                                 for ( ; i < dcb_i; i++) {
3349                                         adapter->tx_ring[i].reg_idx =
3350                                                                  ((i + 8) << 3);
3351                                         adapter->rx_ring[i].reg_idx = i << 4;
3352                                 }
3353
3354                                 ret = true;
3355                         } else if (dcb_i == 4) {
3356                                 /*
3357                                  * Tx TC0 starts at: descriptor queue 0
3358                                  * Tx TC1 starts at: descriptor queue 64
3359                                  * Tx TC2 starts at: descriptor queue 96
3360                                  * Tx TC3 starts at: descriptor queue 112
3361                                  *
3362                                  * Rx TC0-TC3 are offset by 32 queues each
3363                                  */
3364                                 adapter->tx_ring[0].reg_idx = 0;
3365                                 adapter->tx_ring[1].reg_idx = 64;
3366                                 adapter->tx_ring[2].reg_idx = 96;
3367                                 adapter->tx_ring[3].reg_idx = 112;
3368                                 for (i = 0 ; i < dcb_i; i++)
3369                                         adapter->rx_ring[i].reg_idx = i << 5;
3370
3371                                 ret = true;
3372                         } else {
3373                                 ret = false;
3374                         }
3375                 } else {
3376                         ret = false;
3377                 }
3378         } else {
3379                 ret = false;
3380         }
3381
3382         return ret;
3383 }
3384 #endif
3385
3386 /**
3387  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3388  * @adapter: board private structure to initialize
3389  *
3390  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3391  *
3392  **/
3393 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3394 {
3395         int i;
3396         bool ret = false;
3397
3398         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3399             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3400              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3401                 for (i = 0; i < adapter->num_rx_queues; i++)
3402                         adapter->rx_ring[i].reg_idx = i;
3403                 for (i = 0; i < adapter->num_tx_queues; i++)
3404                         adapter->tx_ring[i].reg_idx = i;
3405                 ret = true;
3406         }
3407
3408         return ret;
3409 }
3410
3411 #ifdef IXGBE_FCOE
3412 /**
3413  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3414  * @adapter: board private structure to initialize
3415  *
3416  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3417  *
3418  */
3419 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3420 {
3421         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3422         bool ret = false;
3423         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3424
3425         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3426 #ifdef CONFIG_IXGBE_DCB
3427                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3428                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3429
3430                         ixgbe_cache_ring_dcb(adapter);
3431                         /* find out queues in TC for FCoE */
3432                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3433                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3434                         /*
3435                          * In 82599, the number of Tx queues for each traffic
3436                          * class for both 8-TC and 4-TC modes are:
3437                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3438                          * 8 TCs:  32  32  16  16   8   8   8   8
3439                          * 4 TCs:  64  64  32  32
3440                          * We have max 8 queues for FCoE, where 8 the is
3441                          * FCoE redirection table size. If TC for FCoE is
3442                          * less than or equal to TC3, we have enough queues
3443                          * to add max of 8 queues for FCoE, so we start FCoE
3444                          * tx descriptor from the next one, i.e., reg_idx + 1.
3445                          * If TC for FCoE is above TC3, implying 8 TC mode,
3446                          * and we need 8 for FCoE, we have to take all queues
3447                          * in that traffic class for FCoE.
3448                          */
3449                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3450                                 fcoe_tx_i--;
3451                 }
3452 #endif /* CONFIG_IXGBE_DCB */
3453                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3454                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3455                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3456                                 ixgbe_cache_ring_fdir(adapter);
3457                         else
3458                                 ixgbe_cache_ring_rss(adapter);
3459
3460                         fcoe_rx_i = f->mask;
3461                         fcoe_tx_i = f->mask;
3462                 }
3463                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3464                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3465                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3466                 }
3467                 ret = true;
3468         }
3469         return ret;
3470 }
3471
3472 #endif /* IXGBE_FCOE */
3473 /**
3474  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3475  * @adapter: board private structure to initialize
3476  *
3477  * Once we know the feature-set enabled for the device, we'll cache
3478  * the register offset the descriptor ring is assigned to.
3479  *
3480  * Note, the order the various feature calls is important.  It must start with
3481  * the "most" features enabled at the same time, then trickle down to the
3482  * least amount of features turned on at once.
3483  **/
3484 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3485 {
3486         /* start with default case */
3487         adapter->rx_ring[0].reg_idx = 0;
3488         adapter->tx_ring[0].reg_idx = 0;
3489
3490 #ifdef IXGBE_FCOE
3491         if (ixgbe_cache_ring_fcoe(adapter))
3492                 return;
3493
3494 #endif /* IXGBE_FCOE */
3495 #ifdef CONFIG_IXGBE_DCB
3496         if (ixgbe_cache_ring_dcb(adapter))
3497                 return;
3498
3499 #endif
3500         if (ixgbe_cache_ring_fdir(adapter))
3501                 return;
3502
3503         if (ixgbe_cache_ring_rss(adapter))
3504                 return;
3505 }
3506
3507 /**
3508  * ixgbe_alloc_queues - Allocate memory for all rings
3509  * @adapter: board private structure to initialize
3510  *
3511  * We allocate one ring per queue at run-time since we don't know the
3512  * number of queues at compile-time.  The polling_netdev array is
3513  * intended for Multiqueue, but should work fine with a single queue.
3514  **/
3515 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3516 {
3517         int i;
3518
3519         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3520                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3521         if (!adapter->tx_ring)
3522                 goto err_tx_ring_allocation;
3523
3524         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3525                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3526         if (!adapter->rx_ring)
3527                 goto err_rx_ring_allocation;
3528
3529         for (i = 0; i < adapter->num_tx_queues; i++) {
3530                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3531                 adapter->tx_ring[i].queue_index = i;
3532         }
3533
3534         for (i = 0; i < adapter->num_rx_queues; i++) {
3535                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3536                 adapter->rx_ring[i].queue_index = i;
3537         }
3538
3539         ixgbe_cache_ring_register(adapter);
3540
3541         return 0;
3542
3543 err_rx_ring_allocation:
3544         kfree(adapter->tx_ring);
3545 err_tx_ring_allocation:
3546         return -ENOMEM;
3547 }
3548
3549 /**
3550  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3551  * @adapter: board private structure to initialize
3552  *
3553  * Attempt to configure the interrupts using the best available
3554  * capabilities of the hardware and the kernel.
3555  **/
3556 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3557 {
3558         struct ixgbe_hw *hw = &adapter->hw;
3559         int err = 0;
3560         int vector, v_budget;
3561
3562         /*
3563          * It's easy to be greedy for MSI-X vectors, but it really
3564          * doesn't do us much good if we have a lot more vectors
3565          * than CPU's.  So let's be conservative and only ask for
3566          * (roughly) twice the number of vectors as there are CPU's.
3567          */
3568         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3569                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3570
3571         /*
3572          * At the same time, hardware can only support a maximum of
3573          * hw.mac->max_msix_vectors vectors.  With features
3574          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3575          * descriptor queues supported by our device.  Thus, we cap it off in
3576          * those rare cases where the cpu count also exceeds our vector limit.
3577          */
3578         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3579
3580         /* A failure in MSI-X entry allocation isn't fatal, but it does
3581          * mean we disable MSI-X capabilities of the adapter. */
3582         adapter->msix_entries = kcalloc(v_budget,
3583                                         sizeof(struct msix_entry), GFP_KERNEL);
3584         if (adapter->msix_entries) {
3585                 for (vector = 0; vector < v_budget; vector++)
3586                         adapter->msix_entries[vector].entry = vector;
3587
3588                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3589
3590                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3591                         goto out;
3592         }
3593
3594         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3595         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3596         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3597         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3598         adapter->atr_sample_rate = 0;
3599         ixgbe_set_num_queues(adapter);
3600
3601         err = pci_enable_msi(adapter->pdev);
3602         if (!err) {
3603                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3604         } else {
3605                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3606                         "falling back to legacy.  Error: %d\n", err);
3607                 /* reset err */
3608                 err = 0;
3609         }
3610
3611 out:
3612         return err;
3613 }
3614
3615 /**
3616  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3617  * @adapter: board private structure to initialize
3618  *
3619  * We allocate one q_vector per queue interrupt.  If allocation fails we
3620  * return -ENOMEM.
3621  **/
3622 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3623 {
3624         int q_idx, num_q_vectors;
3625         struct ixgbe_q_vector *q_vector;
3626         int napi_vectors;
3627         int (*poll)(struct napi_struct *, int);
3628
3629         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3630                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3631                 napi_vectors = adapter->num_rx_queues;
3632                 poll = &ixgbe_clean_rxtx_many;
3633         } else {
3634                 num_q_vectors = 1;
3635                 napi_vectors = 1;
3636                 poll = &ixgbe_poll;
3637         }
3638
3639         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3640                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3641                 if (!q_vector)
3642                         goto err_out;
3643                 q_vector->adapter = adapter;
3644                 if (q_vector->txr_count && !q_vector->rxr_count)
3645                         q_vector->eitr = adapter->tx_eitr_param;
3646                 else
3647                         q_vector->eitr = adapter->rx_eitr_param;
3648                 q_vector->v_idx = q_idx;
3649                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3650                 adapter->q_vector[q_idx] = q_vector;
3651         }
3652
3653         return 0;
3654
3655 err_out:
3656         while (q_idx) {
3657                 q_idx--;
3658                 q_vector = adapter->q_vector[q_idx];
3659                 netif_napi_del(&q_vector->napi);
3660                 kfree(q_vector);
3661                 adapter->q_vector[q_idx] = NULL;
3662         }
3663         return -ENOMEM;
3664 }
3665
3666 /**
3667  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3668  * @adapter: board private structure to initialize
3669  *
3670  * This function frees the memory allocated to the q_vectors.  In addition if
3671  * NAPI is enabled it will delete any references to the NAPI struct prior
3672  * to freeing the q_vector.
3673  **/
3674 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3675 {
3676         int q_idx, num_q_vectors;
3677
3678         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3679                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3680         else
3681                 num_q_vectors = 1;
3682
3683         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3684                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3685                 adapter->q_vector[q_idx] = NULL;
3686                 netif_napi_del(&q_vector->napi);
3687                 kfree(q_vector);
3688         }
3689 }
3690
3691 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3692 {
3693         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3694                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3695                 pci_disable_msix(adapter->pdev);
3696                 kfree(adapter->msix_entries);
3697                 adapter->msix_entries = NULL;
3698         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3699                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3700                 pci_disable_msi(adapter->pdev);
3701         }
3702         return;
3703 }
3704
3705 /**
3706  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3707  * @adapter: board private structure to initialize
3708  *
3709  * We determine which interrupt scheme to use based on...
3710  * - Kernel support (MSI, MSI-X)
3711  *   - which can be user-defined (via MODULE_PARAM)
3712  * - Hardware queue count (num_*_queues)
3713  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3714  **/
3715 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3716 {
3717         int err;
3718
3719         /* Number of supported queues */
3720         ixgbe_set_num_queues(adapter);
3721
3722         err = ixgbe_set_interrupt_capability(adapter);
3723         if (err) {
3724                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3725                 goto err_set_interrupt;
3726         }
3727
3728         err = ixgbe_alloc_q_vectors(adapter);
3729         if (err) {
3730                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3731                         "vectors\n");
3732                 goto err_alloc_q_vectors;
3733         }
3734
3735         err = ixgbe_alloc_queues(adapter);
3736         if (err) {
3737                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3738                 goto err_alloc_queues;
3739         }
3740
3741         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3742                 "Tx Queue count = %u\n",
3743                 (adapter->num_rx_queues > 1) ? "Enabled" :
3744                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3745
3746         set_bit(__IXGBE_DOWN, &adapter->state);
3747
3748         return 0;
3749
3750 err_alloc_queues:
3751         ixgbe_free_q_vectors(adapter);
3752 err_alloc_q_vectors:
3753         ixgbe_reset_interrupt_capability(adapter);
3754 err_set_interrupt:
3755         return err;
3756 }
3757
3758 /**
3759  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3760  * @adapter: board private structure to clear interrupt scheme on
3761  *
3762  * We go through and clear interrupt specific resources and reset the structure
3763  * to pre-load conditions
3764  **/
3765 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3766 {
3767         kfree(adapter->tx_ring);
3768         kfree(adapter->rx_ring);
3769         adapter->tx_ring = NULL;
3770         adapter->rx_ring = NULL;
3771
3772         ixgbe_free_q_vectors(adapter);
3773         ixgbe_reset_interrupt_capability(adapter);
3774 }
3775
3776 /**
3777  * ixgbe_sfp_timer - worker thread to find a missing module
3778  * @data: pointer to our adapter struct
3779  **/
3780 static void ixgbe_sfp_timer(unsigned long data)
3781 {
3782         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3783
3784         /*
3785          * Do the sfp_timer outside of interrupt context due to the
3786          * delays that sfp+ detection requires
3787          */
3788         schedule_work(&adapter->sfp_task);
3789 }
3790
3791 /**
3792  * ixgbe_sfp_task - worker thread to find a missing module
3793  * @work: pointer to work_struct containing our data
3794  **/
3795 static void ixgbe_sfp_task(struct work_struct *work)
3796 {
3797         struct ixgbe_adapter *adapter = container_of(work,
3798                                                      struct ixgbe_adapter,
3799                                                      sfp_task);
3800         struct ixgbe_hw *hw = &adapter->hw;
3801
3802         if ((hw->phy.type == ixgbe_phy_nl) &&
3803             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3804                 s32 ret = hw->phy.ops.identify_sfp(hw);
3805                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3806                         goto reschedule;
3807                 ret = hw->phy.ops.reset(hw);
3808                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3809                         dev_err(&adapter->pdev->dev, "failed to initialize "
3810                                 "because an unsupported SFP+ module type "
3811                                 "was detected.\n"
3812                                 "Reload the driver after installing a "
3813                                 "supported module.\n");
3814                         unregister_netdev(adapter->netdev);
3815                 } else {
3816                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3817                                 hw->phy.sfp_type);
3818                 }
3819                 /* don't need this routine any more */
3820                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3821         }
3822         return;
3823 reschedule:
3824         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3825                 mod_timer(&adapter->sfp_timer,
3826                           round_jiffies(jiffies + (2 * HZ)));
3827 }
3828
3829 /**
3830  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3831  * @adapter: board private structure to initialize
3832  *
3833  * ixgbe_sw_init initializes the Adapter private data structure.
3834  * Fields are initialized based on PCI device information and
3835  * OS network device settings (MTU size).
3836  **/
3837 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3838 {
3839         struct ixgbe_hw *hw = &adapter->hw;
3840         struct pci_dev *pdev = adapter->pdev;
3841         unsigned int rss;
3842 #ifdef CONFIG_IXGBE_DCB
3843         int j;
3844         struct tc_configuration *tc;
3845 #endif
3846
3847         /* PCI config space info */
3848
3849         hw->vendor_id = pdev->vendor;
3850         hw->device_id = pdev->device;
3851         hw->revision_id = pdev->revision;
3852         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3853         hw->subsystem_device_id = pdev->subsystem_device;
3854
3855         /* Set capability flags */
3856         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3857         adapter->ring_feature[RING_F_RSS].indices = rss;
3858         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3859         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3860         if (hw->mac.type == ixgbe_mac_82598EB) {
3861                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3862                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3863                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3864         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3865                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3866                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3867                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3868                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3869                 adapter->ring_feature[RING_F_FDIR].indices =
3870                                                          IXGBE_MAX_FDIR_INDICES;
3871                 adapter->atr_sample_rate = 20;
3872                 adapter->fdir_pballoc = 0;
3873 #ifdef IXGBE_FCOE
3874                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3875                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3876                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3877                 /* Default traffic class to use for FCoE */
3878                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3879 #endif /* IXGBE_FCOE */
3880         }
3881
3882 #ifdef CONFIG_IXGBE_DCB
3883         /* Configure DCB traffic classes */
3884         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3885                 tc = &adapter->dcb_cfg.tc_config[j];
3886                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3887                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3888                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3889                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3890                 tc->dcb_pfc = pfc_disabled;
3891         }
3892         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3893         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3894         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3895         adapter->dcb_cfg.pfc_mode_enable = false;
3896         adapter->dcb_cfg.round_robin_enable = false;
3897         adapter->dcb_set_bitmap = 0x00;
3898         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3899                            adapter->ring_feature[RING_F_DCB].indices);
3900
3901 #endif
3902
3903         /* default flow control settings */
3904         hw->fc.requested_mode = ixgbe_fc_full;
3905         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3906 #ifdef CONFIG_DCB
3907         adapter->last_lfc_mode = hw->fc.current_mode;
3908 #endif
3909         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3910         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3911         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3912         hw->fc.send_xon = true;
3913         hw->fc.disable_fc_autoneg = false;
3914
3915         /* enable itr by default in dynamic mode */
3916         adapter->rx_itr_setting = 1;
3917         adapter->rx_eitr_param = 20000;
3918         adapter->tx_itr_setting = 1;
3919         adapter->tx_eitr_param = 10000;
3920
3921         /* set defaults for eitr in MegaBytes */
3922         adapter->eitr_low = 10;
3923         adapter->eitr_high = 20;
3924
3925         /* set default ring sizes */
3926         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3927         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3928
3929         /* initialize eeprom parameters */
3930         if (ixgbe_init_eeprom_params_generic(hw)) {
3931                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3932                 return -EIO;
3933         }
3934
3935         /* enable rx csum by default */
3936         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3937
3938         set_bit(__IXGBE_DOWN, &adapter->state);
3939
3940         return 0;
3941 }
3942
3943 /**
3944  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3945  * @adapter: board private structure
3946  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3947  *
3948  * Return 0 on success, negative on failure
3949  **/
3950 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3951                              struct ixgbe_ring *tx_ring)
3952 {
3953         struct pci_dev *pdev = adapter->pdev;
3954         int size;
3955
3956         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3957         tx_ring->tx_buffer_info = vmalloc(size);
3958         if (!tx_ring->tx_buffer_info)
3959                 goto err;
3960         memset(tx_ring->tx_buffer_info, 0, size);
3961
3962         /* round up to nearest 4K */
3963         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3964         tx_ring->size = ALIGN(tx_ring->size, 4096);
3965
3966         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3967                                              &tx_ring->dma);
3968         if (!tx_ring->desc)
3969                 goto err;
3970
3971         tx_ring->next_to_use = 0;
3972         tx_ring->next_to_clean = 0;
3973         tx_ring->work_limit = tx_ring->count;
3974         return 0;
3975
3976 err:
3977         vfree(tx_ring->tx_buffer_info);
3978         tx_ring->tx_buffer_info = NULL;
3979         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3980                             "descriptor ring\n");
3981         return -ENOMEM;
3982 }
3983
3984 /**
3985  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3986  * @adapter: board private structure
3987  *
3988  * If this function returns with an error, then it's possible one or
3989  * more of the rings is populated (while the rest are not).  It is the
3990  * callers duty to clean those orphaned rings.
3991  *
3992  * Return 0 on success, negative on failure
3993  **/
3994 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3995 {
3996         int i, err = 0;
3997
3998         for (i = 0; i < adapter->num_tx_queues; i++) {
3999                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
4000                 if (!err)
4001                         continue;
4002                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
4003                 break;
4004         }
4005
4006         return err;
4007 }
4008
4009 /**
4010  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4011  * @adapter: board private structure
4012  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4013  *
4014  * Returns 0 on success, negative on failure
4015  **/
4016 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4017                              struct ixgbe_ring *rx_ring)
4018 {
4019         struct pci_dev *pdev = adapter->pdev;
4020         int size;
4021
4022         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4023         rx_ring->rx_buffer_info = vmalloc(size);
4024         if (!rx_ring->rx_buffer_info) {
4025                 DPRINTK(PROBE, ERR,
4026                         "vmalloc allocation failed for the rx desc ring\n");
4027                 goto alloc_failed;
4028         }
4029         memset(rx_ring->rx_buffer_info, 0, size);
4030
4031         /* Round up to nearest 4K */
4032         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4033         rx_ring->size = ALIGN(rx_ring->size, 4096);
4034
4035         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
4036
4037         if (!rx_ring->desc) {
4038                 DPRINTK(PROBE, ERR,
4039                         "Memory allocation failed for the rx desc ring\n");
4040                 vfree(rx_ring->rx_buffer_info);
4041                 goto alloc_failed;
4042         }
4043
4044         rx_ring->next_to_clean = 0;
4045         rx_ring->next_to_use = 0;
4046
4047         return 0;
4048
4049 alloc_failed:
4050         return -ENOMEM;
4051 }
4052
4053 /**
4054  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4055  * @adapter: board private structure
4056  *
4057  * If this function returns with an error, then it's possible one or
4058  * more of the rings is populated (while the rest are not).  It is the
4059  * callers duty to clean those orphaned rings.
4060  *
4061  * Return 0 on success, negative on failure
4062  **/
4063
4064 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4065 {
4066         int i, err = 0;
4067
4068         for (i = 0; i < adapter->num_rx_queues; i++) {
4069                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4070                 if (!err)
4071                         continue;
4072                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4073                 break;
4074         }
4075
4076         return err;
4077 }
4078
4079 /**
4080  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4081  * @adapter: board private structure
4082  * @tx_ring: Tx descriptor ring for a specific queue
4083  *
4084  * Free all transmit software resources
4085  **/
4086 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4087                              struct ixgbe_ring *tx_ring)
4088 {
4089         struct pci_dev *pdev = adapter->pdev;
4090
4091         ixgbe_clean_tx_ring(adapter, tx_ring);
4092
4093         vfree(tx_ring->tx_buffer_info);
4094         tx_ring->tx_buffer_info = NULL;
4095
4096         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4097
4098         tx_ring->desc = NULL;
4099 }
4100
4101 /**
4102  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4103  * @adapter: board private structure
4104  *
4105  * Free all transmit software resources
4106  **/
4107 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4108 {
4109         int i;
4110
4111         for (i = 0; i < adapter->num_tx_queues; i++)
4112                 if (adapter->tx_ring[i].desc)
4113                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4114 }
4115
4116 /**
4117  * ixgbe_free_rx_resources - Free Rx Resources
4118  * @adapter: board private structure
4119  * @rx_ring: ring to clean the resources from
4120  *
4121  * Free all receive software resources
4122  **/
4123 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4124                              struct ixgbe_ring *rx_ring)
4125 {
4126         struct pci_dev *pdev = adapter->pdev;
4127
4128         ixgbe_clean_rx_ring(adapter, rx_ring);
4129
4130         vfree(rx_ring->rx_buffer_info);
4131         rx_ring->rx_buffer_info = NULL;
4132
4133         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4134
4135         rx_ring->desc = NULL;
4136 }
4137
4138 /**
4139  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4140  * @adapter: board private structure
4141  *
4142  * Free all receive software resources
4143  **/
4144 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4145 {
4146         int i;
4147
4148         for (i = 0; i < adapter->num_rx_queues; i++)
4149                 if (adapter->rx_ring[i].desc)
4150                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4151 }
4152
4153 /**
4154  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4155  * @netdev: network interface device structure
4156  * @new_mtu: new value for maximum frame size
4157  *
4158  * Returns 0 on success, negative on failure
4159  **/
4160 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4161 {
4162         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4163         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4164
4165         /* MTU < 68 is an error and causes problems on some kernels */
4166         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4167                 return -EINVAL;
4168
4169         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4170                 netdev->mtu, new_mtu);
4171         /* must set new MTU before calling down or up */
4172         netdev->mtu = new_mtu;
4173
4174         if (netif_running(netdev))
4175                 ixgbe_reinit_locked(adapter);
4176
4177         return 0;
4178 }
4179
4180 /**
4181  * ixgbe_open - Called when a network interface is made active
4182  * @netdev: network interface device structure
4183  *
4184  * Returns 0 on success, negative value on failure
4185  *
4186  * The open entry point is called when a network interface is made
4187  * active by the system (IFF_UP).  At this point all resources needed
4188  * for transmit and receive operations are allocated, the interrupt
4189  * handler is registered with the OS, the watchdog timer is started,
4190  * and the stack is notified that the interface is ready.
4191  **/
4192 static int ixgbe_open(struct net_device *netdev)
4193 {
4194         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4195         int err;
4196
4197         /* disallow open during test */
4198         if (test_bit(__IXGBE_TESTING, &adapter->state))
4199                 return -EBUSY;
4200
4201         netif_carrier_off(netdev);
4202
4203         /* allocate transmit descriptors */
4204         err = ixgbe_setup_all_tx_resources(adapter);
4205         if (err)
4206                 goto err_setup_tx;
4207
4208         /* allocate receive descriptors */
4209         err = ixgbe_setup_all_rx_resources(adapter);
4210         if (err)
4211                 goto err_setup_rx;
4212
4213         ixgbe_configure(adapter);
4214
4215         err = ixgbe_request_irq(adapter);
4216         if (err)
4217                 goto err_req_irq;
4218
4219         err = ixgbe_up_complete(adapter);
4220         if (err)
4221                 goto err_up;
4222
4223         netif_tx_start_all_queues(netdev);
4224
4225         return 0;
4226
4227 err_up:
4228         ixgbe_release_hw_control(adapter);
4229         ixgbe_free_irq(adapter);
4230 err_req_irq:
4231 err_setup_rx:
4232         ixgbe_free_all_rx_resources(adapter);
4233 err_setup_tx:
4234         ixgbe_free_all_tx_resources(adapter);
4235         ixgbe_reset(adapter);
4236
4237         return err;
4238 }
4239
4240 /**
4241  * ixgbe_close - Disables a network interface
4242  * @netdev: network interface device structure
4243  *
4244  * Returns 0, this is not allowed to fail
4245  *
4246  * The close entry point is called when an interface is de-activated
4247  * by the OS.  The hardware is still under the drivers control, but
4248  * needs to be disabled.  A global MAC reset is issued to stop the
4249  * hardware, and all transmit and receive resources are freed.
4250  **/
4251 static int ixgbe_close(struct net_device *netdev)
4252 {
4253         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4254
4255         ixgbe_down(adapter);
4256         ixgbe_free_irq(adapter);
4257
4258         ixgbe_free_all_tx_resources(adapter);
4259         ixgbe_free_all_rx_resources(adapter);
4260
4261         ixgbe_release_hw_control(adapter);
4262
4263         return 0;
4264 }
4265
4266 #ifdef CONFIG_PM
4267 static int ixgbe_resume(struct pci_dev *pdev)
4268 {
4269         struct net_device *netdev = pci_get_drvdata(pdev);
4270         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4271         u32 err;
4272
4273         pci_set_power_state(pdev, PCI_D0);
4274         pci_restore_state(pdev);
4275
4276         err = pci_enable_device_mem(pdev);
4277         if (err) {
4278                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4279                                 "suspend\n");
4280                 return err;
4281         }
4282         pci_set_master(pdev);
4283
4284         pci_wake_from_d3(pdev, false);
4285
4286         err = ixgbe_init_interrupt_scheme(adapter);
4287         if (err) {
4288                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4289                                 "device\n");
4290                 return err;
4291         }
4292
4293         ixgbe_reset(adapter);
4294
4295         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4296
4297         if (netif_running(netdev)) {
4298                 err = ixgbe_open(adapter->netdev);
4299                 if (err)
4300                         return err;
4301         }
4302
4303         netif_device_attach(netdev);
4304
4305         return 0;
4306 }
4307 #endif /* CONFIG_PM */
4308
4309 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4310 {
4311         struct net_device *netdev = pci_get_drvdata(pdev);
4312         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4313         struct ixgbe_hw *hw = &adapter->hw;
4314         u32 ctrl, fctrl;
4315         u32 wufc = adapter->wol;
4316 #ifdef CONFIG_PM
4317         int retval = 0;
4318 #endif
4319
4320         netif_device_detach(netdev);
4321
4322         if (netif_running(netdev)) {
4323                 ixgbe_down(adapter);
4324                 ixgbe_free_irq(adapter);
4325                 ixgbe_free_all_tx_resources(adapter);
4326                 ixgbe_free_all_rx_resources(adapter);
4327         }
4328         ixgbe_clear_interrupt_scheme(adapter);
4329
4330 #ifdef CONFIG_PM
4331         retval = pci_save_state(pdev);
4332         if (retval)
4333                 return retval;
4334
4335 #endif
4336         if (wufc) {
4337                 ixgbe_set_rx_mode(netdev);
4338
4339                 /* turn on all-multi mode if wake on multicast is enabled */
4340                 if (wufc & IXGBE_WUFC_MC) {
4341                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4342                         fctrl |= IXGBE_FCTRL_MPE;
4343                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4344                 }
4345
4346                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4347                 ctrl |= IXGBE_CTRL_GIO_DIS;
4348                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4349
4350                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4351         } else {
4352                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4353                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4354         }
4355
4356         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4357                 pci_wake_from_d3(pdev, true);
4358         else
4359                 pci_wake_from_d3(pdev, false);
4360
4361         *enable_wake = !!wufc;
4362
4363         ixgbe_release_hw_control(adapter);
4364
4365         pci_disable_device(pdev);
4366
4367         return 0;
4368 }
4369
4370 #ifdef CONFIG_PM
4371 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4372 {
4373         int retval;
4374         bool wake;
4375
4376         retval = __ixgbe_shutdown(pdev, &wake);
4377         if (retval)
4378                 return retval;
4379
4380         if (wake) {
4381                 pci_prepare_to_sleep(pdev);
4382         } else {
4383                 pci_wake_from_d3(pdev, false);
4384                 pci_set_power_state(pdev, PCI_D3hot);
4385         }
4386
4387         return 0;
4388 }
4389 #endif /* CONFIG_PM */
4390
4391 static void ixgbe_shutdown(struct pci_dev *pdev)
4392 {
4393         bool wake;
4394
4395         __ixgbe_shutdown(pdev, &wake);
4396
4397         if (system_state == SYSTEM_POWER_OFF) {
4398                 pci_wake_from_d3(pdev, wake);
4399                 pci_set_power_state(pdev, PCI_D3hot);
4400         }
4401 }
4402
4403 /**
4404  * ixgbe_update_stats - Update the board statistics counters.
4405  * @adapter: board private structure
4406  **/
4407 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4408 {
4409         struct ixgbe_hw *hw = &adapter->hw;
4410         u64 total_mpc = 0;
4411         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4412
4413         if (hw->mac.type == ixgbe_mac_82599EB) {
4414                 u64 rsc_count = 0;
4415                 for (i = 0; i < 16; i++)
4416                         adapter->hw_rx_no_dma_resources +=
4417                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4418                 for (i = 0; i < adapter->num_rx_queues; i++)
4419                         rsc_count += adapter->rx_ring[i].rsc_count;
4420                 adapter->rsc_count = rsc_count;
4421         }
4422
4423         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4424         for (i = 0; i < 8; i++) {
4425                 /* for packet buffers not used, the register should read 0 */
4426                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4427                 missed_rx += mpc;
4428                 adapter->stats.mpc[i] += mpc;
4429                 total_mpc += adapter->stats.mpc[i];
4430                 if (hw->mac.type == ixgbe_mac_82598EB)
4431                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4432                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4433                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4434                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4435                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4436                 if (hw->mac.type == ixgbe_mac_82599EB) {
4437                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4438                                                             IXGBE_PXONRXCNT(i));
4439                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4440                                                            IXGBE_PXOFFRXCNT(i));
4441                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4442                 } else {
4443                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4444                                                               IXGBE_PXONRXC(i));
4445                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4446                                                              IXGBE_PXOFFRXC(i));
4447                 }
4448                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4449                                                             IXGBE_PXONTXC(i));
4450                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4451                                                              IXGBE_PXOFFTXC(i));
4452         }
4453         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4454         /* work around hardware counting issue */
4455         adapter->stats.gprc -= missed_rx;
4456
4457         /* 82598 hardware only has a 32 bit counter in the high register */
4458         if (hw->mac.type == ixgbe_mac_82599EB) {
4459                 u64 tmp;
4460                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4461                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4462                 adapter->stats.gorc += (tmp << 32);
4463                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4464                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4465                 adapter->stats.gotc += (tmp << 32);
4466                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4467                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4468                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4469                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4470                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4471                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4472 #ifdef IXGBE_FCOE
4473                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4474                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4475                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4476                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4477                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4478                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4479 #endif /* IXGBE_FCOE */
4480         } else {
4481                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4482                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4483                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4484                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4485                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4486         }
4487         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4488         adapter->stats.bprc += bprc;
4489         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4490         if (hw->mac.type == ixgbe_mac_82598EB)
4491                 adapter->stats.mprc -= bprc;
4492         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4493         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4494         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4495         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4496         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4497         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4498         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4499         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4500         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4501         adapter->stats.lxontxc += lxon;
4502         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4503         adapter->stats.lxofftxc += lxoff;
4504         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4505         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4506         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4507         /*
4508          * 82598 errata - tx of flow control packets is included in tx counters
4509          */
4510         xon_off_tot = lxon + lxoff;
4511         adapter->stats.gptc -= xon_off_tot;
4512         adapter->stats.mptc -= xon_off_tot;
4513         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4514         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4515         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4516         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4517         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4518         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4519         adapter->stats.ptc64 -= xon_off_tot;
4520         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4521         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4522         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4523         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4524         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4525         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4526
4527         /* Fill out the OS statistics structure */
4528         adapter->net_stats.multicast = adapter->stats.mprc;
4529
4530         /* Rx Errors */
4531         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4532                                        adapter->stats.rlec;
4533         adapter->net_stats.rx_dropped = 0;
4534         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4535         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4536         adapter->net_stats.rx_missed_errors = total_mpc;
4537 }
4538
4539 /**
4540  * ixgbe_watchdog - Timer Call-back
4541  * @data: pointer to adapter cast into an unsigned long
4542  **/
4543 static void ixgbe_watchdog(unsigned long data)
4544 {
4545         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4546         struct ixgbe_hw *hw = &adapter->hw;
4547         u64 eics = 0;
4548         int i;
4549
4550         /*
4551          *  Do the watchdog outside of interrupt context due to the lovely
4552          * delays that some of the newer hardware requires
4553          */
4554
4555         if (test_bit(__IXGBE_DOWN, &adapter->state))
4556                 goto watchdog_short_circuit;
4557
4558         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4559                 /*
4560                  * for legacy and MSI interrupts don't set any bits
4561                  * that are enabled for EIAM, because this operation
4562                  * would set *both* EIMS and EICS for any bit in EIAM
4563                  */
4564                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4565                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4566                 goto watchdog_reschedule;
4567         }
4568
4569         /* get one bit for every active tx/rx interrupt vector */
4570         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4571                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4572                 if (qv->rxr_count || qv->txr_count)
4573                         eics |= ((u64)1 << i);
4574         }
4575
4576         /* Cause software interrupt to ensure rx rings are cleaned */
4577         ixgbe_irq_rearm_queues(adapter, eics);
4578
4579 watchdog_reschedule:
4580         /* Reset the timer */
4581         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4582
4583 watchdog_short_circuit:
4584         schedule_work(&adapter->watchdog_task);
4585 }
4586
4587 /**
4588  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4589  * @work: pointer to work_struct containing our data
4590  **/
4591 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4592 {
4593         struct ixgbe_adapter *adapter = container_of(work,
4594                                                      struct ixgbe_adapter,
4595                                                      multispeed_fiber_task);
4596         struct ixgbe_hw *hw = &adapter->hw;
4597         u32 autoneg;
4598         bool negotiation;
4599
4600         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4601         autoneg = hw->phy.autoneg_advertised;
4602         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4603                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4604         if (hw->mac.ops.setup_link)
4605                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4606         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4607         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4608 }
4609
4610 /**
4611  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4612  * @work: pointer to work_struct containing our data
4613  **/
4614 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4615 {
4616         struct ixgbe_adapter *adapter = container_of(work,
4617                                                      struct ixgbe_adapter,
4618                                                      sfp_config_module_task);
4619         struct ixgbe_hw *hw = &adapter->hw;
4620         u32 err;
4621
4622         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4623
4624         /* Time for electrical oscillations to settle down */
4625         msleep(100);
4626         err = hw->phy.ops.identify_sfp(hw);
4627
4628         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4629                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4630                         "an unsupported SFP+ module type was detected.\n"
4631                         "Reload the driver after installing a supported "
4632                         "module.\n");
4633                 unregister_netdev(adapter->netdev);
4634                 return;
4635         }
4636         hw->mac.ops.setup_sfp(hw);
4637
4638         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4639                 /* This will also work for DA Twinax connections */
4640                 schedule_work(&adapter->multispeed_fiber_task);
4641         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4642 }
4643
4644 /**
4645  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4646  * @work: pointer to work_struct containing our data
4647  **/
4648 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4649 {
4650         struct ixgbe_adapter *adapter = container_of(work,
4651                                                      struct ixgbe_adapter,
4652                                                      fdir_reinit_task);
4653         struct ixgbe_hw *hw = &adapter->hw;
4654         int i;
4655
4656         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4657                 for (i = 0; i < adapter->num_tx_queues; i++)
4658                         set_bit(__IXGBE_FDIR_INIT_DONE,
4659                                 &(adapter->tx_ring[i].reinit_state));
4660         } else {
4661                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4662                         "ignored adding FDIR ATR filters \n");
4663         }
4664         /* Done FDIR Re-initialization, enable transmits */
4665         netif_tx_start_all_queues(adapter->netdev);
4666 }
4667
4668 /**
4669  * ixgbe_watchdog_task - worker thread to bring link up
4670  * @work: pointer to work_struct containing our data
4671  **/
4672 static void ixgbe_watchdog_task(struct work_struct *work)
4673 {
4674         struct ixgbe_adapter *adapter = container_of(work,
4675                                                      struct ixgbe_adapter,
4676                                                      watchdog_task);
4677         struct net_device *netdev = adapter->netdev;
4678         struct ixgbe_hw *hw = &adapter->hw;
4679         u32 link_speed = adapter->link_speed;
4680         bool link_up = adapter->link_up;
4681         int i;
4682         struct ixgbe_ring *tx_ring;
4683         int some_tx_pending = 0;
4684
4685         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4686
4687         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4688                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4689                 if (link_up) {
4690 #ifdef CONFIG_DCB
4691                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4692                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4693                                         hw->mac.ops.fc_enable(hw, i);
4694                         } else {
4695                                 hw->mac.ops.fc_enable(hw, 0);
4696                         }
4697 #else
4698                         hw->mac.ops.fc_enable(hw, 0);
4699 #endif
4700                 }
4701
4702                 if (link_up ||
4703                     time_after(jiffies, (adapter->link_check_timeout +
4704                                          IXGBE_TRY_LINK_TIMEOUT))) {
4705                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4706                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4707                 }
4708                 adapter->link_up = link_up;
4709                 adapter->link_speed = link_speed;
4710         }
4711
4712         if (link_up) {
4713                 if (!netif_carrier_ok(netdev)) {
4714                         bool flow_rx, flow_tx;
4715
4716                         if (hw->mac.type == ixgbe_mac_82599EB) {
4717                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4718                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4719                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4720                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4721                         } else {
4722                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4723                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4724                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4725                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4726                         }
4727
4728                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4729                                "Flow Control: %s\n",
4730                                netdev->name,
4731                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4732                                 "10 Gbps" :
4733                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4734                                  "1 Gbps" : "unknown speed")),
4735                                ((flow_rx && flow_tx) ? "RX/TX" :
4736                                 (flow_rx ? "RX" :
4737                                 (flow_tx ? "TX" : "None"))));
4738
4739                         netif_carrier_on(netdev);
4740                 } else {
4741                         /* Force detection of hung controller */
4742                         adapter->detect_tx_hung = true;
4743                 }
4744         } else {
4745                 adapter->link_up = false;
4746                 adapter->link_speed = 0;
4747                 if (netif_carrier_ok(netdev)) {
4748                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4749                                netdev->name);
4750                         netif_carrier_off(netdev);
4751                 }
4752         }
4753
4754         if (!netif_carrier_ok(netdev)) {
4755                 for (i = 0; i < adapter->num_tx_queues; i++) {
4756                         tx_ring = &adapter->tx_ring[i];
4757                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4758                                 some_tx_pending = 1;
4759                                 break;
4760                         }
4761                 }
4762
4763                 if (some_tx_pending) {
4764                         /* We've lost link, so the controller stops DMA,
4765                          * but we've got queued Tx work that's never going
4766                          * to get done, so reset controller to flush Tx.
4767                          * (Do the reset outside of interrupt context).
4768                          */
4769                          schedule_work(&adapter->reset_task);
4770                 }
4771         }
4772
4773         ixgbe_update_stats(adapter);
4774         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4775 }
4776
4777 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4778                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4779                      u32 tx_flags, u8 *hdr_len)
4780 {
4781         struct ixgbe_adv_tx_context_desc *context_desc;
4782         unsigned int i;
4783         int err;
4784         struct ixgbe_tx_buffer *tx_buffer_info;
4785         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4786         u32 mss_l4len_idx, l4len;
4787
4788         if (skb_is_gso(skb)) {
4789                 if (skb_header_cloned(skb)) {
4790                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4791                         if (err)
4792                                 return err;
4793                 }
4794                 l4len = tcp_hdrlen(skb);
4795                 *hdr_len += l4len;
4796
4797                 if (skb->protocol == htons(ETH_P_IP)) {
4798                         struct iphdr *iph = ip_hdr(skb);
4799                         iph->tot_len = 0;
4800                         iph->check = 0;
4801                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4802                                                                  iph->daddr, 0,
4803                                                                  IPPROTO_TCP,
4804                                                                  0);
4805                         adapter->hw_tso_ctxt++;
4806                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4807                         ipv6_hdr(skb)->payload_len = 0;
4808                         tcp_hdr(skb)->check =
4809                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4810                                              &ipv6_hdr(skb)->daddr,
4811                                              0, IPPROTO_TCP, 0);
4812                         adapter->hw_tso6_ctxt++;
4813                 }
4814
4815                 i = tx_ring->next_to_use;
4816
4817                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4818                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4819
4820                 /* VLAN MACLEN IPLEN */
4821                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4822                         vlan_macip_lens |=
4823                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4824                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4825                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4826                 *hdr_len += skb_network_offset(skb);
4827                 vlan_macip_lens |=
4828                     (skb_transport_header(skb) - skb_network_header(skb));
4829                 *hdr_len +=
4830                     (skb_transport_header(skb) - skb_network_header(skb));
4831                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4832                 context_desc->seqnum_seed = 0;
4833
4834                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4835                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4836                                    IXGBE_ADVTXD_DTYP_CTXT);
4837
4838                 if (skb->protocol == htons(ETH_P_IP))
4839                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4840                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4841                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4842
4843                 /* MSS L4LEN IDX */
4844                 mss_l4len_idx =
4845                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4846                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4847                 /* use index 1 for TSO */
4848                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4849                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4850
4851                 tx_buffer_info->time_stamp = jiffies;
4852                 tx_buffer_info->next_to_watch = i;
4853
4854                 i++;
4855                 if (i == tx_ring->count)
4856                         i = 0;
4857                 tx_ring->next_to_use = i;
4858
4859                 return true;
4860         }
4861         return false;
4862 }
4863
4864 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4865                           struct ixgbe_ring *tx_ring,
4866                           struct sk_buff *skb, u32 tx_flags)
4867 {
4868         struct ixgbe_adv_tx_context_desc *context_desc;
4869         unsigned int i;
4870         struct ixgbe_tx_buffer *tx_buffer_info;
4871         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4872
4873         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4874             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4875                 i = tx_ring->next_to_use;
4876                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4877                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4878
4879                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4880                         vlan_macip_lens |=
4881                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4882                 vlan_macip_lens |= (skb_network_offset(skb) <<
4883                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4884                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4885                         vlan_macip_lens |= (skb_transport_header(skb) -
4886                                             skb_network_header(skb));
4887
4888                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4889                 context_desc->seqnum_seed = 0;
4890
4891                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4892                                     IXGBE_ADVTXD_DTYP_CTXT);
4893
4894                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4895                         switch (skb->protocol) {
4896                         case cpu_to_be16(ETH_P_IP):
4897                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4898                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4899                                         type_tucmd_mlhl |=
4900                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4901                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4902                                         type_tucmd_mlhl |=
4903                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4904                                 break;
4905                         case cpu_to_be16(ETH_P_IPV6):
4906                                 /* XXX what about other V6 headers?? */
4907                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4908                                         type_tucmd_mlhl |=
4909                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4910                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4911                                         type_tucmd_mlhl |=
4912                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4913                                 break;
4914                         default:
4915                                 if (unlikely(net_ratelimit())) {
4916                                         DPRINTK(PROBE, WARNING,
4917                                          "partial checksum but proto=%x!\n",
4918                                          skb->protocol);
4919                                 }
4920                                 break;
4921                         }
4922                 }
4923
4924                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4925                 /* use index zero for tx checksum offload */
4926                 context_desc->mss_l4len_idx = 0;
4927
4928                 tx_buffer_info->time_stamp = jiffies;
4929                 tx_buffer_info->next_to_watch = i;
4930
4931                 adapter->hw_csum_tx_good++;
4932                 i++;
4933                 if (i == tx_ring->count)
4934                         i = 0;
4935                 tx_ring->next_to_use = i;
4936
4937                 return true;
4938         }
4939
4940         return false;
4941 }
4942
4943 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4944                         struct ixgbe_ring *tx_ring,
4945                         struct sk_buff *skb, u32 tx_flags,
4946                         unsigned int first)
4947 {
4948         struct ixgbe_tx_buffer *tx_buffer_info;
4949         unsigned int len;
4950         unsigned int total = skb->len;
4951         unsigned int offset = 0, size, count = 0, i;
4952         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4953         unsigned int f;
4954         dma_addr_t *map;
4955
4956         i = tx_ring->next_to_use;
4957
4958         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4959                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4960                 return 0;
4961         }
4962
4963         map = skb_shinfo(skb)->dma_maps;
4964
4965         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4966                 /* excluding fcoe_crc_eof for FCoE */
4967                 total -= sizeof(struct fcoe_crc_eof);
4968
4969         len = min(skb_headlen(skb), total);
4970         while (len) {
4971                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4972                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4973
4974                 tx_buffer_info->length = size;
4975                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4976                 tx_buffer_info->time_stamp = jiffies;
4977                 tx_buffer_info->next_to_watch = i;
4978
4979                 len -= size;
4980                 total -= size;
4981                 offset += size;
4982                 count++;
4983
4984                 if (len) {
4985                         i++;
4986                         if (i == tx_ring->count)
4987                                 i = 0;
4988                 }
4989         }
4990
4991         for (f = 0; f < nr_frags; f++) {
4992                 struct skb_frag_struct *frag;
4993
4994                 frag = &skb_shinfo(skb)->frags[f];
4995                 len = min((unsigned int)frag->size, total);
4996                 offset = 0;
4997
4998                 while (len) {
4999                         i++;
5000                         if (i == tx_ring->count)
5001                                 i = 0;
5002
5003                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
5004                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5005
5006                         tx_buffer_info->length = size;
5007                         tx_buffer_info->dma = map[f] + offset;
5008                         tx_buffer_info->time_stamp = jiffies;
5009                         tx_buffer_info->next_to_watch = i;
5010
5011                         len -= size;
5012                         total -= size;
5013                         offset += size;
5014                         count++;
5015                 }
5016                 if (total == 0)
5017                         break;
5018         }
5019
5020         tx_ring->tx_buffer_info[i].skb = skb;
5021         tx_ring->tx_buffer_info[first].next_to_watch = i;
5022
5023         return count;
5024 }
5025
5026 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
5027                            struct ixgbe_ring *tx_ring,
5028                            int tx_flags, int count, u32 paylen, u8 hdr_len)
5029 {
5030         union ixgbe_adv_tx_desc *tx_desc = NULL;
5031         struct ixgbe_tx_buffer *tx_buffer_info;
5032         u32 olinfo_status = 0, cmd_type_len = 0;
5033         unsigned int i;
5034         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5035
5036         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5037
5038         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5039
5040         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5041                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5042
5043         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5044                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5045
5046                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5047                                  IXGBE_ADVTXD_POPTS_SHIFT;
5048
5049                 /* use index 1 context for tso */
5050                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5051                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5052                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5053                                          IXGBE_ADVTXD_POPTS_SHIFT;
5054
5055         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5056                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5057                                  IXGBE_ADVTXD_POPTS_SHIFT;
5058
5059         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5060                 olinfo_status |= IXGBE_ADVTXD_CC;
5061                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5062                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5063                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5064         }
5065
5066         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5067
5068         i = tx_ring->next_to_use;
5069         while (count--) {
5070                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5071                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5072                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5073                 tx_desc->read.cmd_type_len =
5074                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5075                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5076                 i++;
5077                 if (i == tx_ring->count)
5078                         i = 0;
5079         }
5080
5081         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5082
5083         /*
5084          * Force memory writes to complete before letting h/w
5085          * know there are new descriptors to fetch.  (Only
5086          * applicable for weak-ordered memory model archs,
5087          * such as IA-64).
5088          */
5089         wmb();
5090
5091         tx_ring->next_to_use = i;
5092         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5093 }
5094
5095 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5096                       int queue, u32 tx_flags)
5097 {
5098         /* Right now, we support IPv4 only */
5099         struct ixgbe_atr_input atr_input;
5100         struct tcphdr *th;
5101         struct iphdr *iph = ip_hdr(skb);
5102         struct ethhdr *eth = (struct ethhdr *)skb->data;
5103         u16 vlan_id, src_port, dst_port, flex_bytes;
5104         u32 src_ipv4_addr, dst_ipv4_addr;
5105         u8 l4type = 0;
5106
5107         /* check if we're UDP or TCP */
5108         if (iph->protocol == IPPROTO_TCP) {
5109                 th = tcp_hdr(skb);
5110                 src_port = th->source;
5111                 dst_port = th->dest;
5112                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5113                 /* l4type IPv4 type is 0, no need to assign */
5114         } else {
5115                 /* Unsupported L4 header, just bail here */
5116                 return;
5117         }
5118
5119         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5120
5121         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5122                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5123         src_ipv4_addr = iph->saddr;
5124         dst_ipv4_addr = iph->daddr;
5125         flex_bytes = eth->h_proto;
5126
5127         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5128         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5129         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5130         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5131         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5132         /* src and dst are inverted, think how the receiver sees them */
5133         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5134         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5135
5136         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5137         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5138 }
5139
5140 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5141                                  struct ixgbe_ring *tx_ring, int size)
5142 {
5143         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5144
5145         netif_stop_subqueue(netdev, tx_ring->queue_index);
5146         /* Herbert's original patch had:
5147          *  smp_mb__after_netif_stop_queue();
5148          * but since that doesn't exist yet, just open code it. */
5149         smp_mb();
5150
5151         /* We need to check again in a case another CPU has just
5152          * made room available. */
5153         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5154                 return -EBUSY;
5155
5156         /* A reprieve! - use start_queue because it doesn't call schedule */
5157         netif_start_subqueue(netdev, tx_ring->queue_index);
5158         ++adapter->restart_queue;
5159         return 0;
5160 }
5161
5162 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5163                               struct ixgbe_ring *tx_ring, int size)
5164 {
5165         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5166                 return 0;
5167         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5168 }
5169
5170 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5171 {
5172         struct ixgbe_adapter *adapter = netdev_priv(dev);
5173
5174         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5175                 return smp_processor_id();
5176
5177         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5178                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5179
5180         return skb_tx_hash(dev, skb);
5181 }
5182
5183 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5184                                     struct net_device *netdev)
5185 {
5186         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5187         struct ixgbe_ring *tx_ring;
5188         unsigned int first;
5189         unsigned int tx_flags = 0;
5190         u8 hdr_len = 0;
5191         int r_idx = 0, tso;
5192         int count = 0;
5193         unsigned int f;
5194
5195         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5196                 tx_flags |= vlan_tx_tag_get(skb);
5197                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5198                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5199                         tx_flags |= (skb->queue_mapping << 13);
5200                 }
5201                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5202                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5203         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5204                 if (skb->priority != TC_PRIO_CONTROL) {
5205                         tx_flags |= (skb->queue_mapping << 13);
5206                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5207                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5208                 } else {
5209                         skb->queue_mapping =
5210                                 adapter->ring_feature[RING_F_DCB].indices-1;
5211                 }
5212         }
5213
5214         r_idx = skb->queue_mapping;
5215         tx_ring = &adapter->tx_ring[r_idx];
5216
5217         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5218             (skb->protocol == htons(ETH_P_FCOE))) {
5219                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5220 #ifdef IXGBE_FCOE
5221                 r_idx = smp_processor_id();
5222                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5223                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5224                 tx_ring = &adapter->tx_ring[r_idx];
5225 #endif
5226         }
5227         /* four things can cause us to need a context descriptor */
5228         if (skb_is_gso(skb) ||
5229             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5230             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5231             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5232                 count++;
5233
5234         count += TXD_USE_COUNT(skb_headlen(skb));
5235         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5236                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5237
5238         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5239                 adapter->tx_busy++;
5240                 return NETDEV_TX_BUSY;
5241         }
5242
5243         first = tx_ring->next_to_use;
5244         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5245 #ifdef IXGBE_FCOE
5246                 /* setup tx offload for FCoE */
5247                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5248                 if (tso < 0) {
5249                         dev_kfree_skb_any(skb);
5250                         return NETDEV_TX_OK;
5251                 }
5252                 if (tso)
5253                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5254 #endif /* IXGBE_FCOE */
5255         } else {
5256                 if (skb->protocol == htons(ETH_P_IP))
5257                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5258                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5259                 if (tso < 0) {
5260                         dev_kfree_skb_any(skb);
5261                         return NETDEV_TX_OK;
5262                 }
5263
5264                 if (tso)
5265                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5266                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5267                          (skb->ip_summed == CHECKSUM_PARTIAL))
5268                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5269         }
5270
5271         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5272         if (count) {
5273                 /* add the ATR filter if ATR is on */
5274                 if (tx_ring->atr_sample_rate) {
5275                         ++tx_ring->atr_count;
5276                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5277                              test_bit(__IXGBE_FDIR_INIT_DONE,
5278                                       &tx_ring->reinit_state)) {
5279                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5280                                           tx_flags);
5281                                 tx_ring->atr_count = 0;
5282                         }
5283                 }
5284                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5285                                hdr_len);
5286                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5287
5288         } else {
5289                 dev_kfree_skb_any(skb);
5290                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5291                 tx_ring->next_to_use = first;
5292         }
5293
5294         return NETDEV_TX_OK;
5295 }
5296
5297 /**
5298  * ixgbe_get_stats - Get System Network Statistics
5299  * @netdev: network interface device structure
5300  *
5301  * Returns the address of the device statistics structure.
5302  * The statistics are actually updated from the timer callback.
5303  **/
5304 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5305 {
5306         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5307
5308         /* only return the current stats */
5309         return &adapter->net_stats;
5310 }
5311
5312 /**
5313  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5314  * @netdev: network interface device structure
5315  * @p: pointer to an address structure
5316  *
5317  * Returns 0 on success, negative on failure
5318  **/
5319 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5320 {
5321         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5322         struct ixgbe_hw *hw = &adapter->hw;
5323         struct sockaddr *addr = p;
5324
5325         if (!is_valid_ether_addr(addr->sa_data))
5326                 return -EADDRNOTAVAIL;
5327
5328         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5329         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5330
5331         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5332
5333         return 0;
5334 }
5335
5336 static int
5337 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5338 {
5339         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5340         struct ixgbe_hw *hw = &adapter->hw;
5341         u16 value;
5342         int rc;
5343
5344         if (prtad != hw->phy.mdio.prtad)
5345                 return -EINVAL;
5346         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5347         if (!rc)
5348                 rc = value;
5349         return rc;
5350 }
5351
5352 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5353                             u16 addr, u16 value)
5354 {
5355         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5356         struct ixgbe_hw *hw = &adapter->hw;
5357
5358         if (prtad != hw->phy.mdio.prtad)
5359                 return -EINVAL;
5360         return hw->phy.ops.write_reg(hw, addr, devad, value);
5361 }
5362
5363 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5364 {
5365         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5366
5367         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5368 }
5369
5370 /**
5371  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5372  * netdev->dev_addrs
5373  * @netdev: network interface device structure
5374  *
5375  * Returns non-zero on failure
5376  **/
5377 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5378 {
5379         int err = 0;
5380         struct ixgbe_adapter *adapter = netdev_priv(dev);
5381         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5382
5383         if (is_valid_ether_addr(mac->san_addr)) {
5384                 rtnl_lock();
5385                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5386                 rtnl_unlock();
5387         }
5388         return err;
5389 }
5390
5391 /**
5392  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5393  * netdev->dev_addrs
5394  * @netdev: network interface device structure
5395  *
5396  * Returns non-zero on failure
5397  **/
5398 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5399 {
5400         int err = 0;
5401         struct ixgbe_adapter *adapter = netdev_priv(dev);
5402         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5403
5404         if (is_valid_ether_addr(mac->san_addr)) {
5405                 rtnl_lock();
5406                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5407                 rtnl_unlock();
5408         }
5409         return err;
5410 }
5411
5412 #ifdef CONFIG_NET_POLL_CONTROLLER
5413 /*
5414  * Polling 'interrupt' - used by things like netconsole to send skbs
5415  * without having to re-enable interrupts. It's not called while
5416  * the interrupt routine is executing.
5417  */
5418 static void ixgbe_netpoll(struct net_device *netdev)
5419 {
5420         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5421         int i;
5422
5423         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5424         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5425                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5426                 for (i = 0; i < num_q_vectors; i++) {
5427                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5428                         ixgbe_msix_clean_many(0, q_vector);
5429                 }
5430         } else {
5431                 ixgbe_intr(adapter->pdev->irq, netdev);
5432         }
5433         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5434 }
5435 #endif
5436
5437 static const struct net_device_ops ixgbe_netdev_ops = {
5438         .ndo_open               = ixgbe_open,
5439         .ndo_stop               = ixgbe_close,
5440         .ndo_start_xmit         = ixgbe_xmit_frame,
5441         .ndo_select_queue       = ixgbe_select_queue,
5442         .ndo_get_stats          = ixgbe_get_stats,
5443         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5444         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5445         .ndo_validate_addr      = eth_validate_addr,
5446         .ndo_set_mac_address    = ixgbe_set_mac,
5447         .ndo_change_mtu         = ixgbe_change_mtu,
5448         .ndo_tx_timeout         = ixgbe_tx_timeout,
5449         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5450         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5451         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5452         .ndo_do_ioctl           = ixgbe_ioctl,
5453 #ifdef CONFIG_NET_POLL_CONTROLLER
5454         .ndo_poll_controller    = ixgbe_netpoll,
5455 #endif
5456 #ifdef IXGBE_FCOE
5457         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5458         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5459         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5460         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5461 #endif /* IXGBE_FCOE */
5462 };
5463
5464 /**
5465  * ixgbe_probe - Device Initialization Routine
5466  * @pdev: PCI device information struct
5467  * @ent: entry in ixgbe_pci_tbl
5468  *
5469  * Returns 0 on success, negative on failure
5470  *
5471  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5472  * The OS initialization, configuring of the adapter private structure,
5473  * and a hardware reset occur.
5474  **/
5475 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5476                                  const struct pci_device_id *ent)
5477 {
5478         struct net_device *netdev;
5479         struct ixgbe_adapter *adapter = NULL;
5480         struct ixgbe_hw *hw;
5481         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5482         static int cards_found;
5483         int i, err, pci_using_dac;
5484 #ifdef IXGBE_FCOE
5485         u16 device_caps;
5486 #endif
5487         u32 part_num, eec;
5488
5489         err = pci_enable_device_mem(pdev);
5490         if (err)
5491                 return err;
5492
5493         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5494             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5495                 pci_using_dac = 1;
5496         } else {
5497                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5498                 if (err) {
5499                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5500                         if (err) {
5501                                 dev_err(&pdev->dev, "No usable DMA "
5502                                         "configuration, aborting\n");
5503                                 goto err_dma;
5504                         }
5505                 }
5506                 pci_using_dac = 0;
5507         }
5508
5509         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5510                                            IORESOURCE_MEM), ixgbe_driver_name);
5511         if (err) {
5512                 dev_err(&pdev->dev,
5513                         "pci_request_selected_regions failed 0x%x\n", err);
5514                 goto err_pci_reg;
5515         }
5516
5517         pci_enable_pcie_error_reporting(pdev);
5518
5519         pci_set_master(pdev);
5520         pci_save_state(pdev);
5521
5522         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5523         if (!netdev) {
5524                 err = -ENOMEM;
5525                 goto err_alloc_etherdev;
5526         }
5527
5528         SET_NETDEV_DEV(netdev, &pdev->dev);
5529
5530         pci_set_drvdata(pdev, netdev);
5531         adapter = netdev_priv(netdev);
5532
5533         adapter->netdev = netdev;
5534         adapter->pdev = pdev;
5535         hw = &adapter->hw;
5536         hw->back = adapter;
5537         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5538
5539         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5540                               pci_resource_len(pdev, 0));
5541         if (!hw->hw_addr) {
5542                 err = -EIO;
5543                 goto err_ioremap;
5544         }
5545
5546         for (i = 1; i <= 5; i++) {
5547                 if (pci_resource_len(pdev, i) == 0)
5548                         continue;
5549         }
5550
5551         netdev->netdev_ops = &ixgbe_netdev_ops;
5552         ixgbe_set_ethtool_ops(netdev);
5553         netdev->watchdog_timeo = 5 * HZ;
5554         strcpy(netdev->name, pci_name(pdev));
5555
5556         adapter->bd_number = cards_found;
5557
5558         /* Setup hw api */
5559         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5560         hw->mac.type  = ii->mac;
5561
5562         /* EEPROM */
5563         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5564         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5565         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5566         if (!(eec & (1 << 8)))
5567                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5568
5569         /* PHY */
5570         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5571         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5572         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5573         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5574         hw->phy.mdio.mmds = 0;
5575         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5576         hw->phy.mdio.dev = netdev;
5577         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5578         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5579
5580         /* set up this timer and work struct before calling get_invariants
5581          * which might start the timer
5582          */
5583         init_timer(&adapter->sfp_timer);
5584         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5585         adapter->sfp_timer.data = (unsigned long) adapter;
5586
5587         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5588
5589         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5590         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5591
5592         /* a new SFP+ module arrival, called from GPI SDP2 context */
5593         INIT_WORK(&adapter->sfp_config_module_task,
5594                   ixgbe_sfp_config_module_task);
5595
5596         ii->get_invariants(hw);
5597
5598         /* setup the private structure */
5599         err = ixgbe_sw_init(adapter);
5600         if (err)
5601                 goto err_sw_init;
5602
5603         /*
5604          * If there is a fan on this device and it has failed log the
5605          * failure.
5606          */
5607         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5608                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5609                 if (esdp & IXGBE_ESDP_SDP1)
5610                         DPRINTK(PROBE, CRIT,
5611                                 "Fan has stopped, replace the adapter\n");
5612         }
5613
5614         /* reset_hw fills in the perm_addr as well */
5615         err = hw->mac.ops.reset_hw(hw);
5616         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5617             hw->mac.type == ixgbe_mac_82598EB) {
5618                 /*
5619                  * Start a kernel thread to watch for a module to arrive.
5620                  * Only do this for 82598, since 82599 will generate
5621                  * interrupts on module arrival.
5622                  */
5623                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5624                 mod_timer(&adapter->sfp_timer,
5625                           round_jiffies(jiffies + (2 * HZ)));
5626                 err = 0;
5627         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5628                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5629                         "an unsupported SFP+ module type was detected.\n"
5630                         "Reload the driver after installing a supported "
5631                         "module.\n");
5632                 goto err_sw_init;
5633         } else if (err) {
5634                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5635                 goto err_sw_init;
5636         }
5637
5638         netdev->features = NETIF_F_SG |
5639                            NETIF_F_IP_CSUM |
5640                            NETIF_F_HW_VLAN_TX |
5641                            NETIF_F_HW_VLAN_RX |
5642                            NETIF_F_HW_VLAN_FILTER;
5643
5644         netdev->features |= NETIF_F_IPV6_CSUM;
5645         netdev->features |= NETIF_F_TSO;
5646         netdev->features |= NETIF_F_TSO6;
5647         netdev->features |= NETIF_F_GRO;
5648
5649         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5650                 netdev->features |= NETIF_F_SCTP_CSUM;
5651
5652         netdev->vlan_features |= NETIF_F_TSO;
5653         netdev->vlan_features |= NETIF_F_TSO6;
5654         netdev->vlan_features |= NETIF_F_IP_CSUM;
5655         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5656         netdev->vlan_features |= NETIF_F_SG;
5657
5658         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5659                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5660
5661 #ifdef CONFIG_IXGBE_DCB
5662         netdev->dcbnl_ops = &dcbnl_ops;
5663 #endif
5664
5665 #ifdef IXGBE_FCOE
5666         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5667                 if (hw->mac.ops.get_device_caps) {
5668                         hw->mac.ops.get_device_caps(hw, &device_caps);
5669                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5670                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5671                 }
5672         }
5673 #endif /* IXGBE_FCOE */
5674         if (pci_using_dac)
5675                 netdev->features |= NETIF_F_HIGHDMA;
5676
5677         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5678                 netdev->features |= NETIF_F_LRO;
5679
5680         /* make sure the EEPROM is good */
5681         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5682                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5683                 err = -EIO;
5684                 goto err_eeprom;
5685         }
5686
5687         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5688         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5689
5690         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5691                 dev_err(&pdev->dev, "invalid MAC address\n");
5692                 err = -EIO;
5693                 goto err_eeprom;
5694         }
5695
5696         init_timer(&adapter->watchdog_timer);
5697         adapter->watchdog_timer.function = &ixgbe_watchdog;
5698         adapter->watchdog_timer.data = (unsigned long)adapter;
5699
5700         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5701         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5702
5703         err = ixgbe_init_interrupt_scheme(adapter);
5704         if (err)
5705                 goto err_sw_init;
5706
5707         switch (pdev->device) {
5708         case IXGBE_DEV_ID_82599_KX4:
5709                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5710                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5711                 /* Enable ACPI wakeup in GRC */
5712                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5713                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5714                 break;
5715         default:
5716                 adapter->wol = 0;
5717                 break;
5718         }
5719         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5720
5721         /* pick up the PCI bus settings for reporting later */
5722         hw->mac.ops.get_bus_info(hw);
5723
5724         /* print bus type/speed/width info */
5725         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5726                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5727                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5728                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5729                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5730                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5731                  "Unknown"),
5732                 netdev->dev_addr);
5733         ixgbe_read_pba_num_generic(hw, &part_num);
5734         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5735                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5736                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5737                          (part_num >> 8), (part_num & 0xff));
5738         else
5739                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5740                          hw->mac.type, hw->phy.type,
5741                          (part_num >> 8), (part_num & 0xff));
5742
5743         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5744                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5745                          "this card is not sufficient for optimal "
5746                          "performance.\n");
5747                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5748                          "PCI-Express slot is required.\n");
5749         }
5750
5751         /* save off EEPROM version number */
5752         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5753
5754         /* reset the hardware with the new settings */
5755         err = hw->mac.ops.start_hw(hw);
5756
5757         if (err == IXGBE_ERR_EEPROM_VERSION) {
5758                 /* We are running on a pre-production device, log a warning */
5759                 dev_warn(&pdev->dev, "This device is a pre-production "
5760                          "adapter/LOM.  Please be aware there may be issues "
5761                          "associated with your hardware.  If you are "
5762                          "experiencing problems please contact your Intel or "
5763                          "hardware representative who provided you with this "
5764                          "hardware.\n");
5765         }
5766         strcpy(netdev->name, "eth%d");
5767         err = register_netdev(netdev);
5768         if (err)
5769                 goto err_register;
5770
5771         /* carrier off reporting is important to ethtool even BEFORE open */
5772         netif_carrier_off(netdev);
5773
5774         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5775             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5776                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5777
5778 #ifdef CONFIG_IXGBE_DCA
5779         if (dca_add_requester(&pdev->dev) == 0) {
5780                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5781                 ixgbe_setup_dca(adapter);
5782         }
5783 #endif
5784         /* add san mac addr to netdev */
5785         ixgbe_add_sanmac_netdev(netdev);
5786
5787         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5788         cards_found++;
5789         return 0;
5790
5791 err_register:
5792         ixgbe_release_hw_control(adapter);
5793         ixgbe_clear_interrupt_scheme(adapter);
5794 err_sw_init:
5795 err_eeprom:
5796         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5797         del_timer_sync(&adapter->sfp_timer);
5798         cancel_work_sync(&adapter->sfp_task);
5799         cancel_work_sync(&adapter->multispeed_fiber_task);
5800         cancel_work_sync(&adapter->sfp_config_module_task);
5801         iounmap(hw->hw_addr);
5802 err_ioremap:
5803         free_netdev(netdev);
5804 err_alloc_etherdev:
5805         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5806                                      IORESOURCE_MEM));
5807 err_pci_reg:
5808 err_dma:
5809         pci_disable_device(pdev);
5810         return err;
5811 }
5812
5813 /**
5814  * ixgbe_remove - Device Removal Routine
5815  * @pdev: PCI device information struct
5816  *
5817  * ixgbe_remove is called by the PCI subsystem to alert the driver
5818  * that it should release a PCI device.  The could be caused by a
5819  * Hot-Plug event, or because the driver is going to be removed from
5820  * memory.
5821  **/
5822 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5823 {
5824         struct net_device *netdev = pci_get_drvdata(pdev);
5825         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5826
5827         set_bit(__IXGBE_DOWN, &adapter->state);
5828         /* clear the module not found bit to make sure the worker won't
5829          * reschedule
5830          */
5831         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5832         del_timer_sync(&adapter->watchdog_timer);
5833
5834         del_timer_sync(&adapter->sfp_timer);
5835         cancel_work_sync(&adapter->watchdog_task);
5836         cancel_work_sync(&adapter->sfp_task);
5837         cancel_work_sync(&adapter->multispeed_fiber_task);
5838         cancel_work_sync(&adapter->sfp_config_module_task);
5839         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5840             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5841                 cancel_work_sync(&adapter->fdir_reinit_task);
5842         flush_scheduled_work();
5843
5844 #ifdef CONFIG_IXGBE_DCA
5845         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5846                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5847                 dca_remove_requester(&pdev->dev);
5848                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5849         }
5850
5851 #endif
5852 #ifdef IXGBE_FCOE
5853         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5854                 ixgbe_cleanup_fcoe(adapter);
5855
5856 #endif /* IXGBE_FCOE */
5857
5858         /* remove the added san mac */
5859         ixgbe_del_sanmac_netdev(netdev);
5860
5861         if (netdev->reg_state == NETREG_REGISTERED)
5862                 unregister_netdev(netdev);
5863
5864         ixgbe_clear_interrupt_scheme(adapter);
5865
5866         ixgbe_release_hw_control(adapter);
5867
5868         iounmap(adapter->hw.hw_addr);
5869         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5870                                      IORESOURCE_MEM));
5871
5872         DPRINTK(PROBE, INFO, "complete\n");
5873
5874         free_netdev(netdev);
5875
5876         pci_disable_pcie_error_reporting(pdev);
5877
5878         pci_disable_device(pdev);
5879 }
5880
5881 /**
5882  * ixgbe_io_error_detected - called when PCI error is detected
5883  * @pdev: Pointer to PCI device
5884  * @state: The current pci connection state
5885  *
5886  * This function is called after a PCI bus error affecting
5887  * this device has been detected.
5888  */
5889 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5890                                                 pci_channel_state_t state)
5891 {
5892         struct net_device *netdev = pci_get_drvdata(pdev);
5893         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5894
5895         netif_device_detach(netdev);
5896
5897         if (state == pci_channel_io_perm_failure)
5898                 return PCI_ERS_RESULT_DISCONNECT;
5899
5900         if (netif_running(netdev))
5901                 ixgbe_down(adapter);
5902         pci_disable_device(pdev);
5903
5904         /* Request a slot reset. */
5905         return PCI_ERS_RESULT_NEED_RESET;
5906 }
5907
5908 /**
5909  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5910  * @pdev: Pointer to PCI device
5911  *
5912  * Restart the card from scratch, as if from a cold-boot.
5913  */
5914 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5915 {
5916         struct net_device *netdev = pci_get_drvdata(pdev);
5917         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5918         pci_ers_result_t result;
5919         int err;
5920
5921         if (pci_enable_device_mem(pdev)) {
5922                 DPRINTK(PROBE, ERR,
5923                         "Cannot re-enable PCI device after reset.\n");
5924                 result = PCI_ERS_RESULT_DISCONNECT;
5925         } else {
5926                 pci_set_master(pdev);
5927                 pci_restore_state(pdev);
5928
5929                 pci_wake_from_d3(pdev, false);
5930
5931                 ixgbe_reset(adapter);
5932                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5933                 result = PCI_ERS_RESULT_RECOVERED;
5934         }
5935
5936         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5937         if (err) {
5938                 dev_err(&pdev->dev,
5939                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5940                 /* non-fatal, continue */
5941         }
5942
5943         return result;
5944 }
5945
5946 /**
5947  * ixgbe_io_resume - called when traffic can start flowing again.
5948  * @pdev: Pointer to PCI device
5949  *
5950  * This callback is called when the error recovery driver tells us that
5951  * its OK to resume normal operation.
5952  */
5953 static void ixgbe_io_resume(struct pci_dev *pdev)
5954 {
5955         struct net_device *netdev = pci_get_drvdata(pdev);
5956         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5957
5958         if (netif_running(netdev)) {
5959                 if (ixgbe_up(adapter)) {
5960                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5961                         return;
5962                 }
5963         }
5964
5965         netif_device_attach(netdev);
5966 }
5967
5968 static struct pci_error_handlers ixgbe_err_handler = {
5969         .error_detected = ixgbe_io_error_detected,
5970         .slot_reset = ixgbe_io_slot_reset,
5971         .resume = ixgbe_io_resume,
5972 };
5973
5974 static struct pci_driver ixgbe_driver = {
5975         .name     = ixgbe_driver_name,
5976         .id_table = ixgbe_pci_tbl,
5977         .probe    = ixgbe_probe,
5978         .remove   = __devexit_p(ixgbe_remove),
5979 #ifdef CONFIG_PM
5980         .suspend  = ixgbe_suspend,
5981         .resume   = ixgbe_resume,
5982 #endif
5983         .shutdown = ixgbe_shutdown,
5984         .err_handler = &ixgbe_err_handler
5985 };
5986
5987 /**
5988  * ixgbe_init_module - Driver Registration Routine
5989  *
5990  * ixgbe_init_module is the first routine called when the driver is
5991  * loaded. All it does is register with the PCI subsystem.
5992  **/
5993 static int __init ixgbe_init_module(void)
5994 {
5995         int ret;
5996         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5997                ixgbe_driver_string, ixgbe_driver_version);
5998
5999         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
6000
6001 #ifdef CONFIG_IXGBE_DCA
6002         dca_register_notify(&dca_notifier);
6003 #endif
6004
6005         ret = pci_register_driver(&ixgbe_driver);
6006         return ret;
6007 }
6008
6009 module_init(ixgbe_init_module);
6010
6011 /**
6012  * ixgbe_exit_module - Driver Exit Cleanup Routine
6013  *
6014  * ixgbe_exit_module is called just before the driver is removed
6015  * from memory.
6016  **/
6017 static void __exit ixgbe_exit_module(void)
6018 {
6019 #ifdef CONFIG_IXGBE_DCA
6020         dca_unregister_notify(&dca_notifier);
6021 #endif
6022         pci_unregister_driver(&ixgbe_driver);
6023 }
6024
6025 #ifdef CONFIG_IXGBE_DCA
6026 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
6027                             void *p)
6028 {
6029         int ret_val;
6030
6031         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
6032                                          __ixgbe_notify_dca);
6033
6034         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6035 }
6036
6037 #endif /* CONFIG_IXGBE_DCA */
6038 #ifdef DEBUG
6039 /**
6040  * ixgbe_get_hw_dev_name - return device name string
6041  * used by hardware layer to print debugging information
6042  **/
6043 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6044 {
6045         struct ixgbe_adapter *adapter = hw->back;
6046         return adapter->netdev->name;
6047 }
6048
6049 #endif
6050 module_exit(ixgbe_exit_module);
6051
6052 /* ixgbe_main.c */