drivers/net/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/delay.h>
  33 #include <linux/io.h>
  34
  35 #include "e1000_regs.h"
  36 #include "e1000_defines.h"
  37
  38 struct e1000_hw;
  39
  40 #define E1000_DEV_ID_82576                    0x10C9
  41 #define E1000_DEV_ID_82576_FIBER              0x10E6
  42 #define E1000_DEV_ID_82576_SERDES             0x10E7
  43 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
  44 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
  45 #define E1000_DEV_ID_82576_NS                 0x150A
  46 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
  47 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
  48 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
  49 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
  50 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
  51 #define E1000_DEV_ID_82580_COPPER             0x150E
  52 #define E1000_DEV_ID_82580_FIBER              0x150F
  53 #define E1000_DEV_ID_82580_SERDES             0x1510
  54 #define E1000_DEV_ID_82580_SGMII              0x1511
  55 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
  56 #define E1000_DEV_ID_I350_COPPER              0x1521
  57 #define E1000_DEV_ID_I350_FIBER               0x1522
  58 #define E1000_DEV_ID_I350_SERDES              0x1523
  59 #define E1000_DEV_ID_I350_SGMII               0x1524
  60
  61 #define E1000_REVISION_2 2
  62 #define E1000_REVISION_4 4
  63
  64 #define E1000_FUNC_0     0
  65 #define E1000_FUNC_1     1
  66 #define E1000_FUNC_2     2
  67 #define E1000_FUNC_3     3
  68
  69 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
  70 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  71 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
  72 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
  73
  74 enum e1000_mac_type {
  75         e1000_undefined = 0,
  76         e1000_82575,
  77         e1000_82576,
  78         e1000_82580,
  79         e1000_i350,
  80         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  81 };
  82
  83 enum e1000_media_type {
  84         e1000_media_type_unknown = 0,
  85         e1000_media_type_copper = 1,
  86         e1000_media_type_internal_serdes = 2,
  87         e1000_num_media_types
  88 };
  89
  90 enum e1000_nvm_type {
  91         e1000_nvm_unknown = 0,
  92         e1000_nvm_none,
  93         e1000_nvm_eeprom_spi,
  94         e1000_nvm_flash_hw,
  95         e1000_nvm_flash_sw
  96 };
  97
  98 enum e1000_nvm_override {
  99         e1000_nvm_override_none = 0,
 100         e1000_nvm_override_spi_small,
 101         e1000_nvm_override_spi_large,
 102 };
 103
 104 enum e1000_phy_type {
 105         e1000_phy_unknown = 0,
 106         e1000_phy_none,
 107         e1000_phy_m88,
 108         e1000_phy_igp,
 109         e1000_phy_igp_2,
 110         e1000_phy_gg82563,
 111         e1000_phy_igp_3,
 112         e1000_phy_ife,
 113         e1000_phy_82580,
 114 };
 115
 116 enum e1000_bus_type {
 117         e1000_bus_type_unknown = 0,
 118         e1000_bus_type_pci,
 119         e1000_bus_type_pcix,
 120         e1000_bus_type_pci_express,
 121         e1000_bus_type_reserved
 122 };
 123
 124 enum e1000_bus_speed {
 125         e1000_bus_speed_unknown = 0,
 126         e1000_bus_speed_33,
 127         e1000_bus_speed_66,
 128         e1000_bus_speed_100,
 129         e1000_bus_speed_120,
 130         e1000_bus_speed_133,
 131         e1000_bus_speed_2500,
 132         e1000_bus_speed_5000,
 133         e1000_bus_speed_reserved
 134 };
 135
 136 enum e1000_bus_width {
 137         e1000_bus_width_unknown = 0,
 138         e1000_bus_width_pcie_x1,
 139         e1000_bus_width_pcie_x2,
 140         e1000_bus_width_pcie_x4 = 4,
 141         e1000_bus_width_pcie_x8 = 8,
 142         e1000_bus_width_32,
 143         e1000_bus_width_64,
 144         e1000_bus_width_reserved
 145 };
 146
 147 enum e1000_1000t_rx_status {
 148         e1000_1000t_rx_status_not_ok = 0,
 149         e1000_1000t_rx_status_ok,
 150         e1000_1000t_rx_status_undefined = 0xFF
 151 };
 152
 153 enum e1000_rev_polarity {
 154         e1000_rev_polarity_normal = 0,
 155         e1000_rev_polarity_reversed,
 156         e1000_rev_polarity_undefined = 0xFF
 157 };
 158
 159 enum e1000_fc_mode {
 160         e1000_fc_none = 0,
 161         e1000_fc_rx_pause,
 162         e1000_fc_tx_pause,
 163         e1000_fc_full,
 164         e1000_fc_default = 0xFF
 165 };
 166
 167 /* Statistics counters collected by the MAC */
 168 struct e1000_hw_stats {
 169         u64 crcerrs;
 170         u64 algnerrc;
 171         u64 symerrs;
 172         u64 rxerrc;
 173         u64 mpc;
 174         u64 scc;
 175         u64 ecol;
 176         u64 mcc;
 177         u64 latecol;
 178         u64 colc;
 179         u64 dc;
 180         u64 tncrs;
 181         u64 sec;
 182         u64 cexterr;
 183         u64 rlec;
 184         u64 xonrxc;
 185         u64 xontxc;
 186         u64 xoffrxc;
 187         u64 xofftxc;
 188         u64 fcruc;
 189         u64 prc64;
 190         u64 prc127;
 191         u64 prc255;
 192         u64 prc511;
 193         u64 prc1023;
 194         u64 prc1522;
 195         u64 gprc;
 196         u64 bprc;
 197         u64 mprc;
 198         u64 gptc;
 199         u64 gorc;
 200         u64 gotc;
 201         u64 rnbc;
 202         u64 ruc;
 203         u64 rfc;
 204         u64 roc;
 205         u64 rjc;
 206         u64 mgprc;
 207         u64 mgpdc;
 208         u64 mgptc;
 209         u64 tor;
 210         u64 tot;
 211         u64 tpr;
 212         u64 tpt;
 213         u64 ptc64;
 214         u64 ptc127;
 215         u64 ptc255;
 216         u64 ptc511;
 217         u64 ptc1023;
 218         u64 ptc1522;
 219         u64 mptc;
 220         u64 bptc;
 221         u64 tsctc;
 222         u64 tsctfc;
 223         u64 iac;
 224         u64 icrxptc;
 225         u64 icrxatc;
 226         u64 ictxptc;
 227         u64 ictxatc;
 228         u64 ictxqec;
 229         u64 ictxqmtc;
 230         u64 icrxdmtc;
 231         u64 icrxoc;
 232         u64 cbtmpc;
 233         u64 htdpmc;
 234         u64 cbrdpc;
 235         u64 cbrmpc;
 236         u64 rpthc;
 237         u64 hgptc;
 238         u64 htcbdpc;
 239         u64 hgorc;
 240         u64 hgotc;
 241         u64 lenerrs;
 242         u64 scvpc;
 243         u64 hrmpc;
 244         u64 doosync;
 245 };
 246
 247 struct e1000_phy_stats {
 248         u32 idle_errors;
 249         u32 receive_errors;
 250 };
 251
 252 struct e1000_host_mng_dhcp_cookie {
 253         u32 signature;
 254         u8  status;
 255         u8  reserved0;
 256         u16 vlan_id;
 257         u32 reserved1;
 258         u16 reserved2;
 259         u8  reserved3;
 260         u8  checksum;
 261 };
 262
 263 /* Host Interface "Rev 1" */
 264 struct e1000_host_command_header {
 265         u8 command_id;
 266         u8 command_length;
 267         u8 command_options;
 268         u8 checksum;
 269 };
 270
 271 #define E1000_HI_MAX_DATA_LENGTH     252
 272 struct e1000_host_command_info {
 273         struct e1000_host_command_header command_header;
 274         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 275 };
 276
 277 /* Host Interface "Rev 2" */
 278 struct e1000_host_mng_command_header {
 279         u8  command_id;
 280         u8  checksum;
 281         u16 reserved1;
 282         u16 reserved2;
 283         u16 command_length;
 284 };
 285
 286 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 287 struct e1000_host_mng_command_info {
 288         struct e1000_host_mng_command_header command_header;
 289         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 290 };
 291
 292 #include "e1000_mac.h"
 293 #include "e1000_phy.h"
 294 #include "e1000_nvm.h"
 295 #include "e1000_mbx.h"
 296
 297 struct e1000_mac_operations {
 298         s32  (*check_for_link)(struct e1000_hw *);
 299         s32  (*reset_hw)(struct e1000_hw *);
 300         s32  (*init_hw)(struct e1000_hw *);
 301         bool (*check_mng_mode)(struct e1000_hw *);
 302         s32  (*setup_physical_interface)(struct e1000_hw *);
 303         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 304         s32  (*read_mac_addr)(struct e1000_hw *);
 305         s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
 306 };
 307
 308 struct e1000_phy_operations {
 309         s32  (*acquire)(struct e1000_hw *);
 310         s32  (*check_polarity)(struct e1000_hw *);
 311         s32  (*check_reset_block)(struct e1000_hw *);
 312         s32  (*force_speed_duplex)(struct e1000_hw *);
 313         s32  (*get_cfg_done)(struct e1000_hw *hw);
 314         s32  (*get_cable_length)(struct e1000_hw *);
 315         s32  (*get_phy_info)(struct e1000_hw *);
 316         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 317         void (*release)(struct e1000_hw *);
 318         s32  (*reset)(struct e1000_hw *);
 319         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 320         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 321         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 322 };
 323
 324 struct e1000_nvm_operations {
 325         s32  (*acquire)(struct e1000_hw *);
 326         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 327         void (*release)(struct e1000_hw *);
 328         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 329 };
 330
 331 struct e1000_info {
 332         s32 (*get_invariants)(struct e1000_hw *);
 333         struct e1000_mac_operations *mac_ops;
 334         struct e1000_phy_operations *phy_ops;
 335         struct e1000_nvm_operations *nvm_ops;
 336 };
 337
 338 extern const struct e1000_info e1000_82575_info;
 339
 340 struct e1000_mac_info {
 341         struct e1000_mac_operations ops;
 342
 343         u8 addr[6];
 344         u8 perm_addr[6];
 345
 346         enum e1000_mac_type type;
 347
 348         u32 ledctl_default;
 349         u32 ledctl_mode1;
 350         u32 ledctl_mode2;
 351         u32 mc_filter_type;
 352         u32 txcw;
 353
 354         u16 mta_reg_count;
 355         u16 uta_reg_count;
 356
 357         /* Maximum size of the MTA register table in all supported adapters */
 358         #define MAX_MTA_REG 128
 359         u32 mta_shadow[MAX_MTA_REG];
 360         u16 rar_entry_count;
 361
 362         u8  forced_speed_duplex;
 363
 364         bool adaptive_ifs;
 365         bool arc_subsystem_valid;
 366         bool asf_firmware_present;
 367         bool autoneg;
 368         bool autoneg_failed;
 369         bool disable_hw_init_bits;
 370         bool get_link_status;
 371         bool ifs_params_forced;
 372         bool in_ifs_mode;
 373         bool report_tx_early;
 374         bool serdes_has_link;
 375         bool tx_pkt_filtering;
 376 };
 377
 378 struct e1000_phy_info {
 379         struct e1000_phy_operations ops;
 380
 381         enum e1000_phy_type type;
 382
 383         enum e1000_1000t_rx_status local_rx;
 384         enum e1000_1000t_rx_status remote_rx;
 385         enum e1000_ms_type ms_type;
 386         enum e1000_ms_type original_ms_type;
 387         enum e1000_rev_polarity cable_polarity;
 388         enum e1000_smart_speed smart_speed;
 389
 390         u32 addr;
 391         u32 id;
 392         u32 reset_delay_us; /* in usec */
 393         u32 revision;
 394
 395         enum e1000_media_type media_type;
 396
 397         u16 autoneg_advertised;
 398         u16 autoneg_mask;
 399         u16 cable_length;
 400         u16 max_cable_length;
 401         u16 min_cable_length;
 402
 403         u8 mdix;
 404
 405         bool disable_polarity_correction;
 406         bool is_mdix;
 407         bool polarity_correction;
 408         bool reset_disable;
 409         bool speed_downgraded;
 410         bool autoneg_wait_to_complete;
 411 };
 412
 413 struct e1000_nvm_info {
 414         struct e1000_nvm_operations ops;
 415
 416         enum e1000_nvm_type type;
 417         enum e1000_nvm_override override;
 418
 419         u32 flash_bank_size;
 420         u32 flash_base_addr;
 421
 422         u16 word_size;
 423         u16 delay_usec;
 424         u16 address_bits;
 425         u16 opcode_bits;
 426         u16 page_size;
 427 };
 428
 429 struct e1000_bus_info {
 430         enum e1000_bus_type type;
 431         enum e1000_bus_speed speed;
 432         enum e1000_bus_width width;
 433
 434         u32 snoop;
 435
 436         u16 func;
 437         u16 pci_cmd_word;
 438 };
 439
 440 struct e1000_fc_info {
 441         u32 high_water;     /* Flow control high-water mark */
 442         u32 low_water;      /* Flow control low-water mark */
 443         u16 pause_time;     /* Flow control pause timer */
 444         bool send_xon;      /* Flow control send XON */
 445         bool strict_ieee;   /* Strict IEEE mode */
 446         enum e1000_fc_mode current_mode; /* Type of flow control */
 447         enum e1000_fc_mode requested_mode;
 448 };
 449
 450 struct e1000_mbx_operations {
 451         s32 (*init_params)(struct e1000_hw *hw);
 452         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 453         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 454         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 455         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 456         s32 (*check_for_msg)(struct e1000_hw *, u16);
 457         s32 (*check_for_ack)(struct e1000_hw *, u16);
 458         s32 (*check_for_rst)(struct e1000_hw *, u16);
 459 };
 460
 461 struct e1000_mbx_stats {
 462         u32 msgs_tx;
 463         u32 msgs_rx;
 464
 465         u32 acks;
 466         u32 reqs;
 467         u32 rsts;
 468 };
 469
 470 struct e1000_mbx_info {
 471         struct e1000_mbx_operations ops;
 472         struct e1000_mbx_stats stats;
 473         u32 timeout;
 474         u32 usec_delay;
 475         u16 size;
 476 };
 477
 478 struct e1000_dev_spec_82575 {
 479         bool sgmii_active;
 480         bool global_device_reset;
 481 };
 482
 483 struct e1000_hw {
 484         void *back;
 485
 486         u8 __iomem *hw_addr;
 487         u8 __iomem *flash_address;
 488         unsigned long io_base;
 489
 490         struct e1000_mac_info  mac;
 491         struct e1000_fc_info   fc;
 492         struct e1000_phy_info  phy;
 493         struct e1000_nvm_info  nvm;
 494         struct e1000_bus_info  bus;
 495         struct e1000_mbx_info mbx;
 496         struct e1000_host_mng_dhcp_cookie mng_cookie;
 497
 498         union {
 499                 struct e1000_dev_spec_82575     _82575;
 500         } dev_spec;
 501
 502         u16 device_id;
 503         u16 subsystem_vendor_id;
 504         u16 subsystem_device_id;
 505         u16 vendor_id;
 506
 507         u8  revision_id;
 508 };
 509
 510 #ifdef DEBUG
 511 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 512 #define hw_dbg(format, arg...) \
 513         printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
 514 #else
 515 #define hw_dbg(format, arg...)
 516 #endif
 517 #endif
 518 /* These functions must be implemented by drivers */
 519 s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 520 s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);