2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/netdevice.h>
26 #include "wq_enet_desc.h"
27 #include "rq_enet_desc.h"
28 #include "cq_enet_desc.h"
29 #include "vnic_resource.h"
30 #include "vnic_enet.h"
35 #include "vnic_intr.h"
36 #include "vnic_stats.h"
42 int enic_get_vnic_config(struct enic *enic)
44 struct vnic_enet_config *c = &enic->config;
47 err = vnic_dev_mac_addr(enic->vdev, enic->mac_addr);
49 dev_err(enic_get_dev(enic),
50 "Error getting MAC addr, %d\n", err);
54 #define GET_CONFIG(m) \
56 err = vnic_dev_spec(enic->vdev, \
57 offsetof(struct vnic_enet_config, m), \
58 sizeof(c->m), &c->m); \
60 dev_err(enic_get_dev(enic), \
61 "Error getting %s, %d\n", #m, err); \
67 GET_CONFIG(wq_desc_count);
68 GET_CONFIG(rq_desc_count);
70 GET_CONFIG(intr_timer_type);
71 GET_CONFIG(intr_mode);
72 GET_CONFIG(intr_timer_usec);
76 min_t(u32, ENIC_MAX_WQ_DESCS,
77 max_t(u32, ENIC_MIN_WQ_DESCS,
79 c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
82 min_t(u32, ENIC_MAX_RQ_DESCS,
83 max_t(u32, ENIC_MIN_RQ_DESCS,
85 c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
89 c->mtu = min_t(u16, ENIC_MAX_MTU,
90 max_t(u16, ENIC_MIN_MTU,
93 c->intr_timer_usec = min_t(u32,
94 INTR_COALESCE_HW_TO_USEC(VNIC_INTR_TIMER_MAX),
97 dev_info(enic_get_dev(enic), "vNIC MAC addr %pM wq/rq %d/%d\n",
98 enic->mac_addr, c->wq_desc_count, c->rq_desc_count);
99 dev_info(enic_get_dev(enic), "vNIC mtu %d csum tx/rx %d/%d "
100 "tso/lro %d/%d intr timer %d usec\n",
101 c->mtu, ENIC_SETTING(enic, TXCSUM),
102 ENIC_SETTING(enic, RXCSUM), ENIC_SETTING(enic, TSO),
103 ENIC_SETTING(enic, LRO), c->intr_timer_usec);
108 int enic_add_vlan(struct enic *enic, u16 vlanid)
110 u64 a0 = vlanid, a1 = 0;
114 err = vnic_dev_cmd(enic->vdev, CMD_VLAN_ADD, &a0, &a1, wait);
116 dev_err(enic_get_dev(enic), "Can't add vlan id, %d\n", err);
121 int enic_del_vlan(struct enic *enic, u16 vlanid)
123 u64 a0 = vlanid, a1 = 0;
127 err = vnic_dev_cmd(enic->vdev, CMD_VLAN_DEL, &a0, &a1, wait);
129 dev_err(enic_get_dev(enic), "Can't delete vlan id, %d\n", err);
134 int enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,
135 u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,
142 vnic_set_nic_cfg(&nic_cfg, rss_default_cpu,
143 rss_hash_type, rss_hash_bits, rss_base_cpu,
144 rss_enable, tso_ipid_split_en, ig_vlan_strip_en);
149 return vnic_dev_cmd(enic->vdev, CMD_NIC_CFG, &a0, &a1, wait);
152 int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len)
154 u64 a0 = (u64)key_pa, a1 = len;
157 return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
160 int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len)
162 u64 a0 = (u64)cpu_pa, a1 = len;
165 return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
168 void enic_free_vnic_resources(struct enic *enic)
172 for (i = 0; i < enic->wq_count; i++)
173 vnic_wq_free(&enic->wq[i]);
174 for (i = 0; i < enic->rq_count; i++)
175 vnic_rq_free(&enic->rq[i]);
176 for (i = 0; i < enic->cq_count; i++)
177 vnic_cq_free(&enic->cq[i]);
178 for (i = 0; i < enic->intr_count; i++)
179 vnic_intr_free(&enic->intr[i]);
182 void enic_get_res_counts(struct enic *enic)
184 enic->wq_count = min_t(int,
185 vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ),
187 enic->rq_count = min_t(int,
188 vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ),
190 enic->cq_count = min_t(int,
191 vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ),
193 enic->intr_count = min_t(int,
194 vnic_dev_get_res_count(enic->vdev, RES_TYPE_INTR_CTRL),
197 dev_info(enic_get_dev(enic),
198 "vNIC resources avail: wq %d rq %d cq %d intr %d\n",
199 enic->wq_count, enic->rq_count,
200 enic->cq_count, enic->intr_count);
203 void enic_init_vnic_resources(struct enic *enic)
205 enum vnic_dev_intr_mode intr_mode;
206 unsigned int mask_on_assertion;
207 unsigned int interrupt_offset;
208 unsigned int error_interrupt_enable;
209 unsigned int error_interrupt_offset;
210 unsigned int cq_index;
213 intr_mode = vnic_dev_get_intr_mode(enic->vdev);
215 /* Init RQ/WQ resources.
217 * RQ[0 - n-1] point to CQ[0 - n-1]
218 * WQ[0 - m-1] point to CQ[n - n+m-1]
220 * Error interrupt is not enabled for MSI.
224 case VNIC_DEV_INTR_MODE_INTX:
225 case VNIC_DEV_INTR_MODE_MSIX:
226 error_interrupt_enable = 1;
227 error_interrupt_offset = enic->intr_count - 2;
230 error_interrupt_enable = 0;
231 error_interrupt_offset = 0;
235 for (i = 0; i < enic->rq_count; i++) {
237 vnic_rq_init(&enic->rq[i],
239 error_interrupt_enable,
240 error_interrupt_offset);
243 for (i = 0; i < enic->wq_count; i++) {
244 cq_index = enic->rq_count + i;
245 vnic_wq_init(&enic->wq[i],
247 error_interrupt_enable,
248 error_interrupt_offset);
253 * CQ[0 - n+m-1] point to INTR[0] for INTx, MSI
254 * CQ[0 - n+m-1] point to INTR[0 - n+m-1] for MSI-X
257 for (i = 0; i < enic->cq_count; i++) {
260 case VNIC_DEV_INTR_MODE_MSIX:
261 interrupt_offset = i;
264 interrupt_offset = 0;
268 vnic_cq_init(&enic->cq[i],
269 0 /* flow_control_enable */,
270 1 /* color_enable */,
273 1 /* cq_tail_color */,
274 1 /* interrupt_enable */,
275 1 /* cq_entry_enable */,
276 0 /* cq_message_enable */,
278 0 /* cq_message_addr */);
281 /* Init INTR resources
283 * mask_on_assertion is not used for INTx due to the level-
284 * triggered nature of INTx
288 case VNIC_DEV_INTR_MODE_MSI:
289 case VNIC_DEV_INTR_MODE_MSIX:
290 mask_on_assertion = 1;
293 mask_on_assertion = 0;
297 for (i = 0; i < enic->intr_count; i++) {
298 vnic_intr_init(&enic->intr[i],
299 INTR_COALESCE_USEC_TO_HW(enic->config.intr_timer_usec),
300 enic->config.intr_timer_type,
305 int enic_alloc_vnic_resources(struct enic *enic)
307 enum vnic_dev_intr_mode intr_mode;
311 intr_mode = vnic_dev_get_intr_mode(enic->vdev);
313 dev_info(enic_get_dev(enic), "vNIC resources used: "
314 "wq %d rq %d cq %d intr %d intr mode %s\n",
315 enic->wq_count, enic->rq_count,
316 enic->cq_count, enic->intr_count,
317 intr_mode == VNIC_DEV_INTR_MODE_INTX ? "legacy PCI INTx" :
318 intr_mode == VNIC_DEV_INTR_MODE_MSI ? "MSI" :
319 intr_mode == VNIC_DEV_INTR_MODE_MSIX ? "MSI-X" :
322 /* Allocate queue resources
325 for (i = 0; i < enic->wq_count; i++) {
326 err = vnic_wq_alloc(enic->vdev, &enic->wq[i], i,
327 enic->config.wq_desc_count,
328 sizeof(struct wq_enet_desc));
330 goto err_out_cleanup;
333 for (i = 0; i < enic->rq_count; i++) {
334 err = vnic_rq_alloc(enic->vdev, &enic->rq[i], i,
335 enic->config.rq_desc_count,
336 sizeof(struct rq_enet_desc));
338 goto err_out_cleanup;
341 for (i = 0; i < enic->cq_count; i++) {
342 if (i < enic->rq_count)
343 err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
344 enic->config.rq_desc_count,
345 sizeof(struct cq_enet_rq_desc));
347 err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
348 enic->config.wq_desc_count,
349 sizeof(struct cq_enet_wq_desc));
351 goto err_out_cleanup;
354 for (i = 0; i < enic->intr_count; i++) {
355 err = vnic_intr_alloc(enic->vdev, &enic->intr[i], i);
357 goto err_out_cleanup;
360 /* Hook remaining resource
363 enic->legacy_pba = vnic_dev_get_res(enic->vdev,
364 RES_TYPE_INTR_PBA_LEGACY, 0);
365 if (!enic->legacy_pba && intr_mode == VNIC_DEV_INTR_MODE_INTX) {
366 dev_err(enic_get_dev(enic),
367 "Failed to hook legacy pba resource\n");
369 goto err_out_cleanup;
375 enic_free_vnic_resources(enic);