drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include "e1000.h"
  58
  59 #define ICH_FLASH_GFPREG                0x0000
  60 #define ICH_FLASH_HSFSTS                0x0004
  61 #define ICH_FLASH_HSFCTL                0x0006
  62 #define ICH_FLASH_FADDR                 0x0008
  63 #define ICH_FLASH_FDATA0                0x0010
  64 #define ICH_FLASH_PR0                   0x0074
  65
  66 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  69 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  70 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  71
  72 #define ICH_CYCLE_READ                  0
  73 #define ICH_CYCLE_WRITE                 2
  74 #define ICH_CYCLE_ERASE                 3
  75
  76 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  77 #define FLASH_SECTOR_ADDR_SHIFT         12
  78
  79 #define ICH_FLASH_SEG_SIZE_256          256
  80 #define ICH_FLASH_SEG_SIZE_4K           4096
  81 #define ICH_FLASH_SEG_SIZE_8K           8192
  82 #define ICH_FLASH_SEG_SIZE_64K          65536
  83
  84
  85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  86
  87 #define E1000_ICH_MNG_IAMT_MODE         0x2
  88
  89 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  90                                  (ID_LED_DEF1_OFF2 <<  8) | \
  91                                  (ID_LED_DEF1_ON2  <<  4) | \
  92                                  (ID_LED_DEF1_DEF2))
  93
  94 #define E1000_ICH_NVM_SIG_WORD          0x13
  95 #define E1000_ICH_NVM_SIG_MASK          0xC000
  96 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
  97 #define E1000_ICH_NVM_SIG_VALUE         0x80
  98
  99 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 100
 101 #define E1000_FEXTNVM_SW_CONFIG         1
 102 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 103
 104 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 105
 106 #define E1000_ICH_RAR_ENTRIES           7
 107
 108 #define PHY_PAGE_SHIFT 5
 109 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 110                            ((reg) & MAX_PHY_REG_ADDRESS))
 111 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 112 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 113
 114 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 115 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 116 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 117
 118 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 119
 120 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 121
 122 /* SMBus Address Phy Register */
 123 #define HV_SMB_ADDR            PHY_REG(768, 26)
 124 #define HV_SMB_ADDR_PEC_EN     0x0200
 125 #define HV_SMB_ADDR_VALID      0x0080
 126
 127 /* Strapping Option Register - RO */
 128 #define E1000_STRAP                     0x0000C
 129 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 130 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 131
 132 /* OEM Bits Phy Register */
 133 #define HV_OEM_BITS            PHY_REG(768, 25)
 134 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 135 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 136 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 137
 138 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 139 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 140
 141 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 142 /* Offset 04h HSFSTS */
 143 union ich8_hws_flash_status {
 144         struct ich8_hsfsts {
 145                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 146                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 147                 u16 dael       :1; /* bit 2 Direct Access error Log */
 148                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 149                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 150                 u16 reserved1  :2; /* bit 13:6 Reserved */
 151                 u16 reserved2  :6; /* bit 13:6 Reserved */
 152                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 153                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 154         } hsf_status;
 155         u16 regval;
 156 };
 157
 158 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 159 /* Offset 06h FLCTL */
 160 union ich8_hws_flash_ctrl {
 161         struct ich8_hsflctl {
 162                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 163                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 164                 u16 reserved   :5;   /* 7:3 Reserved  */
 165                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 166                 u16 flockdn    :6;   /* 15:10 Reserved */
 167         } hsf_ctrl;
 168         u16 regval;
 169 };
 170
 171 /* ICH Flash Region Access Permissions */
 172 union ich8_hws_flash_regacc {
 173         struct ich8_flracc {
 174                 u32 grra      :8; /* 0:7 GbE region Read Access */
 175                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 176                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 177                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 178         } hsf_flregacc;
 179         u16 regval;
 180 };
 181
 182 /* ICH Flash Protected Region */
 183 union ich8_flash_protected_range {
 184         struct ich8_pr {
 185                 u32 base:13;     /* 0:12 Protected Range Base */
 186                 u32 reserved1:2; /* 13:14 Reserved */
 187                 u32 rpe:1;       /* 15 Read Protection Enable */
 188                 u32 limit:13;    /* 16:28 Protected Range Limit */
 189                 u32 reserved2:2; /* 29:30 Reserved */
 190                 u32 wpe:1;       /* 31 Write Protection Enable */
 191         } range;
 192         u32 regval;
 193 };
 194
 195 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 196 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 197 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 198 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 199 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 200 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 201                                                 u32 offset, u8 byte);
 202 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 203                                          u8 *data);
 204 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 205                                          u16 *data);
 206 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 207                                          u8 size, u16 *data);
 208 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 209 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 210 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 211 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 212 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 213 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 214 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 215 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 216 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 217 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 218 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 219 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 220 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 221 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 222
 223 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 224 {
 225         return readw(hw->flash_address + reg);
 226 }
 227
 228 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 229 {
 230         return readl(hw->flash_address + reg);
 231 }
 232
 233 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 234 {
 235         writew(val, hw->flash_address + reg);
 236 }
 237
 238 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 239 {
 240         writel(val, hw->flash_address + reg);
 241 }
 242
 243 #define er16flash(reg)          __er16flash(hw, (reg))
 244 #define er32flash(reg)          __er32flash(hw, (reg))
 245 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 246 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 247
 248 /**
 249  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 250  *  @hw: pointer to the HW structure
 251  *
 252  *  Initialize family-specific PHY parameters and function pointers.
 253  **/
 254 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 255 {
 256         struct e1000_phy_info *phy = &hw->phy;
 257         s32 ret_val = 0;
 258
 259         phy->addr                     = 1;
 260         phy->reset_delay_us           = 100;
 261
 262         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 263         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 264         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 265         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 266         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 267         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 268         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 269         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 270
 271         phy->id = e1000_phy_unknown;
 272         e1000e_get_phy_id(hw);
 273         phy->type = e1000e_get_phy_type_from_id(phy->id);
 274
 275         if (phy->type == e1000_phy_82577) {
 276                 phy->ops.check_polarity = e1000_check_polarity_82577;
 277                 phy->ops.force_speed_duplex =
 278                         e1000_phy_force_speed_duplex_82577;
 279                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 280                 phy->ops.get_info = e1000_get_phy_info_82577;
 281                 phy->ops.commit = e1000e_phy_sw_reset;
 282         }
 283
 284         return ret_val;
 285 }
 286
 287 /**
 288  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 289  *  @hw: pointer to the HW structure
 290  *
 291  *  Initialize family-specific PHY parameters and function pointers.
 292  **/
 293 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 294 {
 295         struct e1000_phy_info *phy = &hw->phy;
 296         s32 ret_val;
 297         u16 i = 0;
 298
 299         phy->addr                       = 1;
 300         phy->reset_delay_us             = 100;
 301
 302         /*
 303          * We may need to do this twice - once for IGP and if that fails,
 304          * we'll set BM func pointers and try again
 305          */
 306         ret_val = e1000e_determine_phy_address(hw);
 307         if (ret_val) {
 308                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 309                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 310                 ret_val = e1000e_determine_phy_address(hw);
 311                 if (ret_val)
 312                         return ret_val;
 313         }
 314
 315         phy->id = 0;
 316         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 317                (i++ < 100)) {
 318                 msleep(1);
 319                 ret_val = e1000e_get_phy_id(hw);
 320                 if (ret_val)
 321                         return ret_val;
 322         }
 323
 324         /* Verify phy id */
 325         switch (phy->id) {
 326         case IGP03E1000_E_PHY_ID:
 327                 phy->type = e1000_phy_igp_3;
 328                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 329                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 330                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 331                 break;
 332         case IFE_E_PHY_ID:
 333         case IFE_PLUS_E_PHY_ID:
 334         case IFE_C_E_PHY_ID:
 335                 phy->type = e1000_phy_ife;
 336                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 337                 break;
 338         case BME1000_E_PHY_ID:
 339                 phy->type = e1000_phy_bm;
 340                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 341                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 342                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 343                 phy->ops.commit = e1000e_phy_sw_reset;
 344                 break;
 345         default:
 346                 return -E1000_ERR_PHY;
 347                 break;
 348         }
 349
 350         phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
 351
 352         return 0;
 353 }
 354
 355 /**
 356  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 357  *  @hw: pointer to the HW structure
 358  *
 359  *  Initialize family-specific NVM parameters and function
 360  *  pointers.
 361  **/
 362 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 363 {
 364         struct e1000_nvm_info *nvm = &hw->nvm;
 365         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 366         u32 gfpreg, sector_base_addr, sector_end_addr;
 367         u16 i;
 368
 369         /* Can't read flash registers if the register set isn't mapped. */
 370         if (!hw->flash_address) {
 371                 e_dbg("ERROR: Flash registers not mapped\n");
 372                 return -E1000_ERR_CONFIG;
 373         }
 374
 375         nvm->type = e1000_nvm_flash_sw;
 376
 377         gfpreg = er32flash(ICH_FLASH_GFPREG);
 378
 379         /*
 380          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 381          * Add 1 to sector_end_addr since this sector is included in
 382          * the overall size.
 383          */
 384         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 385         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 386
 387         /* flash_base_addr is byte-aligned */
 388         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 389
 390         /*
 391          * find total size of the NVM, then cut in half since the total
 392          * size represents two separate NVM banks.
 393          */
 394         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 395                                 << FLASH_SECTOR_ADDR_SHIFT;
 396         nvm->flash_bank_size /= 2;
 397         /* Adjust to word count */
 398         nvm->flash_bank_size /= sizeof(u16);
 399
 400         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 401
 402         /* Clear shadow ram */
 403         for (i = 0; i < nvm->word_size; i++) {
 404                 dev_spec->shadow_ram[i].modified = false;
 405                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 406         }
 407
 408         return 0;
 409 }
 410
 411 /**
 412  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 413  *  @hw: pointer to the HW structure
 414  *
 415  *  Initialize family-specific MAC parameters and function
 416  *  pointers.
 417  **/
 418 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 419 {
 420         struct e1000_hw *hw = &adapter->hw;
 421         struct e1000_mac_info *mac = &hw->mac;
 422
 423         /* Set media type function pointer */
 424         hw->phy.media_type = e1000_media_type_copper;
 425
 426         /* Set mta register count */
 427         mac->mta_reg_count = 32;
 428         /* Set rar entry count */
 429         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 430         if (mac->type == e1000_ich8lan)
 431                 mac->rar_entry_count--;
 432         /* Set if manageability features are enabled. */
 433         mac->arc_subsystem_valid = true;
 434
 435         /* LED operations */
 436         switch (mac->type) {
 437         case e1000_ich8lan:
 438         case e1000_ich9lan:
 439         case e1000_ich10lan:
 440                 /* ID LED init */
 441                 mac->ops.id_led_init = e1000e_id_led_init;
 442                 /* setup LED */
 443                 mac->ops.setup_led = e1000e_setup_led_generic;
 444                 /* cleanup LED */
 445                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 446                 /* turn on/off LED */
 447                 mac->ops.led_on = e1000_led_on_ich8lan;
 448                 mac->ops.led_off = e1000_led_off_ich8lan;
 449                 break;
 450         case e1000_pchlan:
 451                 /* ID LED init */
 452                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 453                 /* setup LED */
 454                 mac->ops.setup_led = e1000_setup_led_pchlan;
 455                 /* cleanup LED */
 456                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 457                 /* turn on/off LED */
 458                 mac->ops.led_on = e1000_led_on_pchlan;
 459                 mac->ops.led_off = e1000_led_off_pchlan;
 460                 break;
 461         default:
 462                 break;
 463         }
 464
 465         /* Enable PCS Lock-loss workaround for ICH8 */
 466         if (mac->type == e1000_ich8lan)
 467                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 468
 469         return 0;
 470 }
 471
 472 /**
 473  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 474  *  @hw: pointer to the HW structure
 475  *
 476  *  Checks to see of the link status of the hardware has changed.  If a
 477  *  change in link status has been detected, then we read the PHY registers
 478  *  to get the current speed/duplex if link exists.
 479  **/
 480 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 481 {
 482         struct e1000_mac_info *mac = &hw->mac;
 483         s32 ret_val;
 484         bool link;
 485
 486         /*
 487          * We only want to go out to the PHY registers to see if Auto-Neg
 488          * has completed and/or if our link status has changed.  The
 489          * get_link_status flag is set upon receiving a Link Status
 490          * Change or Rx Sequence Error interrupt.
 491          */
 492         if (!mac->get_link_status) {
 493                 ret_val = 0;
 494                 goto out;
 495         }
 496
 497         /*
 498          * First we want to see if the MII Status Register reports
 499          * link.  If so, then we want to get the current speed/duplex
 500          * of the PHY.
 501          */
 502         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 503         if (ret_val)
 504                 goto out;
 505
 506         if (hw->mac.type == e1000_pchlan) {
 507                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 508                 if (ret_val)
 509                         goto out;
 510         }
 511
 512         if (!link)
 513                 goto out; /* No link detected */
 514
 515         mac->get_link_status = false;
 516
 517         if (hw->phy.type == e1000_phy_82578) {
 518                 ret_val = e1000_link_stall_workaround_hv(hw);
 519                 if (ret_val)
 520                         goto out;
 521         }
 522
 523         /*
 524          * Check if there was DownShift, must be checked
 525          * immediately after link-up
 526          */
 527         e1000e_check_downshift(hw);
 528
 529         /*
 530          * If we are forcing speed/duplex, then we simply return since
 531          * we have already determined whether we have link or not.
 532          */
 533         if (!mac->autoneg) {
 534                 ret_val = -E1000_ERR_CONFIG;
 535                 goto out;
 536         }
 537
 538         /*
 539          * Auto-Neg is enabled.  Auto Speed Detection takes care
 540          * of MAC speed/duplex configuration.  So we only need to
 541          * configure Collision Distance in the MAC.
 542          */
 543         e1000e_config_collision_dist(hw);
 544
 545         /*
 546          * Configure Flow Control now that Auto-Neg has completed.
 547          * First, we need to restore the desired flow control
 548          * settings because we may have had to re-autoneg with a
 549          * different link partner.
 550          */
 551         ret_val = e1000e_config_fc_after_link_up(hw);
 552         if (ret_val)
 553                 e_dbg("Error configuring flow control\n");
 554
 555 out:
 556         return ret_val;
 557 }
 558
 559 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 560 {
 561         struct e1000_hw *hw = &adapter->hw;
 562         s32 rc;
 563
 564         rc = e1000_init_mac_params_ich8lan(adapter);
 565         if (rc)
 566                 return rc;
 567
 568         rc = e1000_init_nvm_params_ich8lan(hw);
 569         if (rc)
 570                 return rc;
 571
 572         if (hw->mac.type == e1000_pchlan)
 573                 rc = e1000_init_phy_params_pchlan(hw);
 574         else
 575                 rc = e1000_init_phy_params_ich8lan(hw);
 576         if (rc)
 577                 return rc;
 578
 579         if (adapter->hw.phy.type == e1000_phy_ife) {
 580                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 581                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 582         }
 583
 584         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 585             (adapter->hw.phy.type == e1000_phy_igp_3))
 586                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 587
 588         return 0;
 589 }
 590
 591 static DEFINE_MUTEX(nvm_mutex);
 592
 593 /**
 594  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 595  *  @hw: pointer to the HW structure
 596  *
 597  *  Acquires the mutex for performing NVM operations.
 598  **/
 599 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 600 {
 601         mutex_lock(&nvm_mutex);
 602
 603         return 0;
 604 }
 605
 606 /**
 607  *  e1000_release_nvm_ich8lan - Release NVM mutex
 608  *  @hw: pointer to the HW structure
 609  *
 610  *  Releases the mutex used while performing NVM operations.
 611  **/
 612 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 613 {
 614         mutex_unlock(&nvm_mutex);
 615
 616         return;
 617 }
 618
 619 static DEFINE_MUTEX(swflag_mutex);
 620
 621 /**
 622  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 623  *  @hw: pointer to the HW structure
 624  *
 625  *  Acquires the software control flag for performing PHY and select
 626  *  MAC CSR accesses.
 627  **/
 628 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 629 {
 630         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 631         s32 ret_val = 0;
 632
 633         mutex_lock(&swflag_mutex);
 634
 635         while (timeout) {
 636                 extcnf_ctrl = er32(EXTCNF_CTRL);
 637                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 638                         break;
 639
 640                 mdelay(1);
 641                 timeout--;
 642         }
 643
 644         if (!timeout) {
 645                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 646                 ret_val = -E1000_ERR_CONFIG;
 647                 goto out;
 648         }
 649
 650         timeout = SW_FLAG_TIMEOUT;
 651
 652         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 653         ew32(EXTCNF_CTRL, extcnf_ctrl);
 654
 655         while (timeout) {
 656                 extcnf_ctrl = er32(EXTCNF_CTRL);
 657                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 658                         break;
 659
 660                 mdelay(1);
 661                 timeout--;
 662         }
 663
 664         if (!timeout) {
 665                 e_dbg("Failed to acquire the semaphore.\n");
 666                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 667                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 668                 ret_val = -E1000_ERR_CONFIG;
 669                 goto out;
 670         }
 671
 672 out:
 673         if (ret_val)
 674                 mutex_unlock(&swflag_mutex);
 675
 676         return ret_val;
 677 }
 678
 679 /**
 680  *  e1000_release_swflag_ich8lan - Release software control flag
 681  *  @hw: pointer to the HW structure
 682  *
 683  *  Releases the software control flag for performing PHY and select
 684  *  MAC CSR accesses.
 685  **/
 686 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 687 {
 688         u32 extcnf_ctrl;
 689
 690         extcnf_ctrl = er32(EXTCNF_CTRL);
 691         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 692         ew32(EXTCNF_CTRL, extcnf_ctrl);
 693
 694         mutex_unlock(&swflag_mutex);
 695
 696         return;
 697 }
 698
 699 /**
 700  *  e1000_check_mng_mode_ich8lan - Checks management mode
 701  *  @hw: pointer to the HW structure
 702  *
 703  *  This checks if the adapter has manageability enabled.
 704  *  This is a function pointer entry point only called by read/write
 705  *  routines for the PHY and NVM parts.
 706  **/
 707 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 708 {
 709         u32 fwsm = er32(FWSM);
 710
 711         return (fwsm & E1000_FWSM_MODE_MASK) ==
 712                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 713 }
 714
 715 /**
 716  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 717  *  @hw: pointer to the HW structure
 718  *
 719  *  Checks if firmware is blocking the reset of the PHY.
 720  *  This is a function pointer entry point only called by
 721  *  reset routines.
 722  **/
 723 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 724 {
 725         u32 fwsm;
 726
 727         fwsm = er32(FWSM);
 728
 729         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 730 }
 731
 732 /**
 733  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 734  *  @hw: pointer to the HW structure
 735  *
 736  *  Forces the speed and duplex settings of the PHY.
 737  *  This is a function pointer entry point only called by
 738  *  PHY setup routines.
 739  **/
 740 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 741 {
 742         struct e1000_phy_info *phy = &hw->phy;
 743         s32 ret_val;
 744         u16 data;
 745         bool link;
 746
 747         if (phy->type != e1000_phy_ife) {
 748                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 749                 return ret_val;
 750         }
 751
 752         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 753         if (ret_val)
 754                 return ret_val;
 755
 756         e1000e_phy_force_speed_duplex_setup(hw, &data);
 757
 758         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 759         if (ret_val)
 760                 return ret_val;
 761
 762         /* Disable MDI-X support for 10/100 */
 763         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 764         if (ret_val)
 765                 return ret_val;
 766
 767         data &= ~IFE_PMC_AUTO_MDIX;
 768         data &= ~IFE_PMC_FORCE_MDIX;
 769
 770         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 771         if (ret_val)
 772                 return ret_val;
 773
 774         e_dbg("IFE PMC: %X\n", data);
 775
 776         udelay(1);
 777
 778         if (phy->autoneg_wait_to_complete) {
 779                 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
 780
 781                 ret_val = e1000e_phy_has_link_generic(hw,
 782                                                      PHY_FORCE_LIMIT,
 783                                                      100000,
 784                                                      &link);
 785                 if (ret_val)
 786                         return ret_val;
 787
 788                 if (!link)
 789                         e_dbg("Link taking longer than expected.\n");
 790
 791                 /* Try once more */
 792                 ret_val = e1000e_phy_has_link_generic(hw,
 793                                                      PHY_FORCE_LIMIT,
 794                                                      100000,
 795                                                      &link);
 796                 if (ret_val)
 797                         return ret_val;
 798         }
 799
 800         return 0;
 801 }
 802
 803 /**
 804  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 805  *  @hw:   pointer to the HW structure
 806  *
 807  *  SW should configure the LCD from the NVM extended configuration region
 808  *  as a workaround for certain parts.
 809  **/
 810 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 811 {
 812         struct e1000_phy_info *phy = &hw->phy;
 813         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 814         s32 ret_val;
 815         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 816
 817         ret_val = hw->phy.ops.acquire(hw);
 818         if (ret_val)
 819                 return ret_val;
 820
 821         /*
 822          * Initialize the PHY from the NVM on ICH platforms.  This
 823          * is needed due to an issue where the NVM configuration is
 824          * not properly autoloaded after power transitions.
 825          * Therefore, after each PHY reset, we will load the
 826          * configuration data out of the NVM manually.
 827          */
 828         if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
 829                 (hw->mac.type == e1000_pchlan)) {
 830                 struct e1000_adapter *adapter = hw->adapter;
 831
 832                 /* Check if SW needs to configure the PHY */
 833                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 834                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
 835                     (hw->mac.type == e1000_pchlan))
 836                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 837                 else
 838                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 839
 840                 data = er32(FEXTNVM);
 841                 if (!(data & sw_cfg_mask))
 842                         goto out;
 843
 844                 /* Wait for basic configuration completes before proceeding */
 845                 e1000_lan_init_done_ich8lan(hw);
 846
 847                 /*
 848                  * Make sure HW does not configure LCD from PHY
 849                  * extended configuration before SW configuration
 850                  */
 851                 data = er32(EXTCNF_CTRL);
 852                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 853                         goto out;
 854
 855                 cnf_size = er32(EXTCNF_SIZE);
 856                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 857                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 858                 if (!cnf_size)
 859                         goto out;
 860
 861                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 862                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 863
 864                 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
 865                     (hw->mac.type == e1000_pchlan)) {
 866                         /*
 867                          * HW configures the SMBus address and LEDs when the
 868                          * OEM and LCD Write Enable bits are set in the NVM.
 869                          * When both NVM bits are cleared, SW will configure
 870                          * them instead.
 871                          */
 872                         data = er32(STRAP);
 873                         data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 874                         reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
 875                         reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 876                         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
 877                                                                 reg_data);
 878                         if (ret_val)
 879                                 goto out;
 880
 881                         data = er32(LEDCTL);
 882                         ret_val = e1000_write_phy_reg_hv_locked(hw,
 883                                                                 HV_LED_CONFIG,
 884                                                                 (u16)data);
 885                         if (ret_val)
 886                                 goto out;
 887                 }
 888                 /* Configure LCD from extended configuration region. */
 889
 890                 /* cnf_base_addr is in DWORD */
 891                 word_addr = (u16)(cnf_base_addr << 1);
 892
 893                 for (i = 0; i < cnf_size; i++) {
 894                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
 895                                                    &reg_data);
 896                         if (ret_val)
 897                                 goto out;
 898
 899                         ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
 900                                                    1, &reg_addr);
 901                         if (ret_val)
 902                                 goto out;
 903
 904                         /* Save off the PHY page for future writes. */
 905                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 906                                 phy_page = reg_data;
 907                                 continue;
 908                         }
 909
 910                         reg_addr &= PHY_REG_MASK;
 911                         reg_addr |= phy_page;
 912
 913                         ret_val = phy->ops.write_reg_locked(hw,
 914                                                             (u32)reg_addr,
 915                                                             reg_data);
 916                         if (ret_val)
 917                                 goto out;
 918                 }
 919         }
 920
 921 out:
 922         hw->phy.ops.release(hw);
 923         return ret_val;
 924 }
 925
 926 /**
 927  *  e1000_k1_gig_workaround_hv - K1 Si workaround
 928  *  @hw:   pointer to the HW structure
 929  *  @link: link up bool flag
 930  *
 931  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
 932  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
 933  *  If link is down, the function will restore the default K1 setting located
 934  *  in the NVM.
 935  **/
 936 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
 937 {
 938         s32 ret_val = 0;
 939         u16 status_reg = 0;
 940         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
 941
 942         if (hw->mac.type != e1000_pchlan)
 943                 goto out;
 944
 945         /* Wrap the whole flow with the sw flag */
 946         ret_val = hw->phy.ops.acquire(hw);
 947         if (ret_val)
 948                 goto out;
 949
 950         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
 951         if (link) {
 952                 if (hw->phy.type == e1000_phy_82578) {
 953                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
 954                                                                   &status_reg);
 955                         if (ret_val)
 956                                 goto release;
 957
 958                         status_reg &= BM_CS_STATUS_LINK_UP |
 959                                       BM_CS_STATUS_RESOLVED |
 960                                       BM_CS_STATUS_SPEED_MASK;
 961
 962                         if (status_reg == (BM_CS_STATUS_LINK_UP |
 963                                            BM_CS_STATUS_RESOLVED |
 964                                            BM_CS_STATUS_SPEED_1000))
 965                                 k1_enable = false;
 966                 }
 967
 968                 if (hw->phy.type == e1000_phy_82577) {
 969                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
 970                                                                   &status_reg);
 971                         if (ret_val)
 972                                 goto release;
 973
 974                         status_reg &= HV_M_STATUS_LINK_UP |
 975                                       HV_M_STATUS_AUTONEG_COMPLETE |
 976                                       HV_M_STATUS_SPEED_MASK;
 977
 978                         if (status_reg == (HV_M_STATUS_LINK_UP |
 979                                            HV_M_STATUS_AUTONEG_COMPLETE |
 980                                            HV_M_STATUS_SPEED_1000))
 981                                 k1_enable = false;
 982                 }
 983
 984                 /* Link stall fix for link up */
 985                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
 986                                                            0x0100);
 987                 if (ret_val)
 988                         goto release;
 989
 990         } else {
 991                 /* Link stall fix for link down */
 992                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
 993                                                            0x4100);
 994                 if (ret_val)
 995                         goto release;
 996         }
 997
 998         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
 999
1000 release:
1001         hw->phy.ops.release(hw);
1002 out:
1003         return ret_val;
1004 }
1005
1006 /**
1007  *  e1000_configure_k1_ich8lan - Configure K1 power state
1008  *  @hw: pointer to the HW structure
1009  *  @enable: K1 state to configure
1010  *
1011  *  Configure the K1 power state based on the provided parameter.
1012  *  Assumes semaphore already acquired.
1013  *
1014  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1015  **/
1016 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1017 {
1018         s32 ret_val = 0;
1019         u32 ctrl_reg = 0;
1020         u32 ctrl_ext = 0;
1021         u32 reg = 0;
1022         u16 kmrn_reg = 0;
1023
1024         ret_val = e1000e_read_kmrn_reg_locked(hw,
1025                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1026                                              &kmrn_reg);
1027         if (ret_val)
1028                 goto out;
1029
1030         if (k1_enable)
1031                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1032         else
1033                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1034
1035         ret_val = e1000e_write_kmrn_reg_locked(hw,
1036                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1037                                               kmrn_reg);
1038         if (ret_val)
1039                 goto out;
1040
1041         udelay(20);
1042         ctrl_ext = er32(CTRL_EXT);
1043         ctrl_reg = er32(CTRL);
1044
1045         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1046         reg |= E1000_CTRL_FRCSPD;
1047         ew32(CTRL, reg);
1048
1049         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1050         udelay(20);
1051         ew32(CTRL, ctrl_reg);
1052         ew32(CTRL_EXT, ctrl_ext);
1053         udelay(20);
1054
1055 out:
1056         return ret_val;
1057 }
1058
1059 /**
1060  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1061  *  @hw:       pointer to the HW structure
1062  *  @d0_state: boolean if entering d0 or d3 device state
1063  *
1064  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1065  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1066  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1067  **/
1068 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1069 {
1070         s32 ret_val = 0;
1071         u32 mac_reg;
1072         u16 oem_reg;
1073
1074         if (hw->mac.type != e1000_pchlan)
1075                 return ret_val;
1076
1077         ret_val = hw->phy.ops.acquire(hw);
1078         if (ret_val)
1079                 return ret_val;
1080
1081         mac_reg = er32(EXTCNF_CTRL);
1082         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1083                 goto out;
1084
1085         mac_reg = er32(FEXTNVM);
1086         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1087                 goto out;
1088
1089         mac_reg = er32(PHY_CTRL);
1090
1091         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1092         if (ret_val)
1093                 goto out;
1094
1095         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1096
1097         if (d0_state) {
1098                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1099                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1100
1101                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1102                         oem_reg |= HV_OEM_BITS_LPLU;
1103         } else {
1104                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1105                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1106
1107                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1108                         oem_reg |= HV_OEM_BITS_LPLU;
1109         }
1110         /* Restart auto-neg to activate the bits */
1111         oem_reg |= HV_OEM_BITS_RESTART_AN;
1112         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1113
1114 out:
1115         hw->phy.ops.release(hw);
1116
1117         return ret_val;
1118 }
1119
1120
1121 /**
1122  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1123  *  done after every PHY reset.
1124  **/
1125 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1126 {
1127         s32 ret_val = 0;
1128
1129         if (hw->mac.type != e1000_pchlan)
1130                 return ret_val;
1131
1132         if (((hw->phy.type == e1000_phy_82577) &&
1133              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1134             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1135                 /* Disable generation of early preamble */
1136                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1137                 if (ret_val)
1138                         return ret_val;
1139
1140                 /* Preamble tuning for SSC */
1141                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1142                 if (ret_val)
1143                         return ret_val;
1144         }
1145
1146         if (hw->phy.type == e1000_phy_82578) {
1147                 /*
1148                  * Return registers to default by doing a soft reset then
1149                  * writing 0x3140 to the control register.
1150                  */
1151                 if (hw->phy.revision < 2) {
1152                         e1000e_phy_sw_reset(hw);
1153                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1154                 }
1155         }
1156
1157         /* Select page 0 */
1158         ret_val = hw->phy.ops.acquire(hw);
1159         if (ret_val)
1160                 return ret_val;
1161
1162         hw->phy.addr = 1;
1163         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1164         if (ret_val)
1165                 goto out;
1166         hw->phy.ops.release(hw);
1167
1168         /*
1169          * Configure the K1 Si workaround during phy reset assuming there is
1170          * link so that it disables K1 if link is in 1Gbps.
1171          */
1172         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1173
1174 out:
1175         return ret_val;
1176 }
1177
1178 /**
1179  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1180  *  @hw: pointer to the HW structure
1181  *
1182  *  Check the appropriate indication the MAC has finished configuring the
1183  *  PHY after a software reset.
1184  **/
1185 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1186 {
1187         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1188
1189         /* Wait for basic configuration completes before proceeding */
1190         do {
1191                 data = er32(STATUS);
1192                 data &= E1000_STATUS_LAN_INIT_DONE;
1193                 udelay(100);
1194         } while ((!data) && --loop);
1195
1196         /*
1197          * If basic configuration is incomplete before the above loop
1198          * count reaches 0, loading the configuration from NVM will
1199          * leave the PHY in a bad state possibly resulting in no link.
1200          */
1201         if (loop == 0)
1202                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1203
1204         /* Clear the Init Done bit for the next init event */
1205         data = er32(STATUS);
1206         data &= ~E1000_STATUS_LAN_INIT_DONE;
1207         ew32(STATUS, data);
1208 }
1209
1210 /**
1211  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1212  *  @hw: pointer to the HW structure
1213  *
1214  *  Resets the PHY
1215  *  This is a function pointer entry point called by drivers
1216  *  or other shared routines.
1217  **/
1218 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1219 {
1220         s32 ret_val = 0;
1221         u16 reg;
1222
1223         ret_val = e1000e_phy_hw_reset_generic(hw);
1224         if (ret_val)
1225                 return ret_val;
1226
1227         /* Allow time for h/w to get to a quiescent state after reset */
1228         mdelay(10);
1229
1230         if (hw->mac.type == e1000_pchlan) {
1231                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1232                 if (ret_val)
1233                         return ret_val;
1234         }
1235
1236         /* Dummy read to clear the phy wakeup bit after lcd reset */
1237         if (hw->mac.type == e1000_pchlan)
1238                 e1e_rphy(hw, BM_WUC, &reg);
1239
1240         /* Configure the LCD with the extended configuration region in NVM */
1241         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1242         if (ret_val)
1243                 goto out;
1244
1245         /* Configure the LCD with the OEM bits in NVM */
1246         if (hw->mac.type == e1000_pchlan)
1247                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1248
1249 out:
1250         return 0;
1251 }
1252
1253 /**
1254  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
1255  *  @hw: pointer to the HW structure
1256  *
1257  *  Populates "phy" structure with various feature states.
1258  *  This function is only called by other family-specific
1259  *  routines.
1260  **/
1261 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
1262 {
1263         struct e1000_phy_info *phy = &hw->phy;
1264         s32 ret_val;
1265         u16 data;
1266         bool link;
1267
1268         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1269         if (ret_val)
1270                 return ret_val;
1271
1272         if (!link) {
1273                 e_dbg("Phy info is only valid if link is up\n");
1274                 return -E1000_ERR_CONFIG;
1275         }
1276
1277         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
1278         if (ret_val)
1279                 return ret_val;
1280         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
1281
1282         if (phy->polarity_correction) {
1283                 ret_val = phy->ops.check_polarity(hw);
1284                 if (ret_val)
1285                         return ret_val;
1286         } else {
1287                 /* Polarity is forced */
1288                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
1289                                       ? e1000_rev_polarity_reversed
1290                                       : e1000_rev_polarity_normal;
1291         }
1292
1293         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1294         if (ret_val)
1295                 return ret_val;
1296
1297         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1298
1299         /* The following parameters are undefined for 10/100 operation. */
1300         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1301         phy->local_rx = e1000_1000t_rx_status_undefined;
1302         phy->remote_rx = e1000_1000t_rx_status_undefined;
1303
1304         return 0;
1305 }
1306
1307 /**
1308  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1309  *  @hw: pointer to the HW structure
1310  *
1311  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
1312  *  This is a function pointer entry point called by drivers
1313  *  or other shared routines.
1314  **/
1315 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1316 {
1317         switch (hw->phy.type) {
1318         case e1000_phy_ife:
1319                 return e1000_get_phy_info_ife_ich8lan(hw);
1320                 break;
1321         case e1000_phy_igp_3:
1322         case e1000_phy_bm:
1323         case e1000_phy_82578:
1324         case e1000_phy_82577:
1325                 return e1000e_get_phy_info_igp(hw);
1326                 break;
1327         default:
1328                 break;
1329         }
1330
1331         return -E1000_ERR_PHY_TYPE;
1332 }
1333
1334 /**
1335  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1336  *  @hw: pointer to the HW structure
1337  *
1338  *  Polarity is determined on the polarity reversal feature being enabled.
1339  *  This function is only called by other family-specific
1340  *  routines.
1341  **/
1342 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1343 {
1344         struct e1000_phy_info *phy = &hw->phy;
1345         s32 ret_val;
1346         u16 phy_data, offset, mask;
1347
1348         /*
1349          * Polarity is determined based on the reversal feature being enabled.
1350          */
1351         if (phy->polarity_correction) {
1352                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
1353                 mask    = IFE_PESC_POLARITY_REVERSED;
1354         } else {
1355                 offset  = IFE_PHY_SPECIAL_CONTROL;
1356                 mask    = IFE_PSC_FORCE_POLARITY;
1357         }
1358
1359         ret_val = e1e_rphy(hw, offset, &phy_data);
1360
1361         if (!ret_val)
1362                 phy->cable_polarity = (phy_data & mask)
1363                                       ? e1000_rev_polarity_reversed
1364                                       : e1000_rev_polarity_normal;
1365
1366         return ret_val;
1367 }
1368
1369 /**
1370  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1371  *  @hw: pointer to the HW structure
1372  *  @active: true to enable LPLU, false to disable
1373  *
1374  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1375  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1376  *  the phy speed. This function will manually set the LPLU bit and restart
1377  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1378  *  since it configures the same bit.
1379  **/
1380 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1381 {
1382         s32 ret_val = 0;
1383         u16 oem_reg;
1384
1385         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1386         if (ret_val)
1387                 goto out;
1388
1389         if (active)
1390                 oem_reg |= HV_OEM_BITS_LPLU;
1391         else
1392                 oem_reg &= ~HV_OEM_BITS_LPLU;
1393
1394         oem_reg |= HV_OEM_BITS_RESTART_AN;
1395         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1396
1397 out:
1398         return ret_val;
1399 }
1400
1401 /**
1402  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1403  *  @hw: pointer to the HW structure
1404  *  @active: true to enable LPLU, false to disable
1405  *
1406  *  Sets the LPLU D0 state according to the active flag.  When
1407  *  activating LPLU this function also disables smart speed
1408  *  and vice versa.  LPLU will not be activated unless the
1409  *  device autonegotiation advertisement meets standards of
1410  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1411  *  This is a function pointer entry point only called by
1412  *  PHY setup routines.
1413  **/
1414 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1415 {
1416         struct e1000_phy_info *phy = &hw->phy;
1417         u32 phy_ctrl;
1418         s32 ret_val = 0;
1419         u16 data;
1420
1421         if (phy->type == e1000_phy_ife)
1422                 return ret_val;
1423
1424         phy_ctrl = er32(PHY_CTRL);
1425
1426         if (active) {
1427                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1428                 ew32(PHY_CTRL, phy_ctrl);
1429
1430                 if (phy->type != e1000_phy_igp_3)
1431                         return 0;
1432
1433                 /*
1434                  * Call gig speed drop workaround on LPLU before accessing
1435                  * any PHY registers
1436                  */
1437                 if (hw->mac.type == e1000_ich8lan)
1438                         e1000e_gig_downshift_workaround_ich8lan(hw);
1439
1440                 /* When LPLU is enabled, we should disable SmartSpeed */
1441                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1442                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1443                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1444                 if (ret_val)
1445                         return ret_val;
1446         } else {
1447                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1448                 ew32(PHY_CTRL, phy_ctrl);
1449
1450                 if (phy->type != e1000_phy_igp_3)
1451                         return 0;
1452
1453                 /*
1454                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1455                  * during Dx states where the power conservation is most
1456                  * important.  During driver activity we should enable
1457                  * SmartSpeed, so performance is maintained.
1458                  */
1459                 if (phy->smart_speed == e1000_smart_speed_on) {
1460                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1461                                            &data);
1462                         if (ret_val)
1463                                 return ret_val;
1464
1465                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1466                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1467                                            data);
1468                         if (ret_val)
1469                                 return ret_val;
1470                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1471                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1472                                            &data);
1473                         if (ret_val)
1474                                 return ret_val;
1475
1476                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1477                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1478                                            data);
1479                         if (ret_val)
1480                                 return ret_val;
1481                 }
1482         }
1483
1484         return 0;
1485 }
1486
1487 /**
1488  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1489  *  @hw: pointer to the HW structure
1490  *  @active: true to enable LPLU, false to disable
1491  *
1492  *  Sets the LPLU D3 state according to the active flag.  When
1493  *  activating LPLU this function also disables smart speed
1494  *  and vice versa.  LPLU will not be activated unless the
1495  *  device autonegotiation advertisement meets standards of
1496  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1497  *  This is a function pointer entry point only called by
1498  *  PHY setup routines.
1499  **/
1500 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1501 {
1502         struct e1000_phy_info *phy = &hw->phy;
1503         u32 phy_ctrl;
1504         s32 ret_val;
1505         u16 data;
1506
1507         phy_ctrl = er32(PHY_CTRL);
1508
1509         if (!active) {
1510                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1511                 ew32(PHY_CTRL, phy_ctrl);
1512
1513                 if (phy->type != e1000_phy_igp_3)
1514                         return 0;
1515
1516                 /*
1517                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1518                  * during Dx states where the power conservation is most
1519                  * important.  During driver activity we should enable
1520                  * SmartSpeed, so performance is maintained.
1521                  */
1522                 if (phy->smart_speed == e1000_smart_speed_on) {
1523                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1524                                            &data);
1525                         if (ret_val)
1526                                 return ret_val;
1527
1528                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1529                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1530                                            data);
1531                         if (ret_val)
1532                                 return ret_val;
1533                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1534                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1535                                            &data);
1536                         if (ret_val)
1537                                 return ret_val;
1538
1539                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1540                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1541                                            data);
1542                         if (ret_val)
1543                                 return ret_val;
1544                 }
1545         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1546                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1547                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1548                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1549                 ew32(PHY_CTRL, phy_ctrl);
1550
1551                 if (phy->type != e1000_phy_igp_3)
1552                         return 0;
1553
1554                 /*
1555                  * Call gig speed drop workaround on LPLU before accessing
1556                  * any PHY registers
1557                  */
1558                 if (hw->mac.type == e1000_ich8lan)
1559                         e1000e_gig_downshift_workaround_ich8lan(hw);
1560
1561                 /* When LPLU is enabled, we should disable SmartSpeed */
1562                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1563                 if (ret_val)
1564                         return ret_val;
1565
1566                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1567                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1568         }
1569
1570         return 0;
1571 }
1572
1573 /**
1574  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1575  *  @hw: pointer to the HW structure
1576  *  @bank:  pointer to the variable that returns the active bank
1577  *
1578  *  Reads signature byte from the NVM using the flash access registers.
1579  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1580  **/
1581 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1582 {
1583         u32 eecd;
1584         struct e1000_nvm_info *nvm = &hw->nvm;
1585         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1586         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1587         u8 sig_byte = 0;
1588         s32 ret_val = 0;
1589
1590         switch (hw->mac.type) {
1591         case e1000_ich8lan:
1592         case e1000_ich9lan:
1593                 eecd = er32(EECD);
1594                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1595                     E1000_EECD_SEC1VAL_VALID_MASK) {
1596                         if (eecd & E1000_EECD_SEC1VAL)
1597                                 *bank = 1;
1598                         else
1599                                 *bank = 0;
1600
1601                         return 0;
1602                 }
1603                 e_dbg("Unable to determine valid NVM bank via EEC - "
1604                        "reading flash signature\n");
1605                 /* fall-thru */
1606         default:
1607                 /* set bank to 0 in case flash read fails */
1608                 *bank = 0;
1609
1610                 /* Check bank 0 */
1611                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1612                                                         &sig_byte);
1613                 if (ret_val)
1614                         return ret_val;
1615                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1616                     E1000_ICH_NVM_SIG_VALUE) {
1617                         *bank = 0;
1618                         return 0;
1619                 }
1620
1621                 /* Check bank 1 */
1622                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1623                                                         bank1_offset,
1624                                                         &sig_byte);
1625                 if (ret_val)
1626                         return ret_val;
1627                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1628                     E1000_ICH_NVM_SIG_VALUE) {
1629                         *bank = 1;
1630                         return 0;
1631                 }
1632
1633                 e_dbg("ERROR: No valid NVM bank present\n");
1634                 return -E1000_ERR_NVM;
1635         }
1636
1637         return 0;
1638 }
1639
1640 /**
1641  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1642  *  @hw: pointer to the HW structure
1643  *  @offset: The offset (in bytes) of the word(s) to read.
1644  *  @words: Size of data to read in words
1645  *  @data: Pointer to the word(s) to read at offset.
1646  *
1647  *  Reads a word(s) from the NVM using the flash access registers.
1648  **/
1649 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1650                                   u16 *data)
1651 {
1652         struct e1000_nvm_info *nvm = &hw->nvm;
1653         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1654         u32 act_offset;
1655         s32 ret_val = 0;
1656         u32 bank = 0;
1657         u16 i, word;
1658
1659         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1660             (words == 0)) {
1661                 e_dbg("nvm parameter(s) out of bounds\n");
1662                 ret_val = -E1000_ERR_NVM;
1663                 goto out;
1664         }
1665
1666         nvm->ops.acquire(hw);
1667
1668         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1669         if (ret_val) {
1670                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1671                 bank = 0;
1672         }
1673
1674         act_offset = (bank) ? nvm->flash_bank_size : 0;
1675         act_offset += offset;
1676
1677         ret_val = 0;
1678         for (i = 0; i < words; i++) {
1679                 if ((dev_spec->shadow_ram) &&
1680                     (dev_spec->shadow_ram[offset+i].modified)) {
1681                         data[i] = dev_spec->shadow_ram[offset+i].value;
1682                 } else {
1683                         ret_val = e1000_read_flash_word_ich8lan(hw,
1684                                                                 act_offset + i,
1685                                                                 &word);
1686                         if (ret_val)
1687                                 break;
1688                         data[i] = word;
1689                 }
1690         }
1691
1692         nvm->ops.release(hw);
1693
1694 out:
1695         if (ret_val)
1696                 e_dbg("NVM read error: %d\n", ret_val);
1697
1698         return ret_val;
1699 }
1700
1701 /**
1702  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1703  *  @hw: pointer to the HW structure
1704  *
1705  *  This function does initial flash setup so that a new read/write/erase cycle
1706  *  can be started.
1707  **/
1708 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1709 {
1710         union ich8_hws_flash_status hsfsts;
1711         s32 ret_val = -E1000_ERR_NVM;
1712         s32 i = 0;
1713
1714         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1715
1716         /* Check if the flash descriptor is valid */
1717         if (hsfsts.hsf_status.fldesvalid == 0) {
1718                 e_dbg("Flash descriptor invalid.  "
1719                          "SW Sequencing must be used.");
1720                 return -E1000_ERR_NVM;
1721         }
1722
1723         /* Clear FCERR and DAEL in hw status by writing 1 */
1724         hsfsts.hsf_status.flcerr = 1;
1725         hsfsts.hsf_status.dael = 1;
1726
1727         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1728
1729         /*
1730          * Either we should have a hardware SPI cycle in progress
1731          * bit to check against, in order to start a new cycle or
1732          * FDONE bit should be changed in the hardware so that it
1733          * is 1 after hardware reset, which can then be used as an
1734          * indication whether a cycle is in progress or has been
1735          * completed.
1736          */
1737
1738         if (hsfsts.hsf_status.flcinprog == 0) {
1739                 /*
1740                  * There is no cycle running at present,
1741                  * so we can start a cycle
1742                  * Begin by setting Flash Cycle Done.
1743                  */
1744                 hsfsts.hsf_status.flcdone = 1;
1745                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1746                 ret_val = 0;
1747         } else {
1748                 /*
1749                  * otherwise poll for sometime so the current
1750                  * cycle has a chance to end before giving up.
1751                  */
1752                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1753                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1754                         if (hsfsts.hsf_status.flcinprog == 0) {
1755                                 ret_val = 0;
1756                                 break;
1757                         }
1758                         udelay(1);
1759                 }
1760                 if (ret_val == 0) {
1761                         /*
1762                          * Successful in waiting for previous cycle to timeout,
1763                          * now set the Flash Cycle Done.
1764                          */
1765                         hsfsts.hsf_status.flcdone = 1;
1766                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1767                 } else {
1768                         e_dbg("Flash controller busy, cannot get access");
1769                 }
1770         }
1771
1772         return ret_val;
1773 }
1774
1775 /**
1776  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1777  *  @hw: pointer to the HW structure
1778  *  @timeout: maximum time to wait for completion
1779  *
1780  *  This function starts a flash cycle and waits for its completion.
1781  **/
1782 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1783 {
1784         union ich8_hws_flash_ctrl hsflctl;
1785         union ich8_hws_flash_status hsfsts;
1786         s32 ret_val = -E1000_ERR_NVM;
1787         u32 i = 0;
1788
1789         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1790         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1791         hsflctl.hsf_ctrl.flcgo = 1;
1792         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1793
1794         /* wait till FDONE bit is set to 1 */
1795         do {
1796                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1797                 if (hsfsts.hsf_status.flcdone == 1)
1798                         break;
1799                 udelay(1);
1800         } while (i++ < timeout);
1801
1802         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1803                 return 0;
1804
1805         return ret_val;
1806 }
1807
1808 /**
1809  *  e1000_read_flash_word_ich8lan - Read word from flash
1810  *  @hw: pointer to the HW structure
1811  *  @offset: offset to data location
1812  *  @data: pointer to the location for storing the data
1813  *
1814  *  Reads the flash word at offset into data.  Offset is converted
1815  *  to bytes before read.
1816  **/
1817 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1818                                          u16 *data)
1819 {
1820         /* Must convert offset into bytes. */
1821         offset <<= 1;
1822
1823         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1824 }
1825
1826 /**
1827  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1828  *  @hw: pointer to the HW structure
1829  *  @offset: The offset of the byte to read.
1830  *  @data: Pointer to a byte to store the value read.
1831  *
1832  *  Reads a single byte from the NVM using the flash access registers.
1833  **/
1834 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1835                                          u8 *data)
1836 {
1837         s32 ret_val;
1838         u16 word = 0;
1839
1840         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1841         if (ret_val)
1842                 return ret_val;
1843
1844         *data = (u8)word;
1845
1846         return 0;
1847 }
1848
1849 /**
1850  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1851  *  @hw: pointer to the HW structure
1852  *  @offset: The offset (in bytes) of the byte or word to read.
1853  *  @size: Size of data to read, 1=byte 2=word
1854  *  @data: Pointer to the word to store the value read.
1855  *
1856  *  Reads a byte or word from the NVM using the flash access registers.
1857  **/
1858 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1859                                          u8 size, u16 *data)
1860 {
1861         union ich8_hws_flash_status hsfsts;
1862         union ich8_hws_flash_ctrl hsflctl;
1863         u32 flash_linear_addr;
1864         u32 flash_data = 0;
1865         s32 ret_val = -E1000_ERR_NVM;
1866         u8 count = 0;
1867
1868         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1869                 return -E1000_ERR_NVM;
1870
1871         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1872                             hw->nvm.flash_base_addr;
1873
1874         do {
1875                 udelay(1);
1876                 /* Steps */
1877                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1878                 if (ret_val != 0)
1879                         break;
1880
1881                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1882                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1883                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1884                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1885                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1886
1887                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1888
1889                 ret_val = e1000_flash_cycle_ich8lan(hw,
1890                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1891
1892                 /*
1893                  * Check if FCERR is set to 1, if set to 1, clear it
1894                  * and try the whole sequence a few more times, else
1895                  * read in (shift in) the Flash Data0, the order is
1896                  * least significant byte first msb to lsb
1897                  */
1898                 if (ret_val == 0) {
1899                         flash_data = er32flash(ICH_FLASH_FDATA0);
1900                         if (size == 1) {
1901                                 *data = (u8)(flash_data & 0x000000FF);
1902                         } else if (size == 2) {
1903                                 *data = (u16)(flash_data & 0x0000FFFF);
1904                         }
1905                         break;
1906                 } else {
1907                         /*
1908                          * If we've gotten here, then things are probably
1909                          * completely hosed, but if the error condition is
1910                          * detected, it won't hurt to give it another try...
1911                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1912                          */
1913                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1914                         if (hsfsts.hsf_status.flcerr == 1) {
1915                                 /* Repeat for some time before giving up. */
1916                                 continue;
1917                         } else if (hsfsts.hsf_status.flcdone == 0) {
1918                                 e_dbg("Timeout error - flash cycle "
1919                                          "did not complete.");
1920                                 break;
1921                         }
1922                 }
1923         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1924
1925         return ret_val;
1926 }
1927
1928 /**
1929  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1930  *  @hw: pointer to the HW structure
1931  *  @offset: The offset (in bytes) of the word(s) to write.
1932  *  @words: Size of data to write in words
1933  *  @data: Pointer to the word(s) to write at offset.
1934  *
1935  *  Writes a byte or word to the NVM using the flash access registers.
1936  **/
1937 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1938                                    u16 *data)
1939 {
1940         struct e1000_nvm_info *nvm = &hw->nvm;
1941         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1942         u16 i;
1943
1944         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1945             (words == 0)) {
1946                 e_dbg("nvm parameter(s) out of bounds\n");
1947                 return -E1000_ERR_NVM;
1948         }
1949
1950         nvm->ops.acquire(hw);
1951
1952         for (i = 0; i < words; i++) {
1953                 dev_spec->shadow_ram[offset+i].modified = true;
1954                 dev_spec->shadow_ram[offset+i].value = data[i];
1955         }
1956
1957         nvm->ops.release(hw);
1958
1959         return 0;
1960 }
1961
1962 /**
1963  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1964  *  @hw: pointer to the HW structure
1965  *
1966  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1967  *  which writes the checksum to the shadow ram.  The changes in the shadow
1968  *  ram are then committed to the EEPROM by processing each bank at a time
1969  *  checking for the modified bit and writing only the pending changes.
1970  *  After a successful commit, the shadow ram is cleared and is ready for
1971  *  future writes.
1972  **/
1973 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1974 {
1975         struct e1000_nvm_info *nvm = &hw->nvm;
1976         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1977         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1978         s32 ret_val;
1979         u16 data;
1980
1981         ret_val = e1000e_update_nvm_checksum_generic(hw);
1982         if (ret_val)
1983                 goto out;
1984
1985         if (nvm->type != e1000_nvm_flash_sw)
1986                 goto out;
1987
1988         nvm->ops.acquire(hw);
1989
1990         /*
1991          * We're writing to the opposite bank so if we're on bank 1,
1992          * write to bank 0 etc.  We also need to erase the segment that
1993          * is going to be written
1994          */
1995         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1996         if (ret_val) {
1997                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1998                 bank = 0;
1999         }
2000
2001         if (bank == 0) {
2002                 new_bank_offset = nvm->flash_bank_size;
2003                 old_bank_offset = 0;
2004                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2005                 if (ret_val) {
2006                         nvm->ops.release(hw);
2007                         goto out;
2008                 }
2009         } else {
2010                 old_bank_offset = nvm->flash_bank_size;
2011                 new_bank_offset = 0;
2012                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2013                 if (ret_val) {
2014                         nvm->ops.release(hw);
2015                         goto out;
2016                 }
2017         }
2018
2019         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2020                 /*
2021                  * Determine whether to write the value stored
2022                  * in the other NVM bank or a modified value stored
2023                  * in the shadow RAM
2024                  */
2025                 if (dev_spec->shadow_ram[i].modified) {
2026                         data = dev_spec->shadow_ram[i].value;
2027                 } else {
2028                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2029                                                                 old_bank_offset,
2030                                                                 &data);
2031                         if (ret_val)
2032                                 break;
2033                 }
2034
2035                 /*
2036                  * If the word is 0x13, then make sure the signature bits
2037                  * (15:14) are 11b until the commit has completed.
2038                  * This will allow us to write 10b which indicates the
2039                  * signature is valid.  We want to do this after the write
2040                  * has completed so that we don't mark the segment valid
2041                  * while the write is still in progress
2042                  */
2043                 if (i == E1000_ICH_NVM_SIG_WORD)
2044                         data |= E1000_ICH_NVM_SIG_MASK;
2045
2046                 /* Convert offset to bytes. */
2047                 act_offset = (i + new_bank_offset) << 1;
2048
2049                 udelay(100);
2050                 /* Write the bytes to the new bank. */
2051                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2052                                                                act_offset,
2053                                                                (u8)data);
2054                 if (ret_val)
2055                         break;
2056
2057                 udelay(100);
2058                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2059                                                           act_offset + 1,
2060                                                           (u8)(data >> 8));
2061                 if (ret_val)
2062                         break;
2063         }
2064
2065         /*
2066          * Don't bother writing the segment valid bits if sector
2067          * programming failed.
2068          */
2069         if (ret_val) {
2070                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2071                 e_dbg("Flash commit failed.\n");
2072                 nvm->ops.release(hw);
2073                 goto out;
2074         }
2075
2076         /*
2077          * Finally validate the new segment by setting bit 15:14
2078          * to 10b in word 0x13 , this can be done without an
2079          * erase as well since these bits are 11 to start with
2080          * and we need to change bit 14 to 0b
2081          */
2082         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2083         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2084         if (ret_val) {
2085                 nvm->ops.release(hw);
2086                 goto out;
2087         }
2088         data &= 0xBFFF;
2089         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2090                                                        act_offset * 2 + 1,
2091                                                        (u8)(data >> 8));
2092         if (ret_val) {
2093                 nvm->ops.release(hw);
2094                 goto out;
2095         }
2096
2097         /*
2098          * And invalidate the previously valid segment by setting
2099          * its signature word (0x13) high_byte to 0b. This can be
2100          * done without an erase because flash erase sets all bits
2101          * to 1's. We can write 1's to 0's without an erase
2102          */
2103         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2104         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2105         if (ret_val) {
2106                 nvm->ops.release(hw);
2107                 goto out;
2108         }
2109
2110         /* Great!  Everything worked, we can now clear the cached entries. */
2111         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2112                 dev_spec->shadow_ram[i].modified = false;
2113                 dev_spec->shadow_ram[i].value = 0xFFFF;
2114         }
2115
2116         nvm->ops.release(hw);
2117
2118         /*
2119          * Reload the EEPROM, or else modifications will not appear
2120          * until after the next adapter reset.
2121          */
2122         e1000e_reload_nvm(hw);
2123         msleep(10);
2124
2125 out:
2126         if (ret_val)
2127                 e_dbg("NVM update error: %d\n", ret_val);
2128
2129         return ret_val;
2130 }
2131
2132 /**
2133  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2134  *  @hw: pointer to the HW structure
2135  *
2136  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2137  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2138  *  calculated, in which case we need to calculate the checksum and set bit 6.
2139  **/
2140 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2141 {
2142         s32 ret_val;
2143         u16 data;
2144
2145         /*
2146          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2147          * needs to be fixed.  This bit is an indication that the NVM
2148          * was prepared by OEM software and did not calculate the
2149          * checksum...a likely scenario.
2150          */
2151         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2152         if (ret_val)
2153                 return ret_val;
2154
2155         if ((data & 0x40) == 0) {
2156                 data |= 0x40;
2157                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2158                 if (ret_val)
2159                         return ret_val;
2160                 ret_val = e1000e_update_nvm_checksum(hw);
2161                 if (ret_val)
2162                         return ret_val;
2163         }
2164
2165         return e1000e_validate_nvm_checksum_generic(hw);
2166 }
2167
2168 /**
2169  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2170  *  @hw: pointer to the HW structure
2171  *
2172  *  To prevent malicious write/erase of the NVM, set it to be read-only
2173  *  so that the hardware ignores all write/erase cycles of the NVM via
2174  *  the flash control registers.  The shadow-ram copy of the NVM will
2175  *  still be updated, however any updates to this copy will not stick
2176  *  across driver reloads.
2177  **/
2178 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2179 {
2180         struct e1000_nvm_info *nvm = &hw->nvm;
2181         union ich8_flash_protected_range pr0;
2182         union ich8_hws_flash_status hsfsts;
2183         u32 gfpreg;
2184
2185         nvm->ops.acquire(hw);
2186
2187         gfpreg = er32flash(ICH_FLASH_GFPREG);
2188
2189         /* Write-protect GbE Sector of NVM */
2190         pr0.regval = er32flash(ICH_FLASH_PR0);
2191         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2192         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2193         pr0.range.wpe = true;
2194         ew32flash(ICH_FLASH_PR0, pr0.regval);
2195
2196         /*
2197          * Lock down a subset of GbE Flash Control Registers, e.g.
2198          * PR0 to prevent the write-protection from being lifted.
2199          * Once FLOCKDN is set, the registers protected by it cannot
2200          * be written until FLOCKDN is cleared by a hardware reset.
2201          */
2202         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2203         hsfsts.hsf_status.flockdn = true;
2204         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2205
2206         nvm->ops.release(hw);
2207 }
2208
2209 /**
2210  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2211  *  @hw: pointer to the HW structure
2212  *  @offset: The offset (in bytes) of the byte/word to read.
2213  *  @size: Size of data to read, 1=byte 2=word
2214  *  @data: The byte(s) to write to the NVM.
2215  *
2216  *  Writes one/two bytes to the NVM using the flash access registers.
2217  **/
2218 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2219                                           u8 size, u16 data)
2220 {
2221         union ich8_hws_flash_status hsfsts;
2222         union ich8_hws_flash_ctrl hsflctl;
2223         u32 flash_linear_addr;
2224         u32 flash_data = 0;
2225         s32 ret_val;
2226         u8 count = 0;
2227
2228         if (size < 1 || size > 2 || data > size * 0xff ||
2229             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2230                 return -E1000_ERR_NVM;
2231
2232         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2233                             hw->nvm.flash_base_addr;
2234
2235         do {
2236                 udelay(1);
2237                 /* Steps */
2238                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2239                 if (ret_val)
2240                         break;
2241
2242                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2243                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2244                 hsflctl.hsf_ctrl.fldbcount = size -1;
2245                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2246                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2247
2248                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2249
2250                 if (size == 1)
2251                         flash_data = (u32)data & 0x00FF;
2252                 else
2253                         flash_data = (u32)data;
2254
2255                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2256
2257                 /*
2258                  * check if FCERR is set to 1 , if set to 1, clear it
2259                  * and try the whole sequence a few more times else done
2260                  */
2261                 ret_val = e1000_flash_cycle_ich8lan(hw,
2262                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2263                 if (!ret_val)
2264                         break;
2265
2266                 /*
2267                  * If we're here, then things are most likely
2268                  * completely hosed, but if the error condition
2269                  * is detected, it won't hurt to give it another
2270                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2271                  */
2272                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2273                 if (hsfsts.hsf_status.flcerr == 1)
2274                         /* Repeat for some time before giving up. */
2275                         continue;
2276                 if (hsfsts.hsf_status.flcdone == 0) {
2277                         e_dbg("Timeout error - flash cycle "
2278                                  "did not complete.");
2279                         break;
2280                 }
2281         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2282
2283         return ret_val;
2284 }
2285
2286 /**
2287  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2288  *  @hw: pointer to the HW structure
2289  *  @offset: The index of the byte to read.
2290  *  @data: The byte to write to the NVM.
2291  *
2292  *  Writes a single byte to the NVM using the flash access registers.
2293  **/
2294 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2295                                           u8 data)
2296 {
2297         u16 word = (u16)data;
2298
2299         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2300 }
2301
2302 /**
2303  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2304  *  @hw: pointer to the HW structure
2305  *  @offset: The offset of the byte to write.
2306  *  @byte: The byte to write to the NVM.
2307  *
2308  *  Writes a single byte to the NVM using the flash access registers.
2309  *  Goes through a retry algorithm before giving up.
2310  **/
2311 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2312                                                 u32 offset, u8 byte)
2313 {
2314         s32 ret_val;
2315         u16 program_retries;
2316
2317         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2318         if (!ret_val)
2319                 return ret_val;
2320
2321         for (program_retries = 0; program_retries < 100; program_retries++) {
2322                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2323                 udelay(100);
2324                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2325                 if (!ret_val)
2326                         break;
2327         }
2328         if (program_retries == 100)
2329                 return -E1000_ERR_NVM;
2330
2331         return 0;
2332 }
2333
2334 /**
2335  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2336  *  @hw: pointer to the HW structure
2337  *  @bank: 0 for first bank, 1 for second bank, etc.
2338  *
2339  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2340  *  bank N is 4096 * N + flash_reg_addr.
2341  **/
2342 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2343 {
2344         struct e1000_nvm_info *nvm = &hw->nvm;
2345         union ich8_hws_flash_status hsfsts;
2346         union ich8_hws_flash_ctrl hsflctl;
2347         u32 flash_linear_addr;
2348         /* bank size is in 16bit words - adjust to bytes */
2349         u32 flash_bank_size = nvm->flash_bank_size * 2;
2350         s32 ret_val;
2351         s32 count = 0;
2352         s32 iteration;
2353         s32 sector_size;
2354         s32 j;
2355
2356         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2357
2358         /*
2359          * Determine HW Sector size: Read BERASE bits of hw flash status
2360          * register
2361          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2362          *     consecutive sectors.  The start index for the nth Hw sector
2363          *     can be calculated as = bank * 4096 + n * 256
2364          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2365          *     The start index for the nth Hw sector can be calculated
2366          *     as = bank * 4096
2367          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2368          *     (ich9 only, otherwise error condition)
2369          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2370          */
2371         switch (hsfsts.hsf_status.berasesz) {
2372         case 0:
2373                 /* Hw sector size 256 */
2374                 sector_size = ICH_FLASH_SEG_SIZE_256;
2375                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2376                 break;
2377         case 1:
2378                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2379                 iteration = 1;
2380                 break;
2381         case 2:
2382                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2383                 iteration = 1;
2384                 break;
2385         case 3:
2386                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2387                 iteration = 1;
2388                 break;
2389         default:
2390                 return -E1000_ERR_NVM;
2391         }
2392
2393         /* Start with the base address, then add the sector offset. */
2394         flash_linear_addr = hw->nvm.flash_base_addr;
2395         flash_linear_addr += (bank) ? flash_bank_size : 0;
2396
2397         for (j = 0; j < iteration ; j++) {
2398                 do {
2399                         /* Steps */
2400                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2401                         if (ret_val)
2402                                 return ret_val;
2403
2404                         /*
2405                          * Write a value 11 (block Erase) in Flash
2406                          * Cycle field in hw flash control
2407                          */
2408                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2409                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2410                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2411
2412                         /*
2413                          * Write the last 24 bits of an index within the
2414                          * block into Flash Linear address field in Flash
2415                          * Address.
2416                          */
2417                         flash_linear_addr += (j * sector_size);
2418                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2419
2420                         ret_val = e1000_flash_cycle_ich8lan(hw,
2421                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2422                         if (ret_val == 0)
2423                                 break;
2424
2425                         /*
2426                          * Check if FCERR is set to 1.  If 1,
2427                          * clear it and try the whole sequence
2428                          * a few more times else Done
2429                          */
2430                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2431                         if (hsfsts.hsf_status.flcerr == 1)
2432                                 /* repeat for some time before giving up */
2433                                 continue;
2434                         else if (hsfsts.hsf_status.flcdone == 0)
2435                                 return ret_val;
2436                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2437         }
2438
2439         return 0;
2440 }
2441
2442 /**
2443  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2444  *  @hw: pointer to the HW structure
2445  *  @data: Pointer to the LED settings
2446  *
2447  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2448  *  settings is all 0's or F's, set the LED default to a valid LED default
2449  *  setting.
2450  **/
2451 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2452 {
2453         s32 ret_val;
2454
2455         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2456         if (ret_val) {
2457                 e_dbg("NVM Read Error\n");
2458                 return ret_val;
2459         }
2460
2461         if (*data == ID_LED_RESERVED_0000 ||
2462             *data == ID_LED_RESERVED_FFFF)
2463                 *data = ID_LED_DEFAULT_ICH8LAN;
2464
2465         return 0;
2466 }
2467
2468 /**
2469  *  e1000_id_led_init_pchlan - store LED configurations
2470  *  @hw: pointer to the HW structure
2471  *
2472  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2473  *  the PHY LED configuration register.
2474  *
2475  *  PCH also does not have an "always on" or "always off" mode which
2476  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2477  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2478  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2479  *  link based on logic in e1000_led_[on|off]_pchlan().
2480  **/
2481 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2482 {
2483         struct e1000_mac_info *mac = &hw->mac;
2484         s32 ret_val;
2485         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2486         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2487         u16 data, i, temp, shift;
2488
2489         /* Get default ID LED modes */
2490         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2491         if (ret_val)
2492                 goto out;
2493
2494         mac->ledctl_default = er32(LEDCTL);
2495         mac->ledctl_mode1 = mac->ledctl_default;
2496         mac->ledctl_mode2 = mac->ledctl_default;
2497
2498         for (i = 0; i < 4; i++) {
2499                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2500                 shift = (i * 5);
2501                 switch (temp) {
2502                 case ID_LED_ON1_DEF2:
2503                 case ID_LED_ON1_ON2:
2504                 case ID_LED_ON1_OFF2:
2505                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2506                         mac->ledctl_mode1 |= (ledctl_on << shift);
2507                         break;
2508                 case ID_LED_OFF1_DEF2:
2509                 case ID_LED_OFF1_ON2:
2510                 case ID_LED_OFF1_OFF2:
2511                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2512                         mac->ledctl_mode1 |= (ledctl_off << shift);
2513                         break;
2514                 default:
2515                         /* Do nothing */
2516                         break;
2517                 }
2518                 switch (temp) {
2519                 case ID_LED_DEF1_ON2:
2520                 case ID_LED_ON1_ON2:
2521                 case ID_LED_OFF1_ON2:
2522                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2523                         mac->ledctl_mode2 |= (ledctl_on << shift);
2524                         break;
2525                 case ID_LED_DEF1_OFF2:
2526                 case ID_LED_ON1_OFF2:
2527                 case ID_LED_OFF1_OFF2:
2528                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2529                         mac->ledctl_mode2 |= (ledctl_off << shift);
2530                         break;
2531                 default:
2532                         /* Do nothing */
2533                         break;
2534                 }
2535         }
2536
2537 out:
2538         return ret_val;
2539 }
2540
2541 /**
2542  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2543  *  @hw: pointer to the HW structure
2544  *
2545  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2546  *  register, so the the bus width is hard coded.
2547  **/
2548 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2549 {
2550         struct e1000_bus_info *bus = &hw->bus;
2551         s32 ret_val;
2552
2553         ret_val = e1000e_get_bus_info_pcie(hw);
2554
2555         /*
2556          * ICH devices are "PCI Express"-ish.  They have
2557          * a configuration space, but do not contain
2558          * PCI Express Capability registers, so bus width
2559          * must be hardcoded.
2560          */
2561         if (bus->width == e1000_bus_width_unknown)
2562                 bus->width = e1000_bus_width_pcie_x1;
2563
2564         return ret_val;
2565 }
2566
2567 /**
2568  *  e1000_reset_hw_ich8lan - Reset the hardware
2569  *  @hw: pointer to the HW structure
2570  *
2571  *  Does a full reset of the hardware which includes a reset of the PHY and
2572  *  MAC.
2573  **/
2574 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2575 {
2576         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2577         u16 reg;
2578         u32 ctrl, icr, kab;
2579         s32 ret_val;
2580
2581         /*
2582          * Prevent the PCI-E bus from sticking if there is no TLP connection
2583          * on the last TLP read/write transaction when MAC is reset.
2584          */
2585         ret_val = e1000e_disable_pcie_master(hw);
2586         if (ret_val) {
2587                 e_dbg("PCI-E Master disable polling has failed.\n");
2588         }
2589
2590         e_dbg("Masking off all interrupts\n");
2591         ew32(IMC, 0xffffffff);
2592
2593         /*
2594          * Disable the Transmit and Receive units.  Then delay to allow
2595          * any pending transactions to complete before we hit the MAC
2596          * with the global reset.
2597          */
2598         ew32(RCTL, 0);
2599         ew32(TCTL, E1000_TCTL_PSP);
2600         e1e_flush();
2601
2602         msleep(10);
2603
2604         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2605         if (hw->mac.type == e1000_ich8lan) {
2606                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2607                 ew32(PBA, E1000_PBA_8K);
2608                 /* Set Packet Buffer Size to 16k. */
2609                 ew32(PBS, E1000_PBS_16K);
2610         }
2611
2612         if (hw->mac.type == e1000_pchlan) {
2613                 /* Save the NVM K1 bit setting*/
2614                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2615                 if (ret_val)
2616                         return ret_val;
2617
2618                 if (reg & E1000_NVM_K1_ENABLE)
2619                         dev_spec->nvm_k1_enabled = true;
2620                 else
2621                         dev_spec->nvm_k1_enabled = false;
2622         }
2623
2624         ctrl = er32(CTRL);
2625
2626         if (!e1000_check_reset_block(hw)) {
2627                 /* Clear PHY Reset Asserted bit */
2628                 if (hw->mac.type >= e1000_pchlan) {
2629                         u32 status = er32(STATUS);
2630                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2631                 }
2632
2633                 /*
2634                  * PHY HW reset requires MAC CORE reset at the same
2635                  * time to make sure the interface between MAC and the
2636                  * external PHY is reset.
2637                  */
2638                 ctrl |= E1000_CTRL_PHY_RST;
2639         }
2640         ret_val = e1000_acquire_swflag_ich8lan(hw);
2641         /* Whether or not the swflag was acquired, we need to reset the part */
2642         e_dbg("Issuing a global reset to ich8lan\n");
2643         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2644         msleep(20);
2645
2646         if (!ret_val)
2647                 e1000_release_swflag_ich8lan(hw);
2648
2649         if (ctrl & E1000_CTRL_PHY_RST)
2650                 ret_val = hw->phy.ops.get_cfg_done(hw);
2651
2652         if (hw->mac.type >= e1000_ich10lan) {
2653                 e1000_lan_init_done_ich8lan(hw);
2654         } else {
2655                 ret_val = e1000e_get_auto_rd_done(hw);
2656                 if (ret_val) {
2657                         /*
2658                          * When auto config read does not complete, do not
2659                          * return with an error. This can happen in situations
2660                          * where there is no eeprom and prevents getting link.
2661                          */
2662                         e_dbg("Auto Read Done did not complete\n");
2663                 }
2664         }
2665         /* Dummy read to clear the phy wakeup bit after lcd reset */
2666         if (hw->mac.type == e1000_pchlan)
2667                 e1e_rphy(hw, BM_WUC, &reg);
2668
2669         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2670         if (ret_val)
2671                 goto out;
2672
2673         if (hw->mac.type == e1000_pchlan) {
2674                 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2675                 if (ret_val)
2676                         goto out;
2677         }
2678         /*
2679          * For PCH, this write will make sure that any noise
2680          * will be detected as a CRC error and be dropped rather than show up
2681          * as a bad packet to the DMA engine.
2682          */
2683         if (hw->mac.type == e1000_pchlan)
2684                 ew32(CRC_OFFSET, 0x65656565);
2685
2686         ew32(IMC, 0xffffffff);
2687         icr = er32(ICR);
2688
2689         kab = er32(KABGTXD);
2690         kab |= E1000_KABGTXD_BGSQLBIAS;
2691         ew32(KABGTXD, kab);
2692
2693         if (hw->mac.type == e1000_pchlan)
2694                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2695
2696 out:
2697         return ret_val;
2698 }
2699
2700 /**
2701  *  e1000_init_hw_ich8lan - Initialize the hardware
2702  *  @hw: pointer to the HW structure
2703  *
2704  *  Prepares the hardware for transmit and receive by doing the following:
2705  *   - initialize hardware bits
2706  *   - initialize LED identification
2707  *   - setup receive address registers
2708  *   - setup flow control
2709  *   - setup transmit descriptors
2710  *   - clear statistics
2711  **/
2712 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2713 {
2714         struct e1000_mac_info *mac = &hw->mac;
2715         u32 ctrl_ext, txdctl, snoop;
2716         s32 ret_val;
2717         u16 i;
2718
2719         e1000_initialize_hw_bits_ich8lan(hw);
2720
2721         /* Initialize identification LED */
2722         ret_val = mac->ops.id_led_init(hw);
2723         if (ret_val)
2724                 e_dbg("Error initializing identification LED\n");
2725                 /* This is not fatal and we should not stop init due to this */
2726
2727         /* Setup the receive address. */
2728         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2729
2730         /* Zero out the Multicast HASH table */
2731         e_dbg("Zeroing the MTA\n");
2732         for (i = 0; i < mac->mta_reg_count; i++)
2733                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2734
2735         /*
2736          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2737          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2738          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2739          */
2740         if (hw->phy.type == e1000_phy_82578) {
2741                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2742                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2743                 if (ret_val)
2744                         return ret_val;
2745         }
2746
2747         /* Setup link and flow control */
2748         ret_val = e1000_setup_link_ich8lan(hw);
2749
2750         /* Set the transmit descriptor write-back policy for both queues */
2751         txdctl = er32(TXDCTL(0));
2752         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2753                  E1000_TXDCTL_FULL_TX_DESC_WB;
2754         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2755                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2756         ew32(TXDCTL(0), txdctl);
2757         txdctl = er32(TXDCTL(1));
2758         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2759                  E1000_TXDCTL_FULL_TX_DESC_WB;
2760         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2761                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2762         ew32(TXDCTL(1), txdctl);
2763
2764         /*
2765          * ICH8 has opposite polarity of no_snoop bits.
2766          * By default, we should use snoop behavior.
2767          */
2768         if (mac->type == e1000_ich8lan)
2769                 snoop = PCIE_ICH8_SNOOP_ALL;
2770         else
2771                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2772         e1000e_set_pcie_no_snoop(hw, snoop);
2773
2774         ctrl_ext = er32(CTRL_EXT);
2775         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2776         ew32(CTRL_EXT, ctrl_ext);
2777
2778         /*
2779          * Clear all of the statistics registers (clear on read).  It is
2780          * important that we do this after we have tried to establish link
2781          * because the symbol error count will increment wildly if there
2782          * is no link.
2783          */
2784         e1000_clear_hw_cntrs_ich8lan(hw);
2785
2786         return 0;
2787 }
2788 /**
2789  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2790  *  @hw: pointer to the HW structure
2791  *
2792  *  Sets/Clears required hardware bits necessary for correctly setting up the
2793  *  hardware for transmit and receive.
2794  **/
2795 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2796 {
2797         u32 reg;
2798
2799         /* Extended Device Control */
2800         reg = er32(CTRL_EXT);
2801         reg |= (1 << 22);
2802         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2803         if (hw->mac.type >= e1000_pchlan)
2804                 reg |= E1000_CTRL_EXT_PHYPDEN;
2805         ew32(CTRL_EXT, reg);
2806
2807         /* Transmit Descriptor Control 0 */
2808         reg = er32(TXDCTL(0));
2809         reg |= (1 << 22);
2810         ew32(TXDCTL(0), reg);
2811
2812         /* Transmit Descriptor Control 1 */
2813         reg = er32(TXDCTL(1));
2814         reg |= (1 << 22);
2815         ew32(TXDCTL(1), reg);
2816
2817         /* Transmit Arbitration Control 0 */
2818         reg = er32(TARC(0));
2819         if (hw->mac.type == e1000_ich8lan)
2820                 reg |= (1 << 28) | (1 << 29);
2821         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2822         ew32(TARC(0), reg);
2823
2824         /* Transmit Arbitration Control 1 */
2825         reg = er32(TARC(1));
2826         if (er32(TCTL) & E1000_TCTL_MULR)
2827                 reg &= ~(1 << 28);
2828         else
2829                 reg |= (1 << 28);
2830         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2831         ew32(TARC(1), reg);
2832
2833         /* Device Status */
2834         if (hw->mac.type == e1000_ich8lan) {
2835                 reg = er32(STATUS);
2836                 reg &= ~(1 << 31);
2837                 ew32(STATUS, reg);
2838         }
2839 }
2840
2841 /**
2842  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2843  *  @hw: pointer to the HW structure
2844  *
2845  *  Determines which flow control settings to use, then configures flow
2846  *  control.  Calls the appropriate media-specific link configuration
2847  *  function.  Assuming the adapter has a valid link partner, a valid link
2848  *  should be established.  Assumes the hardware has previously been reset
2849  *  and the transmitter and receiver are not enabled.
2850  **/
2851 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2852 {
2853         s32 ret_val;
2854
2855         if (e1000_check_reset_block(hw))
2856                 return 0;
2857
2858         /*
2859          * ICH parts do not have a word in the NVM to determine
2860          * the default flow control setting, so we explicitly
2861          * set it to full.
2862          */
2863         if (hw->fc.requested_mode == e1000_fc_default) {
2864                 /* Workaround h/w hang when Tx flow control enabled */
2865                 if (hw->mac.type == e1000_pchlan)
2866                         hw->fc.requested_mode = e1000_fc_rx_pause;
2867                 else
2868                         hw->fc.requested_mode = e1000_fc_full;
2869         }
2870
2871         /*
2872          * Save off the requested flow control mode for use later.  Depending
2873          * on the link partner's capabilities, we may or may not use this mode.
2874          */
2875         hw->fc.current_mode = hw->fc.requested_mode;
2876
2877         e_dbg("After fix-ups FlowControl is now = %x\n",
2878                 hw->fc.current_mode);
2879
2880         /* Continue to configure the copper link. */
2881         ret_val = e1000_setup_copper_link_ich8lan(hw);
2882         if (ret_val)
2883                 return ret_val;
2884
2885         ew32(FCTTV, hw->fc.pause_time);
2886         if ((hw->phy.type == e1000_phy_82578) ||
2887             (hw->phy.type == e1000_phy_82577)) {
2888                 ret_val = hw->phy.ops.write_reg(hw,
2889                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2890                                              hw->fc.pause_time);
2891                 if (ret_val)
2892                         return ret_val;
2893         }
2894
2895         return e1000e_set_fc_watermarks(hw);
2896 }
2897
2898 /**
2899  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2900  *  @hw: pointer to the HW structure
2901  *
2902  *  Configures the kumeran interface to the PHY to wait the appropriate time
2903  *  when polling the PHY, then call the generic setup_copper_link to finish
2904  *  configuring the copper link.
2905  **/
2906 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2907 {
2908         u32 ctrl;
2909         s32 ret_val;
2910         u16 reg_data;
2911
2912         ctrl = er32(CTRL);
2913         ctrl |= E1000_CTRL_SLU;
2914         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2915         ew32(CTRL, ctrl);
2916
2917         /*
2918          * Set the mac to wait the maximum time between each iteration
2919          * and increase the max iterations when polling the phy;
2920          * this fixes erroneous timeouts at 10Mbps.
2921          */
2922         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2923         if (ret_val)
2924                 return ret_val;
2925         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2926         if (ret_val)
2927                 return ret_val;
2928         reg_data |= 0x3F;
2929         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2930         if (ret_val)
2931                 return ret_val;
2932
2933         switch (hw->phy.type) {
2934         case e1000_phy_igp_3:
2935                 ret_val = e1000e_copper_link_setup_igp(hw);
2936                 if (ret_val)
2937                         return ret_val;
2938                 break;
2939         case e1000_phy_bm:
2940         case e1000_phy_82578:
2941                 ret_val = e1000e_copper_link_setup_m88(hw);
2942                 if (ret_val)
2943                         return ret_val;
2944                 break;
2945         case e1000_phy_82577:
2946                 ret_val = e1000_copper_link_setup_82577(hw);
2947                 if (ret_val)
2948                         return ret_val;
2949                 break;
2950         case e1000_phy_ife:
2951                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2952                                                &reg_data);
2953                 if (ret_val)
2954                         return ret_val;
2955
2956                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2957
2958                 switch (hw->phy.mdix) {
2959                 case 1:
2960                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2961                         break;
2962                 case 2:
2963                         reg_data |= IFE_PMC_FORCE_MDIX;
2964                         break;
2965                 case 0:
2966                 default:
2967                         reg_data |= IFE_PMC_AUTO_MDIX;
2968                         break;
2969                 }
2970                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2971                                                 reg_data);
2972                 if (ret_val)
2973                         return ret_val;
2974                 break;
2975         default:
2976                 break;
2977         }
2978         return e1000e_setup_copper_link(hw);
2979 }
2980
2981 /**
2982  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2983  *  @hw: pointer to the HW structure
2984  *  @speed: pointer to store current link speed
2985  *  @duplex: pointer to store the current link duplex
2986  *
2987  *  Calls the generic get_speed_and_duplex to retrieve the current link
2988  *  information and then calls the Kumeran lock loss workaround for links at
2989  *  gigabit speeds.
2990  **/
2991 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2992                                           u16 *duplex)
2993 {
2994         s32 ret_val;
2995
2996         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2997         if (ret_val)
2998                 return ret_val;
2999
3000         if ((hw->mac.type == e1000_ich8lan) &&
3001             (hw->phy.type == e1000_phy_igp_3) &&
3002             (*speed == SPEED_1000)) {
3003                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3004         }
3005
3006         return ret_val;
3007 }
3008
3009 /**
3010  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3011  *  @hw: pointer to the HW structure
3012  *
3013  *  Work-around for 82566 Kumeran PCS lock loss:
3014  *  On link status change (i.e. PCI reset, speed change) and link is up and
3015  *  speed is gigabit-
3016  *    0) if workaround is optionally disabled do nothing
3017  *    1) wait 1ms for Kumeran link to come up
3018  *    2) check Kumeran Diagnostic register PCS lock loss bit
3019  *    3) if not set the link is locked (all is good), otherwise...
3020  *    4) reset the PHY
3021  *    5) repeat up to 10 times
3022  *  Note: this is only called for IGP3 copper when speed is 1gb.
3023  **/
3024 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3025 {
3026         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3027         u32 phy_ctrl;
3028         s32 ret_val;
3029         u16 i, data;
3030         bool link;
3031
3032         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3033                 return 0;
3034
3035         /*
3036          * Make sure link is up before proceeding.  If not just return.
3037          * Attempting this while link is negotiating fouled up link
3038          * stability
3039          */
3040         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3041         if (!link)
3042                 return 0;
3043
3044         for (i = 0; i < 10; i++) {
3045                 /* read once to clear */
3046                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3047                 if (ret_val)
3048                         return ret_val;
3049                 /* and again to get new status */
3050                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3051                 if (ret_val)
3052                         return ret_val;
3053
3054                 /* check for PCS lock */
3055                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3056                         return 0;
3057
3058                 /* Issue PHY reset */
3059                 e1000_phy_hw_reset(hw);
3060                 mdelay(5);
3061         }
3062         /* Disable GigE link negotiation */
3063         phy_ctrl = er32(PHY_CTRL);
3064         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3065                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3066         ew32(PHY_CTRL, phy_ctrl);
3067
3068         /*
3069          * Call gig speed drop workaround on Gig disable before accessing
3070          * any PHY registers
3071          */
3072         e1000e_gig_downshift_workaround_ich8lan(hw);
3073
3074         /* unable to acquire PCS lock */
3075         return -E1000_ERR_PHY;
3076 }
3077
3078 /**
3079  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3080  *  @hw: pointer to the HW structure
3081  *  @state: boolean value used to set the current Kumeran workaround state
3082  *
3083  *  If ICH8, set the current Kumeran workaround state (enabled - true
3084  *  /disabled - false).
3085  **/
3086 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3087                                                  bool state)
3088 {
3089         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3090
3091         if (hw->mac.type != e1000_ich8lan) {
3092                 e_dbg("Workaround applies to ICH8 only.\n");
3093                 return;
3094         }
3095
3096         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3097 }
3098
3099 /**
3100  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3101  *  @hw: pointer to the HW structure
3102  *
3103  *  Workaround for 82566 power-down on D3 entry:
3104  *    1) disable gigabit link
3105  *    2) write VR power-down enable
3106  *    3) read it back
3107  *  Continue if successful, else issue LCD reset and repeat
3108  **/
3109 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3110 {
3111         u32 reg;
3112         u16 data;
3113         u8  retry = 0;
3114
3115         if (hw->phy.type != e1000_phy_igp_3)
3116                 return;
3117
3118         /* Try the workaround twice (if needed) */
3119         do {
3120                 /* Disable link */
3121                 reg = er32(PHY_CTRL);
3122                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3123                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3124                 ew32(PHY_CTRL, reg);
3125
3126                 /*
3127                  * Call gig speed drop workaround on Gig disable before
3128                  * accessing any PHY registers
3129                  */
3130                 if (hw->mac.type == e1000_ich8lan)
3131                         e1000e_gig_downshift_workaround_ich8lan(hw);
3132
3133                 /* Write VR power-down enable */
3134                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3135                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3136                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3137
3138                 /* Read it back and test */
3139                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3140                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3141                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3142                         break;
3143
3144                 /* Issue PHY reset and repeat at most one more time */
3145                 reg = er32(CTRL);
3146                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3147                 retry++;
3148         } while (retry);
3149 }
3150
3151 /**
3152  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3153  *  @hw: pointer to the HW structure
3154  *
3155  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3156  *  LPLU, Gig disable, MDIC PHY reset):
3157  *    1) Set Kumeran Near-end loopback
3158  *    2) Clear Kumeran Near-end loopback
3159  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3160  **/
3161 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3162 {
3163         s32 ret_val;
3164         u16 reg_data;
3165
3166         if ((hw->mac.type != e1000_ich8lan) ||
3167             (hw->phy.type != e1000_phy_igp_3))
3168                 return;
3169
3170         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3171                                       &reg_data);
3172         if (ret_val)
3173                 return;
3174         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3175         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3176                                        reg_data);
3177         if (ret_val)
3178                 return;
3179         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3180         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3181                                        reg_data);
3182 }
3183
3184 /**
3185  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3186  *  @hw: pointer to the HW structure
3187  *
3188  *  During S0 to Sx transition, it is possible the link remains at gig
3189  *  instead of negotiating to a lower speed.  Before going to Sx, set
3190  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3191  *  to a lower speed.
3192  *
3193  *  Should only be called for applicable parts.
3194  **/
3195 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3196 {
3197         u32 phy_ctrl;
3198
3199         switch (hw->mac.type) {
3200         case e1000_ich9lan:
3201         case e1000_ich10lan:
3202         case e1000_pchlan:
3203                 phy_ctrl = er32(PHY_CTRL);
3204                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3205                             E1000_PHY_CTRL_GBE_DISABLE;
3206                 ew32(PHY_CTRL, phy_ctrl);
3207
3208                 if (hw->mac.type == e1000_pchlan)
3209                         e1000_phy_hw_reset_ich8lan(hw);
3210         default:
3211                 break;
3212         }
3213
3214         return;
3215 }
3216
3217 /**
3218  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3219  *  @hw: pointer to the HW structure
3220  *
3221  *  Return the LED back to the default configuration.
3222  **/
3223 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3224 {
3225         if (hw->phy.type == e1000_phy_ife)
3226                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3227
3228         ew32(LEDCTL, hw->mac.ledctl_default);
3229         return 0;
3230 }
3231
3232 /**
3233  *  e1000_led_on_ich8lan - Turn LEDs on
3234  *  @hw: pointer to the HW structure
3235  *
3236  *  Turn on the LEDs.
3237  **/
3238 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3239 {
3240         if (hw->phy.type == e1000_phy_ife)
3241                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3242                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3243
3244         ew32(LEDCTL, hw->mac.ledctl_mode2);
3245         return 0;
3246 }
3247
3248 /**
3249  *  e1000_led_off_ich8lan - Turn LEDs off
3250  *  @hw: pointer to the HW structure
3251  *
3252  *  Turn off the LEDs.
3253  **/
3254 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3255 {
3256         if (hw->phy.type == e1000_phy_ife)
3257                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3258                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3259
3260         ew32(LEDCTL, hw->mac.ledctl_mode1);
3261         return 0;
3262 }
3263
3264 /**
3265  *  e1000_setup_led_pchlan - Configures SW controllable LED
3266  *  @hw: pointer to the HW structure
3267  *
3268  *  This prepares the SW controllable LED for use.
3269  **/
3270 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3271 {
3272         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3273                                         (u16)hw->mac.ledctl_mode1);
3274 }
3275
3276 /**
3277  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3278  *  @hw: pointer to the HW structure
3279  *
3280  *  Return the LED back to the default configuration.
3281  **/
3282 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3283 {
3284         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3285                                         (u16)hw->mac.ledctl_default);
3286 }
3287
3288 /**
3289  *  e1000_led_on_pchlan - Turn LEDs on
3290  *  @hw: pointer to the HW structure
3291  *
3292  *  Turn on the LEDs.
3293  **/
3294 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3295 {
3296         u16 data = (u16)hw->mac.ledctl_mode2;
3297         u32 i, led;
3298
3299         /*
3300          * If no link, then turn LED on by setting the invert bit
3301          * for each LED that's mode is "link_up" in ledctl_mode2.
3302          */
3303         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3304                 for (i = 0; i < 3; i++) {
3305                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3306                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3307                             E1000_LEDCTL_MODE_LINK_UP)
3308                                 continue;
3309                         if (led & E1000_PHY_LED0_IVRT)
3310                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3311                         else
3312                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3313                 }
3314         }
3315
3316         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3317 }
3318
3319 /**
3320  *  e1000_led_off_pchlan - Turn LEDs off
3321  *  @hw: pointer to the HW structure
3322  *
3323  *  Turn off the LEDs.
3324  **/
3325 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3326 {
3327         u16 data = (u16)hw->mac.ledctl_mode1;
3328         u32 i, led;
3329
3330         /*
3331          * If no link, then turn LED off by clearing the invert bit
3332          * for each LED that's mode is "link_up" in ledctl_mode1.
3333          */
3334         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3335                 for (i = 0; i < 3; i++) {
3336                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3337                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3338                             E1000_LEDCTL_MODE_LINK_UP)
3339                                 continue;
3340                         if (led & E1000_PHY_LED0_IVRT)
3341                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3342                         else
3343                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3344                 }
3345         }
3346
3347         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3348 }
3349
3350 /**
3351  *  e1000_get_cfg_done_ich8lan - Read config done bit
3352  *  @hw: pointer to the HW structure
3353  *
3354  *  Read the management control register for the config done bit for
3355  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3356  *  to read the config done bit, so an error is *ONLY* logged and returns
3357  *  0.  If we were to return with error, EEPROM-less silicon
3358  *  would not be able to be reset or change link.
3359  **/
3360 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3361 {
3362         u32 bank = 0;
3363
3364         if (hw->mac.type >= e1000_pchlan) {
3365                 u32 status = er32(STATUS);
3366
3367                 if (status & E1000_STATUS_PHYRA)
3368                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3369                 else
3370                         e_dbg("PHY Reset Asserted not set - needs delay\n");
3371         }
3372
3373         e1000e_get_cfg_done(hw);
3374
3375         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3376         if ((hw->mac.type != e1000_ich10lan) &&
3377             (hw->mac.type != e1000_pchlan)) {
3378                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3379                     (hw->phy.type == e1000_phy_igp_3)) {
3380                         e1000e_phy_init_script_igp3(hw);
3381                 }
3382         } else {
3383                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3384                         /* Maybe we should do a basic PHY config */
3385                         e_dbg("EEPROM not present\n");
3386                         return -E1000_ERR_CONFIG;
3387                 }
3388         }
3389
3390         return 0;
3391 }
3392
3393 /**
3394  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3395  *  @hw: pointer to the HW structure
3396  *
3397  *  Clears hardware counters specific to the silicon family and calls
3398  *  clear_hw_cntrs_generic to clear all general purpose counters.
3399  **/
3400 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3401 {
3402         u16 phy_data;
3403
3404         e1000e_clear_hw_cntrs_base(hw);
3405
3406         er32(ALGNERRC);
3407         er32(RXERRC);
3408         er32(TNCRS);
3409         er32(CEXTERR);
3410         er32(TSCTC);
3411         er32(TSCTFC);
3412
3413         er32(MGTPRC);
3414         er32(MGTPDC);
3415         er32(MGTPTC);
3416
3417         er32(IAC);
3418         er32(ICRXOC);
3419
3420         /* Clear PHY statistics registers */
3421         if ((hw->phy.type == e1000_phy_82578) ||
3422             (hw->phy.type == e1000_phy_82577)) {
3423                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3424                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3425                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3426                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3427                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3428                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3429                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3430                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3431                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3432                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3433                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3434                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3435                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3436                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3437         }
3438 }
3439
3440 static struct e1000_mac_operations ich8_mac_ops = {
3441         .id_led_init            = e1000e_id_led_init,
3442         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3443         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3444         /* cleanup_led dependent on mac type */
3445         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3446         .get_bus_info           = e1000_get_bus_info_ich8lan,
3447         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3448         /* led_on dependent on mac type */
3449         /* led_off dependent on mac type */
3450         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3451         .reset_hw               = e1000_reset_hw_ich8lan,
3452         .init_hw                = e1000_init_hw_ich8lan,
3453         .setup_link             = e1000_setup_link_ich8lan,
3454         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3455         /* id_led_init dependent on mac type */
3456 };
3457
3458 static struct e1000_phy_operations ich8_phy_ops = {
3459         .acquire                = e1000_acquire_swflag_ich8lan,
3460         .check_reset_block      = e1000_check_reset_block_ich8lan,
3461         .commit                 = NULL,
3462         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
3463         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3464         .get_cable_length       = e1000e_get_cable_length_igp_2,
3465         .get_info               = e1000_get_phy_info_ich8lan,
3466         .read_reg               = e1000e_read_phy_reg_igp,
3467         .release                = e1000_release_swflag_ich8lan,
3468         .reset                  = e1000_phy_hw_reset_ich8lan,
3469         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3470         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3471         .write_reg              = e1000e_write_phy_reg_igp,
3472 };
3473
3474 static struct e1000_nvm_operations ich8_nvm_ops = {
3475         .acquire                = e1000_acquire_nvm_ich8lan,
3476         .read                   = e1000_read_nvm_ich8lan,
3477         .release                = e1000_release_nvm_ich8lan,
3478         .update                 = e1000_update_nvm_checksum_ich8lan,
3479         .valid_led_default      = e1000_valid_led_default_ich8lan,
3480         .validate               = e1000_validate_nvm_checksum_ich8lan,
3481         .write                  = e1000_write_nvm_ich8lan,
3482 };
3483
3484 struct e1000_info e1000_ich8_info = {
3485         .mac                    = e1000_ich8lan,
3486         .flags                  = FLAG_HAS_WOL
3487                                   | FLAG_IS_ICH
3488                                   | FLAG_RX_CSUM_ENABLED
3489                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3490                                   | FLAG_HAS_AMT
3491                                   | FLAG_HAS_FLASH
3492                                   | FLAG_APME_IN_WUC,
3493         .pba                    = 8,
3494         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3495         .get_variants           = e1000_get_variants_ich8lan,
3496         .mac_ops                = &ich8_mac_ops,
3497         .phy_ops                = &ich8_phy_ops,
3498         .nvm_ops                = &ich8_nvm_ops,
3499 };
3500
3501 struct e1000_info e1000_ich9_info = {
3502         .mac                    = e1000_ich9lan,
3503         .flags                  = FLAG_HAS_JUMBO_FRAMES
3504                                   | FLAG_IS_ICH
3505                                   | FLAG_HAS_WOL
3506                                   | FLAG_RX_CSUM_ENABLED
3507                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3508                                   | FLAG_HAS_AMT
3509                                   | FLAG_HAS_ERT
3510                                   | FLAG_HAS_FLASH
3511                                   | FLAG_APME_IN_WUC,
3512         .pba                    = 10,
3513         .max_hw_frame_size      = DEFAULT_JUMBO,
3514         .get_variants           = e1000_get_variants_ich8lan,
3515         .mac_ops                = &ich8_mac_ops,
3516         .phy_ops                = &ich8_phy_ops,
3517         .nvm_ops                = &ich8_nvm_ops,
3518 };
3519
3520 struct e1000_info e1000_ich10_info = {
3521         .mac                    = e1000_ich10lan,
3522         .flags                  = FLAG_HAS_JUMBO_FRAMES
3523                                   | FLAG_IS_ICH
3524                                   | FLAG_HAS_WOL
3525                                   | FLAG_RX_CSUM_ENABLED
3526                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3527                                   | FLAG_HAS_AMT
3528                                   | FLAG_HAS_ERT
3529                                   | FLAG_HAS_FLASH
3530                                   | FLAG_APME_IN_WUC,
3531         .pba                    = 10,
3532         .max_hw_frame_size      = DEFAULT_JUMBO,
3533         .get_variants           = e1000_get_variants_ich8lan,
3534         .mac_ops                = &ich8_mac_ops,
3535         .phy_ops                = &ich8_phy_ops,
3536         .nvm_ops                = &ich8_nvm_ops,
3537 };
3538
3539 struct e1000_info e1000_pch_info = {
3540         .mac                    = e1000_pchlan,
3541         .flags                  = FLAG_IS_ICH
3542                                   | FLAG_HAS_WOL
3543                                   | FLAG_RX_CSUM_ENABLED
3544                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3545                                   | FLAG_HAS_AMT
3546                                   | FLAG_HAS_FLASH
3547                                   | FLAG_HAS_JUMBO_FRAMES
3548                                   | FLAG_APME_IN_WUC,
3549         .pba                    = 26,
3550         .max_hw_frame_size      = 4096,
3551         .get_variants           = e1000_get_variants_ich8lan,
3552         .mac_ops                = &ich8_mac_ops,
3553         .phy_ops                = &ich8_phy_ops,
3554         .nvm_ops                = &ich8_nvm_ops,
3555 };