drivers/net/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82571EB Gigabit Ethernet Controller
  31  * 82571EB Gigabit Ethernet Controller (Copper)
  32  * 82571EB Gigabit Ethernet Controller (Fiber)
  33  * 82571EB Dual Port Gigabit Mezzanine Adapter
  34  * 82571EB Quad Port Gigabit Mezzanine Adapter
  35  * 82571PT Gigabit PT Quad Port Server ExpressModule
  36  * 82572EI Gigabit Ethernet Controller (Copper)
  37  * 82572EI Gigabit Ethernet Controller (Fiber)
  38  * 82572EI Gigabit Ethernet Controller
  39  * 82573V Gigabit Ethernet Controller (Copper)
  40  * 82573E Gigabit Ethernet Controller (Copper)
  41  * 82573L Gigabit Ethernet Controller
  42  * 82574L Gigabit Network Connection
  43  * 82583V Gigabit Network Connection
  44  */
  45
  46 #include "e1000.h"
  47
  48 #define ID_LED_RESERVED_F746 0xF746
  49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  50                               (ID_LED_OFF1_ON2  <<  8) | \
  51                               (ID_LED_DEF1_DEF2 <<  4) | \
  52                               (ID_LED_DEF1_DEF2))
  53
  54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  55
  56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
  57
  58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  63                                       u16 words, u16 *data);
  64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  73
  74 /**
  75  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  76  *  @hw: pointer to the HW structure
  77  **/
  78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  79 {
  80         struct e1000_phy_info *phy = &hw->phy;
  81         s32 ret_val;
  82
  83         if (hw->phy.media_type != e1000_media_type_copper) {
  84                 phy->type = e1000_phy_none;
  85                 return 0;
  86         }
  87
  88         phy->addr                        = 1;
  89         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  90         phy->reset_delay_us              = 100;
  91
  92         phy->ops.power_up                = e1000_power_up_phy_copper;
  93         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
  94
  95         switch (hw->mac.type) {
  96         case e1000_82571:
  97         case e1000_82572:
  98                 phy->type                = e1000_phy_igp_2;
  99                 break;
 100         case e1000_82573:
 101                 phy->type                = e1000_phy_m88;
 102                 break;
 103         case e1000_82574:
 104         case e1000_82583:
 105                 phy->type                = e1000_phy_bm;
 106                 break;
 107         default:
 108                 return -E1000_ERR_PHY;
 109                 break;
 110         }
 111
 112         /* This can only be done after all function pointers are setup. */
 113         ret_val = e1000_get_phy_id_82571(hw);
 114
 115         /* Verify phy id */
 116         switch (hw->mac.type) {
 117         case e1000_82571:
 118         case e1000_82572:
 119                 if (phy->id != IGP01E1000_I_PHY_ID)
 120                         return -E1000_ERR_PHY;
 121                 break;
 122         case e1000_82573:
 123                 if (phy->id != M88E1111_I_PHY_ID)
 124                         return -E1000_ERR_PHY;
 125                 break;
 126         case e1000_82574:
 127         case e1000_82583:
 128                 if (phy->id != BME1000_E_PHY_ID_R2)
 129                         return -E1000_ERR_PHY;
 130                 break;
 131         default:
 132                 return -E1000_ERR_PHY;
 133                 break;
 134         }
 135
 136         return 0;
 137 }
 138
 139 /**
 140  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 141  *  @hw: pointer to the HW structure
 142  **/
 143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 144 {
 145         struct e1000_nvm_info *nvm = &hw->nvm;
 146         u32 eecd = er32(EECD);
 147         u16 size;
 148
 149         nvm->opcode_bits = 8;
 150         nvm->delay_usec = 1;
 151         switch (nvm->override) {
 152         case e1000_nvm_override_spi_large:
 153                 nvm->page_size = 32;
 154                 nvm->address_bits = 16;
 155                 break;
 156         case e1000_nvm_override_spi_small:
 157                 nvm->page_size = 8;
 158                 nvm->address_bits = 8;
 159                 break;
 160         default:
 161                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 162                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 163                 break;
 164         }
 165
 166         switch (hw->mac.type) {
 167         case e1000_82573:
 168         case e1000_82574:
 169         case e1000_82583:
 170                 if (((eecd >> 15) & 0x3) == 0x3) {
 171                         nvm->type = e1000_nvm_flash_hw;
 172                         nvm->word_size = 2048;
 173                         /*
 174                          * Autonomous Flash update bit must be cleared due
 175                          * to Flash update issue.
 176                          */
 177                         eecd &= ~E1000_EECD_AUPDEN;
 178                         ew32(EECD, eecd);
 179                         break;
 180                 }
 181                 /* Fall Through */
 182         default:
 183                 nvm->type = e1000_nvm_eeprom_spi;
 184                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 185                                   E1000_EECD_SIZE_EX_SHIFT);
 186                 /*
 187                  * Added to a constant, "size" becomes the left-shift value
 188                  * for setting word_size.
 189                  */
 190                 size += NVM_WORD_SIZE_BASE_SHIFT;
 191
 192                 /* EEPROM access above 16k is unsupported */
 193                 if (size > 14)
 194                         size = 14;
 195                 nvm->word_size  = 1 << size;
 196                 break;
 197         }
 198
 199         return 0;
 200 }
 201
 202 /**
 203  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 204  *  @hw: pointer to the HW structure
 205  **/
 206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
 207 {
 208         struct e1000_hw *hw = &adapter->hw;
 209         struct e1000_mac_info *mac = &hw->mac;
 210         struct e1000_mac_operations *func = &mac->ops;
 211         u32 swsm = 0;
 212         u32 swsm2 = 0;
 213         bool force_clear_smbi = false;
 214
 215         /* Set media type */
 216         switch (adapter->pdev->device) {
 217         case E1000_DEV_ID_82571EB_FIBER:
 218         case E1000_DEV_ID_82572EI_FIBER:
 219         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 220                 hw->phy.media_type = e1000_media_type_fiber;
 221                 break;
 222         case E1000_DEV_ID_82571EB_SERDES:
 223         case E1000_DEV_ID_82572EI_SERDES:
 224         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 225         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 226                 hw->phy.media_type = e1000_media_type_internal_serdes;
 227                 break;
 228         default:
 229                 hw->phy.media_type = e1000_media_type_copper;
 230                 break;
 231         }
 232
 233         /* Set mta register count */
 234         mac->mta_reg_count = 128;
 235         /* Set rar entry count */
 236         mac->rar_entry_count = E1000_RAR_ENTRIES;
 237         /* Adaptive IFS supported */
 238         mac->adaptive_ifs = true;
 239
 240         /* check for link */
 241         switch (hw->phy.media_type) {
 242         case e1000_media_type_copper:
 243                 func->setup_physical_interface = e1000_setup_copper_link_82571;
 244                 func->check_for_link = e1000e_check_for_copper_link;
 245                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
 246                 break;
 247         case e1000_media_type_fiber:
 248                 func->setup_physical_interface =
 249                         e1000_setup_fiber_serdes_link_82571;
 250                 func->check_for_link = e1000e_check_for_fiber_link;
 251                 func->get_link_up_info =
 252                         e1000e_get_speed_and_duplex_fiber_serdes;
 253                 break;
 254         case e1000_media_type_internal_serdes:
 255                 func->setup_physical_interface =
 256                         e1000_setup_fiber_serdes_link_82571;
 257                 func->check_for_link = e1000_check_for_serdes_link_82571;
 258                 func->get_link_up_info =
 259                         e1000e_get_speed_and_duplex_fiber_serdes;
 260                 break;
 261         default:
 262                 return -E1000_ERR_CONFIG;
 263                 break;
 264         }
 265
 266         switch (hw->mac.type) {
 267         case e1000_82573:
 268                 func->set_lan_id = e1000_set_lan_id_single_port;
 269                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 270                 func->led_on = e1000e_led_on_generic;
 271
 272                 /* FWSM register */
 273                 mac->has_fwsm = true;
 274                 /*
 275                  * ARC supported; valid only if manageability features are
 276                  * enabled.
 277                  */
 278                 mac->arc_subsystem_valid =
 279                         (er32(FWSM) & E1000_FWSM_MODE_MASK)
 280                         ? true : false;
 281                 break;
 282         case e1000_82574:
 283         case e1000_82583:
 284                 func->set_lan_id = e1000_set_lan_id_single_port;
 285                 func->check_mng_mode = e1000_check_mng_mode_82574;
 286                 func->led_on = e1000_led_on_82574;
 287                 break;
 288         default:
 289                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 290                 func->led_on = e1000e_led_on_generic;
 291
 292                 /* FWSM register */
 293                 mac->has_fwsm = true;
 294                 break;
 295         }
 296
 297         /*
 298          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 299          * first NVM or PHY acess. This should be done for single-port
 300          * devices, and for one port only on dual-port devices so that
 301          * for those devices we can still use the SMBI lock to synchronize
 302          * inter-port accesses to the PHY & NVM.
 303          */
 304         switch (hw->mac.type) {
 305         case e1000_82571:
 306         case e1000_82572:
 307                 swsm2 = er32(SWSM2);
 308
 309                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 310                         /* Only do this for the first interface on this card */
 311                         ew32(SWSM2,
 312                             swsm2 | E1000_SWSM2_LOCK);
 313                         force_clear_smbi = true;
 314                 } else
 315                         force_clear_smbi = false;
 316                 break;
 317         default:
 318                 force_clear_smbi = true;
 319                 break;
 320         }
 321
 322         if (force_clear_smbi) {
 323                 /* Make sure SWSM.SMBI is clear */
 324                 swsm = er32(SWSM);
 325                 if (swsm & E1000_SWSM_SMBI) {
 326                         /* This bit should not be set on a first interface, and
 327                          * indicates that the bootagent or EFI code has
 328                          * improperly left this bit enabled
 329                          */
 330                         e_dbg("Please update your 82571 Bootagent\n");
 331                 }
 332                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 333         }
 334
 335         /*
 336          * Initialize device specific counter of SMBI acquisition
 337          * timeouts.
 338          */
 339          hw->dev_spec.e82571.smb_counter = 0;
 340
 341         return 0;
 342 }
 343
 344 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 345 {
 346         struct e1000_hw *hw = &adapter->hw;
 347         static int global_quad_port_a; /* global port a indication */
 348         struct pci_dev *pdev = adapter->pdev;
 349         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 350         s32 rc;
 351
 352         rc = e1000_init_mac_params_82571(adapter);
 353         if (rc)
 354                 return rc;
 355
 356         rc = e1000_init_nvm_params_82571(hw);
 357         if (rc)
 358                 return rc;
 359
 360         rc = e1000_init_phy_params_82571(hw);
 361         if (rc)
 362                 return rc;
 363
 364         /* tag quad port adapters first, it's used below */
 365         switch (pdev->device) {
 366         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 367         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 368         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 369         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 370                 adapter->flags |= FLAG_IS_QUAD_PORT;
 371                 /* mark the first port */
 372                 if (global_quad_port_a == 0)
 373                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 374                 /* Reset for multiple quad port adapters */
 375                 global_quad_port_a++;
 376                 if (global_quad_port_a == 4)
 377                         global_quad_port_a = 0;
 378                 break;
 379         default:
 380                 break;
 381         }
 382
 383         switch (adapter->hw.mac.type) {
 384         case e1000_82571:
 385                 /* these dual ports don't have WoL on port B at all */
 386                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 387                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 388                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 389                     (is_port_b))
 390                         adapter->flags &= ~FLAG_HAS_WOL;
 391                 /* quad ports only support WoL on port A */
 392                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 393                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 394                         adapter->flags &= ~FLAG_HAS_WOL;
 395                 /* Does not support WoL on any port */
 396                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 397                         adapter->flags &= ~FLAG_HAS_WOL;
 398                 break;
 399         case e1000_82573:
 400         case e1000_82574:
 401         case e1000_82583:
 402                 /* Disable ASPM L0s due to hardware errata */
 403                 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S);
 404
 405                 if (pdev->device == E1000_DEV_ID_82573L) {
 406                         adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 407                         adapter->max_hw_frame_size = DEFAULT_JUMBO;
 408                 }
 409                 break;
 410         default:
 411                 break;
 412         }
 413
 414         return 0;
 415 }
 416
 417 /**
 418  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 419  *  @hw: pointer to the HW structure
 420  *
 421  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 422  *  revision in the hardware structure.
 423  **/
 424 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 425 {
 426         struct e1000_phy_info *phy = &hw->phy;
 427         s32 ret_val;
 428         u16 phy_id = 0;
 429
 430         switch (hw->mac.type) {
 431         case e1000_82571:
 432         case e1000_82572:
 433                 /*
 434                  * The 82571 firmware may still be configuring the PHY.
 435                  * In this case, we cannot access the PHY until the
 436                  * configuration is done.  So we explicitly set the
 437                  * PHY ID.
 438                  */
 439                 phy->id = IGP01E1000_I_PHY_ID;
 440                 break;
 441         case e1000_82573:
 442                 return e1000e_get_phy_id(hw);
 443                 break;
 444         case e1000_82574:
 445         case e1000_82583:
 446                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
 447                 if (ret_val)
 448                         return ret_val;
 449
 450                 phy->id = (u32)(phy_id << 16);
 451                 udelay(20);
 452                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
 453                 if (ret_val)
 454                         return ret_val;
 455
 456                 phy->id |= (u32)(phy_id);
 457                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 458                 break;
 459         default:
 460                 return -E1000_ERR_PHY;
 461                 break;
 462         }
 463
 464         return 0;
 465 }
 466
 467 /**
 468  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 469  *  @hw: pointer to the HW structure
 470  *
 471  *  Acquire the HW semaphore to access the PHY or NVM
 472  **/
 473 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 474 {
 475         u32 swsm;
 476         s32 sw_timeout = hw->nvm.word_size + 1;
 477         s32 fw_timeout = hw->nvm.word_size + 1;
 478         s32 i = 0;
 479
 480         /*
 481          * If we have timedout 3 times on trying to acquire
 482          * the inter-port SMBI semaphore, there is old code
 483          * operating on the other port, and it is not
 484          * releasing SMBI. Modify the number of times that
 485          * we try for the semaphore to interwork with this
 486          * older code.
 487          */
 488         if (hw->dev_spec.e82571.smb_counter > 2)
 489                 sw_timeout = 1;
 490
 491         /* Get the SW semaphore */
 492         while (i < sw_timeout) {
 493                 swsm = er32(SWSM);
 494                 if (!(swsm & E1000_SWSM_SMBI))
 495                         break;
 496
 497                 udelay(50);
 498                 i++;
 499         }
 500
 501         if (i == sw_timeout) {
 502                 e_dbg("Driver can't access device - SMBI bit is set.\n");
 503                 hw->dev_spec.e82571.smb_counter++;
 504         }
 505         /* Get the FW semaphore. */
 506         for (i = 0; i < fw_timeout; i++) {
 507                 swsm = er32(SWSM);
 508                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 509
 510                 /* Semaphore acquired if bit latched */
 511                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 512                         break;
 513
 514                 udelay(50);
 515         }
 516
 517         if (i == fw_timeout) {
 518                 /* Release semaphores */
 519                 e1000_put_hw_semaphore_82571(hw);
 520                 e_dbg("Driver can't access the NVM\n");
 521                 return -E1000_ERR_NVM;
 522         }
 523
 524         return 0;
 525 }
 526
 527 /**
 528  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 529  *  @hw: pointer to the HW structure
 530  *
 531  *  Release hardware semaphore used to access the PHY or NVM
 532  **/
 533 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 534 {
 535         u32 swsm;
 536
 537         swsm = er32(SWSM);
 538         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 539         ew32(SWSM, swsm);
 540 }
 541
 542 /**
 543  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 544  *  @hw: pointer to the HW structure
 545  *
 546  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 547  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 548  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 549  *  hardware semaphore.
 550  **/
 551 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 552 {
 553         s32 ret_val;
 554
 555         ret_val = e1000_get_hw_semaphore_82571(hw);
 556         if (ret_val)
 557                 return ret_val;
 558
 559         switch (hw->mac.type) {
 560         case e1000_82573:
 561         case e1000_82574:
 562         case e1000_82583:
 563                 break;
 564         default:
 565                 ret_val = e1000e_acquire_nvm(hw);
 566                 break;
 567         }
 568
 569         if (ret_val)
 570                 e1000_put_hw_semaphore_82571(hw);
 571
 572         return ret_val;
 573 }
 574
 575 /**
 576  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 577  *  @hw: pointer to the HW structure
 578  *
 579  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 580  **/
 581 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 582 {
 583         e1000e_release_nvm(hw);
 584         e1000_put_hw_semaphore_82571(hw);
 585 }
 586
 587 /**
 588  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 589  *  @hw: pointer to the HW structure
 590  *  @offset: offset within the EEPROM to be written to
 591  *  @words: number of words to write
 592  *  @data: 16 bit word(s) to be written to the EEPROM
 593  *
 594  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 595  *
 596  *  If e1000e_update_nvm_checksum is not called after this function, the
 597  *  EEPROM will most likely contain an invalid checksum.
 598  **/
 599 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 600                                  u16 *data)
 601 {
 602         s32 ret_val;
 603
 604         switch (hw->mac.type) {
 605         case e1000_82573:
 606         case e1000_82574:
 607         case e1000_82583:
 608                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 609                 break;
 610         case e1000_82571:
 611         case e1000_82572:
 612                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 613                 break;
 614         default:
 615                 ret_val = -E1000_ERR_NVM;
 616                 break;
 617         }
 618
 619         return ret_val;
 620 }
 621
 622 /**
 623  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 624  *  @hw: pointer to the HW structure
 625  *
 626  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 627  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 628  *  value to the EEPROM.
 629  **/
 630 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 631 {
 632         u32 eecd;
 633         s32 ret_val;
 634         u16 i;
 635
 636         ret_val = e1000e_update_nvm_checksum_generic(hw);
 637         if (ret_val)
 638                 return ret_val;
 639
 640         /*
 641          * If our nvm is an EEPROM, then we're done
 642          * otherwise, commit the checksum to the flash NVM.
 643          */
 644         if (hw->nvm.type != e1000_nvm_flash_hw)
 645                 return ret_val;
 646
 647         /* Check for pending operations. */
 648         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 649                 msleep(1);
 650                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 651                         break;
 652         }
 653
 654         if (i == E1000_FLASH_UPDATES)
 655                 return -E1000_ERR_NVM;
 656
 657         /* Reset the firmware if using STM opcode. */
 658         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 659                 /*
 660                  * The enabling of and the actual reset must be done
 661                  * in two write cycles.
 662                  */
 663                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 664                 e1e_flush();
 665                 ew32(HICR, E1000_HICR_FW_RESET);
 666         }
 667
 668         /* Commit the write to flash */
 669         eecd = er32(EECD) | E1000_EECD_FLUPD;
 670         ew32(EECD, eecd);
 671
 672         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 673                 msleep(1);
 674                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 675                         break;
 676         }
 677
 678         if (i == E1000_FLASH_UPDATES)
 679                 return -E1000_ERR_NVM;
 680
 681         return 0;
 682 }
 683
 684 /**
 685  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 686  *  @hw: pointer to the HW structure
 687  *
 688  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 689  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 690  **/
 691 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 692 {
 693         if (hw->nvm.type == e1000_nvm_flash_hw)
 694                 e1000_fix_nvm_checksum_82571(hw);
 695
 696         return e1000e_validate_nvm_checksum_generic(hw);
 697 }
 698
 699 /**
 700  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 701  *  @hw: pointer to the HW structure
 702  *  @offset: offset within the EEPROM to be written to
 703  *  @words: number of words to write
 704  *  @data: 16 bit word(s) to be written to the EEPROM
 705  *
 706  *  After checking for invalid values, poll the EEPROM to ensure the previous
 707  *  command has completed before trying to write the next word.  After write
 708  *  poll for completion.
 709  *
 710  *  If e1000e_update_nvm_checksum is not called after this function, the
 711  *  EEPROM will most likely contain an invalid checksum.
 712  **/
 713 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 714                                       u16 words, u16 *data)
 715 {
 716         struct e1000_nvm_info *nvm = &hw->nvm;
 717         u32 i, eewr = 0;
 718         s32 ret_val = 0;
 719
 720         /*
 721          * A check for invalid values:  offset too large, too many words,
 722          * and not enough words.
 723          */
 724         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 725             (words == 0)) {
 726                 e_dbg("nvm parameter(s) out of bounds\n");
 727                 return -E1000_ERR_NVM;
 728         }
 729
 730         for (i = 0; i < words; i++) {
 731                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 732                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 733                        E1000_NVM_RW_REG_START;
 734
 735                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 736                 if (ret_val)
 737                         break;
 738
 739                 ew32(EEWR, eewr);
 740
 741                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 742                 if (ret_val)
 743                         break;
 744         }
 745
 746         return ret_val;
 747 }
 748
 749 /**
 750  *  e1000_get_cfg_done_82571 - Poll for configuration done
 751  *  @hw: pointer to the HW structure
 752  *
 753  *  Reads the management control register for the config done bit to be set.
 754  **/
 755 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 756 {
 757         s32 timeout = PHY_CFG_TIMEOUT;
 758
 759         while (timeout) {
 760                 if (er32(EEMNGCTL) &
 761                     E1000_NVM_CFG_DONE_PORT_0)
 762                         break;
 763                 msleep(1);
 764                 timeout--;
 765         }
 766         if (!timeout) {
 767                 e_dbg("MNG configuration cycle has not completed.\n");
 768                 return -E1000_ERR_RESET;
 769         }
 770
 771         return 0;
 772 }
 773
 774 /**
 775  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 776  *  @hw: pointer to the HW structure
 777  *  @active: true to enable LPLU, false to disable
 778  *
 779  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 780  *  this function also disables smart speed and vice versa.  LPLU will not be
 781  *  activated unless the device autonegotiation advertisement meets standards
 782  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 783  *  pointer entry point only called by PHY setup routines.
 784  **/
 785 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 786 {
 787         struct e1000_phy_info *phy = &hw->phy;
 788         s32 ret_val;
 789         u16 data;
 790
 791         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 792         if (ret_val)
 793                 return ret_val;
 794
 795         if (active) {
 796                 data |= IGP02E1000_PM_D0_LPLU;
 797                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 798                 if (ret_val)
 799                         return ret_val;
 800
 801                 /* When LPLU is enabled, we should disable SmartSpeed */
 802                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 803                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 804                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 805                 if (ret_val)
 806                         return ret_val;
 807         } else {
 808                 data &= ~IGP02E1000_PM_D0_LPLU;
 809                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 810                 /*
 811                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 812                  * during Dx states where the power conservation is most
 813                  * important.  During driver activity we should enable
 814                  * SmartSpeed, so performance is maintained.
 815                  */
 816                 if (phy->smart_speed == e1000_smart_speed_on) {
 817                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 818                                            &data);
 819                         if (ret_val)
 820                                 return ret_val;
 821
 822                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 823                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 824                                            data);
 825                         if (ret_val)
 826                                 return ret_val;
 827                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 828                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 829                                            &data);
 830                         if (ret_val)
 831                                 return ret_val;
 832
 833                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 834                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 835                                            data);
 836                         if (ret_val)
 837                                 return ret_val;
 838                 }
 839         }
 840
 841         return 0;
 842 }
 843
 844 /**
 845  *  e1000_reset_hw_82571 - Reset hardware
 846  *  @hw: pointer to the HW structure
 847  *
 848  *  This resets the hardware into a known state.
 849  **/
 850 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 851 {
 852         u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
 853         s32 ret_val;
 854         u16 i = 0;
 855
 856         /*
 857          * Prevent the PCI-E bus from sticking if there is no TLP connection
 858          * on the last TLP read/write transaction when MAC is reset.
 859          */
 860         ret_val = e1000e_disable_pcie_master(hw);
 861         if (ret_val)
 862                 e_dbg("PCI-E Master disable polling has failed.\n");
 863
 864         e_dbg("Masking off all interrupts\n");
 865         ew32(IMC, 0xffffffff);
 866
 867         ew32(RCTL, 0);
 868         ew32(TCTL, E1000_TCTL_PSP);
 869         e1e_flush();
 870
 871         msleep(10);
 872
 873         /*
 874          * Must acquire the MDIO ownership before MAC reset.
 875          * Ownership defaults to firmware after a reset.
 876          */
 877         switch (hw->mac.type) {
 878         case e1000_82573:
 879         case e1000_82574:
 880         case e1000_82583:
 881                 extcnf_ctrl = er32(EXTCNF_CTRL);
 882                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 883
 884                 do {
 885                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 886                         extcnf_ctrl = er32(EXTCNF_CTRL);
 887
 888                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 889                                 break;
 890
 891                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 892
 893                         msleep(2);
 894                         i++;
 895                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 896                 break;
 897         default:
 898                 break;
 899         }
 900
 901         ctrl = er32(CTRL);
 902
 903         e_dbg("Issuing a global reset to MAC\n");
 904         ew32(CTRL, ctrl | E1000_CTRL_RST);
 905
 906         if (hw->nvm.type == e1000_nvm_flash_hw) {
 907                 udelay(10);
 908                 ctrl_ext = er32(CTRL_EXT);
 909                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 910                 ew32(CTRL_EXT, ctrl_ext);
 911                 e1e_flush();
 912         }
 913
 914         ret_val = e1000e_get_auto_rd_done(hw);
 915         if (ret_val)
 916                 /* We don't want to continue accessing MAC registers. */
 917                 return ret_val;
 918
 919         /*
 920          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 921          * Need to wait for Phy configuration completion before accessing
 922          * NVM and Phy.
 923          */
 924
 925         switch (hw->mac.type) {
 926         case e1000_82573:
 927         case e1000_82574:
 928         case e1000_82583:
 929                 msleep(25);
 930                 break;
 931         default:
 932                 break;
 933         }
 934
 935         /* Clear any pending interrupt events. */
 936         ew32(IMC, 0xffffffff);
 937         icr = er32(ICR);
 938
 939         /* Install any alternate MAC address into RAR0 */
 940         ret_val = e1000_check_alt_mac_addr_generic(hw);
 941         if (ret_val)
 942                 return ret_val;
 943
 944         e1000e_set_laa_state_82571(hw, true);
 945
 946         /* Reinitialize the 82571 serdes link state machine */
 947         if (hw->phy.media_type == e1000_media_type_internal_serdes)
 948                 hw->mac.serdes_link_state = e1000_serdes_link_down;
 949
 950         return 0;
 951 }
 952
 953 /**
 954  *  e1000_init_hw_82571 - Initialize hardware
 955  *  @hw: pointer to the HW structure
 956  *
 957  *  This inits the hardware readying it for operation.
 958  **/
 959 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 960 {
 961         struct e1000_mac_info *mac = &hw->mac;
 962         u32 reg_data;
 963         s32 ret_val;
 964         u16 i, rar_count = mac->rar_entry_count;
 965
 966         e1000_initialize_hw_bits_82571(hw);
 967
 968         /* Initialize identification LED */
 969         ret_val = e1000e_id_led_init(hw);
 970         if (ret_val)
 971                 e_dbg("Error initializing identification LED\n");
 972                 /* This is not fatal and we should not stop init due to this */
 973
 974         /* Disabling VLAN filtering */
 975         e_dbg("Initializing the IEEE VLAN\n");
 976         mac->ops.clear_vfta(hw);
 977
 978         /* Setup the receive address. */
 979         /*
 980          * If, however, a locally administered address was assigned to the
 981          * 82571, we must reserve a RAR for it to work around an issue where
 982          * resetting one port will reload the MAC on the other port.
 983          */
 984         if (e1000e_get_laa_state_82571(hw))
 985                 rar_count--;
 986         e1000e_init_rx_addrs(hw, rar_count);
 987
 988         /* Zero out the Multicast HASH table */
 989         e_dbg("Zeroing the MTA\n");
 990         for (i = 0; i < mac->mta_reg_count; i++)
 991                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 992
 993         /* Setup link and flow control */
 994         ret_val = e1000_setup_link_82571(hw);
 995
 996         /* Set the transmit descriptor write-back policy */
 997         reg_data = er32(TXDCTL(0));
 998         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 999                    E1000_TXDCTL_FULL_TX_DESC_WB |
1000                    E1000_TXDCTL_COUNT_DESC;
1001         ew32(TXDCTL(0), reg_data);
1002
1003         /* ...for both queues. */
1004         switch (mac->type) {
1005         case e1000_82573:
1006                 e1000e_enable_tx_pkt_filtering(hw);
1007                 /* fall through */
1008         case e1000_82574:
1009         case e1000_82583:
1010                 reg_data = er32(GCR);
1011                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1012                 ew32(GCR, reg_data);
1013                 break;
1014         default:
1015                 reg_data = er32(TXDCTL(1));
1016                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1017                            E1000_TXDCTL_FULL_TX_DESC_WB |
1018                            E1000_TXDCTL_COUNT_DESC;
1019                 ew32(TXDCTL(1), reg_data);
1020                 break;
1021         }
1022
1023         /*
1024          * Clear all of the statistics registers (clear on read).  It is
1025          * important that we do this after we have tried to establish link
1026          * because the symbol error count will increment wildly if there
1027          * is no link.
1028          */
1029         e1000_clear_hw_cntrs_82571(hw);
1030
1031         return ret_val;
1032 }
1033
1034 /**
1035  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1036  *  @hw: pointer to the HW structure
1037  *
1038  *  Initializes required hardware-dependent bits needed for normal operation.
1039  **/
1040 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1041 {
1042         u32 reg;
1043
1044         /* Transmit Descriptor Control 0 */
1045         reg = er32(TXDCTL(0));
1046         reg |= (1 << 22);
1047         ew32(TXDCTL(0), reg);
1048
1049         /* Transmit Descriptor Control 1 */
1050         reg = er32(TXDCTL(1));
1051         reg |= (1 << 22);
1052         ew32(TXDCTL(1), reg);
1053
1054         /* Transmit Arbitration Control 0 */
1055         reg = er32(TARC(0));
1056         reg &= ~(0xF << 27); /* 30:27 */
1057         switch (hw->mac.type) {
1058         case e1000_82571:
1059         case e1000_82572:
1060                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1061                 break;
1062         default:
1063                 break;
1064         }
1065         ew32(TARC(0), reg);
1066
1067         /* Transmit Arbitration Control 1 */
1068         reg = er32(TARC(1));
1069         switch (hw->mac.type) {
1070         case e1000_82571:
1071         case e1000_82572:
1072                 reg &= ~((1 << 29) | (1 << 30));
1073                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1074                 if (er32(TCTL) & E1000_TCTL_MULR)
1075                         reg &= ~(1 << 28);
1076                 else
1077                         reg |= (1 << 28);
1078                 ew32(TARC(1), reg);
1079                 break;
1080         default:
1081                 break;
1082         }
1083
1084         /* Device Control */
1085         switch (hw->mac.type) {
1086         case e1000_82573:
1087         case e1000_82574:
1088         case e1000_82583:
1089                 reg = er32(CTRL);
1090                 reg &= ~(1 << 29);
1091                 ew32(CTRL, reg);
1092                 break;
1093         default:
1094                 break;
1095         }
1096
1097         /* Extended Device Control */
1098         switch (hw->mac.type) {
1099         case e1000_82573:
1100         case e1000_82574:
1101         case e1000_82583:
1102                 reg = er32(CTRL_EXT);
1103                 reg &= ~(1 << 23);
1104                 reg |= (1 << 22);
1105                 ew32(CTRL_EXT, reg);
1106                 break;
1107         default:
1108                 break;
1109         }
1110
1111         if (hw->mac.type == e1000_82571) {
1112                 reg = er32(PBA_ECC);
1113                 reg |= E1000_PBA_ECC_CORR_EN;
1114                 ew32(PBA_ECC, reg);
1115         }
1116         /*
1117          * Workaround for hardware errata.
1118          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1119          */
1120
1121         if ((hw->mac.type == e1000_82571) ||
1122            (hw->mac.type == e1000_82572)) {
1123                 reg = er32(CTRL_EXT);
1124                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1125                 ew32(CTRL_EXT, reg);
1126         }
1127
1128
1129         /* PCI-Ex Control Registers */
1130         switch (hw->mac.type) {
1131         case e1000_82574:
1132         case e1000_82583:
1133                 reg = er32(GCR);
1134                 reg |= (1 << 22);
1135                 ew32(GCR, reg);
1136
1137                 /*
1138                  * Workaround for hardware errata.
1139                  * apply workaround for hardware errata documented in errata
1140                  * docs Fixes issue where some error prone or unreliable PCIe
1141                  * completions are occurring, particularly with ASPM enabled.
1142                  * Without fix, issue can cause tx timeouts.
1143                  */
1144                 reg = er32(GCR2);
1145                 reg |= 1;
1146                 ew32(GCR2, reg);
1147                 break;
1148         default:
1149                 break;
1150         }
1151 }
1152
1153 /**
1154  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1155  *  @hw: pointer to the HW structure
1156  *
1157  *  Clears the register array which contains the VLAN filter table by
1158  *  setting all the values to 0.
1159  **/
1160 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1161 {
1162         u32 offset;
1163         u32 vfta_value = 0;
1164         u32 vfta_offset = 0;
1165         u32 vfta_bit_in_reg = 0;
1166
1167         switch (hw->mac.type) {
1168         case e1000_82573:
1169         case e1000_82574:
1170         case e1000_82583:
1171                 if (hw->mng_cookie.vlan_id != 0) {
1172                         /*
1173                          * The VFTA is a 4096b bit-field, each identifying
1174                          * a single VLAN ID.  The following operations
1175                          * determine which 32b entry (i.e. offset) into the
1176                          * array we want to set the VLAN ID (i.e. bit) of
1177                          * the manageability unit.
1178                          */
1179                         vfta_offset = (hw->mng_cookie.vlan_id >>
1180                                        E1000_VFTA_ENTRY_SHIFT) &
1181                                       E1000_VFTA_ENTRY_MASK;
1182                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1183                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1184                 }
1185                 break;
1186         default:
1187                 break;
1188         }
1189         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1190                 /*
1191                  * If the offset we want to clear is the same offset of the
1192                  * manageability VLAN ID, then clear all bits except that of
1193                  * the manageability unit.
1194                  */
1195                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1196                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1197                 e1e_flush();
1198         }
1199 }
1200
1201 /**
1202  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1203  *  @hw: pointer to the HW structure
1204  *
1205  *  Reads the NVM Initialization Control Word 2 and returns true
1206  *  (>0) if any manageability is enabled, else false (0).
1207  **/
1208 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1209 {
1210         u16 data;
1211
1212         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1213         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1214 }
1215
1216 /**
1217  *  e1000_led_on_82574 - Turn LED on
1218  *  @hw: pointer to the HW structure
1219  *
1220  *  Turn LED on.
1221  **/
1222 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1223 {
1224         u32 ctrl;
1225         u32 i;
1226
1227         ctrl = hw->mac.ledctl_mode2;
1228         if (!(E1000_STATUS_LU & er32(STATUS))) {
1229                 /*
1230                  * If no link, then turn LED on by setting the invert bit
1231                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1232                  */
1233                 for (i = 0; i < 4; i++)
1234                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1235                             E1000_LEDCTL_MODE_LED_ON)
1236                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1237         }
1238         ew32(LEDCTL, ctrl);
1239
1240         return 0;
1241 }
1242
1243 /**
1244  *  e1000_setup_link_82571 - Setup flow control and link settings
1245  *  @hw: pointer to the HW structure
1246  *
1247  *  Determines which flow control settings to use, then configures flow
1248  *  control.  Calls the appropriate media-specific link configuration
1249  *  function.  Assuming the adapter has a valid link partner, a valid link
1250  *  should be established.  Assumes the hardware has previously been reset
1251  *  and the transmitter and receiver are not enabled.
1252  **/
1253 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1254 {
1255         /*
1256          * 82573 does not have a word in the NVM to determine
1257          * the default flow control setting, so we explicitly
1258          * set it to full.
1259          */
1260         switch (hw->mac.type) {
1261         case e1000_82573:
1262         case e1000_82574:
1263         case e1000_82583:
1264                 if (hw->fc.requested_mode == e1000_fc_default)
1265                         hw->fc.requested_mode = e1000_fc_full;
1266                 break;
1267         default:
1268                 break;
1269         }
1270
1271         return e1000e_setup_link(hw);
1272 }
1273
1274 /**
1275  *  e1000_setup_copper_link_82571 - Configure copper link settings
1276  *  @hw: pointer to the HW structure
1277  *
1278  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1279  *  for link, once link is established calls to configure collision distance
1280  *  and flow control are called.
1281  **/
1282 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1283 {
1284         u32 ctrl;
1285         s32 ret_val;
1286
1287         ctrl = er32(CTRL);
1288         ctrl |= E1000_CTRL_SLU;
1289         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1290         ew32(CTRL, ctrl);
1291
1292         switch (hw->phy.type) {
1293         case e1000_phy_m88:
1294         case e1000_phy_bm:
1295                 ret_val = e1000e_copper_link_setup_m88(hw);
1296                 break;
1297         case e1000_phy_igp_2:
1298                 ret_val = e1000e_copper_link_setup_igp(hw);
1299                 break;
1300         default:
1301                 return -E1000_ERR_PHY;
1302                 break;
1303         }
1304
1305         if (ret_val)
1306                 return ret_val;
1307
1308         ret_val = e1000e_setup_copper_link(hw);
1309
1310         return ret_val;
1311 }
1312
1313 /**
1314  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1315  *  @hw: pointer to the HW structure
1316  *
1317  *  Configures collision distance and flow control for fiber and serdes links.
1318  *  Upon successful setup, poll for link.
1319  **/
1320 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1321 {
1322         switch (hw->mac.type) {
1323         case e1000_82571:
1324         case e1000_82572:
1325                 /*
1326                  * If SerDes loopback mode is entered, there is no form
1327                  * of reset to take the adapter out of that mode.  So we
1328                  * have to explicitly take the adapter out of loopback
1329                  * mode.  This prevents drivers from twiddling their thumbs
1330                  * if another tool failed to take it out of loopback mode.
1331                  */
1332                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1333                 break;
1334         default:
1335                 break;
1336         }
1337
1338         return e1000e_setup_fiber_serdes_link(hw);
1339 }
1340
1341 /**
1342  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1343  *  @hw: pointer to the HW structure
1344  *
1345  *  Reports the link state as up or down.
1346  *
1347  *  If autonegotiation is supported by the link partner, the link state is
1348  *  determined by the result of autonegotiation. This is the most likely case.
1349  *  If autonegotiation is not supported by the link partner, and the link
1350  *  has a valid signal, force the link up.
1351  *
1352  *  The link state is represented internally here by 4 states:
1353  *
1354  *  1) down
1355  *  2) autoneg_progress
1356  *  3) autoneg_complete (the link successfully autonegotiated)
1357  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1358  *
1359  **/
1360 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1361 {
1362         struct e1000_mac_info *mac = &hw->mac;
1363         u32 rxcw;
1364         u32 ctrl;
1365         u32 status;
1366         s32 ret_val = 0;
1367
1368         ctrl = er32(CTRL);
1369         status = er32(STATUS);
1370         rxcw = er32(RXCW);
1371
1372         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1373
1374                 /* Receiver is synchronized with no invalid bits.  */
1375                 switch (mac->serdes_link_state) {
1376                 case e1000_serdes_link_autoneg_complete:
1377                         if (!(status & E1000_STATUS_LU)) {
1378                                 /*
1379                                  * We have lost link, retry autoneg before
1380                                  * reporting link failure
1381                                  */
1382                                 mac->serdes_link_state =
1383                                     e1000_serdes_link_autoneg_progress;
1384                                 mac->serdes_has_link = false;
1385                                 e_dbg("AN_UP     -> AN_PROG\n");
1386                         }
1387                 break;
1388
1389                 case e1000_serdes_link_forced_up:
1390                         /*
1391                          * If we are receiving /C/ ordered sets, re-enable
1392                          * auto-negotiation in the TXCW register and disable
1393                          * forced link in the Device Control register in an
1394                          * attempt to auto-negotiate with our link partner.
1395                          */
1396                         if (rxcw & E1000_RXCW_C) {
1397                                 /* Enable autoneg, and unforce link up */
1398                                 ew32(TXCW, mac->txcw);
1399                                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1400                                 mac->serdes_link_state =
1401                                     e1000_serdes_link_autoneg_progress;
1402                                 mac->serdes_has_link = false;
1403                                 e_dbg("FORCED_UP -> AN_PROG\n");
1404                         }
1405                         break;
1406
1407                 case e1000_serdes_link_autoneg_progress:
1408                         if (rxcw & E1000_RXCW_C) {
1409                                 /*
1410                                  * We received /C/ ordered sets, meaning the
1411                                  * link partner has autonegotiated, and we can
1412                                  * trust the Link Up (LU) status bit.
1413                                  */
1414                                 if (status & E1000_STATUS_LU) {
1415                                         mac->serdes_link_state =
1416                                             e1000_serdes_link_autoneg_complete;
1417                                         e_dbg("AN_PROG   -> AN_UP\n");
1418                                         mac->serdes_has_link = true;
1419                                 } else {
1420                                         /* Autoneg completed, but failed. */
1421                                         mac->serdes_link_state =
1422                                             e1000_serdes_link_down;
1423                                         e_dbg("AN_PROG   -> DOWN\n");
1424                                 }
1425                         } else {
1426                                 /*
1427                                  * The link partner did not autoneg.
1428                                  * Force link up and full duplex, and change
1429                                  * state to forced.
1430                                  */
1431                                 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1432                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1433                                 ew32(CTRL, ctrl);
1434
1435                                 /* Configure Flow Control after link up. */
1436                                 ret_val = e1000e_config_fc_after_link_up(hw);
1437                                 if (ret_val) {
1438                                         e_dbg("Error config flow control\n");
1439                                         break;
1440                                 }
1441                                 mac->serdes_link_state =
1442                                     e1000_serdes_link_forced_up;
1443                                 mac->serdes_has_link = true;
1444                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1445                         }
1446                         break;
1447
1448                 case e1000_serdes_link_down:
1449                 default:
1450                         /*
1451                          * The link was down but the receiver has now gained
1452                          * valid sync, so lets see if we can bring the link
1453                          * up.
1454                          */
1455                         ew32(TXCW, mac->txcw);
1456                         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1457                         mac->serdes_link_state =
1458                             e1000_serdes_link_autoneg_progress;
1459                         e_dbg("DOWN      -> AN_PROG\n");
1460                         break;
1461                 }
1462         } else {
1463                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1464                         mac->serdes_has_link = false;
1465                         mac->serdes_link_state = e1000_serdes_link_down;
1466                         e_dbg("ANYSTATE  -> DOWN\n");
1467                 } else {
1468                         /*
1469                          * We have sync, and can tolerate one invalid (IV)
1470                          * codeword before declaring link down, so reread
1471                          * to look again.
1472                          */
1473                         udelay(10);
1474                         rxcw = er32(RXCW);
1475                         if (rxcw & E1000_RXCW_IV) {
1476                                 mac->serdes_link_state = e1000_serdes_link_down;
1477                                 mac->serdes_has_link = false;
1478                                 e_dbg("ANYSTATE  -> DOWN\n");
1479                         }
1480                 }
1481         }
1482
1483         return ret_val;
1484 }
1485
1486 /**
1487  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1488  *  @hw: pointer to the HW structure
1489  *  @data: pointer to the NVM (EEPROM)
1490  *
1491  *  Read the EEPROM for the current default LED configuration.  If the
1492  *  LED configuration is not valid, set to a valid LED configuration.
1493  **/
1494 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1495 {
1496         s32 ret_val;
1497
1498         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1499         if (ret_val) {
1500                 e_dbg("NVM Read Error\n");
1501                 return ret_val;
1502         }
1503
1504         switch (hw->mac.type) {
1505         case e1000_82573:
1506         case e1000_82574:
1507         case e1000_82583:
1508                 if (*data == ID_LED_RESERVED_F746)
1509                         *data = ID_LED_DEFAULT_82573;
1510                 break;
1511         default:
1512                 if (*data == ID_LED_RESERVED_0000 ||
1513                     *data == ID_LED_RESERVED_FFFF)
1514                         *data = ID_LED_DEFAULT;
1515                 break;
1516         }
1517
1518         return 0;
1519 }
1520
1521 /**
1522  *  e1000e_get_laa_state_82571 - Get locally administered address state
1523  *  @hw: pointer to the HW structure
1524  *
1525  *  Retrieve and return the current locally administered address state.
1526  **/
1527 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1528 {
1529         if (hw->mac.type != e1000_82571)
1530                 return false;
1531
1532         return hw->dev_spec.e82571.laa_is_present;
1533 }
1534
1535 /**
1536  *  e1000e_set_laa_state_82571 - Set locally administered address state
1537  *  @hw: pointer to the HW structure
1538  *  @state: enable/disable locally administered address
1539  *
1540  *  Enable/Disable the current locally administered address state.
1541  **/
1542 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1543 {
1544         if (hw->mac.type != e1000_82571)
1545                 return;
1546
1547         hw->dev_spec.e82571.laa_is_present = state;
1548
1549         /* If workaround is activated... */
1550         if (state)
1551                 /*
1552                  * Hold a copy of the LAA in RAR[14] This is done so that
1553                  * between the time RAR[0] gets clobbered and the time it
1554                  * gets fixed, the actual LAA is in one of the RARs and no
1555                  * incoming packets directed to this port are dropped.
1556                  * Eventually the LAA will be in RAR[0] and RAR[14].
1557                  */
1558                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1559 }
1560
1561 /**
1562  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1563  *  @hw: pointer to the HW structure
1564  *
1565  *  Verifies that the EEPROM has completed the update.  After updating the
1566  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1567  *  the checksum fix is not implemented, we need to set the bit and update
1568  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1569  *  we need to return bad checksum.
1570  **/
1571 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1572 {
1573         struct e1000_nvm_info *nvm = &hw->nvm;
1574         s32 ret_val;
1575         u16 data;
1576
1577         if (nvm->type != e1000_nvm_flash_hw)
1578                 return 0;
1579
1580         /*
1581          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1582          * 10h-12h.  Checksum may need to be fixed.
1583          */
1584         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1585         if (ret_val)
1586                 return ret_val;
1587
1588         if (!(data & 0x10)) {
1589                 /*
1590                  * Read 0x23 and check bit 15.  This bit is a 1
1591                  * when the checksum has already been fixed.  If
1592                  * the checksum is still wrong and this bit is a
1593                  * 1, we need to return bad checksum.  Otherwise,
1594                  * we need to set this bit to a 1 and update the
1595                  * checksum.
1596                  */
1597                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1598                 if (ret_val)
1599                         return ret_val;
1600
1601                 if (!(data & 0x8000)) {
1602                         data |= 0x8000;
1603                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1604                         if (ret_val)
1605                                 return ret_val;
1606                         ret_val = e1000e_update_nvm_checksum(hw);
1607                 }
1608         }
1609
1610         return 0;
1611 }
1612
1613 /**
1614  *  e1000_read_mac_addr_82571 - Read device MAC address
1615  *  @hw: pointer to the HW structure
1616  **/
1617 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1618 {
1619         s32 ret_val = 0;
1620
1621         /*
1622          * If there's an alternate MAC address place it in RAR0
1623          * so that it will override the Si installed default perm
1624          * address.
1625          */
1626         ret_val = e1000_check_alt_mac_addr_generic(hw);
1627         if (ret_val)
1628                 goto out;
1629
1630         ret_val = e1000_read_mac_addr_generic(hw);
1631
1632 out:
1633         return ret_val;
1634 }
1635
1636 /**
1637  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1638  * @hw: pointer to the HW structure
1639  *
1640  * In the case of a PHY power down to save power, or to turn off link during a
1641  * driver unload, or wake on lan is not enabled, remove the link.
1642  **/
1643 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1644 {
1645         struct e1000_phy_info *phy = &hw->phy;
1646         struct e1000_mac_info *mac = &hw->mac;
1647
1648         if (!(phy->ops.check_reset_block))
1649                 return;
1650
1651         /* If the management interface is not enabled, then power down */
1652         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1653                 e1000_power_down_phy_copper(hw);
1654 }
1655
1656 /**
1657  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1658  *  @hw: pointer to the HW structure
1659  *
1660  *  Clears the hardware counters by reading the counter registers.
1661  **/
1662 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1663 {
1664         e1000e_clear_hw_cntrs_base(hw);
1665
1666         er32(PRC64);
1667         er32(PRC127);
1668         er32(PRC255);
1669         er32(PRC511);
1670         er32(PRC1023);
1671         er32(PRC1522);
1672         er32(PTC64);
1673         er32(PTC127);
1674         er32(PTC255);
1675         er32(PTC511);
1676         er32(PTC1023);
1677         er32(PTC1522);
1678
1679         er32(ALGNERRC);
1680         er32(RXERRC);
1681         er32(TNCRS);
1682         er32(CEXTERR);
1683         er32(TSCTC);
1684         er32(TSCTFC);
1685
1686         er32(MGTPRC);
1687         er32(MGTPDC);
1688         er32(MGTPTC);
1689
1690         er32(IAC);
1691         er32(ICRXOC);
1692
1693         er32(ICRXPTC);
1694         er32(ICRXATC);
1695         er32(ICTXPTC);
1696         er32(ICTXATC);
1697         er32(ICTXQEC);
1698         er32(ICTXQMTC);
1699         er32(ICRXDMTC);
1700 }
1701
1702 static struct e1000_mac_operations e82571_mac_ops = {
1703         /* .check_mng_mode: mac type dependent */
1704         /* .check_for_link: media type dependent */
1705         .id_led_init            = e1000e_id_led_init,
1706         .cleanup_led            = e1000e_cleanup_led_generic,
1707         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1708         .get_bus_info           = e1000e_get_bus_info_pcie,
1709         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1710         /* .get_link_up_info: media type dependent */
1711         /* .led_on: mac type dependent */
1712         .led_off                = e1000e_led_off_generic,
1713         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1714         .write_vfta             = e1000_write_vfta_generic,
1715         .clear_vfta             = e1000_clear_vfta_82571,
1716         .reset_hw               = e1000_reset_hw_82571,
1717         .init_hw                = e1000_init_hw_82571,
1718         .setup_link             = e1000_setup_link_82571,
1719         /* .setup_physical_interface: media type dependent */
1720         .setup_led              = e1000e_setup_led_generic,
1721         .read_mac_addr          = e1000_read_mac_addr_82571,
1722 };
1723
1724 static struct e1000_phy_operations e82_phy_ops_igp = {
1725         .acquire                = e1000_get_hw_semaphore_82571,
1726         .check_polarity         = e1000_check_polarity_igp,
1727         .check_reset_block      = e1000e_check_reset_block_generic,
1728         .commit                 = NULL,
1729         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1730         .get_cfg_done           = e1000_get_cfg_done_82571,
1731         .get_cable_length       = e1000e_get_cable_length_igp_2,
1732         .get_info               = e1000e_get_phy_info_igp,
1733         .read_reg               = e1000e_read_phy_reg_igp,
1734         .release                = e1000_put_hw_semaphore_82571,
1735         .reset                  = e1000e_phy_hw_reset_generic,
1736         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1737         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1738         .write_reg              = e1000e_write_phy_reg_igp,
1739         .cfg_on_link_up         = NULL,
1740 };
1741
1742 static struct e1000_phy_operations e82_phy_ops_m88 = {
1743         .acquire                = e1000_get_hw_semaphore_82571,
1744         .check_polarity         = e1000_check_polarity_m88,
1745         .check_reset_block      = e1000e_check_reset_block_generic,
1746         .commit                 = e1000e_phy_sw_reset,
1747         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1748         .get_cfg_done           = e1000e_get_cfg_done,
1749         .get_cable_length       = e1000e_get_cable_length_m88,
1750         .get_info               = e1000e_get_phy_info_m88,
1751         .read_reg               = e1000e_read_phy_reg_m88,
1752         .release                = e1000_put_hw_semaphore_82571,
1753         .reset                  = e1000e_phy_hw_reset_generic,
1754         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1755         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1756         .write_reg              = e1000e_write_phy_reg_m88,
1757         .cfg_on_link_up         = NULL,
1758 };
1759
1760 static struct e1000_phy_operations e82_phy_ops_bm = {
1761         .acquire                = e1000_get_hw_semaphore_82571,
1762         .check_polarity         = e1000_check_polarity_m88,
1763         .check_reset_block      = e1000e_check_reset_block_generic,
1764         .commit                 = e1000e_phy_sw_reset,
1765         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1766         .get_cfg_done           = e1000e_get_cfg_done,
1767         .get_cable_length       = e1000e_get_cable_length_m88,
1768         .get_info               = e1000e_get_phy_info_m88,
1769         .read_reg               = e1000e_read_phy_reg_bm2,
1770         .release                = e1000_put_hw_semaphore_82571,
1771         .reset                  = e1000e_phy_hw_reset_generic,
1772         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1773         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1774         .write_reg              = e1000e_write_phy_reg_bm2,
1775         .cfg_on_link_up         = NULL,
1776 };
1777
1778 static struct e1000_nvm_operations e82571_nvm_ops = {
1779         .acquire                = e1000_acquire_nvm_82571,
1780         .read                   = e1000e_read_nvm_eerd,
1781         .release                = e1000_release_nvm_82571,
1782         .update                 = e1000_update_nvm_checksum_82571,
1783         .valid_led_default      = e1000_valid_led_default_82571,
1784         .validate               = e1000_validate_nvm_checksum_82571,
1785         .write                  = e1000_write_nvm_82571,
1786 };
1787
1788 struct e1000_info e1000_82571_info = {
1789         .mac                    = e1000_82571,
1790         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1791                                   | FLAG_HAS_JUMBO_FRAMES
1792                                   | FLAG_HAS_WOL
1793                                   | FLAG_APME_IN_CTRL3
1794                                   | FLAG_RX_CSUM_ENABLED
1795                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1796                                   | FLAG_HAS_SMART_POWER_DOWN
1797                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1798                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1799                                   | FLAG_APME_CHECK_PORT_B,
1800         .flags2                 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */
1801         .pba                    = 38,
1802         .max_hw_frame_size      = DEFAULT_JUMBO,
1803         .get_variants           = e1000_get_variants_82571,
1804         .mac_ops                = &e82571_mac_ops,
1805         .phy_ops                = &e82_phy_ops_igp,
1806         .nvm_ops                = &e82571_nvm_ops,
1807 };
1808
1809 struct e1000_info e1000_82572_info = {
1810         .mac                    = e1000_82572,
1811         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1812                                   | FLAG_HAS_JUMBO_FRAMES
1813                                   | FLAG_HAS_WOL
1814                                   | FLAG_APME_IN_CTRL3
1815                                   | FLAG_RX_CSUM_ENABLED
1816                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1817                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1818         .flags2                 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */
1819         .pba                    = 38,
1820         .max_hw_frame_size      = DEFAULT_JUMBO,
1821         .get_variants           = e1000_get_variants_82571,
1822         .mac_ops                = &e82571_mac_ops,
1823         .phy_ops                = &e82_phy_ops_igp,
1824         .nvm_ops                = &e82571_nvm_ops,
1825 };
1826
1827 struct e1000_info e1000_82573_info = {
1828         .mac                    = e1000_82573,
1829         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1830                                   | FLAG_HAS_WOL
1831                                   | FLAG_APME_IN_CTRL3
1832                                   | FLAG_RX_CSUM_ENABLED
1833                                   | FLAG_HAS_SMART_POWER_DOWN
1834                                   | FLAG_HAS_AMT
1835                                   | FLAG_HAS_SWSM_ON_LOAD,
1836         .pba                    = 20,
1837         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1838         .get_variants           = e1000_get_variants_82571,
1839         .mac_ops                = &e82571_mac_ops,
1840         .phy_ops                = &e82_phy_ops_m88,
1841         .nvm_ops                = &e82571_nvm_ops,
1842 };
1843
1844 struct e1000_info e1000_82574_info = {
1845         .mac                    = e1000_82574,
1846         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1847                                   | FLAG_HAS_MSIX
1848                                   | FLAG_HAS_JUMBO_FRAMES
1849                                   | FLAG_HAS_WOL
1850                                   | FLAG_APME_IN_CTRL3
1851                                   | FLAG_RX_CSUM_ENABLED
1852                                   | FLAG_HAS_SMART_POWER_DOWN
1853                                   | FLAG_HAS_AMT
1854                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1855         .pba                    = 36,
1856         .max_hw_frame_size      = DEFAULT_JUMBO,
1857         .get_variants           = e1000_get_variants_82571,
1858         .mac_ops                = &e82571_mac_ops,
1859         .phy_ops                = &e82_phy_ops_bm,
1860         .nvm_ops                = &e82571_nvm_ops,
1861 };
1862
1863 struct e1000_info e1000_82583_info = {
1864         .mac                    = e1000_82583,
1865         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1866                                   | FLAG_HAS_WOL
1867                                   | FLAG_APME_IN_CTRL3
1868                                   | FLAG_RX_CSUM_ENABLED
1869                                   | FLAG_HAS_SMART_POWER_DOWN
1870                                   | FLAG_HAS_AMT
1871                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1872         .pba                    = 36,
1873         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1874         .get_variants           = e1000_get_variants_82571,
1875         .mac_ops                = &e82571_mac_ops,
1876         .phy_ops                = &e82_phy_ops_bm,
1877         .nvm_ops                = &e82571_nvm_ops,
1878 };
1879