drivers/net/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82571EB Gigabit Ethernet Controller
  31  * 82571EB Gigabit Ethernet Controller (Copper)
  32  * 82571EB Gigabit Ethernet Controller (Fiber)
  33  * 82571EB Dual Port Gigabit Mezzanine Adapter
  34  * 82571EB Quad Port Gigabit Mezzanine Adapter
  35  * 82571PT Gigabit PT Quad Port Server ExpressModule
  36  * 82572EI Gigabit Ethernet Controller (Copper)
  37  * 82572EI Gigabit Ethernet Controller (Fiber)
  38  * 82572EI Gigabit Ethernet Controller
  39  * 82573V Gigabit Ethernet Controller (Copper)
  40  * 82573E Gigabit Ethernet Controller (Copper)
  41  * 82573L Gigabit Ethernet Controller
  42  * 82574L Gigabit Network Connection
  43  */
  44
  45 #include <linux/netdevice.h>
  46 #include <linux/delay.h>
  47 #include <linux/pci.h>
  48
  49 #include "e1000.h"
  50
  51 #define ID_LED_RESERVED_F746 0xF746
  52 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  53                               (ID_LED_OFF1_ON2  <<  8) | \
  54                               (ID_LED_DEF1_DEF2 <<  4) | \
  55                               (ID_LED_DEF1_DEF2))
  56
  57 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  58
  59 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
  60
  61 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  62 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  63 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  64 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  65 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  66                                       u16 words, u16 *data);
  67 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  68 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  69 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  70 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  71 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  72 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  73
  74 /**
  75  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  76  *  @hw: pointer to the HW structure
  77  *
  78  *  This is a function pointer entry point called by the api module.
  79  **/
  80 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  81 {
  82         struct e1000_phy_info *phy = &hw->phy;
  83         s32 ret_val;
  84
  85         if (hw->phy.media_type != e1000_media_type_copper) {
  86                 phy->type = e1000_phy_none;
  87                 return 0;
  88         }
  89
  90         phy->addr                        = 1;
  91         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  92         phy->reset_delay_us              = 100;
  93
  94         switch (hw->mac.type) {
  95         case e1000_82571:
  96         case e1000_82572:
  97                 phy->type                = e1000_phy_igp_2;
  98                 break;
  99         case e1000_82573:
 100                 phy->type                = e1000_phy_m88;
 101                 break;
 102         case e1000_82574:
 103                 phy->type                = e1000_phy_bm;
 104                 break;
 105         default:
 106                 return -E1000_ERR_PHY;
 107                 break;
 108         }
 109
 110         /* This can only be done after all function pointers are setup. */
 111         ret_val = e1000_get_phy_id_82571(hw);
 112
 113         /* Verify phy id */
 114         switch (hw->mac.type) {
 115         case e1000_82571:
 116         case e1000_82572:
 117                 if (phy->id != IGP01E1000_I_PHY_ID)
 118                         return -E1000_ERR_PHY;
 119                 break;
 120         case e1000_82573:
 121                 if (phy->id != M88E1111_I_PHY_ID)
 122                         return -E1000_ERR_PHY;
 123                 break;
 124         case e1000_82574:
 125                 if (phy->id != BME1000_E_PHY_ID_R2)
 126                         return -E1000_ERR_PHY;
 127                 break;
 128         default:
 129                 return -E1000_ERR_PHY;
 130                 break;
 131         }
 132
 133         return 0;
 134 }
 135
 136 /**
 137  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 138  *  @hw: pointer to the HW structure
 139  *
 140  *  This is a function pointer entry point called by the api module.
 141  **/
 142 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 143 {
 144         struct e1000_nvm_info *nvm = &hw->nvm;
 145         u32 eecd = er32(EECD);
 146         u16 size;
 147
 148         nvm->opcode_bits = 8;
 149         nvm->delay_usec = 1;
 150         switch (nvm->override) {
 151         case e1000_nvm_override_spi_large:
 152                 nvm->page_size = 32;
 153                 nvm->address_bits = 16;
 154                 break;
 155         case e1000_nvm_override_spi_small:
 156                 nvm->page_size = 8;
 157                 nvm->address_bits = 8;
 158                 break;
 159         default:
 160                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 161                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 162                 break;
 163         }
 164
 165         switch (hw->mac.type) {
 166         case e1000_82573:
 167         case e1000_82574:
 168                 if (((eecd >> 15) & 0x3) == 0x3) {
 169                         nvm->type = e1000_nvm_flash_hw;
 170                         nvm->word_size = 2048;
 171                         /*
 172                          * Autonomous Flash update bit must be cleared due
 173                          * to Flash update issue.
 174                          */
 175                         eecd &= ~E1000_EECD_AUPDEN;
 176                         ew32(EECD, eecd);
 177                         break;
 178                 }
 179                 /* Fall Through */
 180         default:
 181                 nvm->type = e1000_nvm_eeprom_spi;
 182                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 183                                   E1000_EECD_SIZE_EX_SHIFT);
 184                 /*
 185                  * Added to a constant, "size" becomes the left-shift value
 186                  * for setting word_size.
 187                  */
 188                 size += NVM_WORD_SIZE_BASE_SHIFT;
 189
 190                 /* EEPROM access above 16k is unsupported */
 191                 if (size > 14)
 192                         size = 14;
 193                 nvm->word_size  = 1 << size;
 194                 break;
 195         }
 196
 197         return 0;
 198 }
 199
 200 /**
 201  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 202  *  @hw: pointer to the HW structure
 203  *
 204  *  This is a function pointer entry point called by the api module.
 205  **/
 206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
 207 {
 208         struct e1000_hw *hw = &adapter->hw;
 209         struct e1000_mac_info *mac = &hw->mac;
 210         struct e1000_mac_operations *func = &mac->ops;
 211
 212         /* Set media type */
 213         switch (adapter->pdev->device) {
 214         case E1000_DEV_ID_82571EB_FIBER:
 215         case E1000_DEV_ID_82572EI_FIBER:
 216         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 217                 hw->phy.media_type = e1000_media_type_fiber;
 218                 break;
 219         case E1000_DEV_ID_82571EB_SERDES:
 220         case E1000_DEV_ID_82572EI_SERDES:
 221         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 222         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 223                 hw->phy.media_type = e1000_media_type_internal_serdes;
 224                 break;
 225         default:
 226                 hw->phy.media_type = e1000_media_type_copper;
 227                 break;
 228         }
 229
 230         /* Set mta register count */
 231         mac->mta_reg_count = 128;
 232         /* Set rar entry count */
 233         mac->rar_entry_count = E1000_RAR_ENTRIES;
 234         /* Set if manageability features are enabled. */
 235         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 236
 237         /* check for link */
 238         switch (hw->phy.media_type) {
 239         case e1000_media_type_copper:
 240                 func->setup_physical_interface = e1000_setup_copper_link_82571;
 241                 func->check_for_link = e1000e_check_for_copper_link;
 242                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
 243                 break;
 244         case e1000_media_type_fiber:
 245                 func->setup_physical_interface =
 246                         e1000_setup_fiber_serdes_link_82571;
 247                 func->check_for_link = e1000e_check_for_fiber_link;
 248                 func->get_link_up_info =
 249                         e1000e_get_speed_and_duplex_fiber_serdes;
 250                 break;
 251         case e1000_media_type_internal_serdes:
 252                 func->setup_physical_interface =
 253                         e1000_setup_fiber_serdes_link_82571;
 254                 func->check_for_link = e1000_check_for_serdes_link_82571;
 255                 func->get_link_up_info =
 256                         e1000e_get_speed_and_duplex_fiber_serdes;
 257                 break;
 258         default:
 259                 return -E1000_ERR_CONFIG;
 260                 break;
 261         }
 262
 263         switch (hw->mac.type) {
 264         case e1000_82574:
 265                 func->check_mng_mode = e1000_check_mng_mode_82574;
 266                 func->led_on = e1000_led_on_82574;
 267                 break;
 268         default:
 269                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 270                 func->led_on = e1000e_led_on_generic;
 271                 break;
 272         }
 273
 274         return 0;
 275 }
 276
 277 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 278 {
 279         struct e1000_hw *hw = &adapter->hw;
 280         static int global_quad_port_a; /* global port a indication */
 281         struct pci_dev *pdev = adapter->pdev;
 282         u16 eeprom_data = 0;
 283         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 284         s32 rc;
 285
 286         rc = e1000_init_mac_params_82571(adapter);
 287         if (rc)
 288                 return rc;
 289
 290         rc = e1000_init_nvm_params_82571(hw);
 291         if (rc)
 292                 return rc;
 293
 294         rc = e1000_init_phy_params_82571(hw);
 295         if (rc)
 296                 return rc;
 297
 298         /* tag quad port adapters first, it's used below */
 299         switch (pdev->device) {
 300         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 301         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 302         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 303         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 304                 adapter->flags |= FLAG_IS_QUAD_PORT;
 305                 /* mark the first port */
 306                 if (global_quad_port_a == 0)
 307                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 308                 /* Reset for multiple quad port adapters */
 309                 global_quad_port_a++;
 310                 if (global_quad_port_a == 4)
 311                         global_quad_port_a = 0;
 312                 break;
 313         default:
 314                 break;
 315         }
 316
 317         switch (adapter->hw.mac.type) {
 318         case e1000_82571:
 319                 /* these dual ports don't have WoL on port B at all */
 320                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 321                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 322                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 323                     (is_port_b))
 324                         adapter->flags &= ~FLAG_HAS_WOL;
 325                 /* quad ports only support WoL on port A */
 326                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 327                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 328                         adapter->flags &= ~FLAG_HAS_WOL;
 329                 /* Does not support WoL on any port */
 330                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 331                         adapter->flags &= ~FLAG_HAS_WOL;
 332                 break;
 333
 334         case e1000_82573:
 335                 if (pdev->device == E1000_DEV_ID_82573L) {
 336                         if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
 337                                        &eeprom_data) < 0)
 338                                 break;
 339                         if (eeprom_data & NVM_WORD1A_ASPM_MASK)
 340                                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 341                 }
 342                 break;
 343         default:
 344                 break;
 345         }
 346
 347         return 0;
 348 }
 349
 350 /**
 351  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 352  *  @hw: pointer to the HW structure
 353  *
 354  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 355  *  revision in the hardware structure.
 356  **/
 357 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 358 {
 359         struct e1000_phy_info *phy = &hw->phy;
 360         s32 ret_val;
 361         u16 phy_id = 0;
 362
 363         switch (hw->mac.type) {
 364         case e1000_82571:
 365         case e1000_82572:
 366                 /*
 367                  * The 82571 firmware may still be configuring the PHY.
 368                  * In this case, we cannot access the PHY until the
 369                  * configuration is done.  So we explicitly set the
 370                  * PHY ID.
 371                  */
 372                 phy->id = IGP01E1000_I_PHY_ID;
 373                 break;
 374         case e1000_82573:
 375                 return e1000e_get_phy_id(hw);
 376                 break;
 377         case e1000_82574:
 378                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
 379                 if (ret_val)
 380                         return ret_val;
 381
 382                 phy->id = (u32)(phy_id << 16);
 383                 udelay(20);
 384                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
 385                 if (ret_val)
 386                         return ret_val;
 387
 388                 phy->id |= (u32)(phy_id);
 389                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 390                 break;
 391         default:
 392                 return -E1000_ERR_PHY;
 393                 break;
 394         }
 395
 396         return 0;
 397 }
 398
 399 /**
 400  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 401  *  @hw: pointer to the HW structure
 402  *
 403  *  Acquire the HW semaphore to access the PHY or NVM
 404  **/
 405 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 406 {
 407         u32 swsm;
 408         s32 timeout = hw->nvm.word_size + 1;
 409         s32 i = 0;
 410
 411         /* Get the FW semaphore. */
 412         for (i = 0; i < timeout; i++) {
 413                 swsm = er32(SWSM);
 414                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 415
 416                 /* Semaphore acquired if bit latched */
 417                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 418                         break;
 419
 420                 udelay(50);
 421         }
 422
 423         if (i == timeout) {
 424                 /* Release semaphores */
 425                 e1000e_put_hw_semaphore(hw);
 426                 hw_dbg(hw, "Driver can't access the NVM\n");
 427                 return -E1000_ERR_NVM;
 428         }
 429
 430         return 0;
 431 }
 432
 433 /**
 434  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 435  *  @hw: pointer to the HW structure
 436  *
 437  *  Release hardware semaphore used to access the PHY or NVM
 438  **/
 439 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 440 {
 441         u32 swsm;
 442
 443         swsm = er32(SWSM);
 444
 445         swsm &= ~E1000_SWSM_SWESMBI;
 446
 447         ew32(SWSM, swsm);
 448 }
 449
 450 /**
 451  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 452  *  @hw: pointer to the HW structure
 453  *
 454  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 455  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 456  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 457  *  hardware semaphore.
 458  **/
 459 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 460 {
 461         s32 ret_val;
 462
 463         ret_val = e1000_get_hw_semaphore_82571(hw);
 464         if (ret_val)
 465                 return ret_val;
 466
 467         if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
 468                 ret_val = e1000e_acquire_nvm(hw);
 469
 470         if (ret_val)
 471                 e1000_put_hw_semaphore_82571(hw);
 472
 473         return ret_val;
 474 }
 475
 476 /**
 477  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 478  *  @hw: pointer to the HW structure
 479  *
 480  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 481  **/
 482 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 483 {
 484         e1000e_release_nvm(hw);
 485         e1000_put_hw_semaphore_82571(hw);
 486 }
 487
 488 /**
 489  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 490  *  @hw: pointer to the HW structure
 491  *  @offset: offset within the EEPROM to be written to
 492  *  @words: number of words to write
 493  *  @data: 16 bit word(s) to be written to the EEPROM
 494  *
 495  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 496  *
 497  *  If e1000e_update_nvm_checksum is not called after this function, the
 498  *  EEPROM will most likely contain an invalid checksum.
 499  **/
 500 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 501                                  u16 *data)
 502 {
 503         s32 ret_val;
 504
 505         switch (hw->mac.type) {
 506         case e1000_82573:
 507         case e1000_82574:
 508                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 509                 break;
 510         case e1000_82571:
 511         case e1000_82572:
 512                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 513                 break;
 514         default:
 515                 ret_val = -E1000_ERR_NVM;
 516                 break;
 517         }
 518
 519         return ret_val;
 520 }
 521
 522 /**
 523  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 527  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 528  *  value to the EEPROM.
 529  **/
 530 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 531 {
 532         u32 eecd;
 533         s32 ret_val;
 534         u16 i;
 535
 536         ret_val = e1000e_update_nvm_checksum_generic(hw);
 537         if (ret_val)
 538                 return ret_val;
 539
 540         /*
 541          * If our nvm is an EEPROM, then we're done
 542          * otherwise, commit the checksum to the flash NVM.
 543          */
 544         if (hw->nvm.type != e1000_nvm_flash_hw)
 545                 return ret_val;
 546
 547         /* Check for pending operations. */
 548         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 549                 msleep(1);
 550                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 551                         break;
 552         }
 553
 554         if (i == E1000_FLASH_UPDATES)
 555                 return -E1000_ERR_NVM;
 556
 557         /* Reset the firmware if using STM opcode. */
 558         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 559                 /*
 560                  * The enabling of and the actual reset must be done
 561                  * in two write cycles.
 562                  */
 563                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 564                 e1e_flush();
 565                 ew32(HICR, E1000_HICR_FW_RESET);
 566         }
 567
 568         /* Commit the write to flash */
 569         eecd = er32(EECD) | E1000_EECD_FLUPD;
 570         ew32(EECD, eecd);
 571
 572         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 573                 msleep(1);
 574                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 575                         break;
 576         }
 577
 578         if (i == E1000_FLASH_UPDATES)
 579                 return -E1000_ERR_NVM;
 580
 581         return 0;
 582 }
 583
 584 /**
 585  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 586  *  @hw: pointer to the HW structure
 587  *
 588  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 589  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 590  **/
 591 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 592 {
 593         if (hw->nvm.type == e1000_nvm_flash_hw)
 594                 e1000_fix_nvm_checksum_82571(hw);
 595
 596         return e1000e_validate_nvm_checksum_generic(hw);
 597 }
 598
 599 /**
 600  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 601  *  @hw: pointer to the HW structure
 602  *  @offset: offset within the EEPROM to be written to
 603  *  @words: number of words to write
 604  *  @data: 16 bit word(s) to be written to the EEPROM
 605  *
 606  *  After checking for invalid values, poll the EEPROM to ensure the previous
 607  *  command has completed before trying to write the next word.  After write
 608  *  poll for completion.
 609  *
 610  *  If e1000e_update_nvm_checksum is not called after this function, the
 611  *  EEPROM will most likely contain an invalid checksum.
 612  **/
 613 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 614                                       u16 words, u16 *data)
 615 {
 616         struct e1000_nvm_info *nvm = &hw->nvm;
 617         u32 i;
 618         u32 eewr = 0;
 619         s32 ret_val = 0;
 620
 621         /*
 622          * A check for invalid values:  offset too large, too many words,
 623          * and not enough words.
 624          */
 625         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 626             (words == 0)) {
 627                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
 628                 return -E1000_ERR_NVM;
 629         }
 630
 631         for (i = 0; i < words; i++) {
 632                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 633                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 634                        E1000_NVM_RW_REG_START;
 635
 636                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 637                 if (ret_val)
 638                         break;
 639
 640                 ew32(EEWR, eewr);
 641
 642                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 643                 if (ret_val)
 644                         break;
 645         }
 646
 647         return ret_val;
 648 }
 649
 650 /**
 651  *  e1000_get_cfg_done_82571 - Poll for configuration done
 652  *  @hw: pointer to the HW structure
 653  *
 654  *  Reads the management control register for the config done bit to be set.
 655  **/
 656 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 657 {
 658         s32 timeout = PHY_CFG_TIMEOUT;
 659
 660         while (timeout) {
 661                 if (er32(EEMNGCTL) &
 662                     E1000_NVM_CFG_DONE_PORT_0)
 663                         break;
 664                 msleep(1);
 665                 timeout--;
 666         }
 667         if (!timeout) {
 668                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 669                 return -E1000_ERR_RESET;
 670         }
 671
 672         return 0;
 673 }
 674
 675 /**
 676  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 677  *  @hw: pointer to the HW structure
 678  *  @active: TRUE to enable LPLU, FALSE to disable
 679  *
 680  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 681  *  this function also disables smart speed and vice versa.  LPLU will not be
 682  *  activated unless the device autonegotiation advertisement meets standards
 683  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 684  *  pointer entry point only called by PHY setup routines.
 685  **/
 686 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 687 {
 688         struct e1000_phy_info *phy = &hw->phy;
 689         s32 ret_val;
 690         u16 data;
 691
 692         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 693         if (ret_val)
 694                 return ret_val;
 695
 696         if (active) {
 697                 data |= IGP02E1000_PM_D0_LPLU;
 698                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 699                 if (ret_val)
 700                         return ret_val;
 701
 702                 /* When LPLU is enabled, we should disable SmartSpeed */
 703                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 704                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 705                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 706                 if (ret_val)
 707                         return ret_val;
 708         } else {
 709                 data &= ~IGP02E1000_PM_D0_LPLU;
 710                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 711                 /*
 712                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 713                  * during Dx states where the power conservation is most
 714                  * important.  During driver activity we should enable
 715                  * SmartSpeed, so performance is maintained.
 716                  */
 717                 if (phy->smart_speed == e1000_smart_speed_on) {
 718                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 719                                            &data);
 720                         if (ret_val)
 721                                 return ret_val;
 722
 723                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 724                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 725                                            data);
 726                         if (ret_val)
 727                                 return ret_val;
 728                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 729                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 730                                            &data);
 731                         if (ret_val)
 732                                 return ret_val;
 733
 734                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 735                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 736                                            data);
 737                         if (ret_val)
 738                                 return ret_val;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 /**
 746  *  e1000_reset_hw_82571 - Reset hardware
 747  *  @hw: pointer to the HW structure
 748  *
 749  *  This resets the hardware into a known state.  This is a
 750  *  function pointer entry point called by the api module.
 751  **/
 752 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 753 {
 754         u32 ctrl;
 755         u32 extcnf_ctrl;
 756         u32 ctrl_ext;
 757         u32 icr;
 758         s32 ret_val;
 759         u16 i = 0;
 760
 761         /*
 762          * Prevent the PCI-E bus from sticking if there is no TLP connection
 763          * on the last TLP read/write transaction when MAC is reset.
 764          */
 765         ret_val = e1000e_disable_pcie_master(hw);
 766         if (ret_val)
 767                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 768
 769         hw_dbg(hw, "Masking off all interrupts\n");
 770         ew32(IMC, 0xffffffff);
 771
 772         ew32(RCTL, 0);
 773         ew32(TCTL, E1000_TCTL_PSP);
 774         e1e_flush();
 775
 776         msleep(10);
 777
 778         /*
 779          * Must acquire the MDIO ownership before MAC reset.
 780          * Ownership defaults to firmware after a reset.
 781          */
 782         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
 783                 extcnf_ctrl = er32(EXTCNF_CTRL);
 784                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 785
 786                 do {
 787                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 788                         extcnf_ctrl = er32(EXTCNF_CTRL);
 789
 790                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 791                                 break;
 792
 793                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 794
 795                         msleep(2);
 796                         i++;
 797                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 798         }
 799
 800         ctrl = er32(CTRL);
 801
 802         hw_dbg(hw, "Issuing a global reset to MAC\n");
 803         ew32(CTRL, ctrl | E1000_CTRL_RST);
 804
 805         if (hw->nvm.type == e1000_nvm_flash_hw) {
 806                 udelay(10);
 807                 ctrl_ext = er32(CTRL_EXT);
 808                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 809                 ew32(CTRL_EXT, ctrl_ext);
 810                 e1e_flush();
 811         }
 812
 813         ret_val = e1000e_get_auto_rd_done(hw);
 814         if (ret_val)
 815                 /* We don't want to continue accessing MAC registers. */
 816                 return ret_val;
 817
 818         /*
 819          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 820          * Need to wait for Phy configuration completion before accessing
 821          * NVM and Phy.
 822          */
 823         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
 824                 msleep(25);
 825
 826         /* Clear any pending interrupt events. */
 827         ew32(IMC, 0xffffffff);
 828         icr = er32(ICR);
 829
 830         if (hw->mac.type == e1000_82571 &&
 831                 hw->dev_spec.e82571.alt_mac_addr_is_present)
 832                         e1000e_set_laa_state_82571(hw, true);
 833
 834         /* Reinitialize the 82571 serdes link state machine */
 835         if (hw->phy.media_type == e1000_media_type_internal_serdes)
 836                 hw->mac.serdes_link_state = e1000_serdes_link_down;
 837
 838         return 0;
 839 }
 840
 841 /**
 842  *  e1000_init_hw_82571 - Initialize hardware
 843  *  @hw: pointer to the HW structure
 844  *
 845  *  This inits the hardware readying it for operation.
 846  **/
 847 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 848 {
 849         struct e1000_mac_info *mac = &hw->mac;
 850         u32 reg_data;
 851         s32 ret_val;
 852         u16 i;
 853         u16 rar_count = mac->rar_entry_count;
 854
 855         e1000_initialize_hw_bits_82571(hw);
 856
 857         /* Initialize identification LED */
 858         ret_val = e1000e_id_led_init(hw);
 859         if (ret_val) {
 860                 hw_dbg(hw, "Error initializing identification LED\n");
 861                 return ret_val;
 862         }
 863
 864         /* Disabling VLAN filtering */
 865         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 866         e1000e_clear_vfta(hw);
 867
 868         /* Setup the receive address. */
 869         /*
 870          * If, however, a locally administered address was assigned to the
 871          * 82571, we must reserve a RAR for it to work around an issue where
 872          * resetting one port will reload the MAC on the other port.
 873          */
 874         if (e1000e_get_laa_state_82571(hw))
 875                 rar_count--;
 876         e1000e_init_rx_addrs(hw, rar_count);
 877
 878         /* Zero out the Multicast HASH table */
 879         hw_dbg(hw, "Zeroing the MTA\n");
 880         for (i = 0; i < mac->mta_reg_count; i++)
 881                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 882
 883         /* Setup link and flow control */
 884         ret_val = e1000_setup_link_82571(hw);
 885
 886         /* Set the transmit descriptor write-back policy */
 887         reg_data = er32(TXDCTL(0));
 888         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 889                    E1000_TXDCTL_FULL_TX_DESC_WB |
 890                    E1000_TXDCTL_COUNT_DESC;
 891         ew32(TXDCTL(0), reg_data);
 892
 893         /* ...for both queues. */
 894         if (mac->type != e1000_82573 && mac->type != e1000_82574) {
 895                 reg_data = er32(TXDCTL(1));
 896                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 897                            E1000_TXDCTL_FULL_TX_DESC_WB |
 898                            E1000_TXDCTL_COUNT_DESC;
 899                 ew32(TXDCTL(1), reg_data);
 900         } else {
 901                 e1000e_enable_tx_pkt_filtering(hw);
 902                 reg_data = er32(GCR);
 903                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
 904                 ew32(GCR, reg_data);
 905         }
 906
 907         /*
 908          * Clear all of the statistics registers (clear on read).  It is
 909          * important that we do this after we have tried to establish link
 910          * because the symbol error count will increment wildly if there
 911          * is no link.
 912          */
 913         e1000_clear_hw_cntrs_82571(hw);
 914
 915         return ret_val;
 916 }
 917
 918 /**
 919  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
 920  *  @hw: pointer to the HW structure
 921  *
 922  *  Initializes required hardware-dependent bits needed for normal operation.
 923  **/
 924 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
 925 {
 926         u32 reg;
 927
 928         /* Transmit Descriptor Control 0 */
 929         reg = er32(TXDCTL(0));
 930         reg |= (1 << 22);
 931         ew32(TXDCTL(0), reg);
 932
 933         /* Transmit Descriptor Control 1 */
 934         reg = er32(TXDCTL(1));
 935         reg |= (1 << 22);
 936         ew32(TXDCTL(1), reg);
 937
 938         /* Transmit Arbitration Control 0 */
 939         reg = er32(TARC(0));
 940         reg &= ~(0xF << 27); /* 30:27 */
 941         switch (hw->mac.type) {
 942         case e1000_82571:
 943         case e1000_82572:
 944                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
 945                 break;
 946         default:
 947                 break;
 948         }
 949         ew32(TARC(0), reg);
 950
 951         /* Transmit Arbitration Control 1 */
 952         reg = er32(TARC(1));
 953         switch (hw->mac.type) {
 954         case e1000_82571:
 955         case e1000_82572:
 956                 reg &= ~((1 << 29) | (1 << 30));
 957                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
 958                 if (er32(TCTL) & E1000_TCTL_MULR)
 959                         reg &= ~(1 << 28);
 960                 else
 961                         reg |= (1 << 28);
 962                 ew32(TARC(1), reg);
 963                 break;
 964         default:
 965                 break;
 966         }
 967
 968         /* Device Control */
 969         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
 970                 reg = er32(CTRL);
 971                 reg &= ~(1 << 29);
 972                 ew32(CTRL, reg);
 973         }
 974
 975         /* Extended Device Control */
 976         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
 977                 reg = er32(CTRL_EXT);
 978                 reg &= ~(1 << 23);
 979                 reg |= (1 << 22);
 980                 ew32(CTRL_EXT, reg);
 981         }
 982
 983         if (hw->mac.type == e1000_82571) {
 984                 reg = er32(PBA_ECC);
 985                 reg |= E1000_PBA_ECC_CORR_EN;
 986                 ew32(PBA_ECC, reg);
 987         }
 988         /*
 989          * Workaround for hardware errata.
 990          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
 991          */
 992
 993         if ((hw->mac.type == e1000_82571) ||
 994            (hw->mac.type == e1000_82572)) {
 995                 reg = er32(CTRL_EXT);
 996                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
 997                 ew32(CTRL_EXT, reg);
 998         }
 999
1000
1001         /* PCI-Ex Control Registers */
1002         if (hw->mac.type == e1000_82574) {
1003                 reg = er32(GCR);
1004                 reg |= (1 << 22);
1005                 ew32(GCR, reg);
1006
1007                 reg = er32(GCR2);
1008                 reg |= 1;
1009                 ew32(GCR2, reg);
1010         }
1011
1012         return;
1013 }
1014
1015 /**
1016  *  e1000e_clear_vfta - Clear VLAN filter table
1017  *  @hw: pointer to the HW structure
1018  *
1019  *  Clears the register array which contains the VLAN filter table by
1020  *  setting all the values to 0.
1021  **/
1022 void e1000e_clear_vfta(struct e1000_hw *hw)
1023 {
1024         u32 offset;
1025         u32 vfta_value = 0;
1026         u32 vfta_offset = 0;
1027         u32 vfta_bit_in_reg = 0;
1028
1029         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1030                 if (hw->mng_cookie.vlan_id != 0) {
1031                         /*
1032                          * The VFTA is a 4096b bit-field, each identifying
1033                          * a single VLAN ID.  The following operations
1034                          * determine which 32b entry (i.e. offset) into the
1035                          * array we want to set the VLAN ID (i.e. bit) of
1036                          * the manageability unit.
1037                          */
1038                         vfta_offset = (hw->mng_cookie.vlan_id >>
1039                                        E1000_VFTA_ENTRY_SHIFT) &
1040                                       E1000_VFTA_ENTRY_MASK;
1041                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1042                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1043                 }
1044         }
1045         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1046                 /*
1047                  * If the offset we want to clear is the same offset of the
1048                  * manageability VLAN ID, then clear all bits except that of
1049                  * the manageability unit.
1050                  */
1051                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1052                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1053                 e1e_flush();
1054         }
1055 }
1056
1057 /**
1058  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1059  *  @hw: pointer to the HW structure
1060  *
1061  *  Reads the NVM Initialization Control Word 2 and returns true
1062  *  (>0) if any manageability is enabled, else false (0).
1063  **/
1064 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1065 {
1066         u16 data;
1067
1068         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1069         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1070 }
1071
1072 /**
1073  *  e1000_led_on_82574 - Turn LED on
1074  *  @hw: pointer to the HW structure
1075  *
1076  *  Turn LED on.
1077  **/
1078 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1079 {
1080         u32 ctrl;
1081         u32 i;
1082
1083         ctrl = hw->mac.ledctl_mode2;
1084         if (!(E1000_STATUS_LU & er32(STATUS))) {
1085                 /*
1086                  * If no link, then turn LED on by setting the invert bit
1087                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1088                  */
1089                 for (i = 0; i < 4; i++)
1090                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1091                             E1000_LEDCTL_MODE_LED_ON)
1092                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1093         }
1094         ew32(LEDCTL, ctrl);
1095
1096         return 0;
1097 }
1098
1099 /**
1100  *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
1101  *  @hw: pointer to the HW structure
1102  *  @mc_addr_list: array of multicast addresses to program
1103  *  @mc_addr_count: number of multicast addresses to program
1104  *  @rar_used_count: the first RAR register free to program
1105  *  @rar_count: total number of supported Receive Address Registers
1106  *
1107  *  Updates the Receive Address Registers and Multicast Table Array.
1108  *  The caller must have a packed mc_addr_list of multicast addresses.
1109  *  The parameter rar_count will usually be hw->mac.rar_entry_count
1110  *  unless there are workarounds that change this.
1111  **/
1112 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1113                                             u8 *mc_addr_list,
1114                                             u32 mc_addr_count,
1115                                             u32 rar_used_count,
1116                                             u32 rar_count)
1117 {
1118         if (e1000e_get_laa_state_82571(hw))
1119                 rar_count--;
1120
1121         e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1122                                            rar_used_count, rar_count);
1123 }
1124
1125 /**
1126  *  e1000_setup_link_82571 - Setup flow control and link settings
1127  *  @hw: pointer to the HW structure
1128  *
1129  *  Determines which flow control settings to use, then configures flow
1130  *  control.  Calls the appropriate media-specific link configuration
1131  *  function.  Assuming the adapter has a valid link partner, a valid link
1132  *  should be established.  Assumes the hardware has previously been reset
1133  *  and the transmitter and receiver are not enabled.
1134  **/
1135 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1136 {
1137         /*
1138          * 82573 does not have a word in the NVM to determine
1139          * the default flow control setting, so we explicitly
1140          * set it to full.
1141          */
1142         if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1143             hw->fc.requested_mode == e1000_fc_default)
1144                 hw->fc.requested_mode = e1000_fc_full;
1145
1146         return e1000e_setup_link(hw);
1147 }
1148
1149 /**
1150  *  e1000_setup_copper_link_82571 - Configure copper link settings
1151  *  @hw: pointer to the HW structure
1152  *
1153  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1154  *  for link, once link is established calls to configure collision distance
1155  *  and flow control are called.
1156  **/
1157 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1158 {
1159         u32 ctrl;
1160         u32 led_ctrl;
1161         s32 ret_val;
1162
1163         ctrl = er32(CTRL);
1164         ctrl |= E1000_CTRL_SLU;
1165         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1166         ew32(CTRL, ctrl);
1167
1168         switch (hw->phy.type) {
1169         case e1000_phy_m88:
1170         case e1000_phy_bm:
1171                 ret_val = e1000e_copper_link_setup_m88(hw);
1172                 break;
1173         case e1000_phy_igp_2:
1174                 ret_val = e1000e_copper_link_setup_igp(hw);
1175                 /* Setup activity LED */
1176                 led_ctrl = er32(LEDCTL);
1177                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1178                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1179                 ew32(LEDCTL, led_ctrl);
1180                 break;
1181         default:
1182                 return -E1000_ERR_PHY;
1183                 break;
1184         }
1185
1186         if (ret_val)
1187                 return ret_val;
1188
1189         ret_val = e1000e_setup_copper_link(hw);
1190
1191         return ret_val;
1192 }
1193
1194 /**
1195  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1196  *  @hw: pointer to the HW structure
1197  *
1198  *  Configures collision distance and flow control for fiber and serdes links.
1199  *  Upon successful setup, poll for link.
1200  **/
1201 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1202 {
1203         switch (hw->mac.type) {
1204         case e1000_82571:
1205         case e1000_82572:
1206                 /*
1207                  * If SerDes loopback mode is entered, there is no form
1208                  * of reset to take the adapter out of that mode.  So we
1209                  * have to explicitly take the adapter out of loopback
1210                  * mode.  This prevents drivers from twiddling their thumbs
1211                  * if another tool failed to take it out of loopback mode.
1212                  */
1213                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1214                 break;
1215         default:
1216                 break;
1217         }
1218
1219         return e1000e_setup_fiber_serdes_link(hw);
1220 }
1221
1222 /**
1223  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1224  *  @hw: pointer to the HW structure
1225  *
1226  *  Checks for link up on the hardware.  If link is not up and we have
1227  *  a signal, then we need to force link up.
1228  **/
1229 s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1230 {
1231         struct e1000_mac_info *mac = &hw->mac;
1232         u32 rxcw;
1233         u32 ctrl;
1234         u32 status;
1235         s32 ret_val = 0;
1236
1237         ctrl = er32(CTRL);
1238         status = er32(STATUS);
1239         rxcw = er32(RXCW);
1240
1241         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1242
1243                 /* Receiver is synchronized with no invalid bits.  */
1244                 switch (mac->serdes_link_state) {
1245                 case e1000_serdes_link_autoneg_complete:
1246                         if (!(status & E1000_STATUS_LU)) {
1247                                 /*
1248                                  * We have lost link, retry autoneg before
1249                                  * reporting link failure
1250                                  */
1251                                 mac->serdes_link_state =
1252                                     e1000_serdes_link_autoneg_progress;
1253                                 hw_dbg(hw, "AN_UP     -> AN_PROG\n");
1254                         }
1255                 break;
1256
1257                 case e1000_serdes_link_forced_up:
1258                         /*
1259                          * If we are receiving /C/ ordered sets, re-enable
1260                          * auto-negotiation in the TXCW register and disable
1261                          * forced link in the Device Control register in an
1262                          * attempt to auto-negotiate with our link partner.
1263                          */
1264                         if (rxcw & E1000_RXCW_C) {
1265                                 /* Enable autoneg, and unforce link up */
1266                                 ew32(TXCW, mac->txcw);
1267                                 ew32(CTRL,
1268                                     (ctrl & ~E1000_CTRL_SLU));
1269                                 mac->serdes_link_state =
1270                                     e1000_serdes_link_autoneg_progress;
1271                                 hw_dbg(hw, "FORCED_UP -> AN_PROG\n");
1272                         }
1273                         break;
1274
1275                 case e1000_serdes_link_autoneg_progress:
1276                         /*
1277                          * If the LU bit is set in the STATUS register,
1278                          * autoneg has completed sucessfully. If not,
1279                          * try foring the link because the far end may be
1280                          * available but not capable of autonegotiation.
1281                          */
1282                         if (status & E1000_STATUS_LU)  {
1283                                 mac->serdes_link_state =
1284                                     e1000_serdes_link_autoneg_complete;
1285                                 hw_dbg(hw, "AN_PROG   -> AN_UP\n");
1286                         } else {
1287                                 /*
1288                                  * Disable autoneg, force link up and
1289                                  * full duplex, and change state to forced
1290                                  */
1291                                 ew32(TXCW,
1292                                     (mac->txcw & ~E1000_TXCW_ANE));
1293                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1294                                 ew32(CTRL, ctrl);
1295
1296                                 /* Configure Flow Control after link up. */
1297                                 ret_val =
1298                                     e1000e_config_fc_after_link_up(hw);
1299                                 if (ret_val) {
1300                                         hw_dbg(hw, "Error config flow control\n");
1301                                         break;
1302                                 }
1303                                 mac->serdes_link_state =
1304                                     e1000_serdes_link_forced_up;
1305                                 hw_dbg(hw, "AN_PROG   -> FORCED_UP\n");
1306                         }
1307                         mac->serdes_has_link = true;
1308                         break;
1309
1310                 case e1000_serdes_link_down:
1311                 default:
1312                         /* The link was down but the receiver has now gained
1313                          * valid sync, so lets see if we can bring the link
1314                          * up. */
1315                         ew32(TXCW, mac->txcw);
1316                         ew32(CTRL,
1317                             (ctrl & ~E1000_CTRL_SLU));
1318                         mac->serdes_link_state =
1319                             e1000_serdes_link_autoneg_progress;
1320                         hw_dbg(hw, "DOWN      -> AN_PROG\n");
1321                         break;
1322                 }
1323         } else {
1324                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1325                         mac->serdes_has_link = false;
1326                         mac->serdes_link_state = e1000_serdes_link_down;
1327                         hw_dbg(hw, "ANYSTATE  -> DOWN\n");
1328                 } else {
1329                         /*
1330                          * We have sync, and can tolerate one
1331                          * invalid (IV) codeword before declaring
1332                          * link down, so reread to look again
1333                          */
1334                         udelay(10);
1335                         rxcw = er32(RXCW);
1336                         if (rxcw & E1000_RXCW_IV) {
1337                                 mac->serdes_link_state = e1000_serdes_link_down;
1338                                 mac->serdes_has_link = false;
1339                                 hw_dbg(hw, "ANYSTATE  -> DOWN\n");
1340                         }
1341                 }
1342         }
1343
1344         return ret_val;
1345 }
1346
1347 /**
1348  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1349  *  @hw: pointer to the HW structure
1350  *  @data: pointer to the NVM (EEPROM)
1351  *
1352  *  Read the EEPROM for the current default LED configuration.  If the
1353  *  LED configuration is not valid, set to a valid LED configuration.
1354  **/
1355 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1356 {
1357         s32 ret_val;
1358
1359         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1360         if (ret_val) {
1361                 hw_dbg(hw, "NVM Read Error\n");
1362                 return ret_val;
1363         }
1364
1365         if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1366             *data == ID_LED_RESERVED_F746)
1367                 *data = ID_LED_DEFAULT_82573;
1368         else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1369                 *data = ID_LED_DEFAULT;
1370
1371         return 0;
1372 }
1373
1374 /**
1375  *  e1000e_get_laa_state_82571 - Get locally administered address state
1376  *  @hw: pointer to the HW structure
1377  *
1378  *  Retrieve and return the current locally administered address state.
1379  **/
1380 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1381 {
1382         if (hw->mac.type != e1000_82571)
1383                 return 0;
1384
1385         return hw->dev_spec.e82571.laa_is_present;
1386 }
1387
1388 /**
1389  *  e1000e_set_laa_state_82571 - Set locally administered address state
1390  *  @hw: pointer to the HW structure
1391  *  @state: enable/disable locally administered address
1392  *
1393  *  Enable/Disable the current locally administers address state.
1394  **/
1395 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1396 {
1397         if (hw->mac.type != e1000_82571)
1398                 return;
1399
1400         hw->dev_spec.e82571.laa_is_present = state;
1401
1402         /* If workaround is activated... */
1403         if (state)
1404                 /*
1405                  * Hold a copy of the LAA in RAR[14] This is done so that
1406                  * between the time RAR[0] gets clobbered and the time it
1407                  * gets fixed, the actual LAA is in one of the RARs and no
1408                  * incoming packets directed to this port are dropped.
1409                  * Eventually the LAA will be in RAR[0] and RAR[14].
1410                  */
1411                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1412 }
1413
1414 /**
1415  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1416  *  @hw: pointer to the HW structure
1417  *
1418  *  Verifies that the EEPROM has completed the update.  After updating the
1419  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1420  *  the checksum fix is not implemented, we need to set the bit and update
1421  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1422  *  we need to return bad checksum.
1423  **/
1424 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1425 {
1426         struct e1000_nvm_info *nvm = &hw->nvm;
1427         s32 ret_val;
1428         u16 data;
1429
1430         if (nvm->type != e1000_nvm_flash_hw)
1431                 return 0;
1432
1433         /*
1434          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1435          * 10h-12h.  Checksum may need to be fixed.
1436          */
1437         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1438         if (ret_val)
1439                 return ret_val;
1440
1441         if (!(data & 0x10)) {
1442                 /*
1443                  * Read 0x23 and check bit 15.  This bit is a 1
1444                  * when the checksum has already been fixed.  If
1445                  * the checksum is still wrong and this bit is a
1446                  * 1, we need to return bad checksum.  Otherwise,
1447                  * we need to set this bit to a 1 and update the
1448                  * checksum.
1449                  */
1450                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1451                 if (ret_val)
1452                         return ret_val;
1453
1454                 if (!(data & 0x8000)) {
1455                         data |= 0x8000;
1456                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1457                         if (ret_val)
1458                                 return ret_val;
1459                         ret_val = e1000e_update_nvm_checksum(hw);
1460                 }
1461         }
1462
1463         return 0;
1464 }
1465
1466 /**
1467  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1468  *  @hw: pointer to the HW structure
1469  *
1470  *  Clears the hardware counters by reading the counter registers.
1471  **/
1472 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1473 {
1474         u32 temp;
1475
1476         e1000e_clear_hw_cntrs_base(hw);
1477
1478         temp = er32(PRC64);
1479         temp = er32(PRC127);
1480         temp = er32(PRC255);
1481         temp = er32(PRC511);
1482         temp = er32(PRC1023);
1483         temp = er32(PRC1522);
1484         temp = er32(PTC64);
1485         temp = er32(PTC127);
1486         temp = er32(PTC255);
1487         temp = er32(PTC511);
1488         temp = er32(PTC1023);
1489         temp = er32(PTC1522);
1490
1491         temp = er32(ALGNERRC);
1492         temp = er32(RXERRC);
1493         temp = er32(TNCRS);
1494         temp = er32(CEXTERR);
1495         temp = er32(TSCTC);
1496         temp = er32(TSCTFC);
1497
1498         temp = er32(MGTPRC);
1499         temp = er32(MGTPDC);
1500         temp = er32(MGTPTC);
1501
1502         temp = er32(IAC);
1503         temp = er32(ICRXOC);
1504
1505         temp = er32(ICRXPTC);
1506         temp = er32(ICRXATC);
1507         temp = er32(ICTXPTC);
1508         temp = er32(ICTXATC);
1509         temp = er32(ICTXQEC);
1510         temp = er32(ICTXQMTC);
1511         temp = er32(ICRXDMTC);
1512 }
1513
1514 static struct e1000_mac_operations e82571_mac_ops = {
1515         /* .check_mng_mode: mac type dependent */
1516         /* .check_for_link: media type dependent */
1517         .cleanup_led            = e1000e_cleanup_led_generic,
1518         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1519         .get_bus_info           = e1000e_get_bus_info_pcie,
1520         /* .get_link_up_info: media type dependent */
1521         /* .led_on: mac type dependent */
1522         .led_off                = e1000e_led_off_generic,
1523         .update_mc_addr_list    = e1000_update_mc_addr_list_82571,
1524         .reset_hw               = e1000_reset_hw_82571,
1525         .init_hw                = e1000_init_hw_82571,
1526         .setup_link             = e1000_setup_link_82571,
1527         /* .setup_physical_interface: media type dependent */
1528 };
1529
1530 static struct e1000_phy_operations e82_phy_ops_igp = {
1531         .acquire_phy            = e1000_get_hw_semaphore_82571,
1532         .check_reset_block      = e1000e_check_reset_block_generic,
1533         .commit_phy             = NULL,
1534         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1535         .get_cfg_done           = e1000_get_cfg_done_82571,
1536         .get_cable_length       = e1000e_get_cable_length_igp_2,
1537         .get_phy_info           = e1000e_get_phy_info_igp,
1538         .read_phy_reg           = e1000e_read_phy_reg_igp,
1539         .release_phy            = e1000_put_hw_semaphore_82571,
1540         .reset_phy              = e1000e_phy_hw_reset_generic,
1541         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1542         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1543         .write_phy_reg          = e1000e_write_phy_reg_igp,
1544         .cfg_on_link_up         = NULL,
1545 };
1546
1547 static struct e1000_phy_operations e82_phy_ops_m88 = {
1548         .acquire_phy            = e1000_get_hw_semaphore_82571,
1549         .check_reset_block      = e1000e_check_reset_block_generic,
1550         .commit_phy             = e1000e_phy_sw_reset,
1551         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1552         .get_cfg_done           = e1000e_get_cfg_done,
1553         .get_cable_length       = e1000e_get_cable_length_m88,
1554         .get_phy_info           = e1000e_get_phy_info_m88,
1555         .read_phy_reg           = e1000e_read_phy_reg_m88,
1556         .release_phy            = e1000_put_hw_semaphore_82571,
1557         .reset_phy              = e1000e_phy_hw_reset_generic,
1558         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1559         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1560         .write_phy_reg          = e1000e_write_phy_reg_m88,
1561         .cfg_on_link_up         = NULL,
1562 };
1563
1564 static struct e1000_phy_operations e82_phy_ops_bm = {
1565         .acquire_phy            = e1000_get_hw_semaphore_82571,
1566         .check_reset_block      = e1000e_check_reset_block_generic,
1567         .commit_phy             = e1000e_phy_sw_reset,
1568         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1569         .get_cfg_done           = e1000e_get_cfg_done,
1570         .get_cable_length       = e1000e_get_cable_length_m88,
1571         .get_phy_info           = e1000e_get_phy_info_m88,
1572         .read_phy_reg           = e1000e_read_phy_reg_bm2,
1573         .release_phy            = e1000_put_hw_semaphore_82571,
1574         .reset_phy              = e1000e_phy_hw_reset_generic,
1575         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1576         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1577         .write_phy_reg          = e1000e_write_phy_reg_bm2,
1578         .cfg_on_link_up         = NULL,
1579 };
1580
1581 static struct e1000_nvm_operations e82571_nvm_ops = {
1582         .acquire_nvm            = e1000_acquire_nvm_82571,
1583         .read_nvm               = e1000e_read_nvm_eerd,
1584         .release_nvm            = e1000_release_nvm_82571,
1585         .update_nvm             = e1000_update_nvm_checksum_82571,
1586         .valid_led_default      = e1000_valid_led_default_82571,
1587         .validate_nvm           = e1000_validate_nvm_checksum_82571,
1588         .write_nvm              = e1000_write_nvm_82571,
1589 };
1590
1591 struct e1000_info e1000_82571_info = {
1592         .mac                    = e1000_82571,
1593         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1594                                   | FLAG_HAS_JUMBO_FRAMES
1595                                   | FLAG_HAS_WOL
1596                                   | FLAG_APME_IN_CTRL3
1597                                   | FLAG_RX_CSUM_ENABLED
1598                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1599                                   | FLAG_HAS_SMART_POWER_DOWN
1600                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1601                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1602                                   | FLAG_APME_CHECK_PORT_B,
1603         .pba                    = 38,
1604         .get_variants           = e1000_get_variants_82571,
1605         .mac_ops                = &e82571_mac_ops,
1606         .phy_ops                = &e82_phy_ops_igp,
1607         .nvm_ops                = &e82571_nvm_ops,
1608 };
1609
1610 struct e1000_info e1000_82572_info = {
1611         .mac                    = e1000_82572,
1612         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1613                                   | FLAG_HAS_JUMBO_FRAMES
1614                                   | FLAG_HAS_WOL
1615                                   | FLAG_APME_IN_CTRL3
1616                                   | FLAG_RX_CSUM_ENABLED
1617                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1618                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1619         .pba                    = 38,
1620         .get_variants           = e1000_get_variants_82571,
1621         .mac_ops                = &e82571_mac_ops,
1622         .phy_ops                = &e82_phy_ops_igp,
1623         .nvm_ops                = &e82571_nvm_ops,
1624 };
1625
1626 struct e1000_info e1000_82573_info = {
1627         .mac                    = e1000_82573,
1628         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1629                                   | FLAG_HAS_JUMBO_FRAMES
1630                                   | FLAG_HAS_WOL
1631                                   | FLAG_APME_IN_CTRL3
1632                                   | FLAG_RX_CSUM_ENABLED
1633                                   | FLAG_HAS_SMART_POWER_DOWN
1634                                   | FLAG_HAS_AMT
1635                                   | FLAG_HAS_ERT
1636                                   | FLAG_HAS_SWSM_ON_LOAD,
1637         .pba                    = 20,
1638         .get_variants           = e1000_get_variants_82571,
1639         .mac_ops                = &e82571_mac_ops,
1640         .phy_ops                = &e82_phy_ops_m88,
1641         .nvm_ops                = &e82571_nvm_ops,
1642 };
1643
1644 struct e1000_info e1000_82574_info = {
1645         .mac                    = e1000_82574,
1646         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1647                                   | FLAG_HAS_MSIX
1648                                   | FLAG_HAS_JUMBO_FRAMES
1649                                   | FLAG_HAS_WOL
1650                                   | FLAG_APME_IN_CTRL3
1651                                   | FLAG_RX_CSUM_ENABLED
1652                                   | FLAG_HAS_SMART_POWER_DOWN
1653                                   | FLAG_HAS_AMT
1654                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1655         .pba                    = 20,
1656         .get_variants           = e1000_get_variants_82571,
1657         .mac_ops                = &e82571_mac_ops,
1658         .phy_ops                = &e82_phy_ops_bm,
1659         .nvm_ops                = &e82571_nvm_ops,
1660 };
1661