2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/version.h>
52 #include <linux/spinlock.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/clk.h>
55 #include <linux/platform_device.h>
56 #include <linux/semaphore.h>
57 #include <linux/phy.h>
58 #include <linux/bitops.h>
60 #include <linux/uaccess.h>
61 #include <linux/davinci_emac.h>
66 #include "davinci_cpdma.h"
68 static int debug_level;
69 module_param(debug_level, int, 0);
70 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
72 /* Netif debug messages possible */
73 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
81 NETIF_MSG_TX_QUEUED | \
84 NETIF_MSG_RX_STATUS | \
90 #define EMAC_MAJOR_VERSION 6
91 #define EMAC_MINOR_VERSION 1
92 #define EMAC_MODULE_VERSION "6.1"
93 MODULE_VERSION(EMAC_MODULE_VERSION);
94 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
96 /* Configuration items */
97 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */
98 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
99 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
100 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
101 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
102 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
103 #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */
104 #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */
105 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
106 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
107 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
108 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
110 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
111 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
113 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
114 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
115 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
116 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
117 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
118 #define EMAC_DEF_RX_NUM_DESC (128)
119 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
120 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
121 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
123 /* Buffer descriptor parameters */
124 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
125 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
127 /* EMAC register related defines */
128 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
129 #define EMAC_NUM_MULTICAST_BITS (64)
130 #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC)
131 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
132 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
133 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
134 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
135 #define EMAC_INT_MASK_CLEAR (0xFF)
137 /* RX MBP register bit positions */
138 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
139 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
140 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
141 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
142 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
143 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
144 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
145 #define EMAC_RXMBP_PROMCH_SHIFT (16)
146 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
147 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
148 #define EMAC_RXMBP_BROADCH_SHIFT (8)
149 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
150 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
151 #define EMAC_RXMBP_MULTICH_SHIFT (0)
152 #define EMAC_RXMBP_MULTICH_MASK (0x7)
153 #define EMAC_RXMBP_CHMASK (0x7)
155 /* EMAC register definitions/bit maps used */
156 # define EMAC_MBP_RXPROMISC (0x00200000)
157 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
158 # define EMAC_MBP_RXBCAST (0x00002000)
159 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
160 # define EMAC_MBP_RXMCAST (0x00000020)
161 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
163 /* EMAC mac_control register */
164 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
165 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
166 #define EMAC_MACCONTROL_GMIIEN BIT(5)
167 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
168 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
169 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
171 /* GIGABIT MODE related bits */
172 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
173 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
175 /* EMAC mac_status register */
176 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
177 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
178 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
179 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
180 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
181 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
182 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
183 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
185 /* EMAC RX register masks */
186 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
187 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
189 /* MAC_IN_VECTOR (0x180) register bit fields */
190 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
191 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
192 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
193 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
195 /** NOTE:: For DM646x the IN_VECTOR has changed */
196 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
197 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
198 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
199 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
201 /* CPPI bit positions */
202 #define EMAC_CPPI_SOP_BIT BIT(31)
203 #define EMAC_CPPI_EOP_BIT BIT(30)
204 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
205 #define EMAC_CPPI_EOQ_BIT BIT(28)
206 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
207 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
208 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
209 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
210 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
212 /* Max hardware defines */
213 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
214 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
216 /* EMAC Peripheral Device Register Memory Layout structure */
217 #define EMAC_TXIDVER 0x0
218 #define EMAC_TXCONTROL 0x4
219 #define EMAC_TXTEARDOWN 0x8
220 #define EMAC_RXIDVER 0x10
221 #define EMAC_RXCONTROL 0x14
222 #define EMAC_RXTEARDOWN 0x18
223 #define EMAC_TXINTSTATRAW 0x80
224 #define EMAC_TXINTSTATMASKED 0x84
225 #define EMAC_TXINTMASKSET 0x88
226 #define EMAC_TXINTMASKCLEAR 0x8C
227 #define EMAC_MACINVECTOR 0x90
229 #define EMAC_DM646X_MACEOIVECTOR 0x94
231 #define EMAC_RXINTSTATRAW 0xA0
232 #define EMAC_RXINTSTATMASKED 0xA4
233 #define EMAC_RXINTMASKSET 0xA8
234 #define EMAC_RXINTMASKCLEAR 0xAC
235 #define EMAC_MACINTSTATRAW 0xB0
236 #define EMAC_MACINTSTATMASKED 0xB4
237 #define EMAC_MACINTMASKSET 0xB8
238 #define EMAC_MACINTMASKCLEAR 0xBC
240 #define EMAC_RXMBPENABLE 0x100
241 #define EMAC_RXUNICASTSET 0x104
242 #define EMAC_RXUNICASTCLEAR 0x108
243 #define EMAC_RXMAXLEN 0x10C
244 #define EMAC_RXBUFFEROFFSET 0x110
245 #define EMAC_RXFILTERLOWTHRESH 0x114
247 #define EMAC_MACCONTROL 0x160
248 #define EMAC_MACSTATUS 0x164
249 #define EMAC_EMCONTROL 0x168
250 #define EMAC_FIFOCONTROL 0x16C
251 #define EMAC_MACCONFIG 0x170
252 #define EMAC_SOFTRESET 0x174
253 #define EMAC_MACSRCADDRLO 0x1D0
254 #define EMAC_MACSRCADDRHI 0x1D4
255 #define EMAC_MACHASH1 0x1D8
256 #define EMAC_MACHASH2 0x1DC
257 #define EMAC_MACADDRLO 0x500
258 #define EMAC_MACADDRHI 0x504
259 #define EMAC_MACINDEX 0x508
261 /* EMAC HDP and Completion registors */
262 #define EMAC_TXHDP(ch) (0x600 + (ch * 4))
263 #define EMAC_RXHDP(ch) (0x620 + (ch * 4))
264 #define EMAC_TXCP(ch) (0x640 + (ch * 4))
265 #define EMAC_RXCP(ch) (0x660 + (ch * 4))
267 /* EMAC statistics registers */
268 #define EMAC_RXGOODFRAMES 0x200
269 #define EMAC_RXBCASTFRAMES 0x204
270 #define EMAC_RXMCASTFRAMES 0x208
271 #define EMAC_RXPAUSEFRAMES 0x20C
272 #define EMAC_RXCRCERRORS 0x210
273 #define EMAC_RXALIGNCODEERRORS 0x214
274 #define EMAC_RXOVERSIZED 0x218
275 #define EMAC_RXJABBER 0x21C
276 #define EMAC_RXUNDERSIZED 0x220
277 #define EMAC_RXFRAGMENTS 0x224
278 #define EMAC_RXFILTERED 0x228
279 #define EMAC_RXQOSFILTERED 0x22C
280 #define EMAC_RXOCTETS 0x230
281 #define EMAC_TXGOODFRAMES 0x234
282 #define EMAC_TXBCASTFRAMES 0x238
283 #define EMAC_TXMCASTFRAMES 0x23C
284 #define EMAC_TXPAUSEFRAMES 0x240
285 #define EMAC_TXDEFERRED 0x244
286 #define EMAC_TXCOLLISION 0x248
287 #define EMAC_TXSINGLECOLL 0x24C
288 #define EMAC_TXMULTICOLL 0x250
289 #define EMAC_TXEXCESSIVECOLL 0x254
290 #define EMAC_TXLATECOLL 0x258
291 #define EMAC_TXUNDERRUN 0x25C
292 #define EMAC_TXCARRIERSENSE 0x260
293 #define EMAC_TXOCTETS 0x264
294 #define EMAC_NETOCTETS 0x280
295 #define EMAC_RXSOFOVERRUNS 0x284
296 #define EMAC_RXMOFOVERRUNS 0x288
297 #define EMAC_RXDMAOVERRUNS 0x28C
299 /* EMAC DM644x control registers */
300 #define EMAC_CTRL_EWCTL (0x4)
301 #define EMAC_CTRL_EWINTTCNT (0x8)
303 /* EMAC DM644x control module masks */
304 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
305 #define EMAC_DM644X_INTMIN_INTVL 0x1
306 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
308 /* EMAC DM646X control module registers */
309 #define EMAC_DM646X_CMINTCTRL 0x0C
310 #define EMAC_DM646X_CMRXINTEN 0x14
311 #define EMAC_DM646X_CMTXINTEN 0x18
312 #define EMAC_DM646X_CMRXINTMAX 0x70
313 #define EMAC_DM646X_CMTXINTMAX 0x74
315 /* EMAC DM646X control module masks */
316 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
317 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
318 #define EMAC_DM646X_CMINTMAX_CNT 63
319 #define EMAC_DM646X_CMINTMIN_CNT 2
320 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
321 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
324 /* EMAC EOI codes for C0 */
325 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
326 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
328 /* EMAC Stats Clear Mask */
329 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
331 /** net_buf_obj: EMAC network bufferdata structure
333 * EMAC network buffer data structure
335 struct emac_netbufobj {
341 /** net_pkt_obj: EMAC network packet data structure
343 * EMAC network packet data structure - supports buffer list (for future)
345 struct emac_netpktobj {
346 void *pkt_token; /* data token may hold tx/rx chan id */
347 struct emac_netbufobj *buf_list; /* array of network buffer objects */
352 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
354 * EMAC TX Buffer descriptor data structure
360 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
361 struct emac_tx_bd __iomem *next;
365 /** emac_txch: EMAC TX Channel data structure
367 * EMAC TX Channel data structure
376 void __iomem *bd_mem;
377 struct emac_tx_bd __iomem *bd_pool_head;
378 struct emac_tx_bd __iomem *active_queue_head;
379 struct emac_tx_bd __iomem *active_queue_tail;
380 struct emac_tx_bd __iomem *last_hw_bdprocessed;
382 u32 teardown_pending;
386 u32 proc_count; /* TX: # of times emac_tx_bdproc is called */
387 u32 mis_queued_packets;
389 u32 end_of_queue_add;
391 u32 no_active_pkts; /* IRQ when there were no packets to process */
392 u32 active_queue_count;
395 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
397 * EMAC RX Buffer descriptor data structure
404 struct emac_rx_bd __iomem *next;
409 /** emac_rxch: EMAC RX Channel data structure
411 * EMAC RX Channel data structure
414 /* configuration info */
422 void __iomem *bd_mem;
423 struct emac_rx_bd __iomem *bd_pool_head;
424 struct emac_rx_bd __iomem *active_queue_head;
425 struct emac_rx_bd __iomem *active_queue_tail;
427 u32 teardown_pending;
429 /* packet and buffer objects */
430 struct emac_netpktobj pkt_queue;
431 struct emac_netbufobj buf_queue;
434 u32 proc_count; /* number of times emac_rx_bdproc is called */
438 u32 out_of_rx_buffers;
440 u32 end_of_queue_add;
442 u32 mis_queued_packets;
445 /* emac_priv: EMAC private data structure
447 * EMAC adapter private data structure
451 struct net_device *ndev;
452 struct platform_device *pdev;
453 struct napi_struct napi;
457 void __iomem *remap_addr;
459 void __iomem *emac_base;
460 void __iomem *ctrl_base;
461 void __iomem *emac_ctrl_ram;
464 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
465 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
466 struct cpdma_ctlr *dma;
467 struct cpdma_chan *txchan;
468 struct cpdma_chan *rxchan;
469 u32 link; /* 1=link on, 0=link off */
470 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
471 u32 duplex; /* Link duplex: 0=Half, 1=Full */
480 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
483 struct phy_device *phydev;
485 /*platform specific members*/
486 void (*int_enable) (void);
487 void (*int_disable) (void);
490 /* clock frequency for EMAC */
491 static struct clk *emac_clk;
492 static unsigned long emac_bus_frequency;
494 #define emac_virt_to_phys(addr, priv) \
495 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
498 /* Cache macros - Packet buffers would be from skb pool which is cached */
499 #define EMAC_VIRT_NOCACHE(addr) (addr)
501 /* DM644x does not have BD's in cached memory - so no cache functions */
502 #define BD_CACHE_INVALIDATE(addr, size)
503 #define BD_CACHE_WRITEBACK(addr, size)
504 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
506 /* EMAC TX Host Error description strings */
507 static char *emac_txhost_errcodes[16] = {
508 "No error", "SOP error", "Ownership bit not set in SOP buffer",
509 "Zero Next Buffer Descriptor Pointer Without EOP",
510 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
511 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
512 "Reserved", "Reserved", "Reserved", "Reserved"
515 /* EMAC RX Host Error description strings */
516 static char *emac_rxhost_errcodes[16] = {
517 "No error", "Reserved", "Ownership bit not set in input buffer",
518 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
519 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
520 "Reserved", "Reserved", "Reserved", "Reserved"
524 #define emac_read(reg) ioread32(priv->emac_base + (reg))
525 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
527 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
528 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
531 * emac_dump_regs: Dump important EMAC registers to debug terminal
532 * @priv: The DaVinci EMAC private adapter structure
534 * Executes ethtool set cmd & sets phy mode
537 static void emac_dump_regs(struct emac_priv *priv)
539 struct device *emac_dev = &priv->ndev->dev;
541 /* Print important registers in EMAC */
542 dev_info(emac_dev, "EMAC Basic registers\n");
543 if (priv->version == EMAC_VERSION_1) {
544 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
545 emac_ctrl_read(EMAC_CTRL_EWCTL),
546 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
548 dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
549 emac_read(EMAC_TXIDVER),
550 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
551 emac_read(EMAC_RXIDVER),
552 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
553 dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
554 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
555 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
556 dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
557 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
558 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
559 dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
560 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
561 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
562 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
563 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
564 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
565 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
566 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
567 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
568 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
569 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
570 dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
571 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
572 dev_info(emac_dev, "EMAC Statistics\n");
573 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
574 emac_read(EMAC_RXGOODFRAMES));
575 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
576 emac_read(EMAC_RXBCASTFRAMES));
577 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
578 emac_read(EMAC_RXMCASTFRAMES));
579 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
580 emac_read(EMAC_RXPAUSEFRAMES));
581 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
582 emac_read(EMAC_RXCRCERRORS));
583 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
584 emac_read(EMAC_RXALIGNCODEERRORS));
585 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
586 emac_read(EMAC_RXOVERSIZED));
587 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
588 emac_read(EMAC_RXJABBER));
589 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
590 emac_read(EMAC_RXUNDERSIZED));
591 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
592 emac_read(EMAC_RXFRAGMENTS));
593 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
594 emac_read(EMAC_RXFILTERED));
595 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
596 emac_read(EMAC_RXQOSFILTERED));
597 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
598 emac_read(EMAC_RXOCTETS));
599 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
600 emac_read(EMAC_TXGOODFRAMES));
601 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
602 emac_read(EMAC_TXBCASTFRAMES));
603 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
604 emac_read(EMAC_TXMCASTFRAMES));
605 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
606 emac_read(EMAC_TXPAUSEFRAMES));
607 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
608 emac_read(EMAC_TXDEFERRED));
609 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
610 emac_read(EMAC_TXCOLLISION));
611 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
612 emac_read(EMAC_TXSINGLECOLL));
613 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
614 emac_read(EMAC_TXMULTICOLL));
615 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
616 emac_read(EMAC_TXEXCESSIVECOLL));
617 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
618 emac_read(EMAC_TXLATECOLL));
619 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
620 emac_read(EMAC_TXUNDERRUN));
621 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
622 emac_read(EMAC_TXCARRIERSENSE));
623 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
624 emac_read(EMAC_TXOCTETS));
625 dev_info(emac_dev, "EMAC: net_octets:%d\n",
626 emac_read(EMAC_NETOCTETS));
627 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
628 emac_read(EMAC_RXSOFOVERRUNS));
629 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
630 emac_read(EMAC_RXMOFOVERRUNS));
631 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
632 emac_read(EMAC_RXDMAOVERRUNS));
634 cpdma_ctlr_dump(priv->dma);
638 * emac_get_drvinfo: Get EMAC driver information
639 * @ndev: The DaVinci EMAC network adapter
640 * @info: ethtool info structure containing name and version
642 * Returns EMAC driver information (name and version)
645 static void emac_get_drvinfo(struct net_device *ndev,
646 struct ethtool_drvinfo *info)
648 strcpy(info->driver, emac_version_string);
649 strcpy(info->version, EMAC_MODULE_VERSION);
653 * emac_get_settings: Get EMAC settings
654 * @ndev: The DaVinci EMAC network adapter
655 * @ecmd: ethtool command
657 * Executes ethool get command
660 static int emac_get_settings(struct net_device *ndev,
661 struct ethtool_cmd *ecmd)
663 struct emac_priv *priv = netdev_priv(ndev);
665 return phy_ethtool_gset(priv->phydev, ecmd);
672 * emac_set_settings: Set EMAC settings
673 * @ndev: The DaVinci EMAC network adapter
674 * @ecmd: ethtool command
676 * Executes ethool set command
679 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
681 struct emac_priv *priv = netdev_priv(ndev);
683 return phy_ethtool_sset(priv->phydev, ecmd);
690 * emac_get_coalesce : Get interrupt coalesce settings for this device
691 * @ndev : The DaVinci EMAC network adapter
692 * @coal : ethtool coalesce settings structure
694 * Fetch the current interrupt coalesce settings
697 static int emac_get_coalesce(struct net_device *ndev,
698 struct ethtool_coalesce *coal)
700 struct emac_priv *priv = netdev_priv(ndev);
702 coal->rx_coalesce_usecs = priv->coal_intvl;
708 * emac_set_coalesce : Set interrupt coalesce settings for this device
709 * @ndev : The DaVinci EMAC network adapter
710 * @coal : ethtool coalesce settings structure
712 * Set interrupt coalesce parameters
715 static int emac_set_coalesce(struct net_device *ndev,
716 struct ethtool_coalesce *coal)
718 struct emac_priv *priv = netdev_priv(ndev);
719 u32 int_ctrl, num_interrupts = 0;
720 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
722 if (!coal->rx_coalesce_usecs)
725 coal_intvl = coal->rx_coalesce_usecs;
727 switch (priv->version) {
729 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
730 prescale = priv->bus_freq_mhz * 4;
732 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
733 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
735 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
737 * Interrupt pacer works with 4us Pulse, we can
738 * throttle further by dilating the 4us pulse.
740 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
742 if (addnl_dvdr > 1) {
743 prescale *= addnl_dvdr;
744 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
746 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
750 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
754 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
756 int_ctrl |= EMAC_DM646X_INTPACEEN;
757 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
758 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
759 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
761 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
762 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
766 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
767 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
768 prescale = coal_intvl * priv->bus_freq_mhz;
769 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
770 prescale = EMAC_DM644X_EWINTCNT_MASK;
771 coal_intvl = prescale / priv->bus_freq_mhz;
773 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
778 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
779 priv->coal_intvl = coal_intvl;
787 * ethtool_ops: DaVinci EMAC Ethtool structure
789 * Ethtool support for EMAC adapter
792 static const struct ethtool_ops ethtool_ops = {
793 .get_drvinfo = emac_get_drvinfo,
794 .get_settings = emac_get_settings,
795 .set_settings = emac_set_settings,
796 .get_link = ethtool_op_get_link,
797 .get_coalesce = emac_get_coalesce,
798 .set_coalesce = emac_set_coalesce,
802 * emac_update_phystatus: Update Phy status
803 * @priv: The DaVinci EMAC private adapter structure
805 * Updates phy status and takes action for network queue if required
806 * based upon link status
809 static void emac_update_phystatus(struct emac_priv *priv)
814 struct net_device *ndev = priv->ndev;
816 mac_control = emac_read(EMAC_MACCONTROL);
817 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
818 DUPLEX_FULL : DUPLEX_HALF;
820 new_duplex = priv->phydev->duplex;
822 new_duplex = DUPLEX_FULL;
824 /* We get called only if link has changed (speed/duplex/status) */
825 if ((priv->link) && (new_duplex != cur_duplex)) {
826 priv->duplex = new_duplex;
827 if (DUPLEX_FULL == priv->duplex)
828 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
830 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
833 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
834 mac_control = emac_read(EMAC_MACCONTROL);
835 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
836 EMAC_DM646X_MACCONTORL_GIGFORCE);
838 /* Clear the GIG bit and GIGFORCE bit */
839 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
840 EMAC_DM646X_MACCONTORL_GIG);
842 if (priv->rmii_en && (priv->speed == SPEED_100))
843 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
845 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
848 /* Update mac_control if changed */
849 emac_write(EMAC_MACCONTROL, mac_control);
853 if (!netif_carrier_ok(ndev))
854 netif_carrier_on(ndev);
855 /* reactivate the transmit queue if it is stopped */
856 if (netif_running(ndev) && netif_queue_stopped(ndev))
857 netif_wake_queue(ndev);
860 if (netif_carrier_ok(ndev))
861 netif_carrier_off(ndev);
862 if (!netif_queue_stopped(ndev))
863 netif_stop_queue(ndev);
868 * hash_get: Calculate hash value from mac address
869 * @addr: mac address to delete from hash table
871 * Calculates hash value from mac address
874 static u32 hash_get(u8 *addr)
881 for (cnt = 0; cnt < 2; cnt++) {
883 hash ^= (tmpval >> 2) ^ (tmpval << 4);
885 hash ^= (tmpval >> 4) ^ (tmpval << 2);
887 hash ^= (tmpval >> 6) ^ (tmpval);
894 * hash_add: Hash function to add mac addr from hash table
895 * @priv: The DaVinci EMAC private adapter structure
896 * mac_addr: mac address to delete from hash table
898 * Adds mac address to the internal hash table
901 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
903 struct device *emac_dev = &priv->ndev->dev;
906 u32 hash_value = hash_get(mac_addr);
908 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
909 if (netif_msg_drv(priv)) {
910 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
911 "Hash %08x, should not be greater than %08x",
912 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
917 /* set the hash bit only if not previously set */
918 if (priv->multicast_hash_cnt[hash_value] == 0) {
919 rc = 1; /* hash value changed */
920 if (hash_value < 32) {
921 hash_bit = BIT(hash_value);
922 priv->mac_hash1 |= hash_bit;
924 hash_bit = BIT((hash_value - 32));
925 priv->mac_hash2 |= hash_bit;
929 /* incr counter for num of mcast addr's mapped to "this" hash bit */
930 ++priv->multicast_hash_cnt[hash_value];
936 * hash_del: Hash function to delete mac addr from hash table
937 * @priv: The DaVinci EMAC private adapter structure
938 * mac_addr: mac address to delete from hash table
940 * Removes mac address from the internal hash table
943 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
948 hash_value = hash_get(mac_addr);
949 if (priv->multicast_hash_cnt[hash_value] > 0) {
950 /* dec cntr for num of mcast addr's mapped to this hash bit */
951 --priv->multicast_hash_cnt[hash_value];
954 /* if counter still > 0, at least one multicast address refers
955 * to this hash bit. so return 0 */
956 if (priv->multicast_hash_cnt[hash_value] > 0)
959 if (hash_value < 32) {
960 hash_bit = BIT(hash_value);
961 priv->mac_hash1 &= ~hash_bit;
963 hash_bit = BIT((hash_value - 32));
964 priv->mac_hash2 &= ~hash_bit;
967 /* return 1 to indicate change in mac_hash registers reqd */
971 /* EMAC multicast operation */
972 #define EMAC_MULTICAST_ADD 0
973 #define EMAC_MULTICAST_DEL 1
974 #define EMAC_ALL_MULTI_SET 2
975 #define EMAC_ALL_MULTI_CLR 3
978 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
979 * @priv: The DaVinci EMAC private adapter structure
980 * @action: multicast operation to perform
981 * mac_addr: mac address to set
983 * Set multicast addresses in EMAC adapter - internal function
986 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
988 struct device *emac_dev = &priv->ndev->dev;
992 case EMAC_MULTICAST_ADD:
993 update = hash_add(priv, mac_addr);
995 case EMAC_MULTICAST_DEL:
996 update = hash_del(priv, mac_addr);
998 case EMAC_ALL_MULTI_SET:
1000 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
1001 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
1003 case EMAC_ALL_MULTI_CLR:
1005 priv->mac_hash1 = 0;
1006 priv->mac_hash2 = 0;
1007 memset(&(priv->multicast_hash_cnt[0]), 0,
1008 sizeof(priv->multicast_hash_cnt[0]) *
1009 EMAC_NUM_MULTICAST_BITS);
1012 if (netif_msg_drv(priv))
1013 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
1014 ": bad operation %d", action);
1018 /* write to the hardware only if the register status chances */
1020 emac_write(EMAC_MACHASH1, priv->mac_hash1);
1021 emac_write(EMAC_MACHASH2, priv->mac_hash2);
1026 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
1027 * @ndev: The DaVinci EMAC network adapter
1029 * Set multicast addresses in EMAC adapter
1032 static void emac_dev_mcast_set(struct net_device *ndev)
1035 struct emac_priv *priv = netdev_priv(ndev);
1037 mbp_enable = emac_read(EMAC_RXMBPENABLE);
1038 if (ndev->flags & IFF_PROMISC) {
1039 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
1040 mbp_enable |= (EMAC_MBP_RXPROMISC);
1042 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
1043 if ((ndev->flags & IFF_ALLMULTI) ||
1044 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
1045 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
1046 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
1048 if (!netdev_mc_empty(ndev)) {
1049 struct netdev_hw_addr *ha;
1051 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
1052 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
1053 /* program multicast address list into EMAC hardware */
1054 netdev_for_each_mc_addr(ha, ndev) {
1055 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
1059 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
1060 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
1063 /* Set mbp config register */
1064 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1067 /*************************************************************************
1068 * EMAC Hardware manipulation
1069 *************************************************************************/
1072 * emac_int_disable: Disable EMAC module interrupt (from adapter)
1073 * @priv: The DaVinci EMAC private adapter structure
1075 * Disable EMAC interrupt on the adapter
1078 static void emac_int_disable(struct emac_priv *priv)
1080 if (priv->version == EMAC_VERSION_2) {
1081 unsigned long flags;
1083 local_irq_save(flags);
1085 /* Program C0_Int_En to zero to turn off
1086 * interrupts to the CPU */
1087 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1088 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1089 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1090 if (priv->int_disable)
1091 priv->int_disable();
1093 local_irq_restore(flags);
1096 /* Set DM644x control registers for interrupt control */
1097 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1102 * emac_int_enable: Enable EMAC module interrupt (from adapter)
1103 * @priv: The DaVinci EMAC private adapter structure
1105 * Enable EMAC interrupt on the adapter
1108 static void emac_int_enable(struct emac_priv *priv)
1110 if (priv->version == EMAC_VERSION_2) {
1111 if (priv->int_enable)
1114 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1115 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1117 /* In addition to turning on interrupt Enable, we need
1118 * ack by writing appropriate values to the EOI
1121 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1123 /* ack rxen only then a new pulse will be generated */
1124 emac_write(EMAC_DM646X_MACEOIVECTOR,
1125 EMAC_DM646X_MAC_EOI_C0_RXEN);
1127 /* ack txen- only then a new pulse will be generated */
1128 emac_write(EMAC_DM646X_MACEOIVECTOR,
1129 EMAC_DM646X_MAC_EOI_C0_TXEN);
1132 /* Set DM644x control registers for interrupt control */
1133 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1138 * emac_irq: EMAC interrupt handler
1139 * @irq: interrupt number
1140 * @dev_id: EMAC network adapter data structure ptr
1142 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1143 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1145 * Returns interrupt handled condition
1147 static irqreturn_t emac_irq(int irq, void *dev_id)
1149 struct net_device *ndev = (struct net_device *)dev_id;
1150 struct emac_priv *priv = netdev_priv(ndev);
1153 if (likely(netif_running(priv->ndev))) {
1154 emac_int_disable(priv);
1155 napi_schedule(&priv->napi);
1157 /* we are closing down, so dont process anything */
1162 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
1164 struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
1167 skb->dev = priv->ndev;
1168 skb_reserve(skb, NET_IP_ALIGN);
1172 static void emac_rx_handler(void *token, int len, int status)
1174 struct sk_buff *skb = token;
1175 struct net_device *ndev = skb->dev;
1176 struct emac_priv *priv = netdev_priv(ndev);
1177 struct device *emac_dev = &ndev->dev;
1180 /* free and bail if we are shutting down */
1181 if (unlikely(!netif_running(ndev))) {
1182 dev_kfree_skb_any(skb);
1186 /* recycle on recieve error */
1188 ndev->stats.rx_errors++;
1192 /* feed received packet up the stack */
1194 skb->protocol = eth_type_trans(skb, ndev);
1195 netif_receive_skb(skb);
1196 ndev->stats.rx_bytes += len;
1197 ndev->stats.rx_packets++;
1199 /* alloc a new packet for receive */
1200 skb = emac_rx_alloc(priv);
1202 if (netif_msg_rx_err(priv) && net_ratelimit())
1203 dev_err(emac_dev, "failed rx buffer alloc\n");
1208 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1209 skb_tailroom(skb), GFP_KERNEL);
1210 if (WARN_ON(ret < 0))
1211 dev_kfree_skb_any(skb);
1214 static void emac_tx_handler(void *token, int len, int status)
1216 struct sk_buff *skb = token;
1217 struct net_device *ndev = skb->dev;
1219 if (unlikely(netif_queue_stopped(ndev)))
1220 netif_start_queue(ndev);
1221 ndev->stats.tx_packets++;
1222 ndev->stats.tx_bytes += len;
1223 dev_kfree_skb_any(skb);
1226 /** EMAC on-chip buffer descriptor memory
1228 * WARNING: Please note that the on chip memory is used for both TX and RX
1229 * buffer descriptor queues and is equally divided between TX and RX desc's
1230 * If the number of TX or RX descriptors change this memory pointers need
1231 * to be adjusted. If external memory is allocated then these pointers can
1232 * pointer to the memory
1235 #define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram)
1236 #define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \
1237 (((priv)->ctrl_ram_size) >> 1))
1240 * emac_init_txch: TX channel initialization
1241 * @priv: The DaVinci EMAC private adapter structure
1242 * @ch: RX channel number
1244 * Called during device init to setup a TX channel (allocate buffer desc
1245 * create free pool and keep ready for transmission
1247 * Returns success(0) or mem alloc failures error code
1249 static int emac_init_txch(struct emac_priv *priv, u32 ch)
1251 struct device *emac_dev = &priv->ndev->dev;
1254 struct emac_tx_bd __iomem *curr_bd;
1255 struct emac_txch *txch = NULL;
1257 txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1259 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1262 priv->txch[ch] = txch;
1263 txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1264 txch->active_queue_head = NULL;
1265 txch->active_queue_tail = NULL;
1266 txch->queue_active = 0;
1267 txch->teardown_pending = 0;
1269 /* allocate memory for TX CPPI channel on a 4 byte boundry */
1270 txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1272 if (NULL == txch->tx_complete) {
1273 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1278 /* allocate buffer descriptor pool align every BD on four word
1279 * boundry for future requirements */
1280 bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1281 txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1282 txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1284 /* alloc TX BD memory */
1285 txch->bd_mem = EMAC_TX_BD_MEM(priv);
1286 __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1288 /* initialize the BD linked list */
1289 mem = (void __force __iomem *)
1290 (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1291 txch->bd_pool_head = NULL;
1292 for (cnt = 0; cnt < txch->num_bd; cnt++) {
1293 curr_bd = mem + (cnt * bd_size);
1294 curr_bd->next = txch->bd_pool_head;
1295 txch->bd_pool_head = curr_bd;
1298 /* reset statistics counters */
1299 txch->out_of_tx_bd = 0;
1300 txch->no_active_pkts = 0;
1301 txch->active_queue_count = 0;
1307 * emac_cleanup_txch: Book-keep function to clean TX channel resources
1308 * @priv: The DaVinci EMAC private adapter structure
1309 * @ch: TX channel number
1311 * Called to clean up TX channel resources
1314 static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1316 struct emac_txch *txch = priv->txch[ch];
1320 txch->bd_mem = NULL;
1321 kfree(txch->tx_complete);
1323 priv->txch[ch] = NULL;
1328 * emac_net_tx_complete: TX packet completion function
1329 * @priv: The DaVinci EMAC private adapter structure
1330 * @net_data_tokens: packet token - skb pointer
1331 * @num_tokens: number of skb's to free
1332 * @ch: TX channel number
1334 * Frees the skb once packet is transmitted
1337 static int emac_net_tx_complete(struct emac_priv *priv,
1338 void **net_data_tokens,
1339 int num_tokens, u32 ch)
1341 struct net_device *ndev = priv->ndev;
1344 if (unlikely(num_tokens && netif_queue_stopped(ndev)))
1345 netif_start_queue(ndev);
1346 for (cnt = 0; cnt < num_tokens; cnt++) {
1347 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1350 ndev->stats.tx_packets++;
1351 ndev->stats.tx_bytes += skb->len;
1352 dev_kfree_skb_any(skb);
1358 * emac_txch_teardown: TX channel teardown
1359 * @priv: The DaVinci EMAC private adapter structure
1360 * @ch: TX channel number
1362 * Called to teardown TX channel
1365 static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1367 struct device *emac_dev = &priv->ndev->dev;
1368 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1369 struct emac_txch *txch = priv->txch[ch];
1370 struct emac_tx_bd __iomem *curr_bd;
1372 while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1373 EMAC_TEARDOWN_VALUE) {
1374 /* wait till tx teardown complete */
1375 cpu_relax(); /* TODO: check if this helps ... */
1377 if (0 == teardown_cnt) {
1378 dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1382 emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1384 /* process sent packets and return skb's to upper layer */
1385 if (1 == txch->queue_active) {
1386 curr_bd = txch->active_queue_head;
1387 while (curr_bd != NULL) {
1388 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1389 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1392 emac_net_tx_complete(priv, (void __force *)
1393 &curr_bd->buf_token, 1, ch);
1394 if (curr_bd != txch->active_queue_tail)
1395 curr_bd = curr_bd->next;
1399 txch->bd_pool_head = txch->active_queue_head;
1400 txch->active_queue_head =
1401 txch->active_queue_tail = NULL;
1406 * emac_stop_txch: Stop TX channel operation
1407 * @priv: The DaVinci EMAC private adapter structure
1408 * @ch: TX channel number
1410 * Called to stop TX channel operation
1413 static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1415 struct emac_txch *txch = priv->txch[ch];
1418 txch->teardown_pending = 1;
1419 emac_write(EMAC_TXTEARDOWN, 0);
1420 emac_txch_teardown(priv, ch);
1421 txch->teardown_pending = 0;
1422 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1427 * emac_tx_bdproc: TX buffer descriptor (packet) processing
1428 * @priv: The DaVinci EMAC private adapter structure
1429 * @ch: TX channel number to process buffer descriptors for
1430 * @budget: number of packets allowed to process
1431 * @pending: indication to caller that packets are pending to process
1433 * Processes TX buffer descriptors after packets are transmitted - checks
1434 * ownership bit on the TX * descriptor and requeues it to free pool & frees
1435 * the SKB buffer. Only "budget" number of packets are processed and
1436 * indication of pending packets provided to the caller
1438 * Returns number of packets processed
1440 static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1442 struct device *emac_dev = &priv->ndev->dev;
1443 unsigned long flags;
1445 u32 pkts_processed = 0;
1446 u32 tx_complete_cnt = 0;
1447 struct emac_tx_bd __iomem *curr_bd;
1448 struct emac_txch *txch = priv->txch[ch];
1449 u32 *tx_complete_ptr = txch->tx_complete;
1451 if (unlikely(1 == txch->teardown_pending)) {
1452 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1453 dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1454 "teardown pending\n");
1456 return 0; /* dont handle any pkt completions */
1460 spin_lock_irqsave(&priv->tx_lock, flags);
1461 curr_bd = txch->active_queue_head;
1462 if (NULL == curr_bd) {
1463 emac_write(EMAC_TXCP(ch),
1464 emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1465 txch->no_active_pkts++;
1466 spin_unlock_irqrestore(&priv->tx_lock, flags);
1469 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1470 frame_status = curr_bd->mode;
1472 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1473 (pkts_processed < budget)) {
1474 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1475 txch->active_queue_head = curr_bd->next;
1476 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1477 if (curr_bd->next) { /* misqueued packet */
1478 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1479 ++txch->mis_queued_packets;
1481 txch->queue_active = 0; /* end of queue */
1485 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1486 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1489 *tx_complete_ptr = (u32) curr_bd->buf_token;
1492 curr_bd->next = txch->bd_pool_head;
1493 txch->bd_pool_head = curr_bd;
1494 --txch->active_queue_count;
1496 txch->last_hw_bdprocessed = curr_bd;
1497 curr_bd = txch->active_queue_head;
1499 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1500 frame_status = curr_bd->mode;
1502 } /* end of pkt processing loop */
1504 emac_net_tx_complete(priv,
1505 (void *)&txch->tx_complete[0],
1506 tx_complete_cnt, ch);
1507 spin_unlock_irqrestore(&priv->tx_lock, flags);
1508 return pkts_processed;
1511 #define EMAC_ERR_TX_OUT_OF_BD -1
1514 * emac_send: EMAC Transmit function (internal)
1515 * @priv: The DaVinci EMAC private adapter structure
1516 * @pkt: packet pointer (contains skb ptr)
1517 * @ch: TX channel number
1519 * Called by the transmit function to queue the packet in EMAC hardware queue
1521 * Returns success(0) or error code (typically out of desc's)
1523 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1525 unsigned long flags;
1526 struct emac_tx_bd __iomem *curr_bd;
1527 struct emac_txch *txch;
1528 struct emac_netbufobj *buf_list;
1530 txch = priv->txch[ch];
1531 buf_list = pkt->buf_list; /* get handle to the buffer array */
1533 /* check packet size and pad if short */
1534 if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1535 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1536 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1539 spin_lock_irqsave(&priv->tx_lock, flags);
1540 curr_bd = txch->bd_pool_head;
1541 if (curr_bd == NULL) {
1542 txch->out_of_tx_bd++;
1543 spin_unlock_irqrestore(&priv->tx_lock, flags);
1544 return EMAC_ERR_TX_OUT_OF_BD;
1547 txch->bd_pool_head = curr_bd->next;
1548 curr_bd->buf_token = buf_list->buf_token;
1549 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr,
1550 buf_list->length, DMA_TO_DEVICE);
1551 curr_bd->off_b_len = buf_list->length;
1552 curr_bd->h_next = 0;
1553 curr_bd->next = NULL;
1554 curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1555 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1557 /* flush the packet from cache if write back cache is present */
1558 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1560 /* send the packet */
1561 if (txch->active_queue_head == NULL) {
1562 txch->active_queue_head = curr_bd;
1563 txch->active_queue_tail = curr_bd;
1564 if (1 != txch->queue_active) {
1565 emac_write(EMAC_TXHDP(ch),
1566 emac_virt_to_phys(curr_bd, priv));
1567 txch->queue_active = 1;
1569 ++txch->queue_reinit;
1571 register struct emac_tx_bd __iomem *tail_bd;
1572 register u32 frame_status;
1574 tail_bd = txch->active_queue_tail;
1575 tail_bd->next = curr_bd;
1576 txch->active_queue_tail = curr_bd;
1577 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1578 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1579 frame_status = tail_bd->mode;
1580 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1581 emac_write(EMAC_TXHDP(ch),
1582 emac_virt_to_phys(curr_bd, priv));
1583 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1584 tail_bd->mode = frame_status;
1585 ++txch->end_of_queue_add;
1588 txch->active_queue_count++;
1589 spin_unlock_irqrestore(&priv->tx_lock, flags);
1594 * emac_dev_xmit: EMAC Transmit function
1596 * @ndev: The DaVinci EMAC network adapter
1598 * Called by the system to transmit a packet - we queue the packet in
1599 * EMAC hardware transmit queue
1601 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1603 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1605 struct device *emac_dev = &ndev->dev;
1607 struct emac_priv *priv = netdev_priv(ndev);
1609 /* If no link, return */
1610 if (unlikely(!priv->link)) {
1611 if (netif_msg_tx_err(priv) && net_ratelimit())
1612 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1616 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1617 if (unlikely(ret_code < 0)) {
1618 if (netif_msg_tx_err(priv) && net_ratelimit())
1619 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1623 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1625 if (unlikely(ret_code != 0)) {
1626 if (netif_msg_tx_err(priv) && net_ratelimit())
1627 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1631 return NETDEV_TX_OK;
1634 ndev->stats.tx_dropped++;
1635 netif_stop_queue(ndev);
1636 return NETDEV_TX_BUSY;
1640 * emac_dev_tx_timeout: EMAC Transmit timeout function
1641 * @ndev: The DaVinci EMAC network adapter
1643 * Called when system detects that a skb timeout period has expired
1644 * potentially due to a fault in the adapter in not being able to send
1645 * it out on the wire. We teardown the TX channel assuming a hardware
1646 * error and re-initialize the TX channel for hardware operation
1649 static void emac_dev_tx_timeout(struct net_device *ndev)
1651 struct emac_priv *priv = netdev_priv(ndev);
1652 struct device *emac_dev = &ndev->dev;
1654 if (netif_msg_tx_err(priv))
1655 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1657 emac_dump_regs(priv);
1659 ndev->stats.tx_errors++;
1660 emac_int_disable(priv);
1661 cpdma_chan_stop(priv->txchan);
1662 cpdma_chan_start(priv->txchan);
1663 emac_int_enable(priv);
1667 * emac_net_alloc_rx_buf: Allocate a skb for RX
1668 * @priv: The DaVinci EMAC private adapter structure
1669 * @buf_size: size of SKB data buffer to allocate
1670 * @data_token: data token returned (skb handle for storing in buffer desc)
1671 * @ch: RX channel number
1673 * Called during RX channel setup - allocates skb buffer of required size
1674 * and provides the skb handle and allocated buffer data pointer to caller
1676 * Returns skb data pointer or 0 on failure to alloc skb
1678 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1679 void **data_token, u32 ch)
1681 struct net_device *ndev = priv->ndev;
1682 struct device *emac_dev = &ndev->dev;
1683 struct sk_buff *p_skb;
1685 p_skb = dev_alloc_skb(buf_size);
1686 if (unlikely(NULL == p_skb)) {
1687 if (netif_msg_rx_err(priv) && net_ratelimit())
1688 dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1692 /* set device pointer in skb and reserve space for extra bytes */
1694 skb_reserve(p_skb, NET_IP_ALIGN);
1695 *data_token = (void *) p_skb;
1700 * emac_init_rxch: RX channel initialization
1701 * @priv: The DaVinci EMAC private adapter structure
1702 * @ch: RX channel number
1703 * @param: mac address for RX channel
1705 * Called during device init to setup a RX channel (allocate buffers and
1706 * buffer descriptors, create queue and keep ready for reception
1708 * Returns success(0) or mem alloc failures error code
1710 static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1712 struct device *emac_dev = &priv->ndev->dev;
1715 struct emac_rx_bd __iomem *curr_bd;
1716 struct emac_rxch *rxch = NULL;
1718 rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1720 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1723 priv->rxch[ch] = rxch;
1724 rxch->buf_size = priv->rx_buf_size;
1725 rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1726 rxch->queue_active = 0;
1727 rxch->teardown_pending = 0;
1729 /* save mac address */
1730 for (cnt = 0; cnt < 6; cnt++)
1731 rxch->mac_addr[cnt] = param[cnt];
1733 /* allocate buffer descriptor pool align every BD on four word
1734 * boundry for future requirements */
1735 bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1736 rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1737 rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1738 rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1739 __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1740 rxch->pkt_queue.buf_list = &rxch->buf_queue;
1742 /* allocate RX buffer and initialize the BD linked list */
1743 mem = (void __force __iomem *)
1744 (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1745 rxch->active_queue_head = NULL;
1746 rxch->active_queue_tail = mem;
1747 for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1748 curr_bd = mem + (cnt * bd_size);
1749 /* for future use the last parameter contains the BD ptr */
1750 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1752 (void __force **)&curr_bd->buf_token,
1754 if (curr_bd->data_ptr == NULL) {
1755 dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1756 "failed for ch %d\n", ch);
1761 /* populate the hardware descriptor */
1762 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1764 curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr,
1765 rxch->buf_size, DMA_FROM_DEVICE);
1766 curr_bd->off_b_len = rxch->buf_size;
1767 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1769 /* write back to hardware memory */
1770 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1771 EMAC_BD_LENGTH_FOR_CACHE);
1772 curr_bd->next = rxch->active_queue_head;
1773 rxch->active_queue_head = curr_bd;
1776 /* At this point rxCppi->activeQueueHead points to the first
1777 RX BD ready to be given to RX HDP and rxch->active_queue_tail
1778 points to the last RX BD
1784 * emac_rxch_teardown: RX channel teardown
1785 * @priv: The DaVinci EMAC private adapter structure
1786 * @ch: RX channel number
1788 * Called during device stop to teardown RX channel
1791 static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1793 struct device *emac_dev = &priv->ndev->dev;
1794 u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1796 while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1797 EMAC_TEARDOWN_VALUE) {
1798 /* wait till tx teardown complete */
1799 cpu_relax(); /* TODO: check if this helps ... */
1801 if (0 == teardown_cnt) {
1802 dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1806 emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1810 * emac_stop_rxch: Stop RX channel operation
1811 * @priv: The DaVinci EMAC private adapter structure
1812 * @ch: RX channel number
1814 * Called during device stop to stop RX channel operation
1817 static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1819 struct emac_rxch *rxch = priv->rxch[ch];
1822 rxch->teardown_pending = 1;
1823 emac_write(EMAC_RXTEARDOWN, ch);
1824 /* wait for teardown complete */
1825 emac_rxch_teardown(priv, ch);
1826 rxch->teardown_pending = 0;
1827 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1832 * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1833 * @priv: The DaVinci EMAC private adapter structure
1834 * @ch: RX channel number
1836 * Called during device stop to clean up RX channel resources
1839 static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1841 struct emac_rxch *rxch = priv->rxch[ch];
1842 struct emac_rx_bd __iomem *curr_bd;
1845 /* free the receive buffers previously allocated */
1846 curr_bd = rxch->active_queue_head;
1848 if (curr_bd->buf_token) {
1849 dma_unmap_single(&priv->ndev->dev,
1852 & EMAC_RX_BD_BUF_SIZE,
1855 dev_kfree_skb_any((struct sk_buff *)\
1856 curr_bd->buf_token);
1858 curr_bd = curr_bd->next;
1861 rxch->bd_mem = NULL;
1863 priv->rxch[ch] = NULL;
1868 * emac_set_type0addr: Set EMAC Type0 mac address
1869 * @priv: The DaVinci EMAC private adapter structure
1870 * @ch: RX channel number
1871 * @mac_addr: MAC address to set in device
1873 * Called internally to set Type0 mac address of the adapter (Device)
1875 * Returns success (0) or appropriate error code (none as of now)
1877 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1880 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1881 emac_write(EMAC_MACSRCADDRLO, val);
1883 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1884 (mac_addr[1] << 8) | (mac_addr[0]));
1885 emac_write(EMAC_MACSRCADDRHI, val);
1886 val = emac_read(EMAC_RXUNICASTSET);
1888 emac_write(EMAC_RXUNICASTSET, val);
1889 val = emac_read(EMAC_RXUNICASTCLEAR);
1891 emac_write(EMAC_RXUNICASTCLEAR, val);
1895 * emac_set_type1addr: Set EMAC Type1 mac address
1896 * @priv: The DaVinci EMAC private adapter structure
1897 * @ch: RX channel number
1898 * @mac_addr: MAC address to set in device
1900 * Called internally to set Type1 mac address of the adapter (Device)
1902 * Returns success (0) or appropriate error code (none as of now)
1904 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1907 emac_write(EMAC_MACINDEX, ch);
1908 val = ((mac_addr[5] << 8) | mac_addr[4]);
1909 emac_write(EMAC_MACADDRLO, val);
1910 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1911 (mac_addr[1] << 8) | (mac_addr[0]));
1912 emac_write(EMAC_MACADDRHI, val);
1913 emac_set_type0addr(priv, ch, mac_addr);
1917 * emac_set_type2addr: Set EMAC Type2 mac address
1918 * @priv: The DaVinci EMAC private adapter structure
1919 * @ch: RX channel number
1920 * @mac_addr: MAC address to set in device
1921 * @index: index into RX address entries
1922 * @match: match parameter for RX address matching logic
1924 * Called internally to set Type2 mac address of the adapter (Device)
1926 * Returns success (0) or appropriate error code (none as of now)
1928 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1929 char *mac_addr, int index, int match)
1932 emac_write(EMAC_MACINDEX, index);
1933 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1934 (mac_addr[1] << 8) | (mac_addr[0]));
1935 emac_write(EMAC_MACADDRHI, val);
1936 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1937 (match << 19) | BIT(20));
1938 emac_write(EMAC_MACADDRLO, val);
1939 emac_set_type0addr(priv, ch, mac_addr);
1943 * emac_setmac: Set mac address in the adapter (internal function)
1944 * @priv: The DaVinci EMAC private adapter structure
1945 * @ch: RX channel number
1946 * @mac_addr: MAC address to set in device
1948 * Called internally to set the mac address of the adapter (Device)
1950 * Returns success (0) or appropriate error code (none as of now)
1952 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1954 struct device *emac_dev = &priv->ndev->dev;
1956 if (priv->rx_addr_type == 0) {
1957 emac_set_type0addr(priv, ch, mac_addr);
1958 } else if (priv->rx_addr_type == 1) {
1960 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1961 emac_set_type1addr(priv, ch, mac_addr);
1962 } else if (priv->rx_addr_type == 2) {
1963 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1964 emac_set_type0addr(priv, ch, mac_addr);
1966 if (netif_msg_drv(priv))
1967 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1972 * emac_dev_setmac_addr: Set mac address in the adapter
1973 * @ndev: The DaVinci EMAC network adapter
1974 * @addr: MAC address to set in device
1976 * Called by the system to set the mac address of the adapter (Device)
1978 * Returns success (0) or appropriate error code (none as of now)
1980 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1982 struct emac_priv *priv = netdev_priv(ndev);
1983 struct device *emac_dev = &priv->ndev->dev;
1984 struct sockaddr *sa = addr;
1986 if (!is_valid_ether_addr(sa->sa_data))
1989 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1990 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1991 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1993 /* MAC address is configured only after the interface is enabled. */
1994 if (netif_running(ndev)) {
1995 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1996 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1999 if (netif_msg_drv(priv))
2000 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
2007 * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
2008 * @priv: The DaVinci EMAC private adapter structure
2009 * @ch: RX channel number to process buffer descriptors for
2010 * @curr_bd: current buffer descriptor
2011 * @buffer: buffer pointer for descriptor
2012 * @buf_token: buffer token (stores skb information)
2014 * Prepares the recycled buffer descriptor and addes it to hardware
2015 * receive queue - if queue empty this descriptor becomes the head
2016 * else addes the descriptor to end of queue
2019 static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
2020 struct emac_rx_bd __iomem *curr_bd,
2021 char *buffer, void *buf_token)
2023 struct emac_rxch *rxch = priv->rxch[ch];
2025 /* populate the hardware descriptor */
2026 curr_bd->h_next = 0;
2027 curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer,
2028 rxch->buf_size, DMA_FROM_DEVICE);
2029 curr_bd->off_b_len = rxch->buf_size;
2030 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
2031 curr_bd->next = NULL;
2032 curr_bd->data_ptr = buffer;
2033 curr_bd->buf_token = buf_token;
2036 BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2037 if (rxch->active_queue_head == NULL) {
2038 rxch->active_queue_head = curr_bd;
2039 rxch->active_queue_tail = curr_bd;
2040 if (0 != rxch->queue_active) {
2041 emac_write(EMAC_RXHDP(ch),
2042 emac_virt_to_phys(rxch->active_queue_head, priv));
2043 rxch->queue_active = 1;
2046 struct emac_rx_bd __iomem *tail_bd;
2049 tail_bd = rxch->active_queue_tail;
2050 rxch->active_queue_tail = curr_bd;
2051 tail_bd->next = curr_bd;
2052 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
2053 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
2054 frame_status = tail_bd->mode;
2055 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2056 emac_write(EMAC_RXHDP(ch),
2057 emac_virt_to_phys(curr_bd, priv));
2058 frame_status &= ~(EMAC_CPPI_EOQ_BIT);
2059 tail_bd->mode = frame_status;
2060 ++rxch->end_of_queue_add;
2063 ++rxch->recycled_bd;
2067 * emac_net_rx_cb: Prepares packet and sends to upper layer
2068 * @priv: The DaVinci EMAC private adapter structure
2069 * @net_pkt_list: Network packet list (received packets)
2071 * Invalidates packet buffer memory and sends the received packet to upper
2074 * Returns success or appropriate error code (none as of now)
2076 static int emac_net_rx_cb(struct emac_priv *priv,
2077 struct emac_netpktobj *net_pkt_list)
2079 struct net_device *ndev = priv->ndev;
2080 struct sk_buff *p_skb = net_pkt_list->pkt_token;
2081 /* set length of packet */
2082 skb_put(p_skb, net_pkt_list->pkt_length);
2083 p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
2084 netif_receive_skb(p_skb);
2085 ndev->stats.rx_bytes += net_pkt_list->pkt_length;
2086 ndev->stats.rx_packets++;
2091 * emac_rx_bdproc: RX buffer descriptor (packet) processing
2092 * @priv: The DaVinci EMAC private adapter structure
2093 * @ch: RX channel number to process buffer descriptors for
2094 * @budget: number of packets allowed to process
2095 * @pending: indication to caller that packets are pending to process
2097 * Processes RX buffer descriptors - checks ownership bit on the RX buffer
2098 * descriptor, sends the receive packet to upper layer, allocates a new SKB
2099 * and recycles the buffer descriptor (requeues it in hardware RX queue).
2100 * Only "budget" number of packets are processed and indication of pending
2101 * packets provided to the caller.
2103 * Returns number of packets processed (and indication of pending packets)
2105 static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
2107 unsigned long flags;
2109 u32 pkts_processed = 0;
2111 struct emac_rx_bd __iomem *curr_bd;
2112 struct emac_rx_bd __iomem *last_bd;
2113 struct emac_netpktobj *curr_pkt, pkt_obj;
2114 struct emac_netbufobj buf_obj;
2115 struct emac_netbufobj *rx_buf_obj;
2116 void *new_buf_token;
2117 struct emac_rxch *rxch = priv->rxch[ch];
2119 if (unlikely(1 == rxch->teardown_pending))
2122 spin_lock_irqsave(&priv->rx_lock, flags);
2123 pkt_obj.buf_list = &buf_obj;
2124 curr_pkt = &pkt_obj;
2125 curr_bd = rxch->active_queue_head;
2126 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2127 frame_status = curr_bd->mode;
2130 ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
2131 (pkts_processed < budget)) {
2133 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
2134 &new_buf_token, EMAC_DEF_RX_CH);
2135 if (unlikely(NULL == new_buffer)) {
2136 ++rxch->out_of_rx_buffers;
2137 goto end_emac_rx_bdproc;
2140 /* populate received packet data structure */
2141 rx_buf_obj = &curr_pkt->buf_list[0];
2142 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
2143 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
2144 rx_buf_obj->buf_token = curr_bd->buf_token;
2146 dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr,
2147 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
2150 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
2151 curr_pkt->num_bufs = 1;
2152 curr_pkt->pkt_length =
2153 (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
2154 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
2155 ++rxch->processed_bd;
2157 curr_bd = last_bd->next;
2158 rxch->active_queue_head = curr_bd;
2160 /* check if end of RX queue ? */
2161 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2163 ++rxch->mis_queued_packets;
2164 emac_write(EMAC_RXHDP(ch),
2165 emac_virt_to_phys(curr_bd, priv));
2167 ++rxch->end_of_queue;
2168 rxch->queue_active = 0;
2173 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2176 /* return the packet to the user - BD ptr passed in
2177 * last parameter for potential *future* use */
2178 spin_unlock_irqrestore(&priv->rx_lock, flags);
2179 emac_net_rx_cb(priv, curr_pkt);
2180 spin_lock_irqsave(&priv->rx_lock, flags);
2181 curr_bd = rxch->active_queue_head;
2183 BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2184 frame_status = curr_bd->mode;
2190 spin_unlock_irqrestore(&priv->rx_lock, flags);
2191 return pkts_processed;
2195 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2196 * @priv: The DaVinci EMAC private adapter structure
2198 * Enables EMAC hardware for packet processing - enables PHY, enables RX
2199 * for packet reception and enables device interrupts and then NAPI
2201 * Returns success (0) or appropriate error code (none right now)
2203 static int emac_hw_enable(struct emac_priv *priv)
2205 u32 val, mbp_enable, mac_control;
2208 emac_write(EMAC_SOFTRESET, 1);
2209 while (emac_read(EMAC_SOFTRESET))
2212 /* Disable interrupt & Set pacing for more interrupts initially */
2213 emac_int_disable(priv);
2215 /* Full duplex enable bit set when auto negotiation happens */
2217 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2218 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2219 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2220 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2221 emac_write(EMAC_MACCONTROL, mac_control);
2224 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2225 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2226 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2227 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2228 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2229 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2230 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2231 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2232 EMAC_RXMBP_PROMCH_SHIFT) |
2233 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2234 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2235 EMAC_RXMBP_BROADCH_SHIFT) |
2236 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2237 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2238 EMAC_RXMBP_MULTICH_SHIFT));
2239 emac_write(EMAC_RXMBPENABLE, mbp_enable);
2240 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2241 EMAC_RX_MAX_LEN_MASK));
2242 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2243 EMAC_RX_BUFFER_OFFSET_MASK));
2244 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2245 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2246 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2248 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2250 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2253 val = emac_read(EMAC_MACCONTROL);
2254 val |= (EMAC_MACCONTROL_GMIIEN);
2255 emac_write(EMAC_MACCONTROL, val);
2257 /* Enable NAPI and interrupts */
2258 napi_enable(&priv->napi);
2259 emac_int_enable(priv);
2265 * emac_poll: EMAC NAPI Poll function
2266 * @ndev: The DaVinci EMAC network adapter
2267 * @budget: Number of receive packets to process (as told by NAPI layer)
2269 * NAPI Poll function implemented to process packets as per budget. We check
2270 * the type of interrupt on the device and accordingly call the TX or RX
2271 * packet processing functions. We follow the budget for RX processing and
2272 * also put a cap on number of TX pkts processed through config param. The
2273 * NAPI schedule function is called if more packets pending.
2275 * Returns number of packets received (in most cases; else TX pkts - rarely)
2277 static int emac_poll(struct napi_struct *napi, int budget)
2280 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2281 struct net_device *ndev = priv->ndev;
2282 struct device *emac_dev = &ndev->dev;
2284 u32 num_tx_pkts = 0, num_rx_pkts = 0;
2286 /* Check interrupt vectors and call packet processing */
2287 status = emac_read(EMAC_MACINVECTOR);
2289 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2291 if (priv->version == EMAC_VERSION_2)
2292 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2294 if (status & mask) {
2295 num_tx_pkts = cpdma_chan_process(priv->txchan,
2296 EMAC_DEF_TX_MAX_SERVICE);
2297 } /* TX processing */
2299 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2301 if (priv->version == EMAC_VERSION_2)
2302 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2304 if (status & mask) {
2305 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
2306 } /* RX processing */
2308 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2309 if (priv->version == EMAC_VERSION_2)
2310 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2312 if (unlikely(status & mask)) {
2314 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2315 netif_stop_queue(ndev);
2316 napi_disable(&priv->napi);
2318 status = emac_read(EMAC_MACSTATUS);
2319 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2320 EMAC_MACSTATUS_TXERRCODE_SHIFT);
2322 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2323 EMAC_MACSTATUS_TXERRCH_SHIFT);
2324 if (net_ratelimit()) {
2325 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2326 &emac_txhost_errcodes[cause][0], ch);
2329 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2330 EMAC_MACSTATUS_RXERRCODE_SHIFT);
2332 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2333 EMAC_MACSTATUS_RXERRCH_SHIFT);
2334 if (netif_msg_hw(priv) && net_ratelimit())
2335 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2336 &emac_rxhost_errcodes[cause][0], ch);
2338 } else if (num_rx_pkts < budget) {
2339 napi_complete(napi);
2340 emac_int_enable(priv);
2346 #ifdef CONFIG_NET_POLL_CONTROLLER
2348 * emac_poll_controller: EMAC Poll controller function
2349 * @ndev: The DaVinci EMAC network adapter
2351 * Polled functionality used by netconsole and others in non interrupt mode
2354 void emac_poll_controller(struct net_device *ndev)
2356 struct emac_priv *priv = netdev_priv(ndev);
2358 emac_int_disable(priv);
2359 emac_irq(ndev->irq, ndev);
2360 emac_int_enable(priv);
2364 static void emac_adjust_link(struct net_device *ndev)
2366 struct emac_priv *priv = netdev_priv(ndev);
2367 struct phy_device *phydev = priv->phydev;
2368 unsigned long flags;
2371 spin_lock_irqsave(&priv->lock, flags);
2374 /* check the mode of operation - full/half duplex */
2375 if (phydev->duplex != priv->duplex) {
2377 priv->duplex = phydev->duplex;
2379 if (phydev->speed != priv->speed) {
2381 priv->speed = phydev->speed;
2388 } else if (priv->link) {
2395 emac_update_phystatus(priv);
2396 phy_print_status(priv->phydev);
2399 spin_unlock_irqrestore(&priv->lock, flags);
2402 /*************************************************************************
2403 * Linux Driver Model
2404 *************************************************************************/
2407 * emac_devioctl: EMAC adapter ioctl
2408 * @ndev: The DaVinci EMAC network adapter
2409 * @ifrq: request parameter
2410 * @cmd: command parameter
2412 * EMAC driver ioctl function
2414 * Returns success(0) or appropriate error code
2416 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2418 dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2420 if (!(netif_running(ndev)))
2423 /* TODO: Add phy read and write and private statistics get feature */
2428 static int match_first_device(struct device *dev, void *data)
2434 * emac_dev_open: EMAC device open
2435 * @ndev: The DaVinci EMAC network adapter
2437 * Called when system wants to start the interface. We init TX/RX channels
2438 * and enable the hardware for packet reception/transmission and start the
2441 * Returns 0 for a successful open, or appropriate error code
2443 static int emac_dev_open(struct net_device *ndev)
2445 struct device *emac_dev = &ndev->dev;
2447 struct resource *res;
2451 struct emac_priv *priv = netdev_priv(ndev);
2453 netif_carrier_off(ndev);
2454 for (cnt = 0; cnt < ETH_ALEN; cnt++)
2455 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2457 /* Configuration items */
2458 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2460 priv->mac_hash1 = 0;
2461 priv->mac_hash2 = 0;
2462 emac_write(EMAC_MACHASH1, 0);
2463 emac_write(EMAC_MACHASH2, 0);
2465 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
2466 struct sk_buff *skb = emac_rx_alloc(priv);
2471 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
2472 skb_tailroom(skb), GFP_KERNEL);
2473 if (WARN_ON(ret < 0))
2479 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2480 for (i = res->start; i <= res->end; i++) {
2481 if (request_irq(i, emac_irq, IRQF_DISABLED,
2488 /* Start/Enable EMAC hardware */
2489 emac_hw_enable(priv);
2491 /* Enable Interrupt pacing if configured */
2492 if (priv->coal_intvl != 0) {
2493 struct ethtool_coalesce coal;
2495 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
2496 emac_set_coalesce(ndev, &coal);
2499 cpdma_ctlr_start(priv->dma);
2501 priv->phydev = NULL;
2502 /* use the first phy on the bus if pdata did not give us a phy id */
2503 if (!priv->phy_id) {
2506 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
2507 match_first_device);
2509 priv->phy_id = dev_name(phy);
2512 if (priv->phy_id && *priv->phy_id) {
2513 priv->phydev = phy_connect(ndev, priv->phy_id,
2514 &emac_adjust_link, 0,
2515 PHY_INTERFACE_MODE_MII);
2517 if (IS_ERR(priv->phydev)) {
2518 dev_err(emac_dev, "could not connect to phy %s\n",
2520 priv->phydev = NULL;
2521 return PTR_ERR(priv->phydev);
2528 dev_info(emac_dev, "attached PHY driver [%s] "
2529 "(mii_bus:phy_addr=%s, id=%x)\n",
2530 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2531 priv->phydev->phy_id);
2533 /* No PHY , fix the link, speed and duplex settings */
2534 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
2536 priv->speed = SPEED_100;
2537 priv->duplex = DUPLEX_FULL;
2538 emac_update_phystatus(priv);
2541 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2542 emac_dump_regs(priv);
2544 if (netif_msg_drv(priv))
2545 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2548 phy_start(priv->phydev);
2554 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2556 for (q = k; k >= 0; k--) {
2557 for (m = i; m >= res->start; m--)
2559 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2566 * emac_dev_stop: EMAC device stop
2567 * @ndev: The DaVinci EMAC network adapter
2569 * Called when system wants to stop or down the interface. We stop the network
2570 * queue, disable interrupts and cleanup TX/RX channels.
2572 * We return the statistics in net_device_stats structure pulled from emac
2574 static int emac_dev_stop(struct net_device *ndev)
2576 struct resource *res;
2579 struct emac_priv *priv = netdev_priv(ndev);
2580 struct device *emac_dev = &ndev->dev;
2582 /* inform the upper layers. */
2583 netif_stop_queue(ndev);
2584 napi_disable(&priv->napi);
2586 netif_carrier_off(ndev);
2587 emac_int_disable(priv);
2588 cpdma_ctlr_stop(priv->dma);
2589 emac_write(EMAC_SOFTRESET, 1);
2592 phy_disconnect(priv->phydev);
2595 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2596 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2597 free_irq(irq_num, priv->ndev);
2601 if (netif_msg_drv(priv))
2602 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2608 * emac_dev_getnetstats: EMAC get statistics function
2609 * @ndev: The DaVinci EMAC network adapter
2611 * Called when system wants to get statistics from the device.
2613 * We return the statistics in net_device_stats structure pulled from emac
2615 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2617 struct emac_priv *priv = netdev_priv(ndev);
2619 u32 stats_clear_mask;
2621 /* update emac hardware stats and reset the registers*/
2623 mac_control = emac_read(EMAC_MACCONTROL);
2625 if (mac_control & EMAC_MACCONTROL_GMIIEN)
2626 stats_clear_mask = EMAC_STATS_CLR_MASK;
2628 stats_clear_mask = 0;
2630 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2631 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2633 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2634 emac_read(EMAC_TXSINGLECOLL) +
2635 emac_read(EMAC_TXMULTICOLL));
2636 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2637 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2638 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2640 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2641 emac_read(EMAC_RXJABBER) +
2642 emac_read(EMAC_RXUNDERSIZED));
2643 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2644 emac_write(EMAC_RXJABBER, stats_clear_mask);
2645 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2647 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2648 emac_read(EMAC_RXMOFOVERRUNS));
2649 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2650 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2652 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2653 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2655 ndev->stats.tx_carrier_errors +=
2656 emac_read(EMAC_TXCARRIERSENSE);
2657 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2659 ndev->stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2660 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2662 return &ndev->stats;
2665 static const struct net_device_ops emac_netdev_ops = {
2666 .ndo_open = emac_dev_open,
2667 .ndo_stop = emac_dev_stop,
2668 .ndo_start_xmit = emac_dev_xmit,
2669 .ndo_set_multicast_list = emac_dev_mcast_set,
2670 .ndo_set_mac_address = emac_dev_setmac_addr,
2671 .ndo_do_ioctl = emac_devioctl,
2672 .ndo_tx_timeout = emac_dev_tx_timeout,
2673 .ndo_get_stats = emac_dev_getnetstats,
2674 #ifdef CONFIG_NET_POLL_CONTROLLER
2675 .ndo_poll_controller = emac_poll_controller,
2680 * davinci_emac_probe: EMAC device probe
2681 * @pdev: The DaVinci EMAC device that we are removing
2683 * Called when probing for emac devicesr. We get details of instances and
2684 * resource information from platform init and register a network device
2685 * and allocate resources necessary for driver to perform
2687 static int __devinit davinci_emac_probe(struct platform_device *pdev)
2690 struct resource *res;
2691 struct net_device *ndev;
2692 struct emac_priv *priv;
2693 unsigned long size, hw_ram_addr;
2694 struct emac_platform_data *pdata;
2695 struct device *emac_dev;
2696 struct cpdma_params dma_params;
2698 /* obtain emac clock from kernel */
2699 emac_clk = clk_get(&pdev->dev, NULL);
2700 if (IS_ERR(emac_clk)) {
2701 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2704 emac_bus_frequency = clk_get_rate(emac_clk);
2705 /* TODO: Probe PHY here if possible */
2707 ndev = alloc_etherdev(sizeof(struct emac_priv));
2709 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2714 platform_set_drvdata(pdev, ndev);
2715 priv = netdev_priv(ndev);
2718 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2720 spin_lock_init(&priv->tx_lock);
2721 spin_lock_init(&priv->rx_lock);
2722 spin_lock_init(&priv->lock);
2724 pdata = pdev->dev.platform_data;
2726 printk(KERN_ERR "DaVinci EMAC: No platform data\n");
2730 /* MAC addr and PHY mask , RMII enable info from platform_data */
2731 memcpy(priv->mac_addr, pdata->mac_addr, 6);
2732 priv->phy_id = pdata->phy_id;
2733 priv->rmii_en = pdata->rmii_en;
2734 priv->version = pdata->version;
2735 priv->int_enable = pdata->interrupt_enable;
2736 priv->int_disable = pdata->interrupt_disable;
2738 priv->coal_intvl = 0;
2739 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
2741 emac_dev = &ndev->dev;
2742 /* Get EMAC platform data */
2743 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2745 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2750 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2751 size = res->end - res->start + 1;
2752 if (!request_mem_region(res->start, size, ndev->name)) {
2753 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n");
2758 priv->remap_addr = ioremap(res->start, size);
2759 if (!priv->remap_addr) {
2760 dev_err(emac_dev, "Unable to map IO\n");
2762 release_mem_region(res->start, size);
2765 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2766 ndev->base_addr = (unsigned long)priv->remap_addr;
2768 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2769 priv->ctrl_ram_size = pdata->ctrl_ram_size;
2770 priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2772 hw_ram_addr = pdata->hw_ram_addr;
2774 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
2776 memset(&dma_params, 0, sizeof(dma_params));
2777 dma_params.dev = emac_dev;
2778 dma_params.dmaregs = priv->emac_base;
2779 dma_params.rxthresh = priv->emac_base + 0x120;
2780 dma_params.rxfree = priv->emac_base + 0x140;
2781 dma_params.txhdp = priv->emac_base + 0x600;
2782 dma_params.rxhdp = priv->emac_base + 0x620;
2783 dma_params.txcp = priv->emac_base + 0x640;
2784 dma_params.rxcp = priv->emac_base + 0x660;
2785 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
2786 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
2787 dma_params.desc_mem_phys = hw_ram_addr;
2788 dma_params.desc_mem_size = pdata->ctrl_ram_size;
2789 dma_params.desc_align = 16;
2791 priv->dma = cpdma_ctlr_create(&dma_params);
2793 dev_err(emac_dev, "DaVinci EMAC: Error initializing DMA\n");
2798 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
2800 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
2802 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
2807 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2809 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2813 ndev->irq = res->start;
2815 if (!is_valid_ether_addr(priv->mac_addr)) {
2816 /* Use random MAC if none passed */
2817 random_ether_addr(priv->mac_addr);
2818 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2819 __func__, priv->mac_addr);
2822 ndev->netdev_ops = &emac_netdev_ops;
2823 SET_ETHTOOL_OPS(ndev, ðtool_ops);
2824 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2826 clk_enable(emac_clk);
2828 /* register the network device */
2829 SET_NETDEV_DEV(ndev, &pdev->dev);
2830 rc = register_netdev(ndev);
2832 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2834 goto netdev_reg_err;
2838 if (netif_msg_probe(priv)) {
2839 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2840 "(regs: %p, irq: %d)\n",
2841 (void *)priv->emac_base_phys, ndev->irq);
2846 clk_disable(emac_clk);
2849 cpdma_chan_destroy(priv->txchan);
2851 cpdma_chan_destroy(priv->rxchan);
2852 cpdma_ctlr_destroy(priv->dma);
2854 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2855 release_mem_region(res->start, res->end - res->start + 1);
2856 iounmap(priv->remap_addr);
2865 * davinci_emac_remove: EMAC device remove
2866 * @pdev: The DaVinci EMAC device that we are removing
2868 * Called when removing the device driver. We disable clock usage and release
2869 * the resources taken up by the driver and unregister network device
2871 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2873 struct resource *res;
2874 struct net_device *ndev = platform_get_drvdata(pdev);
2875 struct emac_priv *priv = netdev_priv(ndev);
2877 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2879 platform_set_drvdata(pdev, NULL);
2880 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2883 cpdma_chan_destroy(priv->txchan);
2885 cpdma_chan_destroy(priv->rxchan);
2886 cpdma_ctlr_destroy(priv->dma);
2888 release_mem_region(res->start, res->end - res->start + 1);
2890 unregister_netdev(ndev);
2891 iounmap(priv->remap_addr);
2894 clk_disable(emac_clk);
2900 static int davinci_emac_suspend(struct device *dev)
2902 struct platform_device *pdev = to_platform_device(dev);
2903 struct net_device *ndev = platform_get_drvdata(pdev);
2905 if (netif_running(ndev))
2906 emac_dev_stop(ndev);
2908 clk_disable(emac_clk);
2913 static int davinci_emac_resume(struct device *dev)
2915 struct platform_device *pdev = to_platform_device(dev);
2916 struct net_device *ndev = platform_get_drvdata(pdev);
2918 clk_enable(emac_clk);
2920 if (netif_running(ndev))
2921 emac_dev_open(ndev);
2926 static const struct dev_pm_ops davinci_emac_pm_ops = {
2927 .suspend = davinci_emac_suspend,
2928 .resume = davinci_emac_resume,
2932 * davinci_emac_driver: EMAC platform driver structure
2934 static struct platform_driver davinci_emac_driver = {
2936 .name = "davinci_emac",
2937 .owner = THIS_MODULE,
2938 .pm = &davinci_emac_pm_ops,
2940 .probe = davinci_emac_probe,
2941 .remove = __devexit_p(davinci_emac_remove),
2945 * davinci_emac_init: EMAC driver module init
2947 * Called when initializing the driver. We register the driver with
2950 static int __init davinci_emac_init(void)
2952 return platform_driver_register(&davinci_emac_driver);
2954 late_initcall(davinci_emac_init);
2957 * davinci_emac_exit: EMAC driver module exit
2959 * Called when exiting the driver completely. We unregister the driver with
2960 * the platform and exit
2962 static void __exit davinci_emac_exit(void)
2964 platform_driver_unregister(&davinci_emac_driver);
2966 module_exit(davinci_emac_exit);
2968 MODULE_LICENSE("GPL");
2969 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2970 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2971 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");