2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
28 #define MPU_MAILBOX_DB_OFFSET 0x160
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
32 #define MPU_EP_CONTROL 0
34 /********** MPU semphore ******************/
35 #define MPU_EP_SEMAPHORE_OFFSET 0xac
36 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
37 #define EP_SEMAPHORE_POST_ERR_MASK 0x1
38 #define EP_SEMAPHORE_POST_ERR_SHIFT 31
39 /* MPU semphore POST stage values */
40 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
41 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
42 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
43 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
45 /********* Memory BAR register ************/
46 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
47 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
48 * Disable" may still globally block interrupts in addition to individual
49 * interrupt masks; a mechanism for the device driver to block all interrupts
50 * atomically without having to arbitrate for the PCI Interrupt Disable bit
53 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
55 /********* Power managment (WOL) **********/
56 #define PCICFG_PM_CONTROL_OFFSET 0x44
57 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
59 /********* ISR0 Register offset **********/
60 #define CEV_ISR0_OFFSET 0xC18
61 #define CEV_ISR_SIZE 4
63 /********* Event Q door bell *************/
64 #define DB_EQ_OFFSET DB_CQ_OFFSET
65 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
66 /* Clear the interrupt for this eq */
67 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
69 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
70 /* Number of event entries processed */
71 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
73 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
75 /********* Compl Q door bell *************/
76 #define DB_CQ_OFFSET 0x120
77 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
78 /* Number of event entries processed */
79 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
81 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
83 /********** TX ULP door bell *************/
84 #define DB_TXULP1_OFFSET 0x60
85 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
86 /* Number of tx entries posted */
87 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
88 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
90 /********** RQ(erx) door bell ************/
91 #define DB_RQ_OFFSET 0x100
92 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
93 /* Number of rx frags posted */
94 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
96 /********** MCC door bell ************/
97 #define DB_MCCQ_OFFSET 0x140
98 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
99 /* Number of entries posted */
100 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
103 * BE descriptors: host memory data structures whose formats
104 * are hardwired in BE silicon.
106 /* Event Queue Descriptor */
107 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
108 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
109 #define EQ_ENTRY_RES_ID_SHIFT 16
114 /* TX Queue Descriptor */
115 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
117 u32 frag_pa_hi; /* dword 0 */
118 u32 frag_pa_lo; /* dword 1 */
119 u32 rsvd0; /* dword 2 */
120 u32 frag_len; /* dword 3: bits 0 - 15 */
123 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
124 * actual structure is defined as a byte : used to calculate
125 * offset/shift/mask of each field */
126 struct amap_eth_hdr_wrb {
127 u8 rsvd0[32]; /* dword 0 */
128 u8 rsvd1[32]; /* dword 1 */
129 u8 complete; /* dword 2 */
143 u8 len[16]; /* dword 3 */
147 struct be_eth_hdr_wrb {
151 /* TX Compl Queue Descriptor */
153 /* Pseudo amap definition for eth_tx_compl in which each bit of the
154 * actual structure is defined as a byte: used to calculate
155 * offset/shift/mask of each field */
156 struct amap_eth_tx_compl {
157 u8 wrb_index[16]; /* dword 0 */
158 u8 ct[2]; /* dword 0 */
159 u8 port[2]; /* dword 0 */
160 u8 rsvd0[8]; /* dword 0 */
161 u8 status[4]; /* dword 0 */
162 u8 user_bytes[16]; /* dword 1 */
163 u8 nwh_bytes[8]; /* dword 1 */
164 u8 lso; /* dword 1 */
165 u8 cast_enc[2]; /* dword 1 */
166 u8 rsvd1[5]; /* dword 1 */
167 u8 rsvd2[32]; /* dword 2 */
168 u8 pkts[16]; /* dword 3 */
169 u8 ringid[11]; /* dword 3 */
170 u8 hash_val[4]; /* dword 3 */
171 u8 valid; /* dword 3 */
174 struct be_eth_tx_compl {
178 /* RX Queue Descriptor */
184 /* RX Compl Queue Descriptor */
186 /* Pseudo amap definition for eth_rx_compl in which each bit of the
187 * actual structure is defined as a byte: used to calculate
188 * offset/shift/mask of each field */
189 struct amap_eth_rx_compl {
190 u8 vlan_tag[16]; /* dword 0 */
191 u8 pktsize[14]; /* dword 0 */
192 u8 port; /* dword 0 */
193 u8 ip_opt; /* dword 0 */
194 u8 err; /* dword 1 */
195 u8 rsshp; /* dword 1 */
196 u8 ipf; /* dword 1 */
197 u8 tcpf; /* dword 1 */
198 u8 udpf; /* dword 1 */
199 u8 ipcksm; /* dword 1 */
200 u8 l4_cksm; /* dword 1 */
201 u8 ip_version; /* dword 1 */
202 u8 macdst[6]; /* dword 1 */
203 u8 vtp; /* dword 1 */
204 u8 rsvd0; /* dword 1 */
205 u8 fragndx[10]; /* dword 1 */
206 u8 ct[2]; /* dword 1 */
208 u8 numfrags[3]; /* dword 1 */
209 u8 rss_flush; /* dword 2 */
210 u8 cast_enc[2]; /* dword 2 */
211 u8 vtm; /* dword 2 */
212 u8 rss_bank; /* dword 2 */
213 u8 rsvd1[23]; /* dword 2 */
214 u8 lro_pkt; /* dword 2 */
215 u8 rsvd2[2]; /* dword 2 */
216 u8 valid; /* dword 2 */
217 u8 rsshash[32]; /* dword 3 */
220 struct be_eth_rx_compl {
224 /* Flashrom related descriptors */
225 #define IMAGE_TYPE_FIRMWARE 160
226 #define IMAGE_TYPE_BOOTCODE 224
227 #define IMAGE_TYPE_OPTIONROM 32
229 #define NUM_FLASHDIR_ENTRIES 32
231 #define FLASHROM_TYPE_ISCSI_ACTIVE 0
232 #define FLASHROM_TYPE_REDBOOT 1
233 #define FLASHROM_TYPE_BIOS 2
234 #define FLASHROM_TYPE_PXE_BIOS 3
235 #define FLASHROM_TYPE_FCOE_BIOS 8
236 #define FLASHROM_TYPE_ISCSI_BACKUP 9
237 #define FLASHROM_TYPE_FCOE_FW_ACTIVE 10
238 #define FLASHROM_TYPE_FCOE_FW_BACKUP 11
240 #define FLASHROM_OPER_FLASH 1
241 #define FLASHROM_OPER_SAVE 2
242 #define FLASHROM_OPER_REPORT 4
244 #define FLASH_IMAGE_MAX_SIZE (1310720) /* Max firmware image size */
245 #define FLASH_BIOS_IMAGE_MAX_SIZE (262144) /* Max OPTION ROM image sz */
246 #define FLASH_REDBOOT_IMAGE_MAX_SIZE (262144) /* Max redboot image sz */
248 /* Offsets for components on Flash. */
249 #define FLASH_iSCSI_PRIMARY_IMAGE_START (1048576)
250 #define FLASH_iSCSI_BACKUP_IMAGE_START (2359296)
251 #define FLASH_FCoE_PRIMARY_IMAGE_START (3670016)
252 #define FLASH_FCoE_BACKUP_IMAGE_START (4980736)
253 #define FLASH_iSCSI_BIOS_START (7340032)
254 #define FLASH_PXE_BIOS_START (7864320)
255 #define FLASH_FCoE_BIOS_START (524288)
256 #define FLASH_REDBOOT_START (32768)
257 #define FLASH_REDBOOT_ISM_START (0)
259 struct controller_id {
266 struct flash_file_hdr {
270 struct controller_id cont_id;
278 struct flash_section_hdr {
284 u32 active_entry_mask;
285 u32 valid_entry_mask;
286 u32 org_content_mask;
294 struct flash_section_entry {
306 struct flash_section_info {
308 struct flash_section_hdr fsec_hdr;
309 struct flash_section_entry fsec_entry[32];