drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 static void be_mcc_notify(struct be_adapter *adapter)
  22 {
  23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  24         u32 val = 0;
  25
  26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  28         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  29 }
  30
  31 /* To check if valid bit is set, check the entire word as we don't know
  32  * the endianness of the data (old entry is host endian while a new entry is
  33  * little endian) */
  34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  35 {
  36         if (compl->flags != 0) {
  37                 compl->flags = le32_to_cpu(compl->flags);
  38                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  39                 return true;
  40         } else {
  41                 return false;
  42         }
  43 }
  44
  45 /* Need to reset the entire word that houses the valid bit */
  46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  47 {
  48         compl->flags = 0;
  49 }
  50
  51 static int be_mcc_compl_process(struct be_adapter *adapter,
  52         struct be_mcc_compl *compl)
  53 {
  54         u16 compl_status, extd_status;
  55
  56         /* Just swap the status to host endian; mcc tag is opaquely copied
  57          * from mcc_wrb */
  58         be_dws_le_to_cpu(compl, 4);
  59
  60         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  61                                 CQE_STATUS_COMPL_MASK;
  62         if (compl_status == MCC_STATUS_SUCCESS) {
  63                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
  64                         struct be_cmd_resp_get_stats *resp =
  65                                                 adapter->stats.cmd.va;
  66                         be_dws_le_to_cpu(&resp->hw_stats,
  67                                                 sizeof(resp->hw_stats));
  68                         netdev_stats_update(adapter);
  69                 }
  70         } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
  71                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
  72                                 CQE_STATUS_EXTD_MASK;
  73                 dev_warn(&adapter->pdev->dev,
  74                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
  75                         compl->tag0, compl_status, extd_status);
  76         }
  77         return compl_status;
  78 }
  79
  80 /* Link state evt is a string of bytes; no need for endian swapping */
  81 static void be_async_link_state_process(struct be_adapter *adapter,
  82                 struct be_async_event_link_state *evt)
  83 {
  84         be_link_status_update(adapter,
  85                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
  86 }
  87
  88 static inline bool is_link_state_evt(u32 trailer)
  89 {
  90         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
  91                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
  92                                 ASYNC_EVENT_CODE_LINK_STATE);
  93 }
  94
  95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
  96 {
  97         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
  98         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
  99
 100         if (be_mcc_compl_is_new(compl)) {
 101                 queue_tail_inc(mcc_cq);
 102                 return compl;
 103         }
 104         return NULL;
 105 }
 106
 107 int be_process_mcc(struct be_adapter *adapter)
 108 {
 109         struct be_mcc_compl *compl;
 110         int num = 0, status = 0;
 111
 112         spin_lock_bh(&adapter->mcc_cq_lock);
 113         while ((compl = be_mcc_compl_get(adapter))) {
 114                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 115                         /* Interpret flags as an async trailer */
 116                         BUG_ON(!is_link_state_evt(compl->flags));
 117
 118                         /* Interpret compl as a async link evt */
 119                         be_async_link_state_process(adapter,
 120                                 (struct be_async_event_link_state *) compl);
 121                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 122                                 status = be_mcc_compl_process(adapter, compl);
 123                                 atomic_dec(&adapter->mcc_obj.q.used);
 124                 }
 125                 be_mcc_compl_use(compl);
 126                 num++;
 127         }
 128
 129         if (num)
 130                 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, num);
 131
 132         spin_unlock_bh(&adapter->mcc_cq_lock);
 133         return status;
 134 }
 135
 136 /* Wait till no more pending mcc requests are present */
 137 static int be_mcc_wait_compl(struct be_adapter *adapter)
 138 {
 139 #define mcc_timeout             120000 /* 12s timeout */
 140         int i, status;
 141         for (i = 0; i < mcc_timeout; i++) {
 142                 status = be_process_mcc(adapter);
 143                 if (status)
 144                         return status;
 145
 146                 if (atomic_read(&adapter->mcc_obj.q.used) == 0)
 147                         break;
 148                 udelay(100);
 149         }
 150         if (i == mcc_timeout) {
 151                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 152                 return -1;
 153         }
 154         return 0;
 155 }
 156
 157 /* Notify MCC requests and wait for completion */
 158 static int be_mcc_notify_wait(struct be_adapter *adapter)
 159 {
 160         be_mcc_notify(adapter);
 161         return be_mcc_wait_compl(adapter);
 162 }
 163
 164 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 165 {
 166         int cnt = 0, wait = 5;
 167         u32 ready;
 168
 169         do {
 170                 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
 171                 if (ready)
 172                         break;
 173
 174                 if (cnt > 4000000) {
 175                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 176                         return -1;
 177                 }
 178
 179                 if (cnt > 50)
 180                         wait = 200;
 181                 cnt += wait;
 182                 udelay(wait);
 183         } while (true);
 184
 185         return 0;
 186 }
 187
 188 /*
 189  * Insert the mailbox address into the doorbell in two steps
 190  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 191  */
 192 static int be_mbox_notify_wait(struct be_adapter *adapter)
 193 {
 194         int status;
 195         u32 val = 0;
 196         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 197         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 198         struct be_mcc_mailbox *mbox = mbox_mem->va;
 199         struct be_mcc_compl *compl = &mbox->compl;
 200
 201         val |= MPU_MAILBOX_DB_HI_MASK;
 202         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 203         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 204         iowrite32(val, db);
 205
 206         /* wait for ready to be set */
 207         status = be_mbox_db_ready_wait(adapter, db);
 208         if (status != 0)
 209                 return status;
 210
 211         val = 0;
 212         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 213         val |= (u32)(mbox_mem->dma >> 4) << 2;
 214         iowrite32(val, db);
 215
 216         status = be_mbox_db_ready_wait(adapter, db);
 217         if (status != 0)
 218                 return status;
 219
 220         /* A cq entry has been made now */
 221         if (be_mcc_compl_is_new(compl)) {
 222                 status = be_mcc_compl_process(adapter, &mbox->compl);
 223                 be_mcc_compl_use(compl);
 224                 if (status)
 225                         return status;
 226         } else {
 227                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 228                 return -1;
 229         }
 230         return 0;
 231 }
 232
 233 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 234 {
 235         u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 236
 237         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 238         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 239                 return -1;
 240         else
 241                 return 0;
 242 }
 243
 244 int be_cmd_POST(struct be_adapter *adapter)
 245 {
 246         u16 stage;
 247         int status, timeout = 0;
 248
 249         do {
 250                 status = be_POST_stage_get(adapter, &stage);
 251                 if (status) {
 252                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
 253                                 stage);
 254                         return -1;
 255                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 256                         set_current_state(TASK_INTERRUPTIBLE);
 257                         schedule_timeout(2 * HZ);
 258                         timeout += 2;
 259                 } else {
 260                         return 0;
 261                 }
 262         } while (timeout < 20);
 263
 264         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
 265         return -1;
 266 }
 267
 268 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 269 {
 270         return wrb->payload.embedded_payload;
 271 }
 272
 273 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 274 {
 275         return &wrb->payload.sgl[0];
 276 }
 277
 278 /* Don't touch the hdr after it's prepared */
 279 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 280                                 bool embedded, u8 sge_cnt, u32 opcode)
 281 {
 282         if (embedded)
 283                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 284         else
 285                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 286                                 MCC_WRB_SGE_CNT_SHIFT;
 287         wrb->payload_length = payload_len;
 288         wrb->tag0 = opcode;
 289         be_dws_cpu_to_le(wrb, 8);
 290 }
 291
 292 /* Don't touch the hdr after it's prepared */
 293 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 294                                 u8 subsystem, u8 opcode, int cmd_len)
 295 {
 296         req_hdr->opcode = opcode;
 297         req_hdr->subsystem = subsystem;
 298         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 299         req_hdr->version = 0;
 300 }
 301
 302 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 303                         struct be_dma_mem *mem)
 304 {
 305         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 306         u64 dma = (u64)mem->dma;
 307
 308         for (i = 0; i < buf_pages; i++) {
 309                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 310                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 311                 dma += PAGE_SIZE_4K;
 312         }
 313 }
 314
 315 /* Converts interrupt delay in microseconds to multiplier value */
 316 static u32 eq_delay_to_mult(u32 usec_delay)
 317 {
 318 #define MAX_INTR_RATE                   651042
 319         const u32 round = 10;
 320         u32 multiplier;
 321
 322         if (usec_delay == 0)
 323                 multiplier = 0;
 324         else {
 325                 u32 interrupt_rate = 1000000 / usec_delay;
 326                 /* Max delay, corresponding to the lowest interrupt rate */
 327                 if (interrupt_rate == 0)
 328                         multiplier = 1023;
 329                 else {
 330                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 331                         multiplier /= interrupt_rate;
 332                         /* Round the multiplier to the closest value.*/
 333                         multiplier = (multiplier + round/2) / round;
 334                         multiplier = min(multiplier, (u32)1023);
 335                 }
 336         }
 337         return multiplier;
 338 }
 339
 340 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 341 {
 342         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 343         struct be_mcc_wrb *wrb
 344                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 345         memset(wrb, 0, sizeof(*wrb));
 346         return wrb;
 347 }
 348
 349 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 350 {
 351         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 352         struct be_mcc_wrb *wrb;
 353
 354         if (atomic_read(&mccq->used) >= mccq->len) {
 355                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 356                 return NULL;
 357         }
 358
 359         wrb = queue_head_node(mccq);
 360         queue_head_inc(mccq);
 361         atomic_inc(&mccq->used);
 362         memset(wrb, 0, sizeof(*wrb));
 363         return wrb;
 364 }
 365
 366 /* Tell fw we're about to start firing cmds by writing a
 367  * special pattern across the wrb hdr; uses mbox
 368  */
 369 int be_cmd_fw_init(struct be_adapter *adapter)
 370 {
 371         u8 *wrb;
 372         int status;
 373
 374         spin_lock(&adapter->mbox_lock);
 375
 376         wrb = (u8 *)wrb_from_mbox(adapter);
 377         *wrb++ = 0xFF;
 378         *wrb++ = 0x12;
 379         *wrb++ = 0x34;
 380         *wrb++ = 0xFF;
 381         *wrb++ = 0xFF;
 382         *wrb++ = 0x56;
 383         *wrb++ = 0x78;
 384         *wrb = 0xFF;
 385
 386         status = be_mbox_notify_wait(adapter);
 387
 388         spin_unlock(&adapter->mbox_lock);
 389         return status;
 390 }
 391
 392 /* Tell fw we're done with firing cmds by writing a
 393  * special pattern across the wrb hdr; uses mbox
 394  */
 395 int be_cmd_fw_clean(struct be_adapter *adapter)
 396 {
 397         u8 *wrb;
 398         int status;
 399
 400         spin_lock(&adapter->mbox_lock);
 401
 402         wrb = (u8 *)wrb_from_mbox(adapter);
 403         *wrb++ = 0xFF;
 404         *wrb++ = 0xAA;
 405         *wrb++ = 0xBB;
 406         *wrb++ = 0xFF;
 407         *wrb++ = 0xFF;
 408         *wrb++ = 0xCC;
 409         *wrb++ = 0xDD;
 410         *wrb = 0xFF;
 411
 412         status = be_mbox_notify_wait(adapter);
 413
 414         spin_unlock(&adapter->mbox_lock);
 415         return status;
 416 }
 417 int be_cmd_eq_create(struct be_adapter *adapter,
 418                 struct be_queue_info *eq, int eq_delay)
 419 {
 420         struct be_mcc_wrb *wrb;
 421         struct be_cmd_req_eq_create *req;
 422         struct be_dma_mem *q_mem = &eq->dma_mem;
 423         int status;
 424
 425         spin_lock(&adapter->mbox_lock);
 426
 427         wrb = wrb_from_mbox(adapter);
 428         req = embedded_payload(wrb);
 429
 430         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 431
 432         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 433                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 434
 435         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 436
 437         AMAP_SET_BITS(struct amap_eq_context, func, req->context,
 438                         be_pci_func(adapter));
 439         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 440         /* 4byte eqe*/
 441         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 442         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 443                         __ilog2_u32(eq->len/256));
 444         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 445                         eq_delay_to_mult(eq_delay));
 446         be_dws_cpu_to_le(req->context, sizeof(req->context));
 447
 448         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 449
 450         status = be_mbox_notify_wait(adapter);
 451         if (!status) {
 452                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 453                 eq->id = le16_to_cpu(resp->eq_id);
 454                 eq->created = true;
 455         }
 456
 457         spin_unlock(&adapter->mbox_lock);
 458         return status;
 459 }
 460
 461 /* Uses mbox */
 462 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 463                         u8 type, bool permanent, u32 if_handle)
 464 {
 465         struct be_mcc_wrb *wrb;
 466         struct be_cmd_req_mac_query *req;
 467         int status;
 468
 469         spin_lock(&adapter->mbox_lock);
 470
 471         wrb = wrb_from_mbox(adapter);
 472         req = embedded_payload(wrb);
 473
 474         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 475                         OPCODE_COMMON_NTWK_MAC_QUERY);
 476
 477         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 478                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 479
 480         req->type = type;
 481         if (permanent) {
 482                 req->permanent = 1;
 483         } else {
 484                 req->if_id = cpu_to_le16((u16) if_handle);
 485                 req->permanent = 0;
 486         }
 487
 488         status = be_mbox_notify_wait(adapter);
 489         if (!status) {
 490                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 491                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 492         }
 493
 494         spin_unlock(&adapter->mbox_lock);
 495         return status;
 496 }
 497
 498 /* Uses synchronous MCCQ */
 499 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 500                 u32 if_id, u32 *pmac_id)
 501 {
 502         struct be_mcc_wrb *wrb;
 503         struct be_cmd_req_pmac_add *req;
 504         int status;
 505
 506         spin_lock_bh(&adapter->mcc_lock);
 507
 508         wrb = wrb_from_mccq(adapter);
 509         if (!wrb) {
 510                 status = -EBUSY;
 511                 goto err;
 512         }
 513         req = embedded_payload(wrb);
 514
 515         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 516                         OPCODE_COMMON_NTWK_PMAC_ADD);
 517
 518         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 519                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 520
 521         req->if_id = cpu_to_le32(if_id);
 522         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 523
 524         status = be_mcc_notify_wait(adapter);
 525         if (!status) {
 526                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 527                 *pmac_id = le32_to_cpu(resp->pmac_id);
 528         }
 529
 530 err:
 531         spin_unlock_bh(&adapter->mcc_lock);
 532         return status;
 533 }
 534
 535 /* Uses synchronous MCCQ */
 536 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
 537 {
 538         struct be_mcc_wrb *wrb;
 539         struct be_cmd_req_pmac_del *req;
 540         int status;
 541
 542         spin_lock_bh(&adapter->mcc_lock);
 543
 544         wrb = wrb_from_mccq(adapter);
 545         if (!wrb) {
 546                 status = -EBUSY;
 547                 goto err;
 548         }
 549         req = embedded_payload(wrb);
 550
 551         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 552                         OPCODE_COMMON_NTWK_PMAC_DEL);
 553
 554         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 555                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 556
 557         req->if_id = cpu_to_le32(if_id);
 558         req->pmac_id = cpu_to_le32(pmac_id);
 559
 560         status = be_mcc_notify_wait(adapter);
 561
 562 err:
 563         spin_unlock_bh(&adapter->mcc_lock);
 564         return status;
 565 }
 566
 567 /* Uses Mbox */
 568 int be_cmd_cq_create(struct be_adapter *adapter,
 569                 struct be_queue_info *cq, struct be_queue_info *eq,
 570                 bool sol_evts, bool no_delay, int coalesce_wm)
 571 {
 572         struct be_mcc_wrb *wrb;
 573         struct be_cmd_req_cq_create *req;
 574         struct be_dma_mem *q_mem = &cq->dma_mem;
 575         void *ctxt;
 576         int status;
 577
 578         spin_lock(&adapter->mbox_lock);
 579
 580         wrb = wrb_from_mbox(adapter);
 581         req = embedded_payload(wrb);
 582         ctxt = &req->context;
 583
 584         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 585                         OPCODE_COMMON_CQ_CREATE);
 586
 587         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 588                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 589
 590         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 591
 592         AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
 593         AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
 594         AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
 595                         __ilog2_u32(cq->len/256));
 596         AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
 597         AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
 598         AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
 599         AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
 600         AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
 601         AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter));
 602         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 603
 604         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 605
 606         status = be_mbox_notify_wait(adapter);
 607         if (!status) {
 608                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 609                 cq->id = le16_to_cpu(resp->cq_id);
 610                 cq->created = true;
 611         }
 612
 613         spin_unlock(&adapter->mbox_lock);
 614
 615         return status;
 616 }
 617
 618 static u32 be_encoded_q_len(int q_len)
 619 {
 620         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 621         if (len_encoded == 16)
 622                 len_encoded = 0;
 623         return len_encoded;
 624 }
 625
 626 int be_cmd_mccq_create(struct be_adapter *adapter,
 627                         struct be_queue_info *mccq,
 628                         struct be_queue_info *cq)
 629 {
 630         struct be_mcc_wrb *wrb;
 631         struct be_cmd_req_mcc_create *req;
 632         struct be_dma_mem *q_mem = &mccq->dma_mem;
 633         void *ctxt;
 634         int status;
 635
 636         spin_lock(&adapter->mbox_lock);
 637
 638         wrb = wrb_from_mbox(adapter);
 639         req = embedded_payload(wrb);
 640         ctxt = &req->context;
 641
 642         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 643                         OPCODE_COMMON_MCC_CREATE);
 644
 645         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 646                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
 647
 648         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 649
 650         AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter));
 651         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
 652         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
 653                 be_encoded_q_len(mccq->len));
 654         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
 655
 656         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 657
 658         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 659
 660         status = be_mbox_notify_wait(adapter);
 661         if (!status) {
 662                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 663                 mccq->id = le16_to_cpu(resp->id);
 664                 mccq->created = true;
 665         }
 666         spin_unlock(&adapter->mbox_lock);
 667
 668         return status;
 669 }
 670
 671 int be_cmd_txq_create(struct be_adapter *adapter,
 672                         struct be_queue_info *txq,
 673                         struct be_queue_info *cq)
 674 {
 675         struct be_mcc_wrb *wrb;
 676         struct be_cmd_req_eth_tx_create *req;
 677         struct be_dma_mem *q_mem = &txq->dma_mem;
 678         void *ctxt;
 679         int status;
 680
 681         spin_lock(&adapter->mbox_lock);
 682
 683         wrb = wrb_from_mbox(adapter);
 684         req = embedded_payload(wrb);
 685         ctxt = &req->context;
 686
 687         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 688                         OPCODE_ETH_TX_CREATE);
 689
 690         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 691                 sizeof(*req));
 692
 693         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 694         req->ulp_num = BE_ULP1_NUM;
 695         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 696
 697         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 698                 be_encoded_q_len(txq->len));
 699         AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
 700                         be_pci_func(adapter));
 701         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 702         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 703
 704         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 705
 706         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 707
 708         status = be_mbox_notify_wait(adapter);
 709         if (!status) {
 710                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 711                 txq->id = le16_to_cpu(resp->cid);
 712                 txq->created = true;
 713         }
 714
 715         spin_unlock(&adapter->mbox_lock);
 716
 717         return status;
 718 }
 719
 720 /* Uses mbox */
 721 int be_cmd_rxq_create(struct be_adapter *adapter,
 722                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 723                 u16 max_frame_size, u32 if_id, u32 rss)
 724 {
 725         struct be_mcc_wrb *wrb;
 726         struct be_cmd_req_eth_rx_create *req;
 727         struct be_dma_mem *q_mem = &rxq->dma_mem;
 728         int status;
 729
 730         spin_lock(&adapter->mbox_lock);
 731
 732         wrb = wrb_from_mbox(adapter);
 733         req = embedded_payload(wrb);
 734
 735         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 736                         OPCODE_ETH_RX_CREATE);
 737
 738         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 739                 sizeof(*req));
 740
 741         req->cq_id = cpu_to_le16(cq_id);
 742         req->frag_size = fls(frag_size) - 1;
 743         req->num_pages = 2;
 744         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 745         req->interface_id = cpu_to_le32(if_id);
 746         req->max_frame_size = cpu_to_le16(max_frame_size);
 747         req->rss_queue = cpu_to_le32(rss);
 748
 749         status = be_mbox_notify_wait(adapter);
 750         if (!status) {
 751                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 752                 rxq->id = le16_to_cpu(resp->id);
 753                 rxq->created = true;
 754         }
 755
 756         spin_unlock(&adapter->mbox_lock);
 757
 758         return status;
 759 }
 760
 761 /* Generic destroyer function for all types of queues
 762  * Uses Mbox
 763  */
 764 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 765                 int queue_type)
 766 {
 767         struct be_mcc_wrb *wrb;
 768         struct be_cmd_req_q_destroy *req;
 769         u8 subsys = 0, opcode = 0;
 770         int status;
 771
 772         spin_lock(&adapter->mbox_lock);
 773
 774         wrb = wrb_from_mbox(adapter);
 775         req = embedded_payload(wrb);
 776
 777         switch (queue_type) {
 778         case QTYPE_EQ:
 779                 subsys = CMD_SUBSYSTEM_COMMON;
 780                 opcode = OPCODE_COMMON_EQ_DESTROY;
 781                 break;
 782         case QTYPE_CQ:
 783                 subsys = CMD_SUBSYSTEM_COMMON;
 784                 opcode = OPCODE_COMMON_CQ_DESTROY;
 785                 break;
 786         case QTYPE_TXQ:
 787                 subsys = CMD_SUBSYSTEM_ETH;
 788                 opcode = OPCODE_ETH_TX_DESTROY;
 789                 break;
 790         case QTYPE_RXQ:
 791                 subsys = CMD_SUBSYSTEM_ETH;
 792                 opcode = OPCODE_ETH_RX_DESTROY;
 793                 break;
 794         case QTYPE_MCCQ:
 795                 subsys = CMD_SUBSYSTEM_COMMON;
 796                 opcode = OPCODE_COMMON_MCC_DESTROY;
 797                 break;
 798         default:
 799                 BUG();
 800         }
 801
 802         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
 803
 804         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
 805         req->id = cpu_to_le16(q->id);
 806
 807         status = be_mbox_notify_wait(adapter);
 808
 809         spin_unlock(&adapter->mbox_lock);
 810
 811         return status;
 812 }
 813
 814 /* Create an rx filtering policy configuration on an i/f
 815  * Uses mbox
 816  */
 817 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
 818                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
 819 {
 820         struct be_mcc_wrb *wrb;
 821         struct be_cmd_req_if_create *req;
 822         int status;
 823
 824         spin_lock(&adapter->mbox_lock);
 825
 826         wrb = wrb_from_mbox(adapter);
 827         req = embedded_payload(wrb);
 828
 829         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 830                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
 831
 832         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 833                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
 834
 835         req->capability_flags = cpu_to_le32(cap_flags);
 836         req->enable_flags = cpu_to_le32(en_flags);
 837         req->pmac_invalid = pmac_invalid;
 838         if (!pmac_invalid)
 839                 memcpy(req->mac_addr, mac, ETH_ALEN);
 840
 841         status = be_mbox_notify_wait(adapter);
 842         if (!status) {
 843                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
 844                 *if_handle = le32_to_cpu(resp->interface_id);
 845                 if (!pmac_invalid)
 846                         *pmac_id = le32_to_cpu(resp->pmac_id);
 847         }
 848
 849         spin_unlock(&adapter->mbox_lock);
 850         return status;
 851 }
 852
 853 /* Uses mbox */
 854 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
 855 {
 856         struct be_mcc_wrb *wrb;
 857         struct be_cmd_req_if_destroy *req;
 858         int status;
 859
 860         spin_lock(&adapter->mbox_lock);
 861
 862         wrb = wrb_from_mbox(adapter);
 863         req = embedded_payload(wrb);
 864
 865         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 866                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
 867
 868         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 869                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
 870
 871         req->interface_id = cpu_to_le32(interface_id);
 872
 873         status = be_mbox_notify_wait(adapter);
 874
 875         spin_unlock(&adapter->mbox_lock);
 876
 877         return status;
 878 }
 879
 880 /* Get stats is a non embedded command: the request is not embedded inside
 881  * WRB but is a separate dma memory block
 882  * Uses asynchronous MCC
 883  */
 884 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
 885 {
 886         struct be_mcc_wrb *wrb;
 887         struct be_cmd_req_get_stats *req;
 888         struct be_sge *sge;
 889         int status = 0;
 890
 891         spin_lock_bh(&adapter->mcc_lock);
 892
 893         wrb = wrb_from_mccq(adapter);
 894         if (!wrb) {
 895                 status = -EBUSY;
 896                 goto err;
 897         }
 898         req = nonemb_cmd->va;
 899         sge = nonembedded_sgl(wrb);
 900
 901         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
 902                         OPCODE_ETH_GET_STATISTICS);
 903
 904         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 905                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
 906         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
 907         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
 908         sge->len = cpu_to_le32(nonemb_cmd->size);
 909
 910         be_mcc_notify(adapter);
 911
 912 err:
 913         spin_unlock_bh(&adapter->mcc_lock);
 914         return status;
 915 }
 916
 917 /* Uses synchronous mcc */
 918 int be_cmd_link_status_query(struct be_adapter *adapter,
 919                         bool *link_up, u8 *mac_speed, u16 *link_speed)
 920 {
 921         struct be_mcc_wrb *wrb;
 922         struct be_cmd_req_link_status *req;
 923         int status;
 924
 925         spin_lock_bh(&adapter->mcc_lock);
 926
 927         wrb = wrb_from_mccq(adapter);
 928         if (!wrb) {
 929                 status = -EBUSY;
 930                 goto err;
 931         }
 932         req = embedded_payload(wrb);
 933
 934         *link_up = false;
 935
 936         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 937                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
 938
 939         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 940                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
 941
 942         status = be_mcc_notify_wait(adapter);
 943         if (!status) {
 944                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
 945                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
 946                         *link_up = true;
 947                         *link_speed = le16_to_cpu(resp->link_speed);
 948                         *mac_speed = resp->mac_speed;
 949                 }
 950         }
 951
 952 err:
 953         spin_unlock_bh(&adapter->mcc_lock);
 954         return status;
 955 }
 956
 957 /* Uses Mbox */
 958 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
 959 {
 960         struct be_mcc_wrb *wrb;
 961         struct be_cmd_req_get_fw_version *req;
 962         int status;
 963
 964         spin_lock(&adapter->mbox_lock);
 965
 966         wrb = wrb_from_mbox(adapter);
 967         req = embedded_payload(wrb);
 968
 969         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 970                         OPCODE_COMMON_GET_FW_VERSION);
 971
 972         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 973                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
 974
 975         status = be_mbox_notify_wait(adapter);
 976         if (!status) {
 977                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
 978                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
 979         }
 980
 981         spin_unlock(&adapter->mbox_lock);
 982         return status;
 983 }
 984
 985 /* set the EQ delay interval of an EQ to specified value
 986  * Uses async mcc
 987  */
 988 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
 989 {
 990         struct be_mcc_wrb *wrb;
 991         struct be_cmd_req_modify_eq_delay *req;
 992         int status = 0;
 993
 994         spin_lock_bh(&adapter->mcc_lock);
 995
 996         wrb = wrb_from_mccq(adapter);
 997         if (!wrb) {
 998                 status = -EBUSY;
 999                 goto err;
1000         }
1001         req = embedded_payload(wrb);
1002
1003         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1004                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1005
1006         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1007                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1008
1009         req->num_eq = cpu_to_le32(1);
1010         req->delay[0].eq_id = cpu_to_le32(eq_id);
1011         req->delay[0].phase = 0;
1012         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1013
1014         be_mcc_notify(adapter);
1015
1016 err:
1017         spin_unlock_bh(&adapter->mcc_lock);
1018         return status;
1019 }
1020
1021 /* Uses sycnhronous mcc */
1022 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1023                         u32 num, bool untagged, bool promiscuous)
1024 {
1025         struct be_mcc_wrb *wrb;
1026         struct be_cmd_req_vlan_config *req;
1027         int status;
1028
1029         spin_lock_bh(&adapter->mcc_lock);
1030
1031         wrb = wrb_from_mccq(adapter);
1032         if (!wrb) {
1033                 status = -EBUSY;
1034                 goto err;
1035         }
1036         req = embedded_payload(wrb);
1037
1038         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1039                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1040
1041         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1042                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1043
1044         req->interface_id = if_id;
1045         req->promiscuous = promiscuous;
1046         req->untagged = untagged;
1047         req->num_vlan = num;
1048         if (!promiscuous) {
1049                 memcpy(req->normal_vlan, vtag_array,
1050                         req->num_vlan * sizeof(vtag_array[0]));
1051         }
1052
1053         status = be_mcc_notify_wait(adapter);
1054
1055 err:
1056         spin_unlock_bh(&adapter->mcc_lock);
1057         return status;
1058 }
1059
1060 /* Uses MCC for this command as it may be called in BH context
1061  * Uses synchronous mcc
1062  */
1063 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1064 {
1065         struct be_mcc_wrb *wrb;
1066         struct be_cmd_req_promiscuous_config *req;
1067         int status;
1068
1069         spin_lock_bh(&adapter->mcc_lock);
1070
1071         wrb = wrb_from_mccq(adapter);
1072         if (!wrb) {
1073                 status = -EBUSY;
1074                 goto err;
1075         }
1076         req = embedded_payload(wrb);
1077
1078         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1079
1080         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1081                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1082
1083         if (port_num)
1084                 req->port1_promiscuous = en;
1085         else
1086                 req->port0_promiscuous = en;
1087
1088         status = be_mcc_notify_wait(adapter);
1089
1090 err:
1091         spin_unlock_bh(&adapter->mcc_lock);
1092         return status;
1093 }
1094
1095 /*
1096  * Uses MCC for this command as it may be called in BH context
1097  * (mc == NULL) => multicast promiscous
1098  */
1099 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1100                 struct dev_mc_list *mc_list, u32 mc_count,
1101                 struct be_dma_mem *mem)
1102 {
1103         struct be_mcc_wrb *wrb;
1104         struct be_cmd_req_mcast_mac_config *req = mem->va;
1105         struct be_sge *sge;
1106         int status;
1107
1108         spin_lock_bh(&adapter->mcc_lock);
1109
1110         wrb = wrb_from_mccq(adapter);
1111         if (!wrb) {
1112                 status = -EBUSY;
1113                 goto err;
1114         }
1115         sge = nonembedded_sgl(wrb);
1116         memset(req, 0, sizeof(*req));
1117
1118         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1119                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1120         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1121         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1122         sge->len = cpu_to_le32(mem->size);
1123
1124         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1125                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1126
1127         req->interface_id = if_id;
1128         if (mc_list) {
1129                 int i;
1130                 struct dev_mc_list *mc;
1131
1132                 req->num_mac = cpu_to_le16(mc_count);
1133
1134                 for (mc = mc_list, i = 0; mc; mc = mc->next, i++)
1135                         memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1136         } else {
1137                 req->promiscuous = 1;
1138         }
1139
1140         status = be_mcc_notify_wait(adapter);
1141
1142 err:
1143         spin_unlock_bh(&adapter->mcc_lock);
1144         return status;
1145 }
1146
1147 /* Uses synchrounous mcc */
1148 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1149 {
1150         struct be_mcc_wrb *wrb;
1151         struct be_cmd_req_set_flow_control *req;
1152         int status;
1153
1154         spin_lock_bh(&adapter->mcc_lock);
1155
1156         wrb = wrb_from_mccq(adapter);
1157         if (!wrb) {
1158                 status = -EBUSY;
1159                 goto err;
1160         }
1161         req = embedded_payload(wrb);
1162
1163         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1164                         OPCODE_COMMON_SET_FLOW_CONTROL);
1165
1166         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1167                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1168
1169         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1170         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1171
1172         status = be_mcc_notify_wait(adapter);
1173
1174 err:
1175         spin_unlock_bh(&adapter->mcc_lock);
1176         return status;
1177 }
1178
1179 /* Uses sycn mcc */
1180 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1181 {
1182         struct be_mcc_wrb *wrb;
1183         struct be_cmd_req_get_flow_control *req;
1184         int status;
1185
1186         spin_lock_bh(&adapter->mcc_lock);
1187
1188         wrb = wrb_from_mccq(adapter);
1189         if (!wrb) {
1190                 status = -EBUSY;
1191                 goto err;
1192         }
1193         req = embedded_payload(wrb);
1194
1195         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1196                         OPCODE_COMMON_GET_FLOW_CONTROL);
1197
1198         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1199                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1200
1201         status = be_mcc_notify_wait(adapter);
1202         if (!status) {
1203                 struct be_cmd_resp_get_flow_control *resp =
1204                                                 embedded_payload(wrb);
1205                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1206                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1207         }
1208
1209 err:
1210         spin_unlock_bh(&adapter->mcc_lock);
1211         return status;
1212 }
1213
1214 /* Uses mbox */
1215 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1216 {
1217         struct be_mcc_wrb *wrb;
1218         struct be_cmd_req_query_fw_cfg *req;
1219         int status;
1220
1221         spin_lock(&adapter->mbox_lock);
1222
1223         wrb = wrb_from_mbox(adapter);
1224         req = embedded_payload(wrb);
1225
1226         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1227                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1228
1229         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1230                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1231
1232         status = be_mbox_notify_wait(adapter);
1233         if (!status) {
1234                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1235                 *port_num = le32_to_cpu(resp->phys_port);
1236                 *cap = le32_to_cpu(resp->function_cap);
1237         }
1238
1239         spin_unlock(&adapter->mbox_lock);
1240         return status;
1241 }
1242
1243 /* Uses mbox */
1244 int be_cmd_reset_function(struct be_adapter *adapter)
1245 {
1246         struct be_mcc_wrb *wrb;
1247         struct be_cmd_req_hdr *req;
1248         int status;
1249
1250         spin_lock(&adapter->mbox_lock);
1251
1252         wrb = wrb_from_mbox(adapter);
1253         req = embedded_payload(wrb);
1254
1255         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1256                         OPCODE_COMMON_FUNCTION_RESET);
1257
1258         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1259                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1260
1261         status = be_mbox_notify_wait(adapter);
1262
1263         spin_unlock(&adapter->mbox_lock);
1264         return status;
1265 }
1266
1267 /* Uses sync mcc */
1268 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1269                         u8 bcn, u8 sts, u8 state)
1270 {
1271         struct be_mcc_wrb *wrb;
1272         struct be_cmd_req_enable_disable_beacon *req;
1273         int status;
1274
1275         spin_lock_bh(&adapter->mcc_lock);
1276
1277         wrb = wrb_from_mccq(adapter);
1278         if (!wrb) {
1279                 status = -EBUSY;
1280                 goto err;
1281         }
1282         req = embedded_payload(wrb);
1283
1284         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1285                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1286
1287         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1288                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1289
1290         req->port_num = port_num;
1291         req->beacon_state = state;
1292         req->beacon_duration = bcn;
1293         req->status_duration = sts;
1294
1295         status = be_mcc_notify_wait(adapter);
1296
1297 err:
1298         spin_unlock_bh(&adapter->mcc_lock);
1299         return status;
1300 }
1301
1302 /* Uses sync mcc */
1303 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1304 {
1305         struct be_mcc_wrb *wrb;
1306         struct be_cmd_req_get_beacon_state *req;
1307         int status;
1308
1309         spin_lock_bh(&adapter->mcc_lock);
1310
1311         wrb = wrb_from_mccq(adapter);
1312         if (!wrb) {
1313                 status = -EBUSY;
1314                 goto err;
1315         }
1316         req = embedded_payload(wrb);
1317
1318         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1319                         OPCODE_COMMON_GET_BEACON_STATE);
1320
1321         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1322                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1323
1324         req->port_num = port_num;
1325
1326         status = be_mcc_notify_wait(adapter);
1327         if (!status) {
1328                 struct be_cmd_resp_get_beacon_state *resp =
1329                                                 embedded_payload(wrb);
1330                 *state = resp->beacon_state;
1331         }
1332
1333 err:
1334         spin_unlock_bh(&adapter->mcc_lock);
1335         return status;
1336 }
1337
1338 /* Uses sync mcc */
1339 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1340                                 u8 *connector)
1341 {
1342         struct be_mcc_wrb *wrb;
1343         struct be_cmd_req_port_type *req;
1344         int status;
1345
1346         spin_lock_bh(&adapter->mcc_lock);
1347
1348         wrb = wrb_from_mccq(adapter);
1349         if (!wrb) {
1350                 status = -EBUSY;
1351                 goto err;
1352         }
1353         req = embedded_payload(wrb);
1354
1355         be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1356                         OPCODE_COMMON_READ_TRANSRECV_DATA);
1357
1358         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1359                 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1360
1361         req->port = cpu_to_le32(port);
1362         req->page_num = cpu_to_le32(TR_PAGE_A0);
1363         status = be_mcc_notify_wait(adapter);
1364         if (!status) {
1365                 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1366                         *connector = resp->data.connector;
1367         }
1368
1369 err:
1370         spin_unlock_bh(&adapter->mcc_lock);
1371         return status;
1372 }
1373
1374 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1375                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1376 {
1377         struct be_mcc_wrb *wrb;
1378         struct be_cmd_write_flashrom *req = cmd->va;
1379         struct be_sge *sge;
1380         int status;
1381
1382         spin_lock_bh(&adapter->mcc_lock);
1383
1384         wrb = wrb_from_mccq(adapter);
1385         if (!wrb) {
1386                 status = -EBUSY;
1387                 goto err;
1388         }
1389         req = cmd->va;
1390         sge = nonembedded_sgl(wrb);
1391
1392         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1393                         OPCODE_COMMON_WRITE_FLASHROM);
1394
1395         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1396                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1397         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1398         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1399         sge->len = cpu_to_le32(cmd->size);
1400
1401         req->params.op_type = cpu_to_le32(flash_type);
1402         req->params.op_code = cpu_to_le32(flash_opcode);
1403         req->params.data_buf_size = cpu_to_le32(buf_size);
1404
1405         status = be_mcc_notify_wait(adapter);
1406
1407 err:
1408         spin_unlock_bh(&adapter->mcc_lock);
1409         return status;
1410 }
1411
1412 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc)
1413 {
1414         struct be_mcc_wrb *wrb;
1415         struct be_cmd_write_flashrom *req;
1416         int status;
1417
1418         spin_lock_bh(&adapter->mcc_lock);
1419
1420         wrb = wrb_from_mccq(adapter);
1421         if (!wrb) {
1422                 status = -EBUSY;
1423                 goto err;
1424         }
1425         req = embedded_payload(wrb);
1426
1427         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1428                         OPCODE_COMMON_READ_FLASHROM);
1429
1430         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1431                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1432
1433         req->params.op_type = cpu_to_le32(FLASHROM_TYPE_REDBOOT);
1434         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1435         req->params.offset = 0x3FFFC;
1436         req->params.data_buf_size = 0x4;
1437
1438         status = be_mcc_notify_wait(adapter);
1439         if (!status)
1440                 memcpy(flashed_crc, req->params.data_buf, 4);
1441
1442 err:
1443         spin_unlock_bh(&adapter->mcc_lock);
1444         return status;
1445 }
1446
1447 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1448                                 struct be_dma_mem *nonemb_cmd)
1449 {
1450         struct be_mcc_wrb *wrb;
1451         struct be_cmd_req_acpi_wol_magic_config *req;
1452         struct be_sge *sge;
1453         int status;
1454
1455         spin_lock_bh(&adapter->mcc_lock);
1456
1457         wrb = wrb_from_mccq(adapter);
1458         if (!wrb) {
1459                 status = -EBUSY;
1460                 goto err;
1461         }
1462         req = nonemb_cmd->va;
1463         sge = nonembedded_sgl(wrb);
1464
1465         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1466                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1467
1468         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1469                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1470         memcpy(req->magic_mac, mac, ETH_ALEN);
1471
1472         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1473         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1474         sge->len = cpu_to_le32(nonemb_cmd->size);
1475
1476         status = be_mcc_notify_wait(adapter);
1477
1478 err:
1479         spin_unlock_bh(&adapter->mcc_lock);
1480         return status;
1481 }
1482
1483 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1484                         u8 loopback_type, u8 enable)
1485 {
1486         struct be_mcc_wrb *wrb;
1487         struct be_cmd_req_set_lmode *req;
1488         int status;
1489
1490         spin_lock_bh(&adapter->mcc_lock);
1491
1492         wrb = wrb_from_mccq(adapter);
1493         if (!wrb) {
1494                 status = -EBUSY;
1495                 goto err;
1496         }
1497
1498         req = embedded_payload(wrb);
1499
1500         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1501                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1502
1503         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1504                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1505                         sizeof(*req));
1506
1507         req->src_port = port_num;
1508         req->dest_port = port_num;
1509         req->loopback_type = loopback_type;
1510         req->loopback_state = enable;
1511
1512         status = be_mcc_notify_wait(adapter);
1513 err:
1514         spin_unlock_bh(&adapter->mcc_lock);
1515         return status;
1516 }
1517
1518 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1519                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1520 {
1521         struct be_mcc_wrb *wrb;
1522         struct be_cmd_req_loopback_test *req;
1523         int status;
1524
1525         spin_lock_bh(&adapter->mcc_lock);
1526
1527         wrb = wrb_from_mccq(adapter);
1528         if (!wrb) {
1529                 status = -EBUSY;
1530                 goto err;
1531         }
1532
1533         req = embedded_payload(wrb);
1534
1535         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1536                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1537
1538         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1539                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1540         req->hdr.timeout = 4;
1541
1542         req->pattern = cpu_to_le64(pattern);
1543         req->src_port = cpu_to_le32(port_num);
1544         req->dest_port = cpu_to_le32(port_num);
1545         req->pkt_size = cpu_to_le32(pkt_size);
1546         req->num_pkts = cpu_to_le32(num_pkts);
1547         req->loopback_type = cpu_to_le32(loopback_type);
1548
1549         status = be_mcc_notify_wait(adapter);
1550         if (!status) {
1551                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1552                 status = le32_to_cpu(resp->status);
1553         }
1554
1555 err:
1556         spin_unlock_bh(&adapter->mcc_lock);
1557         return status;
1558 }
1559
1560 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1561                                 u32 byte_cnt, struct be_dma_mem *cmd)
1562 {
1563         struct be_mcc_wrb *wrb;
1564         struct be_cmd_req_ddrdma_test *req;
1565         struct be_sge *sge;
1566         int status;
1567         int i, j = 0;
1568
1569         spin_lock_bh(&adapter->mcc_lock);
1570
1571         wrb = wrb_from_mccq(adapter);
1572         if (!wrb) {
1573                 status = -EBUSY;
1574                 goto err;
1575         }
1576         req = cmd->va;
1577         sge = nonembedded_sgl(wrb);
1578         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1579                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1580         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1581                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1582
1583         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1584         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1585         sge->len = cpu_to_le32(cmd->size);
1586
1587         req->pattern = cpu_to_le64(pattern);
1588         req->byte_count = cpu_to_le32(byte_cnt);
1589         for (i = 0; i < byte_cnt; i++) {
1590                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1591                 j++;
1592                 if (j > 7)
1593                         j = 0;
1594         }
1595
1596         status = be_mcc_notify_wait(adapter);
1597
1598         if (!status) {
1599                 struct be_cmd_resp_ddrdma_test *resp;
1600                 resp = cmd->va;
1601                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1602                                 resp->snd_err) {
1603                         status = -1;
1604                 }
1605         }
1606
1607 err:
1608         spin_unlock_bh(&adapter->mcc_lock);
1609         return status;
1610 }