drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/compatmac.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <asm/io.h>
  50
  51 #ifdef CONFIG_MTD_PARTITIONS
  52 #include <linux/mtd/partitions.h>
  53 #endif
  54
  55 /* Define default oob placement schemes for large and small page devices */
  56 static struct nand_ecclayout nand_oob_8 = {
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {
  60                 {.offset = 3,
  61                  .length = 2},
  62                 {.offset = 6,
  63                  .length = 2}}
  64 };
  65
  66 static struct nand_ecclayout nand_oob_16 = {
  67         .eccbytes = 6,
  68         .eccpos = {0, 1, 2, 3, 6, 7},
  69         .oobfree = {
  70                 {.offset = 8,
  71                  . length = 8}}
  72 };
  73
  74 static struct nand_ecclayout nand_oob_64 = {
  75         .eccbytes = 24,
  76         .eccpos = {
  77                    40, 41, 42, 43, 44, 45, 46, 47,
  78                    48, 49, 50, 51, 52, 53, 54, 55,
  79                    56, 57, 58, 59, 60, 61, 62, 63},
  80         .oobfree = {
  81                 {.offset = 2,
  82                  .length = 38}}
  83 };
  84
  85 static struct nand_ecclayout nand_oob_128 = {
  86         .eccbytes = 48,
  87         .eccpos = {
  88                    80, 81, 82, 83, 84, 85, 86, 87,
  89                    88, 89, 90, 91, 92, 93, 94, 95,
  90                    96, 97, 98, 99, 100, 101, 102, 103,
  91                    104, 105, 106, 107, 108, 109, 110, 111,
  92                    112, 113, 114, 115, 116, 117, 118, 119,
  93                    120, 121, 122, 123, 124, 125, 126, 127},
  94         .oobfree = {
  95                 {.offset = 2,
  96                  .length = 78}}
  97 };
  98
  99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 100                            int new_state);
 101
 102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 103                              struct mtd_oob_ops *ops);
 104
 105 /*
 106  * For devices which display every fart in the system on a separate LED. Is
 107  * compiled away when LED support is disabled.
 108  */
 109 DEFINE_LED_TRIGGER(nand_led_trigger);
 110
 111 static int check_offs_len(struct mtd_info *mtd,
 112                                         loff_t ofs, uint64_t len)
 113 {
 114         struct nand_chip *chip = mtd->priv;
 115         int ret = 0;
 116
 117         /* Start address must align on block boundary */
 118         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 119                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 120                 ret = -EINVAL;
 121         }
 122
 123         /* Length must align on block boundary */
 124         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 125                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 126                                         __func__);
 127                 ret = -EINVAL;
 128         }
 129
 130         /* Do not allow past end of device */
 131         if (ofs + len > mtd->size) {
 132                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
 133                                         __func__);
 134                 ret = -EINVAL;
 135         }
 136
 137         return ret;
 138 }
 139
 140 /**
 141  * nand_release_device - [GENERIC] release chip
 142  * @mtd:        MTD device structure
 143  *
 144  * Deselect, release chip lock and wake up anyone waiting on the device
 145  */
 146 static void nand_release_device(struct mtd_info *mtd)
 147 {
 148         struct nand_chip *chip = mtd->priv;
 149
 150         /* De-select the NAND device */
 151         chip->select_chip(mtd, -1);
 152
 153         /* Release the controller and the chip */
 154         spin_lock(&chip->controller->lock);
 155         chip->controller->active = NULL;
 156         chip->state = FL_READY;
 157         wake_up(&chip->controller->wq);
 158         spin_unlock(&chip->controller->lock);
 159 }
 160
 161 /**
 162  * nand_read_byte - [DEFAULT] read one byte from the chip
 163  * @mtd:        MTD device structure
 164  *
 165  * Default read function for 8bit buswith
 166  */
 167 static uint8_t nand_read_byte(struct mtd_info *mtd)
 168 {
 169         struct nand_chip *chip = mtd->priv;
 170         return readb(chip->IO_ADDR_R);
 171 }
 172
 173 /**
 174  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 175  * @mtd:        MTD device structure
 176  *
 177  * Default read function for 16bit buswith with
 178  * endianess conversion
 179  */
 180 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 181 {
 182         struct nand_chip *chip = mtd->priv;
 183         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 184 }
 185
 186 /**
 187  * nand_read_word - [DEFAULT] read one word from the chip
 188  * @mtd:        MTD device structure
 189  *
 190  * Default read function for 16bit buswith without
 191  * endianess conversion
 192  */
 193 static u16 nand_read_word(struct mtd_info *mtd)
 194 {
 195         struct nand_chip *chip = mtd->priv;
 196         return readw(chip->IO_ADDR_R);
 197 }
 198
 199 /**
 200  * nand_select_chip - [DEFAULT] control CE line
 201  * @mtd:        MTD device structure
 202  * @chipnr:     chipnumber to select, -1 for deselect
 203  *
 204  * Default select function for 1 chip devices.
 205  */
 206 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 207 {
 208         struct nand_chip *chip = mtd->priv;
 209
 210         switch (chipnr) {
 211         case -1:
 212                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 213                 break;
 214         case 0:
 215                 break;
 216
 217         default:
 218                 BUG();
 219         }
 220 }
 221
 222 /**
 223  * nand_write_buf - [DEFAULT] write buffer to chip
 224  * @mtd:        MTD device structure
 225  * @buf:        data buffer
 226  * @len:        number of bytes to write
 227  *
 228  * Default write function for 8bit buswith
 229  */
 230 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 231 {
 232         int i;
 233         struct nand_chip *chip = mtd->priv;
 234
 235         for (i = 0; i < len; i++)
 236                 writeb(buf[i], chip->IO_ADDR_W);
 237 }
 238
 239 /**
 240  * nand_read_buf - [DEFAULT] read chip data into buffer
 241  * @mtd:        MTD device structure
 242  * @buf:        buffer to store date
 243  * @len:        number of bytes to read
 244  *
 245  * Default read function for 8bit buswith
 246  */
 247 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 248 {
 249         int i;
 250         struct nand_chip *chip = mtd->priv;
 251
 252         for (i = 0; i < len; i++)
 253                 buf[i] = readb(chip->IO_ADDR_R);
 254 }
 255
 256 /**
 257  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 258  * @mtd:        MTD device structure
 259  * @buf:        buffer containing the data to compare
 260  * @len:        number of bytes to compare
 261  *
 262  * Default verify function for 8bit buswith
 263  */
 264 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 265 {
 266         int i;
 267         struct nand_chip *chip = mtd->priv;
 268
 269         for (i = 0; i < len; i++)
 270                 if (buf[i] != readb(chip->IO_ADDR_R))
 271                         return -EFAULT;
 272         return 0;
 273 }
 274
 275 /**
 276  * nand_write_buf16 - [DEFAULT] write buffer to chip
 277  * @mtd:        MTD device structure
 278  * @buf:        data buffer
 279  * @len:        number of bytes to write
 280  *
 281  * Default write function for 16bit buswith
 282  */
 283 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 284 {
 285         int i;
 286         struct nand_chip *chip = mtd->priv;
 287         u16 *p = (u16 *) buf;
 288         len >>= 1;
 289
 290         for (i = 0; i < len; i++)
 291                 writew(p[i], chip->IO_ADDR_W);
 292
 293 }
 294
 295 /**
 296  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 297  * @mtd:        MTD device structure
 298  * @buf:        buffer to store date
 299  * @len:        number of bytes to read
 300  *
 301  * Default read function for 16bit buswith
 302  */
 303 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 304 {
 305         int i;
 306         struct nand_chip *chip = mtd->priv;
 307         u16 *p = (u16 *) buf;
 308         len >>= 1;
 309
 310         for (i = 0; i < len; i++)
 311                 p[i] = readw(chip->IO_ADDR_R);
 312 }
 313
 314 /**
 315  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 316  * @mtd:        MTD device structure
 317  * @buf:        buffer containing the data to compare
 318  * @len:        number of bytes to compare
 319  *
 320  * Default verify function for 16bit buswith
 321  */
 322 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 323 {
 324         int i;
 325         struct nand_chip *chip = mtd->priv;
 326         u16 *p = (u16 *) buf;
 327         len >>= 1;
 328
 329         for (i = 0; i < len; i++)
 330                 if (p[i] != readw(chip->IO_ADDR_R))
 331                         return -EFAULT;
 332
 333         return 0;
 334 }
 335
 336 /**
 337  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 338  * @mtd:        MTD device structure
 339  * @ofs:        offset from device start
 340  * @getchip:    0, if the chip is already selected
 341  *
 342  * Check, if the block is bad.
 343  */
 344 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 345 {
 346         int page, chipnr, res = 0;
 347         struct nand_chip *chip = mtd->priv;
 348         u16 bad;
 349
 350         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 351
 352         if (getchip) {
 353                 chipnr = (int)(ofs >> chip->chip_shift);
 354
 355                 nand_get_device(chip, mtd, FL_READING);
 356
 357                 /* Select the NAND device */
 358                 chip->select_chip(mtd, chipnr);
 359         }
 360
 361         if (chip->options & NAND_BUSWIDTH_16) {
 362                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 363                               page);
 364                 bad = cpu_to_le16(chip->read_word(mtd));
 365                 if (chip->badblockpos & 0x1)
 366                         bad >>= 8;
 367                 else
 368                         bad &= 0xFF;
 369         } else {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 371                 bad = chip->read_byte(mtd);
 372         }
 373
 374         if (likely(chip->badblockbits == 8))
 375                 res = bad != 0xFF;
 376         else
 377                 res = hweight8(bad) < chip->badblockbits;
 378
 379         if (getchip)
 380                 nand_release_device(mtd);
 381
 382         return res;
 383 }
 384
 385 /**
 386  * nand_default_block_markbad - [DEFAULT] mark a block bad
 387  * @mtd:        MTD device structure
 388  * @ofs:        offset from device start
 389  *
 390  * This is the default implementation, which can be overridden by
 391  * a hardware specific driver.
 392 */
 393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 394 {
 395         struct nand_chip *chip = mtd->priv;
 396         uint8_t buf[2] = { 0, 0 };
 397         int block, ret;
 398
 399         /* Get block number */
 400         block = (int)(ofs >> chip->bbt_erase_shift);
 401         if (chip->bbt)
 402                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 403
 404         /* Do we have a flash based bad block table ? */
 405         if (chip->options & NAND_USE_FLASH_BBT)
 406                 ret = nand_update_bbt(mtd, ofs);
 407         else {
 408                 /* We write two bytes, so we dont have to mess with 16 bit
 409                  * access
 410                  */
 411                 nand_get_device(chip, mtd, FL_WRITING);
 412                 ofs += mtd->oobsize;
 413                 chip->ops.len = chip->ops.ooblen = 2;
 414                 chip->ops.datbuf = NULL;
 415                 chip->ops.oobbuf = buf;
 416                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 417
 418                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 419                 nand_release_device(mtd);
 420         }
 421         if (!ret)
 422                 mtd->ecc_stats.badblocks++;
 423
 424         return ret;
 425 }
 426
 427 /**
 428  * nand_check_wp - [GENERIC] check if the chip is write protected
 429  * @mtd:        MTD device structure
 430  * Check, if the device is write protected
 431  *
 432  * The function expects, that the device is already selected
 433  */
 434 static int nand_check_wp(struct mtd_info *mtd)
 435 {
 436         struct nand_chip *chip = mtd->priv;
 437         /* Check the WP bit */
 438         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 439         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 440 }
 441
 442 /**
 443  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 444  * @mtd:        MTD device structure
 445  * @ofs:        offset from device start
 446  * @getchip:    0, if the chip is already selected
 447  * @allowbbt:   1, if its allowed to access the bbt area
 448  *
 449  * Check, if the block is bad. Either by reading the bad block table or
 450  * calling of the scan function.
 451  */
 452 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 453                                int allowbbt)
 454 {
 455         struct nand_chip *chip = mtd->priv;
 456
 457         if (!chip->bbt)
 458                 return chip->block_bad(mtd, ofs, getchip);
 459
 460         /* Return info from the table */
 461         return nand_isbad_bbt(mtd, ofs, allowbbt);
 462 }
 463
 464 /**
 465  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 466  * @mtd:        MTD device structure
 467  * @timeo:      Timeout
 468  *
 469  * Helper function for nand_wait_ready used when needing to wait in interrupt
 470  * context.
 471  */
 472 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 473 {
 474         struct nand_chip *chip = mtd->priv;
 475         int i;
 476
 477         /* Wait for the device to get ready */
 478         for (i = 0; i < timeo; i++) {
 479                 if (chip->dev_ready(mtd))
 480                         break;
 481                 touch_softlockup_watchdog();
 482                 mdelay(1);
 483         }
 484 }
 485
 486 /*
 487  * Wait for the ready pin, after a command
 488  * The timeout is catched later.
 489  */
 490 void nand_wait_ready(struct mtd_info *mtd)
 491 {
 492         struct nand_chip *chip = mtd->priv;
 493         unsigned long timeo = jiffies + 2;
 494
 495         /* 400ms timeout */
 496         if (in_interrupt() || oops_in_progress)
 497                 return panic_nand_wait_ready(mtd, 400);
 498
 499         led_trigger_event(nand_led_trigger, LED_FULL);
 500         /* wait until command is processed or timeout occures */
 501         do {
 502                 if (chip->dev_ready(mtd))
 503                         break;
 504                 touch_softlockup_watchdog();
 505         } while (time_before(jiffies, timeo));
 506         led_trigger_event(nand_led_trigger, LED_OFF);
 507 }
 508 EXPORT_SYMBOL_GPL(nand_wait_ready);
 509
 510 /**
 511  * nand_command - [DEFAULT] Send command to NAND device
 512  * @mtd:        MTD device structure
 513  * @command:    the command to be sent
 514  * @column:     the column address for this command, -1 if none
 515  * @page_addr:  the page address for this command, -1 if none
 516  *
 517  * Send command to NAND device. This function is used for small page
 518  * devices (256/512 Bytes per page)
 519  */
 520 static void nand_command(struct mtd_info *mtd, unsigned int command,
 521                          int column, int page_addr)
 522 {
 523         register struct nand_chip *chip = mtd->priv;
 524         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 525
 526         /*
 527          * Write out the command to the device.
 528          */
 529         if (command == NAND_CMD_SEQIN) {
 530                 int readcmd;
 531
 532                 if (column >= mtd->writesize) {
 533                         /* OOB area */
 534                         column -= mtd->writesize;
 535                         readcmd = NAND_CMD_READOOB;
 536                 } else if (column < 256) {
 537                         /* First 256 bytes --> READ0 */
 538                         readcmd = NAND_CMD_READ0;
 539                 } else {
 540                         column -= 256;
 541                         readcmd = NAND_CMD_READ1;
 542                 }
 543                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 544                 ctrl &= ~NAND_CTRL_CHANGE;
 545         }
 546         chip->cmd_ctrl(mtd, command, ctrl);
 547
 548         /*
 549          * Address cycle, when necessary
 550          */
 551         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 552         /* Serially input address */
 553         if (column != -1) {
 554                 /* Adjust columns for 16 bit buswidth */
 555                 if (chip->options & NAND_BUSWIDTH_16)
 556                         column >>= 1;
 557                 chip->cmd_ctrl(mtd, column, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559         }
 560         if (page_addr != -1) {
 561                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 562                 ctrl &= ~NAND_CTRL_CHANGE;
 563                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 564                 /* One more address cycle for devices > 32MiB */
 565                 if (chip->chipsize > (32 << 20))
 566                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 567         }
 568         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 569
 570         /*
 571          * program and erase have their own busy handlers
 572          * status and sequential in needs no delay
 573          */
 574         switch (command) {
 575
 576         case NAND_CMD_PAGEPROG:
 577         case NAND_CMD_ERASE1:
 578         case NAND_CMD_ERASE2:
 579         case NAND_CMD_SEQIN:
 580         case NAND_CMD_STATUS:
 581                 return;
 582
 583         case NAND_CMD_RESET:
 584                 if (chip->dev_ready)
 585                         break;
 586                 udelay(chip->chip_delay);
 587                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 588                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 589                 chip->cmd_ctrl(mtd,
 590                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 591                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 592                 return;
 593
 594                 /* This applies to read commands */
 595         default:
 596                 /*
 597                  * If we don't have access to the busy pin, we apply the given
 598                  * command delay
 599                  */
 600                 if (!chip->dev_ready) {
 601                         udelay(chip->chip_delay);
 602                         return;
 603                 }
 604         }
 605         /* Apply this short delay always to ensure that we do wait tWB in
 606          * any case on any machine. */
 607         ndelay(100);
 608
 609         nand_wait_ready(mtd);
 610 }
 611
 612 /**
 613  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 614  * @mtd:        MTD device structure
 615  * @command:    the command to be sent
 616  * @column:     the column address for this command, -1 if none
 617  * @page_addr:  the page address for this command, -1 if none
 618  *
 619  * Send command to NAND device. This is the version for the new large page
 620  * devices We dont have the separate regions as we have in the small page
 621  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 622  */
 623 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 624                             int column, int page_addr)
 625 {
 626         register struct nand_chip *chip = mtd->priv;
 627
 628         /* Emulate NAND_CMD_READOOB */
 629         if (command == NAND_CMD_READOOB) {
 630                 column += mtd->writesize;
 631                 command = NAND_CMD_READ0;
 632         }
 633
 634         /* Command latch cycle */
 635         chip->cmd_ctrl(mtd, command & 0xff,
 636                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 637
 638         if (column != -1 || page_addr != -1) {
 639                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 640
 641                 /* Serially input address */
 642                 if (column != -1) {
 643                         /* Adjust columns for 16 bit buswidth */
 644                         if (chip->options & NAND_BUSWIDTH_16)
 645                                 column >>= 1;
 646                         chip->cmd_ctrl(mtd, column, ctrl);
 647                         ctrl &= ~NAND_CTRL_CHANGE;
 648                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 649                 }
 650                 if (page_addr != -1) {
 651                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 652                         chip->cmd_ctrl(mtd, page_addr >> 8,
 653                                        NAND_NCE | NAND_ALE);
 654                         /* One more address cycle for devices > 128MiB */
 655                         if (chip->chipsize > (128 << 20))
 656                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 657                                                NAND_NCE | NAND_ALE);
 658                 }
 659         }
 660         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 661
 662         /*
 663          * program and erase have their own busy handlers
 664          * status, sequential in, and deplete1 need no delay
 665          */
 666         switch (command) {
 667
 668         case NAND_CMD_CACHEDPROG:
 669         case NAND_CMD_PAGEPROG:
 670         case NAND_CMD_ERASE1:
 671         case NAND_CMD_ERASE2:
 672         case NAND_CMD_SEQIN:
 673         case NAND_CMD_RNDIN:
 674         case NAND_CMD_STATUS:
 675         case NAND_CMD_DEPLETE1:
 676                 return;
 677
 678                 /*
 679                  * read error status commands require only a short delay
 680                  */
 681         case NAND_CMD_STATUS_ERROR:
 682         case NAND_CMD_STATUS_ERROR0:
 683         case NAND_CMD_STATUS_ERROR1:
 684         case NAND_CMD_STATUS_ERROR2:
 685         case NAND_CMD_STATUS_ERROR3:
 686                 udelay(chip->chip_delay);
 687                 return;
 688
 689         case NAND_CMD_RESET:
 690                 if (chip->dev_ready)
 691                         break;
 692                 udelay(chip->chip_delay);
 693                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 694                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 695                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 696                                NAND_NCE | NAND_CTRL_CHANGE);
 697                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 698                 return;
 699
 700         case NAND_CMD_RNDOUT:
 701                 /* No ready / busy check necessary */
 702                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 703                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 704                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 705                                NAND_NCE | NAND_CTRL_CHANGE);
 706                 return;
 707
 708         case NAND_CMD_READ0:
 709                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 710                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 711                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 712                                NAND_NCE | NAND_CTRL_CHANGE);
 713
 714                 /* This applies to read commands */
 715         default:
 716                 /*
 717                  * If we don't have access to the busy pin, we apply the given
 718                  * command delay
 719                  */
 720                 if (!chip->dev_ready) {
 721                         udelay(chip->chip_delay);
 722                         return;
 723                 }
 724         }
 725
 726         /* Apply this short delay always to ensure that we do wait tWB in
 727          * any case on any machine. */
 728         ndelay(100);
 729
 730         nand_wait_ready(mtd);
 731 }
 732
 733 /**
 734  * panic_nand_get_device - [GENERIC] Get chip for selected access
 735  * @chip:       the nand chip descriptor
 736  * @mtd:        MTD device structure
 737  * @new_state:  the state which is requested
 738  *
 739  * Used when in panic, no locks are taken.
 740  */
 741 static void panic_nand_get_device(struct nand_chip *chip,
 742                       struct mtd_info *mtd, int new_state)
 743 {
 744         /* Hardware controller shared among independend devices */
 745         chip->controller->active = chip;
 746         chip->state = new_state;
 747 }
 748
 749 /**
 750  * nand_get_device - [GENERIC] Get chip for selected access
 751  * @chip:       the nand chip descriptor
 752  * @mtd:        MTD device structure
 753  * @new_state:  the state which is requested
 754  *
 755  * Get the device and lock it for exclusive access
 756  */
 757 static int
 758 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 759 {
 760         spinlock_t *lock = &chip->controller->lock;
 761         wait_queue_head_t *wq = &chip->controller->wq;
 762         DECLARE_WAITQUEUE(wait, current);
 763  retry:
 764         spin_lock(lock);
 765
 766         /* Hardware controller shared among independent devices */
 767         if (!chip->controller->active)
 768                 chip->controller->active = chip;
 769
 770         if (chip->controller->active == chip && chip->state == FL_READY) {
 771                 chip->state = new_state;
 772                 spin_unlock(lock);
 773                 return 0;
 774         }
 775         if (new_state == FL_PM_SUSPENDED) {
 776                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 777                         chip->state = FL_PM_SUSPENDED;
 778                         spin_unlock(lock);
 779                         return 0;
 780                 }
 781         }
 782         set_current_state(TASK_UNINTERRUPTIBLE);
 783         add_wait_queue(wq, &wait);
 784         spin_unlock(lock);
 785         schedule();
 786         remove_wait_queue(wq, &wait);
 787         goto retry;
 788 }
 789
 790 /**
 791  * panic_nand_wait - [GENERIC]  wait until the command is done
 792  * @mtd:        MTD device structure
 793  * @chip:       NAND chip structure
 794  * @timeo:      Timeout
 795  *
 796  * Wait for command done. This is a helper function for nand_wait used when
 797  * we are in interrupt context. May happen when in panic and trying to write
 798  * an oops trough mtdoops.
 799  */
 800 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 801                             unsigned long timeo)
 802 {
 803         int i;
 804         for (i = 0; i < timeo; i++) {
 805                 if (chip->dev_ready) {
 806                         if (chip->dev_ready(mtd))
 807                                 break;
 808                 } else {
 809                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 810                                 break;
 811                 }
 812                 mdelay(1);
 813         }
 814 }
 815
 816 /**
 817  * nand_wait - [DEFAULT]  wait until the command is done
 818  * @mtd:        MTD device structure
 819  * @chip:       NAND chip structure
 820  *
 821  * Wait for command done. This applies to erase and program only
 822  * Erase can take up to 400ms and program up to 20ms according to
 823  * general NAND and SmartMedia specs
 824  */
 825 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 826 {
 827
 828         unsigned long timeo = jiffies;
 829         int status, state = chip->state;
 830
 831         if (state == FL_ERASING)
 832                 timeo += (HZ * 400) / 1000;
 833         else
 834                 timeo += (HZ * 20) / 1000;
 835
 836         led_trigger_event(nand_led_trigger, LED_FULL);
 837
 838         /* Apply this short delay always to ensure that we do wait tWB in
 839          * any case on any machine. */
 840         ndelay(100);
 841
 842         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 843                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 844         else
 845                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 846
 847         if (in_interrupt() || oops_in_progress)
 848                 panic_nand_wait(mtd, chip, timeo);
 849         else {
 850                 while (time_before(jiffies, timeo)) {
 851                         if (chip->dev_ready) {
 852                                 if (chip->dev_ready(mtd))
 853                                         break;
 854                         } else {
 855                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 856                                         break;
 857                         }
 858                         cond_resched();
 859                 }
 860         }
 861         led_trigger_event(nand_led_trigger, LED_OFF);
 862
 863         status = (int)chip->read_byte(mtd);
 864         return status;
 865 }
 866
 867 /**
 868  * __nand_unlock - [REPLACABLE] unlocks specified locked blockes
 869  *
 870  * @param mtd - mtd info
 871  * @param ofs - offset to start unlock from
 872  * @param len - length to unlock
 873  * @invert -  when = 0, unlock the range of blocks within the lower and
 874  *                      upper boundary address
 875  *            whne = 1, unlock the range of blocks outside the boundaries
 876  *                      of the lower and upper boundary address
 877  *
 878  * @return - unlock status
 879  */
 880 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 881                                         uint64_t len, int invert)
 882 {
 883         int ret = 0;
 884         int status, page;
 885         struct nand_chip *chip = mtd->priv;
 886
 887         /* Submit address of first page to unlock */
 888         page = ofs >> chip->page_shift;
 889         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 890
 891         /* Submit address of last page to unlock */
 892         page = (ofs + len) >> chip->page_shift;
 893         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 894                                 (page | invert) & chip->pagemask);
 895
 896         /* Call wait ready function */
 897         status = chip->waitfunc(mtd, chip);
 898         udelay(1000);
 899         /* See if device thinks it succeeded */
 900         if (status & 0x01) {
 901                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
 902                                         __func__, status);
 903                 ret = -EIO;
 904         }
 905
 906         return ret;
 907 }
 908
 909 /**
 910  * nand_unlock - [REPLACABLE] unlocks specified locked blockes
 911  *
 912  * @param mtd - mtd info
 913  * @param ofs - offset to start unlock from
 914  * @param len - length to unlock
 915  *
 916  * @return - unlock status
 917  */
 918 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 919 {
 920         int ret = 0;
 921         int chipnr;
 922         struct nand_chip *chip = mtd->priv;
 923
 924         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 925                         __func__, (unsigned long long)ofs, len);
 926
 927         if (check_offs_len(mtd, ofs, len))
 928                 ret = -EINVAL;
 929
 930         /* Align to last block address if size addresses end of the device */
 931         if (ofs + len == mtd->size)
 932                 len -= mtd->erasesize;
 933
 934         nand_get_device(chip, mtd, FL_UNLOCKING);
 935
 936         /* Shift to get chip number */
 937         chipnr = ofs >> chip->chip_shift;
 938
 939         chip->select_chip(mtd, chipnr);
 940
 941         /* Check, if it is write protected */
 942         if (nand_check_wp(mtd)) {
 943                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 944                                         __func__);
 945                 ret = -EIO;
 946                 goto out;
 947         }
 948
 949         ret = __nand_unlock(mtd, ofs, len, 0);
 950
 951 out:
 952         /* de-select the NAND device */
 953         chip->select_chip(mtd, -1);
 954
 955         nand_release_device(mtd);
 956
 957         return ret;
 958 }
 959
 960 /**
 961  * nand_lock - [REPLACABLE] locks all blockes present in the device
 962  *
 963  * @param mtd - mtd info
 964  * @param ofs - offset to start unlock from
 965  * @param len - length to unlock
 966  *
 967  * @return - lock status
 968  *
 969  * This feature is not support in many NAND parts. 'Micron' NAND parts
 970  * do have this feature, but it allows only to lock all blocks not for
 971  * specified range for block.
 972  *
 973  * Implementing 'lock' feature by making use of 'unlock', for now.
 974  */
 975 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 976 {
 977         int ret = 0;
 978         int chipnr, status, page;
 979         struct nand_chip *chip = mtd->priv;
 980
 981         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 982                         __func__, (unsigned long long)ofs, len);
 983
 984         if (check_offs_len(mtd, ofs, len))
 985                 ret = -EINVAL;
 986
 987         nand_get_device(chip, mtd, FL_LOCKING);
 988
 989         /* Shift to get chip number */
 990         chipnr = ofs >> chip->chip_shift;
 991
 992         chip->select_chip(mtd, chipnr);
 993
 994         /* Check, if it is write protected */
 995         if (nand_check_wp(mtd)) {
 996                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 997                                         __func__);
 998                 status = MTD_ERASE_FAILED;
 999                 ret = -EIO;
1000                 goto out;
1001         }
1002
1003         /* Submit address of first page to lock */
1004         page = ofs >> chip->page_shift;
1005         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1006
1007         /* Call wait ready function */
1008         status = chip->waitfunc(mtd, chip);
1009         udelay(1000);
1010         /* See if device thinks it succeeded */
1011         if (status & 0x01) {
1012                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1013                                         __func__, status);
1014                 ret = -EIO;
1015                 goto out;
1016         }
1017
1018         ret = __nand_unlock(mtd, ofs, len, 0x1);
1019
1020 out:
1021         /* de-select the NAND device */
1022         chip->select_chip(mtd, -1);
1023
1024         nand_release_device(mtd);
1025
1026         return ret;
1027 }
1028
1029 /**
1030  * nand_read_page_raw - [Intern] read raw page data without ecc
1031  * @mtd:        mtd info structure
1032  * @chip:       nand chip info structure
1033  * @buf:        buffer to store read data
1034  * @page:       page number to read
1035  *
1036  * Not for syndrome calculating ecc controllers, which use a special oob layout
1037  */
1038 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1039                               uint8_t *buf, int page)
1040 {
1041         chip->read_buf(mtd, buf, mtd->writesize);
1042         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1043         return 0;
1044 }
1045
1046 /**
1047  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1048  * @mtd:        mtd info structure
1049  * @chip:       nand chip info structure
1050  * @buf:        buffer to store read data
1051  * @page:       page number to read
1052  *
1053  * We need a special oob layout and handling even when OOB isn't used.
1054  */
1055 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1056                               uint8_t *buf, int page)
1057 {
1058         int eccsize = chip->ecc.size;
1059         int eccbytes = chip->ecc.bytes;
1060         uint8_t *oob = chip->oob_poi;
1061         int steps, size;
1062
1063         for (steps = chip->ecc.steps; steps > 0; steps--) {
1064                 chip->read_buf(mtd, buf, eccsize);
1065                 buf += eccsize;
1066
1067                 if (chip->ecc.prepad) {
1068                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1069                         oob += chip->ecc.prepad;
1070                 }
1071
1072                 chip->read_buf(mtd, oob, eccbytes);
1073                 oob += eccbytes;
1074
1075                 if (chip->ecc.postpad) {
1076                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1077                         oob += chip->ecc.postpad;
1078                 }
1079         }
1080
1081         size = mtd->oobsize - (oob - chip->oob_poi);
1082         if (size)
1083                 chip->read_buf(mtd, oob, size);
1084
1085         return 0;
1086 }
1087
1088 /**
1089  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1090  * @mtd:        mtd info structure
1091  * @chip:       nand chip info structure
1092  * @buf:        buffer to store read data
1093  * @page:       page number to read
1094  */
1095 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1096                                 uint8_t *buf, int page)
1097 {
1098         int i, eccsize = chip->ecc.size;
1099         int eccbytes = chip->ecc.bytes;
1100         int eccsteps = chip->ecc.steps;
1101         uint8_t *p = buf;
1102         uint8_t *ecc_calc = chip->buffers->ecccalc;
1103         uint8_t *ecc_code = chip->buffers->ecccode;
1104         uint32_t *eccpos = chip->ecc.layout->eccpos;
1105
1106         chip->ecc.read_page_raw(mtd, chip, buf, page);
1107
1108         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1109                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1110
1111         for (i = 0; i < chip->ecc.total; i++)
1112                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1113
1114         eccsteps = chip->ecc.steps;
1115         p = buf;
1116
1117         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1118                 int stat;
1119
1120                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1121                 if (stat < 0)
1122                         mtd->ecc_stats.failed++;
1123                 else
1124                         mtd->ecc_stats.corrected += stat;
1125         }
1126         return 0;
1127 }
1128
1129 /**
1130  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1131  * @mtd:        mtd info structure
1132  * @chip:       nand chip info structure
1133  * @data_offs:  offset of requested data within the page
1134  * @readlen:    data length
1135  * @bufpoi:     buffer to store read data
1136  */
1137 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1138 {
1139         int start_step, end_step, num_steps;
1140         uint32_t *eccpos = chip->ecc.layout->eccpos;
1141         uint8_t *p;
1142         int data_col_addr, i, gaps = 0;
1143         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1144         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1145
1146         /* Column address wihin the page aligned to ECC size (256bytes). */
1147         start_step = data_offs / chip->ecc.size;
1148         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1149         num_steps = end_step - start_step + 1;
1150
1151         /* Data size aligned to ECC ecc.size*/
1152         datafrag_len = num_steps * chip->ecc.size;
1153         eccfrag_len = num_steps * chip->ecc.bytes;
1154
1155         data_col_addr = start_step * chip->ecc.size;
1156         /* If we read not a page aligned data */
1157         if (data_col_addr != 0)
1158                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1159
1160         p = bufpoi + data_col_addr;
1161         chip->read_buf(mtd, p, datafrag_len);
1162
1163         /* Calculate  ECC */
1164         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1165                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1166
1167         /* The performance is faster if to position offsets
1168            according to ecc.pos. Let make sure here that
1169            there are no gaps in ecc positions */
1170         for (i = 0; i < eccfrag_len - 1; i++) {
1171                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1172                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1173                         gaps = 1;
1174                         break;
1175                 }
1176         }
1177         if (gaps) {
1178                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1179                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1180         } else {
1181                 /* send the command to read the particular ecc bytes */
1182                 /* take care about buswidth alignment in read_buf */
1183                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1184                 aligned_len = eccfrag_len;
1185                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1186                         aligned_len++;
1187                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1188                         aligned_len++;
1189
1190                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1191                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1192         }
1193
1194         for (i = 0; i < eccfrag_len; i++)
1195                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1196
1197         p = bufpoi + data_col_addr;
1198         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1199                 int stat;
1200
1201                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1202                 if (stat == -1)
1203                         mtd->ecc_stats.failed++;
1204                 else
1205                         mtd->ecc_stats.corrected += stat;
1206         }
1207         return 0;
1208 }
1209
1210 /**
1211  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1212  * @mtd:        mtd info structure
1213  * @chip:       nand chip info structure
1214  * @buf:        buffer to store read data
1215  * @page:       page number to read
1216  *
1217  * Not for syndrome calculating ecc controllers which need a special oob layout
1218  */
1219 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1220                                 uint8_t *buf, int page)
1221 {
1222         int i, eccsize = chip->ecc.size;
1223         int eccbytes = chip->ecc.bytes;
1224         int eccsteps = chip->ecc.steps;
1225         uint8_t *p = buf;
1226         uint8_t *ecc_calc = chip->buffers->ecccalc;
1227         uint8_t *ecc_code = chip->buffers->ecccode;
1228         uint32_t *eccpos = chip->ecc.layout->eccpos;
1229
1230         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1231                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1232                 chip->read_buf(mtd, p, eccsize);
1233                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1234         }
1235         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1236
1237         for (i = 0; i < chip->ecc.total; i++)
1238                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1239
1240         eccsteps = chip->ecc.steps;
1241         p = buf;
1242
1243         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1244                 int stat;
1245
1246                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1247                 if (stat < 0)
1248                         mtd->ecc_stats.failed++;
1249                 else
1250                         mtd->ecc_stats.corrected += stat;
1251         }
1252         return 0;
1253 }
1254
1255 /**
1256  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1257  * @mtd:        mtd info structure
1258  * @chip:       nand chip info structure
1259  * @buf:        buffer to store read data
1260  * @page:       page number to read
1261  *
1262  * Hardware ECC for large page chips, require OOB to be read first.
1263  * For this ECC mode, the write_page method is re-used from ECC_HW.
1264  * These methods read/write ECC from the OOB area, unlike the
1265  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1266  * "infix ECC" scheme and reads/writes ECC from the data area, by
1267  * overwriting the NAND manufacturer bad block markings.
1268  */
1269 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1270         struct nand_chip *chip, uint8_t *buf, int page)
1271 {
1272         int i, eccsize = chip->ecc.size;
1273         int eccbytes = chip->ecc.bytes;
1274         int eccsteps = chip->ecc.steps;
1275         uint8_t *p = buf;
1276         uint8_t *ecc_code = chip->buffers->ecccode;
1277         uint32_t *eccpos = chip->ecc.layout->eccpos;
1278         uint8_t *ecc_calc = chip->buffers->ecccalc;
1279
1280         /* Read the OOB area first */
1281         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1282         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1283         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1284
1285         for (i = 0; i < chip->ecc.total; i++)
1286                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1287
1288         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1289                 int stat;
1290
1291                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1292                 chip->read_buf(mtd, p, eccsize);
1293                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1294
1295                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1296                 if (stat < 0)
1297                         mtd->ecc_stats.failed++;
1298                 else
1299                         mtd->ecc_stats.corrected += stat;
1300         }
1301         return 0;
1302 }
1303
1304 /**
1305  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1306  * @mtd:        mtd info structure
1307  * @chip:       nand chip info structure
1308  * @buf:        buffer to store read data
1309  * @page:       page number to read
1310  *
1311  * The hw generator calculates the error syndrome automatically. Therefor
1312  * we need a special oob layout and handling.
1313  */
1314 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1315                                    uint8_t *buf, int page)
1316 {
1317         int i, eccsize = chip->ecc.size;
1318         int eccbytes = chip->ecc.bytes;
1319         int eccsteps = chip->ecc.steps;
1320         uint8_t *p = buf;
1321         uint8_t *oob = chip->oob_poi;
1322
1323         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1324                 int stat;
1325
1326                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1327                 chip->read_buf(mtd, p, eccsize);
1328
1329                 if (chip->ecc.prepad) {
1330                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1331                         oob += chip->ecc.prepad;
1332                 }
1333
1334                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1335                 chip->read_buf(mtd, oob, eccbytes);
1336                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1337
1338                 if (stat < 0)
1339                         mtd->ecc_stats.failed++;
1340                 else
1341                         mtd->ecc_stats.corrected += stat;
1342
1343                 oob += eccbytes;
1344
1345                 if (chip->ecc.postpad) {
1346                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1347                         oob += chip->ecc.postpad;
1348                 }
1349         }
1350
1351         /* Calculate remaining oob bytes */
1352         i = mtd->oobsize - (oob - chip->oob_poi);
1353         if (i)
1354                 chip->read_buf(mtd, oob, i);
1355
1356         return 0;
1357 }
1358
1359 /**
1360  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1361  * @chip:       nand chip structure
1362  * @oob:        oob destination address
1363  * @ops:        oob ops structure
1364  * @len:        size of oob to transfer
1365  */
1366 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1367                                   struct mtd_oob_ops *ops, size_t len)
1368 {
1369         switch(ops->mode) {
1370
1371         case MTD_OOB_PLACE:
1372         case MTD_OOB_RAW:
1373                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1374                 return oob + len;
1375
1376         case MTD_OOB_AUTO: {
1377                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1378                 uint32_t boffs = 0, roffs = ops->ooboffs;
1379                 size_t bytes = 0;
1380
1381                 for(; free->length && len; free++, len -= bytes) {
1382                         /* Read request not from offset 0 ? */
1383                         if (unlikely(roffs)) {
1384                                 if (roffs >= free->length) {
1385                                         roffs -= free->length;
1386                                         continue;
1387                                 }
1388                                 boffs = free->offset + roffs;
1389                                 bytes = min_t(size_t, len,
1390                                               (free->length - roffs));
1391                                 roffs = 0;
1392                         } else {
1393                                 bytes = min_t(size_t, len, free->length);
1394                                 boffs = free->offset;
1395                         }
1396                         memcpy(oob, chip->oob_poi + boffs, bytes);
1397                         oob += bytes;
1398                 }
1399                 return oob;
1400         }
1401         default:
1402                 BUG();
1403         }
1404         return NULL;
1405 }
1406
1407 /**
1408  * nand_do_read_ops - [Internal] Read data with ECC
1409  *
1410  * @mtd:        MTD device structure
1411  * @from:       offset to read from
1412  * @ops:        oob ops structure
1413  *
1414  * Internal function. Called with chip held.
1415  */
1416 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1417                             struct mtd_oob_ops *ops)
1418 {
1419         int chipnr, page, realpage, col, bytes, aligned;
1420         struct nand_chip *chip = mtd->priv;
1421         struct mtd_ecc_stats stats;
1422         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1423         int sndcmd = 1;
1424         int ret = 0;
1425         uint32_t readlen = ops->len;
1426         uint32_t oobreadlen = ops->ooblen;
1427         uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1428                 mtd->oobavail : mtd->oobsize;
1429
1430         uint8_t *bufpoi, *oob, *buf;
1431
1432         stats = mtd->ecc_stats;
1433
1434         chipnr = (int)(from >> chip->chip_shift);
1435         chip->select_chip(mtd, chipnr);
1436
1437         realpage = (int)(from >> chip->page_shift);
1438         page = realpage & chip->pagemask;
1439
1440         col = (int)(from & (mtd->writesize - 1));
1441
1442         buf = ops->datbuf;
1443         oob = ops->oobbuf;
1444
1445         while(1) {
1446                 bytes = min(mtd->writesize - col, readlen);
1447                 aligned = (bytes == mtd->writesize);
1448
1449                 /* Is the current page in the buffer ? */
1450                 if (realpage != chip->pagebuf || oob) {
1451                         bufpoi = aligned ? buf : chip->buffers->databuf;
1452
1453                         if (likely(sndcmd)) {
1454                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1455                                 sndcmd = 0;
1456                         }
1457
1458                         /* Now read the page into the buffer */
1459                         if (unlikely(ops->mode == MTD_OOB_RAW))
1460                                 ret = chip->ecc.read_page_raw(mtd, chip,
1461                                                               bufpoi, page);
1462                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1463                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1464                         else
1465                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1466                                                           page);
1467                         if (ret < 0)
1468                                 break;
1469
1470                         /* Transfer not aligned data */
1471                         if (!aligned) {
1472                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1473                                         chip->pagebuf = realpage;
1474                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1475                         }
1476
1477                         buf += bytes;
1478
1479                         if (unlikely(oob)) {
1480
1481                                 int toread = min(oobreadlen, max_oobsize);
1482
1483                                 if (toread) {
1484                                         oob = nand_transfer_oob(chip,
1485                                                 oob, ops, toread);
1486                                         oobreadlen -= toread;
1487                                 }
1488                         }
1489
1490                         if (!(chip->options & NAND_NO_READRDY)) {
1491                                 /*
1492                                  * Apply delay or wait for ready/busy pin. Do
1493                                  * this before the AUTOINCR check, so no
1494                                  * problems arise if a chip which does auto
1495                                  * increment is marked as NOAUTOINCR by the
1496                                  * board driver.
1497                                  */
1498                                 if (!chip->dev_ready)
1499                                         udelay(chip->chip_delay);
1500                                 else
1501                                         nand_wait_ready(mtd);
1502                         }
1503                 } else {
1504                         memcpy(buf, chip->buffers->databuf + col, bytes);
1505                         buf += bytes;
1506                 }
1507
1508                 readlen -= bytes;
1509
1510                 if (!readlen)
1511                         break;
1512
1513                 /* For subsequent reads align to page boundary. */
1514                 col = 0;
1515                 /* Increment page address */
1516                 realpage++;
1517
1518                 page = realpage & chip->pagemask;
1519                 /* Check, if we cross a chip boundary */
1520                 if (!page) {
1521                         chipnr++;
1522                         chip->select_chip(mtd, -1);
1523                         chip->select_chip(mtd, chipnr);
1524                 }
1525
1526                 /* Check, if the chip supports auto page increment
1527                  * or if we have hit a block boundary.
1528                  */
1529                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1530                         sndcmd = 1;
1531         }
1532
1533         ops->retlen = ops->len - (size_t) readlen;
1534         if (oob)
1535                 ops->oobretlen = ops->ooblen - oobreadlen;
1536
1537         if (ret)
1538                 return ret;
1539
1540         if (mtd->ecc_stats.failed - stats.failed)
1541                 return -EBADMSG;
1542
1543         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1544 }
1545
1546 /**
1547  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1548  * @mtd:        MTD device structure
1549  * @from:       offset to read from
1550  * @len:        number of bytes to read
1551  * @retlen:     pointer to variable to store the number of read bytes
1552  * @buf:        the databuffer to put data
1553  *
1554  * Get hold of the chip and call nand_do_read
1555  */
1556 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1557                      size_t *retlen, uint8_t *buf)
1558 {
1559         struct nand_chip *chip = mtd->priv;
1560         int ret;
1561
1562         /* Do not allow reads past end of device */
1563         if ((from + len) > mtd->size)
1564                 return -EINVAL;
1565         if (!len)
1566                 return 0;
1567
1568         nand_get_device(chip, mtd, FL_READING);
1569
1570         chip->ops.len = len;
1571         chip->ops.datbuf = buf;
1572         chip->ops.oobbuf = NULL;
1573
1574         ret = nand_do_read_ops(mtd, from, &chip->ops);
1575
1576         *retlen = chip->ops.retlen;
1577
1578         nand_release_device(mtd);
1579
1580         return ret;
1581 }
1582
1583 /**
1584  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1585  * @mtd:        mtd info structure
1586  * @chip:       nand chip info structure
1587  * @page:       page number to read
1588  * @sndcmd:     flag whether to issue read command or not
1589  */
1590 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1591                              int page, int sndcmd)
1592 {
1593         if (sndcmd) {
1594                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1595                 sndcmd = 0;
1596         }
1597         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1598         return sndcmd;
1599 }
1600
1601 /**
1602  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1603  *                          with syndromes
1604  * @mtd:        mtd info structure
1605  * @chip:       nand chip info structure
1606  * @page:       page number to read
1607  * @sndcmd:     flag whether to issue read command or not
1608  */
1609 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1610                                   int page, int sndcmd)
1611 {
1612         uint8_t *buf = chip->oob_poi;
1613         int length = mtd->oobsize;
1614         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1615         int eccsize = chip->ecc.size;
1616         uint8_t *bufpoi = buf;
1617         int i, toread, sndrnd = 0, pos;
1618
1619         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1620         for (i = 0; i < chip->ecc.steps; i++) {
1621                 if (sndrnd) {
1622                         pos = eccsize + i * (eccsize + chunk);
1623                         if (mtd->writesize > 512)
1624                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1625                         else
1626                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1627                 } else
1628                         sndrnd = 1;
1629                 toread = min_t(int, length, chunk);
1630                 chip->read_buf(mtd, bufpoi, toread);
1631                 bufpoi += toread;
1632                 length -= toread;
1633         }
1634         if (length > 0)
1635                 chip->read_buf(mtd, bufpoi, length);
1636
1637         return 1;
1638 }
1639
1640 /**
1641  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1642  * @mtd:        mtd info structure
1643  * @chip:       nand chip info structure
1644  * @page:       page number to write
1645  */
1646 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1647                               int page)
1648 {
1649         int status = 0;
1650         const uint8_t *buf = chip->oob_poi;
1651         int length = mtd->oobsize;
1652
1653         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1654         chip->write_buf(mtd, buf, length);
1655         /* Send command to program the OOB data */
1656         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1657
1658         status = chip->waitfunc(mtd, chip);
1659
1660         return status & NAND_STATUS_FAIL ? -EIO : 0;
1661 }
1662
1663 /**
1664  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1665  *                           with syndrome - only for large page flash !
1666  * @mtd:        mtd info structure
1667  * @chip:       nand chip info structure
1668  * @page:       page number to write
1669  */
1670 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1671                                    struct nand_chip *chip, int page)
1672 {
1673         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1674         int eccsize = chip->ecc.size, length = mtd->oobsize;
1675         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1676         const uint8_t *bufpoi = chip->oob_poi;
1677
1678         /*
1679          * data-ecc-data-ecc ... ecc-oob
1680          * or
1681          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1682          */
1683         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1684                 pos = steps * (eccsize + chunk);
1685                 steps = 0;
1686         } else
1687                 pos = eccsize;
1688
1689         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1690         for (i = 0; i < steps; i++) {
1691                 if (sndcmd) {
1692                         if (mtd->writesize <= 512) {
1693                                 uint32_t fill = 0xFFFFFFFF;
1694
1695                                 len = eccsize;
1696                                 while (len > 0) {
1697                                         int num = min_t(int, len, 4);
1698                                         chip->write_buf(mtd, (uint8_t *)&fill,
1699                                                         num);
1700                                         len -= num;
1701                                 }
1702                         } else {
1703                                 pos = eccsize + i * (eccsize + chunk);
1704                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1705                         }
1706                 } else
1707                         sndcmd = 1;
1708                 len = min_t(int, length, chunk);
1709                 chip->write_buf(mtd, bufpoi, len);
1710                 bufpoi += len;
1711                 length -= len;
1712         }
1713         if (length > 0)
1714                 chip->write_buf(mtd, bufpoi, length);
1715
1716         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1717         status = chip->waitfunc(mtd, chip);
1718
1719         return status & NAND_STATUS_FAIL ? -EIO : 0;
1720 }
1721
1722 /**
1723  * nand_do_read_oob - [Intern] NAND read out-of-band
1724  * @mtd:        MTD device structure
1725  * @from:       offset to read from
1726  * @ops:        oob operations description structure
1727  *
1728  * NAND read out-of-band data from the spare area
1729  */
1730 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1731                             struct mtd_oob_ops *ops)
1732 {
1733         int page, realpage, chipnr, sndcmd = 1;
1734         struct nand_chip *chip = mtd->priv;
1735         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1736         int readlen = ops->ooblen;
1737         int len;
1738         uint8_t *buf = ops->oobbuf;
1739
1740         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1741                         __func__, (unsigned long long)from, readlen);
1742
1743         if (ops->mode == MTD_OOB_AUTO)
1744                 len = chip->ecc.layout->oobavail;
1745         else
1746                 len = mtd->oobsize;
1747
1748         if (unlikely(ops->ooboffs >= len)) {
1749                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1750                                         "outside oob\n", __func__);
1751                 return -EINVAL;
1752         }
1753
1754         /* Do not allow reads past end of device */
1755         if (unlikely(from >= mtd->size ||
1756                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1757                                         (from >> chip->page_shift)) * len)) {
1758                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1759                                         "of device\n", __func__);
1760                 return -EINVAL;
1761         }
1762
1763         chipnr = (int)(from >> chip->chip_shift);
1764         chip->select_chip(mtd, chipnr);
1765
1766         /* Shift to get page */
1767         realpage = (int)(from >> chip->page_shift);
1768         page = realpage & chip->pagemask;
1769
1770         while(1) {
1771                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1772
1773                 len = min(len, readlen);
1774                 buf = nand_transfer_oob(chip, buf, ops, len);
1775
1776                 if (!(chip->options & NAND_NO_READRDY)) {
1777                         /*
1778                          * Apply delay or wait for ready/busy pin. Do this
1779                          * before the AUTOINCR check, so no problems arise if a
1780                          * chip which does auto increment is marked as
1781                          * NOAUTOINCR by the board driver.
1782                          */
1783                         if (!chip->dev_ready)
1784                                 udelay(chip->chip_delay);
1785                         else
1786                                 nand_wait_ready(mtd);
1787                 }
1788
1789                 readlen -= len;
1790                 if (!readlen)
1791                         break;
1792
1793                 /* Increment page address */
1794                 realpage++;
1795
1796                 page = realpage & chip->pagemask;
1797                 /* Check, if we cross a chip boundary */
1798                 if (!page) {
1799                         chipnr++;
1800                         chip->select_chip(mtd, -1);
1801                         chip->select_chip(mtd, chipnr);
1802                 }
1803
1804                 /* Check, if the chip supports auto page increment
1805                  * or if we have hit a block boundary.
1806                  */
1807                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1808                         sndcmd = 1;
1809         }
1810
1811         ops->oobretlen = ops->ooblen;
1812         return 0;
1813 }
1814
1815 /**
1816  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1817  * @mtd:        MTD device structure
1818  * @from:       offset to read from
1819  * @ops:        oob operation description structure
1820  *
1821  * NAND read data and/or out-of-band data
1822  */
1823 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1824                          struct mtd_oob_ops *ops)
1825 {
1826         struct nand_chip *chip = mtd->priv;
1827         int ret = -ENOTSUPP;
1828
1829         ops->retlen = 0;
1830
1831         /* Do not allow reads past end of device */
1832         if (ops->datbuf && (from + ops->len) > mtd->size) {
1833                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1834                                 "beyond end of device\n", __func__);
1835                 return -EINVAL;
1836         }
1837
1838         nand_get_device(chip, mtd, FL_READING);
1839
1840         switch(ops->mode) {
1841         case MTD_OOB_PLACE:
1842         case MTD_OOB_AUTO:
1843         case MTD_OOB_RAW:
1844                 break;
1845
1846         default:
1847                 goto out;
1848         }
1849
1850         if (!ops->datbuf)
1851                 ret = nand_do_read_oob(mtd, from, ops);
1852         else
1853                 ret = nand_do_read_ops(mtd, from, ops);
1854
1855  out:
1856         nand_release_device(mtd);
1857         return ret;
1858 }
1859
1860
1861 /**
1862  * nand_write_page_raw - [Intern] raw page write function
1863  * @mtd:        mtd info structure
1864  * @chip:       nand chip info structure
1865  * @buf:        data buffer
1866  *
1867  * Not for syndrome calculating ecc controllers, which use a special oob layout
1868  */
1869 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1870                                 const uint8_t *buf)
1871 {
1872         chip->write_buf(mtd, buf, mtd->writesize);
1873         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1874 }
1875
1876 /**
1877  * nand_write_page_raw_syndrome - [Intern] raw page write function
1878  * @mtd:        mtd info structure
1879  * @chip:       nand chip info structure
1880  * @buf:        data buffer
1881  *
1882  * We need a special oob layout and handling even when ECC isn't checked.
1883  */
1884 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1885                                 const uint8_t *buf)
1886 {
1887         int eccsize = chip->ecc.size;
1888         int eccbytes = chip->ecc.bytes;
1889         uint8_t *oob = chip->oob_poi;
1890         int steps, size;
1891
1892         for (steps = chip->ecc.steps; steps > 0; steps--) {
1893                 chip->write_buf(mtd, buf, eccsize);
1894                 buf += eccsize;
1895
1896                 if (chip->ecc.prepad) {
1897                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1898                         oob += chip->ecc.prepad;
1899                 }
1900
1901                 chip->read_buf(mtd, oob, eccbytes);
1902                 oob += eccbytes;
1903
1904                 if (chip->ecc.postpad) {
1905                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1906                         oob += chip->ecc.postpad;
1907                 }
1908         }
1909
1910         size = mtd->oobsize - (oob - chip->oob_poi);
1911         if (size)
1912                 chip->write_buf(mtd, oob, size);
1913 }
1914 /**
1915  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1916  * @mtd:        mtd info structure
1917  * @chip:       nand chip info structure
1918  * @buf:        data buffer
1919  */
1920 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1921                                   const uint8_t *buf)
1922 {
1923         int i, eccsize = chip->ecc.size;
1924         int eccbytes = chip->ecc.bytes;
1925         int eccsteps = chip->ecc.steps;
1926         uint8_t *ecc_calc = chip->buffers->ecccalc;
1927         const uint8_t *p = buf;
1928         uint32_t *eccpos = chip->ecc.layout->eccpos;
1929
1930         /* Software ecc calculation */
1931         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1932                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1933
1934         for (i = 0; i < chip->ecc.total; i++)
1935                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1936
1937         chip->ecc.write_page_raw(mtd, chip, buf);
1938 }
1939
1940 /**
1941  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1942  * @mtd:        mtd info structure
1943  * @chip:       nand chip info structure
1944  * @buf:        data buffer
1945  */
1946 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1947                                   const uint8_t *buf)
1948 {
1949         int i, eccsize = chip->ecc.size;
1950         int eccbytes = chip->ecc.bytes;
1951         int eccsteps = chip->ecc.steps;
1952         uint8_t *ecc_calc = chip->buffers->ecccalc;
1953         const uint8_t *p = buf;
1954         uint32_t *eccpos = chip->ecc.layout->eccpos;
1955
1956         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1957                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1958                 chip->write_buf(mtd, p, eccsize);
1959                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1960         }
1961
1962         for (i = 0; i < chip->ecc.total; i++)
1963                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1964
1965         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1966 }
1967
1968 /**
1969  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1970  * @mtd:        mtd info structure
1971  * @chip:       nand chip info structure
1972  * @buf:        data buffer
1973  *
1974  * The hw generator calculates the error syndrome automatically. Therefor
1975  * we need a special oob layout and handling.
1976  */
1977 static void nand_write_page_syndrome(struct mtd_info *mtd,
1978                                     struct nand_chip *chip, const uint8_t *buf)
1979 {
1980         int i, eccsize = chip->ecc.size;
1981         int eccbytes = chip->ecc.bytes;
1982         int eccsteps = chip->ecc.steps;
1983         const uint8_t *p = buf;
1984         uint8_t *oob = chip->oob_poi;
1985
1986         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1987
1988                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1989                 chip->write_buf(mtd, p, eccsize);
1990
1991                 if (chip->ecc.prepad) {
1992                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1993                         oob += chip->ecc.prepad;
1994                 }
1995
1996                 chip->ecc.calculate(mtd, p, oob);
1997                 chip->write_buf(mtd, oob, eccbytes);
1998                 oob += eccbytes;
1999
2000                 if (chip->ecc.postpad) {
2001                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2002                         oob += chip->ecc.postpad;
2003                 }
2004         }
2005
2006         /* Calculate remaining oob bytes */
2007         i = mtd->oobsize - (oob - chip->oob_poi);
2008         if (i)
2009                 chip->write_buf(mtd, oob, i);
2010 }
2011
2012 /**
2013  * nand_write_page - [REPLACEABLE] write one page
2014  * @mtd:        MTD device structure
2015  * @chip:       NAND chip descriptor
2016  * @buf:        the data to write
2017  * @page:       page number to write
2018  * @cached:     cached programming
2019  * @raw:        use _raw version of write_page
2020  */
2021 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2022                            const uint8_t *buf, int page, int cached, int raw)
2023 {
2024         int status;
2025
2026         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2027
2028         if (unlikely(raw))
2029                 chip->ecc.write_page_raw(mtd, chip, buf);
2030         else
2031                 chip->ecc.write_page(mtd, chip, buf);
2032
2033         /*
2034          * Cached progamming disabled for now, Not sure if its worth the
2035          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2036          */
2037         cached = 0;
2038
2039         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2040
2041                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2042                 status = chip->waitfunc(mtd, chip);
2043                 /*
2044                  * See if operation failed and additional status checks are
2045                  * available
2046                  */
2047                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2048                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2049                                                page);
2050
2051                 if (status & NAND_STATUS_FAIL)
2052                         return -EIO;
2053         } else {
2054                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2055                 status = chip->waitfunc(mtd, chip);
2056         }
2057
2058 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2059         /* Send command to read back the data */
2060         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2061
2062         if (chip->verify_buf(mtd, buf, mtd->writesize))
2063                 return -EIO;
2064 #endif
2065         return 0;
2066 }
2067
2068 /**
2069  * nand_fill_oob - [Internal] Transfer client buffer to oob
2070  * @chip:       nand chip structure
2071  * @oob:        oob data buffer
2072  * @ops:        oob ops structure
2073  */
2074 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2075                                                 struct mtd_oob_ops *ops)
2076 {
2077         switch(ops->mode) {
2078
2079         case MTD_OOB_PLACE:
2080         case MTD_OOB_RAW:
2081                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2082                 return oob + len;
2083
2084         case MTD_OOB_AUTO: {
2085                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2086                 uint32_t boffs = 0, woffs = ops->ooboffs;
2087                 size_t bytes = 0;
2088
2089                 for(; free->length && len; free++, len -= bytes) {
2090                         /* Write request not from offset 0 ? */
2091                         if (unlikely(woffs)) {
2092                                 if (woffs >= free->length) {
2093                                         woffs -= free->length;
2094                                         continue;
2095                                 }
2096                                 boffs = free->offset + woffs;
2097                                 bytes = min_t(size_t, len,
2098                                               (free->length - woffs));
2099                                 woffs = 0;
2100                         } else {
2101                                 bytes = min_t(size_t, len, free->length);
2102                                 boffs = free->offset;
2103                         }
2104                         memcpy(chip->oob_poi + boffs, oob, bytes);
2105                         oob += bytes;
2106                 }
2107                 return oob;
2108         }
2109         default:
2110                 BUG();
2111         }
2112         return NULL;
2113 }
2114
2115 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
2116
2117 /**
2118  * nand_do_write_ops - [Internal] NAND write with ECC
2119  * @mtd:        MTD device structure
2120  * @to:         offset to write to
2121  * @ops:        oob operations description structure
2122  *
2123  * NAND write with ECC
2124  */
2125 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2126                              struct mtd_oob_ops *ops)
2127 {
2128         int chipnr, realpage, page, blockmask, column;
2129         struct nand_chip *chip = mtd->priv;
2130         uint32_t writelen = ops->len;
2131
2132         uint32_t oobwritelen = ops->ooblen;
2133         uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2134                                 mtd->oobavail : mtd->oobsize;
2135
2136         uint8_t *oob = ops->oobbuf;
2137         uint8_t *buf = ops->datbuf;
2138         int ret, subpage;
2139
2140         ops->retlen = 0;
2141         if (!writelen)
2142                 return 0;
2143
2144         /* reject writes, which are not page aligned */
2145         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2146                 printk(KERN_NOTICE "%s: Attempt to write not "
2147                                 "page aligned data\n", __func__);
2148                 return -EINVAL;
2149         }
2150
2151         column = to & (mtd->writesize - 1);
2152         subpage = column || (writelen & (mtd->writesize - 1));
2153
2154         if (subpage && oob)
2155                 return -EINVAL;
2156
2157         chipnr = (int)(to >> chip->chip_shift);
2158         chip->select_chip(mtd, chipnr);
2159
2160         /* Check, if it is write protected */
2161         if (nand_check_wp(mtd))
2162                 return -EIO;
2163
2164         realpage = (int)(to >> chip->page_shift);
2165         page = realpage & chip->pagemask;
2166         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2167
2168         /* Invalidate the page cache, when we write to the cached page */
2169         if (to <= (chip->pagebuf << chip->page_shift) &&
2170             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2171                 chip->pagebuf = -1;
2172
2173         /* If we're not given explicit OOB data, let it be 0xFF */
2174         if (likely(!oob))
2175                 memset(chip->oob_poi, 0xff, mtd->oobsize);
2176
2177         /* Don't allow multipage oob writes with offset */
2178         if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2179                 return -EINVAL;
2180
2181         while(1) {
2182                 int bytes = mtd->writesize;
2183                 int cached = writelen > bytes && page != blockmask;
2184                 uint8_t *wbuf = buf;
2185
2186                 /* Partial page write ? */
2187                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2188                         cached = 0;
2189                         bytes = min_t(int, bytes - column, (int) writelen);
2190                         chip->pagebuf = -1;
2191                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2192                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2193                         wbuf = chip->buffers->databuf;
2194                 }
2195
2196                 if (unlikely(oob)) {
2197                         size_t len = min(oobwritelen, oobmaxlen);
2198                         oob = nand_fill_oob(chip, oob, len, ops);
2199                         oobwritelen -= len;
2200                 }
2201
2202                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2203                                        (ops->mode == MTD_OOB_RAW));
2204                 if (ret)
2205                         break;
2206
2207                 writelen -= bytes;
2208                 if (!writelen)
2209                         break;
2210
2211                 column = 0;
2212                 buf += bytes;
2213                 realpage++;
2214
2215                 page = realpage & chip->pagemask;
2216                 /* Check, if we cross a chip boundary */
2217                 if (!page) {
2218                         chipnr++;
2219                         chip->select_chip(mtd, -1);
2220                         chip->select_chip(mtd, chipnr);
2221                 }
2222         }
2223
2224         ops->retlen = ops->len - writelen;
2225         if (unlikely(oob))
2226                 ops->oobretlen = ops->ooblen;
2227         return ret;
2228 }
2229
2230 /**
2231  * panic_nand_write - [MTD Interface] NAND write with ECC
2232  * @mtd:        MTD device structure
2233  * @to:         offset to write to
2234  * @len:        number of bytes to write
2235  * @retlen:     pointer to variable to store the number of written bytes
2236  * @buf:        the data to write
2237  *
2238  * NAND write with ECC. Used when performing writes in interrupt context, this
2239  * may for example be called by mtdoops when writing an oops while in panic.
2240  */
2241 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2242                             size_t *retlen, const uint8_t *buf)
2243 {
2244         struct nand_chip *chip = mtd->priv;
2245         int ret;
2246
2247         /* Do not allow reads past end of device */
2248         if ((to + len) > mtd->size)
2249                 return -EINVAL;
2250         if (!len)
2251                 return 0;
2252
2253         /* Wait for the device to get ready.  */
2254         panic_nand_wait(mtd, chip, 400);
2255
2256         /* Grab the device.  */
2257         panic_nand_get_device(chip, mtd, FL_WRITING);
2258
2259         chip->ops.len = len;
2260         chip->ops.datbuf = (uint8_t *)buf;
2261         chip->ops.oobbuf = NULL;
2262
2263         ret = nand_do_write_ops(mtd, to, &chip->ops);
2264
2265         *retlen = chip->ops.retlen;
2266         return ret;
2267 }
2268
2269 /**
2270  * nand_write - [MTD Interface] NAND write with ECC
2271  * @mtd:        MTD device structure
2272  * @to:         offset to write to
2273  * @len:        number of bytes to write
2274  * @retlen:     pointer to variable to store the number of written bytes
2275  * @buf:        the data to write
2276  *
2277  * NAND write with ECC
2278  */
2279 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2280                           size_t *retlen, const uint8_t *buf)
2281 {
2282         struct nand_chip *chip = mtd->priv;
2283         int ret;
2284
2285         /* Do not allow reads past end of device */
2286         if ((to + len) > mtd->size)
2287                 return -EINVAL;
2288         if (!len)
2289                 return 0;
2290
2291         nand_get_device(chip, mtd, FL_WRITING);
2292
2293         chip->ops.len = len;
2294         chip->ops.datbuf = (uint8_t *)buf;
2295         chip->ops.oobbuf = NULL;
2296
2297         ret = nand_do_write_ops(mtd, to, &chip->ops);
2298
2299         *retlen = chip->ops.retlen;
2300
2301         nand_release_device(mtd);
2302
2303         return ret;
2304 }
2305
2306 /**
2307  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2308  * @mtd:        MTD device structure
2309  * @to:         offset to write to
2310  * @ops:        oob operation description structure
2311  *
2312  * NAND write out-of-band
2313  */
2314 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2315                              struct mtd_oob_ops *ops)
2316 {
2317         int chipnr, page, status, len;
2318         struct nand_chip *chip = mtd->priv;
2319
2320         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2321                          __func__, (unsigned int)to, (int)ops->ooblen);
2322
2323         if (ops->mode == MTD_OOB_AUTO)
2324                 len = chip->ecc.layout->oobavail;
2325         else
2326                 len = mtd->oobsize;
2327
2328         /* Do not allow write past end of page */
2329         if ((ops->ooboffs + ops->ooblen) > len) {
2330                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2331                                 "past end of page\n", __func__);
2332                 return -EINVAL;
2333         }
2334
2335         if (unlikely(ops->ooboffs >= len)) {
2336                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2337                                 "write outside oob\n", __func__);
2338                 return -EINVAL;
2339         }
2340
2341         /* Do not allow reads past end of device */
2342         if (unlikely(to >= mtd->size ||
2343                      ops->ooboffs + ops->ooblen >
2344                         ((mtd->size >> chip->page_shift) -
2345                          (to >> chip->page_shift)) * len)) {
2346                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2347                                 "end of device\n", __func__);
2348                 return -EINVAL;
2349         }
2350
2351         chipnr = (int)(to >> chip->chip_shift);
2352         chip->select_chip(mtd, chipnr);
2353
2354         /* Shift to get page */
2355         page = (int)(to >> chip->page_shift);
2356
2357         /*
2358          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2359          * of my DiskOnChip 2000 test units) will clear the whole data page too
2360          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2361          * it in the doc2000 driver in August 1999.  dwmw2.
2362          */
2363         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2364
2365         /* Check, if it is write protected */
2366         if (nand_check_wp(mtd))
2367                 return -EROFS;
2368
2369         /* Invalidate the page cache, if we write to the cached page */
2370         if (page == chip->pagebuf)
2371                 chip->pagebuf = -1;
2372
2373         memset(chip->oob_poi, 0xff, mtd->oobsize);
2374         nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2375         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2376         memset(chip->oob_poi, 0xff, mtd->oobsize);
2377
2378         if (status)
2379                 return status;
2380
2381         ops->oobretlen = ops->ooblen;
2382
2383         return 0;
2384 }
2385
2386 /**
2387  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2388  * @mtd:        MTD device structure
2389  * @to:         offset to write to
2390  * @ops:        oob operation description structure
2391  */
2392 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2393                           struct mtd_oob_ops *ops)
2394 {
2395         struct nand_chip *chip = mtd->priv;
2396         int ret = -ENOTSUPP;
2397
2398         ops->retlen = 0;
2399
2400         /* Do not allow writes past end of device */
2401         if (ops->datbuf && (to + ops->len) > mtd->size) {
2402                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2403                                 "end of device\n", __func__);
2404                 return -EINVAL;
2405         }
2406
2407         nand_get_device(chip, mtd, FL_WRITING);
2408
2409         switch(ops->mode) {
2410         case MTD_OOB_PLACE:
2411         case MTD_OOB_AUTO:
2412         case MTD_OOB_RAW:
2413                 break;
2414
2415         default:
2416                 goto out;
2417         }
2418
2419         if (!ops->datbuf)
2420                 ret = nand_do_write_oob(mtd, to, ops);
2421         else
2422                 ret = nand_do_write_ops(mtd, to, ops);
2423
2424  out:
2425         nand_release_device(mtd);
2426         return ret;
2427 }
2428
2429 /**
2430  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2431  * @mtd:        MTD device structure
2432  * @page:       the page address of the block which will be erased
2433  *
2434  * Standard erase command for NAND chips
2435  */
2436 static void single_erase_cmd(struct mtd_info *mtd, int page)
2437 {
2438         struct nand_chip *chip = mtd->priv;
2439         /* Send commands to erase a block */
2440         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2441         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2442 }
2443
2444 /**
2445  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2446  * @mtd:        MTD device structure
2447  * @page:       the page address of the block which will be erased
2448  *
2449  * AND multi block erase command function
2450  * Erase 4 consecutive blocks
2451  */
2452 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2453 {
2454         struct nand_chip *chip = mtd->priv;
2455         /* Send commands to erase a block */
2456         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2457         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2458         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2459         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2460         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2461 }
2462
2463 /**
2464  * nand_erase - [MTD Interface] erase block(s)
2465  * @mtd:        MTD device structure
2466  * @instr:      erase instruction
2467  *
2468  * Erase one ore more blocks
2469  */
2470 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2471 {
2472         return nand_erase_nand(mtd, instr, 0);
2473 }
2474
2475 #define BBT_PAGE_MASK   0xffffff3f
2476 /**
2477  * nand_erase_nand - [Internal] erase block(s)
2478  * @mtd:        MTD device structure
2479  * @instr:      erase instruction
2480  * @allowbbt:   allow erasing the bbt area
2481  *
2482  * Erase one ore more blocks
2483  */
2484 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2485                     int allowbbt)
2486 {
2487         int page, status, pages_per_block, ret, chipnr;
2488         struct nand_chip *chip = mtd->priv;
2489         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2490         unsigned int bbt_masked_page = 0xffffffff;
2491         loff_t len;
2492
2493         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2494                                 __func__, (unsigned long long)instr->addr,
2495                                 (unsigned long long)instr->len);
2496
2497         if (check_offs_len(mtd, instr->addr, instr->len))
2498                 return -EINVAL;
2499
2500         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2501
2502         /* Grab the lock and see if the device is available */
2503         nand_get_device(chip, mtd, FL_ERASING);
2504
2505         /* Shift to get first page */
2506         page = (int)(instr->addr >> chip->page_shift);
2507         chipnr = (int)(instr->addr >> chip->chip_shift);
2508
2509         /* Calculate pages in each block */
2510         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2511
2512         /* Select the NAND device */
2513         chip->select_chip(mtd, chipnr);
2514
2515         /* Check, if it is write protected */
2516         if (nand_check_wp(mtd)) {
2517                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2518                                         __func__);
2519                 instr->state = MTD_ERASE_FAILED;
2520                 goto erase_exit;
2521         }
2522
2523         /*
2524          * If BBT requires refresh, set the BBT page mask to see if the BBT
2525          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2526          * can not be matched. This is also done when the bbt is actually
2527          * erased to avoid recusrsive updates
2528          */
2529         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2530                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2531
2532         /* Loop through the pages */
2533         len = instr->len;
2534
2535         instr->state = MTD_ERASING;
2536
2537         while (len) {
2538                 /*
2539                  * heck if we have a bad block, we do not erase bad blocks !
2540                  */
2541                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2542                                         chip->page_shift, 0, allowbbt)) {
2543                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2544                                         "at page 0x%08x\n", __func__, page);
2545                         instr->state = MTD_ERASE_FAILED;
2546                         goto erase_exit;
2547                 }
2548
2549                 /*
2550                  * Invalidate the page cache, if we erase the block which
2551                  * contains the current cached page
2552                  */
2553                 if (page <= chip->pagebuf && chip->pagebuf <
2554                     (page + pages_per_block))
2555                         chip->pagebuf = -1;
2556
2557                 chip->erase_cmd(mtd, page & chip->pagemask);
2558
2559                 status = chip->waitfunc(mtd, chip);
2560
2561                 /*
2562                  * See if operation failed and additional status checks are
2563                  * available
2564                  */
2565                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2566                         status = chip->errstat(mtd, chip, FL_ERASING,
2567                                                status, page);
2568
2569                 /* See if block erase succeeded */
2570                 if (status & NAND_STATUS_FAIL) {
2571                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2572                                         "page 0x%08x\n", __func__, page);
2573                         instr->state = MTD_ERASE_FAILED;
2574                         instr->fail_addr =
2575                                 ((loff_t)page << chip->page_shift);
2576                         goto erase_exit;
2577                 }
2578
2579                 /*
2580                  * If BBT requires refresh, set the BBT rewrite flag to the
2581                  * page being erased
2582                  */
2583                 if (bbt_masked_page != 0xffffffff &&
2584                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2585                             rewrite_bbt[chipnr] =
2586                                         ((loff_t)page << chip->page_shift);
2587
2588                 /* Increment page address and decrement length */
2589                 len -= (1 << chip->phys_erase_shift);
2590                 page += pages_per_block;
2591
2592                 /* Check, if we cross a chip boundary */
2593                 if (len && !(page & chip->pagemask)) {
2594                         chipnr++;
2595                         chip->select_chip(mtd, -1);
2596                         chip->select_chip(mtd, chipnr);
2597
2598                         /*
2599                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2600                          * page mask to see if this BBT should be rewritten
2601                          */
2602                         if (bbt_masked_page != 0xffffffff &&
2603                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2604                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2605                                         BBT_PAGE_MASK;
2606                 }
2607         }
2608         instr->state = MTD_ERASE_DONE;
2609
2610  erase_exit:
2611
2612         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2613
2614         /* Deselect and wake up anyone waiting on the device */
2615         nand_release_device(mtd);
2616
2617         /* Do call back function */
2618         if (!ret)
2619                 mtd_erase_callback(instr);
2620
2621         /*
2622          * If BBT requires refresh and erase was successful, rewrite any
2623          * selected bad block tables
2624          */
2625         if (bbt_masked_page == 0xffffffff || ret)
2626                 return ret;
2627
2628         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2629                 if (!rewrite_bbt[chipnr])
2630                         continue;
2631                 /* update the BBT for chip */
2632                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2633                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2634                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2635                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2636         }
2637
2638         /* Return more or less happy */
2639         return ret;
2640 }
2641
2642 /**
2643  * nand_sync - [MTD Interface] sync
2644  * @mtd:        MTD device structure
2645  *
2646  * Sync is actually a wait for chip ready function
2647  */
2648 static void nand_sync(struct mtd_info *mtd)
2649 {
2650         struct nand_chip *chip = mtd->priv;
2651
2652         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2653
2654         /* Grab the lock and see if the device is available */
2655         nand_get_device(chip, mtd, FL_SYNCING);
2656         /* Release it and go back */
2657         nand_release_device(mtd);
2658 }
2659
2660 /**
2661  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2662  * @mtd:        MTD device structure
2663  * @offs:       offset relative to mtd start
2664  */
2665 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2666 {
2667         /* Check for invalid offset */
2668         if (offs > mtd->size)
2669                 return -EINVAL;
2670
2671         return nand_block_checkbad(mtd, offs, 1, 0);
2672 }
2673
2674 /**
2675  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2676  * @mtd:        MTD device structure
2677  * @ofs:        offset relative to mtd start
2678  */
2679 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2680 {
2681         struct nand_chip *chip = mtd->priv;
2682         int ret;
2683
2684         if ((ret = nand_block_isbad(mtd, ofs))) {
2685                 /* If it was bad already, return success and do nothing. */
2686                 if (ret > 0)
2687                         return 0;
2688                 return ret;
2689         }
2690
2691         return chip->block_markbad(mtd, ofs);
2692 }
2693
2694 /**
2695  * nand_suspend - [MTD Interface] Suspend the NAND flash
2696  * @mtd:        MTD device structure
2697  */
2698 static int nand_suspend(struct mtd_info *mtd)
2699 {
2700         struct nand_chip *chip = mtd->priv;
2701
2702         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2703 }
2704
2705 /**
2706  * nand_resume - [MTD Interface] Resume the NAND flash
2707  * @mtd:        MTD device structure
2708  */
2709 static void nand_resume(struct mtd_info *mtd)
2710 {
2711         struct nand_chip *chip = mtd->priv;
2712
2713         if (chip->state == FL_PM_SUSPENDED)
2714                 nand_release_device(mtd);
2715         else
2716                 printk(KERN_ERR "%s called for a chip which is not "
2717                        "in suspended state\n", __func__);
2718 }
2719
2720 /*
2721  * Set default functions
2722  */
2723 static void nand_set_defaults(struct nand_chip *chip, int busw)
2724 {
2725         /* check for proper chip_delay setup, set 20us if not */
2726         if (!chip->chip_delay)
2727                 chip->chip_delay = 20;
2728
2729         /* check, if a user supplied command function given */
2730         if (chip->cmdfunc == NULL)
2731                 chip->cmdfunc = nand_command;
2732
2733         /* check, if a user supplied wait function given */
2734         if (chip->waitfunc == NULL)
2735                 chip->waitfunc = nand_wait;
2736
2737         if (!chip->select_chip)
2738                 chip->select_chip = nand_select_chip;
2739         if (!chip->read_byte)
2740                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2741         if (!chip->read_word)
2742                 chip->read_word = nand_read_word;
2743         if (!chip->block_bad)
2744                 chip->block_bad = nand_block_bad;
2745         if (!chip->block_markbad)
2746                 chip->block_markbad = nand_default_block_markbad;
2747         if (!chip->write_buf)
2748                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2749         if (!chip->read_buf)
2750                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2751         if (!chip->verify_buf)
2752                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2753         if (!chip->scan_bbt)
2754                 chip->scan_bbt = nand_default_bbt;
2755
2756         if (!chip->controller) {
2757                 chip->controller = &chip->hwcontrol;
2758                 spin_lock_init(&chip->controller->lock);
2759                 init_waitqueue_head(&chip->controller->wq);
2760         }
2761
2762 }
2763
2764 /*
2765  * Get the flash and manufacturer id and lookup if the type is supported
2766  */
2767 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2768                                                   struct nand_chip *chip,
2769                                                   int busw, int *maf_id,
2770                                                   struct nand_flash_dev *type)
2771 {
2772         int dev_id, maf_idx;
2773         int tmp_id, tmp_manf;
2774
2775         /* Select the device */
2776         chip->select_chip(mtd, 0);
2777
2778         /*
2779          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2780          * after power-up
2781          */
2782         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2783
2784         /* Send the command for reading device ID */
2785         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2786
2787         /* Read manufacturer and device IDs */
2788         *maf_id = chip->read_byte(mtd);
2789         dev_id = chip->read_byte(mtd);
2790
2791         /* Try again to make sure, as some systems the bus-hold or other
2792          * interface concerns can cause random data which looks like a
2793          * possibly credible NAND flash to appear. If the two results do
2794          * not match, ignore the device completely.
2795          */
2796
2797         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2798
2799         /* Read manufacturer and device IDs */
2800
2801         tmp_manf = chip->read_byte(mtd);
2802         tmp_id = chip->read_byte(mtd);
2803
2804         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2805                 printk(KERN_INFO "%s: second ID read did not match "
2806                        "%02x,%02x against %02x,%02x\n", __func__,
2807                        *maf_id, dev_id, tmp_manf, tmp_id);
2808                 return ERR_PTR(-ENODEV);
2809         }
2810
2811         if (!type)
2812                 type = nand_flash_ids;
2813
2814         for (; type->name != NULL; type++)
2815                 if (dev_id == type->id)
2816                         break;
2817
2818         if (!type->name)
2819                 return ERR_PTR(-ENODEV);
2820
2821         if (!mtd->name)
2822                 mtd->name = type->name;
2823
2824         chip->chipsize = (uint64_t)type->chipsize << 20;
2825
2826         /* Newer devices have all the information in additional id bytes */
2827         if (!type->pagesize) {
2828                 int extid;
2829                 /* The 3rd id byte holds MLC / multichip data */
2830                 chip->cellinfo = chip->read_byte(mtd);
2831                 /* The 4th id byte is the important one */
2832                 extid = chip->read_byte(mtd);
2833                 /* Calc pagesize */
2834                 mtd->writesize = 1024 << (extid & 0x3);
2835                 extid >>= 2;
2836                 /* Calc oobsize */
2837                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2838                 extid >>= 2;
2839                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2840                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2841                 extid >>= 2;
2842                 /* Get buswidth information */
2843                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2844
2845         } else {
2846                 /*
2847                  * Old devices have chip data hardcoded in the device id table
2848                  */
2849                 mtd->erasesize = type->erasesize;
2850                 mtd->writesize = type->pagesize;
2851                 mtd->oobsize = mtd->writesize / 32;
2852                 busw = type->options & NAND_BUSWIDTH_16;
2853         }
2854
2855         /* Try to identify manufacturer */
2856         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2857                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2858                         break;
2859         }
2860
2861         /*
2862          * Check, if buswidth is correct. Hardware drivers should set
2863          * chip correct !
2864          */
2865         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2866                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2867                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2868                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2869                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2870                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2871                        busw ? 16 : 8);
2872                 return ERR_PTR(-EINVAL);
2873         }
2874
2875         /* Calculate the address shift from the page size */
2876         chip->page_shift = ffs(mtd->writesize) - 1;
2877         /* Convert chipsize to number of pages per chip -1. */
2878         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2879
2880         chip->bbt_erase_shift = chip->phys_erase_shift =
2881                 ffs(mtd->erasesize) - 1;
2882         if (chip->chipsize & 0xffffffff)
2883                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2884         else
2885                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2886
2887         /* Set the bad block position */
2888         chip->badblockpos = mtd->writesize > 512 ?
2889                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2890         chip->badblockbits = 8;
2891
2892         /* Get chip options, preserve non chip based options */
2893         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2894         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2895
2896         /*
2897          * Set chip as a default. Board drivers can override it, if necessary
2898          */
2899         chip->options |= NAND_NO_AUTOINCR;
2900
2901         /* Check if chip is a not a samsung device. Do not clear the
2902          * options for chips which are not having an extended id.
2903          */
2904         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2905                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2906
2907         /* Check for AND chips with 4 page planes */
2908         if (chip->options & NAND_4PAGE_ARRAY)
2909                 chip->erase_cmd = multi_erase_cmd;
2910         else
2911                 chip->erase_cmd = single_erase_cmd;
2912
2913         /* Do not replace user supplied command function ! */
2914         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2915                 chip->cmdfunc = nand_command_lp;
2916
2917         printk(KERN_INFO "NAND device: Manufacturer ID:"
2918                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2919                nand_manuf_ids[maf_idx].name, type->name);
2920
2921         return type;
2922 }
2923
2924 /**
2925  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2926  * @mtd:             MTD device structure
2927  * @maxchips:        Number of chips to scan for
2928  * @table:           Alternative NAND ID table
2929  *
2930  * This is the first phase of the normal nand_scan() function. It
2931  * reads the flash ID and sets up MTD fields accordingly.
2932  *
2933  * The mtd->owner field must be set to the module of the caller.
2934  */
2935 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2936                     struct nand_flash_dev *table)
2937 {
2938         int i, busw, nand_maf_id;
2939         struct nand_chip *chip = mtd->priv;
2940         struct nand_flash_dev *type;
2941
2942         /* Get buswidth to select the correct functions */
2943         busw = chip->options & NAND_BUSWIDTH_16;
2944         /* Set the default functions */
2945         nand_set_defaults(chip, busw);
2946
2947         /* Read the flash type */
2948         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table);
2949
2950         if (IS_ERR(type)) {
2951                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
2952                         printk(KERN_WARNING "No NAND device found.\n");
2953                 chip->select_chip(mtd, -1);
2954                 return PTR_ERR(type);
2955         }
2956
2957         /* Check for a chip array */
2958         for (i = 1; i < maxchips; i++) {
2959                 chip->select_chip(mtd, i);
2960                 /* See comment in nand_get_flash_type for reset */
2961                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2962                 /* Send the command for reading device ID */
2963                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2964                 /* Read manufacturer and device IDs */
2965                 if (nand_maf_id != chip->read_byte(mtd) ||
2966                     type->id != chip->read_byte(mtd))
2967                         break;
2968         }
2969         if (i > 1)
2970                 printk(KERN_INFO "%d NAND chips detected\n", i);
2971
2972         /* Store the number of chips and calc total size for mtd */
2973         chip->numchips = i;
2974         mtd->size = i * chip->chipsize;
2975
2976         return 0;
2977 }
2978
2979
2980 /**
2981  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2982  * @mtd:            MTD device structure
2983  *
2984  * This is the second phase of the normal nand_scan() function. It
2985  * fills out all the uninitialized function pointers with the defaults
2986  * and scans for a bad block table if appropriate.
2987  */
2988 int nand_scan_tail(struct mtd_info *mtd)
2989 {
2990         int i;
2991         struct nand_chip *chip = mtd->priv;
2992
2993         if (!(chip->options & NAND_OWN_BUFFERS))
2994                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2995         if (!chip->buffers)
2996                 return -ENOMEM;
2997
2998         /* Set the internal oob buffer location, just after the page data */
2999         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3000
3001         /*
3002          * If no default placement scheme is given, select an appropriate one
3003          */
3004         if (!chip->ecc.layout) {
3005                 switch (mtd->oobsize) {
3006                 case 8:
3007                         chip->ecc.layout = &nand_oob_8;
3008                         break;
3009                 case 16:
3010                         chip->ecc.layout = &nand_oob_16;
3011                         break;
3012                 case 64:
3013                         chip->ecc.layout = &nand_oob_64;
3014                         break;
3015                 case 128:
3016                         chip->ecc.layout = &nand_oob_128;
3017                         break;
3018                 default:
3019                         printk(KERN_WARNING "No oob scheme defined for "
3020                                "oobsize %d\n", mtd->oobsize);
3021                         BUG();
3022                 }
3023         }
3024
3025         if (!chip->write_page)
3026                 chip->write_page = nand_write_page;
3027
3028         /*
3029          * check ECC mode, default to software if 3byte/512byte hardware ECC is
3030          * selected and we have 256 byte pagesize fallback to software ECC
3031          */
3032
3033         switch (chip->ecc.mode) {
3034         case NAND_ECC_HW_OOB_FIRST:
3035                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3036                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3037                      !chip->ecc.hwctl) {
3038                         printk(KERN_WARNING "No ECC functions supplied; "
3039                                "Hardware ECC not possible\n");
3040                         BUG();
3041                 }
3042                 if (!chip->ecc.read_page)
3043                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3044
3045         case NAND_ECC_HW:
3046                 /* Use standard hwecc read page function ? */
3047                 if (!chip->ecc.read_page)
3048                         chip->ecc.read_page = nand_read_page_hwecc;
3049                 if (!chip->ecc.write_page)
3050                         chip->ecc.write_page = nand_write_page_hwecc;
3051                 if (!chip->ecc.read_page_raw)
3052                         chip->ecc.read_page_raw = nand_read_page_raw;
3053                 if (!chip->ecc.write_page_raw)
3054                         chip->ecc.write_page_raw = nand_write_page_raw;
3055                 if (!chip->ecc.read_oob)
3056                         chip->ecc.read_oob = nand_read_oob_std;
3057                 if (!chip->ecc.write_oob)
3058                         chip->ecc.write_oob = nand_write_oob_std;
3059
3060         case NAND_ECC_HW_SYNDROME:
3061                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3062                      !chip->ecc.hwctl) &&
3063                     (!chip->ecc.read_page ||
3064                      chip->ecc.read_page == nand_read_page_hwecc ||
3065                      !chip->ecc.write_page ||
3066                      chip->ecc.write_page == nand_write_page_hwecc)) {
3067                         printk(KERN_WARNING "No ECC functions supplied; "
3068                                "Hardware ECC not possible\n");
3069                         BUG();
3070                 }
3071                 /* Use standard syndrome read/write page function ? */
3072                 if (!chip->ecc.read_page)
3073                         chip->ecc.read_page = nand_read_page_syndrome;
3074                 if (!chip->ecc.write_page)
3075                         chip->ecc.write_page = nand_write_page_syndrome;
3076                 if (!chip->ecc.read_page_raw)
3077                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3078                 if (!chip->ecc.write_page_raw)
3079                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3080                 if (!chip->ecc.read_oob)
3081                         chip->ecc.read_oob = nand_read_oob_syndrome;
3082                 if (!chip->ecc.write_oob)
3083                         chip->ecc.write_oob = nand_write_oob_syndrome;
3084
3085                 if (mtd->writesize >= chip->ecc.size)
3086                         break;
3087                 printk(KERN_WARNING "%d byte HW ECC not possible on "
3088                        "%d byte page size, fallback to SW ECC\n",
3089                        chip->ecc.size, mtd->writesize);
3090                 chip->ecc.mode = NAND_ECC_SOFT;
3091
3092         case NAND_ECC_SOFT:
3093                 chip->ecc.calculate = nand_calculate_ecc;
3094                 chip->ecc.correct = nand_correct_data;
3095                 chip->ecc.read_page = nand_read_page_swecc;
3096                 chip->ecc.read_subpage = nand_read_subpage;
3097                 chip->ecc.write_page = nand_write_page_swecc;
3098                 chip->ecc.read_page_raw = nand_read_page_raw;
3099                 chip->ecc.write_page_raw = nand_write_page_raw;
3100                 chip->ecc.read_oob = nand_read_oob_std;
3101                 chip->ecc.write_oob = nand_write_oob_std;
3102                 if (!chip->ecc.size)
3103                         chip->ecc.size = 256;
3104                 chip->ecc.bytes = 3;
3105                 break;
3106
3107         case NAND_ECC_NONE:
3108                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3109                        "This is not recommended !!\n");
3110                 chip->ecc.read_page = nand_read_page_raw;
3111                 chip->ecc.write_page = nand_write_page_raw;
3112                 chip->ecc.read_oob = nand_read_oob_std;
3113                 chip->ecc.read_page_raw = nand_read_page_raw;
3114                 chip->ecc.write_page_raw = nand_write_page_raw;
3115                 chip->ecc.write_oob = nand_write_oob_std;
3116                 chip->ecc.size = mtd->writesize;
3117                 chip->ecc.bytes = 0;
3118                 break;
3119
3120         default:
3121                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3122                        chip->ecc.mode);
3123                 BUG();
3124         }
3125
3126         /*
3127          * The number of bytes available for a client to place data into
3128          * the out of band area
3129          */
3130         chip->ecc.layout->oobavail = 0;
3131         for (i = 0; chip->ecc.layout->oobfree[i].length
3132                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3133                 chip->ecc.layout->oobavail +=
3134                         chip->ecc.layout->oobfree[i].length;
3135         mtd->oobavail = chip->ecc.layout->oobavail;
3136
3137         /*
3138          * Set the number of read / write steps for one page depending on ECC
3139          * mode
3140          */
3141         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3142         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3143                 printk(KERN_WARNING "Invalid ecc parameters\n");
3144                 BUG();
3145         }
3146         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3147
3148         /*
3149          * Allow subpage writes up to ecc.steps. Not possible for MLC
3150          * FLASH.
3151          */
3152         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3153             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3154                 switch(chip->ecc.steps) {
3155                 case 2:
3156                         mtd->subpage_sft = 1;
3157                         break;
3158                 case 4:
3159                 case 8:
3160                 case 16:
3161                         mtd->subpage_sft = 2;
3162                         break;
3163                 }
3164         }
3165         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3166
3167         /* Initialize state */
3168         chip->state = FL_READY;
3169
3170         /* De-select the device */
3171         chip->select_chip(mtd, -1);
3172
3173         /* Invalidate the pagebuffer reference */
3174         chip->pagebuf = -1;
3175
3176         /* Fill in remaining MTD driver data */
3177         mtd->type = MTD_NANDFLASH;
3178         mtd->flags = MTD_CAP_NANDFLASH;
3179         mtd->erase = nand_erase;
3180         mtd->point = NULL;
3181         mtd->unpoint = NULL;
3182         mtd->read = nand_read;
3183         mtd->write = nand_write;
3184         mtd->panic_write = panic_nand_write;
3185         mtd->read_oob = nand_read_oob;
3186         mtd->write_oob = nand_write_oob;
3187         mtd->sync = nand_sync;
3188         mtd->lock = NULL;
3189         mtd->unlock = NULL;
3190         mtd->suspend = nand_suspend;
3191         mtd->resume = nand_resume;
3192         mtd->block_isbad = nand_block_isbad;
3193         mtd->block_markbad = nand_block_markbad;
3194
3195         /* propagate ecc.layout to mtd_info */
3196         mtd->ecclayout = chip->ecc.layout;
3197
3198         /* Check, if we should skip the bad block table scan */
3199         if (chip->options & NAND_SKIP_BBTSCAN)
3200                 return 0;
3201
3202         /* Build bad block table */
3203         return chip->scan_bbt(mtd);
3204 }
3205
3206 /* is_module_text_address() isn't exported, and it's mostly a pointless
3207    test if this is a module _anyway_ -- they'd have to try _really_ hard
3208    to call us from in-kernel code if the core NAND support is modular. */
3209 #ifdef MODULE
3210 #define caller_is_module() (1)
3211 #else
3212 #define caller_is_module() \
3213         is_module_text_address((unsigned long)__builtin_return_address(0))
3214 #endif
3215
3216 /**
3217  * nand_scan - [NAND Interface] Scan for the NAND device
3218  * @mtd:        MTD device structure
3219  * @maxchips:   Number of chips to scan for
3220  *
3221  * This fills out all the uninitialized function pointers
3222  * with the defaults.
3223  * The flash ID is read and the mtd/chip structures are
3224  * filled with the appropriate values.
3225  * The mtd->owner field must be set to the module of the caller
3226  *
3227  */
3228 int nand_scan(struct mtd_info *mtd, int maxchips)
3229 {
3230         int ret;
3231
3232         /* Many callers got this wrong, so check for it for a while... */
3233         if (!mtd->owner && caller_is_module()) {
3234                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3235                                 __func__);
3236                 BUG();
3237         }
3238
3239         ret = nand_scan_ident(mtd, maxchips, NULL);
3240         if (!ret)
3241                 ret = nand_scan_tail(mtd);
3242         return ret;
3243 }
3244
3245 /**
3246  * nand_release - [NAND Interface] Free resources held by the NAND device
3247  * @mtd:        MTD device structure
3248 */
3249 void nand_release(struct mtd_info *mtd)
3250 {
3251         struct nand_chip *chip = mtd->priv;
3252
3253 #ifdef CONFIG_MTD_PARTITIONS
3254         /* Deregister partitions */
3255         del_mtd_partitions(mtd);
3256 #endif
3257         /* Deregister the device */
3258         del_mtd_device(mtd);
3259
3260         /* Free bad block table memory */
3261         kfree(chip->bbt);
3262         if (!(chip->options & NAND_OWN_BUFFERS))
3263                 kfree(chip->buffers);
3264 }
3265
3266 EXPORT_SYMBOL_GPL(nand_lock);
3267 EXPORT_SYMBOL_GPL(nand_unlock);
3268 EXPORT_SYMBOL_GPL(nand_scan);
3269 EXPORT_SYMBOL_GPL(nand_scan_ident);
3270 EXPORT_SYMBOL_GPL(nand_scan_tail);
3271 EXPORT_SYMBOL_GPL(nand_release);
3272
3273 static int __init nand_base_init(void)
3274 {
3275         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3276         return 0;
3277 }
3278
3279 static void __exit nand_base_exit(void)
3280 {
3281         led_trigger_unregister_simple(nand_led_trigger);
3282 }
3283
3284 module_init(nand_base_init);
3285 module_exit(nand_base_exit);
3286
3287 MODULE_LICENSE("GPL");
3288 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3289 MODULE_DESCRIPTION("Generic NAND flash driver code");