drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34 #include "cimax2.h"
  35 #include "cx23888-ir.h"
  36 #include "cx23885-ir.h"
  37 #include "cx23885-input.h"
  38
  39 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  40 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
  41 MODULE_LICENSE("GPL");
  42
  43 static unsigned int debug;
  44 module_param(debug, int, 0644);
  45 MODULE_PARM_DESC(debug, "enable debug messages");
  46
  47 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  48 module_param_array(card,  int, NULL, 0444);
  49 MODULE_PARM_DESC(card, "card type");
  50
  51 #define dprintk(level, fmt, arg...)\
  52         do { if (debug >= level)\
  53                 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  54         } while (0)
  55
  56 static unsigned int cx23885_devcount;
  57
  58 static DEFINE_MUTEX(devlist);
  59 LIST_HEAD(cx23885_devlist);
  60
  61 #define NO_SYNC_LINE (-1U)
  62
  63 /* FIXME, these allocations will change when
  64  * analog arrives. The be reviewed.
  65  * CX23887 Assumptions
  66  * 1 line = 16 bytes of CDT
  67  * cmds size = 80
  68  * cdt size = 16 * linesize
  69  * iqsize = 64
  70  * maxlines = 6
  71  *
  72  * Address Space:
  73  * 0x00000000 0x00008fff FIFO clusters
  74  * 0x00010000 0x000104af Channel Management Data Structures
  75  * 0x000104b0 0x000104ff Free
  76  * 0x00010500 0x000108bf 15 channels * iqsize
  77  * 0x000108c0 0x000108ff Free
  78  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  79  *                       15 channels * (iqsize + (maxlines * linesize))
  80  * 0x00010ea0 0x00010xxx Free
  81  */
  82
  83 static struct sram_channel cx23885_sram_channels[] = {
  84         [SRAM_CH01] = {
  85                 .name           = "VID A",
  86                 .cmds_start     = 0x10000,
  87                 .ctrl_start     = 0x10380,
  88                 .cdt            = 0x104c0,
  89                 .fifo_start     = 0x40,
  90                 .fifo_size      = 0x2800,
  91                 .ptr1_reg       = DMA1_PTR1,
  92                 .ptr2_reg       = DMA1_PTR2,
  93                 .cnt1_reg       = DMA1_CNT1,
  94                 .cnt2_reg       = DMA1_CNT2,
  95         },
  96         [SRAM_CH02] = {
  97                 .name           = "ch2",
  98                 .cmds_start     = 0x0,
  99                 .ctrl_start     = 0x0,
 100                 .cdt            = 0x0,
 101                 .fifo_start     = 0x0,
 102                 .fifo_size      = 0x0,
 103                 .ptr1_reg       = DMA2_PTR1,
 104                 .ptr2_reg       = DMA2_PTR2,
 105                 .cnt1_reg       = DMA2_CNT1,
 106                 .cnt2_reg       = DMA2_CNT2,
 107         },
 108         [SRAM_CH03] = {
 109                 .name           = "TS1 B",
 110                 .cmds_start     = 0x100A0,
 111                 .ctrl_start     = 0x10400,
 112                 .cdt            = 0x10580,
 113                 .fifo_start     = 0x5000,
 114                 .fifo_size      = 0x1000,
 115                 .ptr1_reg       = DMA3_PTR1,
 116                 .ptr2_reg       = DMA3_PTR2,
 117                 .cnt1_reg       = DMA3_CNT1,
 118                 .cnt2_reg       = DMA3_CNT2,
 119         },
 120         [SRAM_CH04] = {
 121                 .name           = "ch4",
 122                 .cmds_start     = 0x0,
 123                 .ctrl_start     = 0x0,
 124                 .cdt            = 0x0,
 125                 .fifo_start     = 0x0,
 126                 .fifo_size      = 0x0,
 127                 .ptr1_reg       = DMA4_PTR1,
 128                 .ptr2_reg       = DMA4_PTR2,
 129                 .cnt1_reg       = DMA4_CNT1,
 130                 .cnt2_reg       = DMA4_CNT2,
 131         },
 132         [SRAM_CH05] = {
 133                 .name           = "ch5",
 134                 .cmds_start     = 0x0,
 135                 .ctrl_start     = 0x0,
 136                 .cdt            = 0x0,
 137                 .fifo_start     = 0x0,
 138                 .fifo_size      = 0x0,
 139                 .ptr1_reg       = DMA5_PTR1,
 140                 .ptr2_reg       = DMA5_PTR2,
 141                 .cnt1_reg       = DMA5_CNT1,
 142                 .cnt2_reg       = DMA5_CNT2,
 143         },
 144         [SRAM_CH06] = {
 145                 .name           = "TS2 C",
 146                 .cmds_start     = 0x10140,
 147                 .ctrl_start     = 0x10440,
 148                 .cdt            = 0x105e0,
 149                 .fifo_start     = 0x6000,
 150                 .fifo_size      = 0x1000,
 151                 .ptr1_reg       = DMA5_PTR1,
 152                 .ptr2_reg       = DMA5_PTR2,
 153                 .cnt1_reg       = DMA5_CNT1,
 154                 .cnt2_reg       = DMA5_CNT2,
 155         },
 156         [SRAM_CH07] = {
 157                 .name           = "ch7",
 158                 .cmds_start     = 0x0,
 159                 .ctrl_start     = 0x0,
 160                 .cdt            = 0x0,
 161                 .fifo_start     = 0x0,
 162                 .fifo_size      = 0x0,
 163                 .ptr1_reg       = DMA6_PTR1,
 164                 .ptr2_reg       = DMA6_PTR2,
 165                 .cnt1_reg       = DMA6_CNT1,
 166                 .cnt2_reg       = DMA6_CNT2,
 167         },
 168         [SRAM_CH08] = {
 169                 .name           = "ch8",
 170                 .cmds_start     = 0x0,
 171                 .ctrl_start     = 0x0,
 172                 .cdt            = 0x0,
 173                 .fifo_start     = 0x0,
 174                 .fifo_size      = 0x0,
 175                 .ptr1_reg       = DMA7_PTR1,
 176                 .ptr2_reg       = DMA7_PTR2,
 177                 .cnt1_reg       = DMA7_CNT1,
 178                 .cnt2_reg       = DMA7_CNT2,
 179         },
 180         [SRAM_CH09] = {
 181                 .name           = "ch9",
 182                 .cmds_start     = 0x0,
 183                 .ctrl_start     = 0x0,
 184                 .cdt            = 0x0,
 185                 .fifo_start     = 0x0,
 186                 .fifo_size      = 0x0,
 187                 .ptr1_reg       = DMA8_PTR1,
 188                 .ptr2_reg       = DMA8_PTR2,
 189                 .cnt1_reg       = DMA8_CNT1,
 190                 .cnt2_reg       = DMA8_CNT2,
 191         },
 192 };
 193
 194 static struct sram_channel cx23887_sram_channels[] = {
 195         [SRAM_CH01] = {
 196                 .name           = "VID A",
 197                 .cmds_start     = 0x10000,
 198                 .ctrl_start     = 0x105b0,
 199                 .cdt            = 0x107b0,
 200                 .fifo_start     = 0x40,
 201                 .fifo_size      = 0x2800,
 202                 .ptr1_reg       = DMA1_PTR1,
 203                 .ptr2_reg       = DMA1_PTR2,
 204                 .cnt1_reg       = DMA1_CNT1,
 205                 .cnt2_reg       = DMA1_CNT2,
 206         },
 207         [SRAM_CH02] = {
 208                 .name           = "ch2",
 209                 .cmds_start     = 0x0,
 210                 .ctrl_start     = 0x0,
 211                 .cdt            = 0x0,
 212                 .fifo_start     = 0x0,
 213                 .fifo_size      = 0x0,
 214                 .ptr1_reg       = DMA2_PTR1,
 215                 .ptr2_reg       = DMA2_PTR2,
 216                 .cnt1_reg       = DMA2_CNT1,
 217                 .cnt2_reg       = DMA2_CNT2,
 218         },
 219         [SRAM_CH03] = {
 220                 .name           = "TS1 B",
 221                 .cmds_start     = 0x100A0,
 222                 .ctrl_start     = 0x10630,
 223                 .cdt            = 0x10870,
 224                 .fifo_start     = 0x5000,
 225                 .fifo_size      = 0x1000,
 226                 .ptr1_reg       = DMA3_PTR1,
 227                 .ptr2_reg       = DMA3_PTR2,
 228                 .cnt1_reg       = DMA3_CNT1,
 229                 .cnt2_reg       = DMA3_CNT2,
 230         },
 231         [SRAM_CH04] = {
 232                 .name           = "ch4",
 233                 .cmds_start     = 0x0,
 234                 .ctrl_start     = 0x0,
 235                 .cdt            = 0x0,
 236                 .fifo_start     = 0x0,
 237                 .fifo_size      = 0x0,
 238                 .ptr1_reg       = DMA4_PTR1,
 239                 .ptr2_reg       = DMA4_PTR2,
 240                 .cnt1_reg       = DMA4_CNT1,
 241                 .cnt2_reg       = DMA4_CNT2,
 242         },
 243         [SRAM_CH05] = {
 244                 .name           = "ch5",
 245                 .cmds_start     = 0x0,
 246                 .ctrl_start     = 0x0,
 247                 .cdt            = 0x0,
 248                 .fifo_start     = 0x0,
 249                 .fifo_size      = 0x0,
 250                 .ptr1_reg       = DMA5_PTR1,
 251                 .ptr2_reg       = DMA5_PTR2,
 252                 .cnt1_reg       = DMA5_CNT1,
 253                 .cnt2_reg       = DMA5_CNT2,
 254         },
 255         [SRAM_CH06] = {
 256                 .name           = "TS2 C",
 257                 .cmds_start     = 0x10140,
 258                 .ctrl_start     = 0x10670,
 259                 .cdt            = 0x108d0,
 260                 .fifo_start     = 0x6000,
 261                 .fifo_size      = 0x1000,
 262                 .ptr1_reg       = DMA5_PTR1,
 263                 .ptr2_reg       = DMA5_PTR2,
 264                 .cnt1_reg       = DMA5_CNT1,
 265                 .cnt2_reg       = DMA5_CNT2,
 266         },
 267         [SRAM_CH07] = {
 268                 .name           = "ch7",
 269                 .cmds_start     = 0x0,
 270                 .ctrl_start     = 0x0,
 271                 .cdt            = 0x0,
 272                 .fifo_start     = 0x0,
 273                 .fifo_size      = 0x0,
 274                 .ptr1_reg       = DMA6_PTR1,
 275                 .ptr2_reg       = DMA6_PTR2,
 276                 .cnt1_reg       = DMA6_CNT1,
 277                 .cnt2_reg       = DMA6_CNT2,
 278         },
 279         [SRAM_CH08] = {
 280                 .name           = "ch8",
 281                 .cmds_start     = 0x0,
 282                 .ctrl_start     = 0x0,
 283                 .cdt            = 0x0,
 284                 .fifo_start     = 0x0,
 285                 .fifo_size      = 0x0,
 286                 .ptr1_reg       = DMA7_PTR1,
 287                 .ptr2_reg       = DMA7_PTR2,
 288                 .cnt1_reg       = DMA7_CNT1,
 289                 .cnt2_reg       = DMA7_CNT2,
 290         },
 291         [SRAM_CH09] = {
 292                 .name           = "ch9",
 293                 .cmds_start     = 0x0,
 294                 .ctrl_start     = 0x0,
 295                 .cdt            = 0x0,
 296                 .fifo_start     = 0x0,
 297                 .fifo_size      = 0x0,
 298                 .ptr1_reg       = DMA8_PTR1,
 299                 .ptr2_reg       = DMA8_PTR2,
 300                 .cnt1_reg       = DMA8_CNT1,
 301                 .cnt2_reg       = DMA8_CNT2,
 302         },
 303 };
 304
 305 static int cx23885_risc_decode(u32 risc)
 306 {
 307         static char *instr[16] = {
 308                 [RISC_SYNC    >> 28] = "sync",
 309                 [RISC_WRITE   >> 28] = "write",
 310                 [RISC_WRITEC  >> 28] = "writec",
 311                 [RISC_READ    >> 28] = "read",
 312                 [RISC_READC   >> 28] = "readc",
 313                 [RISC_JUMP    >> 28] = "jump",
 314                 [RISC_SKIP    >> 28] = "skip",
 315                 [RISC_WRITERM >> 28] = "writerm",
 316                 [RISC_WRITECM >> 28] = "writecm",
 317                 [RISC_WRITECR >> 28] = "writecr",
 318         };
 319         static int incr[16] = {
 320                 [RISC_WRITE   >> 28] = 3,
 321                 [RISC_JUMP    >> 28] = 3,
 322                 [RISC_SKIP    >> 28] = 1,
 323                 [RISC_SYNC    >> 28] = 1,
 324                 [RISC_WRITERM >> 28] = 3,
 325                 [RISC_WRITECM >> 28] = 3,
 326                 [RISC_WRITECR >> 28] = 4,
 327         };
 328         static char *bits[] = {
 329                 "12",   "13",   "14",   "resync",
 330                 "cnt0", "cnt1", "18",   "19",
 331                 "20",   "21",   "22",   "23",
 332                 "irq1", "irq2", "eol",  "sol",
 333         };
 334         int i;
 335
 336         printk("0x%08x [ %s", risc,
 337                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 338         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 339                 if (risc & (1 << (i + 12)))
 340                         printk(" %s", bits[i]);
 341         printk(" count=%d ]\n", risc & 0xfff);
 342         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 343 }
 344
 345 void cx23885_wakeup(struct cx23885_tsport *port,
 346                            struct cx23885_dmaqueue *q, u32 count)
 347 {
 348         struct cx23885_dev *dev = port->dev;
 349         struct cx23885_buffer *buf;
 350         int bc;
 351
 352         for (bc = 0;; bc++) {
 353                 if (list_empty(&q->active))
 354                         break;
 355                 buf = list_entry(q->active.next,
 356                                  struct cx23885_buffer, vb.queue);
 357
 358                 /* count comes from the hw and is is 16bit wide --
 359                  * this trick handles wrap-arounds correctly for
 360                  * up to 32767 buffers in flight... */
 361                 if ((s16) (count - buf->count) < 0)
 362                         break;
 363
 364                 do_gettimeofday(&buf->vb.ts);
 365                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 366                         count, buf->count);
 367                 buf->vb.state = VIDEOBUF_DONE;
 368                 list_del(&buf->vb.queue);
 369                 wake_up(&buf->vb.done);
 370         }
 371         if (list_empty(&q->active))
 372                 del_timer(&q->timeout);
 373         else
 374                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 375         if (bc != 1)
 376                 printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
 377                        __func__, bc);
 378 }
 379
 380 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 381                                       struct sram_channel *ch,
 382                                       unsigned int bpl, u32 risc)
 383 {
 384         unsigned int i, lines;
 385         u32 cdt;
 386
 387         if (ch->cmds_start == 0) {
 388                 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
 389                         ch->name);
 390                 cx_write(ch->ptr1_reg, 0);
 391                 cx_write(ch->ptr2_reg, 0);
 392                 cx_write(ch->cnt2_reg, 0);
 393                 cx_write(ch->cnt1_reg, 0);
 394                 return 0;
 395         } else {
 396                 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
 397                         ch->name);
 398         }
 399
 400         bpl   = (bpl + 7) & ~7; /* alignment */
 401         cdt   = ch->cdt;
 402         lines = ch->fifo_size / bpl;
 403         if (lines > 6)
 404                 lines = 6;
 405         BUG_ON(lines < 2);
 406
 407         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 408         cx_write(8 + 4, 8);
 409         cx_write(8 + 8, 0);
 410
 411         /* write CDT */
 412         for (i = 0; i < lines; i++) {
 413                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
 414                         ch->fifo_start + bpl*i);
 415                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 416                 cx_write(cdt + 16*i +  4, 0);
 417                 cx_write(cdt + 16*i +  8, 0);
 418                 cx_write(cdt + 16*i + 12, 0);
 419         }
 420
 421         /* write CMDS */
 422         if (ch->jumponly)
 423                 cx_write(ch->cmds_start + 0, 8);
 424         else
 425                 cx_write(ch->cmds_start + 0, risc);
 426         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 427         cx_write(ch->cmds_start +  8, cdt);
 428         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 429         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 430         if (ch->jumponly)
 431                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 432         else
 433                 cx_write(ch->cmds_start + 20, 64 >> 2);
 434         for (i = 24; i < 80; i += 4)
 435                 cx_write(ch->cmds_start + i, 0);
 436
 437         /* fill registers */
 438         cx_write(ch->ptr1_reg, ch->fifo_start);
 439         cx_write(ch->ptr2_reg, cdt);
 440         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 441         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 442
 443         dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 444                 dev->bridge,
 445                 ch->name,
 446                 bpl,
 447                 lines);
 448
 449         return 0;
 450 }
 451
 452 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 453                                       struct sram_channel *ch)
 454 {
 455         static char *name[] = {
 456                 "init risc lo",
 457                 "init risc hi",
 458                 "cdt base",
 459                 "cdt size",
 460                 "iq base",
 461                 "iq size",
 462                 "risc pc lo",
 463                 "risc pc hi",
 464                 "iq wr ptr",
 465                 "iq rd ptr",
 466                 "cdt current",
 467                 "pci target lo",
 468                 "pci target hi",
 469                 "line / byte",
 470         };
 471         u32 risc;
 472         unsigned int i, j, n;
 473
 474         printk(KERN_WARNING "%s: %s - dma channel status dump\n",
 475                dev->name, ch->name);
 476         for (i = 0; i < ARRAY_SIZE(name); i++)
 477                 printk(KERN_WARNING "%s:   cmds: %-15s: 0x%08x\n",
 478                        dev->name, name[i],
 479                        cx_read(ch->cmds_start + 4*i));
 480
 481         for (i = 0; i < 4; i++) {
 482                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 483                 printk(KERN_WARNING "%s:   risc%d: ", dev->name, i);
 484                 cx23885_risc_decode(risc);
 485         }
 486         for (i = 0; i < (64 >> 2); i += n) {
 487                 risc = cx_read(ch->ctrl_start + 4 * i);
 488                 /* No consideration for bits 63-32 */
 489
 490                 printk(KERN_WARNING "%s:   (0x%08x) iq %x: ", dev->name,
 491                        ch->ctrl_start + 4 * i, i);
 492                 n = cx23885_risc_decode(risc);
 493                 for (j = 1; j < n; j++) {
 494                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 495                         printk(KERN_WARNING "%s:   iq %x: 0x%08x [ arg #%d ]\n",
 496                                dev->name, i+j, risc, j);
 497                 }
 498         }
 499
 500         printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
 501                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 502         printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
 503                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 504         printk(KERN_WARNING "%s:   ptr1_reg: 0x%08x\n",
 505                dev->name, cx_read(ch->ptr1_reg));
 506         printk(KERN_WARNING "%s:   ptr2_reg: 0x%08x\n",
 507                dev->name, cx_read(ch->ptr2_reg));
 508         printk(KERN_WARNING "%s:   cnt1_reg: 0x%08x\n",
 509                dev->name, cx_read(ch->cnt1_reg));
 510         printk(KERN_WARNING "%s:   cnt2_reg: 0x%08x\n",
 511                dev->name, cx_read(ch->cnt2_reg));
 512 }
 513
 514 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 515                                 struct btcx_riscmem *risc)
 516 {
 517         struct cx23885_dev *dev = port->dev;
 518         unsigned int i, j, n;
 519
 520         printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
 521                dev->name, risc->cpu, (unsigned long)risc->dma);
 522         for (i = 0; i < (risc->size >> 2); i += n) {
 523                 printk(KERN_INFO "%s:   %04d: ", dev->name, i);
 524                 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
 525                 for (j = 1; j < n; j++)
 526                         printk(KERN_INFO "%s:   %04d: 0x%08x [ arg #%d ]\n",
 527                                dev->name, i + j, risc->cpu[i + j], j);
 528                 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
 529                         break;
 530         }
 531 }
 532
 533 static void cx23885_shutdown(struct cx23885_dev *dev)
 534 {
 535         /* disable RISC controller */
 536         cx_write(DEV_CNTRL2, 0);
 537
 538         /* Disable all IR activity */
 539         cx_write(IR_CNTRL_REG, 0);
 540
 541         /* Disable Video A/B activity */
 542         cx_write(VID_A_DMA_CTL, 0);
 543         cx_write(VID_B_DMA_CTL, 0);
 544         cx_write(VID_C_DMA_CTL, 0);
 545
 546         /* Disable Audio activity */
 547         cx_write(AUD_INT_DMA_CTL, 0);
 548         cx_write(AUD_EXT_DMA_CTL, 0);
 549
 550         /* Disable Serial port */
 551         cx_write(UART_CTL, 0);
 552
 553         /* Disable Interrupts */
 554         cx_write(PCI_INT_MSK, 0);
 555         cx_write(VID_A_INT_MSK, 0);
 556         cx_write(VID_B_INT_MSK, 0);
 557         cx_write(VID_C_INT_MSK, 0);
 558         cx_write(AUDIO_INT_INT_MSK, 0);
 559         cx_write(AUDIO_EXT_INT_MSK, 0);
 560
 561 }
 562
 563 static void cx23885_reset(struct cx23885_dev *dev)
 564 {
 565         dprintk(1, "%s()\n", __func__);
 566
 567         cx23885_shutdown(dev);
 568
 569         cx_write(PCI_INT_STAT, 0xffffffff);
 570         cx_write(VID_A_INT_STAT, 0xffffffff);
 571         cx_write(VID_B_INT_STAT, 0xffffffff);
 572         cx_write(VID_C_INT_STAT, 0xffffffff);
 573         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 574         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 575         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 576         cx_write(PAD_CTRL, 0x00500300);
 577
 578         mdelay(100);
 579
 580         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 581                 720*4, 0);
 582         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 583         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 584                 188*4, 0);
 585         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 586         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 587         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 588                 188*4, 0);
 589         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 590         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 591         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 592
 593         cx23885_gpio_setup(dev);
 594 }
 595
 596
 597 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 598 {
 599         dprintk(1, "%s()\n", __func__);
 600
 601         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 602          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 603          * occur on the cx23887 bridge.
 604          */
 605         if (dev->bridge == CX23885_BRIDGE_885)
 606                 cx_clear(RDR_TLCTL0, 1 << 4);
 607
 608         return 0;
 609 }
 610
 611 static int get_resources(struct cx23885_dev *dev)
 612 {
 613         if (request_mem_region(pci_resource_start(dev->pci, 0),
 614                                pci_resource_len(dev->pci, 0),
 615                                dev->name))
 616                 return 0;
 617
 618         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 619                 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
 620
 621         return -EBUSY;
 622 }
 623
 624 static void cx23885_timeout(unsigned long data);
 625 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 626                                 u32 reg, u32 mask, u32 value);
 627
 628 static int cx23885_init_tsport(struct cx23885_dev *dev,
 629         struct cx23885_tsport *port, int portno)
 630 {
 631         dprintk(1, "%s(portno=%d)\n", __func__, portno);
 632
 633         /* Transport bus init dma queue  - Common settings */
 634         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 635         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 636         port->vld_misc_val       = 0x0;
 637         port->hw_sop_ctrl_val    = (0x47 << 16 | 188 << 4);
 638
 639         spin_lock_init(&port->slock);
 640         port->dev = dev;
 641         port->nr = portno;
 642
 643         INIT_LIST_HEAD(&port->mpegq.active);
 644         INIT_LIST_HEAD(&port->mpegq.queued);
 645         port->mpegq.timeout.function = cx23885_timeout;
 646         port->mpegq.timeout.data = (unsigned long)port;
 647         init_timer(&port->mpegq.timeout);
 648
 649         mutex_init(&port->frontends.lock);
 650         INIT_LIST_HEAD(&port->frontends.felist);
 651         port->frontends.active_fe_id = 0;
 652
 653         /* This should be hardcoded allow a single frontend
 654          * attachment to this tsport, keeping the -dvb.c
 655          * code clean and safe.
 656          */
 657         if (!port->num_frontends)
 658                 port->num_frontends = 1;
 659
 660         switch (portno) {
 661         case 1:
 662                 port->reg_gpcnt          = VID_B_GPCNT;
 663                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 664                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 665                 port->reg_lngth          = VID_B_LNGTH;
 666                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 667                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 668                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 669                 port->reg_sop_status     = VID_B_SOP_STATUS;
 670                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 671                 port->reg_vld_misc       = VID_B_VLD_MISC;
 672                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 673                 port->reg_src_sel        = VID_B_SRC_SEL;
 674                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 675                 port->reg_ts_int_stat    = VID_B_INT_STAT;
 676                 port->sram_chno          = SRAM_CH03; /* VID_B */
 677                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 678                 break;
 679         case 2:
 680                 port->reg_gpcnt          = VID_C_GPCNT;
 681                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 682                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 683                 port->reg_lngth          = VID_C_LNGTH;
 684                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 685                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 686                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 687                 port->reg_sop_status     = VID_C_SOP_STATUS;
 688                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 689                 port->reg_vld_misc       = VID_C_VLD_MISC;
 690                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 691                 port->reg_src_sel        = 0;
 692                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 693                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 694                 port->sram_chno          = SRAM_CH06; /* VID_C */
 695                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 696                 break;
 697         default:
 698                 BUG();
 699         }
 700
 701         cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
 702                      port->reg_dma_ctl, port->dma_ctl_val, 0x00);
 703
 704         return 0;
 705 }
 706
 707 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 708 {
 709         switch (cx_read(RDR_CFG2) & 0xff) {
 710         case 0x00:
 711                 /* cx23885 */
 712                 dev->hwrevision = 0xa0;
 713                 break;
 714         case 0x01:
 715                 /* CX23885-12Z */
 716                 dev->hwrevision = 0xa1;
 717                 break;
 718         case 0x02:
 719                 /* CX23885-13Z/14Z */
 720                 dev->hwrevision = 0xb0;
 721                 break;
 722         case 0x03:
 723                 if (dev->pci->device == 0x8880) {
 724                         /* CX23888-21Z/22Z */
 725                         dev->hwrevision = 0xc0;
 726                 } else {
 727                         /* CX23885-14Z */
 728                         dev->hwrevision = 0xa4;
 729                 }
 730                 break;
 731         case 0x04:
 732                 if (dev->pci->device == 0x8880) {
 733                         /* CX23888-31Z */
 734                         dev->hwrevision = 0xd0;
 735                 } else {
 736                         /* CX23885-15Z, CX23888-31Z */
 737                         dev->hwrevision = 0xa5;
 738                 }
 739                 break;
 740         case 0x0e:
 741                 /* CX23887-15Z */
 742                 dev->hwrevision = 0xc0;
 743         case 0x0f:
 744                 /* CX23887-14Z */
 745                 dev->hwrevision = 0xb1;
 746                 break;
 747         default:
 748                 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
 749                         __func__, dev->hwrevision);
 750         }
 751         if (dev->hwrevision)
 752                 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
 753                         __func__, dev->hwrevision);
 754         else
 755                 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
 756                         __func__, dev->hwrevision);
 757 }
 758
 759 /* Find the first v4l2_subdev member of the group id in hw */
 760 struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw)
 761 {
 762         struct v4l2_subdev *result = NULL;
 763         struct v4l2_subdev *sd;
 764
 765         spin_lock(&dev->v4l2_dev.lock);
 766         v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) {
 767                 if (sd->grp_id == hw) {
 768                         result = sd;
 769                         break;
 770                 }
 771         }
 772         spin_unlock(&dev->v4l2_dev.lock);
 773         return result;
 774 }
 775
 776 static int cx23885_dev_setup(struct cx23885_dev *dev)
 777 {
 778         int i;
 779
 780         mutex_init(&dev->lock);
 781         mutex_init(&dev->gpio_lock);
 782
 783         atomic_inc(&dev->refcount);
 784
 785         dev->nr = cx23885_devcount++;
 786         sprintf(dev->name, "cx23885[%d]", dev->nr);
 787
 788         mutex_lock(&devlist);
 789         list_add_tail(&dev->devlist, &cx23885_devlist);
 790         mutex_unlock(&devlist);
 791
 792         /* Configure the internal memory */
 793         if (dev->pci->device == 0x8880) {
 794                 /* Could be 887 or 888, assume a default */
 795                 dev->bridge = CX23885_BRIDGE_887;
 796                 /* Apply a sensible clock frequency for the PCIe bridge */
 797                 dev->clk_freq = 25000000;
 798                 dev->sram_channels = cx23887_sram_channels;
 799         } else
 800         if (dev->pci->device == 0x8852) {
 801                 dev->bridge = CX23885_BRIDGE_885;
 802                 /* Apply a sensible clock frequency for the PCIe bridge */
 803                 dev->clk_freq = 28000000;
 804                 dev->sram_channels = cx23885_sram_channels;
 805         } else
 806                 BUG();
 807
 808         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 809                 __func__, dev->bridge);
 810
 811         /* board config */
 812         dev->board = UNSET;
 813         if (card[dev->nr] < cx23885_bcount)
 814                 dev->board = card[dev->nr];
 815         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 816                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 817                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 818                         dev->board = cx23885_subids[i].card;
 819         if (UNSET == dev->board) {
 820                 dev->board = CX23885_BOARD_UNKNOWN;
 821                 cx23885_card_list(dev);
 822         }
 823
 824         /* If the user specific a clk freq override, apply it */
 825         if (cx23885_boards[dev->board].clk_freq > 0)
 826                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 827
 828         dev->pci_bus  = dev->pci->bus->number;
 829         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 830         dev->pci_irqmask = 0x001f00;
 831         if (cx23885_boards[dev->board].cimax > 0)
 832                 dev->pci_irqmask |= 0x01800000; /* for CiMaxes */
 833
 834         /* External Master 1 Bus */
 835         dev->i2c_bus[0].nr = 0;
 836         dev->i2c_bus[0].dev = dev;
 837         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 838         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 839         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 840         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 841         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 842         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 843
 844         /* External Master 2 Bus */
 845         dev->i2c_bus[1].nr = 1;
 846         dev->i2c_bus[1].dev = dev;
 847         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 848         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 849         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 850         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 851         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 852         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 853
 854         /* Internal Master 3 Bus */
 855         dev->i2c_bus[2].nr = 2;
 856         dev->i2c_bus[2].dev = dev;
 857         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 858         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 859         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 860         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 861         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 862         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 863
 864         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
 865                 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
 866                 cx23885_init_tsport(dev, &dev->ts1, 1);
 867
 868         if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
 869                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 870                 cx23885_init_tsport(dev, &dev->ts2, 2);
 871
 872         if (get_resources(dev) < 0) {
 873                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 874                        "subsystem: %04x:%04x\n",
 875                        dev->name, dev->pci->subsystem_vendor,
 876                        dev->pci->subsystem_device);
 877
 878                 cx23885_devcount--;
 879                 return -ENODEV;
 880         }
 881
 882         /* PCIe stuff */
 883         dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
 884                              pci_resource_len(dev->pci, 0));
 885
 886         dev->bmmio = (u8 __iomem *)dev->lmmio;
 887
 888         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 889                dev->name, dev->pci->subsystem_vendor,
 890                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 891                dev->board, card[dev->nr] == dev->board ?
 892                "insmod option" : "autodetected");
 893
 894         cx23885_pci_quirks(dev);
 895
 896         /* Assume some sensible defaults */
 897         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 898         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 899         dev->radio_type = cx23885_boards[dev->board].radio_type;
 900         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 901
 902         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
 903                 __func__, dev->tuner_type, dev->tuner_addr);
 904         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 905                 __func__, dev->radio_type, dev->radio_addr);
 906
 907         /* The cx23417 encoder has GPIO's that need to be initialised
 908          * before DVB, so that demodulators and tuners are out of
 909          * reset before DVB uses them.
 910          */
 911         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
 912                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 913                         cx23885_mc417_init(dev);
 914
 915         /* init hardware */
 916         cx23885_reset(dev);
 917
 918         cx23885_i2c_register(&dev->i2c_bus[0]);
 919         cx23885_i2c_register(&dev->i2c_bus[1]);
 920         cx23885_i2c_register(&dev->i2c_bus[2]);
 921         cx23885_card_setup(dev);
 922         call_all(dev, core, s_power, 0);
 923         cx23885_ir_init(dev);
 924
 925         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
 926                 if (cx23885_video_register(dev) < 0) {
 927                         printk(KERN_ERR "%s() Failed to register analog "
 928                                 "video adapters on VID_A\n", __func__);
 929                 }
 930         }
 931
 932         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
 933                 if (cx23885_dvb_register(&dev->ts1) < 0) {
 934                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
 935                                __func__);
 936                 }
 937         } else
 938         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
 939                 if (cx23885_417_register(dev) < 0) {
 940                         printk(KERN_ERR
 941                                 "%s() Failed to register 417 on VID_B\n",
 942                                __func__);
 943                 }
 944         }
 945
 946         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
 947                 if (cx23885_dvb_register(&dev->ts2) < 0) {
 948                         printk(KERN_ERR
 949                                 "%s() Failed to register dvb on VID_C\n",
 950                                __func__);
 951                 }
 952         } else
 953         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
 954                 if (cx23885_417_register(dev) < 0) {
 955                         printk(KERN_ERR
 956                                 "%s() Failed to register 417 on VID_C\n",
 957                                __func__);
 958                 }
 959         }
 960
 961         cx23885_dev_checkrevision(dev);
 962
 963         return 0;
 964 }
 965
 966 static void cx23885_dev_unregister(struct cx23885_dev *dev)
 967 {
 968         release_mem_region(pci_resource_start(dev->pci, 0),
 969                            pci_resource_len(dev->pci, 0));
 970
 971         if (!atomic_dec_and_test(&dev->refcount))
 972                 return;
 973
 974         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
 975                 cx23885_video_unregister(dev);
 976
 977         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 978                 cx23885_dvb_unregister(&dev->ts1);
 979
 980         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
 981                 cx23885_417_unregister(dev);
 982
 983         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 984                 cx23885_dvb_unregister(&dev->ts2);
 985
 986         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
 987                 cx23885_417_unregister(dev);
 988
 989         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 990         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 991         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 992
 993         iounmap(dev->lmmio);
 994 }
 995
 996 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
 997                                unsigned int offset, u32 sync_line,
 998                                unsigned int bpl, unsigned int padding,
 999                                unsigned int lines)
1000 {
1001         struct scatterlist *sg;
1002         unsigned int line, todo;
1003
1004         /* sync instruction */
1005         if (sync_line != NO_SYNC_LINE)
1006                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1007
1008         /* scan lines */
1009         sg = sglist;
1010         for (line = 0; line < lines; line++) {
1011                 while (offset && offset >= sg_dma_len(sg)) {
1012                         offset -= sg_dma_len(sg);
1013                         sg++;
1014                 }
1015                 if (bpl <= sg_dma_len(sg)-offset) {
1016                         /* fits into current chunk */
1017                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
1018                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1019                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1020                         offset += bpl;
1021                 } else {
1022                         /* scanline needs to be split */
1023                         todo = bpl;
1024                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
1025                                             (sg_dma_len(sg)-offset));
1026                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1027                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1028                         todo -= (sg_dma_len(sg)-offset);
1029                         offset = 0;
1030                         sg++;
1031                         while (todo > sg_dma_len(sg)) {
1032                                 *(rp++) = cpu_to_le32(RISC_WRITE|
1033                                                     sg_dma_len(sg));
1034                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1035                                 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1036                                 todo -= sg_dma_len(sg);
1037                                 sg++;
1038                         }
1039                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1040                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1041                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1042                         offset += todo;
1043                 }
1044                 offset += padding;
1045         }
1046
1047         return rp;
1048 }
1049
1050 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1051                         struct scatterlist *sglist, unsigned int top_offset,
1052                         unsigned int bottom_offset, unsigned int bpl,
1053                         unsigned int padding, unsigned int lines)
1054 {
1055         u32 instructions, fields;
1056         __le32 *rp;
1057         int rc;
1058
1059         fields = 0;
1060         if (UNSET != top_offset)
1061                 fields++;
1062         if (UNSET != bottom_offset)
1063                 fields++;
1064
1065         /* estimate risc mem: worst case is one write per page border +
1066            one write per scan line + syncs + jump (all 2 dwords).  Padding
1067            can cause next bpl to start close to a page border.  First DMA
1068            region may be smaller than PAGE_SIZE */
1069         /* write and jump need and extra dword */
1070         instructions  = fields * (1 + ((bpl + padding) * lines)
1071                 / PAGE_SIZE + lines);
1072         instructions += 2;
1073         rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1074         if (rc < 0)
1075                 return rc;
1076
1077         /* write risc instructions */
1078         rp = risc->cpu;
1079         if (UNSET != top_offset)
1080                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1081                                         bpl, padding, lines);
1082         if (UNSET != bottom_offset)
1083                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1084                                         bpl, padding, lines);
1085
1086         /* save pointer to jmp instruction address */
1087         risc->jmp = rp;
1088         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1089         return 0;
1090 }
1091
1092 static int cx23885_risc_databuffer(struct pci_dev *pci,
1093                                    struct btcx_riscmem *risc,
1094                                    struct scatterlist *sglist,
1095                                    unsigned int bpl,
1096                                    unsigned int lines)
1097 {
1098         u32 instructions;
1099         __le32 *rp;
1100         int rc;
1101
1102         /* estimate risc mem: worst case is one write per page border +
1103            one write per scan line + syncs + jump (all 2 dwords).  Here
1104            there is no padding and no sync.  First DMA region may be smaller
1105            than PAGE_SIZE */
1106         /* Jump and write need an extra dword */
1107         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
1108         instructions += 1;
1109
1110         rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1111         if (rc < 0)
1112                 return rc;
1113
1114         /* write risc instructions */
1115         rp = risc->cpu;
1116         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1117
1118         /* save pointer to jmp instruction address */
1119         risc->jmp = rp;
1120         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1121         return 0;
1122 }
1123
1124 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1125                                 u32 reg, u32 mask, u32 value)
1126 {
1127         __le32 *rp;
1128         int rc;
1129
1130         rc = btcx_riscmem_alloc(pci, risc, 4*16);
1131         if (rc < 0)
1132                 return rc;
1133
1134         /* write risc instructions */
1135         rp = risc->cpu;
1136         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
1137         *(rp++) = cpu_to_le32(reg);
1138         *(rp++) = cpu_to_le32(value);
1139         *(rp++) = cpu_to_le32(mask);
1140         *(rp++) = cpu_to_le32(RISC_JUMP);
1141         *(rp++) = cpu_to_le32(risc->dma);
1142         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1143         return 0;
1144 }
1145
1146 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1147 {
1148         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1149
1150         BUG_ON(in_interrupt());
1151         videobuf_waiton(&buf->vb, 0, 0);
1152         videobuf_dma_unmap(q, dma);
1153         videobuf_dma_free(dma);
1154         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1155         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1156 }
1157
1158 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1159 {
1160         struct cx23885_dev *dev = port->dev;
1161
1162         dprintk(1, "%s() Register Dump\n", __func__);
1163         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __func__,
1164                 cx_read(DEV_CNTRL2));
1165         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __func__,
1166                 cx_read(PCI_INT_MSK));
1167         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __func__,
1168                 cx_read(AUDIO_INT_INT_MSK));
1169         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __func__,
1170                 cx_read(AUD_INT_DMA_CTL));
1171         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __func__,
1172                 cx_read(AUDIO_EXT_INT_MSK));
1173         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __func__,
1174                 cx_read(AUD_EXT_DMA_CTL));
1175         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __func__,
1176                 cx_read(PAD_CTRL));
1177         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __func__,
1178                 cx_read(ALT_PIN_OUT_SEL));
1179         dprintk(1, "%s() GPIO2                    0x%08X\n", __func__,
1180                 cx_read(GPIO2));
1181         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __func__,
1182                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1183         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __func__,
1184                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1185         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __func__,
1186                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1187         if (port->reg_src_sel)
1188                 dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __func__,
1189                         port->reg_src_sel, cx_read(port->reg_src_sel));
1190         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __func__,
1191                 port->reg_lngth, cx_read(port->reg_lngth));
1192         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __func__,
1193                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1194         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __func__,
1195                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1196         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __func__,
1197                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1198         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __func__,
1199                 port->reg_sop_status, cx_read(port->reg_sop_status));
1200         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1201                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1202         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __func__,
1203                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1204         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __func__,
1205                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1206         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __func__,
1207                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1208 }
1209
1210 static int cx23885_start_dma(struct cx23885_tsport *port,
1211                              struct cx23885_dmaqueue *q,
1212                              struct cx23885_buffer   *buf)
1213 {
1214         struct cx23885_dev *dev = port->dev;
1215         u32 reg;
1216
1217         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1218                 buf->vb.width, buf->vb.height, buf->vb.field);
1219
1220         /* Stop the fifo and risc engine for this port */
1221         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1222
1223         /* setup fifo + format */
1224         cx23885_sram_channel_setup(dev,
1225                                    &dev->sram_channels[port->sram_chno],
1226                                    port->ts_packet_size, buf->risc.dma);
1227         if (debug > 5) {
1228                 cx23885_sram_channel_dump(dev,
1229                         &dev->sram_channels[port->sram_chno]);
1230                 cx23885_risc_disasm(port, &buf->risc);
1231         }
1232
1233         /* write TS length to chip */
1234         cx_write(port->reg_lngth, buf->vb.width);
1235
1236         if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1237                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1238                 printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1239                         __func__,
1240                         cx23885_boards[dev->board].portb,
1241                         cx23885_boards[dev->board].portc);
1242                 return -EINVAL;
1243         }
1244
1245         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1246                 cx23885_av_clk(dev, 0);
1247
1248         udelay(100);
1249
1250         /* If the port supports SRC SELECT, configure it */
1251         if (port->reg_src_sel)
1252                 cx_write(port->reg_src_sel, port->src_sel_val);
1253
1254         cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1255         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1256         cx_write(port->reg_vld_misc, port->vld_misc_val);
1257         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1258         udelay(100);
1259
1260         /* NOTE: this is 2 (reserved) for portb, does it matter? */
1261         /* reset counter to zero */
1262         cx_write(port->reg_gpcnt_ctl, 3);
1263         q->count = 1;
1264
1265         /* Set VIDB pins to input */
1266         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1267                 reg = cx_read(PAD_CTRL);
1268                 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1269                 cx_write(PAD_CTRL, reg);
1270         }
1271
1272         /* Set VIDC pins to input */
1273         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1274                 reg = cx_read(PAD_CTRL);
1275                 reg &= ~0x4; /* Clear TS2_SOP_OE */
1276                 cx_write(PAD_CTRL, reg);
1277         }
1278
1279         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1280
1281                 reg = cx_read(PAD_CTRL);
1282                 reg = reg & ~0x1;    /* Clear TS1_OE */
1283
1284                 /* FIXME, bit 2 writing here is questionable */
1285                 /* set TS1_SOP_OE and TS1_OE_HI */
1286                 reg = reg | 0xa;
1287                 cx_write(PAD_CTRL, reg);
1288
1289                 /* FIXME and these two registers should be documented. */
1290                 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1291                 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1292         }
1293
1294         switch (dev->bridge) {
1295         case CX23885_BRIDGE_885:
1296         case CX23885_BRIDGE_887:
1297         case CX23885_BRIDGE_888:
1298                 /* enable irqs */
1299                 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1300                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1301                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1302                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1303                 break;
1304         default:
1305                 BUG();
1306         }
1307
1308         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1309
1310         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1311                 cx23885_av_clk(dev, 1);
1312
1313         if (debug > 4)
1314                 cx23885_tsport_reg_dump(port);
1315
1316         return 0;
1317 }
1318
1319 static int cx23885_stop_dma(struct cx23885_tsport *port)
1320 {
1321         struct cx23885_dev *dev = port->dev;
1322         u32 reg;
1323
1324         dprintk(1, "%s()\n", __func__);
1325
1326         /* Stop interrupts and DMA */
1327         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1328         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1329
1330         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1331
1332                 reg = cx_read(PAD_CTRL);
1333
1334                 /* Set TS1_OE */
1335                 reg = reg | 0x1;
1336
1337                 /* clear TS1_SOP_OE and TS1_OE_HI */
1338                 reg = reg & ~0xa;
1339                 cx_write(PAD_CTRL, reg);
1340                 cx_write(port->reg_src_sel, 0);
1341                 cx_write(port->reg_gen_ctrl, 8);
1342
1343         }
1344
1345         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1346                 cx23885_av_clk(dev, 0);
1347
1348         return 0;
1349 }
1350
1351 int cx23885_restart_queue(struct cx23885_tsport *port,
1352                                 struct cx23885_dmaqueue *q)
1353 {
1354         struct cx23885_dev *dev = port->dev;
1355         struct cx23885_buffer *buf;
1356
1357         dprintk(5, "%s()\n", __func__);
1358         if (list_empty(&q->active)) {
1359                 struct cx23885_buffer *prev;
1360                 prev = NULL;
1361
1362                 dprintk(5, "%s() queue is empty\n", __func__);
1363
1364                 for (;;) {
1365                         if (list_empty(&q->queued))
1366                                 return 0;
1367                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1368                                          vb.queue);
1369                         if (NULL == prev) {
1370                                 list_del(&buf->vb.queue);
1371                                 list_add_tail(&buf->vb.queue, &q->active);
1372                                 cx23885_start_dma(port, q, buf);
1373                                 buf->vb.state = VIDEOBUF_ACTIVE;
1374                                 buf->count    = q->count++;
1375                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1376                                 dprintk(5, "[%p/%d] restart_queue - f/active\n",
1377                                         buf, buf->vb.i);
1378
1379                         } else if (prev->vb.width  == buf->vb.width  &&
1380                                    prev->vb.height == buf->vb.height &&
1381                                    prev->fmt       == buf->fmt) {
1382                                 list_del(&buf->vb.queue);
1383                                 list_add_tail(&buf->vb.queue, &q->active);
1384                                 buf->vb.state = VIDEOBUF_ACTIVE;
1385                                 buf->count    = q->count++;
1386                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1387                                 /* 64 bit bits 63-32 */
1388                                 prev->risc.jmp[2] = cpu_to_le32(0);
1389                                 dprintk(5, "[%p/%d] restart_queue - m/active\n",
1390                                         buf, buf->vb.i);
1391                         } else {
1392                                 return 0;
1393                         }
1394                         prev = buf;
1395                 }
1396                 return 0;
1397         }
1398
1399         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1400         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1401                 buf, buf->vb.i);
1402         cx23885_start_dma(port, q, buf);
1403         list_for_each_entry(buf, &q->active, vb.queue)
1404                 buf->count = q->count++;
1405         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1406         return 0;
1407 }
1408
1409 /* ------------------------------------------------------------------ */
1410
1411 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1412                         struct cx23885_buffer *buf, enum v4l2_field field)
1413 {
1414         struct cx23885_dev *dev = port->dev;
1415         int size = port->ts_packet_size * port->ts_packet_count;
1416         int rc;
1417
1418         dprintk(1, "%s: %p\n", __func__, buf);
1419         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1420                 return -EINVAL;
1421
1422         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1423                 buf->vb.width  = port->ts_packet_size;
1424                 buf->vb.height = port->ts_packet_count;
1425                 buf->vb.size   = size;
1426                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1427
1428                 rc = videobuf_iolock(q, &buf->vb, NULL);
1429                 if (0 != rc)
1430                         goto fail;
1431                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1432                                         videobuf_to_dma(&buf->vb)->sglist,
1433                                         buf->vb.width, buf->vb.height);
1434         }
1435         buf->vb.state = VIDEOBUF_PREPARED;
1436         return 0;
1437
1438  fail:
1439         cx23885_free_buffer(q, buf);
1440         return rc;
1441 }
1442
1443 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1444 {
1445         struct cx23885_buffer    *prev;
1446         struct cx23885_dev *dev = port->dev;
1447         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1448
1449         /* add jump to stopper */
1450         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1451         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1452         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1453
1454         if (list_empty(&cx88q->active)) {
1455                 dprintk(1, "queue is empty - first active\n");
1456                 list_add_tail(&buf->vb.queue, &cx88q->active);
1457                 cx23885_start_dma(port, cx88q, buf);
1458                 buf->vb.state = VIDEOBUF_ACTIVE;
1459                 buf->count    = cx88q->count++;
1460                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1461                 dprintk(1, "[%p/%d] %s - first active\n",
1462                         buf, buf->vb.i, __func__);
1463         } else {
1464                 dprintk(1, "queue is not empty - append to active\n");
1465                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1466                                   vb.queue);
1467                 list_add_tail(&buf->vb.queue, &cx88q->active);
1468                 buf->vb.state = VIDEOBUF_ACTIVE;
1469                 buf->count    = cx88q->count++;
1470                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1471                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1472                 dprintk(1, "[%p/%d] %s - append to active\n",
1473                          buf, buf->vb.i, __func__);
1474         }
1475 }
1476
1477 /* ----------------------------------------------------------- */
1478
1479 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1480                               int restart)
1481 {
1482         struct cx23885_dev *dev = port->dev;
1483         struct cx23885_dmaqueue *q = &port->mpegq;
1484         struct cx23885_buffer *buf;
1485         unsigned long flags;
1486
1487         spin_lock_irqsave(&port->slock, flags);
1488         while (!list_empty(&q->active)) {
1489                 buf = list_entry(q->active.next, struct cx23885_buffer,
1490                                  vb.queue);
1491                 list_del(&buf->vb.queue);
1492                 buf->vb.state = VIDEOBUF_ERROR;
1493                 wake_up(&buf->vb.done);
1494                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1495                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1496         }
1497         if (restart) {
1498                 dprintk(1, "restarting queue\n");
1499                 cx23885_restart_queue(port, q);
1500         }
1501         spin_unlock_irqrestore(&port->slock, flags);
1502 }
1503
1504 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1505 {
1506         struct cx23885_dev *dev = port->dev;
1507         struct cx23885_dmaqueue *q = &port->mpegq;
1508
1509         dprintk(1, "%s()\n", __func__);
1510         del_timer_sync(&q->timeout);
1511         cx23885_stop_dma(port);
1512         do_cancel_buffers(port, "cancel", 0);
1513 }
1514
1515 static void cx23885_timeout(unsigned long data)
1516 {
1517         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1518         struct cx23885_dev *dev = port->dev;
1519
1520         dprintk(1, "%s()\n", __func__);
1521
1522         if (debug > 5)
1523                 cx23885_sram_channel_dump(dev,
1524                         &dev->sram_channels[port->sram_chno]);
1525
1526         cx23885_stop_dma(port);
1527         do_cancel_buffers(port, "timeout", 1);
1528 }
1529
1530 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1531 {
1532         /* FIXME: port1 assumption here. */
1533         struct cx23885_tsport *port = &dev->ts1;
1534         int count = 0;
1535         int handled = 0;
1536
1537         if (status == 0)
1538                 return handled;
1539
1540         count = cx_read(port->reg_gpcnt);
1541         dprintk(7, "status: 0x%08x  mask: 0x%08x count: 0x%x\n",
1542                 status, cx_read(port->reg_ts_int_msk), count);
1543
1544         if ((status & VID_B_MSK_BAD_PKT)         ||
1545                 (status & VID_B_MSK_OPC_ERR)     ||
1546                 (status & VID_B_MSK_VBI_OPC_ERR) ||
1547                 (status & VID_B_MSK_SYNC)        ||
1548                 (status & VID_B_MSK_VBI_SYNC)    ||
1549                 (status & VID_B_MSK_OF)          ||
1550                 (status & VID_B_MSK_VBI_OF)) {
1551                 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1552                         "= 0x%x\n", dev->name, status);
1553                 if (status & VID_B_MSK_BAD_PKT)
1554                         dprintk(1, "        VID_B_MSK_BAD_PKT\n");
1555                 if (status & VID_B_MSK_OPC_ERR)
1556                         dprintk(1, "        VID_B_MSK_OPC_ERR\n");
1557                 if (status & VID_B_MSK_VBI_OPC_ERR)
1558                         dprintk(1, "        VID_B_MSK_VBI_OPC_ERR\n");
1559                 if (status & VID_B_MSK_SYNC)
1560                         dprintk(1, "        VID_B_MSK_SYNC\n");
1561                 if (status & VID_B_MSK_VBI_SYNC)
1562                         dprintk(1, "        VID_B_MSK_VBI_SYNC\n");
1563                 if (status & VID_B_MSK_OF)
1564                         dprintk(1, "        VID_B_MSK_OF\n");
1565                 if (status & VID_B_MSK_VBI_OF)
1566                         dprintk(1, "        VID_B_MSK_VBI_OF\n");
1567
1568                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1569                 cx23885_sram_channel_dump(dev,
1570                         &dev->sram_channels[port->sram_chno]);
1571                 cx23885_417_check_encoder(dev);
1572         } else if (status & VID_B_MSK_RISCI1) {
1573                 dprintk(7, "        VID_B_MSK_RISCI1\n");
1574                 spin_lock(&port->slock);
1575                 cx23885_wakeup(port, &port->mpegq, count);
1576                 spin_unlock(&port->slock);
1577         } else if (status & VID_B_MSK_RISCI2) {
1578                 dprintk(7, "        VID_B_MSK_RISCI2\n");
1579                 spin_lock(&port->slock);
1580                 cx23885_restart_queue(port, &port->mpegq);
1581                 spin_unlock(&port->slock);
1582         }
1583         if (status) {
1584                 cx_write(port->reg_ts_int_stat, status);
1585                 handled = 1;
1586         }
1587
1588         return handled;
1589 }
1590
1591 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1592 {
1593         struct cx23885_dev *dev = port->dev;
1594         int handled = 0;
1595         u32 count;
1596
1597         if ((status & VID_BC_MSK_OPC_ERR) ||
1598                 (status & VID_BC_MSK_BAD_PKT) ||
1599                 (status & VID_BC_MSK_SYNC) ||
1600                 (status & VID_BC_MSK_OF)) {
1601
1602                 if (status & VID_BC_MSK_OPC_ERR)
1603                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1604                                 VID_BC_MSK_OPC_ERR);
1605
1606                 if (status & VID_BC_MSK_BAD_PKT)
1607                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1608                                 VID_BC_MSK_BAD_PKT);
1609
1610                 if (status & VID_BC_MSK_SYNC)
1611                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n",
1612                                 VID_BC_MSK_SYNC);
1613
1614                 if (status & VID_BC_MSK_OF)
1615                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n",
1616                                 VID_BC_MSK_OF);
1617
1618                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1619
1620                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1621                 cx23885_sram_channel_dump(dev,
1622                         &dev->sram_channels[port->sram_chno]);
1623
1624         } else if (status & VID_BC_MSK_RISCI1) {
1625
1626                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1627
1628                 spin_lock(&port->slock);
1629                 count = cx_read(port->reg_gpcnt);
1630                 cx23885_wakeup(port, &port->mpegq, count);
1631                 spin_unlock(&port->slock);
1632
1633         } else if (status & VID_BC_MSK_RISCI2) {
1634
1635                 dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);
1636
1637                 spin_lock(&port->slock);
1638                 cx23885_restart_queue(port, &port->mpegq);
1639                 spin_unlock(&port->slock);
1640
1641         }
1642         if (status) {
1643                 cx_write(port->reg_ts_int_stat, status);
1644                 handled = 1;
1645         }
1646
1647         return handled;
1648 }
1649
1650 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1651 {
1652         struct cx23885_dev *dev = dev_id;
1653         struct cx23885_tsport *ts1 = &dev->ts1;
1654         struct cx23885_tsport *ts2 = &dev->ts2;
1655         u32 pci_status, pci_mask;
1656         u32 vida_status, vida_mask;
1657         u32 ts1_status, ts1_mask;
1658         u32 ts2_status, ts2_mask;
1659         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1660         bool ir_handled = false;
1661
1662         pci_status = cx_read(PCI_INT_STAT);
1663         pci_mask = cx_read(PCI_INT_MSK);
1664         vida_status = cx_read(VID_A_INT_STAT);
1665         vida_mask = cx_read(VID_A_INT_MSK);
1666         ts1_status = cx_read(VID_B_INT_STAT);
1667         ts1_mask = cx_read(VID_B_INT_MSK);
1668         ts2_status = cx_read(VID_C_INT_STAT);
1669         ts2_mask = cx_read(VID_C_INT_MSK);
1670
1671         if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1672                 goto out;
1673
1674         vida_count = cx_read(VID_A_GPCNT);
1675         ts1_count = cx_read(ts1->reg_gpcnt);
1676         ts2_count = cx_read(ts2->reg_gpcnt);
1677         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1678                 pci_status, pci_mask);
1679         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1680                 vida_status, vida_mask, vida_count);
1681         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1682                 ts1_status, ts1_mask, ts1_count);
1683         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1684                 ts2_status, ts2_mask, ts2_count);
1685
1686         if (pci_status & (PCI_MSK_RISC_RD | PCI_MSK_RISC_WR |
1687                           PCI_MSK_AL_RD   | PCI_MSK_AL_WR   | PCI_MSK_APB_DMA |
1688                           PCI_MSK_VID_C   | PCI_MSK_VID_B   | PCI_MSK_VID_A   |
1689                           PCI_MSK_AUD_INT | PCI_MSK_AUD_EXT |
1690                           PCI_MSK_GPIO0   | PCI_MSK_GPIO1   |
1691                           PCI_MSK_IR)) {
1692
1693                 if (pci_status & PCI_MSK_RISC_RD)
1694                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n",
1695                                 PCI_MSK_RISC_RD);
1696
1697                 if (pci_status & PCI_MSK_RISC_WR)
1698                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n",
1699                                 PCI_MSK_RISC_WR);
1700
1701                 if (pci_status & PCI_MSK_AL_RD)
1702                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n",
1703                                 PCI_MSK_AL_RD);
1704
1705                 if (pci_status & PCI_MSK_AL_WR)
1706                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n",
1707                                 PCI_MSK_AL_WR);
1708
1709                 if (pci_status & PCI_MSK_APB_DMA)
1710                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n",
1711                                 PCI_MSK_APB_DMA);
1712
1713                 if (pci_status & PCI_MSK_VID_C)
1714                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n",
1715                                 PCI_MSK_VID_C);
1716
1717                 if (pci_status & PCI_MSK_VID_B)
1718                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n",
1719                                 PCI_MSK_VID_B);
1720
1721                 if (pci_status & PCI_MSK_VID_A)
1722                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n",
1723                                 PCI_MSK_VID_A);
1724
1725                 if (pci_status & PCI_MSK_AUD_INT)
1726                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n",
1727                                 PCI_MSK_AUD_INT);
1728
1729                 if (pci_status & PCI_MSK_AUD_EXT)
1730                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n",
1731                                 PCI_MSK_AUD_EXT);
1732
1733                 if (pci_status & PCI_MSK_GPIO0)
1734                         dprintk(7, " (PCI_MSK_GPIO0     0x%08x)\n",
1735                                 PCI_MSK_GPIO0);
1736
1737                 if (pci_status & PCI_MSK_GPIO1)
1738                         dprintk(7, " (PCI_MSK_GPIO1     0x%08x)\n",
1739                                 PCI_MSK_GPIO1);
1740
1741                 if (pci_status & PCI_MSK_IR)
1742                         dprintk(7, " (PCI_MSK_IR        0x%08x)\n",
1743                                 PCI_MSK_IR);
1744         }
1745
1746         if (cx23885_boards[dev->board].cimax > 0 &&
1747                 ((pci_status & PCI_MSK_GPIO0) ||
1748                         (pci_status & PCI_MSK_GPIO1))) {
1749
1750                 if (cx23885_boards[dev->board].cimax > 0)
1751                         handled += netup_ci_slot_status(dev, pci_status);
1752
1753         }
1754
1755         if (ts1_status) {
1756                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1757                         handled += cx23885_irq_ts(ts1, ts1_status);
1758                 else
1759                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1760                         handled += cx23885_irq_417(dev, ts1_status);
1761         }
1762
1763         if (ts2_status) {
1764                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1765                         handled += cx23885_irq_ts(ts2, ts2_status);
1766                 else
1767                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1768                         handled += cx23885_irq_417(dev, ts2_status);
1769         }
1770
1771         if (vida_status)
1772                 handled += cx23885_video_irq(dev, vida_status);
1773
1774         if (pci_status & PCI_MSK_IR) {
1775                 v4l2_subdev_call(dev->sd_ir, ir, interrupt_service_routine,
1776                                  pci_status, &ir_handled);
1777                 if (ir_handled)
1778                         handled++;
1779         }
1780
1781         if (handled)
1782                 cx_write(PCI_INT_STAT, pci_status);
1783 out:
1784         return IRQ_RETVAL(handled);
1785 }
1786
1787 static void cx23885_v4l2_dev_notify(struct v4l2_subdev *sd,
1788                                     unsigned int notification, void *arg)
1789 {
1790         struct cx23885_dev *dev;
1791
1792         if (sd == NULL)
1793                 return;
1794
1795         dev = to_cx23885(sd->v4l2_dev);
1796
1797         switch (notification) {
1798         case V4L2_SUBDEV_IR_RX_NOTIFY: /* Called in an IRQ context */
1799                 if (sd == dev->sd_ir)
1800                         cx23885_ir_rx_v4l2_dev_notify(sd, *(u32 *)arg);
1801                 break;
1802         case V4L2_SUBDEV_IR_TX_NOTIFY: /* Called in an IRQ context */
1803                 if (sd == dev->sd_ir)
1804                         cx23885_ir_tx_v4l2_dev_notify(sd, *(u32 *)arg);
1805                 break;
1806         }
1807 }
1808
1809 static void cx23885_v4l2_dev_notify_init(struct cx23885_dev *dev)
1810 {
1811         INIT_WORK(&dev->ir_rx_work, cx23885_ir_rx_work_handler);
1812         INIT_WORK(&dev->ir_tx_work, cx23885_ir_tx_work_handler);
1813         dev->v4l2_dev.notify = cx23885_v4l2_dev_notify;
1814 }
1815
1816 static inline int encoder_on_portb(struct cx23885_dev *dev)
1817 {
1818         return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1819 }
1820
1821 static inline int encoder_on_portc(struct cx23885_dev *dev)
1822 {
1823         return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1824 }
1825
1826 /* Mask represents 32 different GPIOs, GPIO's are split into multiple
1827  * registers depending on the board configuration (and whether the
1828  * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1829  * be pushed into the correct hardware register, regardless of the
1830  * physical location. Certain registers are shared so we sanity check
1831  * and report errors if we think we're tampering with a GPIo that might
1832  * be assigned to the encoder (and used for the host bus).
1833  *
1834  * GPIO  2 thru  0 - On the cx23885 bridge
1835  * GPIO 18 thru  3 - On the cx23417 host bus interface
1836  * GPIO 23 thru 19 - On the cx25840 a/v core
1837  */
1838 void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1839 {
1840         if (mask & 0x7)
1841                 cx_set(GP0_IO, mask & 0x7);
1842
1843         if (mask & 0x0007fff8) {
1844                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1845                         printk(KERN_ERR
1846                                 "%s: Setting GPIO on encoder ports\n",
1847                                 dev->name);
1848                 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1849         }
1850
1851         /* TODO: 23-19 */
1852         if (mask & 0x00f80000)
1853                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1854 }
1855
1856 void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1857 {
1858         if (mask & 0x00000007)
1859                 cx_clear(GP0_IO, mask & 0x7);
1860
1861         if (mask & 0x0007fff8) {
1862                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1863                         printk(KERN_ERR
1864                                 "%s: Clearing GPIO moving on encoder ports\n",
1865                                 dev->name);
1866                 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1867         }
1868
1869         /* TODO: 23-19 */
1870         if (mask & 0x00f80000)
1871                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1872 }
1873
1874 void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1875 {
1876         if ((mask & 0x00000007) && asoutput)
1877                 cx_set(GP0_IO, (mask & 0x7) << 16);
1878         else if ((mask & 0x00000007) && !asoutput)
1879                 cx_clear(GP0_IO, (mask & 0x7) << 16);
1880
1881         if (mask & 0x0007fff8) {
1882                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1883                         printk(KERN_ERR
1884                                 "%s: Enabling GPIO on encoder ports\n",
1885                                 dev->name);
1886         }
1887
1888         /* MC417_OEN is active low for output, write 1 for an input */
1889         if ((mask & 0x0007fff8) && asoutput)
1890                 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
1891
1892         else if ((mask & 0x0007fff8) && !asoutput)
1893                 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
1894
1895         /* TODO: 23-19 */
1896 }
1897
1898 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1899                                      const struct pci_device_id *pci_id)
1900 {
1901         struct cx23885_dev *dev;
1902         int err;
1903
1904         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1905         if (NULL == dev)
1906                 return -ENOMEM;
1907
1908         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1909         if (err < 0)
1910                 goto fail_free;
1911
1912         /* Prepare to handle notifications from subdevices */
1913         cx23885_v4l2_dev_notify_init(dev);
1914
1915         /* pci init */
1916         dev->pci = pci_dev;
1917         if (pci_enable_device(pci_dev)) {
1918                 err = -EIO;
1919                 goto fail_unreg;
1920         }
1921
1922         if (cx23885_dev_setup(dev) < 0) {
1923                 err = -EINVAL;
1924                 goto fail_unreg;
1925         }
1926
1927         /* print pci info */
1928         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1929         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1930         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1931                "latency: %d, mmio: 0x%llx\n", dev->name,
1932                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1933                dev->pci_lat,
1934                 (unsigned long long)pci_resource_start(pci_dev, 0));
1935
1936         pci_set_master(pci_dev);
1937         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1938                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1939                 err = -EIO;
1940                 goto fail_irq;
1941         }
1942
1943         err = request_irq(pci_dev->irq, cx23885_irq,
1944                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1945         if (err < 0) {
1946                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1947                        dev->name, pci_dev->irq);
1948                 goto fail_irq;
1949         }
1950
1951         switch (dev->board) {
1952         case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1953                 cx_set(PCI_INT_MSK, 0x01800000); /* for NetUP */
1954                 break;
1955         }
1956
1957         /*
1958          * The CX2388[58] IR controller can start firing interrupts when
1959          * enabled, so these have to take place after the cx23885_irq() handler
1960          * is hooked up by the call to request_irq() above.
1961          */
1962         cx23885_ir_pci_int_enable(dev);
1963         cx23885_input_init(dev);
1964
1965         return 0;
1966
1967 fail_irq:
1968         cx23885_dev_unregister(dev);
1969 fail_unreg:
1970         v4l2_device_unregister(&dev->v4l2_dev);
1971 fail_free:
1972         kfree(dev);
1973         return err;
1974 }
1975
1976 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1977 {
1978         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1979         struct cx23885_dev *dev = to_cx23885(v4l2_dev);
1980
1981         cx23885_input_fini(dev);
1982         cx23885_ir_fini(dev);
1983
1984         cx23885_shutdown(dev);
1985
1986         pci_disable_device(pci_dev);
1987
1988         /* unregister stuff */
1989         free_irq(pci_dev->irq, dev);
1990
1991         mutex_lock(&devlist);
1992         list_del(&dev->devlist);
1993         mutex_unlock(&devlist);
1994
1995         cx23885_dev_unregister(dev);
1996         v4l2_device_unregister(v4l2_dev);
1997         kfree(dev);
1998 }
1999
2000 static struct pci_device_id cx23885_pci_tbl[] = {
2001         {
2002                 /* CX23885 */
2003                 .vendor       = 0x14f1,
2004                 .device       = 0x8852,
2005                 .subvendor    = PCI_ANY_ID,
2006                 .subdevice    = PCI_ANY_ID,
2007         }, {
2008                 /* CX23887 Rev 2 */
2009                 .vendor       = 0x14f1,
2010                 .device       = 0x8880,
2011                 .subvendor    = PCI_ANY_ID,
2012                 .subdevice    = PCI_ANY_ID,
2013         }, {
2014                 /* --- end of list --- */
2015         }
2016 };
2017 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
2018
2019 static struct pci_driver cx23885_pci_driver = {
2020         .name     = "cx23885",
2021         .id_table = cx23885_pci_tbl,
2022         .probe    = cx23885_initdev,
2023         .remove   = __devexit_p(cx23885_finidev),
2024         /* TODO */
2025         .suspend  = NULL,
2026         .resume   = NULL,
2027 };
2028
2029 static int __init cx23885_init(void)
2030 {
2031         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
2032                (CX23885_VERSION_CODE >> 16) & 0xff,
2033                (CX23885_VERSION_CODE >>  8) & 0xff,
2034                CX23885_VERSION_CODE & 0xff);
2035 #ifdef SNAPSHOT
2036         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
2037                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
2038 #endif
2039         return pci_register_driver(&cx23885_pci_driver);
2040 }
2041
2042 static void __exit cx23885_fini(void)
2043 {
2044         pci_unregister_driver(&cx23885_pci_driver);
2045 }
2046
2047 module_init(cx23885_init);
2048 module_exit(cx23885_fini);
2049
2050 /* ----------------------------------------------------------- */