drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
  27  */
  28 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  29 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  30
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include "dvb_frontend.h"
  36 #include "tda1004x.h"
  37
  38 enum tda1004x_demod {
  39         TDA1004X_DEMOD_TDA10045,
  40         TDA1004X_DEMOD_TDA10046,
  41 };
  42
  43 struct tda1004x_state {
  44         struct i2c_adapter* i2c;
  45         struct dvb_frontend_ops ops;
  46         const struct tda1004x_config* config;
  47         struct dvb_frontend frontend;
  48
  49         /* private demod data */
  50         u8 initialised;
  51         enum tda1004x_demod demod_type;
  52 };
  53
  54
  55 static int debug;
  56 #define dprintk(args...) \
  57         do { \
  58                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  59         } while (0)
  60
  61 #define TDA1004X_CHIPID          0x00
  62 #define TDA1004X_AUTO            0x01
  63 #define TDA1004X_IN_CONF1        0x02
  64 #define TDA1004X_IN_CONF2        0x03
  65 #define TDA1004X_OUT_CONF1       0x04
  66 #define TDA1004X_OUT_CONF2       0x05
  67 #define TDA1004X_STATUS_CD       0x06
  68 #define TDA1004X_CONFC4          0x07
  69 #define TDA1004X_DSSPARE2        0x0C
  70 #define TDA10045H_CODE_IN        0x0D
  71 #define TDA10045H_FWPAGE         0x0E
  72 #define TDA1004X_SCAN_CPT        0x10
  73 #define TDA1004X_DSP_CMD         0x11
  74 #define TDA1004X_DSP_ARG         0x12
  75 #define TDA1004X_DSP_DATA1       0x13
  76 #define TDA1004X_DSP_DATA2       0x14
  77 #define TDA1004X_CONFADC1        0x15
  78 #define TDA1004X_CONFC1          0x16
  79 #define TDA10045H_S_AGC          0x1a
  80 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  81 #define TDA1004X_SNR             0x1c
  82 #define TDA1004X_CONF_TS1        0x1e
  83 #define TDA1004X_CONF_TS2        0x1f
  84 #define TDA1004X_CBER_RESET      0x20
  85 #define TDA1004X_CBER_MSB        0x21
  86 #define TDA1004X_CBER_LSB        0x22
  87 #define TDA1004X_CVBER_LUT       0x23
  88 #define TDA1004X_VBER_MSB        0x24
  89 #define TDA1004X_VBER_MID        0x25
  90 #define TDA1004X_VBER_LSB        0x26
  91 #define TDA1004X_UNCOR           0x27
  92
  93 #define TDA10045H_CONFPLL_P      0x2D
  94 #define TDA10045H_CONFPLL_M_MSB  0x2E
  95 #define TDA10045H_CONFPLL_M_LSB  0x2F
  96 #define TDA10045H_CONFPLL_N      0x30
  97
  98 #define TDA10046H_CONFPLL1       0x2D
  99 #define TDA10046H_CONFPLL2       0x2F
 100 #define TDA10046H_CONFPLL3       0x30
 101 #define TDA10046H_TIME_WREF1     0x31
 102 #define TDA10046H_TIME_WREF2     0x32
 103 #define TDA10046H_TIME_WREF3     0x33
 104 #define TDA10046H_TIME_WREF4     0x34
 105 #define TDA10046H_TIME_WREF5     0x35
 106
 107 #define TDA10045H_UNSURW_MSB     0x31
 108 #define TDA10045H_UNSURW_LSB     0x32
 109 #define TDA10045H_WREF_MSB       0x33
 110 #define TDA10045H_WREF_MID       0x34
 111 #define TDA10045H_WREF_LSB       0x35
 112 #define TDA10045H_MUXOUT         0x36
 113 #define TDA1004X_CONFADC2        0x37
 114
 115 #define TDA10045H_IOFFSET        0x38
 116
 117 #define TDA10046H_CONF_TRISTATE1 0x3B
 118 #define TDA10046H_CONF_TRISTATE2 0x3C
 119 #define TDA10046H_CONF_POLARITY  0x3D
 120 #define TDA10046H_FREQ_OFFSET    0x3E
 121 #define TDA10046H_GPIO_OUT_SEL   0x41
 122 #define TDA10046H_GPIO_SELECT    0x42
 123 #define TDA10046H_AGC_CONF       0x43
 124 #define TDA10046H_AGC_GAINS      0x46
 125 #define TDA10046H_AGC_TUN_MIN    0x47
 126 #define TDA10046H_AGC_TUN_MAX    0x48
 127 #define TDA10046H_AGC_IF_MIN     0x49
 128 #define TDA10046H_AGC_IF_MAX     0x4A
 129
 130 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 131 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 132
 133 #define TDA10046H_CVBER_CTRL     0x4F
 134 #define TDA10046H_AGC_IF_LEVEL   0x52
 135 #define TDA10046H_CODE_CPT       0x57
 136 #define TDA10046H_CODE_IN        0x58
 137
 138
 139 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 140 {
 141         int ret;
 142         u8 buf[] = { reg, data };
 143         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 144
 145         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 146
 147         msg.addr = state->config->demod_address;
 148         ret = i2c_transfer(state->i2c, &msg, 1);
 149
 150         if (ret != 1)
 151                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 152                         __FUNCTION__, reg, data, ret);
 153
 154         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 155                 reg, data, ret);
 156         return (ret != 1) ? -1 : 0;
 157 }
 158
 159 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 160 {
 161         int ret;
 162         u8 b0[] = { reg };
 163         u8 b1[] = { 0 };
 164         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 165                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 166
 167         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 168
 169         msg[0].addr = state->config->demod_address;
 170         msg[1].addr = state->config->demod_address;
 171         ret = i2c_transfer(state->i2c, msg, 2);
 172
 173         if (ret != 2) {
 174                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 175                         ret);
 176                 return -1;
 177         }
 178
 179         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 180                 reg, b1[0], ret);
 181         return b1[0];
 182 }
 183
 184 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 185 {
 186         int val;
 187         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 188                 mask, data);
 189
 190         // read a byte and check
 191         val = tda1004x_read_byte(state, reg);
 192         if (val < 0)
 193                 return val;
 194
 195         // mask if off
 196         val = val & ~mask;
 197         val |= data & 0xff;
 198
 199         // write it out again
 200         return tda1004x_write_byteI(state, reg, val);
 201 }
 202
 203 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 204 {
 205         int i;
 206         int result;
 207
 208         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 209
 210         result = 0;
 211         for (i = 0; i < len; i++) {
 212                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 213                 if (result != 0)
 214                         break;
 215         }
 216
 217         return result;
 218 }
 219
 220 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 221 {
 222         int result;
 223         dprintk("%s\n", __FUNCTION__);
 224
 225         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 226         msleep(1);
 227         return result;
 228 }
 229
 230 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 231 {
 232         dprintk("%s\n", __FUNCTION__);
 233
 234         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 235 }
 236
 237 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 238                                    fe_bandwidth_t bandwidth)
 239 {
 240         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 241         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 242         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 243
 244         switch (bandwidth) {
 245         case BANDWIDTH_6_MHZ:
 246                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 247                 break;
 248
 249         case BANDWIDTH_7_MHZ:
 250                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 251                 break;
 252
 253         case BANDWIDTH_8_MHZ:
 254                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 255                 break;
 256
 257         default:
 258                 return -EINVAL;
 259         }
 260
 261         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 262
 263         return 0;
 264 }
 265
 266 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 267                                    fe_bandwidth_t bandwidth)
 268 {
 269         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 270         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 271         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 272
 273         switch (bandwidth) {
 274         case BANDWIDTH_6_MHZ:
 275                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 276                 break;
 277
 278         case BANDWIDTH_7_MHZ:
 279                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 280                 break;
 281
 282         case BANDWIDTH_8_MHZ:
 283                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 284                 break;
 285
 286         default:
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int tda1004x_do_upload(struct tda1004x_state *state,
 294                               unsigned char *mem, unsigned int len,
 295                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 296 {
 297         u8 buf[65];
 298         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 299         int tx_size;
 300         int pos = 0;
 301
 302         /* clear code counter */
 303         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 304         fw_msg.addr = state->config->demod_address;
 305
 306         buf[0] = dspCodeInReg;
 307         while (pos != len) {
 308                 // work out how much to send this time
 309                 tx_size = len - pos;
 310                 if (tx_size > 0x10)
 311                         tx_size = 0x10;
 312
 313                 // send the chunk
 314                 memcpy(buf + 1, mem + pos, tx_size);
 315                 fw_msg.len = tx_size + 1;
 316                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 317                         printk("tda1004x: Error during firmware upload\n");
 318                         return -EIO;
 319                 }
 320                 pos += tx_size;
 321
 322                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 323         }
 324
 325         return 0;
 326 }
 327
 328 static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion)
 329 {
 330         u8 data1, data2;
 331
 332         // check upload was OK
 333         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 334         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 335
 336         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 337         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 338         if ((data1 != 0x67) || (data2 != dspVersion))
 339                 return -EIO;
 340
 341         return 0;
 342 }
 343
 344 static int tda10045_fwupload(struct dvb_frontend* fe)
 345 {
 346         struct tda1004x_state* state = fe->demodulator_priv;
 347         int ret;
 348         const struct firmware *fw;
 349
 350         /* don't re-upload unless necessary */
 351         if (tda1004x_check_upload_ok(state, 0x2c) == 0)
 352                 return 0;
 353
 354         /* request the firmware, this will block until someone uploads it */
 355         printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 356         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 357         if (ret) {
 358                 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
 359                 return ret;
 360         }
 361
 362         /* reset chip */
 363         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 364         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 365         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 366         msleep(10);
 367
 368         /* set parameters */
 369         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 370
 371         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 372         if (ret)
 373                 return ret;
 374         printk("tda1004x: firmware upload complete\n");
 375
 376         /* wait for DSP to initialise */
 377         /* DSPREADY doesn't seem to work on the TDA10045H */
 378         msleep(100);
 379
 380         return tda1004x_check_upload_ok(state, 0x2c);
 381 }
 382
 383 static int tda10046_fwupload(struct dvb_frontend* fe)
 384 {
 385         struct tda1004x_state* state = fe->demodulator_priv;
 386         unsigned long timeout;
 387         int ret;
 388         const struct firmware *fw;
 389
 390         /* reset + wake up chip */
 391         tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0);
 392         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 393         msleep(100);
 394
 395         /* don't re-upload unless necessary */
 396         if (tda1004x_check_upload_ok(state, 0x20) == 0)
 397                 return 0;
 398
 399         /* request the firmware, this will block until someone uploads it */
 400         printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10046_DEFAULT_FIRMWARE);
 401         ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 402         if (ret) {
 403                 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
 404                 return ret;
 405         }
 406
 407         /* set parameters */
 408         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10);
 409         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c);
 410         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
 411         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 412         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 413         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 414
 415         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 416         if (ret)
 417                 return ret;
 418         printk("tda1004x: firmware upload complete\n");
 419
 420         /* wait for DSP to initialise */
 421         timeout = jiffies + HZ;
 422         while (!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 423                 if (time_after(jiffies, timeout)) {
 424                         printk("tda1004x: DSP failed to initialised.\n");
 425                         return -EIO;
 426                 }
 427                 msleep(1);
 428         }
 429
 430         return tda1004x_check_upload_ok(state, 0x20);
 431 }
 432
 433 static int tda1004x_encode_fec(int fec)
 434 {
 435         // convert known FEC values
 436         switch (fec) {
 437         case FEC_1_2:
 438                 return 0;
 439         case FEC_2_3:
 440                 return 1;
 441         case FEC_3_4:
 442                 return 2;
 443         case FEC_5_6:
 444                 return 3;
 445         case FEC_7_8:
 446                 return 4;
 447         }
 448
 449         // unsupported
 450         return -EINVAL;
 451 }
 452
 453 static int tda1004x_decode_fec(int tdafec)
 454 {
 455         // convert known FEC values
 456         switch (tdafec) {
 457         case 0:
 458                 return FEC_1_2;
 459         case 1:
 460                 return FEC_2_3;
 461         case 2:
 462                 return FEC_3_4;
 463         case 3:
 464                 return FEC_5_6;
 465         case 4:
 466                 return FEC_7_8;
 467         }
 468
 469         // unsupported
 470         return -1;
 471 }
 472
 473 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
 474 {
 475         struct tda1004x_state* state = fe->demodulator_priv;
 476
 477         return tda1004x_write_byteI(state, reg, data);
 478 }
 479
 480 static int tda10045_init(struct dvb_frontend* fe)
 481 {
 482         struct tda1004x_state* state = fe->demodulator_priv;
 483
 484         dprintk("%s\n", __FUNCTION__);
 485
 486         if (state->initialised)
 487                 return 0;
 488
 489         if (tda10045_fwupload(fe)) {
 490                 printk("tda1004x: firmware upload failed\n");
 491                 return -EIO;
 492         }
 493
 494         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 495
 496         // Init the PLL
 497         if (state->config->pll_init) {
 498                 tda1004x_enable_tuner_i2c(state);
 499                 state->config->pll_init(fe);
 500                 tda1004x_disable_tuner_i2c(state);
 501         }
 502
 503         // tda setup
 504         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 505         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 506         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 507         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 508         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 509         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 510         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 511         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 512         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 513         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 514         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 515
 516         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 517
 518         state->initialised = 1;
 519         return 0;
 520 }
 521
 522 static int tda10046_init(struct dvb_frontend* fe)
 523 {
 524         struct tda1004x_state* state = fe->demodulator_priv;
 525         dprintk("%s\n", __FUNCTION__);
 526
 527         if (state->initialised)
 528                 return 0;
 529
 530         if (tda10046_fwupload(fe)) {
 531                 printk("tda1004x: firmware upload failed\n");
 532                 return -EIO;
 533         }
 534
 535         tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); // wake up the chip
 536
 537         // Init the PLL
 538         if (state->config->pll_init) {
 539                 tda1004x_enable_tuner_i2c(state);
 540                 state->config->pll_init(fe);
 541                 tda1004x_disable_tuner_i2c(state);
 542         }
 543
 544         // tda setup
 545         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 546         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0x40);
 547         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 548         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
 549         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 550         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c); // PLL P = N = 0
 551         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
 552         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
 553         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
 554         tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0); // AGC setup
 555         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
 556         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 557         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 558         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 559         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 560         tda1004x_write_mask(state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
 561         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 562         tda1004x_write_mask(state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
 563         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 564         tda1004x_write_mask(state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
 565         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
 566         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 567         tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 568         tda1004x_write_mask(state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
 569         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 570
 571         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 572
 573         state->initialised = 1;
 574         return 0;
 575 }
 576
 577 static int tda1004x_set_fe(struct dvb_frontend* fe,
 578                            struct dvb_frontend_parameters *fe_params)
 579 {
 580         struct tda1004x_state* state = fe->demodulator_priv;
 581         int tmp;
 582         int inversion;
 583
 584         dprintk("%s\n", __FUNCTION__);
 585
 586         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 587                 // setup auto offset
 588                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 589                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 590                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 591
 592                 // disable agc_conf[2]
 593                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 594         }
 595
 596         // set frequency
 597         tda1004x_enable_tuner_i2c(state);
 598         state->config->pll_set(fe, fe_params);
 599         tda1004x_disable_tuner_i2c(state);
 600
 601         if (state->demod_type == TDA1004X_DEMOD_TDA10046)
 602                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 4);
 603
 604         // Hardcoded to use auto as much as possible on the TDA10045 as it
 605         // is very unreliable if AUTO mode is _not_ used.
 606         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 607                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 608                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 609                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 610         }
 611
 612         // Set standard params.. or put them to auto
 613         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 614             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 615             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 616             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 617                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 618                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 619                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 620                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 621         } else {
 622                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 623
 624                 // set HP FEC
 625                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 626                 if (tmp < 0)
 627                         return tmp;
 628                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 629
 630                 // set LP FEC
 631                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 632                 if (tmp < 0)
 633                         return tmp;
 634                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 635
 636                 // set constellation
 637                 switch (fe_params->u.ofdm.constellation) {
 638                 case QPSK:
 639                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 640                         break;
 641
 642                 case QAM_16:
 643                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 644                         break;
 645
 646                 case QAM_64:
 647                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 648                         break;
 649
 650                 default:
 651                         return -EINVAL;
 652                 }
 653
 654                 // set hierarchy
 655                 switch (fe_params->u.ofdm.hierarchy_information) {
 656                 case HIERARCHY_NONE:
 657                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 658                         break;
 659
 660                 case HIERARCHY_1:
 661                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 662                         break;
 663
 664                 case HIERARCHY_2:
 665                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 666                         break;
 667
 668                 case HIERARCHY_4:
 669                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 670                         break;
 671
 672                 default:
 673                         return -EINVAL;
 674                 }
 675         }
 676
 677         // set bandwidth
 678         switch (state->demod_type) {
 679         case TDA1004X_DEMOD_TDA10045:
 680                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 681                 break;
 682
 683         case TDA1004X_DEMOD_TDA10046:
 684                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 685                 break;
 686         }
 687
 688         // set inversion
 689         inversion = fe_params->inversion;
 690         if (state->config->invert)
 691                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 692         switch (inversion) {
 693         case INVERSION_OFF:
 694                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 695                 break;
 696
 697         case INVERSION_ON:
 698                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 699                 break;
 700
 701         default:
 702                 return -EINVAL;
 703         }
 704
 705         // set guard interval
 706         switch (fe_params->u.ofdm.guard_interval) {
 707         case GUARD_INTERVAL_1_32:
 708                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 709                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 710                 break;
 711
 712         case GUARD_INTERVAL_1_16:
 713                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 714                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 715                 break;
 716
 717         case GUARD_INTERVAL_1_8:
 718                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 719                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 720                 break;
 721
 722         case GUARD_INTERVAL_1_4:
 723                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 724                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 725                 break;
 726
 727         case GUARD_INTERVAL_AUTO:
 728                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 729                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 730                 break;
 731
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         // set transmission mode
 737         switch (fe_params->u.ofdm.transmission_mode) {
 738         case TRANSMISSION_MODE_2K:
 739                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 740                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 741                 break;
 742
 743         case TRANSMISSION_MODE_8K:
 744                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 745                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 746                 break;
 747
 748         case TRANSMISSION_MODE_AUTO:
 749                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 750                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 751                 break;
 752
 753         default:
 754                 return -EINVAL;
 755         }
 756
 757         // start the lock
 758         switch (state->demod_type) {
 759         case TDA1004X_DEMOD_TDA10045:
 760                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 761                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 762                 break;
 763
 764         case TDA1004X_DEMOD_TDA10046:
 765                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 766                 break;
 767         }
 768
 769         msleep(10);
 770
 771         return 0;
 772 }
 773
 774 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 775 {
 776         struct tda1004x_state* state = fe->demodulator_priv;
 777         dprintk("%s\n", __FUNCTION__);
 778
 779         // inversion status
 780         fe_params->inversion = INVERSION_OFF;
 781         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 782                 fe_params->inversion = INVERSION_ON;
 783         if (state->config->invert)
 784                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 785
 786         // bandwidth
 787         switch (state->demod_type) {
 788         case TDA1004X_DEMOD_TDA10045:
 789                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 790                 case 0x14:
 791                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 792                         break;
 793                 case 0xdb:
 794                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 795                         break;
 796                 case 0x4f:
 797                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 798                         break;
 799                 }
 800                 break;
 801
 802         case TDA1004X_DEMOD_TDA10046:
 803                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 804                 case 0x60:
 805                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 806                         break;
 807                 case 0x6e:
 808                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 809                         break;
 810                 case 0x80:
 811                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 812                         break;
 813                 }
 814                 break;
 815         }
 816
 817         // FEC
 818         fe_params->u.ofdm.code_rate_HP =
 819             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 820         fe_params->u.ofdm.code_rate_LP =
 821             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 822
 823         // constellation
 824         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 825         case 0:
 826                 fe_params->u.ofdm.constellation = QPSK;
 827                 break;
 828         case 1:
 829                 fe_params->u.ofdm.constellation = QAM_16;
 830                 break;
 831         case 2:
 832                 fe_params->u.ofdm.constellation = QAM_64;
 833                 break;
 834         }
 835
 836         // transmission mode
 837         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 838         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 839                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 840
 841         // guard interval
 842         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 843         case 0:
 844                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 845                 break;
 846         case 1:
 847                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 848                 break;
 849         case 2:
 850                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 851                 break;
 852         case 3:
 853                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 854                 break;
 855         }
 856
 857         // hierarchy
 858         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 859         case 0:
 860                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 861                 break;
 862         case 1:
 863                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 864                 break;
 865         case 2:
 866                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 867                 break;
 868         case 3:
 869                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 870                 break;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 877 {
 878         struct tda1004x_state* state = fe->demodulator_priv;
 879         int status;
 880         int cber;
 881         int vber;
 882
 883         dprintk("%s\n", __FUNCTION__);
 884
 885         // read status
 886         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 887         if (status == -1)
 888                 return -EIO;
 889
 890         // decode
 891         *fe_status = 0;
 892         if (status & 4)
 893                 *fe_status |= FE_HAS_SIGNAL;
 894         if (status & 2)
 895                 *fe_status |= FE_HAS_CARRIER;
 896         if (status & 8)
 897                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 898
 899         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
 900         // is getting anything valid
 901         if (!(*fe_status & FE_HAS_VITERBI)) {
 902                 // read the CBER
 903                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
 904                 if (cber == -1)
 905                         return -EIO;
 906                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
 907                 if (status == -1)
 908                         return -EIO;
 909                 cber |= (status << 8);
 910                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
 911
 912                 if (cber != 65535)
 913                         *fe_status |= FE_HAS_VITERBI;
 914         }
 915
 916         // if we DO have some valid VITERBI output, but don't already have SYNC
 917         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
 918         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
 919                 // read the VBER
 920                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
 921                 if (vber == -1)
 922                         return -EIO;
 923                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
 924                 if (status == -1)
 925                         return -EIO;
 926                 vber |= (status << 8);
 927                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
 928                 if (status == -1)
 929                         return -EIO;
 930                 vber |= ((status << 16) & 0x0f);
 931                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
 932
 933                 // if RS has passed some valid TS packets, then we must be
 934                 // getting some SYNC bytes
 935                 if (vber < 16632)
 936                         *fe_status |= FE_HAS_SYNC;
 937         }
 938
 939         // success
 940         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
 941         return 0;
 942 }
 943
 944 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
 945 {
 946         struct tda1004x_state* state = fe->demodulator_priv;
 947         int tmp;
 948         int reg = 0;
 949
 950         dprintk("%s\n", __FUNCTION__);
 951
 952         // determine the register to use
 953         switch (state->demod_type) {
 954         case TDA1004X_DEMOD_TDA10045:
 955                 reg = TDA10045H_S_AGC;
 956                 break;
 957
 958         case TDA1004X_DEMOD_TDA10046:
 959                 reg = TDA10046H_AGC_IF_LEVEL;
 960                 break;
 961         }
 962
 963         // read it
 964         tmp = tda1004x_read_byte(state, reg);
 965         if (tmp < 0)
 966                 return -EIO;
 967
 968         *signal = (tmp << 8) | tmp;
 969         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
 970         return 0;
 971 }
 972
 973 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
 974 {
 975         struct tda1004x_state* state = fe->demodulator_priv;
 976         int tmp;
 977
 978         dprintk("%s\n", __FUNCTION__);
 979
 980         // read it
 981         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
 982         if (tmp < 0)
 983                 return -EIO;
 984         if (tmp)
 985                 tmp = 255 - tmp;
 986
 987         *snr = ((tmp << 8) | tmp);
 988         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
 989         return 0;
 990 }
 991
 992 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 993 {
 994         struct tda1004x_state* state = fe->demodulator_priv;
 995         int tmp;
 996         int tmp2;
 997         int counter;
 998
 999         dprintk("%s\n", __FUNCTION__);
1000
1001         // read the UCBLOCKS and reset
1002         counter = 0;
1003         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1004         if (tmp < 0)
1005                 return -EIO;
1006         tmp &= 0x7f;
1007         while (counter++ < 5) {
1008                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1009                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1010                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1011
1012                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1013                 if (tmp2 < 0)
1014                         return -EIO;
1015                 tmp2 &= 0x7f;
1016                 if ((tmp2 < tmp) || (tmp2 == 0))
1017                         break;
1018         }
1019
1020         if (tmp != 0x7f)
1021                 *ucblocks = tmp;
1022         else
1023                 *ucblocks = 0xffffffff;
1024
1025         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1026         return 0;
1027 }
1028
1029 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1030 {
1031         struct tda1004x_state* state = fe->demodulator_priv;
1032         int tmp;
1033
1034         dprintk("%s\n", __FUNCTION__);
1035
1036         // read it in
1037         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1038         if (tmp < 0)
1039                 return -EIO;
1040         *ber = tmp << 1;
1041         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1042         if (tmp < 0)
1043                 return -EIO;
1044         *ber |= (tmp << 9);
1045         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1046
1047         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1048         return 0;
1049 }
1050
1051 static int tda1004x_sleep(struct dvb_frontend* fe)
1052 {
1053         struct tda1004x_state* state = fe->demodulator_priv;
1054
1055         switch (state->demod_type) {
1056         case TDA1004X_DEMOD_TDA10045:
1057                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1058                 break;
1059
1060         case TDA1004X_DEMOD_TDA10046:
1061                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1062                 break;
1063         }
1064         state->initialised = 0;
1065
1066         return 0;
1067 }
1068
1069 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1070 {
1071         fesettings->min_delay_ms = 800;
1072         fesettings->step_size = 166667;
1073         fesettings->max_drift = 166667*2;
1074         return 0;
1075 }
1076
1077 static void tda1004x_release(struct dvb_frontend* fe)
1078 {
1079         struct tda1004x_state *state = fe->demodulator_priv;
1080         kfree(state);
1081 }
1082
1083 static struct dvb_frontend_ops tda10045_ops = {
1084         .info = {
1085                 .name = "Philips TDA10045H DVB-T",
1086                 .type = FE_OFDM,
1087                 .frequency_min = 51000000,
1088                 .frequency_max = 858000000,
1089                 .frequency_stepsize = 166667,
1090                 .caps =
1091                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1092                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1093                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1094                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1095         },
1096
1097         .release = tda1004x_release,
1098
1099         .init = tda10045_init,
1100         .sleep = tda1004x_sleep,
1101
1102         .set_frontend = tda1004x_set_fe,
1103         .get_frontend = tda1004x_get_fe,
1104         .get_tune_settings = tda1004x_get_tune_settings,
1105
1106         .read_status = tda1004x_read_status,
1107         .read_ber = tda1004x_read_ber,
1108         .read_signal_strength = tda1004x_read_signal_strength,
1109         .read_snr = tda1004x_read_snr,
1110         .read_ucblocks = tda1004x_read_ucblocks,
1111 };
1112
1113 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1114                                      struct i2c_adapter* i2c)
1115 {
1116         struct tda1004x_state *state;
1117
1118         /* allocate memory for the internal state */
1119         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1120         if (!state)
1121                 return NULL;
1122
1123         /* setup the state */
1124         state->config = config;
1125         state->i2c = i2c;
1126         memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1127         state->initialised = 0;
1128         state->demod_type = TDA1004X_DEMOD_TDA10045;
1129
1130         /* check if the demod is there */
1131         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1132                 kfree(state);
1133                 return NULL;
1134         }
1135
1136         /* create dvb_frontend */
1137         state->frontend.ops = &state->ops;
1138         state->frontend.demodulator_priv = state;
1139         return &state->frontend;
1140 }
1141
1142 static struct dvb_frontend_ops tda10046_ops = {
1143         .info = {
1144                 .name = "Philips TDA10046H DVB-T",
1145                 .type = FE_OFDM,
1146                 .frequency_min = 51000000,
1147                 .frequency_max = 858000000,
1148                 .frequency_stepsize = 166667,
1149                 .caps =
1150                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1151                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1152                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1153                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1154         },
1155
1156         .release = tda1004x_release,
1157
1158         .init = tda10046_init,
1159         .sleep = tda1004x_sleep,
1160
1161         .set_frontend = tda1004x_set_fe,
1162         .get_frontend = tda1004x_get_fe,
1163         .get_tune_settings = tda1004x_get_tune_settings,
1164
1165         .read_status = tda1004x_read_status,
1166         .read_ber = tda1004x_read_ber,
1167         .read_signal_strength = tda1004x_read_signal_strength,
1168         .read_snr = tda1004x_read_snr,
1169         .read_ucblocks = tda1004x_read_ucblocks,
1170 };
1171
1172 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1173                                      struct i2c_adapter* i2c)
1174 {
1175         struct tda1004x_state *state;
1176
1177         /* allocate memory for the internal state */
1178         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1179         if (!state)
1180                 return NULL;
1181
1182         /* setup the state */
1183         state->config = config;
1184         state->i2c = i2c;
1185         memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1186         state->initialised = 0;
1187         state->demod_type = TDA1004X_DEMOD_TDA10046;
1188
1189         /* check if the demod is there */
1190         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1191                 kfree(state);
1192                 return NULL;
1193         }
1194
1195         /* create dvb_frontend */
1196         state->frontend.ops = &state->ops;
1197         state->frontend.demodulator_priv = state;
1198         return &state->frontend;
1199 }
1200
1201 module_param(debug, int, 0644);
1202 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1203
1204 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1205 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1206 MODULE_LICENSE("GPL");
1207
1208 EXPORT_SYMBOL(tda10045_attach);
1209 EXPORT_SYMBOL(tda10046_attach);
1210 EXPORT_SYMBOL(tda1004x_write_byte);