drivers/ide/au1xxx-ide.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   4  *
   5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   6  *
   7  * This program is free software; you can redistribute it and/or modify it under
   8  * the terms of the GNU General Public License as published by the Free Software
   9  * Foundation; either version 2 of the License, or (at your option) any later
  10  * version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  21  * POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program; if not, write to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  28  *       Interface and Linux Device Driver" Application Note.
  29  */
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/delay.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/ide.h>
  37 #include <linux/scatterlist.h>
  38
  39 #include <asm/mach-au1x00/au1xxx.h>
  40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  41 #include <asm/mach-au1x00/au1xxx_ide.h>
  42
  43 #define DRV_NAME        "au1200-ide"
  44 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  45
  46 /* enable the burstmode in the dbdma */
  47 #define IDE_AU1XXX_BURSTMODE    1
  48
  49 static _auide_hwif auide_hwif;
  50
  51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  52
  53 static inline void auide_insw(unsigned long port, void *addr, u32 count)
  54 {
  55         _auide_hwif *ahwif = &auide_hwif;
  56         chan_tab_t *ctp;
  57         au1x_ddma_desc_t *dp;
  58
  59         if (!au1xxx_dbdma_put_dest(ahwif->rx_chan, virt_to_phys(addr),
  60                                    count << 1, DDMA_FLAGS_NOIE)) {
  61                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  62                 return;
  63         }
  64         ctp = *((chan_tab_t **)ahwif->rx_chan);
  65         dp = ctp->cur_ptr;
  66         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  67                 ;
  68         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  69 }
  70
  71 static inline void auide_outsw(unsigned long port, void *addr, u32 count)
  72 {
  73         _auide_hwif *ahwif = &auide_hwif;
  74         chan_tab_t *ctp;
  75         au1x_ddma_desc_t *dp;
  76
  77         if (!au1xxx_dbdma_put_source(ahwif->tx_chan, virt_to_phys(addr),
  78                                      count << 1, DDMA_FLAGS_NOIE)) {
  79                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  80                 return;
  81         }
  82         ctp = *((chan_tab_t **)ahwif->tx_chan);
  83         dp = ctp->cur_ptr;
  84         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  85                 ;
  86         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  87 }
  88
  89 static void au1xxx_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
  90                               void *buf, unsigned int len)
  91 {
  92         auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  93 }
  94
  95 static void au1xxx_output_data(ide_drive_t *drive, struct ide_cmd *cmd,
  96                                void *buf, unsigned int len)
  97 {
  98         auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  99 }
 100 #endif
 101
 102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 103 {
 104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 105
 106         /* set pio mode! */
 107         switch(pio) {
 108         case 0:
 109                 mem_sttime = SBC_IDE_TIMING(PIO0);
 110
 111                 /* set configuration for RCS2# */
 112                 mem_stcfg |= TS_MASK;
 113                 mem_stcfg &= ~TCSOE_MASK;
 114                 mem_stcfg &= ~TOECS_MASK;
 115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 116                 break;
 117
 118         case 1:
 119                 mem_sttime = SBC_IDE_TIMING(PIO1);
 120
 121                 /* set configuration for RCS2# */
 122                 mem_stcfg |= TS_MASK;
 123                 mem_stcfg &= ~TCSOE_MASK;
 124                 mem_stcfg &= ~TOECS_MASK;
 125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 126                 break;
 127
 128         case 2:
 129                 mem_sttime = SBC_IDE_TIMING(PIO2);
 130
 131                 /* set configuration for RCS2# */
 132                 mem_stcfg &= ~TS_MASK;
 133                 mem_stcfg &= ~TCSOE_MASK;
 134                 mem_stcfg &= ~TOECS_MASK;
 135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 136                 break;
 137
 138         case 3:
 139                 mem_sttime = SBC_IDE_TIMING(PIO3);
 140
 141                 /* set configuration for RCS2# */
 142                 mem_stcfg &= ~TS_MASK;
 143                 mem_stcfg &= ~TCSOE_MASK;
 144                 mem_stcfg &= ~TOECS_MASK;
 145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 146
 147                 break;
 148
 149         case 4:
 150                 mem_sttime = SBC_IDE_TIMING(PIO4);
 151
 152                 /* set configuration for RCS2# */
 153                 mem_stcfg &= ~TS_MASK;
 154                 mem_stcfg &= ~TCSOE_MASK;
 155                 mem_stcfg &= ~TOECS_MASK;
 156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 157                 break;
 158         }
 159
 160         au_writel(mem_sttime,MEM_STTIME2);
 161         au_writel(mem_stcfg,MEM_STCFG2);
 162 }
 163
 164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
 165 {
 166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 167
 168         switch(speed) {
 169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 170         case XFER_MW_DMA_2:
 171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 172
 173                 /* set configuration for RCS2# */
 174                 mem_stcfg &= ~TS_MASK;
 175                 mem_stcfg &= ~TCSOE_MASK;
 176                 mem_stcfg &= ~TOECS_MASK;
 177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 178
 179                 break;
 180         case XFER_MW_DMA_1:
 181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 182
 183                 /* set configuration for RCS2# */
 184                 mem_stcfg &= ~TS_MASK;
 185                 mem_stcfg &= ~TCSOE_MASK;
 186                 mem_stcfg &= ~TOECS_MASK;
 187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 188
 189                 break;
 190         case XFER_MW_DMA_0:
 191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 192
 193                 /* set configuration for RCS2# */
 194                 mem_stcfg |= TS_MASK;
 195                 mem_stcfg &= ~TCSOE_MASK;
 196                 mem_stcfg &= ~TOECS_MASK;
 197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 198
 199                 break;
 200 #endif
 201         }
 202
 203         au_writel(mem_sttime,MEM_STTIME2);
 204         au_writel(mem_stcfg,MEM_STCFG2);
 205 }
 206
 207 /*
 208  * Multi-Word DMA + DbDMA functions
 209  */
 210
 211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 212 static int auide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
 213 {
 214         ide_hwif_t *hwif = drive->hwif;
 215         _auide_hwif *ahwif = &auide_hwif;
 216         struct scatterlist *sg;
 217         int i = cmd->sg_nents, count = 0;
 218         int iswrite = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
 219
 220         /* Save for interrupt context */
 221         ahwif->drive = drive;
 222
 223         /* fill the descriptors */
 224         sg = hwif->sg_table;
 225         while (i && sg_dma_len(sg)) {
 226                 u32 cur_addr;
 227                 u32 cur_len;
 228
 229                 cur_addr = sg_dma_address(sg);
 230                 cur_len = sg_dma_len(sg);
 231
 232                 while (cur_len) {
 233                         u32 flags = DDMA_FLAGS_NOIE;
 234                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 235
 236                         if (++count >= PRD_ENTRIES) {
 237                                 printk(KERN_WARNING "%s: DMA table too small\n",
 238                                        drive->name);
 239                                 return 0;
 240                         }
 241
 242                         /* Lets enable intr for the last descriptor only */
 243                         if (1==i)
 244                                 flags = DDMA_FLAGS_IE;
 245                         else
 246                                 flags = DDMA_FLAGS_NOIE;
 247
 248                         if (iswrite) {
 249                                 if (!au1xxx_dbdma_put_source(ahwif->tx_chan,
 250                                         sg_phys(sg), tc, flags)) {
 251                                         printk(KERN_ERR "%s failed %d\n",
 252                                                __func__, __LINE__);
 253                                 }
 254                         } else  {
 255                                 if (!au1xxx_dbdma_put_dest(ahwif->rx_chan,
 256                                         sg_phys(sg), tc, flags)) {
 257                                         printk(KERN_ERR "%s failed %d\n",
 258                                                __func__, __LINE__);
 259                                 }
 260                         }
 261
 262                         cur_addr += tc;
 263                         cur_len -= tc;
 264                 }
 265                 sg = sg_next(sg);
 266                 i--;
 267         }
 268
 269         if (count)
 270                 return 1;
 271
 272         return 0; /* revert to PIO for this request */
 273 }
 274
 275 static int auide_dma_end(ide_drive_t *drive)
 276 {
 277         return 0;
 278 }
 279
 280 static void auide_dma_start(ide_drive_t *drive )
 281 {
 282 }
 283
 284
 285 static int auide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
 286 {
 287         if (auide_build_dmatable(drive, cmd) == 0)
 288                 return 1;
 289
 290         return 0;
 291 }
 292
 293 static int auide_dma_test_irq(ide_drive_t *drive)
 294 {
 295         /* If dbdma didn't execute the STOP command yet, the
 296          * active bit is still set
 297          */
 298         drive->waiting_for_dma++;
 299         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 300                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 301                                      complete\n", drive->name);
 302                 return 1;
 303         }
 304         udelay(10);
 305         return 0;
 306 }
 307
 308 static void auide_dma_host_set(ide_drive_t *drive, int on)
 309 {
 310 }
 311
 312 static void auide_ddma_tx_callback(int irq, void *param)
 313 {
 314 }
 315
 316 static void auide_ddma_rx_callback(int irq, void *param)
 317 {
 318 }
 319 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 320
 321 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 322 {
 323         dev->dev_id          = dev_id;
 324         dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
 325         dev->dev_intlevel    = 0;
 326         dev->dev_intpolarity = 0;
 327         dev->dev_tsize       = tsize;
 328         dev->dev_devwidth    = devwidth;
 329         dev->dev_flags       = flags;
 330 }
 331
 332 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 333 static const struct ide_dma_ops au1xxx_dma_ops = {
 334         .dma_host_set           = auide_dma_host_set,
 335         .dma_setup              = auide_dma_setup,
 336         .dma_start              = auide_dma_start,
 337         .dma_end                = auide_dma_end,
 338         .dma_test_irq           = auide_dma_test_irq,
 339         .dma_lost_irq           = ide_dma_lost_irq,
 340 };
 341
 342 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 343 {
 344         _auide_hwif *auide = &auide_hwif;
 345         dbdev_tab_t source_dev_tab, target_dev_tab;
 346         u32 dev_id, tsize, devwidth, flags;
 347
 348         dev_id   = IDE_DDMA_REQ;
 349
 350         tsize    =  8; /*  1 */
 351         devwidth = 32; /* 16 */
 352
 353 #ifdef IDE_AU1XXX_BURSTMODE
 354         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 355 #else
 356         flags = DEV_FLAGS_SYNC;
 357 #endif
 358
 359         /* setup dev_tab for tx channel */
 360         auide_init_dbdma_dev( &source_dev_tab,
 361                               dev_id,
 362                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 363         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 364
 365         auide_init_dbdma_dev( &source_dev_tab,
 366                               dev_id,
 367                               tsize, devwidth, DEV_FLAGS_IN | flags);
 368         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 369
 370         /* We also need to add a target device for the DMA */
 371         auide_init_dbdma_dev( &target_dev_tab,
 372                               (u32)DSCR_CMD0_ALWAYS,
 373                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 374         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 375
 376         /* Get a channel for TX */
 377         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 378                                                  auide->tx_dev_id,
 379                                                  auide_ddma_tx_callback,
 380                                                  (void*)auide);
 381
 382         /* Get a channel for RX */
 383         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 384                                                  auide->target_dev_id,
 385                                                  auide_ddma_rx_callback,
 386                                                  (void*)auide);
 387
 388         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 389                                                              NUM_DESCRIPTORS);
 390         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 391                                                              NUM_DESCRIPTORS);
 392
 393         /* FIXME: check return value */
 394         (void)ide_allocate_dma_engine(hwif);
 395
 396         au1xxx_dbdma_start( auide->tx_chan );
 397         au1xxx_dbdma_start( auide->rx_chan );
 398
 399         return 0;
 400 }
 401 #else
 402 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 403 {
 404         _auide_hwif *auide = &auide_hwif;
 405         dbdev_tab_t source_dev_tab;
 406         int flags;
 407
 408 #ifdef IDE_AU1XXX_BURSTMODE
 409         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 410 #else
 411         flags = DEV_FLAGS_SYNC;
 412 #endif
 413
 414         /* setup dev_tab for tx channel */
 415         auide_init_dbdma_dev( &source_dev_tab,
 416                               (u32)DSCR_CMD0_ALWAYS,
 417                               8, 32, DEV_FLAGS_OUT | flags);
 418         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 419
 420         auide_init_dbdma_dev( &source_dev_tab,
 421                               (u32)DSCR_CMD0_ALWAYS,
 422                               8, 32, DEV_FLAGS_IN | flags);
 423         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 424
 425         /* Get a channel for TX */
 426         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 427                                                  auide->tx_dev_id,
 428                                                  NULL,
 429                                                  (void*)auide);
 430
 431         /* Get a channel for RX */
 432         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 433                                                  DSCR_CMD0_ALWAYS,
 434                                                  NULL,
 435                                                  (void*)auide);
 436
 437         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 438                                                              NUM_DESCRIPTORS);
 439         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 440                                                              NUM_DESCRIPTORS);
 441
 442         au1xxx_dbdma_start( auide->tx_chan );
 443         au1xxx_dbdma_start( auide->rx_chan );
 444
 445         return 0;
 446 }
 447 #endif
 448
 449 static void auide_setup_ports(struct ide_hw *hw, _auide_hwif *ahwif)
 450 {
 451         int i;
 452         unsigned long *ata_regs = hw->io_ports_array;
 453
 454         /* FIXME? */
 455         for (i = 0; i < 8; i++)
 456                 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
 457
 458         /* set the Alternative Status register */
 459         *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
 460 }
 461
 462 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 463 static const struct ide_tp_ops au1xxx_tp_ops = {
 464         .exec_command           = ide_exec_command,
 465         .read_status            = ide_read_status,
 466         .read_altstatus         = ide_read_altstatus,
 467         .write_devctl           = ide_write_devctl,
 468
 469         .dev_select             = ide_dev_select,
 470         .tf_load                = ide_tf_load,
 471         .tf_read                = ide_tf_read,
 472
 473         .input_data             = au1xxx_input_data,
 474         .output_data            = au1xxx_output_data,
 475 };
 476 #endif
 477
 478 static const struct ide_port_ops au1xxx_port_ops = {
 479         .set_pio_mode           = au1xxx_set_pio_mode,
 480         .set_dma_mode           = auide_set_dma_mode,
 481 };
 482
 483 static const struct ide_port_info au1xxx_port_info = {
 484         .init_dma               = auide_ddma_init,
 485 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 486         .tp_ops                 = &au1xxx_tp_ops,
 487 #endif
 488         .port_ops               = &au1xxx_port_ops,
 489 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 490         .dma_ops                = &au1xxx_dma_ops,
 491 #endif
 492         .host_flags             = IDE_HFLAG_POST_SET_MODE |
 493                                   IDE_HFLAG_NO_IO_32BIT |
 494                                   IDE_HFLAG_UNMASK_IRQS,
 495         .pio_mask               = ATA_PIO4,
 496 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 497         .mwdma_mask             = ATA_MWDMA2,
 498 #endif
 499         .chipset                = ide_au1xxx,
 500 };
 501
 502 static int au_ide_probe(struct platform_device *dev)
 503 {
 504         _auide_hwif *ahwif = &auide_hwif;
 505         struct resource *res;
 506         struct ide_host *host;
 507         int ret = 0;
 508         struct ide_hw hw, *hws[] = { &hw };
 509
 510 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 511         char *mode = "MWDMA2";
 512 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 513         char *mode = "PIO+DDMA(offload)";
 514 #endif
 515
 516         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 517         ahwif->irq = platform_get_irq(dev, 0);
 518
 519         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 520
 521         if (res == NULL) {
 522                 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
 523                 ret = -ENODEV;
 524                 goto out;
 525         }
 526         if (ahwif->irq < 0) {
 527                 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
 528                 ret = -ENODEV;
 529                 goto out;
 530         }
 531
 532         if (!request_mem_region(res->start, resource_size(res), dev->name)) {
 533                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 534                 ret =  -EBUSY;
 535                 goto out;
 536         }
 537
 538         ahwif->regbase = (u32)ioremap(res->start, resource_size(res));
 539         if (ahwif->regbase == 0) {
 540                 ret = -ENOMEM;
 541                 goto out;
 542         }
 543
 544         memset(&hw, 0, sizeof(hw));
 545         auide_setup_ports(&hw, ahwif);
 546         hw.irq = ahwif->irq;
 547         hw.dev = &dev->dev;
 548
 549         ret = ide_host_add(&au1xxx_port_info, hws, 1, &host);
 550         if (ret)
 551                 goto out;
 552
 553         auide_hwif.hwif = host->ports[0];
 554
 555         platform_set_drvdata(dev, host);
 556
 557         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 558
 559  out:
 560         return ret;
 561 }
 562
 563 static int au_ide_remove(struct platform_device *dev)
 564 {
 565         struct resource *res;
 566         struct ide_host *host = platform_get_drvdata(dev);
 567         _auide_hwif *ahwif = &auide_hwif;
 568
 569         ide_host_remove(host);
 570
 571         iounmap((void *)ahwif->regbase);
 572
 573         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 574         release_mem_region(res->start, resource_size(res));
 575
 576         return 0;
 577 }
 578
 579 static struct platform_driver au1200_ide_driver = {
 580         .driver = {
 581                 .name           = "au1200-ide",
 582                 .owner          = THIS_MODULE,
 583         },
 584         .probe          = au_ide_probe,
 585         .remove         = au_ide_remove,
 586 };
 587
 588 static int __init au_ide_init(void)
 589 {
 590         return platform_driver_register(&au1200_ide_driver);
 591 }
 592
 593 static void __exit au_ide_exit(void)
 594 {
 595         platform_driver_unregister(&au1200_ide_driver);
 596 }
 597
 598 MODULE_LICENSE("GPL");
 599 MODULE_DESCRIPTION("AU1200 IDE driver");
 600
 601 module_init(au_ide_init);
 602 module_exit(au_ide_exit);