drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly separated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c-id.h>
  26 #include <linux/init.h>
  27 #include <linux/time.h>
  28 #include <linux/sched.h>
  29 #include <linux/delay.h>
  30 #include <linux/errno.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/i2c-pxa.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/err.h>
  35 #include <linux/clk.h>
  36 #include <linux/slab.h>
  37
  38 #include <asm/irq.h>
  39 #include <asm/io.h>
  40 #include <plat/i2c.h>
  41
  42 /*
  43  * I2C register offsets will be shifted 0 or 1 bit left, depending on
  44  * different SoCs
  45  */
  46 #define REG_SHIFT_0     (0 << 0)
  47 #define REG_SHIFT_1     (1 << 0)
  48 #define REG_SHIFT(d)    ((d) & 0x1)
  49
  50 static const struct platform_device_id i2c_pxa_id_table[] = {
  51         { "pxa2xx-i2c",         REG_SHIFT_1 },
  52         { "pxa3xx-pwri2c",      REG_SHIFT_0 },
  53         { },
  54 };
  55 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
  56
  57 /*
  58  * I2C registers and bit definitions
  59  */
  60 #define IBMR            (0x00)
  61 #define IDBR            (0x08)
  62 #define ICR             (0x10)
  63 #define ISR             (0x18)
  64 #define ISAR            (0x20)
  65
  66 #define ICR_START       (1 << 0)           /* start bit */
  67 #define ICR_STOP        (1 << 1)           /* stop bit */
  68 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
  69 #define ICR_TB          (1 << 3)           /* transfer byte bit */
  70 #define ICR_MA          (1 << 4)           /* master abort */
  71 #define ICR_SCLE        (1 << 5)           /* master clock enable */
  72 #define ICR_IUE         (1 << 6)           /* unit enable */
  73 #define ICR_GCD         (1 << 7)           /* general call disable */
  74 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
  75 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
  76 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
  77 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
  78 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
  79 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
  80 #define ICR_UR          (1 << 14)          /* unit reset */
  81 #define ICR_FM          (1 << 15)          /* fast mode */
  82
  83 #define ISR_RWM         (1 << 0)           /* read/write mode */
  84 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
  85 #define ISR_UB          (1 << 2)           /* unit busy */
  86 #define ISR_IBB         (1 << 3)           /* bus busy */
  87 #define ISR_SSD         (1 << 4)           /* slave stop detected */
  88 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
  89 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
  90 #define ISR_IRF         (1 << 7)           /* rx buffer full */
  91 #define ISR_GCAD        (1 << 8)           /* general call address detected */
  92 #define ISR_SAD         (1 << 9)           /* slave address detected */
  93 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
  94
  95 struct pxa_i2c {
  96         spinlock_t              lock;
  97         wait_queue_head_t       wait;
  98         struct i2c_msg          *msg;
  99         unsigned int            msg_num;
 100         unsigned int            msg_idx;
 101         unsigned int            msg_ptr;
 102         unsigned int            slave_addr;
 103
 104         struct i2c_adapter      adap;
 105         struct clk              *clk;
 106 #ifdef CONFIG_I2C_PXA_SLAVE
 107         struct i2c_slave_client *slave;
 108 #endif
 109
 110         unsigned int            irqlogidx;
 111         u32                     isrlog[32];
 112         u32                     icrlog[32];
 113
 114         void __iomem            *reg_base;
 115         unsigned int            reg_shift;
 116
 117         unsigned long           iobase;
 118         unsigned long           iosize;
 119
 120         int                     irq;
 121         unsigned int            use_pio :1;
 122         unsigned int            fast_mode :1;
 123 };
 124
 125 #define _IBMR(i2c)      ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
 126 #define _IDBR(i2c)      ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
 127 #define _ICR(i2c)       ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
 128 #define _ISR(i2c)       ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
 129 #define _ISAR(i2c)      ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
 130
 131 /*
 132  * I2C Slave mode address
 133  */
 134 #define I2C_PXA_SLAVE_ADDR      0x1
 135
 136 #ifdef DEBUG
 137
 138 struct bits {
 139         u32     mask;
 140         const char *set;
 141         const char *unset;
 142 };
 143 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 144
 145 static inline void
 146 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 147 {
 148         printk("%s %08x: ", prefix, val);
 149         while (num--) {
 150                 const char *str = val & bits->mask ? bits->set : bits->unset;
 151                 if (str)
 152                         printk("%s ", str);
 153                 bits++;
 154         }
 155 }
 156
 157 static const struct bits isr_bits[] = {
 158         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 159         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 160         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 161         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 162         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 163         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 164         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 165         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 166         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 167         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 168         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 169 };
 170
 171 static void decode_ISR(unsigned int val)
 172 {
 173         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 174         printk("\n");
 175 }
 176
 177 static const struct bits icr_bits[] = {
 178         PXA_BIT(ICR_START,  "START",    NULL),
 179         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 180         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 181         PXA_BIT(ICR_TB,     "TB",       NULL),
 182         PXA_BIT(ICR_MA,     "MA",       NULL),
 183         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 184         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 185         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 186         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 187         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 188         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 189         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 190         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 191         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 192         PXA_BIT(ICR_UR,     "UR",               "ur"),
 193 };
 194
 195 #ifdef CONFIG_I2C_PXA_SLAVE
 196 static void decode_ICR(unsigned int val)
 197 {
 198         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 199         printk("\n");
 200 }
 201 #endif
 202
 203 static unsigned int i2c_debug = DEBUG;
 204
 205 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 206 {
 207         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 208                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 209 }
 210
 211 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 212 #else
 213 #define i2c_debug       0
 214
 215 #define show_state(i2c) do { } while (0)
 216 #define decode_ISR(val) do { } while (0)
 217 #define decode_ICR(val) do { } while (0)
 218 #endif
 219
 220 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 221 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 222
 223 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 224 {
 225         unsigned int i;
 226         printk(KERN_ERR "i2c: error: %s\n", why);
 227         printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 228                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 229         printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
 230                readl(_ICR(i2c)), readl(_ISR(i2c)));
 231         printk(KERN_DEBUG "i2c: log: ");
 232         for (i = 0; i < i2c->irqlogidx; i++)
 233                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 234         printk("\n");
 235 }
 236
 237 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 238 {
 239         return !(readl(_ICR(i2c)) & ICR_SCLE);
 240 }
 241
 242 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 243 {
 244         int i = 250;
 245
 246         if (i2c_pxa_is_slavemode(i2c)) {
 247                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 248                 return;
 249         }
 250
 251         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 252                 unsigned long icr = readl(_ICR(i2c));
 253
 254                 icr &= ~ICR_START;
 255                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 256
 257                 writel(icr, _ICR(i2c));
 258
 259                 show_state(i2c);
 260
 261                 mdelay(1);
 262                 i --;
 263         }
 264
 265         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 266                _ICR(i2c));
 267 }
 268
 269 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 270 {
 271         int timeout = DEF_TIMEOUT;
 272
 273         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 274                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 275                         timeout += 4;
 276
 277                 msleep(2);
 278                 show_state(i2c);
 279         }
 280
 281         if (timeout < 0)
 282                 show_state(i2c);
 283
 284         return timeout < 0 ? I2C_RETRY : 0;
 285 }
 286
 287 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 288 {
 289         unsigned long timeout = jiffies + HZ*4;
 290
 291         while (time_before(jiffies, timeout)) {
 292                 if (i2c_debug > 1)
 293                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 294                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 295
 296                 if (readl(_ISR(i2c)) & ISR_SAD) {
 297                         if (i2c_debug > 0)
 298                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 299                         goto out;
 300                 }
 301
 302                 /* wait for unit and bus being not busy, and we also do a
 303                  * quick check of the i2c lines themselves to ensure they've
 304                  * gone high...
 305                  */
 306                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 307                         if (i2c_debug > 0)
 308                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 309                         return 1;
 310                 }
 311
 312                 msleep(1);
 313         }
 314
 315         if (i2c_debug > 0)
 316                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 317  out:
 318         return 0;
 319 }
 320
 321 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 322 {
 323         if (i2c_debug)
 324                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 325
 326         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 327                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 328                 if (!i2c_pxa_wait_master(i2c)) {
 329                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 330                         return I2C_RETRY;
 331                 }
 332         }
 333
 334         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 335         return 0;
 336 }
 337
 338 #ifdef CONFIG_I2C_PXA_SLAVE
 339 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 340 {
 341         unsigned long timeout = jiffies + HZ*1;
 342
 343         /* wait for stop */
 344
 345         show_state(i2c);
 346
 347         while (time_before(jiffies, timeout)) {
 348                 if (i2c_debug > 1)
 349                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 350                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 351
 352                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 353                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 354                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 355                         if (i2c_debug > 1)
 356                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 357                         return 1;
 358                 }
 359
 360                 msleep(1);
 361         }
 362
 363         if (i2c_debug > 0)
 364                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 365         return 0;
 366 }
 367
 368 /*
 369  * clear the hold on the bus, and take of anything else
 370  * that has been configured
 371  */
 372 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 373 {
 374         show_state(i2c);
 375
 376         if (errcode < 0) {
 377                 udelay(100);   /* simple delay */
 378         } else {
 379                 /* we need to wait for the stop condition to end */
 380
 381                 /* if we where in stop, then clear... */
 382                 if (readl(_ICR(i2c)) & ICR_STOP) {
 383                         udelay(100);
 384                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 385                 }
 386
 387                 if (!i2c_pxa_wait_slave(i2c)) {
 388                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 389                                 __func__);
 390                         return;
 391                 }
 392         }
 393
 394         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 395         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 396
 397         if (i2c_debug) {
 398                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 399                 decode_ICR(readl(_ICR(i2c)));
 400         }
 401 }
 402 #else
 403 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 404 #endif
 405
 406 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 407 {
 408         pr_debug("Resetting I2C Controller Unit\n");
 409
 410         /* abort any transfer currently under way */
 411         i2c_pxa_abort(i2c);
 412
 413         /* reset according to 9.8 */
 414         writel(ICR_UR, _ICR(i2c));
 415         writel(I2C_ISR_INIT, _ISR(i2c));
 416         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 417
 418         writel(i2c->slave_addr, _ISAR(i2c));
 419
 420         /* set control register values */
 421         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
 422
 423 #ifdef CONFIG_I2C_PXA_SLAVE
 424         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 425         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 426 #endif
 427
 428         i2c_pxa_set_slave(i2c, 0);
 429
 430         /* enable unit */
 431         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 432         udelay(100);
 433 }
 434
 435
 436 #ifdef CONFIG_I2C_PXA_SLAVE
 437 /*
 438  * PXA I2C Slave mode
 439  */
 440
 441 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 442 {
 443         if (isr & ISR_BED) {
 444                 /* what should we do here? */
 445         } else {
 446                 int ret = 0;
 447
 448                 if (i2c->slave != NULL)
 449                         ret = i2c->slave->read(i2c->slave->data);
 450
 451                 writel(ret, _IDBR(i2c));
 452                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 453         }
 454 }
 455
 456 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 457 {
 458         unsigned int byte = readl(_IDBR(i2c));
 459
 460         if (i2c->slave != NULL)
 461                 i2c->slave->write(i2c->slave->data, byte);
 462
 463         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 464 }
 465
 466 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 467 {
 468         int timeout;
 469
 470         if (i2c_debug > 0)
 471                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 472                        (isr & ISR_RWM) ? 'r' : 't');
 473
 474         if (i2c->slave != NULL)
 475                 i2c->slave->event(i2c->slave->data,
 476                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 477
 478         /*
 479          * slave could interrupt in the middle of us generating a
 480          * start condition... if this happens, we'd better back off
 481          * and stop holding the poor thing up
 482          */
 483         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 484         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 485
 486         timeout = 0x10000;
 487
 488         while (1) {
 489                 if ((readl(_IBMR(i2c)) & 2) == 2)
 490                         break;
 491
 492                 timeout--;
 493
 494                 if (timeout <= 0) {
 495                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 496                         break;
 497                 }
 498         }
 499
 500         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 501 }
 502
 503 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 504 {
 505         if (i2c_debug > 2)
 506                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 507
 508         if (i2c->slave != NULL)
 509                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 510
 511         if (i2c_debug > 2)
 512                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 513
 514         /*
 515          * If we have a master-mode message waiting,
 516          * kick it off now that the slave has completed.
 517          */
 518         if (i2c->msg)
 519                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 520 }
 521 #else
 522 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 523 {
 524         if (isr & ISR_BED) {
 525                 /* what should we do here? */
 526         } else {
 527                 writel(0, _IDBR(i2c));
 528                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 529         }
 530 }
 531
 532 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 533 {
 534         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 535 }
 536
 537 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 538 {
 539         int timeout;
 540
 541         /*
 542          * slave could interrupt in the middle of us generating a
 543          * start condition... if this happens, we'd better back off
 544          * and stop holding the poor thing up
 545          */
 546         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 547         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 548
 549         timeout = 0x10000;
 550
 551         while (1) {
 552                 if ((readl(_IBMR(i2c)) & 2) == 2)
 553                         break;
 554
 555                 timeout--;
 556
 557                 if (timeout <= 0) {
 558                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 559                         break;
 560                 }
 561         }
 562
 563         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 564 }
 565
 566 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 567 {
 568         if (i2c->msg)
 569                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 570 }
 571 #endif
 572
 573 /*
 574  * PXA I2C Master mode
 575  */
 576
 577 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 578 {
 579         unsigned int addr = (msg->addr & 0x7f) << 1;
 580
 581         if (msg->flags & I2C_M_RD)
 582                 addr |= 1;
 583
 584         return addr;
 585 }
 586
 587 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 588 {
 589         u32 icr;
 590
 591         /*
 592          * Step 1: target slave address into IDBR
 593          */
 594         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 595
 596         /*
 597          * Step 2: initiate the write.
 598          */
 599         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 600         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 601 }
 602
 603 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 604 {
 605         u32 icr;
 606
 607         /*
 608          * Clear the STOP and ACK flags
 609          */
 610         icr = readl(_ICR(i2c));
 611         icr &= ~(ICR_STOP | ICR_ACKNAK);
 612         writel(icr, _ICR(i2c));
 613 }
 614
 615 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 616 {
 617         /* make timeout the same as for interrupt based functions */
 618         long timeout = 2 * DEF_TIMEOUT;
 619
 620         /*
 621          * Wait for the bus to become free.
 622          */
 623         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 624                 udelay(1000);
 625                 show_state(i2c);
 626         }
 627
 628         if (timeout < 0) {
 629                 show_state(i2c);
 630                 dev_err(&i2c->adap.dev,
 631                         "i2c_pxa: timeout waiting for bus free\n");
 632                 return I2C_RETRY;
 633         }
 634
 635         /*
 636          * Set master mode.
 637          */
 638         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 639
 640         return 0;
 641 }
 642
 643 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 644                                struct i2c_msg *msg, int num)
 645 {
 646         unsigned long timeout = 500000; /* 5 seconds */
 647         int ret = 0;
 648
 649         ret = i2c_pxa_pio_set_master(i2c);
 650         if (ret)
 651                 goto out;
 652
 653         i2c->msg = msg;
 654         i2c->msg_num = num;
 655         i2c->msg_idx = 0;
 656         i2c->msg_ptr = 0;
 657         i2c->irqlogidx = 0;
 658
 659         i2c_pxa_start_message(i2c);
 660
 661         while (i2c->msg_num > 0 && --timeout) {
 662                 i2c_pxa_handler(0, i2c);
 663                 udelay(10);
 664         }
 665
 666         i2c_pxa_stop_message(i2c);
 667
 668         /*
 669          * We place the return code in i2c->msg_idx.
 670          */
 671         ret = i2c->msg_idx;
 672
 673 out:
 674         if (timeout == 0)
 675                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 676
 677         return ret;
 678 }
 679
 680 /*
 681  * We are protected by the adapter bus mutex.
 682  */
 683 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 684 {
 685         long timeout;
 686         int ret;
 687
 688         /*
 689          * Wait for the bus to become free.
 690          */
 691         ret = i2c_pxa_wait_bus_not_busy(i2c);
 692         if (ret) {
 693                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 694                 goto out;
 695         }
 696
 697         /*
 698          * Set master mode.
 699          */
 700         ret = i2c_pxa_set_master(i2c);
 701         if (ret) {
 702                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 703                 goto out;
 704         }
 705
 706         spin_lock_irq(&i2c->lock);
 707
 708         i2c->msg = msg;
 709         i2c->msg_num = num;
 710         i2c->msg_idx = 0;
 711         i2c->msg_ptr = 0;
 712         i2c->irqlogidx = 0;
 713
 714         i2c_pxa_start_message(i2c);
 715
 716         spin_unlock_irq(&i2c->lock);
 717
 718         /*
 719          * The rest of the processing occurs in the interrupt handler.
 720          */
 721         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 722         i2c_pxa_stop_message(i2c);
 723
 724         /*
 725          * We place the return code in i2c->msg_idx.
 726          */
 727         ret = i2c->msg_idx;
 728
 729         if (timeout == 0)
 730                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 731
 732  out:
 733         return ret;
 734 }
 735
 736 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 737                             struct i2c_msg msgs[], int num)
 738 {
 739         struct pxa_i2c *i2c = adap->algo_data;
 740         int ret, i;
 741
 742         /* If the I2C controller is disabled we need to reset it
 743           (probably due to a suspend/resume destroying state). We do
 744           this here as we can then avoid worrying about resuming the
 745           controller before its users. */
 746         if (!(readl(_ICR(i2c)) & ICR_IUE))
 747                 i2c_pxa_reset(i2c);
 748
 749         for (i = adap->retries; i >= 0; i--) {
 750                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 751                 if (ret != I2C_RETRY)
 752                         goto out;
 753
 754                 if (i2c_debug)
 755                         dev_dbg(&adap->dev, "Retrying transmission\n");
 756                 udelay(100);
 757         }
 758         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 759         ret = -EREMOTEIO;
 760  out:
 761         i2c_pxa_set_slave(i2c, ret);
 762         return ret;
 763 }
 764
 765 /*
 766  * i2c_pxa_master_complete - complete the message and wake up.
 767  */
 768 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 769 {
 770         i2c->msg_ptr = 0;
 771         i2c->msg = NULL;
 772         i2c->msg_idx ++;
 773         i2c->msg_num = 0;
 774         if (ret)
 775                 i2c->msg_idx = ret;
 776         if (!i2c->use_pio)
 777                 wake_up(&i2c->wait);
 778 }
 779
 780 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 781 {
 782         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 783
 784  again:
 785         /*
 786          * If ISR_ALD is set, we lost arbitration.
 787          */
 788         if (isr & ISR_ALD) {
 789                 /*
 790                  * Do we need to do anything here?  The PXA docs
 791                  * are vague about what happens.
 792                  */
 793                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 794
 795                 /*
 796                  * We ignore this error.  We seem to see spurious ALDs
 797                  * for seemingly no reason.  If we handle them as I think
 798                  * they should, we end up causing an I2C error, which
 799                  * is painful for some systems.
 800                  */
 801                 return; /* ignore */
 802         }
 803
 804         if (isr & ISR_BED) {
 805                 int ret = BUS_ERROR;
 806
 807                 /*
 808                  * I2C bus error - either the device NAK'd us, or
 809                  * something more serious happened.  If we were NAK'd
 810                  * on the initial address phase, we can retry.
 811                  */
 812                 if (isr & ISR_ACKNAK) {
 813                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 814                                 ret = I2C_RETRY;
 815                         else
 816                                 ret = XFER_NAKED;
 817                 }
 818                 i2c_pxa_master_complete(i2c, ret);
 819         } else if (isr & ISR_RWM) {
 820                 /*
 821                  * Read mode.  We have just sent the address byte, and
 822                  * now we must initiate the transfer.
 823                  */
 824                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 825                     i2c->msg_idx == i2c->msg_num - 1)
 826                         icr |= ICR_STOP | ICR_ACKNAK;
 827
 828                 icr |= ICR_ALDIE | ICR_TB;
 829         } else if (i2c->msg_ptr < i2c->msg->len) {
 830                 /*
 831                  * Write mode.  Write the next data byte.
 832                  */
 833                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 834
 835                 icr |= ICR_ALDIE | ICR_TB;
 836
 837                 /*
 838                  * If this is the last byte of the last message, send
 839                  * a STOP.
 840                  */
 841                 if (i2c->msg_ptr == i2c->msg->len &&
 842                     i2c->msg_idx == i2c->msg_num - 1)
 843                         icr |= ICR_STOP;
 844         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 845                 /*
 846                  * Next segment of the message.
 847                  */
 848                 i2c->msg_ptr = 0;
 849                 i2c->msg_idx ++;
 850                 i2c->msg++;
 851
 852                 /*
 853                  * If we aren't doing a repeated start and address,
 854                  * go back and try to send the next byte.  Note that
 855                  * we do not support switching the R/W direction here.
 856                  */
 857                 if (i2c->msg->flags & I2C_M_NOSTART)
 858                         goto again;
 859
 860                 /*
 861                  * Write the next address.
 862                  */
 863                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 864
 865                 /*
 866                  * And trigger a repeated start, and send the byte.
 867                  */
 868                 icr &= ~ICR_ALDIE;
 869                 icr |= ICR_START | ICR_TB;
 870         } else {
 871                 if (i2c->msg->len == 0) {
 872                         /*
 873                          * Device probes have a message length of zero
 874                          * and need the bus to be reset before it can
 875                          * be used again.
 876                          */
 877                         i2c_pxa_reset(i2c);
 878                 }
 879                 i2c_pxa_master_complete(i2c, 0);
 880         }
 881
 882         i2c->icrlog[i2c->irqlogidx-1] = icr;
 883
 884         writel(icr, _ICR(i2c));
 885         show_state(i2c);
 886 }
 887
 888 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 889 {
 890         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 891
 892         /*
 893          * Read the byte.
 894          */
 895         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 896
 897         if (i2c->msg_ptr < i2c->msg->len) {
 898                 /*
 899                  * If this is the last byte of the last
 900                  * message, send a STOP.
 901                  */
 902                 if (i2c->msg_ptr == i2c->msg->len - 1)
 903                         icr |= ICR_STOP | ICR_ACKNAK;
 904
 905                 icr |= ICR_ALDIE | ICR_TB;
 906         } else {
 907                 i2c_pxa_master_complete(i2c, 0);
 908         }
 909
 910         i2c->icrlog[i2c->irqlogidx-1] = icr;
 911
 912         writel(icr, _ICR(i2c));
 913 }
 914
 915 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 916 {
 917         struct pxa_i2c *i2c = dev_id;
 918         u32 isr = readl(_ISR(i2c));
 919
 920         if (i2c_debug > 2 && 0) {
 921                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 922                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
 923                 decode_ISR(isr);
 924         }
 925
 926         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
 927                 i2c->isrlog[i2c->irqlogidx++] = isr;
 928
 929         show_state(i2c);
 930
 931         /*
 932          * Always clear all pending IRQs.
 933          */
 934         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
 935
 936         if (isr & ISR_SAD)
 937                 i2c_pxa_slave_start(i2c, isr);
 938         if (isr & ISR_SSD)
 939                 i2c_pxa_slave_stop(i2c);
 940
 941         if (i2c_pxa_is_slavemode(i2c)) {
 942                 if (isr & ISR_ITE)
 943                         i2c_pxa_slave_txempty(i2c, isr);
 944                 if (isr & ISR_IRF)
 945                         i2c_pxa_slave_rxfull(i2c, isr);
 946         } else if (i2c->msg) {
 947                 if (isr & ISR_ITE)
 948                         i2c_pxa_irq_txempty(i2c, isr);
 949                 if (isr & ISR_IRF)
 950                         i2c_pxa_irq_rxfull(i2c, isr);
 951         } else {
 952                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
 953         }
 954
 955         return IRQ_HANDLED;
 956 }
 957
 958
 959 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 960 {
 961         struct pxa_i2c *i2c = adap->algo_data;
 962         int ret, i;
 963
 964         for (i = adap->retries; i >= 0; i--) {
 965                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
 966                 if (ret != I2C_RETRY)
 967                         goto out;
 968
 969                 if (i2c_debug)
 970                         dev_dbg(&adap->dev, "Retrying transmission\n");
 971                 udelay(100);
 972         }
 973         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 974         ret = -EREMOTEIO;
 975  out:
 976         i2c_pxa_set_slave(i2c, ret);
 977         return ret;
 978 }
 979
 980 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
 981 {
 982         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 983 }
 984
 985 static const struct i2c_algorithm i2c_pxa_algorithm = {
 986         .master_xfer    = i2c_pxa_xfer,
 987         .functionality  = i2c_pxa_functionality,
 988 };
 989
 990 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
 991         .master_xfer    = i2c_pxa_pio_xfer,
 992         .functionality  = i2c_pxa_functionality,
 993 };
 994
 995 static int i2c_pxa_probe(struct platform_device *dev)
 996 {
 997         struct pxa_i2c *i2c;
 998         struct resource *res;
 999         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1000         struct platform_device_id *id = platform_get_device_id(dev);
1001         int ret;
1002         int irq;
1003
1004         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1005         irq = platform_get_irq(dev, 0);
1006         if (res == NULL || irq < 0)
1007                 return -ENODEV;
1008
1009         if (!request_mem_region(res->start, resource_size(res), res->name))
1010                 return -ENOMEM;
1011
1012         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1013         if (!i2c) {
1014                 ret = -ENOMEM;
1015                 goto emalloc;
1016         }
1017
1018         i2c->adap.owner   = THIS_MODULE;
1019         i2c->adap.retries = 5;
1020
1021         spin_lock_init(&i2c->lock);
1022         init_waitqueue_head(&i2c->wait);
1023
1024         /*
1025          * If "dev->id" is negative we consider it as zero.
1026          * The reason to do so is to avoid sysfs names that only make
1027          * sense when there are multiple adapters.
1028          */
1029         i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1030         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1031                  i2c->adap.nr);
1032
1033         i2c->clk = clk_get(&dev->dev, NULL);
1034         if (IS_ERR(i2c->clk)) {
1035                 ret = PTR_ERR(i2c->clk);
1036                 goto eclk;
1037         }
1038
1039         i2c->reg_base = ioremap(res->start, resource_size(res));
1040         if (!i2c->reg_base) {
1041                 ret = -EIO;
1042                 goto eremap;
1043         }
1044         i2c->reg_shift = REG_SHIFT(id->driver_data);
1045
1046         i2c->iobase = res->start;
1047         i2c->iosize = resource_size(res);
1048
1049         i2c->irq = irq;
1050
1051         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1052
1053 #ifdef CONFIG_I2C_PXA_SLAVE
1054         if (plat) {
1055                 i2c->slave_addr = plat->slave_addr;
1056                 i2c->slave = plat->slave;
1057         }
1058 #endif
1059
1060         clk_enable(i2c->clk);
1061
1062         if (plat) {
1063                 i2c->adap.class = plat->class;
1064                 i2c->use_pio = plat->use_pio;
1065                 i2c->fast_mode = plat->fast_mode;
1066         }
1067
1068         if (i2c->use_pio) {
1069                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1070         } else {
1071                 i2c->adap.algo = &i2c_pxa_algorithm;
1072                 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1073                                   i2c->adap.name, i2c);
1074                 if (ret)
1075                         goto ereqirq;
1076         }
1077
1078         i2c_pxa_reset(i2c);
1079
1080         i2c->adap.algo_data = i2c;
1081         i2c->adap.dev.parent = &dev->dev;
1082
1083         ret = i2c_add_numbered_adapter(&i2c->adap);
1084         if (ret < 0) {
1085                 printk(KERN_INFO "I2C: Failed to add bus\n");
1086                 goto eadapt;
1087         }
1088
1089         platform_set_drvdata(dev, i2c);
1090
1091 #ifdef CONFIG_I2C_PXA_SLAVE
1092         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1093                dev_name(&i2c->adap.dev), i2c->slave_addr);
1094 #else
1095         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1096                dev_name(&i2c->adap.dev));
1097 #endif
1098         return 0;
1099
1100 eadapt:
1101         if (!i2c->use_pio)
1102                 free_irq(irq, i2c);
1103 ereqirq:
1104         clk_disable(i2c->clk);
1105         iounmap(i2c->reg_base);
1106 eremap:
1107         clk_put(i2c->clk);
1108 eclk:
1109         kfree(i2c);
1110 emalloc:
1111         release_mem_region(res->start, resource_size(res));
1112         return ret;
1113 }
1114
1115 static int __exit i2c_pxa_remove(struct platform_device *dev)
1116 {
1117         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1118
1119         platform_set_drvdata(dev, NULL);
1120
1121         i2c_del_adapter(&i2c->adap);
1122         if (!i2c->use_pio)
1123                 free_irq(i2c->irq, i2c);
1124
1125         clk_disable(i2c->clk);
1126         clk_put(i2c->clk);
1127
1128         iounmap(i2c->reg_base);
1129         release_mem_region(i2c->iobase, i2c->iosize);
1130         kfree(i2c);
1131
1132         return 0;
1133 }
1134
1135 #ifdef CONFIG_PM
1136 static int i2c_pxa_suspend_noirq(struct device *dev)
1137 {
1138         struct platform_device *pdev = to_platform_device(dev);
1139         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1140
1141         clk_disable(i2c->clk);
1142
1143         return 0;
1144 }
1145
1146 static int i2c_pxa_resume_noirq(struct device *dev)
1147 {
1148         struct platform_device *pdev = to_platform_device(dev);
1149         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1150
1151         clk_enable(i2c->clk);
1152         i2c_pxa_reset(i2c);
1153
1154         return 0;
1155 }
1156
1157 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1158         .suspend_noirq = i2c_pxa_suspend_noirq,
1159         .resume_noirq = i2c_pxa_resume_noirq,
1160 };
1161
1162 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1163 #else
1164 #define I2C_PXA_DEV_PM_OPS NULL
1165 #endif
1166
1167 static struct platform_driver i2c_pxa_driver = {
1168         .probe          = i2c_pxa_probe,
1169         .remove         = __exit_p(i2c_pxa_remove),
1170         .driver         = {
1171                 .name   = "pxa2xx-i2c",
1172                 .owner  = THIS_MODULE,
1173                 .pm     = I2C_PXA_DEV_PM_OPS,
1174         },
1175         .id_table       = i2c_pxa_id_table,
1176 };
1177
1178 static int __init i2c_adap_pxa_init(void)
1179 {
1180         return platform_driver_register(&i2c_pxa_driver);
1181 }
1182
1183 static void __exit i2c_adap_pxa_exit(void)
1184 {
1185         platform_driver_unregister(&i2c_pxa_driver);
1186 }
1187
1188 MODULE_LICENSE("GPL");
1189 MODULE_ALIAS("platform:pxa2xx-i2c");
1190
1191 subsys_initcall(i2c_adap_pxa_init);
1192 module_exit(i2c_adap_pxa_exit);