drivers/gpu/drm/radeon/rs600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 /* RS600 / Radeon X1250/X1270 integrated GPU
  29  *
  30  * This file gather function specific to RS600 which is the IGP of
  31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33  * the avivo one, bios is an atombios, 3D block are the one of the
  34  * R4XX family. The GART is different from the RS400 one and is very
  35  * close to the one of the R600 family (R600 likely being an evolution
  36  * of the RS600 GART block).
  37  */
  38 #include "drmP.h"
  39 #include "radeon.h"
  40 #include "atom.h"
  41 #include "rs600d.h"
  42
  43 #include "rs600_reg_safe.h"
  44
  45 void rs600_gpu_init(struct radeon_device *rdev);
  46 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  47
  48 int rs600_mc_init(struct radeon_device *rdev)
  49 {
  50         /* read back the MC value from the hw */
  51         int r;
  52         u32 tmp;
  53
  54         /* Setup GPU memory space */
  55         tmp = RREG32_MC(R_000004_MC_FB_LOCATION);
  56         rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
  57         rdev->mc.gtt_location = 0xffffffffUL;
  58         r = radeon_mc_setup(rdev);
  59         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
  60         if (r)
  61                 return r;
  62         return 0;
  63 }
  64
  65 /* hpd for digital panel detect/disconnect */
  66 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  67 {
  68         u32 tmp;
  69         bool connected = false;
  70
  71         switch (hpd) {
  72         case RADEON_HPD_1:
  73                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
  74                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
  75                         connected = true;
  76                 break;
  77         case RADEON_HPD_2:
  78                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
  79                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
  80                         connected = true;
  81                 break;
  82         default:
  83                 break;
  84         }
  85         return connected;
  86 }
  87
  88 void rs600_hpd_set_polarity(struct radeon_device *rdev,
  89                             enum radeon_hpd_id hpd)
  90 {
  91         u32 tmp;
  92         bool connected = rs600_hpd_sense(rdev, hpd);
  93
  94         switch (hpd) {
  95         case RADEON_HPD_1:
  96                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  97                 if (connected)
  98                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  99                 else
 100                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
 101                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 102                 break;
 103         case RADEON_HPD_2:
 104                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 105                 if (connected)
 106                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 107                 else
 108                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
 109                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 110                 break;
 111         default:
 112                 break;
 113         }
 114 }
 115
 116 void rs600_hpd_init(struct radeon_device *rdev)
 117 {
 118         struct drm_device *dev = rdev->ddev;
 119         struct drm_connector *connector;
 120
 121         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 122                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 123                 switch (radeon_connector->hpd.hpd) {
 124                 case RADEON_HPD_1:
 125                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 126                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
 127                         rdev->irq.hpd[0] = true;
 128                         break;
 129                 case RADEON_HPD_2:
 130                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 131                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
 132                         rdev->irq.hpd[1] = true;
 133                         break;
 134                 default:
 135                         break;
 136                 }
 137         }
 138         rs600_irq_set(rdev);
 139 }
 140
 141 void rs600_hpd_fini(struct radeon_device *rdev)
 142 {
 143         struct drm_device *dev = rdev->ddev;
 144         struct drm_connector *connector;
 145
 146         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 147                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 148                 switch (radeon_connector->hpd.hpd) {
 149                 case RADEON_HPD_1:
 150                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
 151                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
 152                         rdev->irq.hpd[0] = false;
 153                         break;
 154                 case RADEON_HPD_2:
 155                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
 156                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
 157                         rdev->irq.hpd[1] = false;
 158                         break;
 159                 default:
 160                         break;
 161                 }
 162         }
 163 }
 164
 165 /*
 166  * GART.
 167  */
 168 void rs600_gart_tlb_flush(struct radeon_device *rdev)
 169 {
 170         uint32_t tmp;
 171
 172         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 173         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 174         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 175
 176         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 177         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
 178         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 179
 180         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 181         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
 182         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 183         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 184 }
 185
 186 int rs600_gart_init(struct radeon_device *rdev)
 187 {
 188         int r;
 189
 190         if (rdev->gart.table.vram.robj) {
 191                 WARN(1, "RS600 GART already initialized.\n");
 192                 return 0;
 193         }
 194         /* Initialize common gart structure */
 195         r = radeon_gart_init(rdev);
 196         if (r) {
 197                 return r;
 198         }
 199         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 200         return radeon_gart_table_vram_alloc(rdev);
 201 }
 202
 203 int rs600_gart_enable(struct radeon_device *rdev)
 204 {
 205         u32 tmp;
 206         int r, i;
 207
 208         if (rdev->gart.table.vram.robj == NULL) {
 209                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 210                 return -EINVAL;
 211         }
 212         r = radeon_gart_table_vram_pin(rdev);
 213         if (r)
 214                 return r;
 215         /* Enable bus master */
 216         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
 217         WREG32(R_00004C_BUS_CNTL, tmp);
 218         /* FIXME: setup default page */
 219         WREG32_MC(R_000100_MC_PT0_CNTL,
 220                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
 221                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
 222
 223         for (i = 0; i < 19; i++) {
 224                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
 225                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
 226                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
 227                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
 228                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
 229                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
 230                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
 231                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
 232                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
 233         }
 234         /* enable first context */
 235         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
 236                   S_000102_ENABLE_PAGE_TABLE(1) |
 237                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
 238
 239         /* disable all other contexts */
 240         for (i = 1; i < 8; i++)
 241                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
 242
 243         /* setup the page table */
 244         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 245                   rdev->gart.table_addr);
 246         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
 247         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
 248         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 249
 250         /* System context maps to VRAM space */
 251         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
 252         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
 253
 254         /* enable page tables */
 255         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 256         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
 257         tmp = RREG32_MC(R_000009_MC_CNTL1);
 258         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
 259         rs600_gart_tlb_flush(rdev);
 260         rdev->gart.ready = true;
 261         return 0;
 262 }
 263
 264 void rs600_gart_disable(struct radeon_device *rdev)
 265 {
 266         u32 tmp;
 267         int r;
 268
 269         /* FIXME: disable out of gart access */
 270         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
 271         tmp = RREG32_MC(R_000009_MC_CNTL1);
 272         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
 273         if (rdev->gart.table.vram.robj) {
 274                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 275                 if (r == 0) {
 276                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 277                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 278                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 279                 }
 280         }
 281 }
 282
 283 void rs600_gart_fini(struct radeon_device *rdev)
 284 {
 285         rs600_gart_disable(rdev);
 286         radeon_gart_table_vram_free(rdev);
 287         radeon_gart_fini(rdev);
 288 }
 289
 290 #define R600_PTE_VALID     (1 << 0)
 291 #define R600_PTE_SYSTEM    (1 << 1)
 292 #define R600_PTE_SNOOPED   (1 << 2)
 293 #define R600_PTE_READABLE  (1 << 5)
 294 #define R600_PTE_WRITEABLE (1 << 6)
 295
 296 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 297 {
 298         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 299
 300         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 301                 return -EINVAL;
 302         }
 303         addr = addr & 0xFFFFFFFFFFFFF000ULL;
 304         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 305         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 306         writeq(addr, ((void __iomem *)ptr) + (i * 8));
 307         return 0;
 308 }
 309
 310 int rs600_irq_set(struct radeon_device *rdev)
 311 {
 312         uint32_t tmp = 0;
 313         uint32_t mode_int = 0;
 314         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
 315                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 316         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
 317                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 318
 319         if (rdev->irq.sw_int) {
 320                 tmp |= S_000040_SW_INT_EN(1);
 321         }
 322         if (rdev->irq.crtc_vblank_int[0]) {
 323                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
 324         }
 325         if (rdev->irq.crtc_vblank_int[1]) {
 326                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
 327         }
 328         if (rdev->irq.hpd[0]) {
 329                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
 330         }
 331         if (rdev->irq.hpd[1]) {
 332                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 333         }
 334         WREG32(R_000040_GEN_INT_CNTL, tmp);
 335         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
 336         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
 337         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
 338         return 0;
 339 }
 340
 341 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
 342 {
 343         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
 344         uint32_t irq_mask = ~C_000044_SW_INT;
 345         u32 tmp;
 346
 347         if (G_000044_DISPLAY_INT_STAT(irqs)) {
 348                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
 349                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
 350                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
 351                                 S_006534_D1MODE_VBLANK_ACK(1));
 352                 }
 353                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
 354                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
 355                                 S_006D34_D2MODE_VBLANK_ACK(1));
 356                 }
 357                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
 358                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
 359                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
 360                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 361                 }
 362                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
 363                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
 364                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
 365                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 366                 }
 367         } else {
 368                 *r500_disp_int = 0;
 369         }
 370
 371         if (irqs) {
 372                 WREG32(R_000044_GEN_INT_STATUS, irqs);
 373         }
 374         return irqs & irq_mask;
 375 }
 376
 377 void rs600_irq_disable(struct radeon_device *rdev)
 378 {
 379         u32 tmp;
 380
 381         WREG32(R_000040_GEN_INT_CNTL, 0);
 382         WREG32(R_006540_DxMODE_INT_MASK, 0);
 383         /* Wait and acknowledge irq */
 384         mdelay(1);
 385         rs600_irq_ack(rdev, &tmp);
 386 }
 387
 388 int rs600_irq_process(struct radeon_device *rdev)
 389 {
 390         uint32_t status, msi_rearm;
 391         uint32_t r500_disp_int;
 392         bool queue_hotplug = false;
 393
 394         status = rs600_irq_ack(rdev, &r500_disp_int);
 395         if (!status && !r500_disp_int) {
 396                 return IRQ_NONE;
 397         }
 398         while (status || r500_disp_int) {
 399                 /* SW interrupt */
 400                 if (G_000044_SW_INT(status))
 401                         radeon_fence_process(rdev);
 402                 /* Vertical blank interrupts */
 403                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
 404                         drm_handle_vblank(rdev->ddev, 0);
 405                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
 406                         drm_handle_vblank(rdev->ddev, 1);
 407                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
 408                         queue_hotplug = true;
 409                         DRM_DEBUG("HPD1\n");
 410                 }
 411                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
 412                         queue_hotplug = true;
 413                         DRM_DEBUG("HPD2\n");
 414                 }
 415                 status = rs600_irq_ack(rdev, &r500_disp_int);
 416         }
 417         if (queue_hotplug)
 418                 queue_work(rdev->wq, &rdev->hotplug_work);
 419         if (rdev->msi_enabled) {
 420                 switch (rdev->family) {
 421                 case CHIP_RS600:
 422                 case CHIP_RS690:
 423                 case CHIP_RS740:
 424                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
 425                         WREG32(RADEON_BUS_CNTL, msi_rearm);
 426                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
 427                         break;
 428                 default:
 429                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 430                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 431                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 432                         break;
 433                 }
 434         }
 435         return IRQ_HANDLED;
 436 }
 437
 438 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 439 {
 440         if (crtc == 0)
 441                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
 442         else
 443                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 444 }
 445
 446 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 447 {
 448         unsigned i;
 449
 450         for (i = 0; i < rdev->usec_timeout; i++) {
 451                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
 452                         return 0;
 453                 udelay(1);
 454         }
 455         return -1;
 456 }
 457
 458 void rs600_gpu_init(struct radeon_device *rdev)
 459 {
 460         r100_hdp_reset(rdev);
 461         r420_pipes_init(rdev);
 462         /* Wait for mc idle */
 463         if (rs600_mc_wait_for_idle(rdev))
 464                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 465 }
 466
 467 void rs600_vram_info(struct radeon_device *rdev)
 468 {
 469         rdev->mc.vram_is_ddr = true;
 470         rdev->mc.vram_width = 128;
 471
 472         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
 473         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 474
 475         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 476         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 477
 478         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
 479                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 480
 481         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
 482                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 483 }
 484
 485 void rs600_bandwidth_update(struct radeon_device *rdev)
 486 {
 487         /* FIXME: implement, should this be like rs690 ? */
 488 }
 489
 490 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 491 {
 492         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 493                 S_000070_MC_IND_CITF_ARB0(1));
 494         return RREG32(R_000074_MC_IND_DATA);
 495 }
 496
 497 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 498 {
 499         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
 500                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
 501         WREG32(R_000074_MC_IND_DATA, v);
 502 }
 503
 504 void rs600_debugfs(struct radeon_device *rdev)
 505 {
 506         if (r100_debugfs_rbbm_init(rdev))
 507                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 508 }
 509
 510 void rs600_set_safe_registers(struct radeon_device *rdev)
 511 {
 512         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
 513         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
 514 }
 515
 516 static void rs600_mc_program(struct radeon_device *rdev)
 517 {
 518         struct rv515_mc_save save;
 519
 520         /* Stops all mc clients */
 521         rv515_mc_stop(rdev, &save);
 522
 523         /* Wait for mc idle */
 524         if (rs600_mc_wait_for_idle(rdev))
 525                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 526
 527         /* FIXME: What does AGP means for such chipset ? */
 528         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
 529         WREG32_MC(R_000006_AGP_BASE, 0);
 530         WREG32_MC(R_000007_AGP_BASE_2, 0);
 531         /* Program MC */
 532         WREG32_MC(R_000004_MC_FB_LOCATION,
 533                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 534                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 535         WREG32(R_000134_HDP_FB_LOCATION,
 536                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 537
 538         rv515_mc_resume(rdev, &save);
 539 }
 540
 541 static int rs600_startup(struct radeon_device *rdev)
 542 {
 543         int r;
 544
 545         rs600_mc_program(rdev);
 546         /* Resume clock */
 547         rv515_clock_startup(rdev);
 548         /* Initialize GPU configuration (# pipes, ...) */
 549         rs600_gpu_init(rdev);
 550         /* Initialize GART (initialize after TTM so we can allocate
 551          * memory through TTM but finalize after TTM) */
 552         r = rs600_gart_enable(rdev);
 553         if (r)
 554                 return r;
 555         /* Enable IRQ */
 556         rs600_irq_set(rdev);
 557         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 558         /* 1M ring buffer */
 559         r = r100_cp_init(rdev, 1024 * 1024);
 560         if (r) {
 561                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 562                 return r;
 563         }
 564         r = r100_wb_init(rdev);
 565         if (r)
 566                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 567         r = r100_ib_init(rdev);
 568         if (r) {
 569                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 570                 return r;
 571         }
 572         return 0;
 573 }
 574
 575 int rs600_resume(struct radeon_device *rdev)
 576 {
 577         /* Make sur GART are not working */
 578         rs600_gart_disable(rdev);
 579         /* Resume clock before doing reset */
 580         rv515_clock_startup(rdev);
 581         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 582         if (radeon_gpu_reset(rdev)) {
 583                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 584                         RREG32(R_000E40_RBBM_STATUS),
 585                         RREG32(R_0007C0_CP_STAT));
 586         }
 587         /* post */
 588         atom_asic_init(rdev->mode_info.atom_context);
 589         /* Resume clock after posting */
 590         rv515_clock_startup(rdev);
 591         /* Initialize surface registers */
 592         radeon_surface_init(rdev);
 593         return rs600_startup(rdev);
 594 }
 595
 596 int rs600_suspend(struct radeon_device *rdev)
 597 {
 598         r100_cp_disable(rdev);
 599         r100_wb_disable(rdev);
 600         rs600_irq_disable(rdev);
 601         rs600_gart_disable(rdev);
 602         return 0;
 603 }
 604
 605 void rs600_fini(struct radeon_device *rdev)
 606 {
 607         rs600_suspend(rdev);
 608         r100_cp_fini(rdev);
 609         r100_wb_fini(rdev);
 610         r100_ib_fini(rdev);
 611         radeon_gem_fini(rdev);
 612         rs600_gart_fini(rdev);
 613         radeon_irq_kms_fini(rdev);
 614         radeon_fence_driver_fini(rdev);
 615         radeon_bo_fini(rdev);
 616         radeon_atombios_fini(rdev);
 617         kfree(rdev->bios);
 618         rdev->bios = NULL;
 619 }
 620
 621 int rs600_init(struct radeon_device *rdev)
 622 {
 623         int r;
 624
 625         /* Disable VGA */
 626         rv515_vga_render_disable(rdev);
 627         /* Initialize scratch registers */
 628         radeon_scratch_init(rdev);
 629         /* Initialize surface registers */
 630         radeon_surface_init(rdev);
 631         /* BIOS */
 632         if (!radeon_get_bios(rdev)) {
 633                 if (ASIC_IS_AVIVO(rdev))
 634                         return -EINVAL;
 635         }
 636         if (rdev->is_atom_bios) {
 637                 r = radeon_atombios_init(rdev);
 638                 if (r)
 639                         return r;
 640         } else {
 641                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
 642                 return -EINVAL;
 643         }
 644         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 645         if (radeon_gpu_reset(rdev)) {
 646                 dev_warn(rdev->dev,
 647                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 648                         RREG32(R_000E40_RBBM_STATUS),
 649                         RREG32(R_0007C0_CP_STAT));
 650         }
 651         /* check if cards are posted or not */
 652         if (radeon_boot_test_post_card(rdev) == false)
 653                 return -EINVAL;
 654
 655         /* Initialize clocks */
 656         radeon_get_clock_info(rdev->ddev);
 657         /* Initialize power management */
 658         radeon_pm_init(rdev);
 659         /* Get vram informations */
 660         rs600_vram_info(rdev);
 661         /* Initialize memory controller (also test AGP) */
 662         r = rs600_mc_init(rdev);
 663         if (r)
 664                 return r;
 665         rs600_debugfs(rdev);
 666         /* Fence driver */
 667         r = radeon_fence_driver_init(rdev);
 668         if (r)
 669                 return r;
 670         r = radeon_irq_kms_init(rdev);
 671         if (r)
 672                 return r;
 673         /* Memory manager */
 674         r = radeon_bo_init(rdev);
 675         if (r)
 676                 return r;
 677         r = rs600_gart_init(rdev);
 678         if (r)
 679                 return r;
 680         rs600_set_safe_registers(rdev);
 681         rdev->accel_working = true;
 682         r = rs600_startup(rdev);
 683         if (r) {
 684                 /* Somethings want wront with the accel init stop accel */
 685                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 686                 rs600_suspend(rdev);
 687                 r100_cp_fini(rdev);
 688                 r100_wb_fini(rdev);
 689                 r100_ib_fini(rdev);
 690                 rs600_gart_fini(rdev);
 691                 radeon_irq_kms_fini(rdev);
 692                 rdev->accel_working = false;
 693         }
 694         return 0;
 695 }