drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 static int radeon_ddc_dump(struct drm_connector *connector);
  37
  38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  39 {
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         struct drm_device *dev = crtc->dev;
  42         struct radeon_device *rdev = dev->dev_private;
  43         int i;
  44
  45         DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
  46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  47
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  51
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  55
  56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  59
  60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  61         for (i = 0; i < 256; i++) {
  62                 WREG32(AVIVO_DC_LUT_30_COLOR,
  63                              (radeon_crtc->lut_r[i] << 20) |
  64                              (radeon_crtc->lut_g[i] << 10) |
  65                              (radeon_crtc->lut_b[i] << 0));
  66         }
  67
  68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  69 }
  70
  71 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  74         struct drm_device *dev = crtc->dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76         int i;
  77         uint32_t dac2_cntl;
  78
  79         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
  80         if (radeon_crtc->crtc_id == 0)
  81                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
  82         else
  83                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
  84         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  85
  86         WREG8(RADEON_PALETTE_INDEX, 0);
  87         for (i = 0; i < 256; i++) {
  88                 WREG32(RADEON_PALETTE_30_DATA,
  89                              (radeon_crtc->lut_r[i] << 20) |
  90                              (radeon_crtc->lut_g[i] << 10) |
  91                              (radeon_crtc->lut_b[i] << 0));
  92         }
  93 }
  94
  95 void radeon_crtc_load_lut(struct drm_crtc *crtc)
  96 {
  97         struct drm_device *dev = crtc->dev;
  98         struct radeon_device *rdev = dev->dev_private;
  99
 100         if (!crtc->enabled)
 101                 return;
 102
 103         if (ASIC_IS_AVIVO(rdev))
 104                 avivo_crtc_load_lut(crtc);
 105         else
 106                 legacy_crtc_load_lut(crtc);
 107 }
 108
 109 /** Sets the color ramps on behalf of fbcon */
 110 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 111                               u16 blue, int regno)
 112 {
 113         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 114
 115         radeon_crtc->lut_r[regno] = red >> 6;
 116         radeon_crtc->lut_g[regno] = green >> 6;
 117         radeon_crtc->lut_b[regno] = blue >> 6;
 118 }
 119
 120 /** Gets the color ramps on behalf of fbcon */
 121 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 122                               u16 *blue, int regno)
 123 {
 124         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 125
 126         *red = radeon_crtc->lut_r[regno] << 6;
 127         *green = radeon_crtc->lut_g[regno] << 6;
 128         *blue = radeon_crtc->lut_b[regno] << 6;
 129 }
 130
 131 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 132                                   u16 *blue, uint32_t size)
 133 {
 134         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 135         int i;
 136
 137         if (size != 256) {
 138                 return;
 139         }
 140
 141         /* userspace palettes are always correct as is */
 142         for (i = 0; i < 256; i++) {
 143                 radeon_crtc->lut_r[i] = red[i] >> 6;
 144                 radeon_crtc->lut_g[i] = green[i] >> 6;
 145                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 146         }
 147         radeon_crtc_load_lut(crtc);
 148 }
 149
 150 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 151 {
 152         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 153
 154         drm_crtc_cleanup(crtc);
 155         kfree(radeon_crtc);
 156 }
 157
 158 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 159         .cursor_set = radeon_crtc_cursor_set,
 160         .cursor_move = radeon_crtc_cursor_move,
 161         .gamma_set = radeon_crtc_gamma_set,
 162         .set_config = drm_crtc_helper_set_config,
 163         .destroy = radeon_crtc_destroy,
 164 };
 165
 166 static void radeon_crtc_init(struct drm_device *dev, int index)
 167 {
 168         struct radeon_device *rdev = dev->dev_private;
 169         struct radeon_crtc *radeon_crtc;
 170         int i;
 171
 172         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 173         if (radeon_crtc == NULL)
 174                 return;
 175
 176         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 177
 178         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 179         radeon_crtc->crtc_id = index;
 180         rdev->mode_info.crtcs[index] = radeon_crtc;
 181
 182 #if 0
 183         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 184         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 185         radeon_crtc->mode_set.num_connectors = 0;
 186 #endif
 187
 188         for (i = 0; i < 256; i++) {
 189                 radeon_crtc->lut_r[i] = i << 2;
 190                 radeon_crtc->lut_g[i] = i << 2;
 191                 radeon_crtc->lut_b[i] = i << 2;
 192         }
 193
 194         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 195                 radeon_atombios_init_crtc(dev, radeon_crtc);
 196         else
 197                 radeon_legacy_init_crtc(dev, radeon_crtc);
 198 }
 199
 200 static const char *encoder_names[34] = {
 201         "NONE",
 202         "INTERNAL_LVDS",
 203         "INTERNAL_TMDS1",
 204         "INTERNAL_TMDS2",
 205         "INTERNAL_DAC1",
 206         "INTERNAL_DAC2",
 207         "INTERNAL_SDVOA",
 208         "INTERNAL_SDVOB",
 209         "SI170B",
 210         "CH7303",
 211         "CH7301",
 212         "INTERNAL_DVO1",
 213         "EXTERNAL_SDVOA",
 214         "EXTERNAL_SDVOB",
 215         "TITFP513",
 216         "INTERNAL_LVTM1",
 217         "VT1623",
 218         "HDMI_SI1930",
 219         "HDMI_INTERNAL",
 220         "INTERNAL_KLDSCP_TMDS1",
 221         "INTERNAL_KLDSCP_DVO1",
 222         "INTERNAL_KLDSCP_DAC1",
 223         "INTERNAL_KLDSCP_DAC2",
 224         "SI178",
 225         "MVPU_FPGA",
 226         "INTERNAL_DDI",
 227         "VT1625",
 228         "HDMI_SI1932",
 229         "DP_AN9801",
 230         "DP_DP501",
 231         "INTERNAL_UNIPHY",
 232         "INTERNAL_KLDSCP_LVTMA",
 233         "INTERNAL_UNIPHY1",
 234         "INTERNAL_UNIPHY2",
 235 };
 236
 237 static const char *connector_names[15] = {
 238         "Unknown",
 239         "VGA",
 240         "DVI-I",
 241         "DVI-D",
 242         "DVI-A",
 243         "Composite",
 244         "S-video",
 245         "LVDS",
 246         "Component",
 247         "DIN",
 248         "DisplayPort",
 249         "HDMI-A",
 250         "HDMI-B",
 251         "TV",
 252         "eDP",
 253 };
 254
 255 static const char *hpd_names[7] = {
 256         "NONE",
 257         "HPD1",
 258         "HPD2",
 259         "HPD3",
 260         "HPD4",
 261         "HPD5",
 262         "HPD6",
 263 };
 264
 265 static void radeon_print_display_setup(struct drm_device *dev)
 266 {
 267         struct drm_connector *connector;
 268         struct radeon_connector *radeon_connector;
 269         struct drm_encoder *encoder;
 270         struct radeon_encoder *radeon_encoder;
 271         uint32_t devices;
 272         int i = 0;
 273
 274         DRM_INFO("Radeon Display Connectors\n");
 275         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 276                 radeon_connector = to_radeon_connector(connector);
 277                 DRM_INFO("Connector %d:\n", i);
 278                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 279                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 280                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 281                 if (radeon_connector->ddc_bus) {
 282                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 283                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 284                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 285                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 286                                  radeon_connector->ddc_bus->rec.a_data_reg,
 287                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 288                                  radeon_connector->ddc_bus->rec.en_data_reg,
 289                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 290                                  radeon_connector->ddc_bus->rec.y_data_reg);
 291                 } else {
 292                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 293                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 294                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 295                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 296                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 297                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 298                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 299                 }
 300                 DRM_INFO("  Encoders:\n");
 301                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 302                         radeon_encoder = to_radeon_encoder(encoder);
 303                         devices = radeon_encoder->devices & radeon_connector->devices;
 304                         if (devices) {
 305                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 306                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 307                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 308                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 309                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 310                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 311                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 312                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 313                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 314                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 315                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 316                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 317                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 318                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 319                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 320                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 321                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 322                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 323                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 324                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 325                         }
 326                 }
 327                 i++;
 328         }
 329 }
 330
 331 static bool radeon_setup_enc_conn(struct drm_device *dev)
 332 {
 333         struct radeon_device *rdev = dev->dev_private;
 334         struct drm_connector *drm_connector;
 335         bool ret = false;
 336
 337         if (rdev->bios) {
 338                 if (rdev->is_atom_bios) {
 339                         if (rdev->family >= CHIP_R600)
 340                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 341                         else
 342                                 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 343                 } else {
 344                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 345                         if (ret == false)
 346                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 347                 }
 348         } else {
 349                 if (!ASIC_IS_AVIVO(rdev))
 350                         ret = radeon_get_legacy_connector_info_from_table(dev);
 351         }
 352         if (ret) {
 353                 radeon_setup_encoder_clones(dev);
 354                 radeon_print_display_setup(dev);
 355                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
 356                         radeon_ddc_dump(drm_connector);
 357         }
 358
 359         return ret;
 360 }
 361
 362 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 363 {
 364         int ret = 0;
 365
 366         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 367             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 368                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 369                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 370                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 371                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
 372         }
 373         if (!radeon_connector->ddc_bus)
 374                 return -1;
 375         if (!radeon_connector->edid) {
 376                 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
 377                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 378                 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
 379         }
 380
 381         if (radeon_connector->edid) {
 382                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 383                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 384                 return ret;
 385         }
 386         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 387         return 0;
 388 }
 389
 390 static int radeon_ddc_dump(struct drm_connector *connector)
 391 {
 392         struct edid *edid;
 393         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 394         int ret = 0;
 395
 396         if (!radeon_connector->ddc_bus)
 397                 return -1;
 398         radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
 399         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 400         radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
 401         if (edid) {
 402                 kfree(edid);
 403         }
 404         return ret;
 405 }
 406
 407 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 408 {
 409         uint64_t mod;
 410
 411         n += d / 2;
 412
 413         mod = do_div(n, d);
 414         return n;
 415 }
 416
 417 void radeon_compute_pll(struct radeon_pll *pll,
 418                         uint64_t freq,
 419                         uint32_t *dot_clock_p,
 420                         uint32_t *fb_div_p,
 421                         uint32_t *frac_fb_div_p,
 422                         uint32_t *ref_div_p,
 423                         uint32_t *post_div_p)
 424 {
 425         uint32_t min_ref_div = pll->min_ref_div;
 426         uint32_t max_ref_div = pll->max_ref_div;
 427         uint32_t min_post_div = pll->min_post_div;
 428         uint32_t max_post_div = pll->max_post_div;
 429         uint32_t min_fractional_feed_div = 0;
 430         uint32_t max_fractional_feed_div = 0;
 431         uint32_t best_vco = pll->best_vco;
 432         uint32_t best_post_div = 1;
 433         uint32_t best_ref_div = 1;
 434         uint32_t best_feedback_div = 1;
 435         uint32_t best_frac_feedback_div = 0;
 436         uint32_t best_freq = -1;
 437         uint32_t best_error = 0xffffffff;
 438         uint32_t best_vco_diff = 1;
 439         uint32_t post_div;
 440
 441         DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 442         freq = freq * 1000;
 443
 444         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 445                 min_ref_div = max_ref_div = pll->reference_div;
 446         else {
 447                 while (min_ref_div < max_ref_div-1) {
 448                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 449                         uint32_t pll_in = pll->reference_freq / mid;
 450                         if (pll_in < pll->pll_in_min)
 451                                 max_ref_div = mid;
 452                         else if (pll_in > pll->pll_in_max)
 453                                 min_ref_div = mid;
 454                         else
 455                                 break;
 456                 }
 457         }
 458
 459         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 460                 min_post_div = max_post_div = pll->post_div;
 461
 462         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 463                 min_fractional_feed_div = pll->min_frac_feedback_div;
 464                 max_fractional_feed_div = pll->max_frac_feedback_div;
 465         }
 466
 467         for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
 468                 uint32_t ref_div;
 469
 470                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 471                         continue;
 472
 473                 /* legacy radeons only have a few post_divs */
 474                 if (pll->flags & RADEON_PLL_LEGACY) {
 475                         if ((post_div == 5) ||
 476                             (post_div == 7) ||
 477                             (post_div == 9) ||
 478                             (post_div == 10) ||
 479                             (post_div == 11) ||
 480                             (post_div == 13) ||
 481                             (post_div == 14) ||
 482                             (post_div == 15))
 483                                 continue;
 484                 }
 485
 486                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 487                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 488                         uint32_t pll_in = pll->reference_freq / ref_div;
 489                         uint32_t min_feed_div = pll->min_feedback_div;
 490                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 491
 492                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 493                                 continue;
 494
 495                         while (min_feed_div < max_feed_div) {
 496                                 uint32_t vco;
 497                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 498                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 499                                 uint32_t frac_feedback_div;
 500                                 uint64_t tmp;
 501
 502                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 503
 504                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 505                                 vco = radeon_div(tmp, ref_div);
 506
 507                                 if (vco < pll->pll_out_min) {
 508                                         min_feed_div = feedback_div + 1;
 509                                         continue;
 510                                 } else if (vco > pll->pll_out_max) {
 511                                         max_feed_div = feedback_div;
 512                                         continue;
 513                                 }
 514
 515                                 while (min_frac_feed_div < max_frac_feed_div) {
 516                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 517                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 518                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 519                                         current_freq = radeon_div(tmp, ref_div * post_div);
 520
 521                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 522                                                 error = freq - current_freq;
 523                                                 error = error < 0 ? 0xffffffff : error;
 524                                         } else
 525                                                 error = abs(current_freq - freq);
 526                                         vco_diff = abs(vco - best_vco);
 527
 528                                         if ((best_vco == 0 && error < best_error) ||
 529                                             (best_vco != 0 &&
 530                                              (error < best_error - 100 ||
 531                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 532                                                 best_post_div = post_div;
 533                                                 best_ref_div = ref_div;
 534                                                 best_feedback_div = feedback_div;
 535                                                 best_frac_feedback_div = frac_feedback_div;
 536                                                 best_freq = current_freq;
 537                                                 best_error = error;
 538                                                 best_vco_diff = vco_diff;
 539                                         } else if (current_freq == freq) {
 540                                                 if (best_freq == -1) {
 541                                                         best_post_div = post_div;
 542                                                         best_ref_div = ref_div;
 543                                                         best_feedback_div = feedback_div;
 544                                                         best_frac_feedback_div = frac_feedback_div;
 545                                                         best_freq = current_freq;
 546                                                         best_error = error;
 547                                                         best_vco_diff = vco_diff;
 548                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 549                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 550                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 551                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 552                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 553                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 554                                                         best_post_div = post_div;
 555                                                         best_ref_div = ref_div;
 556                                                         best_feedback_div = feedback_div;
 557                                                         best_frac_feedback_div = frac_feedback_div;
 558                                                         best_freq = current_freq;
 559                                                         best_error = error;
 560                                                         best_vco_diff = vco_diff;
 561                                                 }
 562                                         }
 563                                         if (current_freq < freq)
 564                                                 min_frac_feed_div = frac_feedback_div + 1;
 565                                         else
 566                                                 max_frac_feed_div = frac_feedback_div;
 567                                 }
 568                                 if (current_freq < freq)
 569                                         min_feed_div = feedback_div + 1;
 570                                 else
 571                                         max_feed_div = feedback_div;
 572                         }
 573                 }
 574         }
 575
 576         *dot_clock_p = best_freq / 10000;
 577         *fb_div_p = best_feedback_div;
 578         *frac_fb_div_p = best_frac_feedback_div;
 579         *ref_div_p = best_ref_div;
 580         *post_div_p = best_post_div;
 581 }
 582
 583 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 584                               uint64_t freq,
 585                               uint32_t *dot_clock_p,
 586                               uint32_t *fb_div_p,
 587                               uint32_t *frac_fb_div_p,
 588                               uint32_t *ref_div_p,
 589                               uint32_t *post_div_p)
 590 {
 591         fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
 592         fixed20_12 pll_out_max, pll_out_min;
 593         fixed20_12 pll_in_max, pll_in_min;
 594         fixed20_12 reference_freq;
 595         fixed20_12 error, ffreq, a, b;
 596
 597         pll_out_max.full = rfixed_const(pll->pll_out_max);
 598         pll_out_min.full = rfixed_const(pll->pll_out_min);
 599         pll_in_max.full = rfixed_const(pll->pll_in_max);
 600         pll_in_min.full = rfixed_const(pll->pll_in_min);
 601         reference_freq.full = rfixed_const(pll->reference_freq);
 602         do_div(freq, 10);
 603         ffreq.full = rfixed_const(freq);
 604         error.full = rfixed_const(100 * 100);
 605
 606         /* max p */
 607         p.full = rfixed_div(pll_out_max, ffreq);
 608         p.full = rfixed_floor(p);
 609
 610         /* min m */
 611         m.full = rfixed_div(reference_freq, pll_in_max);
 612         m.full = rfixed_ceil(m);
 613
 614         while (1) {
 615                 n.full = rfixed_div(ffreq, reference_freq);
 616                 n.full = rfixed_mul(n, m);
 617                 n.full = rfixed_mul(n, p);
 618
 619                 f_vco.full = rfixed_div(n, m);
 620                 f_vco.full = rfixed_mul(f_vco, reference_freq);
 621
 622                 f_pclk.full = rfixed_div(f_vco, p);
 623
 624                 if (f_pclk.full > ffreq.full)
 625                         error.full = f_pclk.full - ffreq.full;
 626                 else
 627                         error.full = ffreq.full - f_pclk.full;
 628                 error.full = rfixed_div(error, f_pclk);
 629                 a.full = rfixed_const(100 * 100);
 630                 error.full = rfixed_mul(error, a);
 631
 632                 a.full = rfixed_mul(m, p);
 633                 a.full = rfixed_div(n, a);
 634                 best_freq.full = rfixed_mul(reference_freq, a);
 635
 636                 if (rfixed_trunc(error) < 25)
 637                         break;
 638
 639                 a.full = rfixed_const(1);
 640                 m.full = m.full + a.full;
 641                 a.full = rfixed_div(reference_freq, m);
 642                 if (a.full >= pll_in_min.full)
 643                         continue;
 644
 645                 m.full = rfixed_div(reference_freq, pll_in_max);
 646                 m.full = rfixed_ceil(m);
 647                 a.full= rfixed_const(1);
 648                 p.full = p.full - a.full;
 649                 a.full = rfixed_mul(p, ffreq);
 650                 if (a.full >= pll_out_min.full)
 651                         continue;
 652                 else {
 653                         DRM_ERROR("Unable to find pll dividers\n");
 654                         break;
 655                 }
 656         }
 657
 658         a.full = rfixed_const(10);
 659         b.full = rfixed_mul(n, a);
 660
 661         frac_n.full = rfixed_floor(n);
 662         frac_n.full = rfixed_mul(frac_n, a);
 663         frac_n.full = b.full - frac_n.full;
 664
 665         *dot_clock_p = rfixed_trunc(best_freq);
 666         *fb_div_p = rfixed_trunc(n);
 667         *frac_fb_div_p = rfixed_trunc(frac_n);
 668         *ref_div_p = rfixed_trunc(m);
 669         *post_div_p = rfixed_trunc(p);
 670
 671         DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
 672 }
 673
 674 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 675 {
 676         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 677         struct drm_device *dev = fb->dev;
 678
 679         if (fb->fbdev)
 680                 radeonfb_remove(dev, fb);
 681
 682         if (radeon_fb->obj)
 683                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
 684         drm_framebuffer_cleanup(fb);
 685         kfree(radeon_fb);
 686 }
 687
 688 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 689                                                   struct drm_file *file_priv,
 690                                                   unsigned int *handle)
 691 {
 692         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 693
 694         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 695 }
 696
 697 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 698         .destroy = radeon_user_framebuffer_destroy,
 699         .create_handle = radeon_user_framebuffer_create_handle,
 700 };
 701
 702 struct drm_framebuffer *
 703 radeon_framebuffer_create(struct drm_device *dev,
 704                           struct drm_mode_fb_cmd *mode_cmd,
 705                           struct drm_gem_object *obj)
 706 {
 707         struct radeon_framebuffer *radeon_fb;
 708
 709         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 710         if (radeon_fb == NULL) {
 711                 return NULL;
 712         }
 713         drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
 714         drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
 715         radeon_fb->obj = obj;
 716         return &radeon_fb->base;
 717 }
 718
 719 static struct drm_framebuffer *
 720 radeon_user_framebuffer_create(struct drm_device *dev,
 721                                struct drm_file *file_priv,
 722                                struct drm_mode_fb_cmd *mode_cmd)
 723 {
 724         struct drm_gem_object *obj;
 725
 726         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
 727         if (obj ==  NULL) {
 728                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 729                         "can't create framebuffer\n", mode_cmd->handle);
 730                 return NULL;
 731         }
 732         return radeon_framebuffer_create(dev, mode_cmd, obj);
 733 }
 734
 735 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 736         .fb_create = radeon_user_framebuffer_create,
 737         .fb_changed = radeonfb_probe,
 738 };
 739
 740 struct drm_prop_enum_list {
 741         int type;
 742         char *name;
 743 };
 744
 745 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 746 {       { 0, "driver" },
 747         { 1, "bios" },
 748 };
 749
 750 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 751 {       { TV_STD_NTSC, "ntsc" },
 752         { TV_STD_PAL, "pal" },
 753         { TV_STD_PAL_M, "pal-m" },
 754         { TV_STD_PAL_60, "pal-60" },
 755         { TV_STD_NTSC_J, "ntsc-j" },
 756         { TV_STD_SCART_PAL, "scart-pal" },
 757         { TV_STD_PAL_CN, "pal-cn" },
 758         { TV_STD_SECAM, "secam" },
 759 };
 760
 761 static int radeon_modeset_create_props(struct radeon_device *rdev)
 762 {
 763         int i, sz;
 764
 765         if (rdev->is_atom_bios) {
 766                 rdev->mode_info.coherent_mode_property =
 767                         drm_property_create(rdev->ddev,
 768                                             DRM_MODE_PROP_RANGE,
 769                                             "coherent", 2);
 770                 if (!rdev->mode_info.coherent_mode_property)
 771                         return -ENOMEM;
 772
 773                 rdev->mode_info.coherent_mode_property->values[0] = 0;
 774                 rdev->mode_info.coherent_mode_property->values[1] = 1;
 775         }
 776
 777         if (!ASIC_IS_AVIVO(rdev)) {
 778                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
 779                 rdev->mode_info.tmds_pll_property =
 780                         drm_property_create(rdev->ddev,
 781                                             DRM_MODE_PROP_ENUM,
 782                                             "tmds_pll", sz);
 783                 for (i = 0; i < sz; i++) {
 784                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
 785                                               i,
 786                                               radeon_tmds_pll_enum_list[i].type,
 787                                               radeon_tmds_pll_enum_list[i].name);
 788                 }
 789         }
 790
 791         rdev->mode_info.load_detect_property =
 792                 drm_property_create(rdev->ddev,
 793                                     DRM_MODE_PROP_RANGE,
 794                                     "load detection", 2);
 795         if (!rdev->mode_info.load_detect_property)
 796                 return -ENOMEM;
 797         rdev->mode_info.load_detect_property->values[0] = 0;
 798         rdev->mode_info.load_detect_property->values[1] = 1;
 799
 800         drm_mode_create_scaling_mode_property(rdev->ddev);
 801
 802         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
 803         rdev->mode_info.tv_std_property =
 804                 drm_property_create(rdev->ddev,
 805                                     DRM_MODE_PROP_ENUM,
 806                                     "tv standard", sz);
 807         for (i = 0; i < sz; i++) {
 808                 drm_property_add_enum(rdev->mode_info.tv_std_property,
 809                                       i,
 810                                       radeon_tv_std_enum_list[i].type,
 811                                       radeon_tv_std_enum_list[i].name);
 812         }
 813
 814         return 0;
 815 }
 816
 817 int radeon_modeset_init(struct radeon_device *rdev)
 818 {
 819         int num_crtc = 2, i;
 820         int ret;
 821
 822         drm_mode_config_init(rdev->ddev);
 823         rdev->mode_info.mode_config_initialized = true;
 824
 825         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
 826
 827         if (ASIC_IS_AVIVO(rdev)) {
 828                 rdev->ddev->mode_config.max_width = 8192;
 829                 rdev->ddev->mode_config.max_height = 8192;
 830         } else {
 831                 rdev->ddev->mode_config.max_width = 4096;
 832                 rdev->ddev->mode_config.max_height = 4096;
 833         }
 834
 835         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
 836
 837         ret = radeon_modeset_create_props(rdev);
 838         if (ret) {
 839                 return ret;
 840         }
 841
 842         if (rdev->flags & RADEON_SINGLE_CRTC)
 843                 num_crtc = 1;
 844
 845         /* allocate crtcs */
 846         for (i = 0; i < num_crtc; i++) {
 847                 radeon_crtc_init(rdev->ddev, i);
 848         }
 849
 850         /* okay we should have all the bios connectors */
 851         ret = radeon_setup_enc_conn(rdev->ddev);
 852         if (!ret) {
 853                 return ret;
 854         }
 855         /* initialize hpd */
 856         radeon_hpd_init(rdev);
 857         drm_helper_initial_config(rdev->ddev);
 858         return 0;
 859 }
 860
 861 void radeon_modeset_fini(struct radeon_device *rdev)
 862 {
 863         if (rdev->mode_info.mode_config_initialized) {
 864                 radeon_hpd_fini(rdev);
 865                 drm_mode_config_cleanup(rdev->ddev);
 866                 rdev->mode_info.mode_config_initialized = false;
 867         }
 868 }
 869
 870 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 871                                 struct drm_display_mode *mode,
 872                                 struct drm_display_mode *adjusted_mode)
 873 {
 874         struct drm_device *dev = crtc->dev;
 875         struct drm_encoder *encoder;
 876         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 877         struct radeon_encoder *radeon_encoder;
 878         bool first = true;
 879
 880         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 881                 radeon_encoder = to_radeon_encoder(encoder);
 882                 if (encoder->crtc != crtc)
 883                         continue;
 884                 if (first) {
 885                         /* set scaling */
 886                         if (radeon_encoder->rmx_type == RMX_OFF)
 887                                 radeon_crtc->rmx_type = RMX_OFF;
 888                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
 889                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
 890                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
 891                         else
 892                                 radeon_crtc->rmx_type = RMX_OFF;
 893                         /* copy native mode */
 894                         memcpy(&radeon_crtc->native_mode,
 895                                &radeon_encoder->native_mode,
 896                                 sizeof(struct drm_display_mode));
 897                         first = false;
 898                 } else {
 899                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
 900                                 /* WARNING: Right now this can't happen but
 901                                  * in the future we need to check that scaling
 902                                  * are consistent accross different encoder
 903                                  * (ie all encoder can work with the same
 904                                  *  scaling).
 905                                  */
 906                                 DRM_ERROR("Scaling not consistent accross encoder.\n");
 907                                 return false;
 908                         }
 909                 }
 910         }
 911         if (radeon_crtc->rmx_type != RMX_OFF) {
 912                 fixed20_12 a, b;
 913                 a.full = rfixed_const(crtc->mode.vdisplay);
 914                 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
 915                 radeon_crtc->vsc.full = rfixed_div(a, b);
 916                 a.full = rfixed_const(crtc->mode.hdisplay);
 917                 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
 918                 radeon_crtc->hsc.full = rfixed_div(a, b);
 919         } else {
 920                 radeon_crtc->vsc.full = rfixed_const(1);
 921                 radeon_crtc->hsc.full = rfixed_const(1);
 922         }
 923         return true;
 924 }