2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include <asm/div64.h>
33 #include "drm_crtc_helper.h"
36 static int radeon_ddc_dump(struct drm_connector *connector);
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
136 avivo_crtc_load_lut(crtc);
138 legacy_crtc_load_lut(crtc);
141 void radeon_crtc_save_lut(struct drm_crtc *crtc)
143 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
149 for (i = 0; i < 256; i++) {
150 radeon_crtc->lut_r_copy[i] = radeon_crtc->lut_r[i];
151 radeon_crtc->lut_g_copy[i] = radeon_crtc->lut_g[i];
152 radeon_crtc->lut_b_copy[i] = radeon_crtc->lut_b[i];
156 void radeon_crtc_restore_lut(struct drm_crtc *crtc)
158 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
164 for (i = 0; i < 256; i++) {
165 radeon_crtc->lut_r[i] = radeon_crtc->lut_r_copy[i];
166 radeon_crtc->lut_g[i] = radeon_crtc->lut_g_copy[i];
167 radeon_crtc->lut_b[i] = radeon_crtc->lut_b_copy[i];
170 radeon_crtc_load_lut(crtc);
173 /** Sets the color ramps on behalf of fbcon */
174 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
179 radeon_crtc->lut_r[regno] = red >> 6;
180 radeon_crtc->lut_g[regno] = green >> 6;
181 radeon_crtc->lut_b[regno] = blue >> 6;
184 /** Gets the color ramps on behalf of fbcon */
185 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
186 u16 *blue, int regno)
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
190 *red = radeon_crtc->lut_r[regno] << 6;
191 *green = radeon_crtc->lut_g[regno] << 6;
192 *blue = radeon_crtc->lut_b[regno] << 6;
195 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
196 u16 *blue, uint32_t start, uint32_t size)
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 int end = (start + size > 256) ? 256 : start + size, i;
201 /* userspace palettes are always correct as is */
202 for (i = start; i < end; i++) {
203 radeon_crtc->lut_r[i] = red[i] >> 6;
204 radeon_crtc->lut_g[i] = green[i] >> 6;
205 radeon_crtc->lut_b[i] = blue[i] >> 6;
207 radeon_crtc_load_lut(crtc);
210 static void radeon_crtc_destroy(struct drm_crtc *crtc)
212 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
214 drm_crtc_cleanup(crtc);
218 static const struct drm_crtc_funcs radeon_crtc_funcs = {
219 .cursor_set = radeon_crtc_cursor_set,
220 .cursor_move = radeon_crtc_cursor_move,
221 .gamma_set = radeon_crtc_gamma_set,
222 .set_config = drm_crtc_helper_set_config,
223 .destroy = radeon_crtc_destroy,
226 static void radeon_crtc_init(struct drm_device *dev, int index)
228 struct radeon_device *rdev = dev->dev_private;
229 struct radeon_crtc *radeon_crtc;
232 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
233 if (radeon_crtc == NULL)
236 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
238 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
239 radeon_crtc->crtc_id = index;
240 rdev->mode_info.crtcs[index] = radeon_crtc;
243 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
244 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
245 radeon_crtc->mode_set.num_connectors = 0;
248 for (i = 0; i < 256; i++) {
249 radeon_crtc->lut_r[i] = i << 2;
250 radeon_crtc->lut_g[i] = i << 2;
251 radeon_crtc->lut_b[i] = i << 2;
254 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
255 radeon_atombios_init_crtc(dev, radeon_crtc);
257 radeon_legacy_init_crtc(dev, radeon_crtc);
260 static const char *encoder_names[34] = {
280 "INTERNAL_KLDSCP_TMDS1",
281 "INTERNAL_KLDSCP_DVO1",
282 "INTERNAL_KLDSCP_DAC1",
283 "INTERNAL_KLDSCP_DAC2",
292 "INTERNAL_KLDSCP_LVTMA",
297 static const char *connector_names[15] = {
315 static const char *hpd_names[6] = {
324 static void radeon_print_display_setup(struct drm_device *dev)
326 struct drm_connector *connector;
327 struct radeon_connector *radeon_connector;
328 struct drm_encoder *encoder;
329 struct radeon_encoder *radeon_encoder;
333 DRM_INFO("Radeon Display Connectors\n");
334 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
335 radeon_connector = to_radeon_connector(connector);
336 DRM_INFO("Connector %d:\n", i);
337 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
338 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
339 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
340 if (radeon_connector->ddc_bus) {
341 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
342 radeon_connector->ddc_bus->rec.mask_clk_reg,
343 radeon_connector->ddc_bus->rec.mask_data_reg,
344 radeon_connector->ddc_bus->rec.a_clk_reg,
345 radeon_connector->ddc_bus->rec.a_data_reg,
346 radeon_connector->ddc_bus->rec.en_clk_reg,
347 radeon_connector->ddc_bus->rec.en_data_reg,
348 radeon_connector->ddc_bus->rec.y_clk_reg,
349 radeon_connector->ddc_bus->rec.y_data_reg);
350 if (radeon_connector->router_bus)
351 DRM_INFO(" DDC Router 0x%x/0x%x\n",
352 radeon_connector->router.mux_control_pin,
353 radeon_connector->router.mux_state);
355 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
356 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
357 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
358 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
359 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
360 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
361 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
363 DRM_INFO(" Encoders:\n");
364 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
365 radeon_encoder = to_radeon_encoder(encoder);
366 devices = radeon_encoder->devices & radeon_connector->devices;
368 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
369 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
370 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
371 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
372 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
373 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
374 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
375 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
376 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
377 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
378 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
379 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
380 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
381 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
382 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
383 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
384 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
385 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
386 if (devices & ATOM_DEVICE_TV1_SUPPORT)
387 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
388 if (devices & ATOM_DEVICE_CV_SUPPORT)
389 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
396 static bool radeon_setup_enc_conn(struct drm_device *dev)
398 struct radeon_device *rdev = dev->dev_private;
399 struct drm_connector *drm_connector;
403 if (rdev->is_atom_bios) {
404 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
406 ret = radeon_get_atom_connector_info_from_object_table(dev);
408 ret = radeon_get_legacy_connector_info_from_bios(dev);
410 ret = radeon_get_legacy_connector_info_from_table(dev);
413 if (!ASIC_IS_AVIVO(rdev))
414 ret = radeon_get_legacy_connector_info_from_table(dev);
417 radeon_setup_encoder_clones(dev);
418 radeon_print_display_setup(dev);
419 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
420 radeon_ddc_dump(drm_connector);
426 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
428 struct drm_device *dev = radeon_connector->base.dev;
429 struct radeon_device *rdev = dev->dev_private;
432 /* on hw with routers, select right port */
433 if (radeon_connector->router.valid)
434 radeon_router_select_port(radeon_connector);
436 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
437 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
438 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
439 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
440 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
441 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
443 if (!radeon_connector->ddc_bus)
445 if (!radeon_connector->edid) {
446 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
448 /* some servers provide a hardcoded edid in rom for KVMs */
449 if (!radeon_connector->edid)
450 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
451 if (radeon_connector->edid) {
452 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
453 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
456 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
460 static int radeon_ddc_dump(struct drm_connector *connector)
463 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
466 /* on hw with routers, select right port */
467 if (radeon_connector->router.valid)
468 radeon_router_select_port(radeon_connector);
470 if (!radeon_connector->ddc_bus)
472 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
479 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
489 void radeon_compute_pll(struct radeon_pll *pll,
491 uint32_t *dot_clock_p,
493 uint32_t *frac_fb_div_p,
495 uint32_t *post_div_p)
497 uint32_t min_ref_div = pll->min_ref_div;
498 uint32_t max_ref_div = pll->max_ref_div;
499 uint32_t min_post_div = pll->min_post_div;
500 uint32_t max_post_div = pll->max_post_div;
501 uint32_t min_fractional_feed_div = 0;
502 uint32_t max_fractional_feed_div = 0;
503 uint32_t best_vco = pll->best_vco;
504 uint32_t best_post_div = 1;
505 uint32_t best_ref_div = 1;
506 uint32_t best_feedback_div = 1;
507 uint32_t best_frac_feedback_div = 0;
508 uint32_t best_freq = -1;
509 uint32_t best_error = 0xffffffff;
510 uint32_t best_vco_diff = 1;
512 u32 pll_out_min, pll_out_max;
514 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
517 if (pll->flags & RADEON_PLL_IS_LCD) {
518 pll_out_min = pll->lcd_pll_out_min;
519 pll_out_max = pll->lcd_pll_out_max;
521 pll_out_min = pll->pll_out_min;
522 pll_out_max = pll->pll_out_max;
525 if (pll->flags & RADEON_PLL_USE_REF_DIV)
526 min_ref_div = max_ref_div = pll->reference_div;
528 while (min_ref_div < max_ref_div-1) {
529 uint32_t mid = (min_ref_div + max_ref_div) / 2;
530 uint32_t pll_in = pll->reference_freq / mid;
531 if (pll_in < pll->pll_in_min)
533 else if (pll_in > pll->pll_in_max)
540 if (pll->flags & RADEON_PLL_USE_POST_DIV)
541 min_post_div = max_post_div = pll->post_div;
543 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
544 min_fractional_feed_div = pll->min_frac_feedback_div;
545 max_fractional_feed_div = pll->max_frac_feedback_div;
548 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
551 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
554 /* legacy radeons only have a few post_divs */
555 if (pll->flags & RADEON_PLL_LEGACY) {
556 if ((post_div == 5) ||
567 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
568 uint32_t feedback_div, current_freq = 0, error, vco_diff;
569 uint32_t pll_in = pll->reference_freq / ref_div;
570 uint32_t min_feed_div = pll->min_feedback_div;
571 uint32_t max_feed_div = pll->max_feedback_div + 1;
573 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
576 while (min_feed_div < max_feed_div) {
578 uint32_t min_frac_feed_div = min_fractional_feed_div;
579 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
580 uint32_t frac_feedback_div;
583 feedback_div = (min_feed_div + max_feed_div) / 2;
585 tmp = (uint64_t)pll->reference_freq * feedback_div;
586 vco = radeon_div(tmp, ref_div);
588 if (vco < pll_out_min) {
589 min_feed_div = feedback_div + 1;
591 } else if (vco > pll_out_max) {
592 max_feed_div = feedback_div;
596 while (min_frac_feed_div < max_frac_feed_div) {
597 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
598 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
599 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
600 current_freq = radeon_div(tmp, ref_div * post_div);
602 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
603 if (freq < current_freq)
606 error = freq - current_freq;
608 error = abs(current_freq - freq);
609 vco_diff = abs(vco - best_vco);
611 if ((best_vco == 0 && error < best_error) ||
613 ((best_error > 100 && error < best_error - 100) ||
614 (abs(error - best_error) < 100 &&
615 vco_diff < best_vco_diff)))) {
616 best_post_div = post_div;
617 best_ref_div = ref_div;
618 best_feedback_div = feedback_div;
619 best_frac_feedback_div = frac_feedback_div;
620 best_freq = current_freq;
622 best_vco_diff = vco_diff;
624 if (current_freq < freq)
625 min_frac_feed_div = frac_feedback_div + 1;
627 max_frac_feed_div = frac_feedback_div;
629 if (current_freq < freq)
630 min_feed_div = feedback_div + 1;
632 max_feed_div = feedback_div;
637 *dot_clock_p = best_freq / 10000;
638 *fb_div_p = best_feedback_div;
639 *frac_fb_div_p = best_frac_feedback_div;
640 *ref_div_p = best_ref_div;
641 *post_div_p = best_post_div;
644 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
646 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
648 if (radeon_fb->obj) {
649 drm_gem_object_unreference_unlocked(radeon_fb->obj);
651 drm_framebuffer_cleanup(fb);
655 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
656 struct drm_file *file_priv,
657 unsigned int *handle)
659 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
661 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
664 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
665 .destroy = radeon_user_framebuffer_destroy,
666 .create_handle = radeon_user_framebuffer_create_handle,
670 radeon_framebuffer_init(struct drm_device *dev,
671 struct radeon_framebuffer *rfb,
672 struct drm_mode_fb_cmd *mode_cmd,
673 struct drm_gem_object *obj)
676 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
677 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
680 static struct drm_framebuffer *
681 radeon_user_framebuffer_create(struct drm_device *dev,
682 struct drm_file *file_priv,
683 struct drm_mode_fb_cmd *mode_cmd)
685 struct drm_gem_object *obj;
686 struct radeon_framebuffer *radeon_fb;
688 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
690 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
691 "can't create framebuffer\n", mode_cmd->handle);
692 return ERR_PTR(-ENOENT);
695 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
696 if (radeon_fb == NULL)
697 return ERR_PTR(-ENOMEM);
699 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
701 return &radeon_fb->base;
704 static void radeon_output_poll_changed(struct drm_device *dev)
706 struct radeon_device *rdev = dev->dev_private;
707 radeon_fb_output_poll_changed(rdev);
710 static const struct drm_mode_config_funcs radeon_mode_funcs = {
711 .fb_create = radeon_user_framebuffer_create,
712 .output_poll_changed = radeon_output_poll_changed
715 struct drm_prop_enum_list {
720 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
725 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
726 { { TV_STD_NTSC, "ntsc" },
727 { TV_STD_PAL, "pal" },
728 { TV_STD_PAL_M, "pal-m" },
729 { TV_STD_PAL_60, "pal-60" },
730 { TV_STD_NTSC_J, "ntsc-j" },
731 { TV_STD_SCART_PAL, "scart-pal" },
732 { TV_STD_PAL_CN, "pal-cn" },
733 { TV_STD_SECAM, "secam" },
736 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
737 { { UNDERSCAN_OFF, "off" },
738 { UNDERSCAN_ON, "on" },
739 { UNDERSCAN_AUTO, "auto" },
742 static int radeon_modeset_create_props(struct radeon_device *rdev)
746 if (rdev->is_atom_bios) {
747 rdev->mode_info.coherent_mode_property =
748 drm_property_create(rdev->ddev,
751 if (!rdev->mode_info.coherent_mode_property)
754 rdev->mode_info.coherent_mode_property->values[0] = 0;
755 rdev->mode_info.coherent_mode_property->values[1] = 1;
758 if (!ASIC_IS_AVIVO(rdev)) {
759 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
760 rdev->mode_info.tmds_pll_property =
761 drm_property_create(rdev->ddev,
764 for (i = 0; i < sz; i++) {
765 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
767 radeon_tmds_pll_enum_list[i].type,
768 radeon_tmds_pll_enum_list[i].name);
772 rdev->mode_info.load_detect_property =
773 drm_property_create(rdev->ddev,
775 "load detection", 2);
776 if (!rdev->mode_info.load_detect_property)
778 rdev->mode_info.load_detect_property->values[0] = 0;
779 rdev->mode_info.load_detect_property->values[1] = 1;
781 drm_mode_create_scaling_mode_property(rdev->ddev);
783 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
784 rdev->mode_info.tv_std_property =
785 drm_property_create(rdev->ddev,
788 for (i = 0; i < sz; i++) {
789 drm_property_add_enum(rdev->mode_info.tv_std_property,
791 radeon_tv_std_enum_list[i].type,
792 radeon_tv_std_enum_list[i].name);
795 sz = ARRAY_SIZE(radeon_underscan_enum_list);
796 rdev->mode_info.underscan_property =
797 drm_property_create(rdev->ddev,
800 for (i = 0; i < sz; i++) {
801 drm_property_add_enum(rdev->mode_info.underscan_property,
803 radeon_underscan_enum_list[i].type,
804 radeon_underscan_enum_list[i].name);
807 rdev->mode_info.underscan_hborder_property =
808 drm_property_create(rdev->ddev,
810 "underscan hborder", 2);
811 if (!rdev->mode_info.underscan_hborder_property)
813 rdev->mode_info.underscan_hborder_property->values[0] = 0;
814 rdev->mode_info.underscan_hborder_property->values[1] = 128;
816 rdev->mode_info.underscan_vborder_property =
817 drm_property_create(rdev->ddev,
819 "underscan vborder", 2);
820 if (!rdev->mode_info.underscan_vborder_property)
822 rdev->mode_info.underscan_vborder_property->values[0] = 0;
823 rdev->mode_info.underscan_vborder_property->values[1] = 128;
828 void radeon_update_display_priority(struct radeon_device *rdev)
830 /* adjustment options for the display watermarks */
831 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
832 /* set display priority to high for r3xx, rv515 chips
833 * this avoids flickering due to underflow to the
834 * display controllers during heavy acceleration.
835 * Don't force high on rs4xx igp chips as it seems to
836 * affect the sound card. See kernel bug 15982.
838 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
839 !(rdev->flags & RADEON_IS_IGP))
840 rdev->disp_priority = 2;
842 rdev->disp_priority = 0;
844 rdev->disp_priority = radeon_disp_priority;
848 int radeon_modeset_init(struct radeon_device *rdev)
853 drm_mode_config_init(rdev->ddev);
854 rdev->mode_info.mode_config_initialized = true;
856 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
858 if (ASIC_IS_AVIVO(rdev)) {
859 rdev->ddev->mode_config.max_width = 8192;
860 rdev->ddev->mode_config.max_height = 8192;
862 rdev->ddev->mode_config.max_width = 4096;
863 rdev->ddev->mode_config.max_height = 4096;
866 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
868 ret = radeon_modeset_create_props(rdev);
874 radeon_i2c_init(rdev);
876 /* check combios for a valid hardcoded EDID - Sun servers */
877 if (!rdev->is_atom_bios) {
878 /* check for hardcoded EDID in BIOS */
879 radeon_combios_check_hardcoded_edid(rdev);
883 for (i = 0; i < rdev->num_crtc; i++) {
884 radeon_crtc_init(rdev->ddev, i);
887 /* okay we should have all the bios connectors */
888 ret = radeon_setup_enc_conn(rdev->ddev);
893 radeon_hpd_init(rdev);
895 /* Initialize power management */
896 radeon_pm_init(rdev);
898 radeon_fbdev_init(rdev);
899 drm_kms_helper_poll_init(rdev->ddev);
904 void radeon_modeset_fini(struct radeon_device *rdev)
906 radeon_fbdev_fini(rdev);
907 kfree(rdev->mode_info.bios_hardcoded_edid);
908 radeon_pm_fini(rdev);
910 if (rdev->mode_info.mode_config_initialized) {
911 drm_kms_helper_poll_fini(rdev->ddev);
912 radeon_hpd_fini(rdev);
913 drm_mode_config_cleanup(rdev->ddev);
914 rdev->mode_info.mode_config_initialized = false;
917 radeon_i2c_fini(rdev);
920 static bool is_hdtv_mode(struct drm_display_mode *mode)
922 /* try and guess if this is a tv or a monitor */
923 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
924 (mode->vdisplay == 576) || /* 576p */
925 (mode->vdisplay == 720) || /* 720p */
926 (mode->vdisplay == 1080)) /* 1080p */
932 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
933 struct drm_display_mode *mode,
934 struct drm_display_mode *adjusted_mode)
936 struct drm_device *dev = crtc->dev;
937 struct radeon_device *rdev = dev->dev_private;
938 struct drm_encoder *encoder;
939 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
940 struct radeon_encoder *radeon_encoder;
941 struct drm_connector *connector;
942 struct radeon_connector *radeon_connector;
944 u32 src_v = 1, dst_v = 1;
945 u32 src_h = 1, dst_h = 1;
947 radeon_crtc->h_border = 0;
948 radeon_crtc->v_border = 0;
950 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
951 if (encoder->crtc != crtc)
953 radeon_encoder = to_radeon_encoder(encoder);
954 connector = radeon_get_connector_for_encoder(encoder);
955 radeon_connector = to_radeon_connector(connector);
959 if (radeon_encoder->rmx_type == RMX_OFF)
960 radeon_crtc->rmx_type = RMX_OFF;
961 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
962 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
963 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
965 radeon_crtc->rmx_type = RMX_OFF;
966 /* copy native mode */
967 memcpy(&radeon_crtc->native_mode,
968 &radeon_encoder->native_mode,
969 sizeof(struct drm_display_mode));
970 src_v = crtc->mode.vdisplay;
971 dst_v = radeon_crtc->native_mode.vdisplay;
972 src_h = crtc->mode.hdisplay;
973 dst_h = radeon_crtc->native_mode.hdisplay;
975 /* fix up for overscan on hdmi */
976 if (ASIC_IS_AVIVO(rdev) &&
977 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
978 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
979 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
980 drm_detect_hdmi_monitor(radeon_connector->edid) &&
981 is_hdtv_mode(mode)))) {
982 if (radeon_encoder->underscan_hborder != 0)
983 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
985 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
986 if (radeon_encoder->underscan_vborder != 0)
987 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
989 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
990 radeon_crtc->rmx_type = RMX_FULL;
991 src_v = crtc->mode.vdisplay;
992 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
993 src_h = crtc->mode.hdisplay;
994 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
998 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
999 /* WARNING: Right now this can't happen but
1000 * in the future we need to check that scaling
1001 * are consistent across different encoder
1002 * (ie all encoder can work with the same
1005 DRM_ERROR("Scaling not consistent across encoder.\n");
1010 if (radeon_crtc->rmx_type != RMX_OFF) {
1012 a.full = dfixed_const(src_v);
1013 b.full = dfixed_const(dst_v);
1014 radeon_crtc->vsc.full = dfixed_div(a, b);
1015 a.full = dfixed_const(src_h);
1016 b.full = dfixed_const(dst_h);
1017 radeon_crtc->hsc.full = dfixed_div(a, b);
1019 radeon_crtc->vsc.full = dfixed_const(1);
1020 radeon_crtc->hsc.full = dfixed_const(1);
1026 * Retrieve current video scanout position of crtc on a given gpu.
1028 * \param rdev Device to query.
1029 * \param crtc Crtc to query.
1030 * \param *vpos Location where vertical scanout position should be stored.
1031 * \param *hpos Location where horizontal scanout position should go.
1033 * Returns vpos as a positive number while in active scanout area.
1034 * Returns vpos as a negative number inside vblank, counting the number
1035 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1036 * until start of active scanout / end of vblank."
1038 * \return Flags, or'ed together as follows:
1040 * RADEON_SCANOUTPOS_VALID = Query successfull.
1041 * RADEON_SCANOUTPOS_INVBL = Inside vblank.
1042 * RADEON_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1043 * this flag means that returned position may be offset by a constant but
1044 * unknown small number of scanlines wrt. real scanout position.
1047 int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos)
1049 u32 stat_crtc = 0, vbl = 0, position = 0;
1050 int vbl_start, vbl_end, vtotal, ret = 0;
1053 if (ASIC_IS_DCE4(rdev)) {
1055 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1056 EVERGREEN_CRTC0_REGISTER_OFFSET);
1057 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1058 EVERGREEN_CRTC0_REGISTER_OFFSET);
1059 ret |= RADEON_SCANOUTPOS_VALID;
1062 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1063 EVERGREEN_CRTC1_REGISTER_OFFSET);
1064 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1065 EVERGREEN_CRTC1_REGISTER_OFFSET);
1066 ret |= RADEON_SCANOUTPOS_VALID;
1069 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1070 EVERGREEN_CRTC2_REGISTER_OFFSET);
1071 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1072 EVERGREEN_CRTC2_REGISTER_OFFSET);
1073 ret |= RADEON_SCANOUTPOS_VALID;
1076 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1077 EVERGREEN_CRTC3_REGISTER_OFFSET);
1078 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1079 EVERGREEN_CRTC3_REGISTER_OFFSET);
1080 ret |= RADEON_SCANOUTPOS_VALID;
1083 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1084 EVERGREEN_CRTC4_REGISTER_OFFSET);
1085 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1086 EVERGREEN_CRTC4_REGISTER_OFFSET);
1087 ret |= RADEON_SCANOUTPOS_VALID;
1090 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1091 EVERGREEN_CRTC5_REGISTER_OFFSET);
1092 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1093 EVERGREEN_CRTC5_REGISTER_OFFSET);
1094 ret |= RADEON_SCANOUTPOS_VALID;
1096 } else if (ASIC_IS_AVIVO(rdev)) {
1098 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1099 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1100 ret |= RADEON_SCANOUTPOS_VALID;
1103 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1104 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1105 ret |= RADEON_SCANOUTPOS_VALID;
1108 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1110 /* Assume vbl_end == 0, get vbl_start from
1113 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1114 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1115 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1116 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1117 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1118 if (!(stat_crtc & 1))
1121 ret |= RADEON_SCANOUTPOS_VALID;
1124 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1125 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1126 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1127 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1128 if (!(stat_crtc & 1))
1131 ret |= RADEON_SCANOUTPOS_VALID;
1135 /* Decode into vertical and horizontal scanout position. */
1136 *vpos = position & 0x1fff;
1137 *hpos = (position >> 16) & 0x1fff;
1139 /* Valid vblank area boundaries from gpu retrieved? */
1142 ret |= RADEON_SCANOUTPOS_ACCURATE;
1143 vbl_start = vbl & 0x1fff;
1144 vbl_end = (vbl >> 16) & 0x1fff;
1147 /* No: Fake something reasonable which gives at least ok results. */
1148 vbl_start = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vdisplay;
1152 /* Test scanout position against vblank region. */
1153 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1156 /* Check if inside vblank area and apply corrective offsets:
1157 * vpos will then be >=0 in video scanout area, but negative
1158 * within vblank area, counting down the number of lines until
1162 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1163 if (in_vbl && (*vpos >= vbl_start)) {
1164 vtotal = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vtotal;
1165 *vpos = *vpos - vtotal;
1168 /* Correct for shifted end of vbl at vbl_end. */
1169 *vpos = *vpos - vbl_end;
1173 ret |= RADEON_SCANOUTPOS_INVBL;