drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  36                       uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           bool linkb, uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd);
  52
  53 /* from radeon_legacy_encoder.c */
  54 extern void
  55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  56                           uint32_t supported_device);
  57
  58 union atom_supported_devices {
  59         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  60         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  62 };
  63
  64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  65                                                                uint8_t id)
  66 {
  67         struct atom_context *ctx = rdev->mode_info.atom_context;
  68         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  69         struct radeon_i2c_bus_rec i2c;
  70         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  71         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  72         uint16_t data_offset, size;
  73         int i, num_indices;
  74
  75         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  76         i2c.valid = false;
  77
  78         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  79                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  80
  81                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  82                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  83
  84                 for (i = 0; i < num_indices; i++) {
  85                         gpio = &i2c_info->asGPIO_Info[i];
  86
  87                         if (gpio->sucI2cId.ucAccess == id) {
  88                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
  89                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
  90                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
  91                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
  92                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
  93                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
  94                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
  95                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
  96                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  97                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  98                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  99                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 100                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 101                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 102                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 103                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 104
 105                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 106                                         i2c.hw_capable = true;
 107                                 else
 108                                         i2c.hw_capable = false;
 109
 110                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 111                                         i2c.mm_i2c = true;
 112                                 else
 113                                         i2c.mm_i2c = false;
 114
 115                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 116
 117                                 i2c.valid = true;
 118                                 break;
 119                         }
 120                 }
 121         }
 122
 123         return i2c;
 124 }
 125
 126 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 127                                                         u8 id)
 128 {
 129         struct atom_context *ctx = rdev->mode_info.atom_context;
 130         struct radeon_gpio_rec gpio;
 131         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 132         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 133         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 134         u16 data_offset, size;
 135         int i, num_indices;
 136
 137         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 138         gpio.valid = false;
 139
 140         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 141                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 142
 143                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 144                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 145
 146                 for (i = 0; i < num_indices; i++) {
 147                         pin = &gpio_info->asGPIO_Pin[i];
 148                         if (id == pin->ucGPIO_ID) {
 149                                 gpio.id = pin->ucGPIO_ID;
 150                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 151                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 152                                 gpio.valid = true;
 153                                 break;
 154                         }
 155                 }
 156         }
 157
 158         return gpio;
 159 }
 160
 161 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 162                                                             struct radeon_gpio_rec *gpio)
 163 {
 164         struct radeon_hpd hpd;
 165         u32 reg;
 166
 167         if (ASIC_IS_DCE4(rdev))
 168                 reg = EVERGREEN_DC_GPIO_HPD_A;
 169         else
 170                 reg = AVIVO_DC_GPIO_HPD_A;
 171
 172         hpd.gpio = *gpio;
 173         if (gpio->reg == reg) {
 174                 switch(gpio->mask) {
 175                 case (1 << 0):
 176                         hpd.hpd = RADEON_HPD_1;
 177                         break;
 178                 case (1 << 8):
 179                         hpd.hpd = RADEON_HPD_2;
 180                         break;
 181                 case (1 << 16):
 182                         hpd.hpd = RADEON_HPD_3;
 183                         break;
 184                 case (1 << 24):
 185                         hpd.hpd = RADEON_HPD_4;
 186                         break;
 187                 case (1 << 26):
 188                         hpd.hpd = RADEON_HPD_5;
 189                         break;
 190                 case (1 << 28):
 191                         hpd.hpd = RADEON_HPD_6;
 192                         break;
 193                 default:
 194                         hpd.hpd = RADEON_HPD_NONE;
 195                         break;
 196                 }
 197         } else
 198                 hpd.hpd = RADEON_HPD_NONE;
 199         return hpd;
 200 }
 201
 202 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 203                                      uint32_t supported_device,
 204                                      int *connector_type,
 205                                      struct radeon_i2c_bus_rec *i2c_bus,
 206                                      uint16_t *line_mux,
 207                                      struct radeon_hpd *hpd)
 208 {
 209
 210         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 211         if ((dev->pdev->device == 0x791e) &&
 212             (dev->pdev->subsystem_vendor == 0x1043) &&
 213             (dev->pdev->subsystem_device == 0x826d)) {
 214                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 215                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 216                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 217         }
 218
 219         /* Asrock RS600 board lists the DVI port as HDMI */
 220         if ((dev->pdev->device == 0x7941) &&
 221             (dev->pdev->subsystem_vendor == 0x1849) &&
 222             (dev->pdev->subsystem_device == 0x7941)) {
 223                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 224                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 225                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 226         }
 227
 228         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 229         if ((dev->pdev->device == 0x7941) &&
 230             (dev->pdev->subsystem_vendor == 0x147b) &&
 231             (dev->pdev->subsystem_device == 0x2412)) {
 232                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 233                         return false;
 234         }
 235
 236         /* Falcon NW laptop lists vga ddc line for LVDS */
 237         if ((dev->pdev->device == 0x5653) &&
 238             (dev->pdev->subsystem_vendor == 0x1462) &&
 239             (dev->pdev->subsystem_device == 0x0291)) {
 240                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 241                         i2c_bus->valid = false;
 242                         *line_mux = 53;
 243                 }
 244         }
 245
 246         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 247         if ((dev->pdev->device == 0x7146) &&
 248             (dev->pdev->subsystem_vendor == 0x17af) &&
 249             (dev->pdev->subsystem_device == 0x2058)) {
 250                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 251                         return false;
 252         }
 253
 254         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 255         if ((dev->pdev->device == 0x7142) &&
 256             (dev->pdev->subsystem_vendor == 0x1458) &&
 257             (dev->pdev->subsystem_device == 0x2134)) {
 258                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 259                         return false;
 260         }
 261
 262
 263         /* Funky macbooks */
 264         if ((dev->pdev->device == 0x71C5) &&
 265             (dev->pdev->subsystem_vendor == 0x106b) &&
 266             (dev->pdev->subsystem_device == 0x0080)) {
 267                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 268                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 269                         return false;
 270                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 271                         *line_mux = 0x90;
 272         }
 273
 274         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 275         if ((dev->pdev->device == 0x9598) &&
 276             (dev->pdev->subsystem_vendor == 0x1043) &&
 277             (dev->pdev->subsystem_device == 0x01da)) {
 278                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 279                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 280                 }
 281         }
 282
 283         /* ASUS HD 3450 board lists the DVI port as HDMI */
 284         if ((dev->pdev->device == 0x95C5) &&
 285             (dev->pdev->subsystem_vendor == 0x1043) &&
 286             (dev->pdev->subsystem_device == 0x01e2)) {
 287                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 288                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 289                 }
 290         }
 291
 292         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 293          * HDMI + VGA reporting as HDMI
 294          */
 295         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 296                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 297                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 298                         *line_mux = 0;
 299                 }
 300         }
 301
 302         /* Acer laptop reports DVI-D as DVI-I */
 303         if ((dev->pdev->device == 0x95c4) &&
 304             (dev->pdev->subsystem_vendor == 0x1025) &&
 305             (dev->pdev->subsystem_device == 0x013c)) {
 306                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 307                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
 308                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 309         }
 310
 311         /* XFX Pine Group device rv730 reports no VGA DDC lines
 312          * even though they are wired up to record 0x93
 313          */
 314         if ((dev->pdev->device == 0x9498) &&
 315             (dev->pdev->subsystem_vendor == 0x1682) &&
 316             (dev->pdev->subsystem_device == 0x2452)) {
 317                 struct radeon_device *rdev = dev->dev_private;
 318                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 319         }
 320         return true;
 321 }
 322
 323 const int supported_devices_connector_convert[] = {
 324         DRM_MODE_CONNECTOR_Unknown,
 325         DRM_MODE_CONNECTOR_VGA,
 326         DRM_MODE_CONNECTOR_DVII,
 327         DRM_MODE_CONNECTOR_DVID,
 328         DRM_MODE_CONNECTOR_DVIA,
 329         DRM_MODE_CONNECTOR_SVIDEO,
 330         DRM_MODE_CONNECTOR_Composite,
 331         DRM_MODE_CONNECTOR_LVDS,
 332         DRM_MODE_CONNECTOR_Unknown,
 333         DRM_MODE_CONNECTOR_Unknown,
 334         DRM_MODE_CONNECTOR_HDMIA,
 335         DRM_MODE_CONNECTOR_HDMIB,
 336         DRM_MODE_CONNECTOR_Unknown,
 337         DRM_MODE_CONNECTOR_Unknown,
 338         DRM_MODE_CONNECTOR_9PinDIN,
 339         DRM_MODE_CONNECTOR_DisplayPort
 340 };
 341
 342 const uint16_t supported_devices_connector_object_id_convert[] = {
 343         CONNECTOR_OBJECT_ID_NONE,
 344         CONNECTOR_OBJECT_ID_VGA,
 345         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 346         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 347         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 348         CONNECTOR_OBJECT_ID_COMPOSITE,
 349         CONNECTOR_OBJECT_ID_SVIDEO,
 350         CONNECTOR_OBJECT_ID_LVDS,
 351         CONNECTOR_OBJECT_ID_9PIN_DIN,
 352         CONNECTOR_OBJECT_ID_9PIN_DIN,
 353         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 354         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 355         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 356         CONNECTOR_OBJECT_ID_SVIDEO
 357 };
 358
 359 const int object_connector_convert[] = {
 360         DRM_MODE_CONNECTOR_Unknown,
 361         DRM_MODE_CONNECTOR_DVII,
 362         DRM_MODE_CONNECTOR_DVII,
 363         DRM_MODE_CONNECTOR_DVID,
 364         DRM_MODE_CONNECTOR_DVID,
 365         DRM_MODE_CONNECTOR_VGA,
 366         DRM_MODE_CONNECTOR_Composite,
 367         DRM_MODE_CONNECTOR_SVIDEO,
 368         DRM_MODE_CONNECTOR_Unknown,
 369         DRM_MODE_CONNECTOR_Unknown,
 370         DRM_MODE_CONNECTOR_9PinDIN,
 371         DRM_MODE_CONNECTOR_Unknown,
 372         DRM_MODE_CONNECTOR_HDMIA,
 373         DRM_MODE_CONNECTOR_HDMIB,
 374         DRM_MODE_CONNECTOR_LVDS,
 375         DRM_MODE_CONNECTOR_9PinDIN,
 376         DRM_MODE_CONNECTOR_Unknown,
 377         DRM_MODE_CONNECTOR_Unknown,
 378         DRM_MODE_CONNECTOR_Unknown,
 379         DRM_MODE_CONNECTOR_DisplayPort,
 380         DRM_MODE_CONNECTOR_eDP,
 381         DRM_MODE_CONNECTOR_Unknown
 382 };
 383
 384 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 385 {
 386         struct radeon_device *rdev = dev->dev_private;
 387         struct radeon_mode_info *mode_info = &rdev->mode_info;
 388         struct atom_context *ctx = mode_info->atom_context;
 389         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 390         u16 size, data_offset;
 391         u8 frev, crev;
 392         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 393         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 394         ATOM_OBJECT_HEADER *obj_header;
 395         int i, j, path_size, device_support;
 396         int connector_type;
 397         u16 igp_lane_info, conn_id, connector_object_id;
 398         bool linkb;
 399         struct radeon_i2c_bus_rec ddc_bus;
 400         struct radeon_gpio_rec gpio;
 401         struct radeon_hpd hpd;
 402
 403         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 404                 return false;
 405
 406         if (crev < 2)
 407                 return false;
 408
 409         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 410         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 411             (ctx->bios + data_offset +
 412              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 413         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 414             (ctx->bios + data_offset +
 415              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 416         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 417
 418         path_size = 0;
 419         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 420                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 421                 ATOM_DISPLAY_OBJECT_PATH *path;
 422                 addr += path_size;
 423                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 424                 path_size += le16_to_cpu(path->usSize);
 425                 linkb = false;
 426                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 427                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 428
 429                         con_obj_id =
 430                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 431                             >> OBJECT_ID_SHIFT;
 432                         con_obj_num =
 433                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 434                             >> ENUM_ID_SHIFT;
 435                         con_obj_type =
 436                             (le16_to_cpu(path->usConnObjectId) &
 437                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 438
 439                         /* TODO CV support */
 440                         if (le16_to_cpu(path->usDeviceTag) ==
 441                                 ATOM_DEVICE_CV_SUPPORT)
 442                                 continue;
 443
 444                         /* IGP chips */
 445                         if ((rdev->flags & RADEON_IS_IGP) &&
 446                             (con_obj_id ==
 447                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 448                                 uint16_t igp_offset = 0;
 449                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 450
 451                                 index =
 452                                     GetIndexIntoMasterTable(DATA,
 453                                                             IntegratedSystemInfo);
 454
 455                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 456                                                            &crev, &igp_offset)) {
 457
 458                                         if (crev >= 2) {
 459                                                 igp_obj =
 460                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 461                                                          *) (ctx->bios + igp_offset);
 462
 463                                                 if (igp_obj) {
 464                                                         uint32_t slot_config, ct;
 465
 466                                                         if (con_obj_num == 1)
 467                                                                 slot_config =
 468                                                                         igp_obj->
 469                                                                         ulDDISlot1Config;
 470                                                         else
 471                                                                 slot_config =
 472                                                                         igp_obj->
 473                                                                         ulDDISlot2Config;
 474
 475                                                         ct = (slot_config >> 16) & 0xff;
 476                                                         connector_type =
 477                                                                 object_connector_convert
 478                                                                 [ct];
 479                                                         connector_object_id = ct;
 480                                                         igp_lane_info =
 481                                                                 slot_config & 0xffff;
 482                                                 } else
 483                                                         continue;
 484                                         } else
 485                                                 continue;
 486                                 } else {
 487                                         igp_lane_info = 0;
 488                                         connector_type =
 489                                                 object_connector_convert[con_obj_id];
 490                                         connector_object_id = con_obj_id;
 491                                 }
 492                         } else {
 493                                 igp_lane_info = 0;
 494                                 connector_type =
 495                                     object_connector_convert[con_obj_id];
 496                                 connector_object_id = con_obj_id;
 497                         }
 498
 499                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 500                                 continue;
 501
 502                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
 503                              j++) {
 504                                 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
 505
 506                                 enc_obj_id =
 507                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 508                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 509                                 enc_obj_num =
 510                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 511                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 512                                 enc_obj_type =
 513                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 514                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 515
 516                                 /* FIXME: add support for router objects */
 517                                 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 518                                         if (enc_obj_num == 2)
 519                                                 linkb = true;
 520                                         else
 521                                                 linkb = false;
 522
 523                                         radeon_add_atom_encoder(dev,
 524                                                                 enc_obj_id,
 525                                                                 le16_to_cpu
 526                                                                 (path->
 527                                                                  usDeviceTag));
 528
 529                                 }
 530                         }
 531
 532                         /* look up gpio for ddc, hpd */
 533                         ddc_bus.valid = false;
 534                         hpd.hpd = RADEON_HPD_NONE;
 535                         if ((le16_to_cpu(path->usDeviceTag) &
 536                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 537                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 538                                         if (le16_to_cpu(path->usConnObjectId) ==
 539                                             le16_to_cpu(con_obj->asObjects[j].
 540                                                         usObjectID)) {
 541                                                 ATOM_COMMON_RECORD_HEADER
 542                                                     *record =
 543                                                     (ATOM_COMMON_RECORD_HEADER
 544                                                      *)
 545                                                     (ctx->bios + data_offset +
 546                                                      le16_to_cpu(con_obj->
 547                                                                  asObjects[j].
 548                                                                  usRecordOffset));
 549                                                 ATOM_I2C_RECORD *i2c_record;
 550                                                 ATOM_HPD_INT_RECORD *hpd_record;
 551                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 552
 553                                                 while (record->ucRecordType > 0
 554                                                        && record->
 555                                                        ucRecordType <=
 556                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 557                                                         switch (record->ucRecordType) {
 558                                                         case ATOM_I2C_RECORD_TYPE:
 559                                                                 i2c_record =
 560                                                                     (ATOM_I2C_RECORD *)
 561                                                                         record;
 562                                                                 i2c_config =
 563                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 564                                                                         &i2c_record->sucI2cId;
 565                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 566                                                                                                  i2c_config->
 567                                                                                                  ucAccess);
 568                                                                 break;
 569                                                         case ATOM_HPD_INT_RECORD_TYPE:
 570                                                                 hpd_record =
 571                                                                         (ATOM_HPD_INT_RECORD *)
 572                                                                         record;
 573                                                                 gpio = radeon_lookup_gpio(rdev,
 574                                                                                           hpd_record->ucHPDIntGPIOID);
 575                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 576                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 577                                                                 break;
 578                                                         }
 579                                                         record =
 580                                                             (ATOM_COMMON_RECORD_HEADER
 581                                                              *) ((char *)record
 582                                                                  +
 583                                                                  record->
 584                                                                  ucRecordSize);
 585                                                 }
 586                                                 break;
 587                                         }
 588                                 }
 589                         }
 590
 591                         /* needed for aux chan transactions */
 592                         ddc_bus.hpd = hpd.hpd;
 593
 594                         conn_id = le16_to_cpu(path->usConnObjectId);
 595
 596                         if (!radeon_atom_apply_quirks
 597                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 598                              &ddc_bus, &conn_id, &hpd))
 599                                 continue;
 600
 601                         radeon_add_atom_connector(dev,
 602                                                   conn_id,
 603                                                   le16_to_cpu(path->
 604                                                               usDeviceTag),
 605                                                   connector_type, &ddc_bus,
 606                                                   linkb, igp_lane_info,
 607                                                   connector_object_id,
 608                                                   &hpd);
 609
 610                 }
 611         }
 612
 613         radeon_link_encoder_connector(dev);
 614
 615         return true;
 616 }
 617
 618 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 619                                                  int connector_type,
 620                                                  uint16_t devices)
 621 {
 622         struct radeon_device *rdev = dev->dev_private;
 623
 624         if (rdev->flags & RADEON_IS_IGP) {
 625                 return supported_devices_connector_object_id_convert
 626                         [connector_type];
 627         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 628                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 629                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 630                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 631                 struct atom_context *ctx = mode_info->atom_context;
 632                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 633                 uint16_t size, data_offset;
 634                 uint8_t frev, crev;
 635                 ATOM_XTMDS_INFO *xtmds;
 636
 637                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 638                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 639
 640                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 641                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 642                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 643                                 else
 644                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 645                         } else {
 646                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 647                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 648                                 else
 649                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 650                         }
 651                 } else
 652                         return supported_devices_connector_object_id_convert
 653                                 [connector_type];
 654         } else {
 655                 return supported_devices_connector_object_id_convert
 656                         [connector_type];
 657         }
 658 }
 659
 660 struct bios_connector {
 661         bool valid;
 662         uint16_t line_mux;
 663         uint16_t devices;
 664         int connector_type;
 665         struct radeon_i2c_bus_rec ddc_bus;
 666         struct radeon_hpd hpd;
 667 };
 668
 669 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 670                                                                  drm_device
 671                                                                  *dev)
 672 {
 673         struct radeon_device *rdev = dev->dev_private;
 674         struct radeon_mode_info *mode_info = &rdev->mode_info;
 675         struct atom_context *ctx = mode_info->atom_context;
 676         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 677         uint16_t size, data_offset;
 678         uint8_t frev, crev;
 679         uint16_t device_support;
 680         uint8_t dac;
 681         union atom_supported_devices *supported_devices;
 682         int i, j, max_device;
 683         struct bios_connector *bios_connectors;
 684         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 685
 686         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 687         if (!bios_connectors)
 688                 return false;
 689
 690         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 691                                     &data_offset)) {
 692                 kfree(bios_connectors);
 693                 return false;
 694         }
 695
 696         supported_devices =
 697             (union atom_supported_devices *)(ctx->bios + data_offset);
 698
 699         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 700
 701         if (frev > 1)
 702                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 703         else
 704                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 705
 706         for (i = 0; i < max_device; i++) {
 707                 ATOM_CONNECTOR_INFO_I2C ci =
 708                     supported_devices->info.asConnInfo[i];
 709
 710                 bios_connectors[i].valid = false;
 711
 712                 if (!(device_support & (1 << i))) {
 713                         continue;
 714                 }
 715
 716                 if (i == ATOM_DEVICE_CV_INDEX) {
 717                         DRM_DEBUG("Skipping Component Video\n");
 718                         continue;
 719                 }
 720
 721                 bios_connectors[i].connector_type =
 722                     supported_devices_connector_convert[ci.sucConnectorInfo.
 723                                                         sbfAccess.
 724                                                         bfConnectorType];
 725
 726                 if (bios_connectors[i].connector_type ==
 727                     DRM_MODE_CONNECTOR_Unknown)
 728                         continue;
 729
 730                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 731
 732                 bios_connectors[i].line_mux =
 733                         ci.sucI2cId.ucAccess;
 734
 735                 /* give tv unique connector ids */
 736                 if (i == ATOM_DEVICE_TV1_INDEX) {
 737                         bios_connectors[i].ddc_bus.valid = false;
 738                         bios_connectors[i].line_mux = 50;
 739                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 740                         bios_connectors[i].ddc_bus.valid = false;
 741                         bios_connectors[i].line_mux = 51;
 742                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 743                         bios_connectors[i].ddc_bus.valid = false;
 744                         bios_connectors[i].line_mux = 52;
 745                 } else
 746                         bios_connectors[i].ddc_bus =
 747                             radeon_lookup_i2c_gpio(rdev,
 748                                                    bios_connectors[i].line_mux);
 749
 750                 if ((crev > 1) && (frev > 1)) {
 751                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 752                         switch (isb) {
 753                         case 0x4:
 754                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 755                                 break;
 756                         case 0xa:
 757                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 758                                 break;
 759                         default:
 760                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 761                                 break;
 762                         }
 763                 } else {
 764                         if (i == ATOM_DEVICE_DFP1_INDEX)
 765                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 766                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 767                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 768                         else
 769                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 770                 }
 771
 772                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 773                  * shared with a DVI port, we'll pick up the DVI connector when we
 774                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 775                  */
 776                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 777                         bios_connectors[i].connector_type =
 778                             DRM_MODE_CONNECTOR_VGA;
 779
 780                 if (!radeon_atom_apply_quirks
 781                     (dev, (1 << i), &bios_connectors[i].connector_type,
 782                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 783                      &bios_connectors[i].hpd))
 784                         continue;
 785
 786                 bios_connectors[i].valid = true;
 787                 bios_connectors[i].devices = (1 << i);
 788
 789                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
 790                         radeon_add_atom_encoder(dev,
 791                                                 radeon_get_encoder_id(dev,
 792                                                                       (1 << i),
 793                                                                       dac),
 794                                                 (1 << i));
 795                 else
 796                         radeon_add_legacy_encoder(dev,
 797                                                   radeon_get_encoder_id(dev,
 798                                                                         (1 << i),
 799                                                                         dac),
 800                                                   (1 << i));
 801         }
 802
 803         /* combine shared connectors */
 804         for (i = 0; i < max_device; i++) {
 805                 if (bios_connectors[i].valid) {
 806                         for (j = 0; j < max_device; j++) {
 807                                 if (bios_connectors[j].valid && (i != j)) {
 808                                         if (bios_connectors[i].line_mux ==
 809                                             bios_connectors[j].line_mux) {
 810                                                 /* make sure not to combine LVDS */
 811                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 812                                                         bios_connectors[i].line_mux = 53;
 813                                                         bios_connectors[i].ddc_bus.valid = false;
 814                                                         continue;
 815                                                 }
 816                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 817                                                         bios_connectors[j].line_mux = 53;
 818                                                         bios_connectors[j].ddc_bus.valid = false;
 819                                                         continue;
 820                                                 }
 821                                                 /* combine analog and digital for DVI-I */
 822                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 823                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
 824                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
 825                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
 826                                                         bios_connectors[i].devices |=
 827                                                                 bios_connectors[j].devices;
 828                                                         bios_connectors[i].connector_type =
 829                                                                 DRM_MODE_CONNECTOR_DVII;
 830                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
 831                                                                 bios_connectors[i].hpd =
 832                                                                         bios_connectors[j].hpd;
 833                                                         bios_connectors[j].valid = false;
 834                                                 }
 835                                         }
 836                                 }
 837                         }
 838                 }
 839         }
 840
 841         /* add the connectors */
 842         for (i = 0; i < max_device; i++) {
 843                 if (bios_connectors[i].valid) {
 844                         uint16_t connector_object_id =
 845                                 atombios_get_connector_object_id(dev,
 846                                                       bios_connectors[i].connector_type,
 847                                                       bios_connectors[i].devices);
 848                         radeon_add_atom_connector(dev,
 849                                                   bios_connectors[i].line_mux,
 850                                                   bios_connectors[i].devices,
 851                                                   bios_connectors[i].
 852                                                   connector_type,
 853                                                   &bios_connectors[i].ddc_bus,
 854                                                   false, 0,
 855                                                   connector_object_id,
 856                                                   &bios_connectors[i].hpd);
 857                 }
 858         }
 859
 860         radeon_link_encoder_connector(dev);
 861
 862         kfree(bios_connectors);
 863         return true;
 864 }
 865
 866 union firmware_info {
 867         ATOM_FIRMWARE_INFO info;
 868         ATOM_FIRMWARE_INFO_V1_2 info_12;
 869         ATOM_FIRMWARE_INFO_V1_3 info_13;
 870         ATOM_FIRMWARE_INFO_V1_4 info_14;
 871         ATOM_FIRMWARE_INFO_V2_1 info_21;
 872 };
 873
 874 bool radeon_atom_get_clock_info(struct drm_device *dev)
 875 {
 876         struct radeon_device *rdev = dev->dev_private;
 877         struct radeon_mode_info *mode_info = &rdev->mode_info;
 878         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 879         union firmware_info *firmware_info;
 880         uint8_t frev, crev;
 881         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 882         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 883         struct radeon_pll *dcpll = &rdev->clock.dcpll;
 884         struct radeon_pll *spll = &rdev->clock.spll;
 885         struct radeon_pll *mpll = &rdev->clock.mpll;
 886         uint16_t data_offset;
 887
 888         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
 889                                    &frev, &crev, &data_offset)) {
 890                 firmware_info =
 891                         (union firmware_info *)(mode_info->atom_context->bios +
 892                                                 data_offset);
 893                 /* pixel clocks */
 894                 p1pll->reference_freq =
 895                     le16_to_cpu(firmware_info->info.usReferenceClock);
 896                 p1pll->reference_div = 0;
 897
 898                 if (crev < 2)
 899                         p1pll->pll_out_min =
 900                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
 901                 else
 902                         p1pll->pll_out_min =
 903                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 904                 p1pll->pll_out_max =
 905                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 906
 907                 if (crev >= 4) {
 908                         p1pll->lcd_pll_out_min =
 909                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 910                         if (p1pll->lcd_pll_out_min == 0)
 911                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 912                         p1pll->lcd_pll_out_max =
 913                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 914                         if (p1pll->lcd_pll_out_max == 0)
 915                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 916                 } else {
 917                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 918                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 919                 }
 920
 921                 if (p1pll->pll_out_min == 0) {
 922                         if (ASIC_IS_AVIVO(rdev))
 923                                 p1pll->pll_out_min = 64800;
 924                         else
 925                                 p1pll->pll_out_min = 20000;
 926                 } else if (p1pll->pll_out_min > 64800) {
 927                         /* Limiting the pll output range is a good thing generally as
 928                          * it limits the number of possible pll combinations for a given
 929                          * frequency presumably to the ones that work best on each card.
 930                          * However, certain duallink DVI monitors seem to like
 931                          * pll combinations that would be limited by this at least on
 932                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
 933                          * family.
 934                          */
 935                         if (!radeon_new_pll)
 936                                 p1pll->pll_out_min = 64800;
 937                 }
 938
 939                 p1pll->pll_in_min =
 940                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 941                 p1pll->pll_in_max =
 942                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 943
 944                 *p2pll = *p1pll;
 945
 946                 /* system clock */
 947                 spll->reference_freq =
 948                     le16_to_cpu(firmware_info->info.usReferenceClock);
 949                 spll->reference_div = 0;
 950
 951                 spll->pll_out_min =
 952                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 953                 spll->pll_out_max =
 954                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 955
 956                 /* ??? */
 957                 if (spll->pll_out_min == 0) {
 958                         if (ASIC_IS_AVIVO(rdev))
 959                                 spll->pll_out_min = 64800;
 960                         else
 961                                 spll->pll_out_min = 20000;
 962                 }
 963
 964                 spll->pll_in_min =
 965                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 966                 spll->pll_in_max =
 967                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 968
 969                 /* memory clock */
 970                 mpll->reference_freq =
 971                     le16_to_cpu(firmware_info->info.usReferenceClock);
 972                 mpll->reference_div = 0;
 973
 974                 mpll->pll_out_min =
 975                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 976                 mpll->pll_out_max =
 977                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 978
 979                 /* ??? */
 980                 if (mpll->pll_out_min == 0) {
 981                         if (ASIC_IS_AVIVO(rdev))
 982                                 mpll->pll_out_min = 64800;
 983                         else
 984                                 mpll->pll_out_min = 20000;
 985                 }
 986
 987                 mpll->pll_in_min =
 988                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 989                 mpll->pll_in_max =
 990                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 991
 992                 rdev->clock.default_sclk =
 993                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 994                 rdev->clock.default_mclk =
 995                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 996
 997                 if (ASIC_IS_DCE4(rdev)) {
 998                         rdev->clock.default_dispclk =
 999                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1000                         if (rdev->clock.default_dispclk == 0)
1001                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1002                         rdev->clock.dp_extclk =
1003                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1004                 }
1005                 *dcpll = *p1pll;
1006
1007                 return true;
1008         }
1009
1010         return false;
1011 }
1012
1013 union igp_info {
1014         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1015         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1016 };
1017
1018 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1019 {
1020         struct radeon_mode_info *mode_info = &rdev->mode_info;
1021         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1022         union igp_info *igp_info;
1023         u8 frev, crev;
1024         u16 data_offset;
1025
1026         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1027                                    &frev, &crev, &data_offset)) {
1028                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1029                                       data_offset);
1030                 switch (crev) {
1031                 case 1:
1032                         /* AMD IGPS */
1033                         if ((rdev->family == CHIP_RS690) ||
1034                             (rdev->family == CHIP_RS740)) {
1035                                 if (igp_info->info.ulBootUpMemoryClock)
1036                                         return true;
1037                         } else {
1038                                 if (igp_info->info.ucMemoryType & 0xf0)
1039                                         return true;
1040                         }
1041                         break;
1042                 case 2:
1043                         if (igp_info->info_2.ucMemoryType & 0x0f)
1044                                 return true;
1045                         break;
1046                 default:
1047                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1048                         break;
1049                 }
1050         }
1051         return false;
1052 }
1053
1054 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1055                                    struct radeon_encoder_int_tmds *tmds)
1056 {
1057         struct drm_device *dev = encoder->base.dev;
1058         struct radeon_device *rdev = dev->dev_private;
1059         struct radeon_mode_info *mode_info = &rdev->mode_info;
1060         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1061         uint16_t data_offset;
1062         struct _ATOM_TMDS_INFO *tmds_info;
1063         uint8_t frev, crev;
1064         uint16_t maxfreq;
1065         int i;
1066
1067         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1068                                    &frev, &crev, &data_offset)) {
1069                 tmds_info =
1070                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1071                                                    data_offset);
1072
1073                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1074                 for (i = 0; i < 4; i++) {
1075                         tmds->tmds_pll[i].freq =
1076                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1077                         tmds->tmds_pll[i].value =
1078                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1079                         tmds->tmds_pll[i].value |=
1080                             (tmds_info->asMiscInfo[i].
1081                              ucPLL_VCO_Gain & 0x3f) << 6;
1082                         tmds->tmds_pll[i].value |=
1083                             (tmds_info->asMiscInfo[i].
1084                              ucPLL_DutyCycle & 0xf) << 12;
1085                         tmds->tmds_pll[i].value |=
1086                             (tmds_info->asMiscInfo[i].
1087                              ucPLL_VoltageSwing & 0xf) << 16;
1088
1089                         DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1090                                   tmds->tmds_pll[i].freq,
1091                                   tmds->tmds_pll[i].value);
1092
1093                         if (maxfreq == tmds->tmds_pll[i].freq) {
1094                                 tmds->tmds_pll[i].freq = 0xffffffff;
1095                                 break;
1096                         }
1097                 }
1098                 return true;
1099         }
1100         return false;
1101 }
1102
1103 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1104                                                           radeon_encoder
1105                                                           *encoder,
1106                                                           int id)
1107 {
1108         struct drm_device *dev = encoder->base.dev;
1109         struct radeon_device *rdev = dev->dev_private;
1110         struct radeon_mode_info *mode_info = &rdev->mode_info;
1111         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1112         uint16_t data_offset;
1113         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1114         uint8_t frev, crev;
1115         struct radeon_atom_ss *ss = NULL;
1116         int i;
1117
1118         if (id > ATOM_MAX_SS_ENTRY)
1119                 return NULL;
1120
1121         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1122                                    &frev, &crev, &data_offset)) {
1123                 ss_info =
1124                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1125
1126                 ss =
1127                     kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1128
1129                 if (!ss)
1130                         return NULL;
1131
1132                 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1133                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1134                                 ss->percentage =
1135                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1136                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1137                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1138                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1139                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1140                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1141                                 break;
1142                         }
1143                 }
1144         }
1145         return ss;
1146 }
1147
1148 union lvds_info {
1149         struct _ATOM_LVDS_INFO info;
1150         struct _ATOM_LVDS_INFO_V12 info_12;
1151 };
1152
1153 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1154                                                               radeon_encoder
1155                                                               *encoder)
1156 {
1157         struct drm_device *dev = encoder->base.dev;
1158         struct radeon_device *rdev = dev->dev_private;
1159         struct radeon_mode_info *mode_info = &rdev->mode_info;
1160         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1161         uint16_t data_offset, misc;
1162         union lvds_info *lvds_info;
1163         uint8_t frev, crev;
1164         struct radeon_encoder_atom_dig *lvds = NULL;
1165
1166         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1167                                    &frev, &crev, &data_offset)) {
1168                 lvds_info =
1169                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1170                 lvds =
1171                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1172
1173                 if (!lvds)
1174                         return NULL;
1175
1176                 lvds->native_mode.clock =
1177                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1178                 lvds->native_mode.hdisplay =
1179                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1180                 lvds->native_mode.vdisplay =
1181                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1182                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1183                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1184                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1185                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1186                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1187                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1188                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1189                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1190                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1191                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1192                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1193                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1194                 lvds->panel_pwr_delay =
1195                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1196                 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1197
1198                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1199                 if (misc & ATOM_VSYNC_POLARITY)
1200                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1201                 if (misc & ATOM_HSYNC_POLARITY)
1202                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1203                 if (misc & ATOM_COMPOSITESYNC)
1204                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1205                 if (misc & ATOM_INTERLACE)
1206                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1207                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1208                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1209
1210                 /* set crtc values */
1211                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1212
1213                 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1214
1215                 if (ASIC_IS_AVIVO(rdev)) {
1216                         if (radeon_new_pll == 0)
1217                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1218                         else
1219                                 lvds->pll_algo = PLL_ALGO_NEW;
1220                 } else {
1221                         if (radeon_new_pll == 1)
1222                                 lvds->pll_algo = PLL_ALGO_NEW;
1223                         else
1224                                 lvds->pll_algo = PLL_ALGO_LEGACY;
1225                 }
1226
1227                 encoder->native_mode = lvds->native_mode;
1228         }
1229         return lvds;
1230 }
1231
1232 struct radeon_encoder_primary_dac *
1233 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1234 {
1235         struct drm_device *dev = encoder->base.dev;
1236         struct radeon_device *rdev = dev->dev_private;
1237         struct radeon_mode_info *mode_info = &rdev->mode_info;
1238         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1239         uint16_t data_offset;
1240         struct _COMPASSIONATE_DATA *dac_info;
1241         uint8_t frev, crev;
1242         uint8_t bg, dac;
1243         struct radeon_encoder_primary_dac *p_dac = NULL;
1244
1245         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1246                                    &frev, &crev, &data_offset)) {
1247                 dac_info = (struct _COMPASSIONATE_DATA *)
1248                         (mode_info->atom_context->bios + data_offset);
1249
1250                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1251
1252                 if (!p_dac)
1253                         return NULL;
1254
1255                 bg = dac_info->ucDAC1_BG_Adjustment;
1256                 dac = dac_info->ucDAC1_DAC_Adjustment;
1257                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1258
1259         }
1260         return p_dac;
1261 }
1262
1263 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1264                                 struct drm_display_mode *mode)
1265 {
1266         struct radeon_mode_info *mode_info = &rdev->mode_info;
1267         ATOM_ANALOG_TV_INFO *tv_info;
1268         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1269         ATOM_DTD_FORMAT *dtd_timings;
1270         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1271         u8 frev, crev;
1272         u16 data_offset, misc;
1273
1274         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1275                                     &frev, &crev, &data_offset))
1276                 return false;
1277
1278         switch (crev) {
1279         case 1:
1280                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1281                 if (index >= MAX_SUPPORTED_TV_TIMING)
1282                         return false;
1283
1284                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1285                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1286                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1287                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1288                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1289
1290                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1291                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1292                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1293                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1294                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1295
1296                 mode->flags = 0;
1297                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1298                 if (misc & ATOM_VSYNC_POLARITY)
1299                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1300                 if (misc & ATOM_HSYNC_POLARITY)
1301                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1302                 if (misc & ATOM_COMPOSITESYNC)
1303                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1304                 if (misc & ATOM_INTERLACE)
1305                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1306                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1307                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1308
1309                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1310
1311                 if (index == 1) {
1312                         /* PAL timings appear to have wrong values for totals */
1313                         mode->crtc_htotal -= 1;
1314                         mode->crtc_vtotal -= 1;
1315                 }
1316                 break;
1317         case 2:
1318                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1319                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1320                         return false;
1321
1322                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1323                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1324                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1325                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1326                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1327                         le16_to_cpu(dtd_timings->usHSyncOffset);
1328                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1329                         le16_to_cpu(dtd_timings->usHSyncWidth);
1330
1331                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1332                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1333                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1334                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1335                         le16_to_cpu(dtd_timings->usVSyncOffset);
1336                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1337                         le16_to_cpu(dtd_timings->usVSyncWidth);
1338
1339                 mode->flags = 0;
1340                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1341                 if (misc & ATOM_VSYNC_POLARITY)
1342                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1343                 if (misc & ATOM_HSYNC_POLARITY)
1344                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1345                 if (misc & ATOM_COMPOSITESYNC)
1346                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1347                 if (misc & ATOM_INTERLACE)
1348                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1349                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1350                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1351
1352                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1353                 break;
1354         }
1355         return true;
1356 }
1357
1358 enum radeon_tv_std
1359 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1360 {
1361         struct radeon_mode_info *mode_info = &rdev->mode_info;
1362         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1363         uint16_t data_offset;
1364         uint8_t frev, crev;
1365         struct _ATOM_ANALOG_TV_INFO *tv_info;
1366         enum radeon_tv_std tv_std = TV_STD_NTSC;
1367
1368         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1369                                    &frev, &crev, &data_offset)) {
1370
1371                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1372                         (mode_info->atom_context->bios + data_offset);
1373
1374                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1375                 case ATOM_TV_NTSC:
1376                         tv_std = TV_STD_NTSC;
1377                         DRM_INFO("Default TV standard: NTSC\n");
1378                         break;
1379                 case ATOM_TV_NTSCJ:
1380                         tv_std = TV_STD_NTSC_J;
1381                         DRM_INFO("Default TV standard: NTSC-J\n");
1382                         break;
1383                 case ATOM_TV_PAL:
1384                         tv_std = TV_STD_PAL;
1385                         DRM_INFO("Default TV standard: PAL\n");
1386                         break;
1387                 case ATOM_TV_PALM:
1388                         tv_std = TV_STD_PAL_M;
1389                         DRM_INFO("Default TV standard: PAL-M\n");
1390                         break;
1391                 case ATOM_TV_PALN:
1392                         tv_std = TV_STD_PAL_N;
1393                         DRM_INFO("Default TV standard: PAL-N\n");
1394                         break;
1395                 case ATOM_TV_PALCN:
1396                         tv_std = TV_STD_PAL_CN;
1397                         DRM_INFO("Default TV standard: PAL-CN\n");
1398                         break;
1399                 case ATOM_TV_PAL60:
1400                         tv_std = TV_STD_PAL_60;
1401                         DRM_INFO("Default TV standard: PAL-60\n");
1402                         break;
1403                 case ATOM_TV_SECAM:
1404                         tv_std = TV_STD_SECAM;
1405                         DRM_INFO("Default TV standard: SECAM\n");
1406                         break;
1407                 default:
1408                         tv_std = TV_STD_NTSC;
1409                         DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1410                         break;
1411                 }
1412         }
1413         return tv_std;
1414 }
1415
1416 struct radeon_encoder_tv_dac *
1417 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1418 {
1419         struct drm_device *dev = encoder->base.dev;
1420         struct radeon_device *rdev = dev->dev_private;
1421         struct radeon_mode_info *mode_info = &rdev->mode_info;
1422         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1423         uint16_t data_offset;
1424         struct _COMPASSIONATE_DATA *dac_info;
1425         uint8_t frev, crev;
1426         uint8_t bg, dac;
1427         struct radeon_encoder_tv_dac *tv_dac = NULL;
1428
1429         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1430                                    &frev, &crev, &data_offset)) {
1431
1432                 dac_info = (struct _COMPASSIONATE_DATA *)
1433                         (mode_info->atom_context->bios + data_offset);
1434
1435                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1436
1437                 if (!tv_dac)
1438                         return NULL;
1439
1440                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1441                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1442                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1443
1444                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1445                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1446                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1447
1448                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1449                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1450                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1451
1452                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1453         }
1454         return tv_dac;
1455 }
1456
1457 static const char *thermal_controller_names[] = {
1458         "NONE",
1459         "lm63",
1460         "adm1032",
1461         "adm1030",
1462         "max6649",
1463         "lm64",
1464         "f75375",
1465         "asc7xxx",
1466 };
1467
1468 static const char *pp_lib_thermal_controller_names[] = {
1469         "NONE",
1470         "lm63",
1471         "adm1032",
1472         "adm1030",
1473         "max6649",
1474         "lm64",
1475         "f75375",
1476         "RV6xx",
1477         "RV770",
1478         "adt7473",
1479         "External GPIO",
1480         "Evergreen",
1481         "adt7473 with internal",
1482
1483 };
1484
1485 union power_info {
1486         struct _ATOM_POWERPLAY_INFO info;
1487         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1488         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1489         struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1490 };
1491
1492 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1493 {
1494         struct radeon_mode_info *mode_info = &rdev->mode_info;
1495         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1496         u16 data_offset;
1497         u8 frev, crev;
1498         u32 misc, misc2 = 0, sclk, mclk;
1499         union power_info *power_info;
1500         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1501         struct _ATOM_PPLIB_STATE *power_state;
1502         int num_modes = 0, i, j;
1503         int state_index = 0, mode_index = 0;
1504         struct radeon_i2c_bus_rec i2c_bus;
1505
1506         rdev->pm.default_power_state_index = -1;
1507
1508         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1509                                    &frev, &crev, &data_offset)) {
1510                 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1511                 if (frev < 4) {
1512                         /* add the i2c bus for thermal/fan chip */
1513                         if (power_info->info.ucOverdriveThermalController > 0) {
1514                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1515                                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1516                                          power_info->info.ucOverdriveControllerAddress >> 1);
1517                                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1518                                 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1519                                 if (rdev->pm.i2c_bus) {
1520                                         struct i2c_board_info info = { };
1521                                         const char *name = thermal_controller_names[power_info->info.
1522                                                                                     ucOverdriveThermalController];
1523                                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1524                                         strlcpy(info.type, name, sizeof(info.type));
1525                                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1526                                 }
1527                         }
1528                         num_modes = power_info->info.ucNumOfPowerModeEntries;
1529                         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1530                                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1531                         /* last mode is usually default, array is low to high */
1532                         for (i = 0; i < num_modes; i++) {
1533                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1534                                 switch (frev) {
1535                                 case 1:
1536                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1537                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1538                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1539                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1540                                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1541                                         /* skip invalid modes */
1542                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1543                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1544                                                 continue;
1545                                         rdev->pm.power_state[state_index].pcie_lanes =
1546                                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1547                                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1548                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1549                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1550                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1551                                                         VOLTAGE_GPIO;
1552                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1553                                                         radeon_lookup_gpio(rdev,
1554                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1555                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1556                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1557                                                                 true;
1558                                                 else
1559                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1560                                                                 false;
1561                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1562                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1563                                                         VOLTAGE_VDDC;
1564                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1565                                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1566                                         }
1567                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1568                                         rdev->pm.power_state[state_index].misc = misc;
1569                                         /* order matters! */
1570                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1571                                                 rdev->pm.power_state[state_index].type =
1572                                                         POWER_STATE_TYPE_POWERSAVE;
1573                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1574                                                 rdev->pm.power_state[state_index].type =
1575                                                         POWER_STATE_TYPE_BATTERY;
1576                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1577                                                 rdev->pm.power_state[state_index].type =
1578                                                         POWER_STATE_TYPE_BATTERY;
1579                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1580                                                 rdev->pm.power_state[state_index].type =
1581                                                         POWER_STATE_TYPE_BALANCED;
1582                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1583                                                 rdev->pm.power_state[state_index].type =
1584                                                         POWER_STATE_TYPE_PERFORMANCE;
1585                                                 rdev->pm.power_state[state_index].flags &=
1586                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1587                                         }
1588                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1589                                                 rdev->pm.power_state[state_index].type =
1590                                                         POWER_STATE_TYPE_DEFAULT;
1591                                                 rdev->pm.default_power_state_index = state_index;
1592                                                 rdev->pm.power_state[state_index].default_clock_mode =
1593                                                         &rdev->pm.power_state[state_index].clock_info[0];
1594                                                 rdev->pm.power_state[state_index].flags &=
1595                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1596                                         } else if (state_index == 0) {
1597                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1598                                                         RADEON_PM_MODE_NO_DISPLAY;
1599                                         }
1600                                         state_index++;
1601                                         break;
1602                                 case 2:
1603                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1604                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1605                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1606                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1607                                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1608                                         /* skip invalid modes */
1609                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1610                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1611                                                 continue;
1612                                         rdev->pm.power_state[state_index].pcie_lanes =
1613                                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1614                                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1615                                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1616                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1617                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1618                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1619                                                         VOLTAGE_GPIO;
1620                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1621                                                         radeon_lookup_gpio(rdev,
1622                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1623                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1624                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1625                                                                 true;
1626                                                 else
1627                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1628                                                                 false;
1629                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1630                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1631                                                         VOLTAGE_VDDC;
1632                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1633                                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1634                                         }
1635                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1636                                         rdev->pm.power_state[state_index].misc = misc;
1637                                         rdev->pm.power_state[state_index].misc2 = misc2;
1638                                         /* order matters! */
1639                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1640                                                 rdev->pm.power_state[state_index].type =
1641                                                         POWER_STATE_TYPE_POWERSAVE;
1642                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1643                                                 rdev->pm.power_state[state_index].type =
1644                                                         POWER_STATE_TYPE_BATTERY;
1645                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1646                                                 rdev->pm.power_state[state_index].type =
1647                                                         POWER_STATE_TYPE_BATTERY;
1648                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1649                                                 rdev->pm.power_state[state_index].type =
1650                                                         POWER_STATE_TYPE_BALANCED;
1651                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1652                                                 rdev->pm.power_state[state_index].type =
1653                                                         POWER_STATE_TYPE_PERFORMANCE;
1654                                                 rdev->pm.power_state[state_index].flags &=
1655                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1656                                         }
1657                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1658                                                 rdev->pm.power_state[state_index].type =
1659                                                         POWER_STATE_TYPE_BALANCED;
1660                                         if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1661                                                 rdev->pm.power_state[state_index].flags &=
1662                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1663                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1664                                                 rdev->pm.power_state[state_index].type =
1665                                                         POWER_STATE_TYPE_DEFAULT;
1666                                                 rdev->pm.default_power_state_index = state_index;
1667                                                 rdev->pm.power_state[state_index].default_clock_mode =
1668                                                         &rdev->pm.power_state[state_index].clock_info[0];
1669                                                 rdev->pm.power_state[state_index].flags &=
1670                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1671                                         } else if (state_index == 0) {
1672                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1673                                                         RADEON_PM_MODE_NO_DISPLAY;
1674                                         }
1675                                         state_index++;
1676                                         break;
1677                                 case 3:
1678                                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1679                                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1680                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1681                                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1682                                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1683                                         /* skip invalid modes */
1684                                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1685                                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1686                                                 continue;
1687                                         rdev->pm.power_state[state_index].pcie_lanes =
1688                                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1689                                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1690                                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1691                                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1692                                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1693                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1694                                                         VOLTAGE_GPIO;
1695                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1696                                                         radeon_lookup_gpio(rdev,
1697                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1698                                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1699                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1700                                                                 true;
1701                                                 else
1702                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1703                                                                 false;
1704                                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1705                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1706                                                         VOLTAGE_VDDC;
1707                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1708                                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1709                                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1710                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1711                                                                 true;
1712                                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1713                                                         power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1714                                                 }
1715                                         }
1716                                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1717                                         rdev->pm.power_state[state_index].misc = misc;
1718                                         rdev->pm.power_state[state_index].misc2 = misc2;
1719                                         /* order matters! */
1720                                         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1721                                                 rdev->pm.power_state[state_index].type =
1722                                                         POWER_STATE_TYPE_POWERSAVE;
1723                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1724                                                 rdev->pm.power_state[state_index].type =
1725                                                         POWER_STATE_TYPE_BATTERY;
1726                                         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1727                                                 rdev->pm.power_state[state_index].type =
1728                                                         POWER_STATE_TYPE_BATTERY;
1729                                         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1730                                                 rdev->pm.power_state[state_index].type =
1731                                                         POWER_STATE_TYPE_BALANCED;
1732                                         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1733                                                 rdev->pm.power_state[state_index].type =
1734                                                         POWER_STATE_TYPE_PERFORMANCE;
1735                                                 rdev->pm.power_state[state_index].flags &=
1736                                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1737                                         }
1738                                         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1739                                                 rdev->pm.power_state[state_index].type =
1740                                                         POWER_STATE_TYPE_BALANCED;
1741                                         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1742                                                 rdev->pm.power_state[state_index].type =
1743                                                         POWER_STATE_TYPE_DEFAULT;
1744                                                 rdev->pm.default_power_state_index = state_index;
1745                                                 rdev->pm.power_state[state_index].default_clock_mode =
1746                                                         &rdev->pm.power_state[state_index].clock_info[0];
1747                                         } else if (state_index == 0) {
1748                                                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1749                                                         RADEON_PM_MODE_NO_DISPLAY;
1750                                         }
1751                                         state_index++;
1752                                         break;
1753                                 }
1754                         }
1755                         /* last mode is usually default */
1756                         if (rdev->pm.default_power_state_index == -1) {
1757                                 rdev->pm.power_state[state_index - 1].type =
1758                                         POWER_STATE_TYPE_DEFAULT;
1759                                 rdev->pm.default_power_state_index = state_index - 1;
1760                                 rdev->pm.power_state[state_index - 1].default_clock_mode =
1761                                         &rdev->pm.power_state[state_index - 1].clock_info[0];
1762                                 rdev->pm.power_state[state_index].flags &=
1763                                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1764                                 rdev->pm.power_state[state_index].misc = 0;
1765                                 rdev->pm.power_state[state_index].misc2 = 0;
1766                         }
1767                 } else {
1768                         int fw_index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1769                         uint8_t fw_frev, fw_crev;
1770                         uint16_t fw_data_offset, vddc = 0;
1771                         union firmware_info *firmware_info;
1772                         ATOM_PPLIB_THERMALCONTROLLER *controller = &power_info->info_4.sThermalController;
1773
1774                         if (atom_parse_data_header(mode_info->atom_context, fw_index, NULL,
1775                                                    &fw_frev, &fw_crev, &fw_data_offset)) {
1776                                 firmware_info =
1777                                         (union firmware_info *)(mode_info->atom_context->bios +
1778                                                                 fw_data_offset);
1779                                 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
1780                         }
1781
1782                         /* add the i2c bus for thermal/fan chip */
1783                         /* no support for internal controller yet */
1784                         if (controller->ucType > 0) {
1785                                 if ((controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1786                                     (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) ||
1787                                     (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) {
1788                                         DRM_INFO("Internal thermal controller %s fan control\n",
1789                                                  (controller->ucFanParameters &
1790                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1791                                 } else if ((controller->ucType ==
1792                                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
1793                                            (controller->ucType ==
1794                                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1795                                         DRM_INFO("Special thermal controller config\n");
1796                                 } else {
1797                                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1798                                                  pp_lib_thermal_controller_names[controller->ucType],
1799                                                  controller->ucI2cAddress >> 1,
1800                                                  (controller->ucFanParameters &
1801                                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1802                                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
1803                                         rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1804                                         if (rdev->pm.i2c_bus) {
1805                                                 struct i2c_board_info info = { };
1806                                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
1807                                                 info.addr = controller->ucI2cAddress >> 1;
1808                                                 strlcpy(info.type, name, sizeof(info.type));
1809                                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1810                                         }
1811
1812                                 }
1813                         }
1814                         /* first mode is usually default, followed by low to high */
1815                         for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1816                                 mode_index = 0;
1817                                 power_state = (struct _ATOM_PPLIB_STATE *)
1818                                         (mode_info->atom_context->bios +
1819                                          data_offset +
1820                                          le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1821                                          i * power_info->info_4.ucStateEntrySize);
1822                                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1823                                         (mode_info->atom_context->bios +
1824                                          data_offset +
1825                                          le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1826                                          (power_state->ucNonClockStateIndex *
1827                                           power_info->info_4.ucNonClockSize));
1828                                 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1829                                         if (rdev->flags & RADEON_IS_IGP) {
1830                                                 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1831                                                         (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1832                                                         (mode_info->atom_context->bios +
1833                                                          data_offset +
1834                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1835                                                          (power_state->ucClockStateIndices[j] *
1836                                                           power_info->info_4.ucClockInfoSize));
1837                                                 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1838                                                 sclk |= clock_info->ucLowEngineClockHigh << 16;
1839                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1840                                                 /* skip invalid modes */
1841                                                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1842                                                         continue;
1843                                                 /* voltage works differently on IGPs */
1844                                                 mode_index++;
1845                                         } else if (ASIC_IS_DCE4(rdev)) {
1846                                                 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1847                                                         (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1848                                                         (mode_info->atom_context->bios +
1849                                                          data_offset +
1850                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1851                                                          (power_state->ucClockStateIndices[j] *
1852                                                           power_info->info_4.ucClockInfoSize));
1853                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1854                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1855                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1856                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1857                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1858                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1859                                                 /* skip invalid modes */
1860                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1861                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1862                                                         continue;
1863                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1864                                                         VOLTAGE_SW;
1865                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1866                                                         clock_info->usVDDC;
1867                                                 /* XXX usVDDCI */
1868                                                 mode_index++;
1869                                         } else {
1870                                                 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1871                                                         (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1872                                                         (mode_info->atom_context->bios +
1873                                                          data_offset +
1874                                                          le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1875                                                          (power_state->ucClockStateIndices[j] *
1876                                                           power_info->info_4.ucClockInfoSize));
1877                                                 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1878                                                 sclk |= clock_info->ucEngineClockHigh << 16;
1879                                                 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1880                                                 mclk |= clock_info->ucMemoryClockHigh << 16;
1881                                                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1882                                                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1883                                                 /* skip invalid modes */
1884                                                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1885                                                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1886                                                         continue;
1887                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1888                                                         VOLTAGE_SW;
1889                                                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1890                                                         clock_info->usVDDC;
1891                                                 mode_index++;
1892                                         }
1893                                 }
1894                                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1895                                 if (mode_index) {
1896                                         misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1897                                         misc2 = le16_to_cpu(non_clock_info->usClassification);
1898                                         rdev->pm.power_state[state_index].misc = misc;
1899                                         rdev->pm.power_state[state_index].misc2 = misc2;
1900                                         rdev->pm.power_state[state_index].pcie_lanes =
1901                                                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1902                                                 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1903                                         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1904                                         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1905                                                 rdev->pm.power_state[state_index].type =
1906                                                         POWER_STATE_TYPE_BATTERY;
1907                                                 break;
1908                                         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1909                                                 rdev->pm.power_state[state_index].type =
1910                                                         POWER_STATE_TYPE_BALANCED;
1911                                                 break;
1912                                         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1913                                                 rdev->pm.power_state[state_index].type =
1914                                                         POWER_STATE_TYPE_PERFORMANCE;
1915                                                 break;
1916                                         }
1917                                         rdev->pm.power_state[state_index].flags = 0;
1918                                         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1919                                                 rdev->pm.power_state[state_index].flags |=
1920                                                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1921                                         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1922                                                 rdev->pm.power_state[state_index].type =
1923                                                         POWER_STATE_TYPE_DEFAULT;
1924                                                 rdev->pm.default_power_state_index = state_index;
1925                                                 rdev->pm.power_state[state_index].default_clock_mode =
1926                                                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1927                                                 /* patch the table values with the default slck/mclk from firmware info */
1928                                                 for (j = 0; j < mode_index; j++) {
1929                                                         rdev->pm.power_state[state_index].clock_info[j].mclk =
1930                                                                 rdev->clock.default_mclk;
1931                                                         rdev->pm.power_state[state_index].clock_info[j].sclk =
1932                                                                 rdev->clock.default_sclk;
1933                                                         if (vddc)
1934                                                                 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
1935                                                                         vddc;
1936                                                 }
1937                                         }
1938                                         state_index++;
1939                                 }
1940                         }
1941                         /* if multiple clock modes, mark the lowest as no display */
1942                         for (i = 0; i < state_index; i++) {
1943                                 if (rdev->pm.power_state[i].num_clock_modes > 1)
1944                                         rdev->pm.power_state[i].clock_info[0].flags |=
1945                                                 RADEON_PM_MODE_NO_DISPLAY;
1946                         }
1947                         /* first mode is usually default */
1948                         if (rdev->pm.default_power_state_index == -1) {
1949                                 rdev->pm.power_state[0].type =
1950                                         POWER_STATE_TYPE_DEFAULT;
1951                                 rdev->pm.default_power_state_index = 0;
1952                                 rdev->pm.power_state[0].default_clock_mode =
1953                                         &rdev->pm.power_state[0].clock_info[0];
1954                         }
1955                 }
1956         } else {
1957                 /* add the default mode */
1958                 rdev->pm.power_state[state_index].type =
1959                         POWER_STATE_TYPE_DEFAULT;
1960                 rdev->pm.power_state[state_index].num_clock_modes = 1;
1961                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1962                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1963                 rdev->pm.power_state[state_index].default_clock_mode =
1964                         &rdev->pm.power_state[state_index].clock_info[0];
1965                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1966                 rdev->pm.power_state[state_index].pcie_lanes = 16;
1967                 rdev->pm.default_power_state_index = state_index;
1968                 rdev->pm.power_state[state_index].flags = 0;
1969                 state_index++;
1970         }
1971
1972         rdev->pm.num_power_states = state_index;
1973
1974         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1975         rdev->pm.current_clock_mode_index = 0;
1976         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1977 }
1978
1979 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1980 {
1981         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1982         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1983
1984         args.ucEnable = enable;
1985
1986         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1987 }
1988
1989 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1990 {
1991         GET_ENGINE_CLOCK_PS_ALLOCATION args;
1992         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1993
1994         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1995         return args.ulReturnEngineClock;
1996 }
1997
1998 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1999 {
2000         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2001         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2002
2003         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2004         return args.ulReturnMemoryClock;
2005 }
2006
2007 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2008                                   uint32_t eng_clock)
2009 {
2010         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2011         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2012
2013         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
2014
2015         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2016 }
2017
2018 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2019                                   uint32_t mem_clock)
2020 {
2021         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2022         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2023
2024         if (rdev->flags & RADEON_IS_IGP)
2025                 return;
2026
2027         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
2028
2029         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2030 }
2031
2032 union set_voltage {
2033         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2034         struct _SET_VOLTAGE_PARAMETERS v1;
2035         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2036 };
2037
2038 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2039 {
2040         union set_voltage args;
2041         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2042         u8 frev, crev, volt_index = level;
2043
2044         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2045                 return;
2046
2047         switch (crev) {
2048         case 1:
2049                 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2050                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2051                 args.v1.ucVoltageIndex = volt_index;
2052                 break;
2053         case 2:
2054                 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2055                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2056                 args.v2.usVoltageLevel = cpu_to_le16(level);
2057                 break;
2058         default:
2059                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2060                 return;
2061         }
2062
2063         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2064 }
2065
2066
2067
2068 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2069 {
2070         struct radeon_device *rdev = dev->dev_private;
2071         uint32_t bios_2_scratch, bios_6_scratch;
2072
2073         if (rdev->family >= CHIP_R600) {
2074                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2075                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2076         } else {
2077                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2078                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2079         }
2080
2081         /* let the bios control the backlight */
2082         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2083
2084         /* tell the bios not to handle mode switching */
2085         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2086
2087         if (rdev->family >= CHIP_R600) {
2088                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2089                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2090         } else {
2091                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2092                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2093         }
2094
2095 }
2096
2097 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2098 {
2099         uint32_t scratch_reg;
2100         int i;
2101
2102         if (rdev->family >= CHIP_R600)
2103                 scratch_reg = R600_BIOS_0_SCRATCH;
2104         else
2105                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2106
2107         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2108                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2109 }
2110
2111 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2112 {
2113         uint32_t scratch_reg;
2114         int i;
2115
2116         if (rdev->family >= CHIP_R600)
2117                 scratch_reg = R600_BIOS_0_SCRATCH;
2118         else
2119                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2120
2121         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2122                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2123 }
2124
2125 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2126 {
2127         struct drm_device *dev = encoder->dev;
2128         struct radeon_device *rdev = dev->dev_private;
2129         uint32_t bios_6_scratch;
2130
2131         if (rdev->family >= CHIP_R600)
2132                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2133         else
2134                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2135
2136         if (lock)
2137                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2138         else
2139                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2140
2141         if (rdev->family >= CHIP_R600)
2142                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2143         else
2144                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2145 }
2146
2147 /* at some point we may want to break this out into individual functions */
2148 void
2149 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2150                                        struct drm_encoder *encoder,
2151                                        bool connected)
2152 {
2153         struct drm_device *dev = connector->dev;
2154         struct radeon_device *rdev = dev->dev_private;
2155         struct radeon_connector *radeon_connector =
2156             to_radeon_connector(connector);
2157         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2158         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2159
2160         if (rdev->family >= CHIP_R600) {
2161                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2162                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2163                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2164         } else {
2165                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2166                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2167                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2168         }
2169
2170         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2171             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2172                 if (connected) {
2173                         DRM_DEBUG("TV1 connected\n");
2174                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2175                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2176                 } else {
2177                         DRM_DEBUG("TV1 disconnected\n");
2178                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2179                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2180                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2181                 }
2182         }
2183         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2184             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2185                 if (connected) {
2186                         DRM_DEBUG("CV connected\n");
2187                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2188                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2189                 } else {
2190                         DRM_DEBUG("CV disconnected\n");
2191                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2192                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2193                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2194                 }
2195         }
2196         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2197             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2198                 if (connected) {
2199                         DRM_DEBUG("LCD1 connected\n");
2200                         bios_0_scratch |= ATOM_S0_LCD1;
2201                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2202                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2203                 } else {
2204                         DRM_DEBUG("LCD1 disconnected\n");
2205                         bios_0_scratch &= ~ATOM_S0_LCD1;
2206                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2207                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2208                 }
2209         }
2210         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2211             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2212                 if (connected) {
2213                         DRM_DEBUG("CRT1 connected\n");
2214                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2215                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2216                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2217                 } else {
2218                         DRM_DEBUG("CRT1 disconnected\n");
2219                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2220                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2221                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2222                 }
2223         }
2224         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2225             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2226                 if (connected) {
2227                         DRM_DEBUG("CRT2 connected\n");
2228                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2229                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2230                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2231                 } else {
2232                         DRM_DEBUG("CRT2 disconnected\n");
2233                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2234                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2235                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2236                 }
2237         }
2238         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2239             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2240                 if (connected) {
2241                         DRM_DEBUG("DFP1 connected\n");
2242                         bios_0_scratch |= ATOM_S0_DFP1;
2243                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2244                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2245                 } else {
2246                         DRM_DEBUG("DFP1 disconnected\n");
2247                         bios_0_scratch &= ~ATOM_S0_DFP1;
2248                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2249                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2250                 }
2251         }
2252         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2253             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2254                 if (connected) {
2255                         DRM_DEBUG("DFP2 connected\n");
2256                         bios_0_scratch |= ATOM_S0_DFP2;
2257                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2258                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2259                 } else {
2260                         DRM_DEBUG("DFP2 disconnected\n");
2261                         bios_0_scratch &= ~ATOM_S0_DFP2;
2262                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2263                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2264                 }
2265         }
2266         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2267             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2268                 if (connected) {
2269                         DRM_DEBUG("DFP3 connected\n");
2270                         bios_0_scratch |= ATOM_S0_DFP3;
2271                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2272                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2273                 } else {
2274                         DRM_DEBUG("DFP3 disconnected\n");
2275                         bios_0_scratch &= ~ATOM_S0_DFP3;
2276                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2277                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2278                 }
2279         }
2280         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2281             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2282                 if (connected) {
2283                         DRM_DEBUG("DFP4 connected\n");
2284                         bios_0_scratch |= ATOM_S0_DFP4;
2285                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2286                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2287                 } else {
2288                         DRM_DEBUG("DFP4 disconnected\n");
2289                         bios_0_scratch &= ~ATOM_S0_DFP4;
2290                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2291                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2292                 }
2293         }
2294         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2295             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2296                 if (connected) {
2297                         DRM_DEBUG("DFP5 connected\n");
2298                         bios_0_scratch |= ATOM_S0_DFP5;
2299                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2300                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2301                 } else {
2302                         DRM_DEBUG("DFP5 disconnected\n");
2303                         bios_0_scratch &= ~ATOM_S0_DFP5;
2304                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2305                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2306                 }
2307         }
2308
2309         if (rdev->family >= CHIP_R600) {
2310                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2311                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2312                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2313         } else {
2314                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2315                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2316                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2317         }
2318 }
2319
2320 void
2321 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2322 {
2323         struct drm_device *dev = encoder->dev;
2324         struct radeon_device *rdev = dev->dev_private;
2325         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2326         uint32_t bios_3_scratch;
2327
2328         if (rdev->family >= CHIP_R600)
2329                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2330         else
2331                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2332
2333         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2334                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2335                 bios_3_scratch |= (crtc << 18);
2336         }
2337         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2338                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2339                 bios_3_scratch |= (crtc << 24);
2340         }
2341         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2342                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2343                 bios_3_scratch |= (crtc << 16);
2344         }
2345         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2346                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2347                 bios_3_scratch |= (crtc << 20);
2348         }
2349         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2350                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2351                 bios_3_scratch |= (crtc << 17);
2352         }
2353         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2354                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2355                 bios_3_scratch |= (crtc << 19);
2356         }
2357         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2358                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2359                 bios_3_scratch |= (crtc << 23);
2360         }
2361         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2362                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2363                 bios_3_scratch |= (crtc << 25);
2364         }
2365
2366         if (rdev->family >= CHIP_R600)
2367                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2368         else
2369                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2370 }
2371
2372 void
2373 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2374 {
2375         struct drm_device *dev = encoder->dev;
2376         struct radeon_device *rdev = dev->dev_private;
2377         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2378         uint32_t bios_2_scratch;
2379
2380         if (rdev->family >= CHIP_R600)
2381                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2382         else
2383                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2384
2385         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2386                 if (on)
2387                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2388                 else
2389                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2390         }
2391         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2392                 if (on)
2393                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2394                 else
2395                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2396         }
2397         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2398                 if (on)
2399                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2400                 else
2401                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2402         }
2403         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2404                 if (on)
2405                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2406                 else
2407                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2408         }
2409         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2410                 if (on)
2411                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2412                 else
2413                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2414         }
2415         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2416                 if (on)
2417                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2418                 else
2419                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2420         }
2421         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2422                 if (on)
2423                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2424                 else
2425                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2426         }
2427         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2428                 if (on)
2429                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2430                 else
2431                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2432         }
2433         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2434                 if (on)
2435                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2436                 else
2437                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2438         }
2439         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2440                 if (on)
2441                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2442                 else
2443                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2444         }
2445
2446         if (rdev->family >= CHIP_R600)
2447                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2448         else
2449                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2450 }