2 * Copyright 2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
27 #include <linux/types.h>
28 #include <linux/kernel.h>
31 * R6xx+ cards need to use the 3D engine to blit data which requires
32 * quite a bit of hw state setup. Rather than pull the whole 3D driver
33 * (which normally generates the 3D state) into the DRM, we opt to use
34 * statically generated state tables. The regsiter state and shaders
35 * were hand generated to support blitting functionality. See the 3D
36 * driver or documentation for descriptions of the registers and
37 * shader instructions.
40 const u32 r6xx_default_state[] =
42 0xc0002400, /* START_3D_CMDBUF */
45 0xc0012800, /* CONTEXT_CONTROL */
51 0x00008000, /* WAIT_UNTIL */
55 0x07000003, /* TA_CNTL_AUX */
59 0x00000000, /* VC_ENHANCE */
63 0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
67 0x82000000, /* DB_DEBUG */
71 0x01020204, /* DB_WATERMARKS */
75 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
76 0x00000000, /* SQ_VTX_START_INST_LOC */
80 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
92 0x00000000, /* DB_DEPTH_INFO */
96 0x00000000, /* DB_STENCIL_CLEAR */
97 0x00000000, /* DB_DEPTH_CLEAR */
101 0x00000000, /* DB_DEPTH_CONTROL */
105 0x00000060, /* DB_RENDER_CONTROL */
106 0x00000040, /* DB_RENDER_OVERRIDE */
110 0x0000aa00, /* DB_ALPHA_TO_MASK */
114 0x00000800, /* VGT_MAX_VTX_INDX */
115 0x00000000, /* VGT_MIN_VTX_INDX */
116 0x00000000, /* VGT_INDX_OFFSET */
120 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
124 0x00000000, /* SX_ALPHA_TEST_CONTROL */
128 0x00000000, /* CB_BLEND_RED */
132 0x00000000, /* CB_FOG_RED */
138 0x00000000, /* DB_STENCILREFMASK */
139 0x00000000, /* DB_STENCILREFMASK_BF */
143 0x00000000, /* SX_ALPHA_REF */
147 0x01000000, /* CB_CLRCMP_CNTL */
154 0x3f800000, /* CB_CLEAR_RED */
161 0x00000000, /* PA_SC_WINDOW_OFFSET */
165 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
166 0x00000000, /* PA_SC_CLIPRECT_0_TL */
174 0x00000000, /* PA_SC_EDGERULE */
178 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
179 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
180 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
210 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
245 0x00000000, /* PA_SC_MPASS_PS_CNTL */
249 0x00004010, /* PA_SC_MODE_CNTL */
253 0x00000000, /* PA_CL_VPORT_0_XSCALE */
262 0x00000000, /* PA_SC_LINE_CNTL */
263 0x00000000, /* PA_SC_AA_CONFIG */
267 0x0000002d, /* PA_SU_VTX_CNTL */
271 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
278 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
283 0xffffffff, /* PA_SC_AA_MASK */
287 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
291 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
295 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
299 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
303 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
307 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
311 0x00000000, /* SPI_INPUT_Z */
312 0x00000000, /* SPI_FOG_CNTL */
313 0x00000000, /* SPI_FOG_FUNC_SCALE */
314 0x00000000, /* SPI_FOG_FUNC_BIAS */
318 0x00000000, /* SQ_PGM_START_FS */
322 0x00000000, /* SQ_PGM_RESOURCES_FS */
326 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
330 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
331 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
335 0x00000000, /* PA_SU_POINT_SIZE */
336 0x00000000, /* PA_SU_POINT_MINMAX */
340 0x00000008, /* PA_SU_LINE_CNTL */
344 0x00000000, /* PA_SC_LINE_STIPPLE */
348 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
352 0x00000000, /* VGT_HOS_CNTL */
356 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
357 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
358 0x00000000, /* VGT_HOS_REUSE_DEPTH */
359 0x00000000, /* VGT_GROUP_PRIM_TYPE */
360 0x00000000, /* VGT_GROUP_FIRST_DECR */
361 0x00000000, /* VGT_GROUP_DECR */
362 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
363 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
364 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
365 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
369 0x00000000, /* VGT_GS_MODE */
373 0x00000000, /* VGT_PRIMITIVEID_EN */
377 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
381 0x00000000, /* VGT_STRMOUT_EN */
382 0x00000000, /* VGT_REUSE_OFF */
383 0x00000000, /* VGT_VTX_CNT_EN */
387 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
391 0x00cc0000, /* CB_COLOR_CONTROL */
395 0x00000210, /* DB_SHADER_CNTL */
399 0x00010000, /* PA_CL_CLIP_CNTL */
403 0x00000244, /* PA_SU_SC_MODE_CNTL */
407 0x00000100, /* PA_CL_VTE_CNTL */
411 0x00000000, /* PA_CL_VS_OUT_CNTL */
412 0x00000000, /* PA_CL_NANINF_CNTL */
416 0x0000000f, /* CB_TARGET_MASK */
420 0x0000000f, /* CB_SHADER_MASK */
424 0x00000001, /* CB_SHADER_CONTROL */
428 0x00000000, /* SPI_VS_OUT_ID_0 */
432 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
436 0x00000000, /* SPI_VS_OUT_CONFIG */
440 0x00000000, /* SPI_THREAD_GROUPING */
444 0x00000001, /* SPI_PS_IN_CONTROL_0 */
445 0x00000000, /* SPI_PS_IN_CONTROL_1 */
449 0x00000000, /* SPI_INTERP_CONTROL_0 */
451 0xc0036e00, /* SET_SAMPLER */
458 const u32 r7xx_default_state[] =
460 0xc0012800, /* CONTEXT_CONTROL */
466 0x00008000, /* WAIT_UNTIL */
470 0x07000002, /* TA_CNTL_AUX */
474 0x00000000, /* VC_ENHANCE */
478 0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
482 0x00000000, /* DB_DEBUG */
486 0x00420204, /* DB_WATERMARKS */
490 0x00000000, /* SQ_VTX_BASE_VTX_LOC */
491 0x00000000, /* SQ_VTX_START_INST_LOC */
495 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
507 0x00000000, /* DB_DEPTH_INFO */
511 0x00000000, /* DB_STENCIL_CLEAR */
512 0x00000000, /* DB_DEPTH_CLEAR */
516 0x00000000, /* DB_DEPTH_CONTROL */
520 0x00000060, /* DB_RENDER_CONTROL */
521 0x00000000, /* DB_RENDER_OVERRIDE */
525 0x0000aa00, /* DB_ALPHA_TO_MASK */
529 0x00000800, /* VGT_MAX_VTX_INDX */
530 0x00000000, /* VGT_MIN_VTX_INDX */
531 0x00000000, /* VGT_INDX_OFFSET */
535 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
539 0x00000000, /* SX_ALPHA_TEST_CONTROL */
543 0x00000000, /* CB_BLEND_RED */
550 0x00000000, /* DB_STENCILREFMASK */
551 0x00000000, /* DB_STENCILREFMASK_BF */
555 0x00000000, /* SX_ALPHA_REF */
558 0x0000030c, /* CB_CLRCMP_CNTL */
566 0x00000000, /* PA_SC_WINDOW_OFFSET */
570 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
571 0x00000000, /* PA_SC_CLIPRECT_0_TL */
579 0xaaaaaaaa, /* PA_SC_EDGERULE */
583 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
584 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
585 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
615 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
650 0x00000000, /* PA_SC_MPASS_PS_CNTL */
654 0x00514000, /* PA_SC_MODE_CNTL */
658 0x00000000, /* PA_CL_VPORT_0_XSCALE */
667 0x00000000, /* PA_SC_LINE_CNTL */
668 0x00000000, /* PA_SC_AA_CONFIG */
672 0x0000002d, /* PA_SU_VTX_CNTL */
676 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
683 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
688 0xffffffff, /* PA_SC_AA_MASK */
692 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
696 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
700 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
704 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
708 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
712 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
716 0x00000000, /* SPI_INPUT_Z */
717 0x00000000, /* SPI_FOG_CNTL */
718 0x00000000, /* SPI_FOG_FUNC_SCALE */
719 0x00000000, /* SPI_FOG_FUNC_BIAS */
723 0x00000000, /* SQ_PGM_START_FS */
727 0x00000000, /* SQ_PGM_RESOURCES_FS */
731 0x00000000, /* SQ_PGM_CF_OFFSET_FS */
735 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
736 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
740 0x00000000, /* PA_SU_POINT_SIZE */
741 0x00000000, /* PA_SU_POINT_MINMAX */
745 0x00000008, /* PA_SU_LINE_CNTL */
749 0x00000000, /* PA_SC_LINE_STIPPLE */
753 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
757 0x00000000, /* VGT_HOS_CNTL */
758 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
759 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
760 0x00000000, /* VGT_HOS_REUSE_DEPTH */
761 0x00000000, /* VGT_GROUP_PRIM_TYPE */
762 0x00000000, /* VGT_GROUP_FIRST_DECR */
763 0x00000000, /* VGT_GROUP_DECR */
764 0x00000000, /* VGT_GROUP_VECT_0_CNTL */
765 0x00000000, /* VGT_GROUP_VECT_1_CNTL */
766 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
767 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
771 0x00000000, /* VGT_GS_MODE */
775 0x00000000, /* VGT_PRIMITIVEID_EN */
779 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
783 0x00000000, /* VGT_STRMOUT_EN */
784 0x00000000, /* VGT_REUSE_OFF */
785 0x00000000, /* VGT_VTX_CNT_EN */
789 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
793 0x00cc0000, /* CB_COLOR_CONTROL */
797 0x00000210, /* DB_SHADER_CNTL */
801 0x00010000, /* PA_CL_CLIP_CNTL */
805 0x00000244, /* PA_SU_SC_MODE_CNTL */
809 0x00000100, /* PA_CL_VTE_CNTL */
813 0x00000000, /* PA_CL_VS_OUT_CNTL */
814 0x00000000, /* PA_CL_NANINF_CNTL */
818 0x0000000f, /* CB_TARGET_MASK */
822 0x0000000f, /* CB_SHADER_MASK */
826 0x00000001, /* CB_SHADER_CONTROL */
830 0x00000000, /* SPI_VS_OUT_ID_0 */
834 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
838 0x00000000, /* SPI_VS_OUT_CONFIG */
842 0x00000001, /* SPI_THREAD_GROUPING */
846 0x00000001, /* SPI_PS_IN_CONTROL_0 */
847 0x00000000, /* SPI_PS_IN_CONTROL_1 */
851 0x00000000, /* SPI_INTERP_CONTROL_0 */
853 0xc0036e00, /* SET_SAMPLER */
860 /* same for r6xx/r7xx */
861 const u32 r6xx_vs[] =
877 const u32 r6xx_ps[] =
889 const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
890 const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
891 const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
892 const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);