drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "radeon_share.h"
  36 #include "r600d.h"
  37 #include "avivod.h"
  38 #include "atom.h"
  39
  40 #define PFP_UCODE_SIZE 576
  41 #define PM4_UCODE_SIZE 1792
  42 #define R700_PFP_UCODE_SIZE 848
  43 #define R700_PM4_UCODE_SIZE 1360
  44
  45 /* Firmware Names */
  46 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  47 MODULE_FIRMWARE("radeon/R600_me.bin");
  48 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  49 MODULE_FIRMWARE("radeon/RV610_me.bin");
  50 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  51 MODULE_FIRMWARE("radeon/RV630_me.bin");
  52 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  53 MODULE_FIRMWARE("radeon/RV620_me.bin");
  54 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV635_me.bin");
  56 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV670_me.bin");
  58 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RS780_me.bin");
  60 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV770_me.bin");
  62 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV730_me.bin");
  64 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV710_me.bin");
  66
  67 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  68
  69 /* This files gather functions specifics to:
  70  * r600,rv610,rv630,rv620,rv635,rv670
  71  *
  72  * Some of these functions might be used by newer ASICs.
  73  */
  74 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  75 void r600_gpu_init(struct radeon_device *rdev);
  76 void r600_fini(struct radeon_device *rdev);
  77
  78
  79 /*
  80  * R600 PCIE GART
  81  */
  82 int r600_gart_clear_page(struct radeon_device *rdev, int i)
  83 {
  84         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  85         u64 pte;
  86
  87         if (i < 0 || i > rdev->gart.num_gpu_pages)
  88                 return -EINVAL;
  89         pte = 0;
  90         writeq(pte, ((void __iomem *)ptr) + (i * 8));
  91         return 0;
  92 }
  93
  94 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
  95 {
  96         unsigned i;
  97         u32 tmp;
  98
  99         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 100         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 101         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 102         for (i = 0; i < rdev->usec_timeout; i++) {
 103                 /* read MC_STATUS */
 104                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 105                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 106                 if (tmp == 2) {
 107                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 108                         return;
 109                 }
 110                 if (tmp) {
 111                         return;
 112                 }
 113                 udelay(1);
 114         }
 115 }
 116
 117 int r600_pcie_gart_enable(struct radeon_device *rdev)
 118 {
 119         u32 tmp;
 120         int r, i;
 121
 122         /* Initialize common gart structure */
 123         r = radeon_gart_init(rdev);
 124         if (r) {
 125                 return r;
 126         }
 127         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 128         r = radeon_gart_table_vram_alloc(rdev);
 129         if (r) {
 130                 return r;
 131         }
 132         for (i = 0; i < rdev->gart.num_gpu_pages; i++)
 133                 r600_gart_clear_page(rdev, i);
 134         /* Setup L2 cache */
 135         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 136                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 137                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 138         WREG32(VM_L2_CNTL2, 0);
 139         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 140         /* Setup TLB control */
 141         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 142                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 143                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 144                 ENABLE_WAIT_L2_QUERY;
 145         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 146         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 147         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 148         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 149         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 150         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 151         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 152         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 153         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 154         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 155         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 156         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 157         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 158         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 159         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 160         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 161         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 162         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 163                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 164         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 165                         (u32)(rdev->dummy_page.addr >> 12));
 166         for (i = 1; i < 7; i++)
 167                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 168
 169         r600_pcie_gart_tlb_flush(rdev);
 170         rdev->gart.ready = true;
 171         return 0;
 172 }
 173
 174 void r600_pcie_gart_disable(struct radeon_device *rdev)
 175 {
 176         u32 tmp;
 177         int i;
 178
 179         /* Clear ptes*/
 180         for (i = 0; i < rdev->gart.num_gpu_pages; i++)
 181                 r600_gart_clear_page(rdev, i);
 182         r600_pcie_gart_tlb_flush(rdev);
 183         /* Disable all tables */
 184         for (i = 0; i < 7; i++)
 185                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 186
 187         /* Disable L2 cache */
 188         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 189                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 190         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 191         /* Setup L1 TLB control */
 192         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 193                 ENABLE_WAIT_L2_QUERY;
 194         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 195         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 196         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 197         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 198         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 199         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 200         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 201         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 202         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 203         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 204         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 205         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 206         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 207         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 208 }
 209
 210 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 211 {
 212         unsigned i;
 213         u32 tmp;
 214
 215         for (i = 0; i < rdev->usec_timeout; i++) {
 216                 /* read MC_STATUS */
 217                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 218                 if (!tmp)
 219                         return 0;
 220                 udelay(1);
 221         }
 222         return -1;
 223 }
 224
 225 static void r600_mc_resume(struct radeon_device *rdev)
 226 {
 227         u32 d1vga_control, d2vga_control;
 228         u32 vga_render_control, vga_hdp_control;
 229         u32 d1crtc_control, d2crtc_control;
 230         u32 new_d1grph_primary, new_d1grph_secondary;
 231         u32 new_d2grph_primary, new_d2grph_secondary;
 232         u64 old_vram_start;
 233         u32 tmp;
 234         int i, j;
 235
 236         /* Initialize HDP */
 237         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 238                 WREG32((0x2c14 + j), 0x00000000);
 239                 WREG32((0x2c18 + j), 0x00000000);
 240                 WREG32((0x2c1c + j), 0x00000000);
 241                 WREG32((0x2c20 + j), 0x00000000);
 242                 WREG32((0x2c24 + j), 0x00000000);
 243         }
 244         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 245
 246         d1vga_control = RREG32(D1VGA_CONTROL);
 247         d2vga_control = RREG32(D2VGA_CONTROL);
 248         vga_render_control = RREG32(VGA_RENDER_CONTROL);
 249         vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 250         d1crtc_control = RREG32(D1CRTC_CONTROL);
 251         d2crtc_control = RREG32(D2CRTC_CONTROL);
 252         old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 253         new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
 254         new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
 255         new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
 256         new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
 257         new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
 258         new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
 259         new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
 260         new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
 261
 262         /* Stop all video */
 263         WREG32(D1VGA_CONTROL, 0);
 264         WREG32(D2VGA_CONTROL, 0);
 265         WREG32(VGA_RENDER_CONTROL, 0);
 266         WREG32(D1CRTC_UPDATE_LOCK, 1);
 267         WREG32(D2CRTC_UPDATE_LOCK, 1);
 268         WREG32(D1CRTC_CONTROL, 0);
 269         WREG32(D2CRTC_CONTROL, 0);
 270         WREG32(D1CRTC_UPDATE_LOCK, 0);
 271         WREG32(D2CRTC_UPDATE_LOCK, 0);
 272
 273         mdelay(1);
 274         if (r600_mc_wait_for_idle(rdev)) {
 275                 printk(KERN_WARNING "[drm] MC not idle !\n");
 276         }
 277
 278         /* Lockout access through VGA aperture*/
 279         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 280
 281         /* Update configuration */
 282         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 283         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
 284         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 285         tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
 286         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 287         WREG32(MC_VM_FB_LOCATION, tmp);
 288         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 289         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 290         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
 291         if (rdev->flags & RADEON_IS_AGP) {
 292                 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
 293                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 294                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 295         } else {
 296                 WREG32(MC_VM_AGP_BASE, 0);
 297                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 298                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 299         }
 300         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
 301         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
 302         WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
 303         WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
 304         WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
 305
 306         /* Unlock host access */
 307         WREG32(VGA_HDP_CONTROL, vga_hdp_control);
 308
 309         mdelay(1);
 310         if (r600_mc_wait_for_idle(rdev)) {
 311                 printk(KERN_WARNING "[drm] MC not idle !\n");
 312         }
 313
 314         /* Restore video state */
 315         WREG32(D1CRTC_UPDATE_LOCK, 1);
 316         WREG32(D2CRTC_UPDATE_LOCK, 1);
 317         WREG32(D1CRTC_CONTROL, d1crtc_control);
 318         WREG32(D2CRTC_CONTROL, d2crtc_control);
 319         WREG32(D1CRTC_UPDATE_LOCK, 0);
 320         WREG32(D2CRTC_UPDATE_LOCK, 0);
 321         WREG32(D1VGA_CONTROL, d1vga_control);
 322         WREG32(D2VGA_CONTROL, d2vga_control);
 323         WREG32(VGA_RENDER_CONTROL, vga_render_control);
 324 }
 325
 326 int r600_mc_init(struct radeon_device *rdev)
 327 {
 328         fixed20_12 a;
 329         u32 tmp;
 330         int chansize;
 331         int r;
 332
 333         /* Get VRAM informations */
 334         rdev->mc.vram_width = 128;
 335         rdev->mc.vram_is_ddr = true;
 336         tmp = RREG32(RAMCFG);
 337         if (tmp & CHANSIZE_OVERRIDE) {
 338                 chansize = 16;
 339         } else if (tmp & CHANSIZE_MASK) {
 340                 chansize = 64;
 341         } else {
 342                 chansize = 32;
 343         }
 344         if (rdev->family == CHIP_R600) {
 345                 rdev->mc.vram_width = 8 * chansize;
 346         } else if (rdev->family == CHIP_RV670) {
 347                 rdev->mc.vram_width = 4 * chansize;
 348         } else if ((rdev->family == CHIP_RV610) ||
 349                         (rdev->family == CHIP_RV620)) {
 350                 rdev->mc.vram_width = chansize;
 351         } else if ((rdev->family == CHIP_RV630) ||
 352                         (rdev->family == CHIP_RV635)) {
 353                 rdev->mc.vram_width = 2 * chansize;
 354         }
 355         /* Could aper size report 0 ? */
 356         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 357         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 358         /* Setup GPU memory space */
 359         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 360         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 361         if (rdev->flags & RADEON_IS_AGP) {
 362                 r = radeon_agp_init(rdev);
 363                 if (r)
 364                         return r;
 365                 /* gtt_size is setup by radeon_agp_init */
 366                 rdev->mc.gtt_location = rdev->mc.agp_base;
 367                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 368                 /* Try to put vram before or after AGP because we
 369                  * we want SYSTEM_APERTURE to cover both VRAM and
 370                  * AGP so that GPU can catch out of VRAM/AGP access
 371                  */
 372                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 373                         /* Enought place before */
 374                         rdev->mc.vram_location = rdev->mc.gtt_location -
 375                                                         rdev->mc.mc_vram_size;
 376                 } else if (tmp > rdev->mc.mc_vram_size) {
 377                         /* Enought place after */
 378                         rdev->mc.vram_location = rdev->mc.gtt_location +
 379                                                         rdev->mc.gtt_size;
 380                 } else {
 381                         /* Try to setup VRAM then AGP might not
 382                          * not work on some card
 383                          */
 384                         rdev->mc.vram_location = 0x00000000UL;
 385                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 386                 }
 387         } else {
 388                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 389                         rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 390                                                                 0xFFFF) << 24;
 391                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 392                         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 393                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 394                                 /* Enough place after vram */
 395                                 rdev->mc.gtt_location = tmp;
 396                         } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 397                                 /* Enough place before vram */
 398                                 rdev->mc.gtt_location = 0;
 399                         } else {
 400                                 /* Not enough place after or before shrink
 401                                  * gart size
 402                                  */
 403                                 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
 404                                         rdev->mc.gtt_location = 0;
 405                                         rdev->mc.gtt_size = rdev->mc.vram_location;
 406                                 } else {
 407                                         rdev->mc.gtt_location = tmp;
 408                                         rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 409                                 }
 410                         }
 411                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 412                 } else {
 413                         rdev->mc.vram_location = 0x00000000UL;
 414                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 415                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 416                 }
 417         }
 418         rdev->mc.vram_start = rdev->mc.vram_location;
 419         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 420         rdev->mc.gtt_start = rdev->mc.gtt_location;
 421         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
 422         /* FIXME: we should enforce default clock in case GPU is not in
 423          * default setup
 424          */
 425         a.full = rfixed_const(100);
 426         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 427         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 428         return 0;
 429 }
 430
 431 /* We doesn't check that the GPU really needs a reset we simply do the
 432  * reset, it's up to the caller to determine if the GPU needs one. We
 433  * might add an helper function to check that.
 434  */
 435 int r600_gpu_soft_reset(struct radeon_device *rdev)
 436 {
 437         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 438                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 439                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 440                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 441                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 442                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 443                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 444                                 S_008010_GUI_ACTIVE(1);
 445         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 446                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 447                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 448                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 449                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 450                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 451                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 452                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 453         u32 srbm_reset = 0;
 454
 455         /* Disable CP parsing/prefetching */
 456         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 457         /* Check if any of the rendering block is busy and reset it */
 458         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 459             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 460                 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
 461                         S_008020_SOFT_RESET_DB(1) |
 462                         S_008020_SOFT_RESET_CB(1) |
 463                         S_008020_SOFT_RESET_PA(1) |
 464                         S_008020_SOFT_RESET_SC(1) |
 465                         S_008020_SOFT_RESET_SMX(1) |
 466                         S_008020_SOFT_RESET_SPI(1) |
 467                         S_008020_SOFT_RESET_SX(1) |
 468                         S_008020_SOFT_RESET_SH(1) |
 469                         S_008020_SOFT_RESET_TC(1) |
 470                         S_008020_SOFT_RESET_TA(1) |
 471                         S_008020_SOFT_RESET_VC(1) |
 472                         S_008020_SOFT_RESET_VGT(1));
 473                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 474                 udelay(50);
 475                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 476                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 477         }
 478         /* Reset CP (we always reset CP) */
 479         WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
 480         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 481         udelay(50);
 482         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 483         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 484         /* Reset others GPU block if necessary */
 485         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 486                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 487         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 488                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 489         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 490                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 491         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 492                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 493         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 494                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 495         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 496                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 497         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 498                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 499         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 500                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 501         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 502                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 503         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 504                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 505         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 506                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 507         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 508         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 509         udelay(50);
 510         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 511         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 512         /* Wait a little for things to settle down */
 513         udelay(50);
 514         return 0;
 515 }
 516
 517 int r600_gpu_reset(struct radeon_device *rdev)
 518 {
 519         return r600_gpu_soft_reset(rdev);
 520 }
 521
 522 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 523                                              u32 num_backends,
 524                                              u32 backend_disable_mask)
 525 {
 526         u32 backend_map = 0;
 527         u32 enabled_backends_mask;
 528         u32 enabled_backends_count;
 529         u32 cur_pipe;
 530         u32 swizzle_pipe[R6XX_MAX_PIPES];
 531         u32 cur_backend;
 532         u32 i;
 533
 534         if (num_tile_pipes > R6XX_MAX_PIPES)
 535                 num_tile_pipes = R6XX_MAX_PIPES;
 536         if (num_tile_pipes < 1)
 537                 num_tile_pipes = 1;
 538         if (num_backends > R6XX_MAX_BACKENDS)
 539                 num_backends = R6XX_MAX_BACKENDS;
 540         if (num_backends < 1)
 541                 num_backends = 1;
 542
 543         enabled_backends_mask = 0;
 544         enabled_backends_count = 0;
 545         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 546                 if (((backend_disable_mask >> i) & 1) == 0) {
 547                         enabled_backends_mask |= (1 << i);
 548                         ++enabled_backends_count;
 549                 }
 550                 if (enabled_backends_count == num_backends)
 551                         break;
 552         }
 553
 554         if (enabled_backends_count == 0) {
 555                 enabled_backends_mask = 1;
 556                 enabled_backends_count = 1;
 557         }
 558
 559         if (enabled_backends_count != num_backends)
 560                 num_backends = enabled_backends_count;
 561
 562         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 563         switch (num_tile_pipes) {
 564         case 1:
 565                 swizzle_pipe[0] = 0;
 566                 break;
 567         case 2:
 568                 swizzle_pipe[0] = 0;
 569                 swizzle_pipe[1] = 1;
 570                 break;
 571         case 3:
 572                 swizzle_pipe[0] = 0;
 573                 swizzle_pipe[1] = 1;
 574                 swizzle_pipe[2] = 2;
 575                 break;
 576         case 4:
 577                 swizzle_pipe[0] = 0;
 578                 swizzle_pipe[1] = 1;
 579                 swizzle_pipe[2] = 2;
 580                 swizzle_pipe[3] = 3;
 581                 break;
 582         case 5:
 583                 swizzle_pipe[0] = 0;
 584                 swizzle_pipe[1] = 1;
 585                 swizzle_pipe[2] = 2;
 586                 swizzle_pipe[3] = 3;
 587                 swizzle_pipe[4] = 4;
 588                 break;
 589         case 6:
 590                 swizzle_pipe[0] = 0;
 591                 swizzle_pipe[1] = 2;
 592                 swizzle_pipe[2] = 4;
 593                 swizzle_pipe[3] = 5;
 594                 swizzle_pipe[4] = 1;
 595                 swizzle_pipe[5] = 3;
 596                 break;
 597         case 7:
 598                 swizzle_pipe[0] = 0;
 599                 swizzle_pipe[1] = 2;
 600                 swizzle_pipe[2] = 4;
 601                 swizzle_pipe[3] = 6;
 602                 swizzle_pipe[4] = 1;
 603                 swizzle_pipe[5] = 3;
 604                 swizzle_pipe[6] = 5;
 605                 break;
 606         case 8:
 607                 swizzle_pipe[0] = 0;
 608                 swizzle_pipe[1] = 2;
 609                 swizzle_pipe[2] = 4;
 610                 swizzle_pipe[3] = 6;
 611                 swizzle_pipe[4] = 1;
 612                 swizzle_pipe[5] = 3;
 613                 swizzle_pipe[6] = 5;
 614                 swizzle_pipe[7] = 7;
 615                 break;
 616         }
 617
 618         cur_backend = 0;
 619         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 620                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 621                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 622
 623                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 624
 625                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 626         }
 627
 628         return backend_map;
 629 }
 630
 631 int r600_count_pipe_bits(uint32_t val)
 632 {
 633         int i, ret = 0;
 634
 635         for (i = 0; i < 32; i++) {
 636                 ret += val & 1;
 637                 val >>= 1;
 638         }
 639         return ret;
 640 }
 641
 642 void r600_gpu_init(struct radeon_device *rdev)
 643 {
 644         u32 tiling_config;
 645         u32 ramcfg;
 646         u32 tmp;
 647         int i, j;
 648         u32 sq_config;
 649         u32 sq_gpr_resource_mgmt_1 = 0;
 650         u32 sq_gpr_resource_mgmt_2 = 0;
 651         u32 sq_thread_resource_mgmt = 0;
 652         u32 sq_stack_resource_mgmt_1 = 0;
 653         u32 sq_stack_resource_mgmt_2 = 0;
 654
 655         /* FIXME: implement */
 656         switch (rdev->family) {
 657         case CHIP_R600:
 658                 rdev->config.r600.max_pipes = 4;
 659                 rdev->config.r600.max_tile_pipes = 8;
 660                 rdev->config.r600.max_simds = 4;
 661                 rdev->config.r600.max_backends = 4;
 662                 rdev->config.r600.max_gprs = 256;
 663                 rdev->config.r600.max_threads = 192;
 664                 rdev->config.r600.max_stack_entries = 256;
 665                 rdev->config.r600.max_hw_contexts = 8;
 666                 rdev->config.r600.max_gs_threads = 16;
 667                 rdev->config.r600.sx_max_export_size = 128;
 668                 rdev->config.r600.sx_max_export_pos_size = 16;
 669                 rdev->config.r600.sx_max_export_smx_size = 128;
 670                 rdev->config.r600.sq_num_cf_insts = 2;
 671                 break;
 672         case CHIP_RV630:
 673         case CHIP_RV635:
 674                 rdev->config.r600.max_pipes = 2;
 675                 rdev->config.r600.max_tile_pipes = 2;
 676                 rdev->config.r600.max_simds = 3;
 677                 rdev->config.r600.max_backends = 1;
 678                 rdev->config.r600.max_gprs = 128;
 679                 rdev->config.r600.max_threads = 192;
 680                 rdev->config.r600.max_stack_entries = 128;
 681                 rdev->config.r600.max_hw_contexts = 8;
 682                 rdev->config.r600.max_gs_threads = 4;
 683                 rdev->config.r600.sx_max_export_size = 128;
 684                 rdev->config.r600.sx_max_export_pos_size = 16;
 685                 rdev->config.r600.sx_max_export_smx_size = 128;
 686                 rdev->config.r600.sq_num_cf_insts = 2;
 687                 break;
 688         case CHIP_RV610:
 689         case CHIP_RV620:
 690         case CHIP_RS780:
 691         case CHIP_RS880:
 692                 rdev->config.r600.max_pipes = 1;
 693                 rdev->config.r600.max_tile_pipes = 1;
 694                 rdev->config.r600.max_simds = 2;
 695                 rdev->config.r600.max_backends = 1;
 696                 rdev->config.r600.max_gprs = 128;
 697                 rdev->config.r600.max_threads = 192;
 698                 rdev->config.r600.max_stack_entries = 128;
 699                 rdev->config.r600.max_hw_contexts = 4;
 700                 rdev->config.r600.max_gs_threads = 4;
 701                 rdev->config.r600.sx_max_export_size = 128;
 702                 rdev->config.r600.sx_max_export_pos_size = 16;
 703                 rdev->config.r600.sx_max_export_smx_size = 128;
 704                 rdev->config.r600.sq_num_cf_insts = 1;
 705                 break;
 706         case CHIP_RV670:
 707                 rdev->config.r600.max_pipes = 4;
 708                 rdev->config.r600.max_tile_pipes = 4;
 709                 rdev->config.r600.max_simds = 4;
 710                 rdev->config.r600.max_backends = 4;
 711                 rdev->config.r600.max_gprs = 192;
 712                 rdev->config.r600.max_threads = 192;
 713                 rdev->config.r600.max_stack_entries = 256;
 714                 rdev->config.r600.max_hw_contexts = 8;
 715                 rdev->config.r600.max_gs_threads = 16;
 716                 rdev->config.r600.sx_max_export_size = 128;
 717                 rdev->config.r600.sx_max_export_pos_size = 16;
 718                 rdev->config.r600.sx_max_export_smx_size = 128;
 719                 rdev->config.r600.sq_num_cf_insts = 2;
 720                 break;
 721         default:
 722                 break;
 723         }
 724
 725         /* Initialize HDP */
 726         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 727                 WREG32((0x2c14 + j), 0x00000000);
 728                 WREG32((0x2c18 + j), 0x00000000);
 729                 WREG32((0x2c1c + j), 0x00000000);
 730                 WREG32((0x2c20 + j), 0x00000000);
 731                 WREG32((0x2c24 + j), 0x00000000);
 732         }
 733
 734         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 735
 736         /* Setup tiling */
 737         tiling_config = 0;
 738         ramcfg = RREG32(RAMCFG);
 739         switch (rdev->config.r600.max_tile_pipes) {
 740         case 1:
 741                 tiling_config |= PIPE_TILING(0);
 742                 break;
 743         case 2:
 744                 tiling_config |= PIPE_TILING(1);
 745                 break;
 746         case 4:
 747                 tiling_config |= PIPE_TILING(2);
 748                 break;
 749         case 8:
 750                 tiling_config |= PIPE_TILING(3);
 751                 break;
 752         default:
 753                 break;
 754         }
 755         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 756         tiling_config |= GROUP_SIZE(0);
 757         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
 758         if (tmp > 3) {
 759                 tiling_config |= ROW_TILING(3);
 760                 tiling_config |= SAMPLE_SPLIT(3);
 761         } else {
 762                 tiling_config |= ROW_TILING(tmp);
 763                 tiling_config |= SAMPLE_SPLIT(tmp);
 764         }
 765         tiling_config |= BANK_SWAPS(1);
 766         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
 767                                                 rdev->config.r600.max_backends,
 768                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
 769         tiling_config |= BACKEND_MAP(tmp);
 770         WREG32(GB_TILING_CONFIG, tiling_config);
 771         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
 772         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
 773
 774         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
 775         WREG32(CC_RB_BACKEND_DISABLE, tmp);
 776
 777         /* Setup pipes */
 778         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
 779         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
 780         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
 781         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
 782
 783         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
 784         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
 785         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 786
 787         /* Setup some CP states */
 788         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
 789         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
 790
 791         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
 792                              SYNC_WALKER | SYNC_ALIGNER));
 793         /* Setup various GPU states */
 794         if (rdev->family == CHIP_RV670)
 795                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
 796
 797         tmp = RREG32(SX_DEBUG_1);
 798         tmp |= SMX_EVENT_RELEASE;
 799         if ((rdev->family > CHIP_R600))
 800                 tmp |= ENABLE_NEW_SMX_ADDRESS;
 801         WREG32(SX_DEBUG_1, tmp);
 802
 803         if (((rdev->family) == CHIP_R600) ||
 804             ((rdev->family) == CHIP_RV630) ||
 805             ((rdev->family) == CHIP_RV610) ||
 806             ((rdev->family) == CHIP_RV620) ||
 807             ((rdev->family) == CHIP_RS780)) {
 808                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 809         } else {
 810                 WREG32(DB_DEBUG, 0);
 811         }
 812         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
 813                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
 814
 815         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 816         WREG32(VGT_NUM_INSTANCES, 0);
 817
 818         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 819         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
 820
 821         tmp = RREG32(SQ_MS_FIFO_SIZES);
 822         if (((rdev->family) == CHIP_RV610) ||
 823             ((rdev->family) == CHIP_RV620) ||
 824             ((rdev->family) == CHIP_RS780)) {
 825                 tmp = (CACHE_FIFO_SIZE(0xa) |
 826                        FETCH_FIFO_HIWATER(0xa) |
 827                        DONE_FIFO_HIWATER(0xe0) |
 828                        ALU_UPDATE_FIFO_HIWATER(0x8));
 829         } else if (((rdev->family) == CHIP_R600) ||
 830                    ((rdev->family) == CHIP_RV630)) {
 831                 tmp &= ~DONE_FIFO_HIWATER(0xff);
 832                 tmp |= DONE_FIFO_HIWATER(0x4);
 833         }
 834         WREG32(SQ_MS_FIFO_SIZES, tmp);
 835
 836         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 837          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 838          */
 839         sq_config = RREG32(SQ_CONFIG);
 840         sq_config &= ~(PS_PRIO(3) |
 841                        VS_PRIO(3) |
 842                        GS_PRIO(3) |
 843                        ES_PRIO(3));
 844         sq_config |= (DX9_CONSTS |
 845                       VC_ENABLE |
 846                       PS_PRIO(0) |
 847                       VS_PRIO(1) |
 848                       GS_PRIO(2) |
 849                       ES_PRIO(3));
 850
 851         if ((rdev->family) == CHIP_R600) {
 852                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
 853                                           NUM_VS_GPRS(124) |
 854                                           NUM_CLAUSE_TEMP_GPRS(4));
 855                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
 856                                           NUM_ES_GPRS(0));
 857                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
 858                                            NUM_VS_THREADS(48) |
 859                                            NUM_GS_THREADS(4) |
 860                                            NUM_ES_THREADS(4));
 861                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
 862                                             NUM_VS_STACK_ENTRIES(128));
 863                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
 864                                             NUM_ES_STACK_ENTRIES(0));
 865         } else if (((rdev->family) == CHIP_RV610) ||
 866                    ((rdev->family) == CHIP_RV620) ||
 867                    ((rdev->family) == CHIP_RS780)) {
 868                 /* no vertex cache */
 869                 sq_config &= ~VC_ENABLE;
 870
 871                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 872                                           NUM_VS_GPRS(44) |
 873                                           NUM_CLAUSE_TEMP_GPRS(2));
 874                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 875                                           NUM_ES_GPRS(17));
 876                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 877                                            NUM_VS_THREADS(78) |
 878                                            NUM_GS_THREADS(4) |
 879                                            NUM_ES_THREADS(31));
 880                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 881                                             NUM_VS_STACK_ENTRIES(40));
 882                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 883                                             NUM_ES_STACK_ENTRIES(16));
 884         } else if (((rdev->family) == CHIP_RV630) ||
 885                    ((rdev->family) == CHIP_RV635)) {
 886                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 887                                           NUM_VS_GPRS(44) |
 888                                           NUM_CLAUSE_TEMP_GPRS(2));
 889                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
 890                                           NUM_ES_GPRS(18));
 891                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 892                                            NUM_VS_THREADS(78) |
 893                                            NUM_GS_THREADS(4) |
 894                                            NUM_ES_THREADS(31));
 895                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 896                                             NUM_VS_STACK_ENTRIES(40));
 897                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 898                                             NUM_ES_STACK_ENTRIES(16));
 899         } else if ((rdev->family) == CHIP_RV670) {
 900                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 901                                           NUM_VS_GPRS(44) |
 902                                           NUM_CLAUSE_TEMP_GPRS(2));
 903                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 904                                           NUM_ES_GPRS(17));
 905                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 906                                            NUM_VS_THREADS(78) |
 907                                            NUM_GS_THREADS(4) |
 908                                            NUM_ES_THREADS(31));
 909                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
 910                                             NUM_VS_STACK_ENTRIES(64));
 911                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
 912                                             NUM_ES_STACK_ENTRIES(64));
 913         }
 914
 915         WREG32(SQ_CONFIG, sq_config);
 916         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 917         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 918         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 919         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 920         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 921
 922         if (((rdev->family) == CHIP_RV610) ||
 923             ((rdev->family) == CHIP_RV620) ||
 924             ((rdev->family) == CHIP_RS780)) {
 925                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
 926         } else {
 927                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
 928         }
 929
 930         /* More default values. 2D/3D driver should adjust as needed */
 931         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
 932                                          S1_X(0x4) | S1_Y(0xc)));
 933         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
 934                                          S1_X(0x2) | S1_Y(0x2) |
 935                                          S2_X(0xa) | S2_Y(0x6) |
 936                                          S3_X(0x6) | S3_Y(0xa)));
 937         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
 938                                              S1_X(0x4) | S1_Y(0xc) |
 939                                              S2_X(0x1) | S2_Y(0x6) |
 940                                              S3_X(0xa) | S3_Y(0xe)));
 941         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
 942                                              S5_X(0x0) | S5_Y(0x0) |
 943                                              S6_X(0xb) | S6_Y(0x4) |
 944                                              S7_X(0x7) | S7_Y(0x8)));
 945
 946         WREG32(VGT_STRMOUT_EN, 0);
 947         tmp = rdev->config.r600.max_pipes * 16;
 948         switch (rdev->family) {
 949         case CHIP_RV610:
 950         case CHIP_RS780:
 951         case CHIP_RV620:
 952                 tmp += 32;
 953                 break;
 954         case CHIP_RV670:
 955                 tmp += 128;
 956                 break;
 957         default:
 958                 break;
 959         }
 960         if (tmp > 256) {
 961                 tmp = 256;
 962         }
 963         WREG32(VGT_ES_PER_GS, 128);
 964         WREG32(VGT_GS_PER_ES, tmp);
 965         WREG32(VGT_GS_PER_VS, 2);
 966         WREG32(VGT_GS_VERTEX_REUSE, 16);
 967
 968         /* more default values. 2D/3D driver should adjust as needed */
 969         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 970         WREG32(VGT_STRMOUT_EN, 0);
 971         WREG32(SX_MISC, 0);
 972         WREG32(PA_SC_MODE_CNTL, 0);
 973         WREG32(PA_SC_AA_CONFIG, 0);
 974         WREG32(PA_SC_LINE_STIPPLE, 0);
 975         WREG32(SPI_INPUT_Z, 0);
 976         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 977         WREG32(CB_COLOR7_FRAG, 0);
 978
 979         /* Clear render buffer base addresses */
 980         WREG32(CB_COLOR0_BASE, 0);
 981         WREG32(CB_COLOR1_BASE, 0);
 982         WREG32(CB_COLOR2_BASE, 0);
 983         WREG32(CB_COLOR3_BASE, 0);
 984         WREG32(CB_COLOR4_BASE, 0);
 985         WREG32(CB_COLOR5_BASE, 0);
 986         WREG32(CB_COLOR6_BASE, 0);
 987         WREG32(CB_COLOR7_BASE, 0);
 988         WREG32(CB_COLOR7_FRAG, 0);
 989
 990         switch (rdev->family) {
 991         case CHIP_RV610:
 992         case CHIP_RS780:
 993         case CHIP_RV620:
 994                 tmp = TC_L2_SIZE(8);
 995                 break;
 996         case CHIP_RV630:
 997         case CHIP_RV635:
 998                 tmp = TC_L2_SIZE(4);
 999                 break;
1000         case CHIP_R600:
1001                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1002                 break;
1003         default:
1004                 tmp = TC_L2_SIZE(0);
1005                 break;
1006         }
1007         WREG32(TC_CNTL, tmp);
1008
1009         tmp = RREG32(HDP_HOST_PATH_CNTL);
1010         WREG32(HDP_HOST_PATH_CNTL, tmp);
1011
1012         tmp = RREG32(ARB_POP);
1013         tmp |= ENABLE_TC128;
1014         WREG32(ARB_POP, tmp);
1015
1016         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1017         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1018                                NUM_CLIP_SEQ(3)));
1019         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1020 }
1021
1022
1023 /*
1024  * Indirect registers accessor
1025  */
1026 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1027 {
1028         u32 r;
1029
1030         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1031         (void)RREG32(PCIE_PORT_INDEX);
1032         r = RREG32(PCIE_PORT_DATA);
1033         return r;
1034 }
1035
1036 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1037 {
1038         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1039         (void)RREG32(PCIE_PORT_INDEX);
1040         WREG32(PCIE_PORT_DATA, (v));
1041         (void)RREG32(PCIE_PORT_DATA);
1042 }
1043
1044
1045 /*
1046  * CP & Ring
1047  */
1048 void r600_cp_stop(struct radeon_device *rdev)
1049 {
1050         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1051 }
1052
1053 int r600_cp_init_microcode(struct radeon_device *rdev)
1054 {
1055         struct platform_device *pdev;
1056         const char *chip_name;
1057         size_t pfp_req_size, me_req_size;
1058         char fw_name[30];
1059         int err;
1060
1061         DRM_DEBUG("\n");
1062
1063         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1064         err = IS_ERR(pdev);
1065         if (err) {
1066                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1067                 return -EINVAL;
1068         }
1069
1070         switch (rdev->family) {
1071         case CHIP_R600: chip_name = "R600"; break;
1072         case CHIP_RV610: chip_name = "RV610"; break;
1073         case CHIP_RV630: chip_name = "RV630"; break;
1074         case CHIP_RV620: chip_name = "RV620"; break;
1075         case CHIP_RV635: chip_name = "RV635"; break;
1076         case CHIP_RV670: chip_name = "RV670"; break;
1077         case CHIP_RS780:
1078         case CHIP_RS880: chip_name = "RS780"; break;
1079         case CHIP_RV770: chip_name = "RV770"; break;
1080         case CHIP_RV730:
1081         case CHIP_RV740: chip_name = "RV730"; break;
1082         case CHIP_RV710: chip_name = "RV710"; break;
1083         default: BUG();
1084         }
1085
1086         if (rdev->family >= CHIP_RV770) {
1087                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1088                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1089         } else {
1090                 pfp_req_size = PFP_UCODE_SIZE * 4;
1091                 me_req_size = PM4_UCODE_SIZE * 12;
1092         }
1093
1094         DRM_INFO("Loading %s CP Microcode\n", chip_name);
1095
1096         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1097         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1098         if (err)
1099                 goto out;
1100         if (rdev->pfp_fw->size != pfp_req_size) {
1101                 printk(KERN_ERR
1102                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1103                        rdev->pfp_fw->size, fw_name);
1104                 err = -EINVAL;
1105                 goto out;
1106         }
1107
1108         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1109         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1110         if (err)
1111                 goto out;
1112         if (rdev->me_fw->size != me_req_size) {
1113                 printk(KERN_ERR
1114                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1115                        rdev->me_fw->size, fw_name);
1116                 err = -EINVAL;
1117         }
1118 out:
1119         platform_device_unregister(pdev);
1120
1121         if (err) {
1122                 if (err != -EINVAL)
1123                         printk(KERN_ERR
1124                                "r600_cp: Failed to load firmware \"%s\"\n",
1125                                fw_name);
1126                 release_firmware(rdev->pfp_fw);
1127                 rdev->pfp_fw = NULL;
1128                 release_firmware(rdev->me_fw);
1129                 rdev->me_fw = NULL;
1130         }
1131         return err;
1132 }
1133
1134 static int r600_cp_load_microcode(struct radeon_device *rdev)
1135 {
1136         const __be32 *fw_data;
1137         int i;
1138
1139         if (!rdev->me_fw || !rdev->pfp_fw)
1140                 return -EINVAL;
1141
1142         r600_cp_stop(rdev);
1143
1144         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1145
1146         /* Reset cp */
1147         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1148         RREG32(GRBM_SOFT_RESET);
1149         mdelay(15);
1150         WREG32(GRBM_SOFT_RESET, 0);
1151
1152         WREG32(CP_ME_RAM_WADDR, 0);
1153
1154         fw_data = (const __be32 *)rdev->me_fw->data;
1155         WREG32(CP_ME_RAM_WADDR, 0);
1156         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1157                 WREG32(CP_ME_RAM_DATA,
1158                        be32_to_cpup(fw_data++));
1159
1160         fw_data = (const __be32 *)rdev->pfp_fw->data;
1161         WREG32(CP_PFP_UCODE_ADDR, 0);
1162         for (i = 0; i < PFP_UCODE_SIZE; i++)
1163                 WREG32(CP_PFP_UCODE_DATA,
1164                        be32_to_cpup(fw_data++));
1165
1166         WREG32(CP_PFP_UCODE_ADDR, 0);
1167         WREG32(CP_ME_RAM_WADDR, 0);
1168         WREG32(CP_ME_RAM_RADDR, 0);
1169         return 0;
1170 }
1171
1172 int r600_cp_start(struct radeon_device *rdev)
1173 {
1174         int r;
1175         uint32_t cp_me;
1176
1177         r = radeon_ring_lock(rdev, 7);
1178         if (r) {
1179                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1180                 return r;
1181         }
1182         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1183         radeon_ring_write(rdev, 0x1);
1184         if (rdev->family < CHIP_RV770) {
1185                 radeon_ring_write(rdev, 0x3);
1186                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1187         } else {
1188                 radeon_ring_write(rdev, 0x0);
1189                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1190         }
1191         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1192         radeon_ring_write(rdev, 0);
1193         radeon_ring_write(rdev, 0);
1194         radeon_ring_unlock_commit(rdev);
1195
1196         cp_me = 0xff;
1197         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1198         return 0;
1199 }
1200
1201 int r600_cp_resume(struct radeon_device *rdev)
1202 {
1203         u32 tmp;
1204         u32 rb_bufsz;
1205         int r;
1206
1207         /* Reset cp */
1208         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1209         RREG32(GRBM_SOFT_RESET);
1210         mdelay(15);
1211         WREG32(GRBM_SOFT_RESET, 0);
1212
1213         /* Set ring buffer size */
1214         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1215 #ifdef __BIG_ENDIAN
1216         WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
1217                 (drm_order(4096/8) << 8) | rb_bufsz);
1218 #else
1219         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1220 #endif
1221         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1222
1223         /* Set the write pointer delay */
1224         WREG32(CP_RB_WPTR_DELAY, 0);
1225
1226         /* Initialize the ring buffer's read and write pointers */
1227         tmp = RREG32(CP_RB_CNTL);
1228         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1229         WREG32(CP_RB_RPTR_WR, 0);
1230         WREG32(CP_RB_WPTR, 0);
1231         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1232         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1233         mdelay(1);
1234         WREG32(CP_RB_CNTL, tmp);
1235
1236         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1237         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1238
1239         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1240         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1241
1242         r600_cp_start(rdev);
1243         rdev->cp.ready = true;
1244         r = radeon_ring_test(rdev);
1245         if (r) {
1246                 rdev->cp.ready = false;
1247                 return r;
1248         }
1249         return 0;
1250 }
1251
1252 void r600_cp_commit(struct radeon_device *rdev)
1253 {
1254         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1255         (void)RREG32(CP_RB_WPTR);
1256 }
1257
1258 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1259 {
1260         u32 rb_bufsz;
1261
1262         /* Align ring size */
1263         rb_bufsz = drm_order(ring_size / 8);
1264         ring_size = (1 << (rb_bufsz + 1)) * 4;
1265         rdev->cp.ring_size = ring_size;
1266         rdev->cp.align_mask = 16 - 1;
1267 }
1268
1269
1270 /*
1271  * GPU scratch registers helpers function.
1272  */
1273 void r600_scratch_init(struct radeon_device *rdev)
1274 {
1275         int i;
1276
1277         rdev->scratch.num_reg = 7;
1278         for (i = 0; i < rdev->scratch.num_reg; i++) {
1279                 rdev->scratch.free[i] = true;
1280                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1281         }
1282 }
1283
1284 int r600_ring_test(struct radeon_device *rdev)
1285 {
1286         uint32_t scratch;
1287         uint32_t tmp = 0;
1288         unsigned i;
1289         int r;
1290
1291         r = radeon_scratch_get(rdev, &scratch);
1292         if (r) {
1293                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1294                 return r;
1295         }
1296         WREG32(scratch, 0xCAFEDEAD);
1297         r = radeon_ring_lock(rdev, 3);
1298         if (r) {
1299                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1300                 radeon_scratch_free(rdev, scratch);
1301                 return r;
1302         }
1303         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1304         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1305         radeon_ring_write(rdev, 0xDEADBEEF);
1306         radeon_ring_unlock_commit(rdev);
1307         for (i = 0; i < rdev->usec_timeout; i++) {
1308                 tmp = RREG32(scratch);
1309                 if (tmp == 0xDEADBEEF)
1310                         break;
1311                 DRM_UDELAY(1);
1312         }
1313         if (i < rdev->usec_timeout) {
1314                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1315         } else {
1316                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1317                           scratch, tmp);
1318                 r = -EINVAL;
1319         }
1320         radeon_scratch_free(rdev, scratch);
1321         return r;
1322 }
1323
1324 /*
1325  * Writeback
1326  */
1327 int r600_wb_init(struct radeon_device *rdev)
1328 {
1329         int r;
1330
1331         if (rdev->wb.wb_obj == NULL) {
1332                 r = radeon_object_create(rdev, NULL, 4096,
1333                                          true,
1334                                          RADEON_GEM_DOMAIN_GTT,
1335                                          false, &rdev->wb.wb_obj);
1336                 if (r) {
1337                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
1338                         return r;
1339                 }
1340                 r = radeon_object_pin(rdev->wb.wb_obj,
1341                                       RADEON_GEM_DOMAIN_GTT,
1342                                       &rdev->wb.gpu_addr);
1343                 if (r) {
1344                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
1345                         return r;
1346                 }
1347                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1348                 if (r) {
1349                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
1350                         return r;
1351                 }
1352         }
1353         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1354         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1355         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1356         WREG32(SCRATCH_UMSK, 0xff);
1357         return 0;
1358 }
1359
1360 void r600_wb_fini(struct radeon_device *rdev)
1361 {
1362         if (rdev->wb.wb_obj) {
1363                 radeon_object_kunmap(rdev->wb.wb_obj);
1364                 radeon_object_unpin(rdev->wb.wb_obj);
1365                 radeon_object_unref(&rdev->wb.wb_obj);
1366                 rdev->wb.wb = NULL;
1367                 rdev->wb.wb_obj = NULL;
1368         }
1369 }
1370
1371
1372 /*
1373  * CS
1374  */
1375 void r600_fence_ring_emit(struct radeon_device *rdev,
1376                           struct radeon_fence *fence)
1377 {
1378         /* Emit fence sequence & fire IRQ */
1379         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1380         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1381         radeon_ring_write(rdev, fence->seq);
1382 }
1383
1384 int r600_copy_dma(struct radeon_device *rdev,
1385                   uint64_t src_offset,
1386                   uint64_t dst_offset,
1387                   unsigned num_pages,
1388                   struct radeon_fence *fence)
1389 {
1390         /* FIXME: implement */
1391         return 0;
1392 }
1393
1394 int r600_copy_blit(struct radeon_device *rdev,
1395                    uint64_t src_offset, uint64_t dst_offset,
1396                    unsigned num_pages, struct radeon_fence *fence)
1397 {
1398         r600_blit_prepare_copy(rdev, num_pages * 4096);
1399         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
1400         r600_blit_done_copy(rdev, fence);
1401         return 0;
1402 }
1403
1404 int r600_irq_process(struct radeon_device *rdev)
1405 {
1406         /* FIXME: implement */
1407         return 0;
1408 }
1409
1410 int r600_irq_set(struct radeon_device *rdev)
1411 {
1412         /* FIXME: implement */
1413         return 0;
1414 }
1415
1416 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1417                          uint32_t tiling_flags, uint32_t pitch,
1418                          uint32_t offset, uint32_t obj_size)
1419 {
1420         /* FIXME: implement */
1421         return 0;
1422 }
1423
1424 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1425 {
1426         /* FIXME: implement */
1427 }
1428
1429
1430 bool r600_card_posted(struct radeon_device *rdev)
1431 {
1432         uint32_t reg;
1433
1434         /* first check CRTCs */
1435         reg = RREG32(D1CRTC_CONTROL) |
1436                 RREG32(D2CRTC_CONTROL);
1437         if (reg & CRTC_EN)
1438                 return true;
1439
1440         /* then check MEM_SIZE, in case the crtcs are off */
1441         if (RREG32(CONFIG_MEMSIZE))
1442                 return true;
1443
1444         return false;
1445 }
1446
1447 int r600_resume(struct radeon_device *rdev)
1448 {
1449         int r;
1450
1451         r600_gpu_reset(rdev);
1452         r600_mc_resume(rdev);
1453         r = r600_pcie_gart_enable(rdev);
1454         if (r)
1455                 return r;
1456         r600_gpu_init(rdev);
1457         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1458         if (r)
1459                 return r;
1460         r = r600_cp_load_microcode(rdev);
1461         if (r)
1462                 return r;
1463         r = r600_cp_resume(rdev);
1464         if (r)
1465                 return r;
1466         r = r600_wb_init(rdev);
1467         if (r)
1468                 return r;
1469         return 0;
1470 }
1471
1472 int r600_suspend(struct radeon_device *rdev)
1473 {
1474         /* FIXME: we should wait for ring to be empty */
1475         r600_cp_stop(rdev);
1476         return 0;
1477 }
1478
1479 /* Plan is to move initialization in that function and use
1480  * helper function so that radeon_device_init pretty much
1481  * do nothing more than calling asic specific function. This
1482  * should also allow to remove a bunch of callback function
1483  * like vram_info.
1484  */
1485 int r600_init(struct radeon_device *rdev)
1486 {
1487         int r;
1488
1489         rdev->new_init_path = true;
1490         r = radeon_dummy_page_init(rdev);
1491         if (r)
1492                 return r;
1493         if (r600_debugfs_mc_info_init(rdev)) {
1494                 DRM_ERROR("Failed to register debugfs file for mc !\n");
1495         }
1496         /* This don't do much */
1497         r = radeon_gem_init(rdev);
1498         if (r)
1499                 return r;
1500         /* Read BIOS */
1501         if (!radeon_get_bios(rdev)) {
1502                 if (ASIC_IS_AVIVO(rdev))
1503                         return -EINVAL;
1504         }
1505         /* Must be an ATOMBIOS */
1506         if (!rdev->is_atom_bios)
1507                 return -EINVAL;
1508         r = radeon_atombios_init(rdev);
1509         if (r)
1510                 return r;
1511         /* Post card if necessary */
1512         if (!r600_card_posted(rdev) && rdev->bios) {
1513                 DRM_INFO("GPU not posted. posting now...\n");
1514                 atom_asic_init(rdev->mode_info.atom_context);
1515         }
1516         /* Initialize scratch registers */
1517         r600_scratch_init(rdev);
1518         /* Initialize surface registers */
1519         radeon_surface_init(rdev);
1520         r = radeon_clocks_init(rdev);
1521         if (r)
1522                 return r;
1523         /* Fence driver */
1524         r = radeon_fence_driver_init(rdev);
1525         if (r)
1526                 return r;
1527         r = r600_mc_init(rdev);
1528         if (r) {
1529                 if (rdev->flags & RADEON_IS_AGP) {
1530                         /* Retry with disabling AGP */
1531                         r600_fini(rdev);
1532                         rdev->flags &= ~RADEON_IS_AGP;
1533                         return r600_init(rdev);
1534                 }
1535                 return r;
1536         }
1537         /* Memory manager */
1538         r = radeon_object_init(rdev);
1539         if (r)
1540                 return r;
1541         rdev->cp.ring_obj = NULL;
1542         r600_ring_init(rdev, 1024 * 1024);
1543
1544         if (!rdev->me_fw || !rdev->pfp_fw) {
1545                 r = r600_cp_init_microcode(rdev);
1546                 if (r) {
1547                         DRM_ERROR("Failed to load firmware!\n");
1548                         return r;
1549                 }
1550         }
1551
1552         r = r600_resume(rdev);
1553         if (r) {
1554                 if (rdev->flags & RADEON_IS_AGP) {
1555                         /* Retry with disabling AGP */
1556                         r600_fini(rdev);
1557                         rdev->flags &= ~RADEON_IS_AGP;
1558                         return r600_init(rdev);
1559                 }
1560                 return r;
1561         }
1562         r = radeon_ib_pool_init(rdev);
1563         if (r) {
1564                 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1565                 return r;
1566         }
1567         r = r600_blit_init(rdev);
1568         if (r) {
1569                 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1570                 return r;
1571         }
1572         r = radeon_ib_test(rdev);
1573         if (r) {
1574                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1575                         return r;
1576         }
1577         return 0;
1578 }
1579
1580 void r600_fini(struct radeon_device *rdev)
1581 {
1582         /* Suspend operations */
1583         r600_suspend(rdev);
1584
1585         r600_blit_fini(rdev);
1586         radeon_ring_fini(rdev);
1587         r600_pcie_gart_disable(rdev);
1588         radeon_gart_table_vram_free(rdev);
1589         radeon_gart_fini(rdev);
1590         radeon_gem_fini(rdev);
1591         radeon_fence_driver_fini(rdev);
1592         radeon_clocks_fini(rdev);
1593 #if __OS_HAS_AGP
1594         if (rdev->flags & RADEON_IS_AGP)
1595                 radeon_agp_fini(rdev);
1596 #endif
1597         radeon_object_fini(rdev);
1598         if (rdev->is_atom_bios)
1599                 radeon_atombios_fini(rdev);
1600         else
1601                 radeon_combios_fini(rdev);
1602         kfree(rdev->bios);
1603         rdev->bios = NULL;
1604         radeon_dummy_page_fini(rdev);
1605 }
1606
1607
1608 /*
1609  * CS stuff
1610  */
1611 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1612 {
1613         /* FIXME: implement */
1614         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1615         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1616         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1617         radeon_ring_write(rdev, ib->length_dw);
1618 }
1619
1620 int r600_ib_test(struct radeon_device *rdev)
1621 {
1622         struct radeon_ib *ib;
1623         uint32_t scratch;
1624         uint32_t tmp = 0;
1625         unsigned i;
1626         int r;
1627
1628         r = radeon_scratch_get(rdev, &scratch);
1629         if (r) {
1630                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1631                 return r;
1632         }
1633         WREG32(scratch, 0xCAFEDEAD);
1634         r = radeon_ib_get(rdev, &ib);
1635         if (r) {
1636                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1637                 return r;
1638         }
1639         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1640         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1641         ib->ptr[2] = 0xDEADBEEF;
1642         ib->ptr[3] = PACKET2(0);
1643         ib->ptr[4] = PACKET2(0);
1644         ib->ptr[5] = PACKET2(0);
1645         ib->ptr[6] = PACKET2(0);
1646         ib->ptr[7] = PACKET2(0);
1647         ib->ptr[8] = PACKET2(0);
1648         ib->ptr[9] = PACKET2(0);
1649         ib->ptr[10] = PACKET2(0);
1650         ib->ptr[11] = PACKET2(0);
1651         ib->ptr[12] = PACKET2(0);
1652         ib->ptr[13] = PACKET2(0);
1653         ib->ptr[14] = PACKET2(0);
1654         ib->ptr[15] = PACKET2(0);
1655         ib->length_dw = 16;
1656         r = radeon_ib_schedule(rdev, ib);
1657         if (r) {
1658                 radeon_scratch_free(rdev, scratch);
1659                 radeon_ib_free(rdev, &ib);
1660                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1661                 return r;
1662         }
1663         r = radeon_fence_wait(ib->fence, false);
1664         if (r) {
1665                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1666                 return r;
1667         }
1668         for (i = 0; i < rdev->usec_timeout; i++) {
1669                 tmp = RREG32(scratch);
1670                 if (tmp == 0xDEADBEEF)
1671                         break;
1672                 DRM_UDELAY(1);
1673         }
1674         if (i < rdev->usec_timeout) {
1675                 DRM_INFO("ib test succeeded in %u usecs\n", i);
1676         } else {
1677                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1678                           scratch, tmp);
1679                 r = -EINVAL;
1680         }
1681         radeon_scratch_free(rdev, scratch);
1682         radeon_ib_free(rdev, &ib);
1683         return r;
1684 }
1685
1686
1687
1688
1689 /*
1690  * Debugfs info
1691  */
1692 #if defined(CONFIG_DEBUG_FS)
1693
1694 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1695 {
1696         struct drm_info_node *node = (struct drm_info_node *) m->private;
1697         struct drm_device *dev = node->minor->dev;
1698         struct radeon_device *rdev = dev->dev_private;
1699         uint32_t rdp, wdp;
1700         unsigned count, i, j;
1701
1702         radeon_ring_free_size(rdev);
1703         rdp = RREG32(CP_RB_RPTR);
1704         wdp = RREG32(CP_RB_WPTR);
1705         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1706         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1707         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1708         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1709         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1710         seq_printf(m, "%u dwords in ring\n", count);
1711         for (j = 0; j <= count; j++) {
1712                 i = (rdp + j) & rdev->cp.ptr_mask;
1713                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1714         }
1715         return 0;
1716 }
1717
1718 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1719 {
1720         struct drm_info_node *node = (struct drm_info_node *) m->private;
1721         struct drm_device *dev = node->minor->dev;
1722         struct radeon_device *rdev = dev->dev_private;
1723
1724         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1725         DREG32_SYS(m, rdev, VM_L2_STATUS);
1726         return 0;
1727 }
1728
1729 static struct drm_info_list r600_mc_info_list[] = {
1730         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1731         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1732 };
1733 #endif
1734
1735 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1736 {
1737 #if defined(CONFIG_DEBUG_FS)
1738         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1739 #else
1740         return 0;
1741 #endif
1742 }