drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "r600d.h"
  36 #include "avivod.h"
  37 #include "atom.h"
  38
  39 #define PFP_UCODE_SIZE 576
  40 #define PM4_UCODE_SIZE 1792
  41 #define R700_PFP_UCODE_SIZE 848
  42 #define R700_PM4_UCODE_SIZE 1360
  43
  44 /* Firmware Names */
  45 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  46 MODULE_FIRMWARE("radeon/R600_me.bin");
  47 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  48 MODULE_FIRMWARE("radeon/RV610_me.bin");
  49 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV630_me.bin");
  51 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV620_me.bin");
  53 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV635_me.bin");
  55 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV670_me.bin");
  57 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RS780_me.bin");
  59 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV770_me.bin");
  61 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV730_me.bin");
  63 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV710_me.bin");
  65
  66 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  67
  68 /* This files gather functions specifics to:
  69  * r600,rv610,rv630,rv620,rv635,rv670
  70  *
  71  * Some of these functions might be used by newer ASICs.
  72  */
  73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  74 void r600_gpu_init(struct radeon_device *rdev);
  75 void r600_fini(struct radeon_device *rdev);
  76
  77
  78 /*
  79  * R600 PCIE GART
  80  */
  81 int r600_gart_clear_page(struct radeon_device *rdev, int i)
  82 {
  83         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  84         u64 pte;
  85
  86         if (i < 0 || i > rdev->gart.num_gpu_pages)
  87                 return -EINVAL;
  88         pte = 0;
  89         writeq(pte, ((void __iomem *)ptr) + (i * 8));
  90         return 0;
  91 }
  92
  93 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
  94 {
  95         unsigned i;
  96         u32 tmp;
  97
  98         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
  99         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 100         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 101         for (i = 0; i < rdev->usec_timeout; i++) {
 102                 /* read MC_STATUS */
 103                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 104                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 105                 if (tmp == 2) {
 106                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 107                         return;
 108                 }
 109                 if (tmp) {
 110                         return;
 111                 }
 112                 udelay(1);
 113         }
 114 }
 115
 116 int r600_pcie_gart_init(struct radeon_device *rdev)
 117 {
 118         int r;
 119
 120         if (rdev->gart.table.vram.robj) {
 121                 WARN(1, "R600 PCIE GART already initialized.\n");
 122                 return 0;
 123         }
 124         /* Initialize common gart structure */
 125         r = radeon_gart_init(rdev);
 126         if (r)
 127                 return r;
 128         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 129         return radeon_gart_table_vram_alloc(rdev);
 130 }
 131
 132 int r600_pcie_gart_enable(struct radeon_device *rdev)
 133 {
 134         u32 tmp;
 135         int r, i;
 136
 137         if (rdev->gart.table.vram.robj == NULL) {
 138                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 139                 return -EINVAL;
 140         }
 141         r = radeon_gart_table_vram_pin(rdev);
 142         if (r)
 143                 return r;
 144         for (i = 0; i < rdev->gart.num_gpu_pages; i++)
 145                 r600_gart_clear_page(rdev, i);
 146         /* Setup L2 cache */
 147         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 148                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 149                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 150         WREG32(VM_L2_CNTL2, 0);
 151         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 152         /* Setup TLB control */
 153         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 154                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 155                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 156                 ENABLE_WAIT_L2_QUERY;
 157         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 158         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 159         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 160         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 161         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 162         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 163         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 164         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 165         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 166         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 167         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 168         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 169         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 170         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 171         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 172         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 173         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 174         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 175                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 176         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 177                         (u32)(rdev->dummy_page.addr >> 12));
 178         for (i = 1; i < 7; i++)
 179                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 180
 181         r600_pcie_gart_tlb_flush(rdev);
 182         rdev->gart.ready = true;
 183         return 0;
 184 }
 185
 186 void r600_pcie_gart_disable(struct radeon_device *rdev)
 187 {
 188         u32 tmp;
 189         int i;
 190
 191         /* Disable all tables */
 192         for (i = 0; i < 7; i++)
 193                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 194
 195         /* Disable L2 cache */
 196         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 197                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 198         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 199         /* Setup L1 TLB control */
 200         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 201                 ENABLE_WAIT_L2_QUERY;
 202         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 203         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 204         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 205         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 206         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 207         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 208         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 209         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 210         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 211         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 212         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 213         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 214         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 215         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 216         if (rdev->gart.table.vram.robj) {
 217                 radeon_object_kunmap(rdev->gart.table.vram.robj);
 218                 radeon_object_unpin(rdev->gart.table.vram.robj);
 219         }
 220 }
 221
 222 void r600_pcie_gart_fini(struct radeon_device *rdev)
 223 {
 224         r600_pcie_gart_disable(rdev);
 225         radeon_gart_table_vram_free(rdev);
 226         radeon_gart_fini(rdev);
 227 }
 228
 229 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 230 {
 231         unsigned i;
 232         u32 tmp;
 233
 234         for (i = 0; i < rdev->usec_timeout; i++) {
 235                 /* read MC_STATUS */
 236                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 237                 if (!tmp)
 238                         return 0;
 239                 udelay(1);
 240         }
 241         return -1;
 242 }
 243
 244 static void r600_mc_resume(struct radeon_device *rdev)
 245 {
 246         u32 d1vga_control, d2vga_control;
 247         u32 vga_render_control, vga_hdp_control;
 248         u32 d1crtc_control, d2crtc_control;
 249         u32 new_d1grph_primary, new_d1grph_secondary;
 250         u32 new_d2grph_primary, new_d2grph_secondary;
 251         u64 old_vram_start;
 252         u32 tmp;
 253         int i, j;
 254
 255         /* Initialize HDP */
 256         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 257                 WREG32((0x2c14 + j), 0x00000000);
 258                 WREG32((0x2c18 + j), 0x00000000);
 259                 WREG32((0x2c1c + j), 0x00000000);
 260                 WREG32((0x2c20 + j), 0x00000000);
 261                 WREG32((0x2c24 + j), 0x00000000);
 262         }
 263         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 264
 265         d1vga_control = RREG32(D1VGA_CONTROL);
 266         d2vga_control = RREG32(D2VGA_CONTROL);
 267         vga_render_control = RREG32(VGA_RENDER_CONTROL);
 268         vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 269         d1crtc_control = RREG32(D1CRTC_CONTROL);
 270         d2crtc_control = RREG32(D2CRTC_CONTROL);
 271         old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 272         new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
 273         new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
 274         new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
 275         new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
 276         new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
 277         new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
 278         new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
 279         new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
 280
 281         /* Stop all video */
 282         WREG32(D1VGA_CONTROL, 0);
 283         WREG32(D2VGA_CONTROL, 0);
 284         WREG32(VGA_RENDER_CONTROL, 0);
 285         WREG32(D1CRTC_UPDATE_LOCK, 1);
 286         WREG32(D2CRTC_UPDATE_LOCK, 1);
 287         WREG32(D1CRTC_CONTROL, 0);
 288         WREG32(D2CRTC_CONTROL, 0);
 289         WREG32(D1CRTC_UPDATE_LOCK, 0);
 290         WREG32(D2CRTC_UPDATE_LOCK, 0);
 291
 292         mdelay(1);
 293         if (r600_mc_wait_for_idle(rdev)) {
 294                 printk(KERN_WARNING "[drm] MC not idle !\n");
 295         }
 296
 297         /* Lockout access through VGA aperture*/
 298         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 299
 300         /* Update configuration */
 301         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 302         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
 303         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 304         tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
 305         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 306         WREG32(MC_VM_FB_LOCATION, tmp);
 307         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 308         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 309         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
 310         if (rdev->flags & RADEON_IS_AGP) {
 311                 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
 312                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 313                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 314         } else {
 315                 WREG32(MC_VM_AGP_BASE, 0);
 316                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 317                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 318         }
 319         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
 320         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
 321         WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
 322         WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
 323         WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
 324
 325         /* Unlock host access */
 326         WREG32(VGA_HDP_CONTROL, vga_hdp_control);
 327
 328         mdelay(1);
 329         if (r600_mc_wait_for_idle(rdev)) {
 330                 printk(KERN_WARNING "[drm] MC not idle !\n");
 331         }
 332
 333         /* Restore video state */
 334         WREG32(D1CRTC_UPDATE_LOCK, 1);
 335         WREG32(D2CRTC_UPDATE_LOCK, 1);
 336         WREG32(D1CRTC_CONTROL, d1crtc_control);
 337         WREG32(D2CRTC_CONTROL, d2crtc_control);
 338         WREG32(D1CRTC_UPDATE_LOCK, 0);
 339         WREG32(D2CRTC_UPDATE_LOCK, 0);
 340         WREG32(D1VGA_CONTROL, d1vga_control);
 341         WREG32(D2VGA_CONTROL, d2vga_control);
 342         WREG32(VGA_RENDER_CONTROL, vga_render_control);
 343 }
 344
 345 int r600_mc_init(struct radeon_device *rdev)
 346 {
 347         fixed20_12 a;
 348         u32 tmp;
 349         int chansize;
 350         int r;
 351
 352         /* Get VRAM informations */
 353         rdev->mc.vram_width = 128;
 354         rdev->mc.vram_is_ddr = true;
 355         tmp = RREG32(RAMCFG);
 356         if (tmp & CHANSIZE_OVERRIDE) {
 357                 chansize = 16;
 358         } else if (tmp & CHANSIZE_MASK) {
 359                 chansize = 64;
 360         } else {
 361                 chansize = 32;
 362         }
 363         if (rdev->family == CHIP_R600) {
 364                 rdev->mc.vram_width = 8 * chansize;
 365         } else if (rdev->family == CHIP_RV670) {
 366                 rdev->mc.vram_width = 4 * chansize;
 367         } else if ((rdev->family == CHIP_RV610) ||
 368                         (rdev->family == CHIP_RV620)) {
 369                 rdev->mc.vram_width = chansize;
 370         } else if ((rdev->family == CHIP_RV630) ||
 371                         (rdev->family == CHIP_RV635)) {
 372                 rdev->mc.vram_width = 2 * chansize;
 373         }
 374         /* Could aper size report 0 ? */
 375         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 376         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 377         /* Setup GPU memory space */
 378         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 379         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 380         if (rdev->flags & RADEON_IS_AGP) {
 381                 r = radeon_agp_init(rdev);
 382                 if (r)
 383                         return r;
 384                 /* gtt_size is setup by radeon_agp_init */
 385                 rdev->mc.gtt_location = rdev->mc.agp_base;
 386                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 387                 /* Try to put vram before or after AGP because we
 388                  * we want SYSTEM_APERTURE to cover both VRAM and
 389                  * AGP so that GPU can catch out of VRAM/AGP access
 390                  */
 391                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 392                         /* Enought place before */
 393                         rdev->mc.vram_location = rdev->mc.gtt_location -
 394                                                         rdev->mc.mc_vram_size;
 395                 } else if (tmp > rdev->mc.mc_vram_size) {
 396                         /* Enought place after */
 397                         rdev->mc.vram_location = rdev->mc.gtt_location +
 398                                                         rdev->mc.gtt_size;
 399                 } else {
 400                         /* Try to setup VRAM then AGP might not
 401                          * not work on some card
 402                          */
 403                         rdev->mc.vram_location = 0x00000000UL;
 404                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 405                 }
 406         } else {
 407                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 408                         rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 409                                                                 0xFFFF) << 24;
 410                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 411                         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 412                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 413                                 /* Enough place after vram */
 414                                 rdev->mc.gtt_location = tmp;
 415                         } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 416                                 /* Enough place before vram */
 417                                 rdev->mc.gtt_location = 0;
 418                         } else {
 419                                 /* Not enough place after or before shrink
 420                                  * gart size
 421                                  */
 422                                 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
 423                                         rdev->mc.gtt_location = 0;
 424                                         rdev->mc.gtt_size = rdev->mc.vram_location;
 425                                 } else {
 426                                         rdev->mc.gtt_location = tmp;
 427                                         rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 428                                 }
 429                         }
 430                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 431                 } else {
 432                         rdev->mc.vram_location = 0x00000000UL;
 433                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 434                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 435                 }
 436         }
 437         rdev->mc.vram_start = rdev->mc.vram_location;
 438         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 439         rdev->mc.gtt_start = rdev->mc.gtt_location;
 440         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
 441         /* FIXME: we should enforce default clock in case GPU is not in
 442          * default setup
 443          */
 444         a.full = rfixed_const(100);
 445         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 446         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 447         return 0;
 448 }
 449
 450 /* We doesn't check that the GPU really needs a reset we simply do the
 451  * reset, it's up to the caller to determine if the GPU needs one. We
 452  * might add an helper function to check that.
 453  */
 454 int r600_gpu_soft_reset(struct radeon_device *rdev)
 455 {
 456         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 457                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 458                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 459                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 460                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 461                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 462                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 463                                 S_008010_GUI_ACTIVE(1);
 464         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 465                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 466                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 467                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 468                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 469                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 470                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 471                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 472         u32 srbm_reset = 0;
 473
 474         /* Disable CP parsing/prefetching */
 475         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 476         /* Check if any of the rendering block is busy and reset it */
 477         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 478             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 479                 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
 480                         S_008020_SOFT_RESET_DB(1) |
 481                         S_008020_SOFT_RESET_CB(1) |
 482                         S_008020_SOFT_RESET_PA(1) |
 483                         S_008020_SOFT_RESET_SC(1) |
 484                         S_008020_SOFT_RESET_SMX(1) |
 485                         S_008020_SOFT_RESET_SPI(1) |
 486                         S_008020_SOFT_RESET_SX(1) |
 487                         S_008020_SOFT_RESET_SH(1) |
 488                         S_008020_SOFT_RESET_TC(1) |
 489                         S_008020_SOFT_RESET_TA(1) |
 490                         S_008020_SOFT_RESET_VC(1) |
 491                         S_008020_SOFT_RESET_VGT(1));
 492                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 493                 udelay(50);
 494                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 495                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 496         }
 497         /* Reset CP (we always reset CP) */
 498         WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
 499         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 500         udelay(50);
 501         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 502         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 503         /* Reset others GPU block if necessary */
 504         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 505                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 506         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 507                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 508         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 509                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 510         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 511                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 512         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 513                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 514         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 515                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 516         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 517                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 518         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 519                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 520         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 521                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 522         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 523                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 524         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 525                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 526         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 527         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 528         udelay(50);
 529         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 530         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 531         /* Wait a little for things to settle down */
 532         udelay(50);
 533         return 0;
 534 }
 535
 536 int r600_gpu_reset(struct radeon_device *rdev)
 537 {
 538         return r600_gpu_soft_reset(rdev);
 539 }
 540
 541 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 542                                              u32 num_backends,
 543                                              u32 backend_disable_mask)
 544 {
 545         u32 backend_map = 0;
 546         u32 enabled_backends_mask;
 547         u32 enabled_backends_count;
 548         u32 cur_pipe;
 549         u32 swizzle_pipe[R6XX_MAX_PIPES];
 550         u32 cur_backend;
 551         u32 i;
 552
 553         if (num_tile_pipes > R6XX_MAX_PIPES)
 554                 num_tile_pipes = R6XX_MAX_PIPES;
 555         if (num_tile_pipes < 1)
 556                 num_tile_pipes = 1;
 557         if (num_backends > R6XX_MAX_BACKENDS)
 558                 num_backends = R6XX_MAX_BACKENDS;
 559         if (num_backends < 1)
 560                 num_backends = 1;
 561
 562         enabled_backends_mask = 0;
 563         enabled_backends_count = 0;
 564         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 565                 if (((backend_disable_mask >> i) & 1) == 0) {
 566                         enabled_backends_mask |= (1 << i);
 567                         ++enabled_backends_count;
 568                 }
 569                 if (enabled_backends_count == num_backends)
 570                         break;
 571         }
 572
 573         if (enabled_backends_count == 0) {
 574                 enabled_backends_mask = 1;
 575                 enabled_backends_count = 1;
 576         }
 577
 578         if (enabled_backends_count != num_backends)
 579                 num_backends = enabled_backends_count;
 580
 581         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 582         switch (num_tile_pipes) {
 583         case 1:
 584                 swizzle_pipe[0] = 0;
 585                 break;
 586         case 2:
 587                 swizzle_pipe[0] = 0;
 588                 swizzle_pipe[1] = 1;
 589                 break;
 590         case 3:
 591                 swizzle_pipe[0] = 0;
 592                 swizzle_pipe[1] = 1;
 593                 swizzle_pipe[2] = 2;
 594                 break;
 595         case 4:
 596                 swizzle_pipe[0] = 0;
 597                 swizzle_pipe[1] = 1;
 598                 swizzle_pipe[2] = 2;
 599                 swizzle_pipe[3] = 3;
 600                 break;
 601         case 5:
 602                 swizzle_pipe[0] = 0;
 603                 swizzle_pipe[1] = 1;
 604                 swizzle_pipe[2] = 2;
 605                 swizzle_pipe[3] = 3;
 606                 swizzle_pipe[4] = 4;
 607                 break;
 608         case 6:
 609                 swizzle_pipe[0] = 0;
 610                 swizzle_pipe[1] = 2;
 611                 swizzle_pipe[2] = 4;
 612                 swizzle_pipe[3] = 5;
 613                 swizzle_pipe[4] = 1;
 614                 swizzle_pipe[5] = 3;
 615                 break;
 616         case 7:
 617                 swizzle_pipe[0] = 0;
 618                 swizzle_pipe[1] = 2;
 619                 swizzle_pipe[2] = 4;
 620                 swizzle_pipe[3] = 6;
 621                 swizzle_pipe[4] = 1;
 622                 swizzle_pipe[5] = 3;
 623                 swizzle_pipe[6] = 5;
 624                 break;
 625         case 8:
 626                 swizzle_pipe[0] = 0;
 627                 swizzle_pipe[1] = 2;
 628                 swizzle_pipe[2] = 4;
 629                 swizzle_pipe[3] = 6;
 630                 swizzle_pipe[4] = 1;
 631                 swizzle_pipe[5] = 3;
 632                 swizzle_pipe[6] = 5;
 633                 swizzle_pipe[7] = 7;
 634                 break;
 635         }
 636
 637         cur_backend = 0;
 638         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 639                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 640                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 641
 642                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 643
 644                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 645         }
 646
 647         return backend_map;
 648 }
 649
 650 int r600_count_pipe_bits(uint32_t val)
 651 {
 652         int i, ret = 0;
 653
 654         for (i = 0; i < 32; i++) {
 655                 ret += val & 1;
 656                 val >>= 1;
 657         }
 658         return ret;
 659 }
 660
 661 void r600_gpu_init(struct radeon_device *rdev)
 662 {
 663         u32 tiling_config;
 664         u32 ramcfg;
 665         u32 tmp;
 666         int i, j;
 667         u32 sq_config;
 668         u32 sq_gpr_resource_mgmt_1 = 0;
 669         u32 sq_gpr_resource_mgmt_2 = 0;
 670         u32 sq_thread_resource_mgmt = 0;
 671         u32 sq_stack_resource_mgmt_1 = 0;
 672         u32 sq_stack_resource_mgmt_2 = 0;
 673
 674         /* FIXME: implement */
 675         switch (rdev->family) {
 676         case CHIP_R600:
 677                 rdev->config.r600.max_pipes = 4;
 678                 rdev->config.r600.max_tile_pipes = 8;
 679                 rdev->config.r600.max_simds = 4;
 680                 rdev->config.r600.max_backends = 4;
 681                 rdev->config.r600.max_gprs = 256;
 682                 rdev->config.r600.max_threads = 192;
 683                 rdev->config.r600.max_stack_entries = 256;
 684                 rdev->config.r600.max_hw_contexts = 8;
 685                 rdev->config.r600.max_gs_threads = 16;
 686                 rdev->config.r600.sx_max_export_size = 128;
 687                 rdev->config.r600.sx_max_export_pos_size = 16;
 688                 rdev->config.r600.sx_max_export_smx_size = 128;
 689                 rdev->config.r600.sq_num_cf_insts = 2;
 690                 break;
 691         case CHIP_RV630:
 692         case CHIP_RV635:
 693                 rdev->config.r600.max_pipes = 2;
 694                 rdev->config.r600.max_tile_pipes = 2;
 695                 rdev->config.r600.max_simds = 3;
 696                 rdev->config.r600.max_backends = 1;
 697                 rdev->config.r600.max_gprs = 128;
 698                 rdev->config.r600.max_threads = 192;
 699                 rdev->config.r600.max_stack_entries = 128;
 700                 rdev->config.r600.max_hw_contexts = 8;
 701                 rdev->config.r600.max_gs_threads = 4;
 702                 rdev->config.r600.sx_max_export_size = 128;
 703                 rdev->config.r600.sx_max_export_pos_size = 16;
 704                 rdev->config.r600.sx_max_export_smx_size = 128;
 705                 rdev->config.r600.sq_num_cf_insts = 2;
 706                 break;
 707         case CHIP_RV610:
 708         case CHIP_RV620:
 709         case CHIP_RS780:
 710         case CHIP_RS880:
 711                 rdev->config.r600.max_pipes = 1;
 712                 rdev->config.r600.max_tile_pipes = 1;
 713                 rdev->config.r600.max_simds = 2;
 714                 rdev->config.r600.max_backends = 1;
 715                 rdev->config.r600.max_gprs = 128;
 716                 rdev->config.r600.max_threads = 192;
 717                 rdev->config.r600.max_stack_entries = 128;
 718                 rdev->config.r600.max_hw_contexts = 4;
 719                 rdev->config.r600.max_gs_threads = 4;
 720                 rdev->config.r600.sx_max_export_size = 128;
 721                 rdev->config.r600.sx_max_export_pos_size = 16;
 722                 rdev->config.r600.sx_max_export_smx_size = 128;
 723                 rdev->config.r600.sq_num_cf_insts = 1;
 724                 break;
 725         case CHIP_RV670:
 726                 rdev->config.r600.max_pipes = 4;
 727                 rdev->config.r600.max_tile_pipes = 4;
 728                 rdev->config.r600.max_simds = 4;
 729                 rdev->config.r600.max_backends = 4;
 730                 rdev->config.r600.max_gprs = 192;
 731                 rdev->config.r600.max_threads = 192;
 732                 rdev->config.r600.max_stack_entries = 256;
 733                 rdev->config.r600.max_hw_contexts = 8;
 734                 rdev->config.r600.max_gs_threads = 16;
 735                 rdev->config.r600.sx_max_export_size = 128;
 736                 rdev->config.r600.sx_max_export_pos_size = 16;
 737                 rdev->config.r600.sx_max_export_smx_size = 128;
 738                 rdev->config.r600.sq_num_cf_insts = 2;
 739                 break;
 740         default:
 741                 break;
 742         }
 743
 744         /* Initialize HDP */
 745         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 746                 WREG32((0x2c14 + j), 0x00000000);
 747                 WREG32((0x2c18 + j), 0x00000000);
 748                 WREG32((0x2c1c + j), 0x00000000);
 749                 WREG32((0x2c20 + j), 0x00000000);
 750                 WREG32((0x2c24 + j), 0x00000000);
 751         }
 752
 753         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 754
 755         /* Setup tiling */
 756         tiling_config = 0;
 757         ramcfg = RREG32(RAMCFG);
 758         switch (rdev->config.r600.max_tile_pipes) {
 759         case 1:
 760                 tiling_config |= PIPE_TILING(0);
 761                 break;
 762         case 2:
 763                 tiling_config |= PIPE_TILING(1);
 764                 break;
 765         case 4:
 766                 tiling_config |= PIPE_TILING(2);
 767                 break;
 768         case 8:
 769                 tiling_config |= PIPE_TILING(3);
 770                 break;
 771         default:
 772                 break;
 773         }
 774         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 775         tiling_config |= GROUP_SIZE(0);
 776         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
 777         if (tmp > 3) {
 778                 tiling_config |= ROW_TILING(3);
 779                 tiling_config |= SAMPLE_SPLIT(3);
 780         } else {
 781                 tiling_config |= ROW_TILING(tmp);
 782                 tiling_config |= SAMPLE_SPLIT(tmp);
 783         }
 784         tiling_config |= BANK_SWAPS(1);
 785         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
 786                                                 rdev->config.r600.max_backends,
 787                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
 788         tiling_config |= BACKEND_MAP(tmp);
 789         WREG32(GB_TILING_CONFIG, tiling_config);
 790         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
 791         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
 792
 793         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
 794         WREG32(CC_RB_BACKEND_DISABLE, tmp);
 795
 796         /* Setup pipes */
 797         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
 798         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
 799         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
 800         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
 801
 802         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
 803         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
 804         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 805
 806         /* Setup some CP states */
 807         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
 808         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
 809
 810         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
 811                              SYNC_WALKER | SYNC_ALIGNER));
 812         /* Setup various GPU states */
 813         if (rdev->family == CHIP_RV670)
 814                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
 815
 816         tmp = RREG32(SX_DEBUG_1);
 817         tmp |= SMX_EVENT_RELEASE;
 818         if ((rdev->family > CHIP_R600))
 819                 tmp |= ENABLE_NEW_SMX_ADDRESS;
 820         WREG32(SX_DEBUG_1, tmp);
 821
 822         if (((rdev->family) == CHIP_R600) ||
 823             ((rdev->family) == CHIP_RV630) ||
 824             ((rdev->family) == CHIP_RV610) ||
 825             ((rdev->family) == CHIP_RV620) ||
 826             ((rdev->family) == CHIP_RS780)) {
 827                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 828         } else {
 829                 WREG32(DB_DEBUG, 0);
 830         }
 831         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
 832                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
 833
 834         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 835         WREG32(VGT_NUM_INSTANCES, 0);
 836
 837         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 838         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
 839
 840         tmp = RREG32(SQ_MS_FIFO_SIZES);
 841         if (((rdev->family) == CHIP_RV610) ||
 842             ((rdev->family) == CHIP_RV620) ||
 843             ((rdev->family) == CHIP_RS780)) {
 844                 tmp = (CACHE_FIFO_SIZE(0xa) |
 845                        FETCH_FIFO_HIWATER(0xa) |
 846                        DONE_FIFO_HIWATER(0xe0) |
 847                        ALU_UPDATE_FIFO_HIWATER(0x8));
 848         } else if (((rdev->family) == CHIP_R600) ||
 849                    ((rdev->family) == CHIP_RV630)) {
 850                 tmp &= ~DONE_FIFO_HIWATER(0xff);
 851                 tmp |= DONE_FIFO_HIWATER(0x4);
 852         }
 853         WREG32(SQ_MS_FIFO_SIZES, tmp);
 854
 855         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 856          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 857          */
 858         sq_config = RREG32(SQ_CONFIG);
 859         sq_config &= ~(PS_PRIO(3) |
 860                        VS_PRIO(3) |
 861                        GS_PRIO(3) |
 862                        ES_PRIO(3));
 863         sq_config |= (DX9_CONSTS |
 864                       VC_ENABLE |
 865                       PS_PRIO(0) |
 866                       VS_PRIO(1) |
 867                       GS_PRIO(2) |
 868                       ES_PRIO(3));
 869
 870         if ((rdev->family) == CHIP_R600) {
 871                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
 872                                           NUM_VS_GPRS(124) |
 873                                           NUM_CLAUSE_TEMP_GPRS(4));
 874                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
 875                                           NUM_ES_GPRS(0));
 876                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
 877                                            NUM_VS_THREADS(48) |
 878                                            NUM_GS_THREADS(4) |
 879                                            NUM_ES_THREADS(4));
 880                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
 881                                             NUM_VS_STACK_ENTRIES(128));
 882                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
 883                                             NUM_ES_STACK_ENTRIES(0));
 884         } else if (((rdev->family) == CHIP_RV610) ||
 885                    ((rdev->family) == CHIP_RV620) ||
 886                    ((rdev->family) == CHIP_RS780)) {
 887                 /* no vertex cache */
 888                 sq_config &= ~VC_ENABLE;
 889
 890                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 891                                           NUM_VS_GPRS(44) |
 892                                           NUM_CLAUSE_TEMP_GPRS(2));
 893                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 894                                           NUM_ES_GPRS(17));
 895                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 896                                            NUM_VS_THREADS(78) |
 897                                            NUM_GS_THREADS(4) |
 898                                            NUM_ES_THREADS(31));
 899                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 900                                             NUM_VS_STACK_ENTRIES(40));
 901                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 902                                             NUM_ES_STACK_ENTRIES(16));
 903         } else if (((rdev->family) == CHIP_RV630) ||
 904                    ((rdev->family) == CHIP_RV635)) {
 905                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 906                                           NUM_VS_GPRS(44) |
 907                                           NUM_CLAUSE_TEMP_GPRS(2));
 908                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
 909                                           NUM_ES_GPRS(18));
 910                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 911                                            NUM_VS_THREADS(78) |
 912                                            NUM_GS_THREADS(4) |
 913                                            NUM_ES_THREADS(31));
 914                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
 915                                             NUM_VS_STACK_ENTRIES(40));
 916                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
 917                                             NUM_ES_STACK_ENTRIES(16));
 918         } else if ((rdev->family) == CHIP_RV670) {
 919                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
 920                                           NUM_VS_GPRS(44) |
 921                                           NUM_CLAUSE_TEMP_GPRS(2));
 922                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
 923                                           NUM_ES_GPRS(17));
 924                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
 925                                            NUM_VS_THREADS(78) |
 926                                            NUM_GS_THREADS(4) |
 927                                            NUM_ES_THREADS(31));
 928                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
 929                                             NUM_VS_STACK_ENTRIES(64));
 930                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
 931                                             NUM_ES_STACK_ENTRIES(64));
 932         }
 933
 934         WREG32(SQ_CONFIG, sq_config);
 935         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
 936         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
 937         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 938         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
 939         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
 940
 941         if (((rdev->family) == CHIP_RV610) ||
 942             ((rdev->family) == CHIP_RV620) ||
 943             ((rdev->family) == CHIP_RS780)) {
 944                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
 945         } else {
 946                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
 947         }
 948
 949         /* More default values. 2D/3D driver should adjust as needed */
 950         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
 951                                          S1_X(0x4) | S1_Y(0xc)));
 952         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
 953                                          S1_X(0x2) | S1_Y(0x2) |
 954                                          S2_X(0xa) | S2_Y(0x6) |
 955                                          S3_X(0x6) | S3_Y(0xa)));
 956         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
 957                                              S1_X(0x4) | S1_Y(0xc) |
 958                                              S2_X(0x1) | S2_Y(0x6) |
 959                                              S3_X(0xa) | S3_Y(0xe)));
 960         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
 961                                              S5_X(0x0) | S5_Y(0x0) |
 962                                              S6_X(0xb) | S6_Y(0x4) |
 963                                              S7_X(0x7) | S7_Y(0x8)));
 964
 965         WREG32(VGT_STRMOUT_EN, 0);
 966         tmp = rdev->config.r600.max_pipes * 16;
 967         switch (rdev->family) {
 968         case CHIP_RV610:
 969         case CHIP_RS780:
 970         case CHIP_RV620:
 971                 tmp += 32;
 972                 break;
 973         case CHIP_RV670:
 974                 tmp += 128;
 975                 break;
 976         default:
 977                 break;
 978         }
 979         if (tmp > 256) {
 980                 tmp = 256;
 981         }
 982         WREG32(VGT_ES_PER_GS, 128);
 983         WREG32(VGT_GS_PER_ES, tmp);
 984         WREG32(VGT_GS_PER_VS, 2);
 985         WREG32(VGT_GS_VERTEX_REUSE, 16);
 986
 987         /* more default values. 2D/3D driver should adjust as needed */
 988         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 989         WREG32(VGT_STRMOUT_EN, 0);
 990         WREG32(SX_MISC, 0);
 991         WREG32(PA_SC_MODE_CNTL, 0);
 992         WREG32(PA_SC_AA_CONFIG, 0);
 993         WREG32(PA_SC_LINE_STIPPLE, 0);
 994         WREG32(SPI_INPUT_Z, 0);
 995         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 996         WREG32(CB_COLOR7_FRAG, 0);
 997
 998         /* Clear render buffer base addresses */
 999         WREG32(CB_COLOR0_BASE, 0);
1000         WREG32(CB_COLOR1_BASE, 0);
1001         WREG32(CB_COLOR2_BASE, 0);
1002         WREG32(CB_COLOR3_BASE, 0);
1003         WREG32(CB_COLOR4_BASE, 0);
1004         WREG32(CB_COLOR5_BASE, 0);
1005         WREG32(CB_COLOR6_BASE, 0);
1006         WREG32(CB_COLOR7_BASE, 0);
1007         WREG32(CB_COLOR7_FRAG, 0);
1008
1009         switch (rdev->family) {
1010         case CHIP_RV610:
1011         case CHIP_RS780:
1012         case CHIP_RV620:
1013                 tmp = TC_L2_SIZE(8);
1014                 break;
1015         case CHIP_RV630:
1016         case CHIP_RV635:
1017                 tmp = TC_L2_SIZE(4);
1018                 break;
1019         case CHIP_R600:
1020                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1021                 break;
1022         default:
1023                 tmp = TC_L2_SIZE(0);
1024                 break;
1025         }
1026         WREG32(TC_CNTL, tmp);
1027
1028         tmp = RREG32(HDP_HOST_PATH_CNTL);
1029         WREG32(HDP_HOST_PATH_CNTL, tmp);
1030
1031         tmp = RREG32(ARB_POP);
1032         tmp |= ENABLE_TC128;
1033         WREG32(ARB_POP, tmp);
1034
1035         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1036         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1037                                NUM_CLIP_SEQ(3)));
1038         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1039 }
1040
1041
1042 /*
1043  * Indirect registers accessor
1044  */
1045 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1046 {
1047         u32 r;
1048
1049         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1050         (void)RREG32(PCIE_PORT_INDEX);
1051         r = RREG32(PCIE_PORT_DATA);
1052         return r;
1053 }
1054
1055 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1056 {
1057         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1058         (void)RREG32(PCIE_PORT_INDEX);
1059         WREG32(PCIE_PORT_DATA, (v));
1060         (void)RREG32(PCIE_PORT_DATA);
1061 }
1062
1063
1064 /*
1065  * CP & Ring
1066  */
1067 void r600_cp_stop(struct radeon_device *rdev)
1068 {
1069         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1070 }
1071
1072 int r600_cp_init_microcode(struct radeon_device *rdev)
1073 {
1074         struct platform_device *pdev;
1075         const char *chip_name;
1076         size_t pfp_req_size, me_req_size;
1077         char fw_name[30];
1078         int err;
1079
1080         DRM_DEBUG("\n");
1081
1082         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1083         err = IS_ERR(pdev);
1084         if (err) {
1085                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1086                 return -EINVAL;
1087         }
1088
1089         switch (rdev->family) {
1090         case CHIP_R600: chip_name = "R600"; break;
1091         case CHIP_RV610: chip_name = "RV610"; break;
1092         case CHIP_RV630: chip_name = "RV630"; break;
1093         case CHIP_RV620: chip_name = "RV620"; break;
1094         case CHIP_RV635: chip_name = "RV635"; break;
1095         case CHIP_RV670: chip_name = "RV670"; break;
1096         case CHIP_RS780:
1097         case CHIP_RS880: chip_name = "RS780"; break;
1098         case CHIP_RV770: chip_name = "RV770"; break;
1099         case CHIP_RV730:
1100         case CHIP_RV740: chip_name = "RV730"; break;
1101         case CHIP_RV710: chip_name = "RV710"; break;
1102         default: BUG();
1103         }
1104
1105         if (rdev->family >= CHIP_RV770) {
1106                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1107                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1108         } else {
1109                 pfp_req_size = PFP_UCODE_SIZE * 4;
1110                 me_req_size = PM4_UCODE_SIZE * 12;
1111         }
1112
1113         DRM_INFO("Loading %s CP Microcode\n", chip_name);
1114
1115         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1116         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1117         if (err)
1118                 goto out;
1119         if (rdev->pfp_fw->size != pfp_req_size) {
1120                 printk(KERN_ERR
1121                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1122                        rdev->pfp_fw->size, fw_name);
1123                 err = -EINVAL;
1124                 goto out;
1125         }
1126
1127         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1128         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1129         if (err)
1130                 goto out;
1131         if (rdev->me_fw->size != me_req_size) {
1132                 printk(KERN_ERR
1133                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1134                        rdev->me_fw->size, fw_name);
1135                 err = -EINVAL;
1136         }
1137 out:
1138         platform_device_unregister(pdev);
1139
1140         if (err) {
1141                 if (err != -EINVAL)
1142                         printk(KERN_ERR
1143                                "r600_cp: Failed to load firmware \"%s\"\n",
1144                                fw_name);
1145                 release_firmware(rdev->pfp_fw);
1146                 rdev->pfp_fw = NULL;
1147                 release_firmware(rdev->me_fw);
1148                 rdev->me_fw = NULL;
1149         }
1150         return err;
1151 }
1152
1153 static int r600_cp_load_microcode(struct radeon_device *rdev)
1154 {
1155         const __be32 *fw_data;
1156         int i;
1157
1158         if (!rdev->me_fw || !rdev->pfp_fw)
1159                 return -EINVAL;
1160
1161         r600_cp_stop(rdev);
1162
1163         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1164
1165         /* Reset cp */
1166         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1167         RREG32(GRBM_SOFT_RESET);
1168         mdelay(15);
1169         WREG32(GRBM_SOFT_RESET, 0);
1170
1171         WREG32(CP_ME_RAM_WADDR, 0);
1172
1173         fw_data = (const __be32 *)rdev->me_fw->data;
1174         WREG32(CP_ME_RAM_WADDR, 0);
1175         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1176                 WREG32(CP_ME_RAM_DATA,
1177                        be32_to_cpup(fw_data++));
1178
1179         fw_data = (const __be32 *)rdev->pfp_fw->data;
1180         WREG32(CP_PFP_UCODE_ADDR, 0);
1181         for (i = 0; i < PFP_UCODE_SIZE; i++)
1182                 WREG32(CP_PFP_UCODE_DATA,
1183                        be32_to_cpup(fw_data++));
1184
1185         WREG32(CP_PFP_UCODE_ADDR, 0);
1186         WREG32(CP_ME_RAM_WADDR, 0);
1187         WREG32(CP_ME_RAM_RADDR, 0);
1188         return 0;
1189 }
1190
1191 int r600_cp_start(struct radeon_device *rdev)
1192 {
1193         int r;
1194         uint32_t cp_me;
1195
1196         r = radeon_ring_lock(rdev, 7);
1197         if (r) {
1198                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1199                 return r;
1200         }
1201         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1202         radeon_ring_write(rdev, 0x1);
1203         if (rdev->family < CHIP_RV770) {
1204                 radeon_ring_write(rdev, 0x3);
1205                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1206         } else {
1207                 radeon_ring_write(rdev, 0x0);
1208                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1209         }
1210         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1211         radeon_ring_write(rdev, 0);
1212         radeon_ring_write(rdev, 0);
1213         radeon_ring_unlock_commit(rdev);
1214
1215         cp_me = 0xff;
1216         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1217         return 0;
1218 }
1219
1220 int r600_cp_resume(struct radeon_device *rdev)
1221 {
1222         u32 tmp;
1223         u32 rb_bufsz;
1224         int r;
1225
1226         /* Reset cp */
1227         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1228         RREG32(GRBM_SOFT_RESET);
1229         mdelay(15);
1230         WREG32(GRBM_SOFT_RESET, 0);
1231
1232         /* Set ring buffer size */
1233         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1234 #ifdef __BIG_ENDIAN
1235         WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
1236                 (drm_order(4096/8) << 8) | rb_bufsz);
1237 #else
1238         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1239 #endif
1240         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1241
1242         /* Set the write pointer delay */
1243         WREG32(CP_RB_WPTR_DELAY, 0);
1244
1245         /* Initialize the ring buffer's read and write pointers */
1246         tmp = RREG32(CP_RB_CNTL);
1247         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1248         WREG32(CP_RB_RPTR_WR, 0);
1249         WREG32(CP_RB_WPTR, 0);
1250         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1251         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1252         mdelay(1);
1253         WREG32(CP_RB_CNTL, tmp);
1254
1255         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1256         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1257
1258         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1259         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1260
1261         r600_cp_start(rdev);
1262         rdev->cp.ready = true;
1263         r = radeon_ring_test(rdev);
1264         if (r) {
1265                 rdev->cp.ready = false;
1266                 return r;
1267         }
1268         return 0;
1269 }
1270
1271 void r600_cp_commit(struct radeon_device *rdev)
1272 {
1273         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1274         (void)RREG32(CP_RB_WPTR);
1275 }
1276
1277 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1278 {
1279         u32 rb_bufsz;
1280
1281         /* Align ring size */
1282         rb_bufsz = drm_order(ring_size / 8);
1283         ring_size = (1 << (rb_bufsz + 1)) * 4;
1284         rdev->cp.ring_size = ring_size;
1285         rdev->cp.align_mask = 16 - 1;
1286 }
1287
1288
1289 /*
1290  * GPU scratch registers helpers function.
1291  */
1292 void r600_scratch_init(struct radeon_device *rdev)
1293 {
1294         int i;
1295
1296         rdev->scratch.num_reg = 7;
1297         for (i = 0; i < rdev->scratch.num_reg; i++) {
1298                 rdev->scratch.free[i] = true;
1299                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1300         }
1301 }
1302
1303 int r600_ring_test(struct radeon_device *rdev)
1304 {
1305         uint32_t scratch;
1306         uint32_t tmp = 0;
1307         unsigned i;
1308         int r;
1309
1310         r = radeon_scratch_get(rdev, &scratch);
1311         if (r) {
1312                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1313                 return r;
1314         }
1315         WREG32(scratch, 0xCAFEDEAD);
1316         r = radeon_ring_lock(rdev, 3);
1317         if (r) {
1318                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1319                 radeon_scratch_free(rdev, scratch);
1320                 return r;
1321         }
1322         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1323         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1324         radeon_ring_write(rdev, 0xDEADBEEF);
1325         radeon_ring_unlock_commit(rdev);
1326         for (i = 0; i < rdev->usec_timeout; i++) {
1327                 tmp = RREG32(scratch);
1328                 if (tmp == 0xDEADBEEF)
1329                         break;
1330                 DRM_UDELAY(1);
1331         }
1332         if (i < rdev->usec_timeout) {
1333                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1334         } else {
1335                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1336                           scratch, tmp);
1337                 r = -EINVAL;
1338         }
1339         radeon_scratch_free(rdev, scratch);
1340         return r;
1341 }
1342
1343 /*
1344  * Writeback
1345  */
1346 int r600_wb_init(struct radeon_device *rdev)
1347 {
1348         int r;
1349
1350         if (rdev->wb.wb_obj == NULL) {
1351                 r = radeon_object_create(rdev, NULL, 4096,
1352                                          true,
1353                                          RADEON_GEM_DOMAIN_GTT,
1354                                          false, &rdev->wb.wb_obj);
1355                 if (r) {
1356                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
1357                         return r;
1358                 }
1359                 r = radeon_object_pin(rdev->wb.wb_obj,
1360                                       RADEON_GEM_DOMAIN_GTT,
1361                                       &rdev->wb.gpu_addr);
1362                 if (r) {
1363                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
1364                         return r;
1365                 }
1366                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1367                 if (r) {
1368                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
1369                         return r;
1370                 }
1371         }
1372         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1373         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1374         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1375         WREG32(SCRATCH_UMSK, 0xff);
1376         return 0;
1377 }
1378
1379 void r600_wb_fini(struct radeon_device *rdev)
1380 {
1381         if (rdev->wb.wb_obj) {
1382                 radeon_object_kunmap(rdev->wb.wb_obj);
1383                 radeon_object_unpin(rdev->wb.wb_obj);
1384                 radeon_object_unref(&rdev->wb.wb_obj);
1385                 rdev->wb.wb = NULL;
1386                 rdev->wb.wb_obj = NULL;
1387         }
1388 }
1389
1390
1391 /*
1392  * CS
1393  */
1394 void r600_fence_ring_emit(struct radeon_device *rdev,
1395                           struct radeon_fence *fence)
1396 {
1397         /* Emit fence sequence & fire IRQ */
1398         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1399         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1400         radeon_ring_write(rdev, fence->seq);
1401 }
1402
1403 int r600_copy_dma(struct radeon_device *rdev,
1404                   uint64_t src_offset,
1405                   uint64_t dst_offset,
1406                   unsigned num_pages,
1407                   struct radeon_fence *fence)
1408 {
1409         /* FIXME: implement */
1410         return 0;
1411 }
1412
1413 int r600_copy_blit(struct radeon_device *rdev,
1414                    uint64_t src_offset, uint64_t dst_offset,
1415                    unsigned num_pages, struct radeon_fence *fence)
1416 {
1417         r600_blit_prepare_copy(rdev, num_pages * 4096);
1418         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
1419         r600_blit_done_copy(rdev, fence);
1420         return 0;
1421 }
1422
1423 int r600_irq_process(struct radeon_device *rdev)
1424 {
1425         /* FIXME: implement */
1426         return 0;
1427 }
1428
1429 int r600_irq_set(struct radeon_device *rdev)
1430 {
1431         /* FIXME: implement */
1432         return 0;
1433 }
1434
1435 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1436                          uint32_t tiling_flags, uint32_t pitch,
1437                          uint32_t offset, uint32_t obj_size)
1438 {
1439         /* FIXME: implement */
1440         return 0;
1441 }
1442
1443 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1444 {
1445         /* FIXME: implement */
1446 }
1447
1448
1449 bool r600_card_posted(struct radeon_device *rdev)
1450 {
1451         uint32_t reg;
1452
1453         /* first check CRTCs */
1454         reg = RREG32(D1CRTC_CONTROL) |
1455                 RREG32(D2CRTC_CONTROL);
1456         if (reg & CRTC_EN)
1457                 return true;
1458
1459         /* then check MEM_SIZE, in case the crtcs are off */
1460         if (RREG32(CONFIG_MEMSIZE))
1461                 return true;
1462
1463         return false;
1464 }
1465
1466 int r600_resume(struct radeon_device *rdev)
1467 {
1468         int r;
1469
1470         r600_gpu_reset(rdev);
1471         r600_mc_resume(rdev);
1472         r = r600_pcie_gart_enable(rdev);
1473         if (r)
1474                 return r;
1475         r600_gpu_init(rdev);
1476         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1477         if (r)
1478                 return r;
1479         r = r600_cp_load_microcode(rdev);
1480         if (r)
1481                 return r;
1482         r = r600_cp_resume(rdev);
1483         if (r)
1484                 return r;
1485         r = r600_wb_init(rdev);
1486         if (r)
1487                 return r;
1488         return 0;
1489 }
1490
1491 int r600_suspend(struct radeon_device *rdev)
1492 {
1493         /* FIXME: we should wait for ring to be empty */
1494         r600_cp_stop(rdev);
1495         r600_pcie_gart_disable(rdev);
1496         return 0;
1497 }
1498
1499 /* Plan is to move initialization in that function and use
1500  * helper function so that radeon_device_init pretty much
1501  * do nothing more than calling asic specific function. This
1502  * should also allow to remove a bunch of callback function
1503  * like vram_info.
1504  */
1505 int r600_init(struct radeon_device *rdev)
1506 {
1507         int r;
1508
1509         rdev->new_init_path = true;
1510         r = radeon_dummy_page_init(rdev);
1511         if (r)
1512                 return r;
1513         if (r600_debugfs_mc_info_init(rdev)) {
1514                 DRM_ERROR("Failed to register debugfs file for mc !\n");
1515         }
1516         /* This don't do much */
1517         r = radeon_gem_init(rdev);
1518         if (r)
1519                 return r;
1520         /* Read BIOS */
1521         if (!radeon_get_bios(rdev)) {
1522                 if (ASIC_IS_AVIVO(rdev))
1523                         return -EINVAL;
1524         }
1525         /* Must be an ATOMBIOS */
1526         if (!rdev->is_atom_bios)
1527                 return -EINVAL;
1528         r = radeon_atombios_init(rdev);
1529         if (r)
1530                 return r;
1531         /* Post card if necessary */
1532         if (!r600_card_posted(rdev) && rdev->bios) {
1533                 DRM_INFO("GPU not posted. posting now...\n");
1534                 atom_asic_init(rdev->mode_info.atom_context);
1535         }
1536         /* Initialize scratch registers */
1537         r600_scratch_init(rdev);
1538         /* Initialize surface registers */
1539         radeon_surface_init(rdev);
1540         r = radeon_clocks_init(rdev);
1541         if (r)
1542                 return r;
1543         /* Fence driver */
1544         r = radeon_fence_driver_init(rdev);
1545         if (r)
1546                 return r;
1547         r = r600_mc_init(rdev);
1548         if (r) {
1549                 if (rdev->flags & RADEON_IS_AGP) {
1550                         /* Retry with disabling AGP */
1551                         r600_fini(rdev);
1552                         rdev->flags &= ~RADEON_IS_AGP;
1553                         return r600_init(rdev);
1554                 }
1555                 return r;
1556         }
1557         /* Memory manager */
1558         r = radeon_object_init(rdev);
1559         if (r)
1560                 return r;
1561         rdev->cp.ring_obj = NULL;
1562         r600_ring_init(rdev, 1024 * 1024);
1563
1564         if (!rdev->me_fw || !rdev->pfp_fw) {
1565                 r = r600_cp_init_microcode(rdev);
1566                 if (r) {
1567                         DRM_ERROR("Failed to load firmware!\n");
1568                         return r;
1569                 }
1570         }
1571
1572         r = r600_pcie_gart_init(rdev);
1573         if (r)
1574                 return r;
1575
1576         r = r600_resume(rdev);
1577         if (r) {
1578                 if (rdev->flags & RADEON_IS_AGP) {
1579                         /* Retry with disabling AGP */
1580                         r600_fini(rdev);
1581                         rdev->flags &= ~RADEON_IS_AGP;
1582                         return r600_init(rdev);
1583                 }
1584                 return r;
1585         }
1586         r = radeon_ib_pool_init(rdev);
1587         if (r) {
1588                 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1589                 return r;
1590         }
1591         r = r600_blit_init(rdev);
1592         if (r) {
1593                 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1594                 return r;
1595         }
1596         r = radeon_ib_test(rdev);
1597         if (r) {
1598                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1599                         return r;
1600         }
1601         return 0;
1602 }
1603
1604 void r600_fini(struct radeon_device *rdev)
1605 {
1606         /* Suspend operations */
1607         r600_suspend(rdev);
1608
1609         r600_blit_fini(rdev);
1610         radeon_ring_fini(rdev);
1611         r600_pcie_gart_fini(rdev);
1612         radeon_gem_fini(rdev);
1613         radeon_fence_driver_fini(rdev);
1614         radeon_clocks_fini(rdev);
1615 #if __OS_HAS_AGP
1616         if (rdev->flags & RADEON_IS_AGP)
1617                 radeon_agp_fini(rdev);
1618 #endif
1619         radeon_object_fini(rdev);
1620         if (rdev->is_atom_bios)
1621                 radeon_atombios_fini(rdev);
1622         else
1623                 radeon_combios_fini(rdev);
1624         kfree(rdev->bios);
1625         rdev->bios = NULL;
1626         radeon_dummy_page_fini(rdev);
1627 }
1628
1629
1630 /*
1631  * CS stuff
1632  */
1633 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1634 {
1635         /* FIXME: implement */
1636         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1637         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1638         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1639         radeon_ring_write(rdev, ib->length_dw);
1640 }
1641
1642 int r600_ib_test(struct radeon_device *rdev)
1643 {
1644         struct radeon_ib *ib;
1645         uint32_t scratch;
1646         uint32_t tmp = 0;
1647         unsigned i;
1648         int r;
1649
1650         r = radeon_scratch_get(rdev, &scratch);
1651         if (r) {
1652                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1653                 return r;
1654         }
1655         WREG32(scratch, 0xCAFEDEAD);
1656         r = radeon_ib_get(rdev, &ib);
1657         if (r) {
1658                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1659                 return r;
1660         }
1661         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1662         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1663         ib->ptr[2] = 0xDEADBEEF;
1664         ib->ptr[3] = PACKET2(0);
1665         ib->ptr[4] = PACKET2(0);
1666         ib->ptr[5] = PACKET2(0);
1667         ib->ptr[6] = PACKET2(0);
1668         ib->ptr[7] = PACKET2(0);
1669         ib->ptr[8] = PACKET2(0);
1670         ib->ptr[9] = PACKET2(0);
1671         ib->ptr[10] = PACKET2(0);
1672         ib->ptr[11] = PACKET2(0);
1673         ib->ptr[12] = PACKET2(0);
1674         ib->ptr[13] = PACKET2(0);
1675         ib->ptr[14] = PACKET2(0);
1676         ib->ptr[15] = PACKET2(0);
1677         ib->length_dw = 16;
1678         r = radeon_ib_schedule(rdev, ib);
1679         if (r) {
1680                 radeon_scratch_free(rdev, scratch);
1681                 radeon_ib_free(rdev, &ib);
1682                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1683                 return r;
1684         }
1685         r = radeon_fence_wait(ib->fence, false);
1686         if (r) {
1687                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1688                 return r;
1689         }
1690         for (i = 0; i < rdev->usec_timeout; i++) {
1691                 tmp = RREG32(scratch);
1692                 if (tmp == 0xDEADBEEF)
1693                         break;
1694                 DRM_UDELAY(1);
1695         }
1696         if (i < rdev->usec_timeout) {
1697                 DRM_INFO("ib test succeeded in %u usecs\n", i);
1698         } else {
1699                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1700                           scratch, tmp);
1701                 r = -EINVAL;
1702         }
1703         radeon_scratch_free(rdev, scratch);
1704         radeon_ib_free(rdev, &ib);
1705         return r;
1706 }
1707
1708
1709
1710
1711 /*
1712  * Debugfs info
1713  */
1714 #if defined(CONFIG_DEBUG_FS)
1715
1716 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1717 {
1718         struct drm_info_node *node = (struct drm_info_node *) m->private;
1719         struct drm_device *dev = node->minor->dev;
1720         struct radeon_device *rdev = dev->dev_private;
1721         uint32_t rdp, wdp;
1722         unsigned count, i, j;
1723
1724         radeon_ring_free_size(rdev);
1725         rdp = RREG32(CP_RB_RPTR);
1726         wdp = RREG32(CP_RB_WPTR);
1727         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1728         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1729         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1730         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1731         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1732         seq_printf(m, "%u dwords in ring\n", count);
1733         for (j = 0; j <= count; j++) {
1734                 i = (rdp + j) & rdev->cp.ptr_mask;
1735                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1736         }
1737         return 0;
1738 }
1739
1740 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1741 {
1742         struct drm_info_node *node = (struct drm_info_node *) m->private;
1743         struct drm_device *dev = node->minor->dev;
1744         struct radeon_device *rdev = dev->dev_private;
1745
1746         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1747         DREG32_SYS(m, rdev, VM_L2_STATUS);
1748         return 0;
1749 }
1750
1751 static struct drm_info_list r600_mc_info_list[] = {
1752         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1753         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1754 };
1755 #endif
1756
1757 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1758 {
1759 #if defined(CONFIG_DEBUG_FS)
1760         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1761 #else
1762         return 0;
1763 #endif
1764 }