drivers/gpu/drm/radeon/r520.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31
  32 /* r520,rv530,rv560,rv570,r580 depends on : */
  33 void r100_hdp_reset(struct radeon_device *rdev);
  34 void r420_pipes_init(struct radeon_device *rdev);
  35 void rs600_mc_disable_clients(struct radeon_device *rdev);
  36 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  37 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  38
  39 /* This files gather functions specifics to:
  40  * r520,rv530,rv560,rv570,r580
  41  *
  42  * Some of these functions might be used by newer ASICs.
  43  */
  44 void r520_gpu_init(struct radeon_device *rdev);
  45 int r520_mc_wait_for_idle(struct radeon_device *rdev);
  46
  47
  48 /*
  49  * MC
  50  */
  51 int r520_mc_init(struct radeon_device *rdev)
  52 {
  53         uint32_t tmp;
  54         int r;
  55
  56         if (r100_debugfs_rbbm_init(rdev)) {
  57                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  58         }
  59         if (rv515_debugfs_pipes_info_init(rdev)) {
  60                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  61         }
  62         if (rv515_debugfs_ga_info_init(rdev)) {
  63                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  64         }
  65
  66         r520_gpu_init(rdev);
  67         rv370_pcie_gart_disable(rdev);
  68
  69         /* Setup GPU memory space */
  70         rdev->mc.vram_location = 0xFFFFFFFFUL;
  71         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  72         if (rdev->flags & RADEON_IS_AGP) {
  73                 r = radeon_agp_init(rdev);
  74                 if (r) {
  75                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  76                         rdev->flags &= ~RADEON_IS_AGP;
  77                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  78                 } else {
  79                         rdev->mc.gtt_location = rdev->mc.agp_base;
  80                 }
  81         }
  82         r = radeon_mc_setup(rdev);
  83         if (r) {
  84                 return r;
  85         }
  86
  87         /* Program GPU memory space */
  88         rs600_mc_disable_clients(rdev);
  89         if (r520_mc_wait_for_idle(rdev)) {
  90                 printk(KERN_WARNING "Failed to wait MC idle while "
  91                        "programming pipes. Bad things might happen.\n");
  92         }
  93         /* Write VRAM size in case we are limiting it */
  94         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  95         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
  96         tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
  97         tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
  98         WREG32_MC(R520_MC_FB_LOCATION, tmp);
  99         WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
 100         WREG32(0x310, rdev->mc.vram_location);
 101         if (rdev->flags & RADEON_IS_AGP) {
 102                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 103                 tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16);
 104                 tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16);
 105                 WREG32_MC(R520_MC_AGP_LOCATION, tmp);
 106                 WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base);
 107                 WREG32_MC(R520_MC_AGP_BASE_2, 0);
 108         } else {
 109                 WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
 110                 WREG32_MC(R520_MC_AGP_BASE, 0);
 111                 WREG32_MC(R520_MC_AGP_BASE_2, 0);
 112         }
 113         return 0;
 114 }
 115
 116 void r520_mc_fini(struct radeon_device *rdev)
 117 {
 118 }
 119
 120
 121 /*
 122  * Global GPU functions
 123  */
 124 void r520_errata(struct radeon_device *rdev)
 125 {
 126         rdev->pll_errata = 0;
 127 }
 128
 129 int r520_mc_wait_for_idle(struct radeon_device *rdev)
 130 {
 131         unsigned i;
 132         uint32_t tmp;
 133
 134         for (i = 0; i < rdev->usec_timeout; i++) {
 135                 /* read MC_STATUS */
 136                 tmp = RREG32_MC(R520_MC_STATUS);
 137                 if (tmp & R520_MC_STATUS_IDLE) {
 138                         return 0;
 139                 }
 140                 DRM_UDELAY(1);
 141         }
 142         return -1;
 143 }
 144
 145 void r520_gpu_init(struct radeon_device *rdev)
 146 {
 147         unsigned pipe_select_current, gb_pipe_select, tmp;
 148
 149         r100_hdp_reset(rdev);
 150         rv515_vga_render_disable(rdev);
 151         /*
 152          * DST_PIPE_CONFIG              0x170C
 153          * GB_TILE_CONFIG               0x4018
 154          * GB_FIFO_SIZE                 0x4024
 155          * GB_PIPE_SELECT               0x402C
 156          * GB_PIPE_SELECT2              0x4124
 157          *      Z_PIPE_SHIFT                    0
 158          *      Z_PIPE_MASK                     0x000000003
 159          * GB_FIFO_SIZE2                0x4128
 160          *      SC_SFIFO_SIZE_SHIFT             0
 161          *      SC_SFIFO_SIZE_MASK              0x000000003
 162          *      SC_MFIFO_SIZE_SHIFT             2
 163          *      SC_MFIFO_SIZE_MASK              0x00000000C
 164          *      FG_SFIFO_SIZE_SHIFT             4
 165          *      FG_SFIFO_SIZE_MASK              0x000000030
 166          *      ZB_MFIFO_SIZE_SHIFT             6
 167          *      ZB_MFIFO_SIZE_MASK              0x0000000C0
 168          * GA_ENHANCE                   0x4274
 169          * SU_REG_DEST                  0x42C8
 170          */
 171         /* workaround for RV530 */
 172         if (rdev->family == CHIP_RV530) {
 173                 WREG32(0x4128, 0xFF);
 174         }
 175         r420_pipes_init(rdev);
 176         gb_pipe_select = RREG32(0x402C);
 177         tmp = RREG32(0x170C);
 178         pipe_select_current = (tmp >> 2) & 3;
 179         tmp = (1 << pipe_select_current) |
 180               (((gb_pipe_select >> 8) & 0xF) << 4);
 181         WREG32_PLL(0x000D, tmp);
 182         if (r520_mc_wait_for_idle(rdev)) {
 183                 printk(KERN_WARNING "Failed to wait MC idle while "
 184                        "programming pipes. Bad things might happen.\n");
 185         }
 186 }
 187
 188
 189 /*
 190  * VRAM info
 191  */
 192 static void r520_vram_get_type(struct radeon_device *rdev)
 193 {
 194         uint32_t tmp;
 195
 196         rdev->mc.vram_width = 128;
 197         rdev->mc.vram_is_ddr = true;
 198         tmp = RREG32_MC(R520_MC_CNTL0);
 199         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
 200         case 0:
 201                 rdev->mc.vram_width = 32;
 202                 break;
 203         case 1:
 204                 rdev->mc.vram_width = 64;
 205                 break;
 206         case 2:
 207                 rdev->mc.vram_width = 128;
 208                 break;
 209         case 3:
 210                 rdev->mc.vram_width = 256;
 211                 break;
 212         default:
 213                 rdev->mc.vram_width = 128;
 214                 break;
 215         }
 216         if (tmp & R520_MC_CHANNEL_SIZE)
 217                 rdev->mc.vram_width *= 2;
 218 }
 219
 220 void r520_vram_info(struct radeon_device *rdev)
 221 {
 222         fixed20_12 a;
 223
 224         r520_vram_get_type(rdev);
 225
 226         r100_vram_init_sizes(rdev);
 227         /* FIXME: we should enforce default clock in case GPU is not in
 228          * default setup
 229          */
 230         a.full = rfixed_const(100);
 231         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 232         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 233 }
 234
 235 void r520_bandwidth_update(struct radeon_device *rdev)
 236 {
 237         rv515_bandwidth_avivo_update(rdev);
 238 }
 239
 240 int r520_init(struct radeon_device *rdev)
 241 {
 242         rv515_set_safe_registers(rdev);
 243         return 0;
 244 }