drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "radeon_drm.h"
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "r100d.h"
  35 #include "rs100d.h"
  36 #include "rv200d.h"
  37 #include "rv250d.h"
  38
  39 #include <linux/firmware.h>
  40 #include <linux/platform_device.h>
  41
  42 #include "r100_reg_safe.h"
  43 #include "rn50_reg_safe.h"
  44
  45 /* Firmware Names */
  46 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  47 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  48 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  49 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  50 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  51 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  52 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  53
  54 MODULE_FIRMWARE(FIRMWARE_R100);
  55 MODULE_FIRMWARE(FIRMWARE_R200);
  56 MODULE_FIRMWARE(FIRMWARE_R300);
  57 MODULE_FIRMWARE(FIRMWARE_R420);
  58 MODULE_FIRMWARE(FIRMWARE_RS690);
  59 MODULE_FIRMWARE(FIRMWARE_RS600);
  60 MODULE_FIRMWARE(FIRMWARE_R520);
  61
  62 #include "r100_track.h"
  63
  64 /* This files gather functions specifics to:
  65  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  66  */
  67
  68 /* hpd for digital panel detect/disconnect */
  69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  70 {
  71         bool connected = false;
  72
  73         switch (hpd) {
  74         case RADEON_HPD_1:
  75                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
  76                         connected = true;
  77                 break;
  78         case RADEON_HPD_2:
  79                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
  80                         connected = true;
  81                 break;
  82         default:
  83                 break;
  84         }
  85         return connected;
  86 }
  87
  88 void r100_hpd_set_polarity(struct radeon_device *rdev,
  89                            enum radeon_hpd_id hpd)
  90 {
  91         u32 tmp;
  92         bool connected = r100_hpd_sense(rdev, hpd);
  93
  94         switch (hpd) {
  95         case RADEON_HPD_1:
  96                 tmp = RREG32(RADEON_FP_GEN_CNTL);
  97                 if (connected)
  98                         tmp &= ~RADEON_FP_DETECT_INT_POL;
  99                 else
 100                         tmp |= RADEON_FP_DETECT_INT_POL;
 101                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 102                 break;
 103         case RADEON_HPD_2:
 104                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 105                 if (connected)
 106                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 107                 else
 108                         tmp |= RADEON_FP2_DETECT_INT_POL;
 109                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 110                 break;
 111         default:
 112                 break;
 113         }
 114 }
 115
 116 void r100_hpd_init(struct radeon_device *rdev)
 117 {
 118         struct drm_device *dev = rdev->ddev;
 119         struct drm_connector *connector;
 120
 121         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 122                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 123                 switch (radeon_connector->hpd.hpd) {
 124                 case RADEON_HPD_1:
 125                         rdev->irq.hpd[0] = true;
 126                         break;
 127                 case RADEON_HPD_2:
 128                         rdev->irq.hpd[1] = true;
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134         if (rdev->irq.installed)
 135                 r100_irq_set(rdev);
 136 }
 137
 138 void r100_hpd_fini(struct radeon_device *rdev)
 139 {
 140         struct drm_device *dev = rdev->ddev;
 141         struct drm_connector *connector;
 142
 143         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 144                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 145                 switch (radeon_connector->hpd.hpd) {
 146                 case RADEON_HPD_1:
 147                         rdev->irq.hpd[0] = false;
 148                         break;
 149                 case RADEON_HPD_2:
 150                         rdev->irq.hpd[1] = false;
 151                         break;
 152                 default:
 153                         break;
 154                 }
 155         }
 156 }
 157
 158 /*
 159  * PCI GART
 160  */
 161 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 162 {
 163         /* TODO: can we do somethings here ? */
 164         /* It seems hw only cache one entry so we should discard this
 165          * entry otherwise if first GPU GART read hit this entry it
 166          * could end up in wrong address. */
 167 }
 168
 169 int r100_pci_gart_init(struct radeon_device *rdev)
 170 {
 171         int r;
 172
 173         if (rdev->gart.table.ram.ptr) {
 174                 WARN(1, "R100 PCI GART already initialized.\n");
 175                 return 0;
 176         }
 177         /* Initialize common gart structure */
 178         r = radeon_gart_init(rdev);
 179         if (r)
 180                 return r;
 181         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 182         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 183         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 184         return radeon_gart_table_ram_alloc(rdev);
 185 }
 186
 187 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 188 void r100_enable_bm(struct radeon_device *rdev)
 189 {
 190         uint32_t tmp;
 191         /* Enable bus mastering */
 192         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 193         WREG32(RADEON_BUS_CNTL, tmp);
 194 }
 195
 196 int r100_pci_gart_enable(struct radeon_device *rdev)
 197 {
 198         uint32_t tmp;
 199
 200         radeon_gart_restore(rdev);
 201         /* discard memory request outside of configured range */
 202         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 203         WREG32(RADEON_AIC_CNTL, tmp);
 204         /* set address range for PCI address translate */
 205         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 206         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 207         /* set PCI GART page-table base address */
 208         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 209         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 210         WREG32(RADEON_AIC_CNTL, tmp);
 211         r100_pci_gart_tlb_flush(rdev);
 212         rdev->gart.ready = true;
 213         return 0;
 214 }
 215
 216 void r100_pci_gart_disable(struct radeon_device *rdev)
 217 {
 218         uint32_t tmp;
 219
 220         /* discard memory request outside of configured range */
 221         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 222         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 223         WREG32(RADEON_AIC_LO_ADDR, 0);
 224         WREG32(RADEON_AIC_HI_ADDR, 0);
 225 }
 226
 227 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 228 {
 229         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 230                 return -EINVAL;
 231         }
 232         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 233         return 0;
 234 }
 235
 236 void r100_pci_gart_fini(struct radeon_device *rdev)
 237 {
 238         r100_pci_gart_disable(rdev);
 239         radeon_gart_table_ram_free(rdev);
 240         radeon_gart_fini(rdev);
 241 }
 242
 243 int r100_irq_set(struct radeon_device *rdev)
 244 {
 245         uint32_t tmp = 0;
 246
 247         if (!rdev->irq.installed) {
 248                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
 249                 WREG32(R_000040_GEN_INT_CNTL, 0);
 250                 return -EINVAL;
 251         }
 252         if (rdev->irq.sw_int) {
 253                 tmp |= RADEON_SW_INT_ENABLE;
 254         }
 255         if (rdev->irq.crtc_vblank_int[0]) {
 256                 tmp |= RADEON_CRTC_VBLANK_MASK;
 257         }
 258         if (rdev->irq.crtc_vblank_int[1]) {
 259                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 260         }
 261         if (rdev->irq.hpd[0]) {
 262                 tmp |= RADEON_FP_DETECT_MASK;
 263         }
 264         if (rdev->irq.hpd[1]) {
 265                 tmp |= RADEON_FP2_DETECT_MASK;
 266         }
 267         WREG32(RADEON_GEN_INT_CNTL, tmp);
 268         return 0;
 269 }
 270
 271 void r100_irq_disable(struct radeon_device *rdev)
 272 {
 273         u32 tmp;
 274
 275         WREG32(R_000040_GEN_INT_CNTL, 0);
 276         /* Wait and acknowledge irq */
 277         mdelay(1);
 278         tmp = RREG32(R_000044_GEN_INT_STATUS);
 279         WREG32(R_000044_GEN_INT_STATUS, tmp);
 280 }
 281
 282 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 283 {
 284         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 285         uint32_t irq_mask = RADEON_SW_INT_TEST |
 286                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 287                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 288
 289         if (irqs) {
 290                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 291         }
 292         return irqs & irq_mask;
 293 }
 294
 295 int r100_irq_process(struct radeon_device *rdev)
 296 {
 297         uint32_t status, msi_rearm;
 298         bool queue_hotplug = false;
 299
 300         status = r100_irq_ack(rdev);
 301         if (!status) {
 302                 return IRQ_NONE;
 303         }
 304         if (rdev->shutdown) {
 305                 return IRQ_NONE;
 306         }
 307         while (status) {
 308                 /* SW interrupt */
 309                 if (status & RADEON_SW_INT_TEST) {
 310                         radeon_fence_process(rdev);
 311                 }
 312                 /* Vertical blank interrupts */
 313                 if (status & RADEON_CRTC_VBLANK_STAT) {
 314                         drm_handle_vblank(rdev->ddev, 0);
 315                         rdev->pm.vblank_sync = true;
 316                         wake_up(&rdev->irq.vblank_queue);
 317                 }
 318                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 319                         drm_handle_vblank(rdev->ddev, 1);
 320                         rdev->pm.vblank_sync = true;
 321                         wake_up(&rdev->irq.vblank_queue);
 322                 }
 323                 if (status & RADEON_FP_DETECT_STAT) {
 324                         queue_hotplug = true;
 325                         DRM_DEBUG("HPD1\n");
 326                 }
 327                 if (status & RADEON_FP2_DETECT_STAT) {
 328                         queue_hotplug = true;
 329                         DRM_DEBUG("HPD2\n");
 330                 }
 331                 status = r100_irq_ack(rdev);
 332         }
 333         if (queue_hotplug)
 334                 queue_work(rdev->wq, &rdev->hotplug_work);
 335         if (rdev->msi_enabled) {
 336                 switch (rdev->family) {
 337                 case CHIP_RS400:
 338                 case CHIP_RS480:
 339                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 340                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 341                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 342                         break;
 343                 default:
 344                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 345                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 346                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 347                         break;
 348                 }
 349         }
 350         return IRQ_HANDLED;
 351 }
 352
 353 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 354 {
 355         if (crtc == 0)
 356                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 357         else
 358                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 359 }
 360
 361 /* Who ever call radeon_fence_emit should call ring_lock and ask
 362  * for enough space (today caller are ib schedule and buffer move) */
 363 void r100_fence_ring_emit(struct radeon_device *rdev,
 364                           struct radeon_fence *fence)
 365 {
 366         /* We have to make sure that caches are flushed before
 367          * CPU might read something from VRAM. */
 368         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 369         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 370         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 371         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 372         /* Wait until IDLE & CLEAN */
 373         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 374         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 375         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 376         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 377                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 378         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 379         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 380         /* Emit fence sequence & fire IRQ */
 381         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 382         radeon_ring_write(rdev, fence->seq);
 383         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 384         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 385 }
 386
 387 int r100_wb_init(struct radeon_device *rdev)
 388 {
 389         int r;
 390
 391         if (rdev->wb.wb_obj == NULL) {
 392                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
 393                                         RADEON_GEM_DOMAIN_GTT,
 394                                         &rdev->wb.wb_obj);
 395                 if (r) {
 396                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
 397                         return r;
 398                 }
 399                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 400                 if (unlikely(r != 0))
 401                         return r;
 402                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 403                                         &rdev->wb.gpu_addr);
 404                 if (r) {
 405                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
 406                         radeon_bo_unreserve(rdev->wb.wb_obj);
 407                         return r;
 408                 }
 409                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 410                 radeon_bo_unreserve(rdev->wb.wb_obj);
 411                 if (r) {
 412                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
 413                         return r;
 414                 }
 415         }
 416         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
 417         WREG32(R_00070C_CP_RB_RPTR_ADDR,
 418                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
 419         WREG32(R_000770_SCRATCH_UMSK, 0xff);
 420         return 0;
 421 }
 422
 423 void r100_wb_disable(struct radeon_device *rdev)
 424 {
 425         WREG32(R_000770_SCRATCH_UMSK, 0);
 426 }
 427
 428 void r100_wb_fini(struct radeon_device *rdev)
 429 {
 430         int r;
 431
 432         r100_wb_disable(rdev);
 433         if (rdev->wb.wb_obj) {
 434                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 435                 if (unlikely(r != 0)) {
 436                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
 437                         return;
 438                 }
 439                 radeon_bo_kunmap(rdev->wb.wb_obj);
 440                 radeon_bo_unpin(rdev->wb.wb_obj);
 441                 radeon_bo_unreserve(rdev->wb.wb_obj);
 442                 radeon_bo_unref(&rdev->wb.wb_obj);
 443                 rdev->wb.wb = NULL;
 444                 rdev->wb.wb_obj = NULL;
 445         }
 446 }
 447
 448 int r100_copy_blit(struct radeon_device *rdev,
 449                    uint64_t src_offset,
 450                    uint64_t dst_offset,
 451                    unsigned num_pages,
 452                    struct radeon_fence *fence)
 453 {
 454         uint32_t cur_pages;
 455         uint32_t stride_bytes = PAGE_SIZE;
 456         uint32_t pitch;
 457         uint32_t stride_pixels;
 458         unsigned ndw;
 459         int num_loops;
 460         int r = 0;
 461
 462         /* radeon limited to 16k stride */
 463         stride_bytes &= 0x3fff;
 464         /* radeon pitch is /64 */
 465         pitch = stride_bytes / 64;
 466         stride_pixels = stride_bytes / 4;
 467         num_loops = DIV_ROUND_UP(num_pages, 8191);
 468
 469         /* Ask for enough room for blit + flush + fence */
 470         ndw = 64 + (10 * num_loops);
 471         r = radeon_ring_lock(rdev, ndw);
 472         if (r) {
 473                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 474                 return -EINVAL;
 475         }
 476         while (num_pages > 0) {
 477                 cur_pages = num_pages;
 478                 if (cur_pages > 8191) {
 479                         cur_pages = 8191;
 480                 }
 481                 num_pages -= cur_pages;
 482
 483                 /* pages are in Y direction - height
 484                    page width in X direction - width */
 485                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 486                 radeon_ring_write(rdev,
 487                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 488                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 489                                   RADEON_GMC_SRC_CLIPPING |
 490                                   RADEON_GMC_DST_CLIPPING |
 491                                   RADEON_GMC_BRUSH_NONE |
 492                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 493                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 494                                   RADEON_ROP3_S |
 495                                   RADEON_DP_SRC_SOURCE_MEMORY |
 496                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 497                                   RADEON_GMC_WR_MSK_DIS);
 498                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 499                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 500                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 501                 radeon_ring_write(rdev, 0);
 502                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 503                 radeon_ring_write(rdev, num_pages);
 504                 radeon_ring_write(rdev, num_pages);
 505                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 506         }
 507         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 508         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 509         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 510         radeon_ring_write(rdev,
 511                           RADEON_WAIT_2D_IDLECLEAN |
 512                           RADEON_WAIT_HOST_IDLECLEAN |
 513                           RADEON_WAIT_DMA_GUI_IDLE);
 514         if (fence) {
 515                 r = radeon_fence_emit(rdev, fence);
 516         }
 517         radeon_ring_unlock_commit(rdev);
 518         return r;
 519 }
 520
 521 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 522 {
 523         unsigned i;
 524         u32 tmp;
 525
 526         for (i = 0; i < rdev->usec_timeout; i++) {
 527                 tmp = RREG32(R_000E40_RBBM_STATUS);
 528                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 529                         return 0;
 530                 }
 531                 udelay(1);
 532         }
 533         return -1;
 534 }
 535
 536 void r100_ring_start(struct radeon_device *rdev)
 537 {
 538         int r;
 539
 540         r = radeon_ring_lock(rdev, 2);
 541         if (r) {
 542                 return;
 543         }
 544         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 545         radeon_ring_write(rdev,
 546                           RADEON_ISYNC_ANY2D_IDLE3D |
 547                           RADEON_ISYNC_ANY3D_IDLE2D |
 548                           RADEON_ISYNC_WAIT_IDLEGUI |
 549                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 550         radeon_ring_unlock_commit(rdev);
 551 }
 552
 553
 554 /* Load the microcode for the CP */
 555 static int r100_cp_init_microcode(struct radeon_device *rdev)
 556 {
 557         struct platform_device *pdev;
 558         const char *fw_name = NULL;
 559         int err;
 560
 561         DRM_DEBUG("\n");
 562
 563         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 564         err = IS_ERR(pdev);
 565         if (err) {
 566                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 567                 return -EINVAL;
 568         }
 569         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 570             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 571             (rdev->family == CHIP_RS200)) {
 572                 DRM_INFO("Loading R100 Microcode\n");
 573                 fw_name = FIRMWARE_R100;
 574         } else if ((rdev->family == CHIP_R200) ||
 575                    (rdev->family == CHIP_RV250) ||
 576                    (rdev->family == CHIP_RV280) ||
 577                    (rdev->family == CHIP_RS300)) {
 578                 DRM_INFO("Loading R200 Microcode\n");
 579                 fw_name = FIRMWARE_R200;
 580         } else if ((rdev->family == CHIP_R300) ||
 581                    (rdev->family == CHIP_R350) ||
 582                    (rdev->family == CHIP_RV350) ||
 583                    (rdev->family == CHIP_RV380) ||
 584                    (rdev->family == CHIP_RS400) ||
 585                    (rdev->family == CHIP_RS480)) {
 586                 DRM_INFO("Loading R300 Microcode\n");
 587                 fw_name = FIRMWARE_R300;
 588         } else if ((rdev->family == CHIP_R420) ||
 589                    (rdev->family == CHIP_R423) ||
 590                    (rdev->family == CHIP_RV410)) {
 591                 DRM_INFO("Loading R400 Microcode\n");
 592                 fw_name = FIRMWARE_R420;
 593         } else if ((rdev->family == CHIP_RS690) ||
 594                    (rdev->family == CHIP_RS740)) {
 595                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 596                 fw_name = FIRMWARE_RS690;
 597         } else if (rdev->family == CHIP_RS600) {
 598                 DRM_INFO("Loading RS600 Microcode\n");
 599                 fw_name = FIRMWARE_RS600;
 600         } else if ((rdev->family == CHIP_RV515) ||
 601                    (rdev->family == CHIP_R520) ||
 602                    (rdev->family == CHIP_RV530) ||
 603                    (rdev->family == CHIP_R580) ||
 604                    (rdev->family == CHIP_RV560) ||
 605                    (rdev->family == CHIP_RV570)) {
 606                 DRM_INFO("Loading R500 Microcode\n");
 607                 fw_name = FIRMWARE_R520;
 608         }
 609
 610         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 611         platform_device_unregister(pdev);
 612         if (err) {
 613                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 614                        fw_name);
 615         } else if (rdev->me_fw->size % 8) {
 616                 printk(KERN_ERR
 617                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 618                        rdev->me_fw->size, fw_name);
 619                 err = -EINVAL;
 620                 release_firmware(rdev->me_fw);
 621                 rdev->me_fw = NULL;
 622         }
 623         return err;
 624 }
 625
 626 static void r100_cp_load_microcode(struct radeon_device *rdev)
 627 {
 628         const __be32 *fw_data;
 629         int i, size;
 630
 631         if (r100_gui_wait_for_idle(rdev)) {
 632                 printk(KERN_WARNING "Failed to wait GUI idle while "
 633                        "programming pipes. Bad things might happen.\n");
 634         }
 635
 636         if (rdev->me_fw) {
 637                 size = rdev->me_fw->size / 4;
 638                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 639                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 640                 for (i = 0; i < size; i += 2) {
 641                         WREG32(RADEON_CP_ME_RAM_DATAH,
 642                                be32_to_cpup(&fw_data[i]));
 643                         WREG32(RADEON_CP_ME_RAM_DATAL,
 644                                be32_to_cpup(&fw_data[i + 1]));
 645                 }
 646         }
 647 }
 648
 649 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 650 {
 651         unsigned rb_bufsz;
 652         unsigned rb_blksz;
 653         unsigned max_fetch;
 654         unsigned pre_write_timer;
 655         unsigned pre_write_limit;
 656         unsigned indirect2_start;
 657         unsigned indirect1_start;
 658         uint32_t tmp;
 659         int r;
 660
 661         if (r100_debugfs_cp_init(rdev)) {
 662                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 663         }
 664         /* Reset CP */
 665         tmp = RREG32(RADEON_CP_CSQ_STAT);
 666         if ((tmp & (1 << 31))) {
 667                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
 668                 WREG32(RADEON_CP_CSQ_MODE, 0);
 669                 WREG32(RADEON_CP_CSQ_CNTL, 0);
 670                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 671                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 672                 mdelay(2);
 673                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
 674                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
 675                 mdelay(2);
 676                 tmp = RREG32(RADEON_CP_CSQ_STAT);
 677                 if ((tmp & (1 << 31))) {
 678                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
 679                 }
 680         } else {
 681                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
 682         }
 683
 684         if (!rdev->me_fw) {
 685                 r = r100_cp_init_microcode(rdev);
 686                 if (r) {
 687                         DRM_ERROR("Failed to load firmware!\n");
 688                         return r;
 689                 }
 690         }
 691
 692         /* Align ring size */
 693         rb_bufsz = drm_order(ring_size / 8);
 694         ring_size = (1 << (rb_bufsz + 1)) * 4;
 695         r100_cp_load_microcode(rdev);
 696         r = radeon_ring_init(rdev, ring_size);
 697         if (r) {
 698                 return r;
 699         }
 700         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 701          * the rptr copy in system ram */
 702         rb_blksz = 9;
 703         /* cp will read 128bytes at a time (4 dwords) */
 704         max_fetch = 1;
 705         rdev->cp.align_mask = 16 - 1;
 706         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 707         pre_write_timer = 64;
 708         /* Force CP_RB_WPTR write if written more than one time before the
 709          * delay expire
 710          */
 711         pre_write_limit = 0;
 712         /* Setup the cp cache like this (cache size is 96 dwords) :
 713          *      RING            0  to 15
 714          *      INDIRECT1       16 to 79
 715          *      INDIRECT2       80 to 95
 716          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 717          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 718          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 719          * Idea being that most of the gpu cmd will be through indirect1 buffer
 720          * so it gets the bigger cache.
 721          */
 722         indirect2_start = 80;
 723         indirect1_start = 16;
 724         /* cp setup */
 725         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 726         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 727                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 728                REG_SET(RADEON_MAX_FETCH, max_fetch) |
 729                RADEON_RB_NO_UPDATE);
 730 #ifdef __BIG_ENDIAN
 731         tmp |= RADEON_BUF_SWAP_32BIT;
 732 #endif
 733         WREG32(RADEON_CP_RB_CNTL, tmp);
 734
 735         /* Set ring address */
 736         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
 737         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
 738         /* Force read & write ptr to 0 */
 739         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 740         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 741         WREG32(RADEON_CP_RB_WPTR, 0);
 742         WREG32(RADEON_CP_RB_CNTL, tmp);
 743         udelay(10);
 744         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
 745         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
 746         /* Set cp mode to bus mastering & enable cp*/
 747         WREG32(RADEON_CP_CSQ_MODE,
 748                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
 749                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
 750         WREG32(0x718, 0);
 751         WREG32(0x744, 0x00004D4D);
 752         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
 753         radeon_ring_start(rdev);
 754         r = radeon_ring_test(rdev);
 755         if (r) {
 756                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
 757                 return r;
 758         }
 759         rdev->cp.ready = true;
 760         return 0;
 761 }
 762
 763 void r100_cp_fini(struct radeon_device *rdev)
 764 {
 765         if (r100_cp_wait_for_idle(rdev)) {
 766                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
 767         }
 768         /* Disable ring */
 769         r100_cp_disable(rdev);
 770         radeon_ring_fini(rdev);
 771         DRM_INFO("radeon: cp finalized\n");
 772 }
 773
 774 void r100_cp_disable(struct radeon_device *rdev)
 775 {
 776         /* Disable ring */
 777         rdev->cp.ready = false;
 778         WREG32(RADEON_CP_CSQ_MODE, 0);
 779         WREG32(RADEON_CP_CSQ_CNTL, 0);
 780         if (r100_gui_wait_for_idle(rdev)) {
 781                 printk(KERN_WARNING "Failed to wait GUI idle while "
 782                        "programming pipes. Bad things might happen.\n");
 783         }
 784 }
 785
 786 int r100_cp_reset(struct radeon_device *rdev)
 787 {
 788         uint32_t tmp;
 789         bool reinit_cp;
 790         int i;
 791
 792         reinit_cp = rdev->cp.ready;
 793         rdev->cp.ready = false;
 794         WREG32(RADEON_CP_CSQ_MODE, 0);
 795         WREG32(RADEON_CP_CSQ_CNTL, 0);
 796         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
 797         (void)RREG32(RADEON_RBBM_SOFT_RESET);
 798         udelay(200);
 799         WREG32(RADEON_RBBM_SOFT_RESET, 0);
 800         /* Wait to prevent race in RBBM_STATUS */
 801         mdelay(1);
 802         for (i = 0; i < rdev->usec_timeout; i++) {
 803                 tmp = RREG32(RADEON_RBBM_STATUS);
 804                 if (!(tmp & (1 << 16))) {
 805                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
 806                                  tmp);
 807                         if (reinit_cp) {
 808                                 return r100_cp_init(rdev, rdev->cp.ring_size);
 809                         }
 810                         return 0;
 811                 }
 812                 DRM_UDELAY(1);
 813         }
 814         tmp = RREG32(RADEON_RBBM_STATUS);
 815         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
 816         return -1;
 817 }
 818
 819 void r100_cp_commit(struct radeon_device *rdev)
 820 {
 821         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
 822         (void)RREG32(RADEON_CP_RB_WPTR);
 823 }
 824
 825
 826 /*
 827  * CS functions
 828  */
 829 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 830                           struct radeon_cs_packet *pkt,
 831                           const unsigned *auth, unsigned n,
 832                           radeon_packet0_check_t check)
 833 {
 834         unsigned reg;
 835         unsigned i, j, m;
 836         unsigned idx;
 837         int r;
 838
 839         idx = pkt->idx + 1;
 840         reg = pkt->reg;
 841         /* Check that register fall into register range
 842          * determined by the number of entry (n) in the
 843          * safe register bitmap.
 844          */
 845         if (pkt->one_reg_wr) {
 846                 if ((reg >> 7) > n) {
 847                         return -EINVAL;
 848                 }
 849         } else {
 850                 if (((reg + (pkt->count << 2)) >> 7) > n) {
 851                         return -EINVAL;
 852                 }
 853         }
 854         for (i = 0; i <= pkt->count; i++, idx++) {
 855                 j = (reg >> 7);
 856                 m = 1 << ((reg >> 2) & 31);
 857                 if (auth[j] & m) {
 858                         r = check(p, pkt, idx, reg);
 859                         if (r) {
 860                                 return r;
 861                         }
 862                 }
 863                 if (pkt->one_reg_wr) {
 864                         if (!(auth[j] & m)) {
 865                                 break;
 866                         }
 867                 } else {
 868                         reg += 4;
 869                 }
 870         }
 871         return 0;
 872 }
 873
 874 void r100_cs_dump_packet(struct radeon_cs_parser *p,
 875                          struct radeon_cs_packet *pkt)
 876 {
 877         volatile uint32_t *ib;
 878         unsigned i;
 879         unsigned idx;
 880
 881         ib = p->ib->ptr;
 882         idx = pkt->idx;
 883         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
 884                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 885         }
 886 }
 887
 888 /**
 889  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
 890  * @parser:     parser structure holding parsing context.
 891  * @pkt:        where to store packet informations
 892  *
 893  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 894  * if packet is bigger than remaining ib size. or if packets is unknown.
 895  **/
 896 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 897                          struct radeon_cs_packet *pkt,
 898                          unsigned idx)
 899 {
 900         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 901         uint32_t header;
 902
 903         if (idx >= ib_chunk->length_dw) {
 904                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 905                           idx, ib_chunk->length_dw);
 906                 return -EINVAL;
 907         }
 908         header = radeon_get_ib_value(p, idx);
 909         pkt->idx = idx;
 910         pkt->type = CP_PACKET_GET_TYPE(header);
 911         pkt->count = CP_PACKET_GET_COUNT(header);
 912         switch (pkt->type) {
 913         case PACKET_TYPE0:
 914                 pkt->reg = CP_PACKET0_GET_REG(header);
 915                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
 916                 break;
 917         case PACKET_TYPE3:
 918                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 919                 break;
 920         case PACKET_TYPE2:
 921                 pkt->count = -1;
 922                 break;
 923         default:
 924                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 925                 return -EINVAL;
 926         }
 927         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 928                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 929                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 930                 return -EINVAL;
 931         }
 932         return 0;
 933 }
 934
 935 /**
 936  * r100_cs_packet_next_vline() - parse userspace VLINE packet
 937  * @parser:             parser structure holding parsing context.
 938  *
 939  * Userspace sends a special sequence for VLINE waits.
 940  * PACKET0 - VLINE_START_END + value
 941  * PACKET0 - WAIT_UNTIL +_value
 942  * RELOC (P3) - crtc_id in reloc.
 943  *
 944  * This function parses this and relocates the VLINE START END
 945  * and WAIT UNTIL packets to the correct crtc.
 946  * It also detects a switched off crtc and nulls out the
 947  * wait in that case.
 948  */
 949 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 950 {
 951         struct drm_mode_object *obj;
 952         struct drm_crtc *crtc;
 953         struct radeon_crtc *radeon_crtc;
 954         struct radeon_cs_packet p3reloc, waitreloc;
 955         int crtc_id;
 956         int r;
 957         uint32_t header, h_idx, reg;
 958         volatile uint32_t *ib;
 959
 960         ib = p->ib->ptr;
 961
 962         /* parse the wait until */
 963         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
 964         if (r)
 965                 return r;
 966
 967         /* check its a wait until and only 1 count */
 968         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
 969             waitreloc.count != 0) {
 970                 DRM_ERROR("vline wait had illegal wait until segment\n");
 971                 r = -EINVAL;
 972                 return r;
 973         }
 974
 975         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
 976                 DRM_ERROR("vline wait had illegal wait until\n");
 977                 r = -EINVAL;
 978                 return r;
 979         }
 980
 981         /* jump over the NOP */
 982         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
 983         if (r)
 984                 return r;
 985
 986         h_idx = p->idx - 2;
 987         p->idx += waitreloc.count + 2;
 988         p->idx += p3reloc.count + 2;
 989
 990         header = radeon_get_ib_value(p, h_idx);
 991         crtc_id = radeon_get_ib_value(p, h_idx + 5);
 992         reg = CP_PACKET0_GET_REG(header);
 993         mutex_lock(&p->rdev->ddev->mode_config.mutex);
 994         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
 995         if (!obj) {
 996                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
 997                 r = -EINVAL;
 998                 goto out;
 999         }
1000         crtc = obj_to_crtc(obj);
1001         radeon_crtc = to_radeon_crtc(crtc);
1002         crtc_id = radeon_crtc->crtc_id;
1003
1004         if (!crtc->enabled) {
1005                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1006                 ib[h_idx + 2] = PACKET2(0);
1007                 ib[h_idx + 3] = PACKET2(0);
1008         } else if (crtc_id == 1) {
1009                 switch (reg) {
1010                 case AVIVO_D1MODE_VLINE_START_END:
1011                         header &= ~R300_CP_PACKET0_REG_MASK;
1012                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1013                         break;
1014                 case RADEON_CRTC_GUI_TRIG_VLINE:
1015                         header &= ~R300_CP_PACKET0_REG_MASK;
1016                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1017                         break;
1018                 default:
1019                         DRM_ERROR("unknown crtc reloc\n");
1020                         r = -EINVAL;
1021                         goto out;
1022                 }
1023                 ib[h_idx] = header;
1024                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1025         }
1026 out:
1027         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1028         return r;
1029 }
1030
1031 /**
1032  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1033  * @parser:             parser structure holding parsing context.
1034  * @data:               pointer to relocation data
1035  * @offset_start:       starting offset
1036  * @offset_mask:        offset mask (to align start offset on)
1037  * @reloc:              reloc informations
1038  *
1039  * Check next packet is relocation packet3, do bo validation and compute
1040  * GPU offset using the provided start.
1041  **/
1042 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1043                               struct radeon_cs_reloc **cs_reloc)
1044 {
1045         struct radeon_cs_chunk *relocs_chunk;
1046         struct radeon_cs_packet p3reloc;
1047         unsigned idx;
1048         int r;
1049
1050         if (p->chunk_relocs_idx == -1) {
1051                 DRM_ERROR("No relocation chunk !\n");
1052                 return -EINVAL;
1053         }
1054         *cs_reloc = NULL;
1055         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1056         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1057         if (r) {
1058                 return r;
1059         }
1060         p->idx += p3reloc.count + 2;
1061         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1062                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1063                           p3reloc.idx);
1064                 r100_cs_dump_packet(p, &p3reloc);
1065                 return -EINVAL;
1066         }
1067         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1068         if (idx >= relocs_chunk->length_dw) {
1069                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1070                           idx, relocs_chunk->length_dw);
1071                 r100_cs_dump_packet(p, &p3reloc);
1072                 return -EINVAL;
1073         }
1074         /* FIXME: we assume reloc size is 4 dwords */
1075         *cs_reloc = p->relocs_ptr[(idx / 4)];
1076         return 0;
1077 }
1078
1079 static int r100_get_vtx_size(uint32_t vtx_fmt)
1080 {
1081         int vtx_size;
1082         vtx_size = 2;
1083         /* ordered according to bits in spec */
1084         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1085                 vtx_size++;
1086         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1087                 vtx_size += 3;
1088         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1089                 vtx_size++;
1090         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1091                 vtx_size++;
1092         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1093                 vtx_size += 3;
1094         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1095                 vtx_size++;
1096         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1097                 vtx_size++;
1098         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1099                 vtx_size += 2;
1100         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1101                 vtx_size += 2;
1102         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1103                 vtx_size++;
1104         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1105                 vtx_size += 2;
1106         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1107                 vtx_size++;
1108         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1109                 vtx_size += 2;
1110         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1111                 vtx_size++;
1112         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1113                 vtx_size++;
1114         /* blend weight */
1115         if (vtx_fmt & (0x7 << 15))
1116                 vtx_size += (vtx_fmt >> 15) & 0x7;
1117         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1118                 vtx_size += 3;
1119         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1120                 vtx_size += 2;
1121         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1122                 vtx_size++;
1123         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1124                 vtx_size++;
1125         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1126                 vtx_size++;
1127         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1128                 vtx_size++;
1129         return vtx_size;
1130 }
1131
1132 static int r100_packet0_check(struct radeon_cs_parser *p,
1133                               struct radeon_cs_packet *pkt,
1134                               unsigned idx, unsigned reg)
1135 {
1136         struct radeon_cs_reloc *reloc;
1137         struct r100_cs_track *track;
1138         volatile uint32_t *ib;
1139         uint32_t tmp;
1140         int r;
1141         int i, face;
1142         u32 tile_flags = 0;
1143         u32 idx_value;
1144
1145         ib = p->ib->ptr;
1146         track = (struct r100_cs_track *)p->track;
1147
1148         idx_value = radeon_get_ib_value(p, idx);
1149
1150         switch (reg) {
1151         case RADEON_CRTC_GUI_TRIG_VLINE:
1152                 r = r100_cs_packet_parse_vline(p);
1153                 if (r) {
1154                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1155                                   idx, reg);
1156                         r100_cs_dump_packet(p, pkt);
1157                         return r;
1158                 }
1159                 break;
1160                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1161                  * range access */
1162         case RADEON_DST_PITCH_OFFSET:
1163         case RADEON_SRC_PITCH_OFFSET:
1164                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1165                 if (r)
1166                         return r;
1167                 break;
1168         case RADEON_RB3D_DEPTHOFFSET:
1169                 r = r100_cs_packet_next_reloc(p, &reloc);
1170                 if (r) {
1171                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1172                                   idx, reg);
1173                         r100_cs_dump_packet(p, pkt);
1174                         return r;
1175                 }
1176                 track->zb.robj = reloc->robj;
1177                 track->zb.offset = idx_value;
1178                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179                 break;
1180         case RADEON_RB3D_COLOROFFSET:
1181                 r = r100_cs_packet_next_reloc(p, &reloc);
1182                 if (r) {
1183                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1184                                   idx, reg);
1185                         r100_cs_dump_packet(p, pkt);
1186                         return r;
1187                 }
1188                 track->cb[0].robj = reloc->robj;
1189                 track->cb[0].offset = idx_value;
1190                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1191                 break;
1192         case RADEON_PP_TXOFFSET_0:
1193         case RADEON_PP_TXOFFSET_1:
1194         case RADEON_PP_TXOFFSET_2:
1195                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1196                 r = r100_cs_packet_next_reloc(p, &reloc);
1197                 if (r) {
1198                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1199                                   idx, reg);
1200                         r100_cs_dump_packet(p, pkt);
1201                         return r;
1202                 }
1203                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1204                 track->textures[i].robj = reloc->robj;
1205                 break;
1206         case RADEON_PP_CUBIC_OFFSET_T0_0:
1207         case RADEON_PP_CUBIC_OFFSET_T0_1:
1208         case RADEON_PP_CUBIC_OFFSET_T0_2:
1209         case RADEON_PP_CUBIC_OFFSET_T0_3:
1210         case RADEON_PP_CUBIC_OFFSET_T0_4:
1211                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1212                 r = r100_cs_packet_next_reloc(p, &reloc);
1213                 if (r) {
1214                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1215                                   idx, reg);
1216                         r100_cs_dump_packet(p, pkt);
1217                         return r;
1218                 }
1219                 track->textures[0].cube_info[i].offset = idx_value;
1220                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1221                 track->textures[0].cube_info[i].robj = reloc->robj;
1222                 break;
1223         case RADEON_PP_CUBIC_OFFSET_T1_0:
1224         case RADEON_PP_CUBIC_OFFSET_T1_1:
1225         case RADEON_PP_CUBIC_OFFSET_T1_2:
1226         case RADEON_PP_CUBIC_OFFSET_T1_3:
1227         case RADEON_PP_CUBIC_OFFSET_T1_4:
1228                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1229                 r = r100_cs_packet_next_reloc(p, &reloc);
1230                 if (r) {
1231                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1232                                   idx, reg);
1233                         r100_cs_dump_packet(p, pkt);
1234                         return r;
1235                 }
1236                 track->textures[1].cube_info[i].offset = idx_value;
1237                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1238                 track->textures[1].cube_info[i].robj = reloc->robj;
1239                 break;
1240         case RADEON_PP_CUBIC_OFFSET_T2_0:
1241         case RADEON_PP_CUBIC_OFFSET_T2_1:
1242         case RADEON_PP_CUBIC_OFFSET_T2_2:
1243         case RADEON_PP_CUBIC_OFFSET_T2_3:
1244         case RADEON_PP_CUBIC_OFFSET_T2_4:
1245                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1246                 r = r100_cs_packet_next_reloc(p, &reloc);
1247                 if (r) {
1248                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1249                                   idx, reg);
1250                         r100_cs_dump_packet(p, pkt);
1251                         return r;
1252                 }
1253                 track->textures[2].cube_info[i].offset = idx_value;
1254                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1255                 track->textures[2].cube_info[i].robj = reloc->robj;
1256                 break;
1257         case RADEON_RE_WIDTH_HEIGHT:
1258                 track->maxy = ((idx_value >> 16) & 0x7FF);
1259                 break;
1260         case RADEON_RB3D_COLORPITCH:
1261                 r = r100_cs_packet_next_reloc(p, &reloc);
1262                 if (r) {
1263                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1264                                   idx, reg);
1265                         r100_cs_dump_packet(p, pkt);
1266                         return r;
1267                 }
1268
1269                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1270                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1271                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1272                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1273
1274                 tmp = idx_value & ~(0x7 << 16);
1275                 tmp |= tile_flags;
1276                 ib[idx] = tmp;
1277
1278                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1279                 break;
1280         case RADEON_RB3D_DEPTHPITCH:
1281                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1282                 break;
1283         case RADEON_RB3D_CNTL:
1284                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1285                 case 7:
1286                 case 8:
1287                 case 9:
1288                 case 11:
1289                 case 12:
1290                         track->cb[0].cpp = 1;
1291                         break;
1292                 case 3:
1293                 case 4:
1294                 case 15:
1295                         track->cb[0].cpp = 2;
1296                         break;
1297                 case 6:
1298                         track->cb[0].cpp = 4;
1299                         break;
1300                 default:
1301                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1302                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1303                         return -EINVAL;
1304                 }
1305                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1306                 break;
1307         case RADEON_RB3D_ZSTENCILCNTL:
1308                 switch (idx_value & 0xf) {
1309                 case 0:
1310                         track->zb.cpp = 2;
1311                         break;
1312                 case 2:
1313                 case 3:
1314                 case 4:
1315                 case 5:
1316                 case 9:
1317                 case 11:
1318                         track->zb.cpp = 4;
1319                         break;
1320                 default:
1321                         break;
1322                 }
1323                 break;
1324         case RADEON_RB3D_ZPASS_ADDR:
1325                 r = r100_cs_packet_next_reloc(p, &reloc);
1326                 if (r) {
1327                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1328                                   idx, reg);
1329                         r100_cs_dump_packet(p, pkt);
1330                         return r;
1331                 }
1332                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1333                 break;
1334         case RADEON_PP_CNTL:
1335                 {
1336                         uint32_t temp = idx_value >> 4;
1337                         for (i = 0; i < track->num_texture; i++)
1338                                 track->textures[i].enabled = !!(temp & (1 << i));
1339                 }
1340                 break;
1341         case RADEON_SE_VF_CNTL:
1342                 track->vap_vf_cntl = idx_value;
1343                 break;
1344         case RADEON_SE_VTX_FMT:
1345                 track->vtx_size = r100_get_vtx_size(idx_value);
1346                 break;
1347         case RADEON_PP_TEX_SIZE_0:
1348         case RADEON_PP_TEX_SIZE_1:
1349         case RADEON_PP_TEX_SIZE_2:
1350                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1351                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1352                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1353                 break;
1354         case RADEON_PP_TEX_PITCH_0:
1355         case RADEON_PP_TEX_PITCH_1:
1356         case RADEON_PP_TEX_PITCH_2:
1357                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1358                 track->textures[i].pitch = idx_value + 32;
1359                 break;
1360         case RADEON_PP_TXFILTER_0:
1361         case RADEON_PP_TXFILTER_1:
1362         case RADEON_PP_TXFILTER_2:
1363                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1364                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1365                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1366                 tmp = (idx_value >> 23) & 0x7;
1367                 if (tmp == 2 || tmp == 6)
1368                         track->textures[i].roundup_w = false;
1369                 tmp = (idx_value >> 27) & 0x7;
1370                 if (tmp == 2 || tmp == 6)
1371                         track->textures[i].roundup_h = false;
1372                 break;
1373         case RADEON_PP_TXFORMAT_0:
1374         case RADEON_PP_TXFORMAT_1:
1375         case RADEON_PP_TXFORMAT_2:
1376                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1377                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1378                         track->textures[i].use_pitch = 1;
1379                 } else {
1380                         track->textures[i].use_pitch = 0;
1381                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1382                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1383                 }
1384                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1385                         track->textures[i].tex_coord_type = 2;
1386                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1387                 case RADEON_TXFORMAT_I8:
1388                 case RADEON_TXFORMAT_RGB332:
1389                 case RADEON_TXFORMAT_Y8:
1390                         track->textures[i].cpp = 1;
1391                         break;
1392                 case RADEON_TXFORMAT_AI88:
1393                 case RADEON_TXFORMAT_ARGB1555:
1394                 case RADEON_TXFORMAT_RGB565:
1395                 case RADEON_TXFORMAT_ARGB4444:
1396                 case RADEON_TXFORMAT_VYUY422:
1397                 case RADEON_TXFORMAT_YVYU422:
1398                 case RADEON_TXFORMAT_SHADOW16:
1399                 case RADEON_TXFORMAT_LDUDV655:
1400                 case RADEON_TXFORMAT_DUDV88:
1401                         track->textures[i].cpp = 2;
1402                         break;
1403                 case RADEON_TXFORMAT_ARGB8888:
1404                 case RADEON_TXFORMAT_RGBA8888:
1405                 case RADEON_TXFORMAT_SHADOW32:
1406                 case RADEON_TXFORMAT_LDUDUV8888:
1407                         track->textures[i].cpp = 4;
1408                         break;
1409                 case RADEON_TXFORMAT_DXT1:
1410                         track->textures[i].cpp = 1;
1411                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1412                         break;
1413                 case RADEON_TXFORMAT_DXT23:
1414                 case RADEON_TXFORMAT_DXT45:
1415                         track->textures[i].cpp = 1;
1416                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1417                         break;
1418                 }
1419                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1420                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1421                 break;
1422         case RADEON_PP_CUBIC_FACES_0:
1423         case RADEON_PP_CUBIC_FACES_1:
1424         case RADEON_PP_CUBIC_FACES_2:
1425                 tmp = idx_value;
1426                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1427                 for (face = 0; face < 4; face++) {
1428                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1429                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1430                 }
1431                 break;
1432         default:
1433                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1434                        reg, idx);
1435                 return -EINVAL;
1436         }
1437         return 0;
1438 }
1439
1440 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1441                                          struct radeon_cs_packet *pkt,
1442                                          struct radeon_bo *robj)
1443 {
1444         unsigned idx;
1445         u32 value;
1446         idx = pkt->idx + 1;
1447         value = radeon_get_ib_value(p, idx + 2);
1448         if ((value + 1) > radeon_bo_size(robj)) {
1449                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1450                           "(need %u have %lu) !\n",
1451                           value + 1,
1452                           radeon_bo_size(robj));
1453                 return -EINVAL;
1454         }
1455         return 0;
1456 }
1457
1458 static int r100_packet3_check(struct radeon_cs_parser *p,
1459                               struct radeon_cs_packet *pkt)
1460 {
1461         struct radeon_cs_reloc *reloc;
1462         struct r100_cs_track *track;
1463         unsigned idx;
1464         volatile uint32_t *ib;
1465         int r;
1466
1467         ib = p->ib->ptr;
1468         idx = pkt->idx + 1;
1469         track = (struct r100_cs_track *)p->track;
1470         switch (pkt->opcode) {
1471         case PACKET3_3D_LOAD_VBPNTR:
1472                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1473                 if (r)
1474                         return r;
1475                 break;
1476         case PACKET3_INDX_BUFFER:
1477                 r = r100_cs_packet_next_reloc(p, &reloc);
1478                 if (r) {
1479                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1480                         r100_cs_dump_packet(p, pkt);
1481                         return r;
1482                 }
1483                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1484                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1485                 if (r) {
1486                         return r;
1487                 }
1488                 break;
1489         case 0x23:
1490                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1491                 r = r100_cs_packet_next_reloc(p, &reloc);
1492                 if (r) {
1493                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1494                         r100_cs_dump_packet(p, pkt);
1495                         return r;
1496                 }
1497                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1498                 track->num_arrays = 1;
1499                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1500
1501                 track->arrays[0].robj = reloc->robj;
1502                 track->arrays[0].esize = track->vtx_size;
1503
1504                 track->max_indx = radeon_get_ib_value(p, idx+1);
1505
1506                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1507                 track->immd_dwords = pkt->count - 1;
1508                 r = r100_cs_track_check(p->rdev, track);
1509                 if (r)
1510                         return r;
1511                 break;
1512         case PACKET3_3D_DRAW_IMMD:
1513                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1514                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1515                         return -EINVAL;
1516                 }
1517                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1518                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1519                 track->immd_dwords = pkt->count - 1;
1520                 r = r100_cs_track_check(p->rdev, track);
1521                 if (r)
1522                         return r;
1523                 break;
1524                 /* triggers drawing using in-packet vertex data */
1525         case PACKET3_3D_DRAW_IMMD_2:
1526                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1527                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1528                         return -EINVAL;
1529                 }
1530                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1531                 track->immd_dwords = pkt->count;
1532                 r = r100_cs_track_check(p->rdev, track);
1533                 if (r)
1534                         return r;
1535                 break;
1536                 /* triggers drawing using in-packet vertex data */
1537         case PACKET3_3D_DRAW_VBUF_2:
1538                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1539                 r = r100_cs_track_check(p->rdev, track);
1540                 if (r)
1541                         return r;
1542                 break;
1543                 /* triggers drawing of vertex buffers setup elsewhere */
1544         case PACKET3_3D_DRAW_INDX_2:
1545                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1546                 r = r100_cs_track_check(p->rdev, track);
1547                 if (r)
1548                         return r;
1549                 break;
1550                 /* triggers drawing using indices to vertex buffer */
1551         case PACKET3_3D_DRAW_VBUF:
1552                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1553                 r = r100_cs_track_check(p->rdev, track);
1554                 if (r)
1555                         return r;
1556                 break;
1557                 /* triggers drawing of vertex buffers setup elsewhere */
1558         case PACKET3_3D_DRAW_INDX:
1559                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1560                 r = r100_cs_track_check(p->rdev, track);
1561                 if (r)
1562                         return r;
1563                 break;
1564                 /* triggers drawing using indices to vertex buffer */
1565         case PACKET3_NOP:
1566                 break;
1567         default:
1568                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1569                 return -EINVAL;
1570         }
1571         return 0;
1572 }
1573
1574 int r100_cs_parse(struct radeon_cs_parser *p)
1575 {
1576         struct radeon_cs_packet pkt;
1577         struct r100_cs_track *track;
1578         int r;
1579
1580         track = kzalloc(sizeof(*track), GFP_KERNEL);
1581         r100_cs_track_clear(p->rdev, track);
1582         p->track = track;
1583         do {
1584                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1585                 if (r) {
1586                         return r;
1587                 }
1588                 p->idx += pkt.count + 2;
1589                 switch (pkt.type) {
1590                         case PACKET_TYPE0:
1591                                 if (p->rdev->family >= CHIP_R200)
1592                                         r = r100_cs_parse_packet0(p, &pkt,
1593                                                                   p->rdev->config.r100.reg_safe_bm,
1594                                                                   p->rdev->config.r100.reg_safe_bm_size,
1595                                                                   &r200_packet0_check);
1596                                 else
1597                                         r = r100_cs_parse_packet0(p, &pkt,
1598                                                                   p->rdev->config.r100.reg_safe_bm,
1599                                                                   p->rdev->config.r100.reg_safe_bm_size,
1600                                                                   &r100_packet0_check);
1601                                 break;
1602                         case PACKET_TYPE2:
1603                                 break;
1604                         case PACKET_TYPE3:
1605                                 r = r100_packet3_check(p, &pkt);
1606                                 break;
1607                         default:
1608                                 DRM_ERROR("Unknown packet type %d !\n",
1609                                           pkt.type);
1610                                 return -EINVAL;
1611                 }
1612                 if (r) {
1613                         return r;
1614                 }
1615         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1616         return 0;
1617 }
1618
1619
1620 /*
1621  * Global GPU functions
1622  */
1623 void r100_errata(struct radeon_device *rdev)
1624 {
1625         rdev->pll_errata = 0;
1626
1627         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1628                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1629         }
1630
1631         if (rdev->family == CHIP_RV100 ||
1632             rdev->family == CHIP_RS100 ||
1633             rdev->family == CHIP_RS200) {
1634                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1635         }
1636 }
1637
1638 /* Wait for vertical sync on primary CRTC */
1639 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1640 {
1641         uint32_t crtc_gen_cntl, tmp;
1642         int i;
1643
1644         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1645         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1646             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1647                 return;
1648         }
1649         /* Clear the CRTC_VBLANK_SAVE bit */
1650         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1651         for (i = 0; i < rdev->usec_timeout; i++) {
1652                 tmp = RREG32(RADEON_CRTC_STATUS);
1653                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1654                         return;
1655                 }
1656                 DRM_UDELAY(1);
1657         }
1658 }
1659
1660 /* Wait for vertical sync on secondary CRTC */
1661 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1662 {
1663         uint32_t crtc2_gen_cntl, tmp;
1664         int i;
1665
1666         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1667         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1668             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1669                 return;
1670
1671         /* Clear the CRTC_VBLANK_SAVE bit */
1672         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1673         for (i = 0; i < rdev->usec_timeout; i++) {
1674                 tmp = RREG32(RADEON_CRTC2_STATUS);
1675                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1676                         return;
1677                 }
1678                 DRM_UDELAY(1);
1679         }
1680 }
1681
1682 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1683 {
1684         unsigned i;
1685         uint32_t tmp;
1686
1687         for (i = 0; i < rdev->usec_timeout; i++) {
1688                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1689                 if (tmp >= n) {
1690                         return 0;
1691                 }
1692                 DRM_UDELAY(1);
1693         }
1694         return -1;
1695 }
1696
1697 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1698 {
1699         unsigned i;
1700         uint32_t tmp;
1701
1702         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1703                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1704                        " Bad things might happen.\n");
1705         }
1706         for (i = 0; i < rdev->usec_timeout; i++) {
1707                 tmp = RREG32(RADEON_RBBM_STATUS);
1708                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1709                         return 0;
1710                 }
1711                 DRM_UDELAY(1);
1712         }
1713         return -1;
1714 }
1715
1716 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1717 {
1718         unsigned i;
1719         uint32_t tmp;
1720
1721         for (i = 0; i < rdev->usec_timeout; i++) {
1722                 /* read MC_STATUS */
1723                 tmp = RREG32(RADEON_MC_STATUS);
1724                 if (tmp & RADEON_MC_IDLE) {
1725                         return 0;
1726                 }
1727                 DRM_UDELAY(1);
1728         }
1729         return -1;
1730 }
1731
1732 void r100_gpu_init(struct radeon_device *rdev)
1733 {
1734         /* TODO: anythings to do here ? pipes ? */
1735         r100_hdp_reset(rdev);
1736 }
1737
1738 void r100_hdp_reset(struct radeon_device *rdev)
1739 {
1740         uint32_t tmp;
1741
1742         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1743         tmp |= (7 << 28);
1744         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1745         (void)RREG32(RADEON_HOST_PATH_CNTL);
1746         udelay(200);
1747         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1748         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1749         (void)RREG32(RADEON_HOST_PATH_CNTL);
1750 }
1751
1752 int r100_rb2d_reset(struct radeon_device *rdev)
1753 {
1754         uint32_t tmp;
1755         int i;
1756
1757         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1758         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1759         udelay(200);
1760         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1761         /* Wait to prevent race in RBBM_STATUS */
1762         mdelay(1);
1763         for (i = 0; i < rdev->usec_timeout; i++) {
1764                 tmp = RREG32(RADEON_RBBM_STATUS);
1765                 if (!(tmp & (1 << 26))) {
1766                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1767                                  tmp);
1768                         return 0;
1769                 }
1770                 DRM_UDELAY(1);
1771         }
1772         tmp = RREG32(RADEON_RBBM_STATUS);
1773         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1774         return -1;
1775 }
1776
1777 int r100_gpu_reset(struct radeon_device *rdev)
1778 {
1779         uint32_t status;
1780
1781         /* reset order likely matter */
1782         status = RREG32(RADEON_RBBM_STATUS);
1783         /* reset HDP */
1784         r100_hdp_reset(rdev);
1785         /* reset rb2d */
1786         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1787                 r100_rb2d_reset(rdev);
1788         }
1789         /* TODO: reset 3D engine */
1790         /* reset CP */
1791         status = RREG32(RADEON_RBBM_STATUS);
1792         if (status & (1 << 16)) {
1793                 r100_cp_reset(rdev);
1794         }
1795         /* Check if GPU is idle */
1796         status = RREG32(RADEON_RBBM_STATUS);
1797         if (status & RADEON_RBBM_ACTIVE) {
1798                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1799                 return -1;
1800         }
1801         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1802         return 0;
1803 }
1804
1805 void r100_set_common_regs(struct radeon_device *rdev)
1806 {
1807         struct drm_device *dev = rdev->ddev;
1808         bool force_dac2 = false;
1809
1810         /* set these so they don't interfere with anything */
1811         WREG32(RADEON_OV0_SCALE_CNTL, 0);
1812         WREG32(RADEON_SUBPIC_CNTL, 0);
1813         WREG32(RADEON_VIPH_CONTROL, 0);
1814         WREG32(RADEON_I2C_CNTL_1, 0);
1815         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1816         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1817         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1818
1819         /* always set up dac2 on rn50 and some rv100 as lots
1820          * of servers seem to wire it up to a VGA port but
1821          * don't report it in the bios connector
1822          * table.
1823          */
1824         switch (dev->pdev->device) {
1825                 /* RN50 */
1826         case 0x515e:
1827         case 0x5969:
1828                 force_dac2 = true;
1829                 break;
1830                 /* RV100*/
1831         case 0x5159:
1832         case 0x515a:
1833                 /* DELL triple head servers */
1834                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1835                     ((dev->pdev->subsystem_device == 0x016c) ||
1836                      (dev->pdev->subsystem_device == 0x016d) ||
1837                      (dev->pdev->subsystem_device == 0x016e) ||
1838                      (dev->pdev->subsystem_device == 0x016f) ||
1839                      (dev->pdev->subsystem_device == 0x0170) ||
1840                      (dev->pdev->subsystem_device == 0x017d) ||
1841                      (dev->pdev->subsystem_device == 0x017e) ||
1842                      (dev->pdev->subsystem_device == 0x0183) ||
1843                      (dev->pdev->subsystem_device == 0x018a) ||
1844                      (dev->pdev->subsystem_device == 0x019a)))
1845                         force_dac2 = true;
1846                 break;
1847         }
1848
1849         if (force_dac2) {
1850                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1851                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1852                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1853
1854                 /* For CRT on DAC2, don't turn it on if BIOS didn't
1855                    enable it, even it's detected.
1856                 */
1857
1858                 /* force it to crtc0 */
1859                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1860                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1861                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1862
1863                 /* set up the TV DAC */
1864                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1865                                  RADEON_TV_DAC_STD_MASK |
1866                                  RADEON_TV_DAC_RDACPD |
1867                                  RADEON_TV_DAC_GDACPD |
1868                                  RADEON_TV_DAC_BDACPD |
1869                                  RADEON_TV_DAC_BGADJ_MASK |
1870                                  RADEON_TV_DAC_DACADJ_MASK);
1871                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1872                                 RADEON_TV_DAC_NHOLD |
1873                                 RADEON_TV_DAC_STD_PS2 |
1874                                 (0x58 << 16));
1875
1876                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1877                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1878                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1879         }
1880 }
1881
1882 /*
1883  * VRAM info
1884  */
1885 static void r100_vram_get_type(struct radeon_device *rdev)
1886 {
1887         uint32_t tmp;
1888
1889         rdev->mc.vram_is_ddr = false;
1890         if (rdev->flags & RADEON_IS_IGP)
1891                 rdev->mc.vram_is_ddr = true;
1892         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1893                 rdev->mc.vram_is_ddr = true;
1894         if ((rdev->family == CHIP_RV100) ||
1895             (rdev->family == CHIP_RS100) ||
1896             (rdev->family == CHIP_RS200)) {
1897                 tmp = RREG32(RADEON_MEM_CNTL);
1898                 if (tmp & RV100_HALF_MODE) {
1899                         rdev->mc.vram_width = 32;
1900                 } else {
1901                         rdev->mc.vram_width = 64;
1902                 }
1903                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1904                         rdev->mc.vram_width /= 4;
1905                         rdev->mc.vram_is_ddr = true;
1906                 }
1907         } else if (rdev->family <= CHIP_RV280) {
1908                 tmp = RREG32(RADEON_MEM_CNTL);
1909                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1910                         rdev->mc.vram_width = 128;
1911                 } else {
1912                         rdev->mc.vram_width = 64;
1913                 }
1914         } else {
1915                 /* newer IGPs */
1916                 rdev->mc.vram_width = 128;
1917         }
1918 }
1919
1920 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1921 {
1922         u32 aper_size;
1923         u8 byte;
1924
1925         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1926
1927         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1928          * that is has the 2nd generation multifunction PCI interface
1929          */
1930         if (rdev->family == CHIP_RV280 ||
1931             rdev->family >= CHIP_RV350) {
1932                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1933                        ~RADEON_HDP_APER_CNTL);
1934                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1935                 return aper_size * 2;
1936         }
1937
1938         /* Older cards have all sorts of funny issues to deal with. First
1939          * check if it's a multifunction card by reading the PCI config
1940          * header type... Limit those to one aperture size
1941          */
1942         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1943         if (byte & 0x80) {
1944                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1945                 DRM_INFO("Limiting VRAM to one aperture\n");
1946                 return aper_size;
1947         }
1948
1949         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1950          * have set it up. We don't write this as it's broken on some ASICs but
1951          * we expect the BIOS to have done the right thing (might be too optimistic...)
1952          */
1953         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1954                 return aper_size * 2;
1955         return aper_size;
1956 }
1957
1958 void r100_vram_init_sizes(struct radeon_device *rdev)
1959 {
1960         u64 config_aper_size;
1961
1962         /* work out accessible VRAM */
1963         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1964         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1965         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1966         /* FIXME we don't use the second aperture yet when we could use it */
1967         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1968                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1969         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1970         if (rdev->flags & RADEON_IS_IGP) {
1971                 uint32_t tom;
1972                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1973                 tom = RREG32(RADEON_NB_TOM);
1974                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1975                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1976                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1977         } else {
1978                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1979                 /* Some production boards of m6 will report 0
1980                  * if it's 8 MB
1981                  */
1982                 if (rdev->mc.real_vram_size == 0) {
1983                         rdev->mc.real_vram_size = 8192 * 1024;
1984                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1985                 }
1986                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1987                  * Novell bug 204882 + along with lots of ubuntu ones
1988                  */
1989                 if (config_aper_size > rdev->mc.real_vram_size)
1990                         rdev->mc.mc_vram_size = config_aper_size;
1991                 else
1992                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1993         }
1994         /* FIXME remove this once we support unmappable VRAM */
1995         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1996                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1997                 rdev->mc.real_vram_size = rdev->mc.aper_size;
1998         }
1999 }
2000
2001 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2002 {
2003         uint32_t temp;
2004
2005         temp = RREG32(RADEON_CONFIG_CNTL);
2006         if (state == false) {
2007                 temp &= ~(1<<8);
2008                 temp |= (1<<9);
2009         } else {
2010                 temp &= ~(1<<9);
2011         }
2012         WREG32(RADEON_CONFIG_CNTL, temp);
2013 }
2014
2015 void r100_mc_init(struct radeon_device *rdev)
2016 {
2017         u64 base;
2018
2019         r100_vram_get_type(rdev);
2020         r100_vram_init_sizes(rdev);
2021         base = rdev->mc.aper_base;
2022         if (rdev->flags & RADEON_IS_IGP)
2023                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2024         radeon_vram_location(rdev, &rdev->mc, base);
2025         if (!(rdev->flags & RADEON_IS_AGP))
2026                 radeon_gtt_location(rdev, &rdev->mc);
2027 }
2028
2029
2030 /*
2031  * Indirect registers accessor
2032  */
2033 void r100_pll_errata_after_index(struct radeon_device *rdev)
2034 {
2035         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2036                 return;
2037         }
2038         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2039         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2040 }
2041
2042 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2043 {
2044         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2045          * or the chip could hang on a subsequent access
2046          */
2047         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2048                 udelay(5000);
2049         }
2050
2051         /* This function is required to workaround a hardware bug in some (all?)
2052          * revisions of the R300.  This workaround should be called after every
2053          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2054          * may not be correct.
2055          */
2056         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2057                 uint32_t save, tmp;
2058
2059                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2060                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2061                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2062                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2063                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2064         }
2065 }
2066
2067 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2068 {
2069         uint32_t data;
2070
2071         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2072         r100_pll_errata_after_index(rdev);
2073         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2074         r100_pll_errata_after_data(rdev);
2075         return data;
2076 }
2077
2078 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2079 {
2080         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2081         r100_pll_errata_after_index(rdev);
2082         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2083         r100_pll_errata_after_data(rdev);
2084 }
2085
2086 void r100_set_safe_registers(struct radeon_device *rdev)
2087 {
2088         if (ASIC_IS_RN50(rdev)) {
2089                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2090                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2091         } else if (rdev->family < CHIP_R200) {
2092                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2093                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2094         } else {
2095                 r200_set_safe_registers(rdev);
2096         }
2097 }
2098
2099 /*
2100  * Debugfs info
2101  */
2102 #if defined(CONFIG_DEBUG_FS)
2103 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2104 {
2105         struct drm_info_node *node = (struct drm_info_node *) m->private;
2106         struct drm_device *dev = node->minor->dev;
2107         struct radeon_device *rdev = dev->dev_private;
2108         uint32_t reg, value;
2109         unsigned i;
2110
2111         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2112         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2113         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2114         for (i = 0; i < 64; i++) {
2115                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2116                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2117                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2118                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2119                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2120         }
2121         return 0;
2122 }
2123
2124 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2125 {
2126         struct drm_info_node *node = (struct drm_info_node *) m->private;
2127         struct drm_device *dev = node->minor->dev;
2128         struct radeon_device *rdev = dev->dev_private;
2129         uint32_t rdp, wdp;
2130         unsigned count, i, j;
2131
2132         radeon_ring_free_size(rdev);
2133         rdp = RREG32(RADEON_CP_RB_RPTR);
2134         wdp = RREG32(RADEON_CP_RB_WPTR);
2135         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2136         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2137         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2138         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2139         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2140         seq_printf(m, "%u dwords in ring\n", count);
2141         for (j = 0; j <= count; j++) {
2142                 i = (rdp + j) & rdev->cp.ptr_mask;
2143                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2144         }
2145         return 0;
2146 }
2147
2148
2149 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2150 {
2151         struct drm_info_node *node = (struct drm_info_node *) m->private;
2152         struct drm_device *dev = node->minor->dev;
2153         struct radeon_device *rdev = dev->dev_private;
2154         uint32_t csq_stat, csq2_stat, tmp;
2155         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2156         unsigned i;
2157
2158         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2159         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2160         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2161         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2162         r_rptr = (csq_stat >> 0) & 0x3ff;
2163         r_wptr = (csq_stat >> 10) & 0x3ff;
2164         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2165         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2166         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2167         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2168         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2169         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2170         seq_printf(m, "Ring rptr %u\n", r_rptr);
2171         seq_printf(m, "Ring wptr %u\n", r_wptr);
2172         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2173         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2174         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2175         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2176         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2177          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2178         seq_printf(m, "Ring fifo:\n");
2179         for (i = 0; i < 256; i++) {
2180                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2181                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2182                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2183         }
2184         seq_printf(m, "Indirect1 fifo:\n");
2185         for (i = 256; i <= 512; i++) {
2186                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2187                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2188                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2189         }
2190         seq_printf(m, "Indirect2 fifo:\n");
2191         for (i = 640; i < ib1_wptr; i++) {
2192                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2193                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2194                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2195         }
2196         return 0;
2197 }
2198
2199 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2200 {
2201         struct drm_info_node *node = (struct drm_info_node *) m->private;
2202         struct drm_device *dev = node->minor->dev;
2203         struct radeon_device *rdev = dev->dev_private;
2204         uint32_t tmp;
2205
2206         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2207         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2208         tmp = RREG32(RADEON_MC_FB_LOCATION);
2209         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2210         tmp = RREG32(RADEON_BUS_CNTL);
2211         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2212         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2213         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2214         tmp = RREG32(RADEON_AGP_BASE);
2215         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2216         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2217         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2218         tmp = RREG32(0x01D0);
2219         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2220         tmp = RREG32(RADEON_AIC_LO_ADDR);
2221         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2222         tmp = RREG32(RADEON_AIC_HI_ADDR);
2223         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2224         tmp = RREG32(0x01E4);
2225         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2226         return 0;
2227 }
2228
2229 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2230         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2231 };
2232
2233 static struct drm_info_list r100_debugfs_cp_list[] = {
2234         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2235         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2236 };
2237
2238 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2239         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2240 };
2241 #endif
2242
2243 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2244 {
2245 #if defined(CONFIG_DEBUG_FS)
2246         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2247 #else
2248         return 0;
2249 #endif
2250 }
2251
2252 int r100_debugfs_cp_init(struct radeon_device *rdev)
2253 {
2254 #if defined(CONFIG_DEBUG_FS)
2255         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2256 #else
2257         return 0;
2258 #endif
2259 }
2260
2261 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2262 {
2263 #if defined(CONFIG_DEBUG_FS)
2264         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2265 #else
2266         return 0;
2267 #endif
2268 }
2269
2270 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2271                          uint32_t tiling_flags, uint32_t pitch,
2272                          uint32_t offset, uint32_t obj_size)
2273 {
2274         int surf_index = reg * 16;
2275         int flags = 0;
2276
2277         /* r100/r200 divide by 16 */
2278         if (rdev->family < CHIP_R300)
2279                 flags = pitch / 16;
2280         else
2281                 flags = pitch / 8;
2282
2283         if (rdev->family <= CHIP_RS200) {
2284                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2285                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2286                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2287                 if (tiling_flags & RADEON_TILING_MACRO)
2288                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2289         } else if (rdev->family <= CHIP_RV280) {
2290                 if (tiling_flags & (RADEON_TILING_MACRO))
2291                         flags |= R200_SURF_TILE_COLOR_MACRO;
2292                 if (tiling_flags & RADEON_TILING_MICRO)
2293                         flags |= R200_SURF_TILE_COLOR_MICRO;
2294         } else {
2295                 if (tiling_flags & RADEON_TILING_MACRO)
2296                         flags |= R300_SURF_TILE_MACRO;
2297                 if (tiling_flags & RADEON_TILING_MICRO)
2298                         flags |= R300_SURF_TILE_MICRO;
2299         }
2300
2301         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2302                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2303         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2304                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2305
2306         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2307         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2308         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2309         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2310         return 0;
2311 }
2312
2313 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2314 {
2315         int surf_index = reg * 16;
2316         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2317 }
2318
2319 void r100_bandwidth_update(struct radeon_device *rdev)
2320 {
2321         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2322         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2323         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2324         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2325         fixed20_12 memtcas_ff[8] = {
2326                 fixed_init(1),
2327                 fixed_init(2),
2328                 fixed_init(3),
2329                 fixed_init(0),
2330                 fixed_init_half(1),
2331                 fixed_init_half(2),
2332                 fixed_init(0),
2333         };
2334         fixed20_12 memtcas_rs480_ff[8] = {
2335                 fixed_init(0),
2336                 fixed_init(1),
2337                 fixed_init(2),
2338                 fixed_init(3),
2339                 fixed_init(0),
2340                 fixed_init_half(1),
2341                 fixed_init_half(2),
2342                 fixed_init_half(3),
2343         };
2344         fixed20_12 memtcas2_ff[8] = {
2345                 fixed_init(0),
2346                 fixed_init(1),
2347                 fixed_init(2),
2348                 fixed_init(3),
2349                 fixed_init(4),
2350                 fixed_init(5),
2351                 fixed_init(6),
2352                 fixed_init(7),
2353         };
2354         fixed20_12 memtrbs[8] = {
2355                 fixed_init(1),
2356                 fixed_init_half(1),
2357                 fixed_init(2),
2358                 fixed_init_half(2),
2359                 fixed_init(3),
2360                 fixed_init_half(3),
2361                 fixed_init(4),
2362                 fixed_init_half(4)
2363         };
2364         fixed20_12 memtrbs_r4xx[8] = {
2365                 fixed_init(4),
2366                 fixed_init(5),
2367                 fixed_init(6),
2368                 fixed_init(7),
2369                 fixed_init(8),
2370                 fixed_init(9),
2371                 fixed_init(10),
2372                 fixed_init(11)
2373         };
2374         fixed20_12 min_mem_eff;
2375         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2376         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2377         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2378                 disp_drain_rate2, read_return_rate;
2379         fixed20_12 time_disp1_drop_priority;
2380         int c;
2381         int cur_size = 16;       /* in octawords */
2382         int critical_point = 0, critical_point2;
2383 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2384         int stop_req, max_stop_req;
2385         struct drm_display_mode *mode1 = NULL;
2386         struct drm_display_mode *mode2 = NULL;
2387         uint32_t pixel_bytes1 = 0;
2388         uint32_t pixel_bytes2 = 0;
2389
2390         if (rdev->mode_info.crtcs[0]->base.enabled) {
2391                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2392                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2393         }
2394         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2395                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2396                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2397                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2398                 }
2399         }
2400
2401         min_mem_eff.full = rfixed_const_8(0);
2402         /* get modes */
2403         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2404                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2405                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2406                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2407                 /* check crtc enables */
2408                 if (mode2)
2409                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2410                 if (mode1)
2411                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2412                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2413         }
2414
2415         /*
2416          * determine is there is enough bw for current mode
2417          */
2418         mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2419         temp_ff.full = rfixed_const(100);
2420         mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2421         sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2422         sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2423
2424         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2425         temp_ff.full = rfixed_const(temp);
2426         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2427
2428         pix_clk.full = 0;
2429         pix_clk2.full = 0;
2430         peak_disp_bw.full = 0;
2431         if (mode1) {
2432                 temp_ff.full = rfixed_const(1000);
2433                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2434                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2435                 temp_ff.full = rfixed_const(pixel_bytes1);
2436                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2437         }
2438         if (mode2) {
2439                 temp_ff.full = rfixed_const(1000);
2440                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2441                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2442                 temp_ff.full = rfixed_const(pixel_bytes2);
2443                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2444         }
2445
2446         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2447         if (peak_disp_bw.full >= mem_bw.full) {
2448                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2449                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2450         }
2451
2452         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2453         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2454         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2455                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2456                 mem_trp  = ((temp & 0x3)) + 1;
2457                 mem_tras = ((temp & 0x70) >> 4) + 1;
2458         } else if (rdev->family == CHIP_R300 ||
2459                    rdev->family == CHIP_R350) { /* r300, r350 */
2460                 mem_trcd = (temp & 0x7) + 1;
2461                 mem_trp = ((temp >> 8) & 0x7) + 1;
2462                 mem_tras = ((temp >> 11) & 0xf) + 4;
2463         } else if (rdev->family == CHIP_RV350 ||
2464                    rdev->family <= CHIP_RV380) {
2465                 /* rv3x0 */
2466                 mem_trcd = (temp & 0x7) + 3;
2467                 mem_trp = ((temp >> 8) & 0x7) + 3;
2468                 mem_tras = ((temp >> 11) & 0xf) + 6;
2469         } else if (rdev->family == CHIP_R420 ||
2470                    rdev->family == CHIP_R423 ||
2471                    rdev->family == CHIP_RV410) {
2472                 /* r4xx */
2473                 mem_trcd = (temp & 0xf) + 3;
2474                 if (mem_trcd > 15)
2475                         mem_trcd = 15;
2476                 mem_trp = ((temp >> 8) & 0xf) + 3;
2477                 if (mem_trp > 15)
2478                         mem_trp = 15;
2479                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2480                 if (mem_tras > 31)
2481                         mem_tras = 31;
2482         } else { /* RV200, R200 */
2483                 mem_trcd = (temp & 0x7) + 1;
2484                 mem_trp = ((temp >> 8) & 0x7) + 1;
2485                 mem_tras = ((temp >> 12) & 0xf) + 4;
2486         }
2487         /* convert to FF */
2488         trcd_ff.full = rfixed_const(mem_trcd);
2489         trp_ff.full = rfixed_const(mem_trp);
2490         tras_ff.full = rfixed_const(mem_tras);
2491
2492         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2493         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2494         data = (temp & (7 << 20)) >> 20;
2495         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2496                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2497                         tcas_ff = memtcas_rs480_ff[data];
2498                 else
2499                         tcas_ff = memtcas_ff[data];
2500         } else
2501                 tcas_ff = memtcas2_ff[data];
2502
2503         if (rdev->family == CHIP_RS400 ||
2504             rdev->family == CHIP_RS480) {
2505                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2506                 data = (temp >> 23) & 0x7;
2507                 if (data < 5)
2508                         tcas_ff.full += rfixed_const(data);
2509         }
2510
2511         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2512                 /* on the R300, Tcas is included in Trbs.
2513                  */
2514                 temp = RREG32(RADEON_MEM_CNTL);
2515                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2516                 if (data == 1) {
2517                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2518                                 temp = RREG32(R300_MC_IND_INDEX);
2519                                 temp &= ~R300_MC_IND_ADDR_MASK;
2520                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2521                                 WREG32(R300_MC_IND_INDEX, temp);
2522                                 temp = RREG32(R300_MC_IND_DATA);
2523                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2524                         } else {
2525                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2526                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2527                         }
2528                 } else {
2529                         temp = RREG32(R300_MC_READ_CNTL_AB);
2530                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2531                 }
2532                 if (rdev->family == CHIP_RV410 ||
2533                     rdev->family == CHIP_R420 ||
2534                     rdev->family == CHIP_R423)
2535                         trbs_ff = memtrbs_r4xx[data];
2536                 else
2537                         trbs_ff = memtrbs[data];
2538                 tcas_ff.full += trbs_ff.full;
2539         }
2540
2541         sclk_eff_ff.full = sclk_ff.full;
2542
2543         if (rdev->flags & RADEON_IS_AGP) {
2544                 fixed20_12 agpmode_ff;
2545                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2546                 temp_ff.full = rfixed_const_666(16);
2547                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2548         }
2549         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2550
2551         if (ASIC_IS_R300(rdev)) {
2552                 sclk_delay_ff.full = rfixed_const(250);
2553         } else {
2554                 if ((rdev->family == CHIP_RV100) ||
2555                     rdev->flags & RADEON_IS_IGP) {
2556                         if (rdev->mc.vram_is_ddr)
2557                                 sclk_delay_ff.full = rfixed_const(41);
2558                         else
2559                                 sclk_delay_ff.full = rfixed_const(33);
2560                 } else {
2561                         if (rdev->mc.vram_width == 128)
2562                                 sclk_delay_ff.full = rfixed_const(57);
2563                         else
2564                                 sclk_delay_ff.full = rfixed_const(41);
2565                 }
2566         }
2567
2568         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2569
2570         if (rdev->mc.vram_is_ddr) {
2571                 if (rdev->mc.vram_width == 32) {
2572                         k1.full = rfixed_const(40);
2573                         c  = 3;
2574                 } else {
2575                         k1.full = rfixed_const(20);
2576                         c  = 1;
2577                 }
2578         } else {
2579                 k1.full = rfixed_const(40);
2580                 c  = 3;
2581         }
2582
2583         temp_ff.full = rfixed_const(2);
2584         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2585         temp_ff.full = rfixed_const(c);
2586         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2587         temp_ff.full = rfixed_const(4);
2588         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2589         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2590         mc_latency_mclk.full += k1.full;
2591
2592         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2593         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2594
2595         /*
2596           HW cursor time assuming worst case of full size colour cursor.
2597         */
2598         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2599         temp_ff.full += trcd_ff.full;
2600         if (temp_ff.full < tras_ff.full)
2601                 temp_ff.full = tras_ff.full;
2602         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2603
2604         temp_ff.full = rfixed_const(cur_size);
2605         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2606         /*
2607           Find the total latency for the display data.
2608         */
2609         disp_latency_overhead.full = rfixed_const(8);
2610         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2611         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2612         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2613
2614         if (mc_latency_mclk.full > mc_latency_sclk.full)
2615                 disp_latency.full = mc_latency_mclk.full;
2616         else
2617                 disp_latency.full = mc_latency_sclk.full;
2618
2619         /* setup Max GRPH_STOP_REQ default value */
2620         if (ASIC_IS_RV100(rdev))
2621                 max_stop_req = 0x5c;
2622         else
2623                 max_stop_req = 0x7c;
2624
2625         if (mode1) {
2626                 /*  CRTC1
2627                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2628                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2629                 */
2630                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2631
2632                 if (stop_req > max_stop_req)
2633                         stop_req = max_stop_req;
2634
2635                 /*
2636                   Find the drain rate of the display buffer.
2637                 */
2638                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2639                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2640
2641                 /*
2642                   Find the critical point of the display buffer.
2643                 */
2644                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2645                 crit_point_ff.full += rfixed_const_half(0);
2646
2647                 critical_point = rfixed_trunc(crit_point_ff);
2648
2649                 if (rdev->disp_priority == 2) {
2650                         critical_point = 0;
2651                 }
2652
2653                 /*
2654                   The critical point should never be above max_stop_req-4.  Setting
2655                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2656                 */
2657                 if (max_stop_req - critical_point < 4)
2658                         critical_point = 0;
2659
2660                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2661                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2662                         critical_point = 0x10;
2663                 }
2664
2665                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2666                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2667                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2668                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2669                 if ((rdev->family == CHIP_R350) &&
2670                     (stop_req > 0x15)) {
2671                         stop_req -= 0x10;
2672                 }
2673                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2674                 temp |= RADEON_GRPH_BUFFER_SIZE;
2675                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2676                           RADEON_GRPH_CRITICAL_AT_SOF |
2677                           RADEON_GRPH_STOP_CNTL);
2678                 /*
2679                   Write the result into the register.
2680                 */
2681                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2682                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2683
2684 #if 0
2685                 if ((rdev->family == CHIP_RS400) ||
2686                     (rdev->family == CHIP_RS480)) {
2687                         /* attempt to program RS400 disp regs correctly ??? */
2688                         temp = RREG32(RS400_DISP1_REG_CNTL);
2689                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2690                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2691                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2692                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2693                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2694                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2695                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2696                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2697                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2698                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2699                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2700                 }
2701 #endif
2702
2703                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2704                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2705                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2706         }
2707
2708         if (mode2) {
2709                 u32 grph2_cntl;
2710                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2711
2712                 if (stop_req > max_stop_req)
2713                         stop_req = max_stop_req;
2714
2715                 /*
2716                   Find the drain rate of the display buffer.
2717                 */
2718                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2719                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2720
2721                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2722                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2723                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2724                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2725                 if ((rdev->family == CHIP_R350) &&
2726                     (stop_req > 0x15)) {
2727                         stop_req -= 0x10;
2728                 }
2729                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2730                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2731                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2732                           RADEON_GRPH_CRITICAL_AT_SOF |
2733                           RADEON_GRPH_STOP_CNTL);
2734
2735                 if ((rdev->family == CHIP_RS100) ||
2736                     (rdev->family == CHIP_RS200))
2737                         critical_point2 = 0;
2738                 else {
2739                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2740                         temp_ff.full = rfixed_const(temp);
2741                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2742                         if (sclk_ff.full < temp_ff.full)
2743                                 temp_ff.full = sclk_ff.full;
2744
2745                         read_return_rate.full = temp_ff.full;
2746
2747                         if (mode1) {
2748                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2749                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2750                         } else {
2751                                 time_disp1_drop_priority.full = 0;
2752                         }
2753                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2754                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2755                         crit_point_ff.full += rfixed_const_half(0);
2756
2757                         critical_point2 = rfixed_trunc(crit_point_ff);
2758
2759                         if (rdev->disp_priority == 2) {
2760                                 critical_point2 = 0;
2761                         }
2762
2763                         if (max_stop_req - critical_point2 < 4)
2764                                 critical_point2 = 0;
2765
2766                 }
2767
2768                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2769                         /* some R300 cards have problem with this set to 0 */
2770                         critical_point2 = 0x10;
2771                 }
2772
2773                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2774                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2775
2776                 if ((rdev->family == CHIP_RS400) ||
2777                     (rdev->family == CHIP_RS480)) {
2778 #if 0
2779                         /* attempt to program RS400 disp2 regs correctly ??? */
2780                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2781                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2782                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2783                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2784                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2785                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2786                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2787                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2788                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2789                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2790                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2791                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2792 #endif
2793                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2794                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2795                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2796                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2797                 }
2798
2799                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2800                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2801         }
2802 }
2803
2804 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2805 {
2806         DRM_ERROR("pitch                      %d\n", t->pitch);
2807         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2808         DRM_ERROR("width                      %d\n", t->width);
2809         DRM_ERROR("width_11                   %d\n", t->width_11);
2810         DRM_ERROR("height                     %d\n", t->height);
2811         DRM_ERROR("height_11                  %d\n", t->height_11);
2812         DRM_ERROR("num levels                 %d\n", t->num_levels);
2813         DRM_ERROR("depth                      %d\n", t->txdepth);
2814         DRM_ERROR("bpp                        %d\n", t->cpp);
2815         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2816         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2817         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2818         DRM_ERROR("compress format            %d\n", t->compress_format);
2819 }
2820
2821 static int r100_cs_track_cube(struct radeon_device *rdev,
2822                               struct r100_cs_track *track, unsigned idx)
2823 {
2824         unsigned face, w, h;
2825         struct radeon_bo *cube_robj;
2826         unsigned long size;
2827
2828         for (face = 0; face < 5; face++) {
2829                 cube_robj = track->textures[idx].cube_info[face].robj;
2830                 w = track->textures[idx].cube_info[face].width;
2831                 h = track->textures[idx].cube_info[face].height;
2832
2833                 size = w * h;
2834                 size *= track->textures[idx].cpp;
2835
2836                 size += track->textures[idx].cube_info[face].offset;
2837
2838                 if (size > radeon_bo_size(cube_robj)) {
2839                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2840                                   size, radeon_bo_size(cube_robj));
2841                         r100_cs_track_texture_print(&track->textures[idx]);
2842                         return -1;
2843                 }
2844         }
2845         return 0;
2846 }
2847
2848 static int r100_track_compress_size(int compress_format, int w, int h)
2849 {
2850         int block_width, block_height, block_bytes;
2851         int wblocks, hblocks;
2852         int min_wblocks;
2853         int sz;
2854
2855         block_width = 4;
2856         block_height = 4;
2857
2858         switch (compress_format) {
2859         case R100_TRACK_COMP_DXT1:
2860                 block_bytes = 8;
2861                 min_wblocks = 4;
2862                 break;
2863         default:
2864         case R100_TRACK_COMP_DXT35:
2865                 block_bytes = 16;
2866                 min_wblocks = 2;
2867                 break;
2868         }
2869
2870         hblocks = (h + block_height - 1) / block_height;
2871         wblocks = (w + block_width - 1) / block_width;
2872         if (wblocks < min_wblocks)
2873                 wblocks = min_wblocks;
2874         sz = wblocks * hblocks * block_bytes;
2875         return sz;
2876 }
2877
2878 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2879                                        struct r100_cs_track *track)
2880 {
2881         struct radeon_bo *robj;
2882         unsigned long size;
2883         unsigned u, i, w, h;
2884         int ret;
2885
2886         for (u = 0; u < track->num_texture; u++) {
2887                 if (!track->textures[u].enabled)
2888                         continue;
2889                 robj = track->textures[u].robj;
2890                 if (robj == NULL) {
2891                         DRM_ERROR("No texture bound to unit %u\n", u);
2892                         return -EINVAL;
2893                 }
2894                 size = 0;
2895                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2896                         if (track->textures[u].use_pitch) {
2897                                 if (rdev->family < CHIP_R300)
2898                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2899                                 else
2900                                         w = track->textures[u].pitch / (1 << i);
2901                         } else {
2902                                 w = track->textures[u].width;
2903                                 if (rdev->family >= CHIP_RV515)
2904                                         w |= track->textures[u].width_11;
2905                                 w = w / (1 << i);
2906                                 if (track->textures[u].roundup_w)
2907                                         w = roundup_pow_of_two(w);
2908                         }
2909                         h = track->textures[u].height;
2910                         if (rdev->family >= CHIP_RV515)
2911                                 h |= track->textures[u].height_11;
2912                         h = h / (1 << i);
2913                         if (track->textures[u].roundup_h)
2914                                 h = roundup_pow_of_two(h);
2915                         if (track->textures[u].compress_format) {
2916
2917                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2918                                 /* compressed textures are block based */
2919                         } else
2920                                 size += w * h;
2921                 }
2922                 size *= track->textures[u].cpp;
2923
2924                 switch (track->textures[u].tex_coord_type) {
2925                 case 0:
2926                         break;
2927                 case 1:
2928                         size *= (1 << track->textures[u].txdepth);
2929                         break;
2930                 case 2:
2931                         if (track->separate_cube) {
2932                                 ret = r100_cs_track_cube(rdev, track, u);
2933                                 if (ret)
2934                                         return ret;
2935                         } else
2936                                 size *= 6;
2937                         break;
2938                 default:
2939                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2940                                   "%u\n", track->textures[u].tex_coord_type, u);
2941                         return -EINVAL;
2942                 }
2943                 if (size > radeon_bo_size(robj)) {
2944                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2945                                   "%lu\n", u, size, radeon_bo_size(robj));
2946                         r100_cs_track_texture_print(&track->textures[u]);
2947                         return -EINVAL;
2948                 }
2949         }
2950         return 0;
2951 }
2952
2953 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2954 {
2955         unsigned i;
2956         unsigned long size;
2957         unsigned prim_walk;
2958         unsigned nverts;
2959
2960         for (i = 0; i < track->num_cb; i++) {
2961                 if (track->cb[i].robj == NULL) {
2962                         if (!(track->fastfill || track->color_channel_mask ||
2963                               track->blend_read_enable)) {
2964                                 continue;
2965                         }
2966                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2967                         return -EINVAL;
2968                 }
2969                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2970                 size += track->cb[i].offset;
2971                 if (size > radeon_bo_size(track->cb[i].robj)) {
2972                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2973                                   "(need %lu have %lu) !\n", i, size,
2974                                   radeon_bo_size(track->cb[i].robj));
2975                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2976                                   i, track->cb[i].pitch, track->cb[i].cpp,
2977                                   track->cb[i].offset, track->maxy);
2978                         return -EINVAL;
2979                 }
2980         }
2981         if (track->z_enabled) {
2982                 if (track->zb.robj == NULL) {
2983                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2984                         return -EINVAL;
2985                 }
2986                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2987                 size += track->zb.offset;
2988                 if (size > radeon_bo_size(track->zb.robj)) {
2989                         DRM_ERROR("[drm] Buffer too small for z buffer "
2990                                   "(need %lu have %lu) !\n", size,
2991                                   radeon_bo_size(track->zb.robj));
2992                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2993                                   track->zb.pitch, track->zb.cpp,
2994                                   track->zb.offset, track->maxy);
2995                         return -EINVAL;
2996                 }
2997         }
2998         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2999         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3000         switch (prim_walk) {
3001         case 1:
3002                 for (i = 0; i < track->num_arrays; i++) {
3003                         size = track->arrays[i].esize * track->max_indx * 4;
3004                         if (track->arrays[i].robj == NULL) {
3005                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3006                                           "bound\n", prim_walk, i);
3007                                 return -EINVAL;
3008                         }
3009                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3010                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3011                                         "need %lu dwords have %lu dwords\n",
3012                                         prim_walk, i, size >> 2,
3013                                         radeon_bo_size(track->arrays[i].robj)
3014                                         >> 2);
3015                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3016                                 return -EINVAL;
3017                         }
3018                 }
3019                 break;
3020         case 2:
3021                 for (i = 0; i < track->num_arrays; i++) {
3022                         size = track->arrays[i].esize * (nverts - 1) * 4;
3023                         if (track->arrays[i].robj == NULL) {
3024                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3025                                           "bound\n", prim_walk, i);
3026                                 return -EINVAL;
3027                         }
3028                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3029                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3030                                         "need %lu dwords have %lu dwords\n",
3031                                         prim_walk, i, size >> 2,
3032                                         radeon_bo_size(track->arrays[i].robj)
3033                                         >> 2);
3034                                 return -EINVAL;
3035                         }
3036                 }
3037                 break;
3038         case 3:
3039                 size = track->vtx_size * nverts;
3040                 if (size != track->immd_dwords) {
3041                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3042                                   track->immd_dwords, size);
3043                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3044                                   nverts, track->vtx_size);
3045                         return -EINVAL;
3046                 }
3047                 break;
3048         default:
3049                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3050                           prim_walk);
3051                 return -EINVAL;
3052         }
3053         return r100_cs_track_texture_check(rdev, track);
3054 }
3055
3056 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3057 {
3058         unsigned i, face;
3059
3060         if (rdev->family < CHIP_R300) {
3061                 track->num_cb = 1;
3062                 if (rdev->family <= CHIP_RS200)
3063                         track->num_texture = 3;
3064                 else
3065                         track->num_texture = 6;
3066                 track->maxy = 2048;
3067                 track->separate_cube = 1;
3068         } else {
3069                 track->num_cb = 4;
3070                 track->num_texture = 16;
3071                 track->maxy = 4096;
3072                 track->separate_cube = 0;
3073         }
3074
3075         for (i = 0; i < track->num_cb; i++) {
3076                 track->cb[i].robj = NULL;
3077                 track->cb[i].pitch = 8192;
3078                 track->cb[i].cpp = 16;
3079                 track->cb[i].offset = 0;
3080         }
3081         track->z_enabled = true;
3082         track->zb.robj = NULL;
3083         track->zb.pitch = 8192;
3084         track->zb.cpp = 4;
3085         track->zb.offset = 0;
3086         track->vtx_size = 0x7F;
3087         track->immd_dwords = 0xFFFFFFFFUL;
3088         track->num_arrays = 11;
3089         track->max_indx = 0x00FFFFFFUL;
3090         for (i = 0; i < track->num_arrays; i++) {
3091                 track->arrays[i].robj = NULL;
3092                 track->arrays[i].esize = 0x7F;
3093         }
3094         for (i = 0; i < track->num_texture; i++) {
3095                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3096                 track->textures[i].pitch = 16536;
3097                 track->textures[i].width = 16536;
3098                 track->textures[i].height = 16536;
3099                 track->textures[i].width_11 = 1 << 11;
3100                 track->textures[i].height_11 = 1 << 11;
3101                 track->textures[i].num_levels = 12;
3102                 if (rdev->family <= CHIP_RS200) {
3103                         track->textures[i].tex_coord_type = 0;
3104                         track->textures[i].txdepth = 0;
3105                 } else {
3106                         track->textures[i].txdepth = 16;
3107                         track->textures[i].tex_coord_type = 1;
3108                 }
3109                 track->textures[i].cpp = 64;
3110                 track->textures[i].robj = NULL;
3111                 /* CS IB emission code makes sure texture unit are disabled */
3112                 track->textures[i].enabled = false;
3113                 track->textures[i].roundup_w = true;
3114                 track->textures[i].roundup_h = true;
3115                 if (track->separate_cube)
3116                         for (face = 0; face < 5; face++) {
3117                                 track->textures[i].cube_info[face].robj = NULL;
3118                                 track->textures[i].cube_info[face].width = 16536;
3119                                 track->textures[i].cube_info[face].height = 16536;
3120                                 track->textures[i].cube_info[face].offset = 0;
3121                         }
3122         }
3123 }
3124
3125 int r100_ring_test(struct radeon_device *rdev)
3126 {
3127         uint32_t scratch;
3128         uint32_t tmp = 0;
3129         unsigned i;
3130         int r;
3131
3132         r = radeon_scratch_get(rdev, &scratch);
3133         if (r) {
3134                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3135                 return r;
3136         }
3137         WREG32(scratch, 0xCAFEDEAD);
3138         r = radeon_ring_lock(rdev, 2);
3139         if (r) {
3140                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3141                 radeon_scratch_free(rdev, scratch);
3142                 return r;
3143         }
3144         radeon_ring_write(rdev, PACKET0(scratch, 0));
3145         radeon_ring_write(rdev, 0xDEADBEEF);
3146         radeon_ring_unlock_commit(rdev);
3147         for (i = 0; i < rdev->usec_timeout; i++) {
3148                 tmp = RREG32(scratch);
3149                 if (tmp == 0xDEADBEEF) {
3150                         break;
3151                 }
3152                 DRM_UDELAY(1);
3153         }
3154         if (i < rdev->usec_timeout) {
3155                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3156         } else {
3157                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3158                           scratch, tmp);
3159                 r = -EINVAL;
3160         }
3161         radeon_scratch_free(rdev, scratch);
3162         return r;
3163 }
3164
3165 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3166 {
3167         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3168         radeon_ring_write(rdev, ib->gpu_addr);
3169         radeon_ring_write(rdev, ib->length_dw);
3170 }
3171
3172 int r100_ib_test(struct radeon_device *rdev)
3173 {
3174         struct radeon_ib *ib;
3175         uint32_t scratch;
3176         uint32_t tmp = 0;
3177         unsigned i;
3178         int r;
3179
3180         r = radeon_scratch_get(rdev, &scratch);
3181         if (r) {
3182                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3183                 return r;
3184         }
3185         WREG32(scratch, 0xCAFEDEAD);
3186         r = radeon_ib_get(rdev, &ib);
3187         if (r) {
3188                 return r;
3189         }
3190         ib->ptr[0] = PACKET0(scratch, 0);
3191         ib->ptr[1] = 0xDEADBEEF;
3192         ib->ptr[2] = PACKET2(0);
3193         ib->ptr[3] = PACKET2(0);
3194         ib->ptr[4] = PACKET2(0);
3195         ib->ptr[5] = PACKET2(0);
3196         ib->ptr[6] = PACKET2(0);
3197         ib->ptr[7] = PACKET2(0);
3198         ib->length_dw = 8;
3199         r = radeon_ib_schedule(rdev, ib);
3200         if (r) {
3201                 radeon_scratch_free(rdev, scratch);
3202                 radeon_ib_free(rdev, &ib);
3203                 return r;
3204         }
3205         r = radeon_fence_wait(ib->fence, false);
3206         if (r) {
3207                 return r;
3208         }
3209         for (i = 0; i < rdev->usec_timeout; i++) {
3210                 tmp = RREG32(scratch);
3211                 if (tmp == 0xDEADBEEF) {
3212                         break;
3213                 }
3214                 DRM_UDELAY(1);
3215         }
3216         if (i < rdev->usec_timeout) {
3217                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3218         } else {
3219                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3220                           scratch, tmp);
3221                 r = -EINVAL;
3222         }
3223         radeon_scratch_free(rdev, scratch);
3224         radeon_ib_free(rdev, &ib);
3225         return r;
3226 }
3227
3228 void r100_ib_fini(struct radeon_device *rdev)
3229 {
3230         radeon_ib_pool_fini(rdev);
3231 }
3232
3233 int r100_ib_init(struct radeon_device *rdev)
3234 {
3235         int r;
3236
3237         r = radeon_ib_pool_init(rdev);
3238         if (r) {
3239                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3240                 r100_ib_fini(rdev);
3241                 return r;
3242         }
3243         r = r100_ib_test(rdev);
3244         if (r) {
3245                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3246                 r100_ib_fini(rdev);
3247                 return r;
3248         }
3249         return 0;
3250 }
3251
3252 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3253 {
3254         /* Shutdown CP we shouldn't need to do that but better be safe than
3255          * sorry
3256          */
3257         rdev->cp.ready = false;
3258         WREG32(R_000740_CP_CSQ_CNTL, 0);
3259
3260         /* Save few CRTC registers */
3261         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3262         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3263         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3264         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3265         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3266                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3267                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3268         }
3269
3270         /* Disable VGA aperture access */
3271         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3272         /* Disable cursor, overlay, crtc */
3273         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3274         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3275                                         S_000054_CRTC_DISPLAY_DIS(1));
3276         WREG32(R_000050_CRTC_GEN_CNTL,
3277                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3278                         S_000050_CRTC_DISP_REQ_EN_B(1));
3279         WREG32(R_000420_OV0_SCALE_CNTL,
3280                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3281         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3282         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3283                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3284                                                 S_000360_CUR2_LOCK(1));
3285                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3286                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3287                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3288                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3289                 WREG32(R_000360_CUR2_OFFSET,
3290                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3291         }
3292 }
3293
3294 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3295 {
3296         /* Update base address for crtc */
3297         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3298         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3299                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3300         }
3301         /* Restore CRTC registers */
3302         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3303         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3304         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3305         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3306                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3307         }
3308 }
3309
3310 void r100_vga_render_disable(struct radeon_device *rdev)
3311 {
3312         u32 tmp;
3313
3314         tmp = RREG8(R_0003C2_GENMO_WT);
3315         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3316 }
3317
3318 static void r100_debugfs(struct radeon_device *rdev)
3319 {
3320         int r;
3321
3322         r = r100_debugfs_mc_info_init(rdev);
3323         if (r)
3324                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3325 }
3326
3327 static void r100_mc_program(struct radeon_device *rdev)
3328 {
3329         struct r100_mc_save save;
3330
3331         /* Stops all mc clients */
3332         r100_mc_stop(rdev, &save);
3333         if (rdev->flags & RADEON_IS_AGP) {
3334                 WREG32(R_00014C_MC_AGP_LOCATION,
3335                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3336                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3337                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3338                 if (rdev->family > CHIP_RV200)
3339                         WREG32(R_00015C_AGP_BASE_2,
3340                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3341         } else {
3342                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3343                 WREG32(R_000170_AGP_BASE, 0);
3344                 if (rdev->family > CHIP_RV200)
3345                         WREG32(R_00015C_AGP_BASE_2, 0);
3346         }
3347         /* Wait for mc idle */
3348         if (r100_mc_wait_for_idle(rdev))
3349                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3350         /* Program MC, should be a 32bits limited address space */
3351         WREG32(R_000148_MC_FB_LOCATION,
3352                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3353                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3354         r100_mc_resume(rdev, &save);
3355 }
3356
3357 void r100_clock_startup(struct radeon_device *rdev)
3358 {
3359         u32 tmp;
3360
3361         if (radeon_dynclks != -1 && radeon_dynclks)
3362                 radeon_legacy_set_clock_gating(rdev, 1);
3363         /* We need to force on some of the block */
3364         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3365         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3366         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3367                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3368         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3369 }
3370
3371 static int r100_startup(struct radeon_device *rdev)
3372 {
3373         int r;
3374
3375         /* set common regs */
3376         r100_set_common_regs(rdev);
3377         /* program mc */
3378         r100_mc_program(rdev);
3379         /* Resume clock */
3380         r100_clock_startup(rdev);
3381         /* Initialize GPU configuration (# pipes, ...) */
3382         r100_gpu_init(rdev);
3383         /* Initialize GART (initialize after TTM so we can allocate
3384          * memory through TTM but finalize after TTM) */
3385         r100_enable_bm(rdev);
3386         if (rdev->flags & RADEON_IS_PCI) {
3387                 r = r100_pci_gart_enable(rdev);
3388                 if (r)
3389                         return r;
3390         }
3391         /* Enable IRQ */
3392         r100_irq_set(rdev);
3393         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3394         /* 1M ring buffer */
3395         r = r100_cp_init(rdev, 1024 * 1024);
3396         if (r) {
3397                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3398                 return r;
3399         }
3400         r = r100_wb_init(rdev);
3401         if (r)
3402                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3403         r = r100_ib_init(rdev);
3404         if (r) {
3405                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3406                 return r;
3407         }
3408         return 0;
3409 }
3410
3411 int r100_resume(struct radeon_device *rdev)
3412 {
3413         /* Make sur GART are not working */
3414         if (rdev->flags & RADEON_IS_PCI)
3415                 r100_pci_gart_disable(rdev);
3416         /* Resume clock before doing reset */
3417         r100_clock_startup(rdev);
3418         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3419         if (radeon_gpu_reset(rdev)) {
3420                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3421                         RREG32(R_000E40_RBBM_STATUS),
3422                         RREG32(R_0007C0_CP_STAT));
3423         }
3424         /* post */
3425         radeon_combios_asic_init(rdev->ddev);
3426         /* Resume clock after posting */
3427         r100_clock_startup(rdev);
3428         /* Initialize surface registers */
3429         radeon_surface_init(rdev);
3430         return r100_startup(rdev);
3431 }
3432
3433 int r100_suspend(struct radeon_device *rdev)
3434 {
3435         r100_cp_disable(rdev);
3436         r100_wb_disable(rdev);
3437         r100_irq_disable(rdev);
3438         if (rdev->flags & RADEON_IS_PCI)
3439                 r100_pci_gart_disable(rdev);
3440         return 0;
3441 }
3442
3443 void r100_fini(struct radeon_device *rdev)
3444 {
3445         r100_cp_fini(rdev);
3446         r100_wb_fini(rdev);
3447         r100_ib_fini(rdev);
3448         radeon_gem_fini(rdev);
3449         if (rdev->flags & RADEON_IS_PCI)
3450                 r100_pci_gart_fini(rdev);
3451         radeon_agp_fini(rdev);
3452         radeon_irq_kms_fini(rdev);
3453         radeon_fence_driver_fini(rdev);
3454         radeon_bo_fini(rdev);
3455         radeon_atombios_fini(rdev);
3456         kfree(rdev->bios);
3457         rdev->bios = NULL;
3458 }
3459
3460 int r100_init(struct radeon_device *rdev)
3461 {
3462         int r;
3463
3464         /* Register debugfs file specific to this group of asics */
3465         r100_debugfs(rdev);
3466         /* Disable VGA */
3467         r100_vga_render_disable(rdev);
3468         /* Initialize scratch registers */
3469         radeon_scratch_init(rdev);
3470         /* Initialize surface registers */
3471         radeon_surface_init(rdev);
3472         /* TODO: disable VGA need to use VGA request */
3473         /* BIOS*/
3474         if (!radeon_get_bios(rdev)) {
3475                 if (ASIC_IS_AVIVO(rdev))
3476                         return -EINVAL;
3477         }
3478         if (rdev->is_atom_bios) {
3479                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3480                 return -EINVAL;
3481         } else {
3482                 r = radeon_combios_init(rdev);
3483                 if (r)
3484                         return r;
3485         }
3486         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3487         if (radeon_gpu_reset(rdev)) {
3488                 dev_warn(rdev->dev,
3489                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3490                         RREG32(R_000E40_RBBM_STATUS),
3491                         RREG32(R_0007C0_CP_STAT));
3492         }
3493         /* check if cards are posted or not */
3494         if (radeon_boot_test_post_card(rdev) == false)
3495                 return -EINVAL;
3496         /* Set asic errata */
3497         r100_errata(rdev);
3498         /* Initialize clocks */
3499         radeon_get_clock_info(rdev->ddev);
3500         /* Initialize power management */
3501         radeon_pm_init(rdev);
3502         /* initialize AGP */
3503         if (rdev->flags & RADEON_IS_AGP) {
3504                 r = radeon_agp_init(rdev);
3505                 if (r) {
3506                         radeon_agp_disable(rdev);
3507                 }
3508         }
3509         /* initialize VRAM */
3510         r100_mc_init(rdev);
3511         /* Fence driver */
3512         r = radeon_fence_driver_init(rdev);
3513         if (r)
3514                 return r;
3515         r = radeon_irq_kms_init(rdev);
3516         if (r)
3517                 return r;
3518         /* Memory manager */
3519         r = radeon_bo_init(rdev);
3520         if (r)
3521                 return r;
3522         if (rdev->flags & RADEON_IS_PCI) {
3523                 r = r100_pci_gart_init(rdev);
3524                 if (r)
3525                         return r;
3526         }
3527         r100_set_safe_registers(rdev);
3528         rdev->accel_working = true;
3529         r = r100_startup(rdev);
3530         if (r) {
3531                 /* Somethings want wront with the accel init stop accel */
3532                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3533                 r100_cp_fini(rdev);
3534                 r100_wb_fini(rdev);
3535                 r100_ib_fini(rdev);
3536                 radeon_irq_kms_fini(rdev);
3537                 if (rdev->flags & RADEON_IS_PCI)
3538                         r100_pci_gart_fini(rdev);
3539                 rdev->accel_working = false;
3540         }
3541         return 0;
3542 }