drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.usOverscanRight = 0;
  48         args.usOverscanLeft = 0;
  49         args.usOverscanBottom = 0;
  50         args.usOverscanTop = 0;
  51         args.ucCRTC = radeon_crtc->crtc_id;
  52
  53         switch (radeon_crtc->rmx_type) {
  54         case RMX_CENTER:
  55                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  56                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  57                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  58                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  59                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  60                 break;
  61         case RMX_ASPECT:
  62                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  63                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  64
  65                 if (a1 > a2) {
  66                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  67                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  68                 } else if (a2 > a1) {
  69                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  70                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  71                 }
  72                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  73                 break;
  74         case RMX_FULL:
  75         default:
  76                 args.usOverscanRight = 0;
  77                 args.usOverscanLeft = 0;
  78                 args.usOverscanBottom = 0;
  79                 args.usOverscanTop = 0;
  80                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  81                 break;
  82         }
  83 }
  84
  85 static void atombios_scaler_setup(struct drm_crtc *crtc)
  86 {
  87         struct drm_device *dev = crtc->dev;
  88         struct radeon_device *rdev = dev->dev_private;
  89         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  90         ENABLE_SCALER_PS_ALLOCATION args;
  91         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  92
  93         /* fixme - fill in enc_priv for atom dac */
  94         enum radeon_tv_std tv_std = TV_STD_NTSC;
  95         bool is_tv = false, is_cv = false;
  96         struct drm_encoder *encoder;
  97
  98         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  99                 return;
 100
 101         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 102                 /* find tv std */
 103                 if (encoder->crtc == crtc) {
 104                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 105                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 106                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 107                                 tv_std = tv_dac->tv_std;
 108                                 is_tv = true;
 109                         }
 110                 }
 111         }
 112
 113         memset(&args, 0, sizeof(args));
 114
 115         args.ucScaler = radeon_crtc->crtc_id;
 116
 117         if (is_tv) {
 118                 switch (tv_std) {
 119                 case TV_STD_NTSC:
 120                 default:
 121                         args.ucTVStandard = ATOM_TV_NTSC;
 122                         break;
 123                 case TV_STD_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL;
 125                         break;
 126                 case TV_STD_PAL_M:
 127                         args.ucTVStandard = ATOM_TV_PALM;
 128                         break;
 129                 case TV_STD_PAL_60:
 130                         args.ucTVStandard = ATOM_TV_PAL60;
 131                         break;
 132                 case TV_STD_NTSC_J:
 133                         args.ucTVStandard = ATOM_TV_NTSCJ;
 134                         break;
 135                 case TV_STD_SCART_PAL:
 136                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 137                         break;
 138                 case TV_STD_SECAM:
 139                         args.ucTVStandard = ATOM_TV_SECAM;
 140                         break;
 141                 case TV_STD_PAL_CN:
 142                         args.ucTVStandard = ATOM_TV_PALCN;
 143                         break;
 144                 }
 145                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 146         } else if (is_cv) {
 147                 args.ucTVStandard = ATOM_TV_CV;
 148                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 149         } else {
 150                 switch (radeon_crtc->rmx_type) {
 151                 case RMX_FULL:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 case RMX_CENTER:
 155                         args.ucEnable = ATOM_SCALER_CENTER;
 156                         break;
 157                 case RMX_ASPECT:
 158                         args.ucEnable = ATOM_SCALER_EXPANSION;
 159                         break;
 160                 default:
 161                         if (ASIC_IS_AVIVO(rdev))
 162                                 args.ucEnable = ATOM_SCALER_DISABLE;
 163                         else
 164                                 args.ucEnable = ATOM_SCALER_CENTER;
 165                         break;
 166                 }
 167         }
 168         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 169         if ((is_tv || is_cv)
 170             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 171                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 172         }
 173 }
 174
 175 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 176 {
 177         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 178         struct drm_device *dev = crtc->dev;
 179         struct radeon_device *rdev = dev->dev_private;
 180         int index =
 181             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 182         ENABLE_CRTC_PS_ALLOCATION args;
 183
 184         memset(&args, 0, sizeof(args));
 185
 186         args.ucCRTC = radeon_crtc->crtc_id;
 187         args.ucEnable = lock;
 188
 189         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 190 }
 191
 192 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 193 {
 194         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 195         struct drm_device *dev = crtc->dev;
 196         struct radeon_device *rdev = dev->dev_private;
 197         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 198         ENABLE_CRTC_PS_ALLOCATION args;
 199
 200         memset(&args, 0, sizeof(args));
 201
 202         args.ucCRTC = radeon_crtc->crtc_id;
 203         args.ucEnable = state;
 204
 205         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 206 }
 207
 208 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 209 {
 210         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 211         struct drm_device *dev = crtc->dev;
 212         struct radeon_device *rdev = dev->dev_private;
 213         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 214         ENABLE_CRTC_PS_ALLOCATION args;
 215
 216         memset(&args, 0, sizeof(args));
 217
 218         args.ucCRTC = radeon_crtc->crtc_id;
 219         args.ucEnable = state;
 220
 221         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 222 }
 223
 224 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 225 {
 226         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 227         struct drm_device *dev = crtc->dev;
 228         struct radeon_device *rdev = dev->dev_private;
 229         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 230         BLANK_CRTC_PS_ALLOCATION args;
 231
 232         memset(&args, 0, sizeof(args));
 233
 234         args.ucCRTC = radeon_crtc->crtc_id;
 235         args.ucBlanking = state;
 236
 237         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 238 }
 239
 240 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 241 {
 242         struct drm_device *dev = crtc->dev;
 243         struct radeon_device *rdev = dev->dev_private;
 244         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 245
 246         switch (mode) {
 247         case DRM_MODE_DPMS_ON:
 248                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 249                 if (ASIC_IS_DCE3(rdev))
 250                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 251                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 252                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 253                 radeon_crtc_load_lut(crtc);
 254                 radeon_crtc->enabled = true;
 255                 break;
 256         case DRM_MODE_DPMS_STANDBY:
 257         case DRM_MODE_DPMS_SUSPEND:
 258         case DRM_MODE_DPMS_OFF:
 259                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 260                 atombios_blank_crtc(crtc, ATOM_ENABLE);
 261                 if (ASIC_IS_DCE3(rdev))
 262                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 263                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 264                 radeon_crtc->enabled = false;
 265                 break;
 266         }
 267
 268         /* adjust pm to dpms change */
 269         radeon_pm_compute_clocks(rdev);
 270 }
 271
 272 static void
 273 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 274                              struct drm_display_mode *mode)
 275 {
 276         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 277         struct drm_device *dev = crtc->dev;
 278         struct radeon_device *rdev = dev->dev_private;
 279         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 280         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 281         u16 misc = 0;
 282
 283         memset(&args, 0, sizeof(args));
 284         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
 285         args.usH_Blanking_Time =
 286                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
 287         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
 288         args.usV_Blanking_Time =
 289             cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
 290         args.usH_SyncOffset =
 291                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
 292         args.usH_SyncWidth =
 293                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 294         args.usV_SyncOffset =
 295                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
 296         args.usV_SyncWidth =
 297                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 298         /*args.ucH_Border = mode->hborder;*/
 299         /*args.ucV_Border = mode->vborder;*/
 300
 301         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 302                 misc |= ATOM_VSYNC_POLARITY;
 303         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 304                 misc |= ATOM_HSYNC_POLARITY;
 305         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 306                 misc |= ATOM_COMPOSITESYNC;
 307         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 308                 misc |= ATOM_INTERLACE;
 309         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 310                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 311
 312         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 313         args.ucCRTC = radeon_crtc->crtc_id;
 314
 315         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 316 }
 317
 318 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 319                                      struct drm_display_mode *mode)
 320 {
 321         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 322         struct drm_device *dev = crtc->dev;
 323         struct radeon_device *rdev = dev->dev_private;
 324         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 325         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 326         u16 misc = 0;
 327
 328         memset(&args, 0, sizeof(args));
 329         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 330         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 331         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 332         args.usH_SyncWidth =
 333                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 334         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 335         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 336         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 337         args.usV_SyncWidth =
 338                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 339
 340         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 341                 misc |= ATOM_VSYNC_POLARITY;
 342         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 343                 misc |= ATOM_HSYNC_POLARITY;
 344         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 345                 misc |= ATOM_COMPOSITESYNC;
 346         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 347                 misc |= ATOM_INTERLACE;
 348         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 349                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 350
 351         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 352         args.ucCRTC = radeon_crtc->crtc_id;
 353
 354         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 355 }
 356
 357 static void atombios_disable_ss(struct drm_crtc *crtc)
 358 {
 359         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 360         struct drm_device *dev = crtc->dev;
 361         struct radeon_device *rdev = dev->dev_private;
 362         u32 ss_cntl;
 363
 364         if (ASIC_IS_DCE4(rdev)) {
 365                 switch (radeon_crtc->pll_id) {
 366                 case ATOM_PPLL1:
 367                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 368                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 369                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 370                         break;
 371                 case ATOM_PPLL2:
 372                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 373                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 374                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 375                         break;
 376                 case ATOM_DCPLL:
 377                 case ATOM_PPLL_INVALID:
 378                         return;
 379                 }
 380         } else if (ASIC_IS_AVIVO(rdev)) {
 381                 switch (radeon_crtc->pll_id) {
 382                 case ATOM_PPLL1:
 383                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 384                         ss_cntl &= ~1;
 385                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 386                         break;
 387                 case ATOM_PPLL2:
 388                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 389                         ss_cntl &= ~1;
 390                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 391                         break;
 392                 case ATOM_DCPLL:
 393                 case ATOM_PPLL_INVALID:
 394                         return;
 395                 }
 396         }
 397 }
 398
 399
 400 union atom_enable_ss {
 401         ENABLE_LVDS_SS_PARAMETERS legacy;
 402         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 403 };
 404
 405 static void atombios_enable_ss(struct drm_crtc *crtc)
 406 {
 407         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 408         struct drm_device *dev = crtc->dev;
 409         struct radeon_device *rdev = dev->dev_private;
 410         struct drm_encoder *encoder = NULL;
 411         struct radeon_encoder *radeon_encoder = NULL;
 412         struct radeon_encoder_atom_dig *dig = NULL;
 413         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 414         union atom_enable_ss args;
 415         uint16_t percentage = 0;
 416         uint8_t type = 0, step = 0, delay = 0, range = 0;
 417
 418         /* XXX add ss support for DCE4 */
 419         if (ASIC_IS_DCE4(rdev))
 420                 return;
 421
 422         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 423                 if (encoder->crtc == crtc) {
 424                         radeon_encoder = to_radeon_encoder(encoder);
 425                         /* only enable spread spectrum on LVDS */
 426                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 427                                 dig = radeon_encoder->enc_priv;
 428                                 if (dig && dig->ss) {
 429                                         percentage = dig->ss->percentage;
 430                                         type = dig->ss->type;
 431                                         step = dig->ss->step;
 432                                         delay = dig->ss->delay;
 433                                         range = dig->ss->range;
 434                                 } else
 435                                         return;
 436                         } else
 437                                 return;
 438                         break;
 439                 }
 440         }
 441
 442         if (!radeon_encoder)
 443                 return;
 444
 445         memset(&args, 0, sizeof(args));
 446         if (ASIC_IS_AVIVO(rdev)) {
 447                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 448                 args.v1.ucSpreadSpectrumType = type;
 449                 args.v1.ucSpreadSpectrumStep = step;
 450                 args.v1.ucSpreadSpectrumDelay = delay;
 451                 args.v1.ucSpreadSpectrumRange = range;
 452                 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 453                 args.v1.ucEnable = ATOM_ENABLE;
 454         } else {
 455                 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 456                 args.legacy.ucSpreadSpectrumType = type;
 457                 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
 458                 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
 459                 args.legacy.ucEnable = ATOM_ENABLE;
 460         }
 461         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 462 }
 463
 464 union adjust_pixel_clock {
 465         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 466         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 467 };
 468
 469 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 470                                struct drm_display_mode *mode,
 471                                struct radeon_pll *pll)
 472 {
 473         struct drm_device *dev = crtc->dev;
 474         struct radeon_device *rdev = dev->dev_private;
 475         struct drm_encoder *encoder = NULL;
 476         struct radeon_encoder *radeon_encoder = NULL;
 477         u32 adjusted_clock = mode->clock;
 478         int encoder_mode = 0;
 479
 480         /* reset the pll flags */
 481         pll->flags = 0;
 482
 483         /* select the PLL algo */
 484         if (ASIC_IS_AVIVO(rdev)) {
 485                 if (radeon_new_pll == 0)
 486                         pll->algo = PLL_ALGO_LEGACY;
 487                 else
 488                         pll->algo = PLL_ALGO_NEW;
 489         } else {
 490                 if (radeon_new_pll == 1)
 491                         pll->algo = PLL_ALGO_NEW;
 492                 else
 493                         pll->algo = PLL_ALGO_LEGACY;
 494         }
 495
 496         if (ASIC_IS_AVIVO(rdev)) {
 497                 if ((rdev->family == CHIP_RS600) ||
 498                     (rdev->family == CHIP_RS690) ||
 499                     (rdev->family == CHIP_RS740))
 500                         pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
 501                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 502
 503                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 504                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 505                 else
 506                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 507         } else {
 508                 pll->flags |= RADEON_PLL_LEGACY;
 509
 510                 if (mode->clock > 200000)       /* range limits??? */
 511                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 512                 else
 513                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 514
 515         }
 516
 517         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 518                 if (encoder->crtc == crtc) {
 519                         radeon_encoder = to_radeon_encoder(encoder);
 520                         encoder_mode = atombios_get_encoder_mode(encoder);
 521                         if (ASIC_IS_AVIVO(rdev)) {
 522                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 523                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 524                                         adjusted_clock = mode->clock * 2;
 525                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 526                                         pll->algo = PLL_ALGO_LEGACY;
 527                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 528                                 }
 529                         } else {
 530                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 531                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 532                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 533                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 534                         }
 535                         break;
 536                 }
 537         }
 538
 539         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 540          * accordingly based on the encoder/transmitter to work around
 541          * special hw requirements.
 542          */
 543         if (ASIC_IS_DCE3(rdev)) {
 544                 union adjust_pixel_clock args;
 545                 u8 frev, crev;
 546                 int index;
 547
 548                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 549                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 550                                            &crev))
 551                         return adjusted_clock;
 552
 553                 memset(&args, 0, sizeof(args));
 554
 555                 switch (frev) {
 556                 case 1:
 557                         switch (crev) {
 558                         case 1:
 559                         case 2:
 560                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 561                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 562                                 args.v1.ucEncodeMode = encoder_mode;
 563
 564                                 atom_execute_table(rdev->mode_info.atom_context,
 565                                                    index, (uint32_t *)&args);
 566                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 567                                 break;
 568                         case 3:
 569                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 570                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 571                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 572                                 args.v3.sInput.ucDispPllConfig = 0;
 573                                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 574                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 575
 576                                         if (encoder_mode == ATOM_ENCODER_MODE_DP)
 577                                                 args.v3.sInput.ucDispPllConfig |=
 578                                                         DISPPLL_CONFIG_COHERENT_MODE;
 579                                         else {
 580                                                 if (dig->coherent_mode)
 581                                                         args.v3.sInput.ucDispPllConfig |=
 582                                                                 DISPPLL_CONFIG_COHERENT_MODE;
 583                                                 if (mode->clock > 165000)
 584                                                         args.v3.sInput.ucDispPllConfig |=
 585                                                                 DISPPLL_CONFIG_DUAL_LINK;
 586                                         }
 587                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 588                                         /* may want to enable SS on DP/eDP eventually */
 589                                         /*args.v3.sInput.ucDispPllConfig |=
 590                                                 DISPPLL_CONFIG_SS_ENABLE;*/
 591                                         if (encoder_mode == ATOM_ENCODER_MODE_DP)
 592                                                 args.v3.sInput.ucDispPllConfig |=
 593                                                         DISPPLL_CONFIG_COHERENT_MODE;
 594                                         else {
 595                                                 if (mode->clock > 165000)
 596                                                         args.v3.sInput.ucDispPllConfig |=
 597                                                                 DISPPLL_CONFIG_DUAL_LINK;
 598                                         }
 599                                 }
 600                                 atom_execute_table(rdev->mode_info.atom_context,
 601                                                    index, (uint32_t *)&args);
 602                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 603                                 if (args.v3.sOutput.ucRefDiv) {
 604                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 605                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 606                                 }
 607                                 if (args.v3.sOutput.ucPostDiv) {
 608                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 609                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 610                                 }
 611                                 break;
 612                         default:
 613                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 614                                 return adjusted_clock;
 615                         }
 616                         break;
 617                 default:
 618                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 619                         return adjusted_clock;
 620                 }
 621         }
 622         return adjusted_clock;
 623 }
 624
 625 union set_pixel_clock {
 626         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 627         PIXEL_CLOCK_PARAMETERS v1;
 628         PIXEL_CLOCK_PARAMETERS_V2 v2;
 629         PIXEL_CLOCK_PARAMETERS_V3 v3;
 630         PIXEL_CLOCK_PARAMETERS_V5 v5;
 631 };
 632
 633 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
 634 {
 635         struct drm_device *dev = crtc->dev;
 636         struct radeon_device *rdev = dev->dev_private;
 637         u8 frev, crev;
 638         int index;
 639         union set_pixel_clock args;
 640
 641         memset(&args, 0, sizeof(args));
 642
 643         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 644         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 645                                    &crev))
 646                 return;
 647
 648         switch (frev) {
 649         case 1:
 650                 switch (crev) {
 651                 case 5:
 652                         /* if the default dcpll clock is specified,
 653                          * SetPixelClock provides the dividers
 654                          */
 655                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 656                         args.v5.usPixelClock = rdev->clock.default_dispclk;
 657                         args.v5.ucPpll = ATOM_DCPLL;
 658                         break;
 659                 default:
 660                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 661                         return;
 662                 }
 663                 break;
 664         default:
 665                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 666                 return;
 667         }
 668         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 669 }
 670
 671 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 672 {
 673         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 674         struct drm_device *dev = crtc->dev;
 675         struct radeon_device *rdev = dev->dev_private;
 676         struct drm_encoder *encoder = NULL;
 677         struct radeon_encoder *radeon_encoder = NULL;
 678         u8 frev, crev;
 679         int index;
 680         union set_pixel_clock args;
 681         u32 pll_clock = mode->clock;
 682         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 683         struct radeon_pll *pll;
 684         u32 adjusted_clock;
 685         int encoder_mode = 0;
 686
 687         memset(&args, 0, sizeof(args));
 688
 689         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 690                 if (encoder->crtc == crtc) {
 691                         radeon_encoder = to_radeon_encoder(encoder);
 692                         encoder_mode = atombios_get_encoder_mode(encoder);
 693                         break;
 694                 }
 695         }
 696
 697         if (!radeon_encoder)
 698                 return;
 699
 700         switch (radeon_crtc->pll_id) {
 701         case ATOM_PPLL1:
 702                 pll = &rdev->clock.p1pll;
 703                 break;
 704         case ATOM_PPLL2:
 705                 pll = &rdev->clock.p2pll;
 706                 break;
 707         case ATOM_DCPLL:
 708         case ATOM_PPLL_INVALID:
 709                 pll = &rdev->clock.dcpll;
 710                 break;
 711         }
 712
 713         /* adjust pixel clock as needed */
 714         adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
 715
 716         radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
 717                            &ref_div, &post_div);
 718
 719         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 720         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 721                                    &crev))
 722                 return;
 723
 724         switch (frev) {
 725         case 1:
 726                 switch (crev) {
 727                 case 1:
 728                         args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 729                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 730                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 731                         args.v1.ucFracFbDiv = frac_fb_div;
 732                         args.v1.ucPostDiv = post_div;
 733                         args.v1.ucPpll = radeon_crtc->pll_id;
 734                         args.v1.ucCRTC = radeon_crtc->crtc_id;
 735                         args.v1.ucRefDivSrc = 1;
 736                         break;
 737                 case 2:
 738                         args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
 739                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 740                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 741                         args.v2.ucFracFbDiv = frac_fb_div;
 742                         args.v2.ucPostDiv = post_div;
 743                         args.v2.ucPpll = radeon_crtc->pll_id;
 744                         args.v2.ucCRTC = radeon_crtc->crtc_id;
 745                         args.v2.ucRefDivSrc = 1;
 746                         break;
 747                 case 3:
 748                         args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
 749                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 750                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 751                         args.v3.ucFracFbDiv = frac_fb_div;
 752                         args.v3.ucPostDiv = post_div;
 753                         args.v3.ucPpll = radeon_crtc->pll_id;
 754                         args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
 755                         args.v3.ucTransmitterId = radeon_encoder->encoder_id;
 756                         args.v3.ucEncoderMode = encoder_mode;
 757                         break;
 758                 case 5:
 759                         args.v5.ucCRTC = radeon_crtc->crtc_id;
 760                         args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
 761                         args.v5.ucRefDiv = ref_div;
 762                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 763                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 764                         args.v5.ucPostDiv = post_div;
 765                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 766                         args.v5.ucTransmitterID = radeon_encoder->encoder_id;
 767                         args.v5.ucEncoderMode = encoder_mode;
 768                         args.v5.ucPpll = radeon_crtc->pll_id;
 769                         break;
 770                 default:
 771                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 772                         return;
 773                 }
 774                 break;
 775         default:
 776                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 777                 return;
 778         }
 779
 780         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 781 }
 782
 783 static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 784                                    struct drm_framebuffer *old_fb)
 785 {
 786         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 787         struct drm_device *dev = crtc->dev;
 788         struct radeon_device *rdev = dev->dev_private;
 789         struct radeon_framebuffer *radeon_fb;
 790         struct drm_gem_object *obj;
 791         struct radeon_bo *rbo;
 792         uint64_t fb_location;
 793         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 794         int r;
 795
 796         /* no fb bound */
 797         if (!crtc->fb) {
 798                 DRM_DEBUG("No FB bound\n");
 799                 return 0;
 800         }
 801
 802         radeon_fb = to_radeon_framebuffer(crtc->fb);
 803
 804         /* Pin framebuffer & get tilling informations */
 805         obj = radeon_fb->obj;
 806         rbo = obj->driver_private;
 807         r = radeon_bo_reserve(rbo, false);
 808         if (unlikely(r != 0))
 809                 return r;
 810         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 811         if (unlikely(r != 0)) {
 812                 radeon_bo_unreserve(rbo);
 813                 return -EINVAL;
 814         }
 815         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 816         radeon_bo_unreserve(rbo);
 817
 818         switch (crtc->fb->bits_per_pixel) {
 819         case 8:
 820                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
 821                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
 822                 break;
 823         case 15:
 824                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 825                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
 826                 break;
 827         case 16:
 828                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
 829                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
 830                 break;
 831         case 24:
 832         case 32:
 833                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
 834                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
 835                 break;
 836         default:
 837                 DRM_ERROR("Unsupported screen depth %d\n",
 838                           crtc->fb->bits_per_pixel);
 839                 return -EINVAL;
 840         }
 841
 842         switch (radeon_crtc->crtc_id) {
 843         case 0:
 844                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 845                 break;
 846         case 1:
 847                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 848                 break;
 849         case 2:
 850                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
 851                 break;
 852         case 3:
 853                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
 854                 break;
 855         case 4:
 856                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
 857                 break;
 858         case 5:
 859                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
 860                 break;
 861         default:
 862                 break;
 863         }
 864
 865         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 866                upper_32_bits(fb_location));
 867         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 868                upper_32_bits(fb_location));
 869         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 870                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 871         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 872                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
 873         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 874
 875         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 876         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 877         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
 878         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
 879         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
 880         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
 881
 882         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 883         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 884         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 885
 886         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 887                crtc->mode.vdisplay);
 888         x &= ~3;
 889         y &= ~1;
 890         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
 891                (x << 16) | y);
 892         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 893                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 894
 895         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
 896                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
 897                        EVERGREEN_INTERLEAVE_EN);
 898         else
 899                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
 900
 901         if (old_fb && old_fb != crtc->fb) {
 902                 radeon_fb = to_radeon_framebuffer(old_fb);
 903                 rbo = radeon_fb->obj->driver_private;
 904                 r = radeon_bo_reserve(rbo, false);
 905                 if (unlikely(r != 0))
 906                         return r;
 907                 radeon_bo_unpin(rbo);
 908                 radeon_bo_unreserve(rbo);
 909         }
 910
 911         /* Bytes per pixel may have changed */
 912         radeon_bandwidth_update(rdev);
 913
 914         return 0;
 915 }
 916
 917 static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 918                                struct drm_framebuffer *old_fb)
 919 {
 920         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 921         struct drm_device *dev = crtc->dev;
 922         struct radeon_device *rdev = dev->dev_private;
 923         struct radeon_framebuffer *radeon_fb;
 924         struct drm_gem_object *obj;
 925         struct radeon_bo *rbo;
 926         uint64_t fb_location;
 927         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 928         int r;
 929
 930         /* no fb bound */
 931         if (!crtc->fb) {
 932                 DRM_DEBUG("No FB bound\n");
 933                 return 0;
 934         }
 935
 936         radeon_fb = to_radeon_framebuffer(crtc->fb);
 937
 938         /* Pin framebuffer & get tilling informations */
 939         obj = radeon_fb->obj;
 940         rbo = obj->driver_private;
 941         r = radeon_bo_reserve(rbo, false);
 942         if (unlikely(r != 0))
 943                 return r;
 944         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
 945         if (unlikely(r != 0)) {
 946                 radeon_bo_unreserve(rbo);
 947                 return -EINVAL;
 948         }
 949         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 950         radeon_bo_unreserve(rbo);
 951
 952         switch (crtc->fb->bits_per_pixel) {
 953         case 8:
 954                 fb_format =
 955                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
 956                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
 957                 break;
 958         case 15:
 959                 fb_format =
 960                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 961                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 962                 break;
 963         case 16:
 964                 fb_format =
 965                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
 966                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 967                 break;
 968         case 24:
 969         case 32:
 970                 fb_format =
 971                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
 972                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 973                 break;
 974         default:
 975                 DRM_ERROR("Unsupported screen depth %d\n",
 976                           crtc->fb->bits_per_pixel);
 977                 return -EINVAL;
 978         }
 979
 980         if (tiling_flags & RADEON_TILING_MACRO)
 981                 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 982
 983         if (tiling_flags & RADEON_TILING_MICRO)
 984                 fb_format |= AVIVO_D1GRPH_TILED;
 985
 986         if (radeon_crtc->crtc_id == 0)
 987                 WREG32(AVIVO_D1VGA_CONTROL, 0);
 988         else
 989                 WREG32(AVIVO_D2VGA_CONTROL, 0);
 990
 991         if (rdev->family >= CHIP_RV770) {
 992                 if (radeon_crtc->crtc_id) {
 993                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 994                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
 995                 } else {
 996                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
 997                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
 998                 }
 999         }
1000         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1001                (u32) fb_location);
1002         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1003                radeon_crtc->crtc_offset, (u32) fb_location);
1004         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1005
1006         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1007         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1008         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1009         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1010         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1011         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1012
1013         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1014         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1015         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1016
1017         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1018                crtc->mode.vdisplay);
1019         x &= ~3;
1020         y &= ~1;
1021         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1022                (x << 16) | y);
1023         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1024                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1025
1026         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1027                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1028                        AVIVO_D1MODE_INTERLEAVE_EN);
1029         else
1030                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1031
1032         if (old_fb && old_fb != crtc->fb) {
1033                 radeon_fb = to_radeon_framebuffer(old_fb);
1034                 rbo = radeon_fb->obj->driver_private;
1035                 r = radeon_bo_reserve(rbo, false);
1036                 if (unlikely(r != 0))
1037                         return r;
1038                 radeon_bo_unpin(rbo);
1039                 radeon_bo_unreserve(rbo);
1040         }
1041
1042         /* Bytes per pixel may have changed */
1043         radeon_bandwidth_update(rdev);
1044
1045         return 0;
1046 }
1047
1048 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1049                            struct drm_framebuffer *old_fb)
1050 {
1051         struct drm_device *dev = crtc->dev;
1052         struct radeon_device *rdev = dev->dev_private;
1053
1054         if (ASIC_IS_DCE4(rdev))
1055                 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1056         else if (ASIC_IS_AVIVO(rdev))
1057                 return avivo_crtc_set_base(crtc, x, y, old_fb);
1058         else
1059                 return radeon_crtc_set_base(crtc, x, y, old_fb);
1060 }
1061
1062 /* properly set additional regs when using atombios */
1063 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1064 {
1065         struct drm_device *dev = crtc->dev;
1066         struct radeon_device *rdev = dev->dev_private;
1067         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1068         u32 disp_merge_cntl;
1069
1070         switch (radeon_crtc->crtc_id) {
1071         case 0:
1072                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1073                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1074                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1075                 break;
1076         case 1:
1077                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1078                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1079                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1080                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1081                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1082                 break;
1083         }
1084 }
1085
1086 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1087 {
1088         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1089         struct drm_device *dev = crtc->dev;
1090         struct radeon_device *rdev = dev->dev_private;
1091         struct drm_encoder *test_encoder;
1092         struct drm_crtc *test_crtc;
1093         uint32_t pll_in_use = 0;
1094
1095         if (ASIC_IS_DCE4(rdev)) {
1096                 /* if crtc is driving DP and we have an ext clock, use that */
1097                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1098                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1099                                 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1100                                         if (rdev->clock.dp_extclk)
1101                                                 return ATOM_PPLL_INVALID;
1102                                 }
1103                         }
1104                 }
1105
1106                 /* otherwise, pick one of the plls */
1107                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1108                         struct radeon_crtc *radeon_test_crtc;
1109
1110                         if (crtc == test_crtc)
1111                                 continue;
1112
1113                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1114                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1115                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1116                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1117                 }
1118                 if (!(pll_in_use & 1))
1119                         return ATOM_PPLL1;
1120                 return ATOM_PPLL2;
1121         } else
1122                 return radeon_crtc->crtc_id;
1123
1124 }
1125
1126 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1127                            struct drm_display_mode *mode,
1128                            struct drm_display_mode *adjusted_mode,
1129                            int x, int y, struct drm_framebuffer *old_fb)
1130 {
1131         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1132         struct drm_device *dev = crtc->dev;
1133         struct radeon_device *rdev = dev->dev_private;
1134
1135         /* TODO color tiling */
1136
1137         atombios_disable_ss(crtc);
1138         /* always set DCPLL */
1139         if (ASIC_IS_DCE4(rdev))
1140                 atombios_crtc_set_dcpll(crtc);
1141         atombios_crtc_set_pll(crtc, adjusted_mode);
1142         atombios_enable_ss(crtc);
1143
1144         if (ASIC_IS_DCE4(rdev))
1145                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1146         else if (ASIC_IS_AVIVO(rdev))
1147                 atombios_crtc_set_timing(crtc, adjusted_mode);
1148         else {
1149                 atombios_crtc_set_timing(crtc, adjusted_mode);
1150                 if (radeon_crtc->crtc_id == 0)
1151                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1152                 radeon_legacy_atom_fixup(crtc);
1153         }
1154         atombios_crtc_set_base(crtc, x, y, old_fb);
1155         atombios_overscan_setup(crtc, mode, adjusted_mode);
1156         atombios_scaler_setup(crtc);
1157         return 0;
1158 }
1159
1160 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1161                                      struct drm_display_mode *mode,
1162                                      struct drm_display_mode *adjusted_mode)
1163 {
1164         struct drm_device *dev = crtc->dev;
1165         struct radeon_device *rdev = dev->dev_private;
1166
1167         /* adjust pm to upcoming mode change */
1168         radeon_pm_compute_clocks(rdev);
1169
1170         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1171                 return false;
1172         return true;
1173 }
1174
1175 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1176 {
1177         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1178
1179         /* pick pll */
1180         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1181
1182         atombios_lock_crtc(crtc, ATOM_ENABLE);
1183         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1184 }
1185
1186 static void atombios_crtc_commit(struct drm_crtc *crtc)
1187 {
1188         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1189         atombios_lock_crtc(crtc, ATOM_DISABLE);
1190 }
1191
1192 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1193         .dpms = atombios_crtc_dpms,
1194         .mode_fixup = atombios_crtc_mode_fixup,
1195         .mode_set = atombios_crtc_mode_set,
1196         .mode_set_base = atombios_crtc_set_base,
1197         .prepare = atombios_crtc_prepare,
1198         .commit = atombios_crtc_commit,
1199         .load_lut = radeon_crtc_load_lut,
1200 };
1201
1202 void radeon_atombios_init_crtc(struct drm_device *dev,
1203                                struct radeon_crtc *radeon_crtc)
1204 {
1205         struct radeon_device *rdev = dev->dev_private;
1206
1207         if (ASIC_IS_DCE4(rdev)) {
1208                 switch (radeon_crtc->crtc_id) {
1209                 case 0:
1210                 default:
1211                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1212                         break;
1213                 case 1:
1214                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1215                         break;
1216                 case 2:
1217                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1218                         break;
1219                 case 3:
1220                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1221                         break;
1222                 case 4:
1223                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1224                         break;
1225                 case 5:
1226                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1227                         break;
1228                 }
1229         } else {
1230                 if (radeon_crtc->crtc_id == 1)
1231                         radeon_crtc->crtc_offset =
1232                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1233                 else
1234                         radeon_crtc->crtc_offset = 0;
1235         }
1236         radeon_crtc->pll_id = -1;
1237         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1238 }