drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "drm_crtc_helper.h"
  34
  35 static void
  36 nv50_evo_channel_del(struct nouveau_channel **pchan)
  37 {
  38         struct nouveau_channel *chan = *pchan;
  39
  40         if (!chan)
  41                 return;
  42         *pchan = NULL;
  43
  44         nouveau_gpuobj_channel_takedown(chan);
  45         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  46
  47         if (chan->user)
  48                 iounmap(chan->user);
  49
  50         kfree(chan);
  51 }
  52
  53 static int
  54 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
  55                     uint32_t tile_flags, uint32_t magic_flags,
  56                     uint32_t offset, uint32_t limit)
  57 {
  58         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
  59         struct drm_device *dev = evo->dev;
  60         struct nouveau_gpuobj *obj = NULL;
  61         int ret;
  62
  63         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
  64         if (ret)
  65                 return ret;
  66         obj->engine = NVOBJ_ENGINE_DISPLAY;
  67
  68         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
  69         if (ret) {
  70                 nouveau_gpuobj_del(dev, &obj);
  71                 return ret;
  72         }
  73
  74         dev_priv->engine.instmem.prepare_access(dev, true);
  75         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
  76         nv_wo32(dev, obj, 1, limit);
  77         nv_wo32(dev, obj, 2, offset);
  78         nv_wo32(dev, obj, 3, 0x00000000);
  79         nv_wo32(dev, obj, 4, 0x00000000);
  80         nv_wo32(dev, obj, 5, 0x00010000);
  81         dev_priv->engine.instmem.finish_access(dev);
  82
  83         return 0;
  84 }
  85
  86 static int
  87 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
  88 {
  89         struct drm_nouveau_private *dev_priv = dev->dev_private;
  90         struct nouveau_channel *chan;
  91         int ret;
  92
  93         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
  94         if (!chan)
  95                 return -ENOMEM;
  96         *pchan = chan;
  97
  98         chan->id = -1;
  99         chan->dev = dev;
 100         chan->user_get = 4;
 101         chan->user_put = 0;
 102
 103         INIT_LIST_HEAD(&chan->ramht_refs);
 104
 105         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
 106                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 107         if (ret) {
 108                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
 109                 nv50_evo_channel_del(pchan);
 110                 return ret;
 111         }
 112
 113         ret = nouveau_mem_init_heap(&chan->ramin_heap, chan->ramin->gpuobj->
 114                                     im_pramin->start, 32768);
 115         if (ret) {
 116                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
 117                 nv50_evo_channel_del(pchan);
 118                 return ret;
 119         }
 120
 121         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
 122                                      0, &chan->ramht);
 123         if (ret) {
 124                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
 125                 nv50_evo_channel_del(pchan);
 126                 return ret;
 127         }
 128
 129         if (dev_priv->chipset != 0x50) {
 130                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
 131                                           0, 0xffffffff);
 132                 if (ret) {
 133                         nv50_evo_channel_del(pchan);
 134                         return ret;
 135                 }
 136
 137
 138                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
 139                                           0, 0xffffffff);
 140                 if (ret) {
 141                         nv50_evo_channel_del(pchan);
 142                         return ret;
 143                 }
 144         }
 145
 146         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
 147                                   0, nouveau_mem_fb_amount(dev));
 148         if (ret) {
 149                 nv50_evo_channel_del(pchan);
 150                 return ret;
 151         }
 152
 153         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
 154                              false, true, &chan->pushbuf_bo);
 155         if (ret == 0)
 156                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
 157         if (ret) {
 158                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
 159                 nv50_evo_channel_del(pchan);
 160                 return ret;
 161         }
 162
 163         ret = nouveau_bo_map(chan->pushbuf_bo);
 164         if (ret) {
 165                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
 166                 nv50_evo_channel_del(pchan);
 167                 return ret;
 168         }
 169
 170         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 171                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
 172         if (!chan->user) {
 173                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
 174                 nv50_evo_channel_del(pchan);
 175                 return -ENOMEM;
 176         }
 177
 178         return 0;
 179 }
 180
 181 int
 182 nv50_display_init(struct drm_device *dev)
 183 {
 184         struct drm_nouveau_private *dev_priv = dev->dev_private;
 185         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 186         struct nouveau_channel *evo = dev_priv->evo;
 187         struct drm_connector *connector;
 188         uint32_t val, ram_amount, hpd_en[2];
 189         uint64_t start;
 190         int ret, i;
 191
 192         NV_DEBUG_KMS(dev, "\n");
 193
 194         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 195         /*
 196          * I think the 0x006101XX range is some kind of main control area
 197          * that enables things.
 198          */
 199         /* CRTC? */
 200         for (i = 0; i < 2; i++) {
 201                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 202                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 203                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 204                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 205                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 206                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 207                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 208                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 209         }
 210         /* DAC */
 211         for (i = 0; i < 3; i++) {
 212                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 213                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 214         }
 215         /* SOR */
 216         for (i = 0; i < 4; i++) {
 217                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 218                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 219         }
 220         /* Something not yet in use, tv-out maybe. */
 221         for (i = 0; i < 3; i++) {
 222                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 223                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 224         }
 225
 226         for (i = 0; i < 3; i++) {
 227                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 228                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 229                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 230         }
 231
 232         /* This used to be in crtc unblank, but seems out of place there. */
 233         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
 234         /* RAM is clamped to 256 MiB. */
 235         ram_amount = nouveau_mem_fb_amount(dev);
 236         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
 237         if (ram_amount > 256*1024*1024)
 238                 ram_amount = 256*1024*1024;
 239         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
 240         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
 241         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
 242
 243         /* The precise purpose is unknown, i suspect it has something to do
 244          * with text mode.
 245          */
 246         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 247                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 248                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 249                 if (!nv_wait(0x006194e8, 2, 0)) {
 250                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 251                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 252                                                 nv_rd32(dev, 0x6194e8));
 253                         return -EBUSY;
 254                 }
 255         }
 256
 257         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
 258          * stuck in some unspecified state
 259          */
 260         start = ptimer->read(dev);
 261         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
 262         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
 263                 if ((val & 0x9f0000) == 0x20000)
 264                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 265                                                         val | 0x800000);
 266
 267                 if ((val & 0x3f0000) == 0x30000)
 268                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 269                                                         val | 0x200000);
 270
 271                 if (ptimer->read(dev) - start > 1000000000ULL) {
 272                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
 273                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
 274                         return -EBUSY;
 275                 }
 276         }
 277
 278         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 279         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
 280         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
 281                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
 282                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 283                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 284                 return -EBUSY;
 285         }
 286
 287         for (i = 0; i < 2; i++) {
 288                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 289                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 290                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 291                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 292                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 293                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 294                         return -EBUSY;
 295                 }
 296
 297                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 298                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 299                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 300                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 301                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 302                         NV_ERROR(dev, "timeout: "
 303                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 304                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 305                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 306                         return -EBUSY;
 307                 }
 308         }
 309
 310         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
 311
 312         /* initialise fifo */
 313         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
 314                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
 315                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
 316                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
 317         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
 318         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
 319         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
 320                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
 321                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
 322                 return -EBUSY;
 323         }
 324         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 325                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
 326                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 327         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
 328         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
 329                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 330         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
 331
 332         evo->dma.max = (4096/4) - 2;
 333         evo->dma.put = 0;
 334         evo->dma.cur = evo->dma.put;
 335         evo->dma.free = evo->dma.max - evo->dma.cur;
 336
 337         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
 338         if (ret)
 339                 return ret;
 340
 341         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 342                 OUT_RING(evo, 0);
 343
 344         ret = RING_SPACE(evo, 11);
 345         if (ret)
 346                 return ret;
 347         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 348         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 349         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 350         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 351         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 352         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 353         OUT_RING(evo, 0);
 354         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 355         OUT_RING(evo, 0);
 356         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 357         OUT_RING(evo, 0);
 358         FIRE_RING(evo);
 359         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
 360                 NV_ERROR(dev, "evo pushbuf stalled\n");
 361
 362         /* enable clock change interrupts. */
 363         nv_wr32(dev, 0x610028, 0x00010001);
 364         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
 365                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
 366                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
 367
 368         /* enable hotplug interrupts */
 369         hpd_en[0] = hpd_en[1] = 0;
 370         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 371                 struct nouveau_connector *conn = nouveau_connector(connector);
 372                 struct dcb_gpio_entry *gpio;
 373
 374                 if (conn->dcb->gpio_tag == 0xff)
 375                         continue;
 376
 377                 gpio = nouveau_bios_gpio_entry(dev, conn->dcb->gpio_tag);
 378                 if (!gpio)
 379                         continue;
 380
 381                 hpd_en[gpio->line >> 4] |= (0x00010001 << (gpio->line & 0xf));
 382         }
 383
 384         nv_wr32(dev, 0xe054, 0xffffffff);
 385         nv_wr32(dev, 0xe050, hpd_en[0]);
 386         if (dev_priv->chipset >= 0x90) {
 387                 nv_wr32(dev, 0xe074, 0xffffffff);
 388                 nv_wr32(dev, 0xe070, hpd_en[1]);
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int nv50_display_disable(struct drm_device *dev)
 395 {
 396         struct drm_nouveau_private *dev_priv = dev->dev_private;
 397         struct drm_crtc *drm_crtc;
 398         int ret, i;
 399
 400         NV_DEBUG_KMS(dev, "\n");
 401
 402         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 403                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 404
 405                 nv50_crtc_blank(crtc, true);
 406         }
 407
 408         ret = RING_SPACE(dev_priv->evo, 2);
 409         if (ret == 0) {
 410                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 411                 OUT_RING(dev_priv->evo, 0);
 412         }
 413         FIRE_RING(dev_priv->evo);
 414
 415         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 416          * cleaning up?
 417          */
 418         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 419                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 420                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 421
 422                 if (!crtc->base.enabled)
 423                         continue;
 424
 425                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 426                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
 427                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 428                                       "0x%08x\n", mask, mask);
 429                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 430                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 431                 }
 432         }
 433
 434         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
 435         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
 436         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
 437                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
 438                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 439                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 440         }
 441
 442         for (i = 0; i < 3; i++) {
 443                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
 444                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 445                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 446                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 447                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 448                 }
 449         }
 450
 451         /* disable interrupts. */
 452         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
 453
 454         /* disable hotplug interrupts */
 455         nv_wr32(dev, 0xe054, 0xffffffff);
 456         nv_wr32(dev, 0xe050, 0x00000000);
 457         if (dev_priv->chipset >= 0x90) {
 458                 nv_wr32(dev, 0xe074, 0xffffffff);
 459                 nv_wr32(dev, 0xe070, 0x00000000);
 460         }
 461         return 0;
 462 }
 463
 464 int nv50_display_create(struct drm_device *dev)
 465 {
 466         struct drm_nouveau_private *dev_priv = dev->dev_private;
 467         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 468         int ret, i;
 469
 470         NV_DEBUG_KMS(dev, "\n");
 471
 472         /* init basic kernel modesetting */
 473         drm_mode_config_init(dev);
 474
 475         /* Initialise some optional connector properties. */
 476         drm_mode_create_scaling_mode_property(dev);
 477         drm_mode_create_dithering_property(dev);
 478
 479         dev->mode_config.min_width = 0;
 480         dev->mode_config.min_height = 0;
 481
 482         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 483
 484         dev->mode_config.max_width = 8192;
 485         dev->mode_config.max_height = 8192;
 486
 487         dev->mode_config.fb_base = dev_priv->fb_phys;
 488
 489         /* Create EVO channel */
 490         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
 491         if (ret) {
 492                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
 493                 return ret;
 494         }
 495
 496         /* Create CRTC objects */
 497         for (i = 0; i < 2; i++)
 498                 nv50_crtc_create(dev, i);
 499
 500         /* We setup the encoders from the BIOS table */
 501         for (i = 0 ; i < dcb->entries; i++) {
 502                 struct dcb_entry *entry = &dcb->entry[i];
 503
 504                 if (entry->location != DCB_LOC_ON_CHIP) {
 505                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 506                                 entry->type, ffs(entry->or) - 1);
 507                         continue;
 508                 }
 509
 510                 switch (entry->type) {
 511                 case OUTPUT_TMDS:
 512                 case OUTPUT_LVDS:
 513                 case OUTPUT_DP:
 514                         nv50_sor_create(dev, entry);
 515                         break;
 516                 case OUTPUT_ANALOG:
 517                         nv50_dac_create(dev, entry);
 518                         break;
 519                 default:
 520                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 521                         continue;
 522                 }
 523         }
 524
 525         for (i = 0 ; i < dcb->connector.entries; i++) {
 526                 if (i != 0 && dcb->connector.entry[i].index2 ==
 527                               dcb->connector.entry[i - 1].index2)
 528                         continue;
 529                 nouveau_connector_create(dev, &dcb->connector.entry[i]);
 530         }
 531
 532         ret = nv50_display_init(dev);
 533         if (ret)
 534                 return ret;
 535
 536         return 0;
 537 }
 538
 539 int nv50_display_destroy(struct drm_device *dev)
 540 {
 541         struct drm_nouveau_private *dev_priv = dev->dev_private;
 542
 543         NV_DEBUG_KMS(dev, "\n");
 544
 545         drm_mode_config_cleanup(dev);
 546
 547         nv50_display_disable(dev);
 548         nv50_evo_channel_del(&dev_priv->evo);
 549
 550         return 0;
 551 }
 552
 553 static inline uint32_t
 554 nv50_display_mode_ctrl(struct drm_device *dev, bool sor, int or)
 555 {
 556         struct drm_nouveau_private *dev_priv = dev->dev_private;
 557         uint32_t mc;
 558
 559         if (sor) {
 560                 if (dev_priv->chipset < 0x90 ||
 561                     dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0)
 562                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(or));
 563                 else
 564                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(or));
 565         } else {
 566                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(or));
 567         }
 568
 569         return mc;
 570 }
 571
 572 static int
 573 nv50_display_irq_head(struct drm_device *dev, int *phead,
 574                       struct dcb_entry **pdcbent)
 575 {
 576         struct drm_nouveau_private *dev_priv = dev->dev_private;
 577         uint32_t unk30 = nv_rd32(dev, NV50_PDISPLAY_UNK30_CTRL);
 578         uint32_t dac = 0, sor = 0;
 579         int head, i, or = 0, type = OUTPUT_ANY;
 580
 581         /* We're assuming that head 0 *or* head 1 will be active here,
 582          * and not both.  I'm not sure if the hw will even signal both
 583          * ever, but it definitely shouldn't for us as we commit each
 584          * CRTC separately, and submission will be blocked by the GPU
 585          * until we handle each in turn.
 586          */
 587         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 588         head = ffs((unk30 >> 9) & 3) - 1;
 589         if (head < 0)
 590                 return -EINVAL;
 591
 592         /* This assumes CRTCs are never bound to multiple encoders, which
 593          * should be the case.
 594          */
 595         for (i = 0; i < 3 && type == OUTPUT_ANY; i++) {
 596                 uint32_t mc = nv50_display_mode_ctrl(dev, false, i);
 597                 if (!(mc & (1 << head)))
 598                         continue;
 599
 600                 switch ((mc >> 8) & 0xf) {
 601                 case 0: type = OUTPUT_ANALOG; break;
 602                 case 1: type = OUTPUT_TV; break;
 603                 default:
 604                         NV_ERROR(dev, "unknown dac mode_ctrl: 0x%08x\n", dac);
 605                         return -1;
 606                 }
 607
 608                 or = i;
 609         }
 610
 611         for (i = 0; i < 4 && type == OUTPUT_ANY; i++) {
 612                 uint32_t mc = nv50_display_mode_ctrl(dev, true, i);
 613                 if (!(mc & (1 << head)))
 614                         continue;
 615
 616                 switch ((mc >> 8) & 0xf) {
 617                 case 0: type = OUTPUT_LVDS; break;
 618                 case 1: type = OUTPUT_TMDS; break;
 619                 case 2: type = OUTPUT_TMDS; break;
 620                 case 5: type = OUTPUT_TMDS; break;
 621                 case 8: type = OUTPUT_DP; break;
 622                 case 9: type = OUTPUT_DP; break;
 623                 default:
 624                         NV_ERROR(dev, "unknown sor mode_ctrl: 0x%08x\n", sor);
 625                         return -1;
 626                 }
 627
 628                 or = i;
 629         }
 630
 631         NV_DEBUG_KMS(dev, "type %d, or %d\n", type, or);
 632         if (type == OUTPUT_ANY) {
 633                 NV_ERROR(dev, "unknown encoder!!\n");
 634                 return -1;
 635         }
 636
 637         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 638                 struct dcb_entry *dcbent = &dev_priv->vbios.dcb.entry[i];
 639
 640                 if (dcbent->type != type)
 641                         continue;
 642
 643                 if (!(dcbent->or & (1 << or)))
 644                         continue;
 645
 646                 *phead = head;
 647                 *pdcbent = dcbent;
 648                 return 0;
 649         }
 650
 651         NV_ERROR(dev, "no DCB entry for %d %d\n", dac != 0, or);
 652         return 0;
 653 }
 654
 655 static uint32_t
 656 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcbent,
 657                            int pxclk)
 658 {
 659         struct drm_nouveau_private *dev_priv = dev->dev_private;
 660         struct nouveau_connector *nv_connector = NULL;
 661         struct drm_encoder *encoder;
 662         struct nvbios *bios = &dev_priv->vbios;
 663         uint32_t mc, script = 0, or;
 664
 665         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 666                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 667
 668                 if (nv_encoder->dcb != dcbent)
 669                         continue;
 670
 671                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 672                 break;
 673         }
 674
 675         or = ffs(dcbent->or) - 1;
 676         mc = nv50_display_mode_ctrl(dev, dcbent->type != OUTPUT_ANALOG, or);
 677         switch (dcbent->type) {
 678         case OUTPUT_LVDS:
 679                 script = (mc >> 8) & 0xf;
 680                 if (bios->fp_no_ddc) {
 681                         if (bios->fp.dual_link)
 682                                 script |= 0x0100;
 683                         if (bios->fp.if_is_24bit)
 684                                 script |= 0x0200;
 685                 } else {
 686                         if (pxclk >= bios->fp.duallink_transition_clk) {
 687                                 script |= 0x0100;
 688                                 if (bios->fp.strapless_is_24bit & 2)
 689                                         script |= 0x0200;
 690                         } else
 691                         if (bios->fp.strapless_is_24bit & 1)
 692                                 script |= 0x0200;
 693
 694                         if (nv_connector && nv_connector->edid &&
 695                             (nv_connector->edid->revision >= 4) &&
 696                             (nv_connector->edid->input & 0x70) >= 0x20)
 697                                 script |= 0x0200;
 698                 }
 699
 700                 if (nouveau_uscript_lvds >= 0) {
 701                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 702                                      "for output LVDS-%d\n", script,
 703                                      nouveau_uscript_lvds, or);
 704                         script = nouveau_uscript_lvds;
 705                 }
 706                 break;
 707         case OUTPUT_TMDS:
 708                 script = (mc >> 8) & 0xf;
 709                 if (pxclk >= 165000)
 710                         script |= 0x0100;
 711
 712                 if (nouveau_uscript_tmds >= 0) {
 713                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 714                                      "for output TMDS-%d\n", script,
 715                                      nouveau_uscript_tmds, or);
 716                         script = nouveau_uscript_tmds;
 717                 }
 718                 break;
 719         case OUTPUT_DP:
 720                 script = (mc >> 8) & 0xf;
 721                 break;
 722         case OUTPUT_ANALOG:
 723                 script = 0xff;
 724                 break;
 725         default:
 726                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 727                 break;
 728         }
 729
 730         return script;
 731 }
 732
 733 static void
 734 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 735 {
 736         struct drm_nouveau_private *dev_priv = dev->dev_private;
 737         struct nouveau_channel *chan;
 738         struct list_head *entry, *tmp;
 739
 740         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
 741                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
 742
 743                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 744                                                 chan->nvsw.vblsem_rval);
 745                 list_del(&chan->nvsw.vbl_wait);
 746         }
 747 }
 748
 749 static void
 750 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 751 {
 752         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 753
 754         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 755                 nv50_display_vblank_crtc_handler(dev, 0);
 756
 757         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 758                 nv50_display_vblank_crtc_handler(dev, 1);
 759
 760         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
 761                      NV50_PDISPLAY_INTR_EN) & ~intr);
 762         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
 763 }
 764
 765 static void
 766 nv50_display_unk10_handler(struct drm_device *dev)
 767 {
 768         struct dcb_entry *dcbent;
 769         int head, ret;
 770
 771         ret = nv50_display_irq_head(dev, &head, &dcbent);
 772         if (ret)
 773                 goto ack;
 774
 775         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 776
 777         nouveau_bios_run_display_table(dev, dcbent, 0, -1);
 778
 779 ack:
 780         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 781         nv_wr32(dev, 0x610030, 0x80000000);
 782 }
 783
 784 static void
 785 nv50_display_unk20_handler(struct drm_device *dev)
 786 {
 787         struct dcb_entry *dcbent;
 788         uint32_t tmp, pclk, script;
 789         int head, or, ret;
 790
 791         ret = nv50_display_irq_head(dev, &head, &dcbent);
 792         if (ret)
 793                 goto ack;
 794         or = ffs(dcbent->or) - 1;
 795         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
 796         script = nv50_display_script_select(dev, dcbent, pclk);
 797
 798         NV_DEBUG_KMS(dev, "head %d pxclk: %dKHz\n", head, pclk);
 799
 800         if (dcbent->type != OUTPUT_DP)
 801                 nouveau_bios_run_display_table(dev, dcbent, 0, -2);
 802
 803         nv50_crtc_set_clock(dev, head, pclk);
 804
 805         nouveau_bios_run_display_table(dev, dcbent, script, pclk);
 806
 807         tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head));
 808         tmp &= ~0x000000f;
 809         nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(head), tmp);
 810
 811         if (dcbent->type != OUTPUT_ANALOG) {
 812                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 813                 tmp &= ~0x00000f0f;
 814                 if (script & 0x0100)
 815                         tmp |= 0x00000101;
 816                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 817         } else {
 818                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 819         }
 820
 821 ack:
 822         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 823         nv_wr32(dev, 0x610030, 0x80000000);
 824 }
 825
 826 static void
 827 nv50_display_unk40_handler(struct drm_device *dev)
 828 {
 829         struct dcb_entry *dcbent;
 830         int head, pclk, script, ret;
 831
 832         ret = nv50_display_irq_head(dev, &head, &dcbent);
 833         if (ret)
 834                 goto ack;
 835         pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(head, CLOCK)) & 0x3fffff;
 836         script = nv50_display_script_select(dev, dcbent, pclk);
 837
 838         nouveau_bios_run_display_table(dev, dcbent, script, -pclk);
 839
 840 ack:
 841         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 842         nv_wr32(dev, 0x610030, 0x80000000);
 843         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 844 }
 845
 846 void
 847 nv50_display_irq_handler_bh(struct work_struct *work)
 848 {
 849         struct drm_nouveau_private *dev_priv =
 850                 container_of(work, struct drm_nouveau_private, irq_work);
 851         struct drm_device *dev = dev_priv->dev;
 852
 853         for (;;) {
 854                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 855                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 856
 857                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 858
 859                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 860                         nv50_display_unk10_handler(dev);
 861                 else
 862                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 863                         nv50_display_unk20_handler(dev);
 864                 else
 865                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 866                         nv50_display_unk40_handler(dev);
 867                 else
 868                         break;
 869         }
 870
 871         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 872 }
 873
 874 static void
 875 nv50_display_error_handler(struct drm_device *dev)
 876 {
 877         uint32_t addr, data;
 878
 879         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
 880         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
 881         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
 882
 883         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
 884                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 885
 886         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
 887 }
 888
 889 static void
 890 nv50_display_irq_hotplug(struct drm_device *dev)
 891 {
 892         struct drm_nouveau_private *dev_priv = dev->dev_private;
 893         struct drm_connector *connector;
 894         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
 895         uint32_t unplug_mask, plug_mask, change_mask;
 896         uint32_t hpd0, hpd1 = 0;
 897
 898         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
 899         if (dev_priv->chipset >= 0x90)
 900                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
 901
 902         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
 903         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
 904         change_mask = plug_mask | unplug_mask;
 905
 906         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 907                 struct drm_encoder_helper_funcs *helper;
 908                 struct nouveau_connector *nv_connector =
 909                         nouveau_connector(connector);
 910                 struct nouveau_encoder *nv_encoder;
 911                 struct dcb_gpio_entry *gpio;
 912                 uint32_t reg;
 913                 bool plugged;
 914
 915                 if (!nv_connector->dcb)
 916                         continue;
 917
 918                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
 919                 if (!gpio || !(change_mask & (1 << gpio->line)))
 920                         continue;
 921
 922                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
 923                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
 924                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
 925                         drm_get_connector_name(connector)) ;
 926
 927                 if (!connector->encoder || !connector->encoder->crtc ||
 928                     !connector->encoder->crtc->enabled)
 929                         continue;
 930                 nv_encoder = nouveau_encoder(connector->encoder);
 931                 helper = connector->encoder->helper_private;
 932
 933                 if (nv_encoder->dcb->type != OUTPUT_DP)
 934                         continue;
 935
 936                 if (plugged)
 937                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
 938                 else
 939                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
 940         }
 941
 942         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
 943         if (dev_priv->chipset >= 0x90)
 944                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
 945
 946         nouveau_fbcon_hotplug(dev);
 947 }
 948
 949 void
 950 nv50_display_irq_handler(struct drm_device *dev)
 951 {
 952         struct drm_nouveau_private *dev_priv = dev->dev_private;
 953         uint32_t delayed = 0;
 954
 955         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG)
 956                 nv50_display_irq_hotplug(dev);
 957
 958         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 959                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 960                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 961                 uint32_t clock;
 962
 963                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 964
 965                 if (!intr0 && !(intr1 & ~delayed))
 966                         break;
 967
 968                 if (intr0 & 0x00010000) {
 969                         nv50_display_error_handler(dev);
 970                         intr0 &= ~0x00010000;
 971                 }
 972
 973                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 974                         nv50_display_vblank_handler(dev, intr1);
 975                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 976                 }
 977
 978                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 979                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 980                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 981                 if (clock) {
 982                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 983                         if (!work_pending(&dev_priv->irq_work))
 984                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
 985                         delayed |= clock;
 986                         intr1 &= ~clock;
 987                 }
 988
 989                 if (intr0) {
 990                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 991                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
 992                 }
 993
 994                 if (intr1) {
 995                         NV_ERROR(dev,
 996                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
 997                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
 998                 }
 999         }
1000 }
1001