drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nouveau_crtc.h"
  29 #include "nouveau_encoder.h"
  30 #include "nouveau_connector.h"
  31 #include "nouveau_fb.h"
  32 #include "nouveau_fbcon.h"
  33 #include "drm_crtc_helper.h"
  34
  35 static void
  36 nv50_evo_channel_del(struct nouveau_channel **pchan)
  37 {
  38         struct nouveau_channel *chan = *pchan;
  39
  40         if (!chan)
  41                 return;
  42         *pchan = NULL;
  43
  44         nouveau_gpuobj_channel_takedown(chan);
  45         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  46
  47         if (chan->user)
  48                 iounmap(chan->user);
  49
  50         kfree(chan);
  51 }
  52
  53 static int
  54 nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
  55                     uint32_t tile_flags, uint32_t magic_flags,
  56                     uint32_t offset, uint32_t limit)
  57 {
  58         struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
  59         struct drm_device *dev = evo->dev;
  60         struct nouveau_gpuobj *obj = NULL;
  61         int ret;
  62
  63         ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
  64         if (ret)
  65                 return ret;
  66         obj->engine = NVOBJ_ENGINE_DISPLAY;
  67
  68         ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
  69         if (ret) {
  70                 nouveau_gpuobj_del(dev, &obj);
  71                 return ret;
  72         }
  73
  74         nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
  75         nv_wo32(dev, obj, 1, limit);
  76         nv_wo32(dev, obj, 2, offset);
  77         nv_wo32(dev, obj, 3, 0x00000000);
  78         nv_wo32(dev, obj, 4, 0x00000000);
  79         nv_wo32(dev, obj, 5, 0x00010000);
  80         dev_priv->engine.instmem.flush(dev);
  81
  82         return 0;
  83 }
  84
  85 static int
  86 nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
  87 {
  88         struct drm_nouveau_private *dev_priv = dev->dev_private;
  89         struct nouveau_channel *chan;
  90         int ret;
  91
  92         chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
  93         if (!chan)
  94                 return -ENOMEM;
  95         *pchan = chan;
  96
  97         chan->id = -1;
  98         chan->dev = dev;
  99         chan->user_get = 4;
 100         chan->user_put = 0;
 101
 102         INIT_LIST_HEAD(&chan->ramht_refs);
 103
 104         ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
 105                                      NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
 106         if (ret) {
 107                 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
 108                 nv50_evo_channel_del(pchan);
 109                 return ret;
 110         }
 111
 112         ret = drm_mm_init(&chan->ramin_heap,
 113                           chan->ramin->gpuobj->im_pramin->start, 32768);
 114         if (ret) {
 115                 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
 116                 nv50_evo_channel_del(pchan);
 117                 return ret;
 118         }
 119
 120         ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
 121                                      0, &chan->ramht);
 122         if (ret) {
 123                 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
 124                 nv50_evo_channel_del(pchan);
 125                 return ret;
 126         }
 127
 128         if (dev_priv->chipset != 0x50) {
 129                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
 130                                           0, 0xffffffff);
 131                 if (ret) {
 132                         nv50_evo_channel_del(pchan);
 133                         return ret;
 134                 }
 135
 136
 137                 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
 138                                           0, 0xffffffff);
 139                 if (ret) {
 140                         nv50_evo_channel_del(pchan);
 141                         return ret;
 142                 }
 143         }
 144
 145         ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
 146                                   0, dev_priv->vram_size);
 147         if (ret) {
 148                 nv50_evo_channel_del(pchan);
 149                 return ret;
 150         }
 151
 152         ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
 153                              false, true, &chan->pushbuf_bo);
 154         if (ret == 0)
 155                 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
 156         if (ret) {
 157                 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
 158                 nv50_evo_channel_del(pchan);
 159                 return ret;
 160         }
 161
 162         ret = nouveau_bo_map(chan->pushbuf_bo);
 163         if (ret) {
 164                 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
 165                 nv50_evo_channel_del(pchan);
 166                 return ret;
 167         }
 168
 169         chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
 170                                         NV50_PDISPLAY_USER(0), PAGE_SIZE);
 171         if (!chan->user) {
 172                 NV_ERROR(dev, "Error mapping EVO control regs.\n");
 173                 nv50_evo_channel_del(pchan);
 174                 return -ENOMEM;
 175         }
 176
 177         return 0;
 178 }
 179
 180 int
 181 nv50_display_early_init(struct drm_device *dev)
 182 {
 183         return 0;
 184 }
 185
 186 void
 187 nv50_display_late_takedown(struct drm_device *dev)
 188 {
 189 }
 190
 191 int
 192 nv50_display_init(struct drm_device *dev)
 193 {
 194         struct drm_nouveau_private *dev_priv = dev->dev_private;
 195         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
 196         struct nouveau_channel *evo = dev_priv->evo;
 197         struct drm_connector *connector;
 198         uint32_t val, ram_amount;
 199         uint64_t start;
 200         int ret, i;
 201
 202         NV_DEBUG_KMS(dev, "\n");
 203
 204         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 205         /*
 206          * I think the 0x006101XX range is some kind of main control area
 207          * that enables things.
 208          */
 209         /* CRTC? */
 210         for (i = 0; i < 2; i++) {
 211                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 212                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 213                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 214                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 215                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 216                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 217                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 218                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 219         }
 220         /* DAC */
 221         for (i = 0; i < 3; i++) {
 222                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 223                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 224         }
 225         /* SOR */
 226         for (i = 0; i < 4; i++) {
 227                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 228                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 229         }
 230         /* Something not yet in use, tv-out maybe. */
 231         for (i = 0; i < 3; i++) {
 232                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 233                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 234         }
 235
 236         for (i = 0; i < 3; i++) {
 237                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 238                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 239                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 240         }
 241
 242         /* This used to be in crtc unblank, but seems out of place there. */
 243         nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
 244         /* RAM is clamped to 256 MiB. */
 245         ram_amount = dev_priv->vram_size;
 246         NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
 247         if (ram_amount > 256*1024*1024)
 248                 ram_amount = 256*1024*1024;
 249         nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
 250         nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
 251         nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
 252
 253         /* The precise purpose is unknown, i suspect it has something to do
 254          * with text mode.
 255          */
 256         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 257                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 258                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 259                 if (!nv_wait(0x006194e8, 2, 0)) {
 260                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 261                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 262                                                 nv_rd32(dev, 0x6194e8));
 263                         return -EBUSY;
 264                 }
 265         }
 266
 267         /* taken from nv bug #12637, attempts to un-wedge the hw if it's
 268          * stuck in some unspecified state
 269          */
 270         start = ptimer->read(dev);
 271         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
 272         while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
 273                 if ((val & 0x9f0000) == 0x20000)
 274                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 275                                                         val | 0x800000);
 276
 277                 if ((val & 0x3f0000) == 0x30000)
 278                         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 279                                                         val | 0x200000);
 280
 281                 if (ptimer->read(dev) - start > 1000000000ULL) {
 282                         NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
 283                         NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
 284                         return -EBUSY;
 285                 }
 286         }
 287
 288         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 289         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
 290         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
 291                 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
 292                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 293                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 294                 return -EBUSY;
 295         }
 296
 297         for (i = 0; i < 2; i++) {
 298                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 299                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 300                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 301                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 302                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 303                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 304                         return -EBUSY;
 305                 }
 306
 307                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 308                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 309                 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 310                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 311                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 312                         NV_ERROR(dev, "timeout: "
 313                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 314                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 315                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 316                         return -EBUSY;
 317                 }
 318         }
 319
 320         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
 321
 322         /* initialise fifo */
 323         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
 324                 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
 325                 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
 326                 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
 327         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
 328         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
 329         if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
 330                 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
 331                 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
 332                 return -EBUSY;
 333         }
 334         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
 335                 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
 336                  NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 337         nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
 338         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
 339                 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
 340         nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
 341
 342         evo->dma.max = (4096/4) - 2;
 343         evo->dma.put = 0;
 344         evo->dma.cur = evo->dma.put;
 345         evo->dma.free = evo->dma.max - evo->dma.cur;
 346
 347         ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
 348         if (ret)
 349                 return ret;
 350
 351         for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
 352                 OUT_RING(evo, 0);
 353
 354         ret = RING_SPACE(evo, 11);
 355         if (ret)
 356                 return ret;
 357         BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
 358         OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 359         OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
 360         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
 361         OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
 362         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
 363         OUT_RING(evo, 0);
 364         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
 365         OUT_RING(evo, 0);
 366         BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
 367         OUT_RING(evo, 0);
 368         FIRE_RING(evo);
 369         if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
 370                 NV_ERROR(dev, "evo pushbuf stalled\n");
 371
 372         /* enable clock change interrupts. */
 373         nv_wr32(dev, 0x610028, 0x00010001);
 374         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
 375                                              NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
 376                                              NV50_PDISPLAY_INTR_EN_CLK_UNK40));
 377
 378         /* enable hotplug interrupts */
 379         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 380                 struct nouveau_connector *conn = nouveau_connector(connector);
 381
 382                 nv50_gpio_irq_enable(dev, conn->dcb->gpio_tag, true);
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int nv50_display_disable(struct drm_device *dev)
 389 {
 390         struct drm_nouveau_private *dev_priv = dev->dev_private;
 391         struct drm_crtc *drm_crtc;
 392         int ret, i;
 393
 394         NV_DEBUG_KMS(dev, "\n");
 395
 396         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 397                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 398
 399                 nv50_crtc_blank(crtc, true);
 400         }
 401
 402         ret = RING_SPACE(dev_priv->evo, 2);
 403         if (ret == 0) {
 404                 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
 405                 OUT_RING(dev_priv->evo, 0);
 406         }
 407         FIRE_RING(dev_priv->evo);
 408
 409         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 410          * cleaning up?
 411          */
 412         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 413                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 414                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 415
 416                 if (!crtc->base.enabled)
 417                         continue;
 418
 419                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 420                 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
 421                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 422                                       "0x%08x\n", mask, mask);
 423                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 424                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 425                 }
 426         }
 427
 428         nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
 429         nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
 430         if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
 431                 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
 432                 NV_ERROR(dev, "0x610200 = 0x%08x\n",
 433                           nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
 434         }
 435
 436         for (i = 0; i < 3; i++) {
 437                 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
 438                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 439                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 440                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 441                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 442                 }
 443         }
 444
 445         /* disable interrupts. */
 446         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
 447
 448         /* disable hotplug interrupts */
 449         nv_wr32(dev, 0xe054, 0xffffffff);
 450         nv_wr32(dev, 0xe050, 0x00000000);
 451         if (dev_priv->chipset >= 0x90) {
 452                 nv_wr32(dev, 0xe074, 0xffffffff);
 453                 nv_wr32(dev, 0xe070, 0x00000000);
 454         }
 455         return 0;
 456 }
 457
 458 int nv50_display_create(struct drm_device *dev)
 459 {
 460         struct drm_nouveau_private *dev_priv = dev->dev_private;
 461         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 462         struct drm_connector *connector, *ct;
 463         int ret, i;
 464
 465         NV_DEBUG_KMS(dev, "\n");
 466
 467         /* init basic kernel modesetting */
 468         drm_mode_config_init(dev);
 469
 470         /* Initialise some optional connector properties. */
 471         drm_mode_create_scaling_mode_property(dev);
 472         drm_mode_create_dithering_property(dev);
 473
 474         dev->mode_config.min_width = 0;
 475         dev->mode_config.min_height = 0;
 476
 477         dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
 478
 479         dev->mode_config.max_width = 8192;
 480         dev->mode_config.max_height = 8192;
 481
 482         dev->mode_config.fb_base = dev_priv->fb_phys;
 483
 484         /* Create EVO channel */
 485         ret = nv50_evo_channel_new(dev, &dev_priv->evo);
 486         if (ret) {
 487                 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
 488                 return ret;
 489         }
 490
 491         /* Create CRTC objects */
 492         for (i = 0; i < 2; i++)
 493                 nv50_crtc_create(dev, i);
 494
 495         /* We setup the encoders from the BIOS table */
 496         for (i = 0 ; i < dcb->entries; i++) {
 497                 struct dcb_entry *entry = &dcb->entry[i];
 498
 499                 if (entry->location != DCB_LOC_ON_CHIP) {
 500                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 501                                 entry->type, ffs(entry->or) - 1);
 502                         continue;
 503                 }
 504
 505                 connector = nouveau_connector_create(dev, entry->connector);
 506                 if (IS_ERR(connector))
 507                         continue;
 508
 509                 switch (entry->type) {
 510                 case OUTPUT_TMDS:
 511                 case OUTPUT_LVDS:
 512                 case OUTPUT_DP:
 513                         nv50_sor_create(connector, entry);
 514                         break;
 515                 case OUTPUT_ANALOG:
 516                         nv50_dac_create(connector, entry);
 517                         break;
 518                 default:
 519                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 520                         continue;
 521                 }
 522         }
 523
 524         list_for_each_entry_safe(connector, ct,
 525                                  &dev->mode_config.connector_list, head) {
 526                 if (!connector->encoder_ids[0]) {
 527                         NV_WARN(dev, "%s has no encoders, removing\n",
 528                                 drm_get_connector_name(connector));
 529                         connector->funcs->destroy(connector);
 530                 }
 531         }
 532
 533         ret = nv50_display_init(dev);
 534         if (ret) {
 535                 nv50_display_destroy(dev);
 536                 return ret;
 537         }
 538
 539         return 0;
 540 }
 541
 542 void
 543 nv50_display_destroy(struct drm_device *dev)
 544 {
 545         struct drm_nouveau_private *dev_priv = dev->dev_private;
 546
 547         NV_DEBUG_KMS(dev, "\n");
 548
 549         drm_mode_config_cleanup(dev);
 550
 551         nv50_display_disable(dev);
 552         nv50_evo_channel_del(&dev_priv->evo);
 553 }
 554
 555 static u16
 556 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
 557                            u32 mc, int pxclk)
 558 {
 559         struct drm_nouveau_private *dev_priv = dev->dev_private;
 560         struct nouveau_connector *nv_connector = NULL;
 561         struct drm_encoder *encoder;
 562         struct nvbios *bios = &dev_priv->vbios;
 563         u32 script = 0, or;
 564
 565         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 566                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 567
 568                 if (nv_encoder->dcb != dcb)
 569                         continue;
 570
 571                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 572                 break;
 573         }
 574
 575         or = ffs(dcb->or) - 1;
 576         switch (dcb->type) {
 577         case OUTPUT_LVDS:
 578                 script = (mc >> 8) & 0xf;
 579                 if (bios->fp_no_ddc) {
 580                         if (bios->fp.dual_link)
 581                                 script |= 0x0100;
 582                         if (bios->fp.if_is_24bit)
 583                                 script |= 0x0200;
 584                 } else {
 585                         if (pxclk >= bios->fp.duallink_transition_clk) {
 586                                 script |= 0x0100;
 587                                 if (bios->fp.strapless_is_24bit & 2)
 588                                         script |= 0x0200;
 589                         } else
 590                         if (bios->fp.strapless_is_24bit & 1)
 591                                 script |= 0x0200;
 592
 593                         if (nv_connector && nv_connector->edid &&
 594                             (nv_connector->edid->revision >= 4) &&
 595                             (nv_connector->edid->input & 0x70) >= 0x20)
 596                                 script |= 0x0200;
 597                 }
 598
 599                 if (nouveau_uscript_lvds >= 0) {
 600                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 601                                      "for output LVDS-%d\n", script,
 602                                      nouveau_uscript_lvds, or);
 603                         script = nouveau_uscript_lvds;
 604                 }
 605                 break;
 606         case OUTPUT_TMDS:
 607                 script = (mc >> 8) & 0xf;
 608                 if (pxclk >= 165000)
 609                         script |= 0x0100;
 610
 611                 if (nouveau_uscript_tmds >= 0) {
 612                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 613                                      "for output TMDS-%d\n", script,
 614                                      nouveau_uscript_tmds, or);
 615                         script = nouveau_uscript_tmds;
 616                 }
 617                 break;
 618         case OUTPUT_DP:
 619                 script = (mc >> 8) & 0xf;
 620                 break;
 621         case OUTPUT_ANALOG:
 622                 script = 0xff;
 623                 break;
 624         default:
 625                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 626                 break;
 627         }
 628
 629         return script;
 630 }
 631
 632 static void
 633 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 634 {
 635         struct drm_nouveau_private *dev_priv = dev->dev_private;
 636         struct nouveau_channel *chan;
 637         struct list_head *entry, *tmp;
 638
 639         list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
 640                 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
 641
 642                 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
 643                                                 chan->nvsw.vblsem_rval);
 644                 list_del(&chan->nvsw.vbl_wait);
 645         }
 646 }
 647
 648 static void
 649 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 650 {
 651         intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 652
 653         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 654                 nv50_display_vblank_crtc_handler(dev, 0);
 655
 656         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 657                 nv50_display_vblank_crtc_handler(dev, 1);
 658
 659         nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
 660                      NV50_PDISPLAY_INTR_EN) & ~intr);
 661         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
 662 }
 663
 664 static void
 665 nv50_display_unk10_handler(struct drm_device *dev)
 666 {
 667         struct drm_nouveau_private *dev_priv = dev->dev_private;
 668         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 669         int i, crtc, or, type = OUTPUT_ANY;
 670
 671         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 672         dev_priv->evo_irq.dcb = NULL;
 673
 674         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 675
 676         /* Determine which CRTC we're dealing with, only 1 ever will be
 677          * signalled at the same time with the current nouveau code.
 678          */
 679         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 680         if (crtc < 0)
 681                 goto ack;
 682
 683         /* Nothing needs to be done for the encoder */
 684         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 685         if (crtc < 0)
 686                 goto ack;
 687
 688         /* Find which encoder was connected to the CRTC */
 689         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 690                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 691                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 692                 if (!(mc & (1 << crtc)))
 693                         continue;
 694
 695                 switch ((mc & 0x00000f00) >> 8) {
 696                 case 0: type = OUTPUT_ANALOG; break;
 697                 case 1: type = OUTPUT_TV; break;
 698                 default:
 699                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 700                         goto ack;
 701                 }
 702
 703                 or = i;
 704         }
 705
 706         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 707                 if (dev_priv->chipset  < 0x90 ||
 708                     dev_priv->chipset == 0x92 ||
 709                     dev_priv->chipset == 0xa0)
 710                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 711                 else
 712                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 713
 714                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 715                 if (!(mc & (1 << crtc)))
 716                         continue;
 717
 718                 switch ((mc & 0x00000f00) >> 8) {
 719                 case 0: type = OUTPUT_LVDS; break;
 720                 case 1: type = OUTPUT_TMDS; break;
 721                 case 2: type = OUTPUT_TMDS; break;
 722                 case 5: type = OUTPUT_TMDS; break;
 723                 case 8: type = OUTPUT_DP; break;
 724                 case 9: type = OUTPUT_DP; break;
 725                 default:
 726                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 727                         goto ack;
 728                 }
 729
 730                 or = i;
 731         }
 732
 733         /* There was no encoder to disable */
 734         if (type == OUTPUT_ANY)
 735                 goto ack;
 736
 737         /* Disable the encoder */
 738         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 739                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 740
 741                 if (dcb->type == type && (dcb->or & (1 << or))) {
 742                         nouveau_bios_run_display_table(dev, dcb, 0, -1);
 743                         dev_priv->evo_irq.dcb = dcb;
 744                         goto ack;
 745                 }
 746         }
 747
 748         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 749 ack:
 750         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 751         nv_wr32(dev, 0x610030, 0x80000000);
 752 }
 753
 754 static void
 755 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
 756 {
 757         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 758         struct drm_encoder *encoder;
 759         uint32_t tmp, unk0 = 0, unk1 = 0;
 760
 761         if (dcb->type != OUTPUT_DP)
 762                 return;
 763
 764         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 765                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 766
 767                 if (nv_encoder->dcb == dcb) {
 768                         unk0 = nv_encoder->dp.unk0;
 769                         unk1 = nv_encoder->dp.unk1;
 770                         break;
 771                 }
 772         }
 773
 774         if (unk0 || unk1) {
 775                 tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 776                 tmp &= 0xfffffe03;
 777                 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
 778
 779                 tmp  = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
 780                 tmp &= 0xfef080c0;
 781                 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
 782         }
 783 }
 784
 785 static void
 786 nv50_display_unk20_handler(struct drm_device *dev)
 787 {
 788         struct drm_nouveau_private *dev_priv = dev->dev_private;
 789         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
 790         struct dcb_entry *dcb;
 791         int i, crtc, or, type = OUTPUT_ANY;
 792
 793         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 794         dcb = dev_priv->evo_irq.dcb;
 795         if (dcb) {
 796                 nouveau_bios_run_display_table(dev, dcb, 0, -2);
 797                 dev_priv->evo_irq.dcb = NULL;
 798         }
 799
 800         /* CRTC clock change requested? */
 801         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 802         if (crtc >= 0) {
 803                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 804                 pclk &= 0x003fffff;
 805
 806                 nv50_crtc_set_clock(dev, crtc, pclk);
 807
 808                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 809                 tmp &= ~0x000000f;
 810                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 811         }
 812
 813         /* Nothing needs to be done for the encoder */
 814         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 815         if (crtc < 0)
 816                 goto ack;
 817         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 818
 819         /* Find which encoder is connected to the CRTC */
 820         for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
 821                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 822                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 823                 if (!(mc & (1 << crtc)))
 824                         continue;
 825
 826                 switch ((mc & 0x00000f00) >> 8) {
 827                 case 0: type = OUTPUT_ANALOG; break;
 828                 case 1: type = OUTPUT_TV; break;
 829                 default:
 830                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 831                         goto ack;
 832                 }
 833
 834                 or = i;
 835         }
 836
 837         for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
 838                 if (dev_priv->chipset  < 0x90 ||
 839                     dev_priv->chipset == 0x92 ||
 840                     dev_priv->chipset == 0xa0)
 841                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 842                 else
 843                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 844
 845                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 846                 if (!(mc & (1 << crtc)))
 847                         continue;
 848
 849                 switch ((mc & 0x00000f00) >> 8) {
 850                 case 0: type = OUTPUT_LVDS; break;
 851                 case 1: type = OUTPUT_TMDS; break;
 852                 case 2: type = OUTPUT_TMDS; break;
 853                 case 5: type = OUTPUT_TMDS; break;
 854                 case 8: type = OUTPUT_DP; break;
 855                 case 9: type = OUTPUT_DP; break;
 856                 default:
 857                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 858                         goto ack;
 859                 }
 860
 861                 or = i;
 862         }
 863
 864         if (type == OUTPUT_ANY)
 865                 goto ack;
 866
 867         /* Enable the encoder */
 868         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 869                 dcb = &dev_priv->vbios.dcb.entry[i];
 870                 if (dcb->type == type && (dcb->or & (1 << or)))
 871                         break;
 872         }
 873
 874         if (i == dev_priv->vbios.dcb.entries) {
 875                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 876                 goto ack;
 877         }
 878
 879         script = nv50_display_script_select(dev, dcb, mc, pclk);
 880         nouveau_bios_run_display_table(dev, dcb, script, pclk);
 881
 882         nv50_display_unk20_dp_hack(dev, dcb);
 883
 884         if (dcb->type != OUTPUT_ANALOG) {
 885                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 886                 tmp &= ~0x00000f0f;
 887                 if (script & 0x0100)
 888                         tmp |= 0x00000101;
 889                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 890         } else {
 891                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 892         }
 893
 894         dev_priv->evo_irq.dcb = dcb;
 895         dev_priv->evo_irq.pclk = pclk;
 896         dev_priv->evo_irq.script = script;
 897
 898 ack:
 899         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 900         nv_wr32(dev, 0x610030, 0x80000000);
 901 }
 902
 903 /* If programming a TMDS output on a SOR that can also be configured for
 904  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 905  *
 906  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 907  * the VBIOS scripts on at least one board I have only switch it off on
 908  * link 0, causing a blank display if the output has previously been
 909  * programmed for DisplayPort.
 910  */
 911 static void
 912 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
 913 {
 914         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 915         struct drm_encoder *encoder;
 916         u32 tmp;
 917
 918         if (dcb->type != OUTPUT_TMDS)
 919                 return;
 920
 921         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 922                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 923
 924                 if (nv_encoder->dcb->type == OUTPUT_DP &&
 925                     nv_encoder->dcb->or & (1 << or)) {
 926                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 927                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 928                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 929                         break;
 930                 }
 931         }
 932 }
 933
 934 static void
 935 nv50_display_unk40_handler(struct drm_device *dev)
 936 {
 937         struct drm_nouveau_private *dev_priv = dev->dev_private;
 938         struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
 939         u16 script = dev_priv->evo_irq.script;
 940         u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
 941
 942         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 943         dev_priv->evo_irq.dcb = NULL;
 944         if (!dcb)
 945                 goto ack;
 946
 947         nouveau_bios_run_display_table(dev, dcb, script, -pclk);
 948         nv50_display_unk40_dp_set_tmds(dev, dcb);
 949
 950 ack:
 951         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 952         nv_wr32(dev, 0x610030, 0x80000000);
 953         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 954 }
 955
 956 void
 957 nv50_display_irq_handler_bh(struct work_struct *work)
 958 {
 959         struct drm_nouveau_private *dev_priv =
 960                 container_of(work, struct drm_nouveau_private, irq_work);
 961         struct drm_device *dev = dev_priv->dev;
 962
 963         for (;;) {
 964                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 965                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 966
 967                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 968
 969                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 970                         nv50_display_unk10_handler(dev);
 971                 else
 972                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 973                         nv50_display_unk20_handler(dev);
 974                 else
 975                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 976                         nv50_display_unk40_handler(dev);
 977                 else
 978                         break;
 979         }
 980
 981         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 982 }
 983
 984 static void
 985 nv50_display_error_handler(struct drm_device *dev)
 986 {
 987         uint32_t addr, data;
 988
 989         nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
 990         addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
 991         data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
 992
 993         NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
 994                  0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 995
 996         nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
 997 }
 998
 999 void
1000 nv50_display_irq_hotplug_bh(struct work_struct *work)
1001 {
1002         struct drm_nouveau_private *dev_priv =
1003                 container_of(work, struct drm_nouveau_private, hpd_work);
1004         struct drm_device *dev = dev_priv->dev;
1005         struct drm_connector *connector;
1006         const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1007         uint32_t unplug_mask, plug_mask, change_mask;
1008         uint32_t hpd0, hpd1 = 0;
1009
1010         hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1011         if (dev_priv->chipset >= 0x90)
1012                 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1013
1014         plug_mask   = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1015         unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1016         change_mask = plug_mask | unplug_mask;
1017
1018         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1019                 struct drm_encoder_helper_funcs *helper;
1020                 struct nouveau_connector *nv_connector =
1021                         nouveau_connector(connector);
1022                 struct nouveau_encoder *nv_encoder;
1023                 struct dcb_gpio_entry *gpio;
1024                 uint32_t reg;
1025                 bool plugged;
1026
1027                 if (!nv_connector->dcb)
1028                         continue;
1029
1030                 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1031                 if (!gpio || !(change_mask & (1 << gpio->line)))
1032                         continue;
1033
1034                 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1035                 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1036                 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1037                         drm_get_connector_name(connector)) ;
1038
1039                 if (!connector->encoder || !connector->encoder->crtc ||
1040                     !connector->encoder->crtc->enabled)
1041                         continue;
1042                 nv_encoder = nouveau_encoder(connector->encoder);
1043                 helper = connector->encoder->helper_private;
1044
1045                 if (nv_encoder->dcb->type != OUTPUT_DP)
1046                         continue;
1047
1048                 if (plugged)
1049                         helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1050                 else
1051                         helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1052         }
1053
1054         nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1055         if (dev_priv->chipset >= 0x90)
1056                 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
1057
1058         drm_helper_hpd_irq_event(dev);
1059 }
1060
1061 void
1062 nv50_display_irq_handler(struct drm_device *dev)
1063 {
1064         struct drm_nouveau_private *dev_priv = dev->dev_private;
1065         uint32_t delayed = 0;
1066
1067         if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1068                 if (!work_pending(&dev_priv->hpd_work))
1069                         queue_work(dev_priv->wq, &dev_priv->hpd_work);
1070         }
1071
1072         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1073                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1074                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1075                 uint32_t clock;
1076
1077                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
1078
1079                 if (!intr0 && !(intr1 & ~delayed))
1080                         break;
1081
1082                 if (intr0 & 0x00010000) {
1083                         nv50_display_error_handler(dev);
1084                         intr0 &= ~0x00010000;
1085                 }
1086
1087                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1088                         nv50_display_vblank_handler(dev, intr1);
1089                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1090                 }
1091
1092                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1093                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1094                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
1095                 if (clock) {
1096                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1097                         if (!work_pending(&dev_priv->irq_work))
1098                                 queue_work(dev_priv->wq, &dev_priv->irq_work);
1099                         delayed |= clock;
1100                         intr1 &= ~clock;
1101                 }
1102
1103                 if (intr0) {
1104                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1105                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1106                 }
1107
1108                 if (intr1) {
1109                         NV_ERROR(dev,
1110                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1111                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1112                 }
1113         }
1114 }
1115