drivers/gpu/drm/nouveau/nv04_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30
  31 #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
  32 #define NV04_RAMFC__SIZE 32
  33 #define NV04_RAMFC_DMA_PUT                                       0x00
  34 #define NV04_RAMFC_DMA_GET                                       0x04
  35 #define NV04_RAMFC_DMA_INSTANCE                                  0x08
  36 #define NV04_RAMFC_DMA_STATE                                     0x0C
  37 #define NV04_RAMFC_DMA_FETCH                                     0x10
  38 #define NV04_RAMFC_ENGINE                                        0x14
  39 #define NV04_RAMFC_PULL1_ENGINE                                  0x18
  40
  41 #define RAMFC_WR(offset, val) nv_wo32(dev, chan->ramfc->gpuobj, \
  42                                          NV04_RAMFC_##offset/4, (val))
  43 #define RAMFC_RD(offset)      nv_ro32(dev, chan->ramfc->gpuobj, \
  44                                          NV04_RAMFC_##offset/4)
  45
  46 void
  47 nv04_fifo_disable(struct drm_device *dev)
  48 {
  49         uint32_t tmp;
  50
  51         tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH);
  52         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, tmp & ~1);
  53         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
  54         tmp = nv_rd32(dev, NV03_PFIFO_CACHE1_PULL1);
  55         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, tmp & ~1);
  56 }
  57
  58 void
  59 nv04_fifo_enable(struct drm_device *dev)
  60 {
  61         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
  62         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
  63 }
  64
  65 bool
  66 nv04_fifo_reassign(struct drm_device *dev, bool enable)
  67 {
  68         uint32_t reassign = nv_rd32(dev, NV03_PFIFO_CACHES);
  69
  70         nv_wr32(dev, NV03_PFIFO_CACHES, enable ? 1 : 0);
  71         return (reassign == 1);
  72 }
  73
  74 bool
  75 nv04_fifo_cache_flush(struct drm_device *dev)
  76 {
  77         struct drm_nouveau_private *dev_priv = dev->dev_private;
  78         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  79         uint64_t start = ptimer->read(dev);
  80
  81         do {
  82                 if (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) ==
  83                     nv_rd32(dev, NV03_PFIFO_CACHE1_PUT))
  84                         return true;
  85
  86         } while (ptimer->read(dev) - start < 100000000);
  87
  88         NV_ERROR(dev, "Timeout flushing the PFIFO cache.\n");
  89
  90         return false;
  91 }
  92
  93 bool
  94 nv04_fifo_cache_pull(struct drm_device *dev, bool enable)
  95 {
  96         uint32_t pull = nv_rd32(dev, NV04_PFIFO_CACHE1_PULL0);
  97
  98         if (enable) {
  99                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull | 1);
 100         } else {
 101                 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, pull & ~1);
 102                 nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
 103         }
 104
 105         return !!(pull & 1);
 106 }
 107
 108 int
 109 nv04_fifo_channel_id(struct drm_device *dev)
 110 {
 111         return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
 112                         NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
 113 }
 114
 115 int
 116 nv04_fifo_create_context(struct nouveau_channel *chan)
 117 {
 118         struct drm_device *dev = chan->dev;
 119         struct drm_nouveau_private *dev_priv = dev->dev_private;
 120         int ret;
 121
 122         ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
 123                                                 NV04_RAMFC__SIZE,
 124                                                 NVOBJ_FLAG_ZERO_ALLOC |
 125                                                 NVOBJ_FLAG_ZERO_FREE,
 126                                                 NULL, &chan->ramfc);
 127         if (ret)
 128                 return ret;
 129
 130         /* Setup initial state */
 131         dev_priv->engine.instmem.prepare_access(dev, true);
 132         RAMFC_WR(DMA_PUT, chan->pushbuf_base);
 133         RAMFC_WR(DMA_GET, chan->pushbuf_base);
 134         RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4);
 135         RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 136                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 137                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
 138 #ifdef __BIG_ENDIAN
 139                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 140 #endif
 141                              0));
 142         dev_priv->engine.instmem.finish_access(dev);
 143
 144         /* enable the fifo dma operation */
 145         nv_wr32(dev, NV04_PFIFO_MODE,
 146                 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
 147         return 0;
 148 }
 149
 150 void
 151 nv04_fifo_destroy_context(struct nouveau_channel *chan)
 152 {
 153         struct drm_device *dev = chan->dev;
 154
 155         nv_wr32(dev, NV04_PFIFO_MODE,
 156                 nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
 157
 158         nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 159 }
 160
 161 static void
 162 nv04_fifo_do_load_context(struct drm_device *dev, int chid)
 163 {
 164         struct drm_nouveau_private *dev_priv = dev->dev_private;
 165         uint32_t fc = NV04_RAMFC(chid), tmp;
 166
 167         dev_priv->engine.instmem.prepare_access(dev, false);
 168
 169         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
 170         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
 171         tmp = nv_ri32(dev, fc + 8);
 172         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
 173         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
 174         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 12));
 175         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 16));
 176         nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 20));
 177         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 24));
 178
 179         dev_priv->engine.instmem.finish_access(dev);
 180
 181         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
 182         nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
 183 }
 184
 185 int
 186 nv04_fifo_load_context(struct nouveau_channel *chan)
 187 {
 188         uint32_t tmp;
 189
 190         nv_wr32(chan->dev, NV03_PFIFO_CACHE1_PUSH1,
 191                            NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 192         nv04_fifo_do_load_context(chan->dev, chan->id);
 193         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
 194
 195         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 196         tmp = nv_rd32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
 197         nv_wr32(chan->dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 198
 199         return 0;
 200 }
 201
 202 int
 203 nv04_fifo_unload_context(struct drm_device *dev)
 204 {
 205         struct drm_nouveau_private *dev_priv = dev->dev_private;
 206         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 207         struct nouveau_channel *chan = NULL;
 208         uint32_t tmp;
 209         int chid;
 210
 211         chid = pfifo->channel_id(dev);
 212         if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
 213                 return 0;
 214
 215         chan = dev_priv->fifos[chid];
 216         if (!chan) {
 217                 NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
 218                 return -EINVAL;
 219         }
 220
 221         dev_priv->engine.instmem.prepare_access(dev, true);
 222         RAMFC_WR(DMA_PUT, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
 223         RAMFC_WR(DMA_GET, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
 224         tmp  = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
 225         tmp |= nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE);
 226         RAMFC_WR(DMA_INSTANCE, tmp);
 227         RAMFC_WR(DMA_STATE, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
 228         RAMFC_WR(DMA_FETCH, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
 229         RAMFC_WR(ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
 230         RAMFC_WR(PULL1_ENGINE, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
 231         dev_priv->engine.instmem.finish_access(dev);
 232
 233         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 234         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 235         return 0;
 236 }
 237
 238 static void
 239 nv04_fifo_init_reset(struct drm_device *dev)
 240 {
 241         nv_wr32(dev, NV03_PMC_ENABLE,
 242                 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
 243         nv_wr32(dev, NV03_PMC_ENABLE,
 244                 nv_rd32(dev, NV03_PMC_ENABLE) |  NV_PMC_ENABLE_PFIFO);
 245
 246         nv_wr32(dev, 0x003224, 0x000f0078);
 247         nv_wr32(dev, 0x002044, 0x0101ffff);
 248         nv_wr32(dev, 0x002040, 0x000000ff);
 249         nv_wr32(dev, 0x002500, 0x00000000);
 250         nv_wr32(dev, 0x003000, 0x00000000);
 251         nv_wr32(dev, 0x003050, 0x00000000);
 252         nv_wr32(dev, 0x003200, 0x00000000);
 253         nv_wr32(dev, 0x003250, 0x00000000);
 254         nv_wr32(dev, 0x003220, 0x00000000);
 255
 256         nv_wr32(dev, 0x003250, 0x00000000);
 257         nv_wr32(dev, 0x003270, 0x00000000);
 258         nv_wr32(dev, 0x003210, 0x00000000);
 259 }
 260
 261 static void
 262 nv04_fifo_init_ramxx(struct drm_device *dev)
 263 {
 264         struct drm_nouveau_private *dev_priv = dev->dev_private;
 265
 266         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 267                                        ((dev_priv->ramht_bits - 9) << 16) |
 268                                        (dev_priv->ramht_offset >> 8));
 269         nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
 270         nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8);
 271 }
 272
 273 static void
 274 nv04_fifo_init_intr(struct drm_device *dev)
 275 {
 276         nv_wr32(dev, 0x002100, 0xffffffff);
 277         nv_wr32(dev, 0x002140, 0xffffffff);
 278 }
 279
 280 int
 281 nv04_fifo_init(struct drm_device *dev)
 282 {
 283         struct drm_nouveau_private *dev_priv = dev->dev_private;
 284         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 285         int i;
 286
 287         nv04_fifo_init_reset(dev);
 288         nv04_fifo_init_ramxx(dev);
 289
 290         nv04_fifo_do_load_context(dev, pfifo->channels - 1);
 291         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
 292
 293         nv04_fifo_init_intr(dev);
 294         pfifo->enable(dev);
 295
 296         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 297                 if (dev_priv->fifos[i]) {
 298                         uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
 299                         nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
 300                 }
 301         }
 302
 303         return 0;
 304 }
 305