drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include "drmP.h"
  31
  32 #include "nouveau_drm.h"
  33 #include "nouveau_drv.h"
  34 #include "nouveau_dma.h"
  35
  36 #include <linux/log2.h>
  37 #include <linux/slab.h>
  38
  39 static void
  40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  41 {
  42         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  43         struct drm_device *dev = dev_priv->dev;
  44         struct nouveau_bo *nvbo = nouveau_bo(bo);
  45
  46         if (unlikely(nvbo->gem))
  47                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
  48
  49         if (nvbo->tile)
  50                 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
  51
  52         kfree(nvbo);
  53 }
  54
  55 static void
  56 nouveau_bo_fixup_align(struct drm_device *dev,
  57                        uint32_t tile_mode, uint32_t tile_flags,
  58                        int *align, int *size)
  59 {
  60         struct drm_nouveau_private *dev_priv = dev->dev_private;
  61
  62         /*
  63          * Some of the tile_flags have a periodic structure of N*4096 bytes,
  64          * align to to that as well as the page size. Align the size to the
  65          * appropriate boundaries. This does imply that sizes are rounded up
  66          * 3-7 pages, so be aware of this and do not waste memory by allocating
  67          * many small buffers.
  68          */
  69         if (dev_priv->card_type == NV_50) {
  70                 uint32_t block_size = dev_priv->vram_size >> 15;
  71                 int i;
  72
  73                 switch (tile_flags) {
  74                 case 0x1800:
  75                 case 0x2800:
  76                 case 0x4800:
  77                 case 0x7a00:
  78                         if (is_power_of_2(block_size)) {
  79                                 for (i = 1; i < 10; i++) {
  80                                         *align = 12 * i * block_size;
  81                                         if (!(*align % 65536))
  82                                                 break;
  83                                 }
  84                         } else {
  85                                 for (i = 1; i < 10; i++) {
  86                                         *align = 8 * i * block_size;
  87                                         if (!(*align % 65536))
  88                                                 break;
  89                                 }
  90                         }
  91                         *size = roundup(*size, *align);
  92                         break;
  93                 default:
  94                         break;
  95                 }
  96
  97         } else {
  98                 if (tile_mode) {
  99                         if (dev_priv->chipset >= 0x40) {
 100                                 *align = 65536;
 101                                 *size = roundup(*size, 64 * tile_mode);
 102
 103                         } else if (dev_priv->chipset >= 0x30) {
 104                                 *align = 32768;
 105                                 *size = roundup(*size, 64 * tile_mode);
 106
 107                         } else if (dev_priv->chipset >= 0x20) {
 108                                 *align = 16384;
 109                                 *size = roundup(*size, 64 * tile_mode);
 110
 111                         } else if (dev_priv->chipset >= 0x10) {
 112                                 *align = 16384;
 113                                 *size = roundup(*size, 32 * tile_mode);
 114                         }
 115                 }
 116         }
 117
 118         /* ALIGN works only on powers of two. */
 119         *size = roundup(*size, PAGE_SIZE);
 120
 121         if (dev_priv->card_type == NV_50) {
 122                 *size = roundup(*size, 65536);
 123                 *align = max(65536, *align);
 124         }
 125 }
 126
 127 int
 128 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
 129                int size, int align, uint32_t flags, uint32_t tile_mode,
 130                uint32_t tile_flags, bool no_vm, bool mappable,
 131                struct nouveau_bo **pnvbo)
 132 {
 133         struct drm_nouveau_private *dev_priv = dev->dev_private;
 134         struct nouveau_bo *nvbo;
 135         int ret = 0;
 136
 137         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 138         if (!nvbo)
 139                 return -ENOMEM;
 140         INIT_LIST_HEAD(&nvbo->head);
 141         INIT_LIST_HEAD(&nvbo->entry);
 142         nvbo->mappable = mappable;
 143         nvbo->no_vm = no_vm;
 144         nvbo->tile_mode = tile_mode;
 145         nvbo->tile_flags = tile_flags;
 146
 147         nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
 148         align >>= PAGE_SHIFT;
 149
 150         nouveau_bo_placement_set(nvbo, flags, 0);
 151
 152         nvbo->channel = chan;
 153         ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
 154                           ttm_bo_type_device, &nvbo->placement, align, 0,
 155                           false, NULL, size, nouveau_bo_del_ttm);
 156         if (ret) {
 157                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 158                 return ret;
 159         }
 160         nvbo->channel = NULL;
 161
 162         *pnvbo = nvbo;
 163         return 0;
 164 }
 165
 166 static void
 167 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
 168 {
 169         *n = 0;
 170
 171         if (type & TTM_PL_FLAG_VRAM)
 172                 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
 173         if (type & TTM_PL_FLAG_TT)
 174                 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
 175         if (type & TTM_PL_FLAG_SYSTEM)
 176                 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
 177 }
 178
 179 void
 180 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 181 {
 182         struct ttm_placement *pl = &nvbo->placement;
 183         uint32_t flags = TTM_PL_MASK_CACHING |
 184                 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 185
 186         pl->placement = nvbo->placements;
 187         set_placement_list(nvbo->placements, &pl->num_placement,
 188                            type, flags);
 189
 190         pl->busy_placement = nvbo->busy_placements;
 191         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 192                            type | busy, flags);
 193 }
 194
 195 int
 196 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
 197 {
 198         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 199         struct ttm_buffer_object *bo = &nvbo->bo;
 200         int ret;
 201
 202         if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
 203                 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
 204                          "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
 205                          1 << bo->mem.mem_type, memtype);
 206                 return -EINVAL;
 207         }
 208
 209         if (nvbo->pin_refcnt++)
 210                 return 0;
 211
 212         ret = ttm_bo_reserve(bo, false, false, false, 0);
 213         if (ret)
 214                 goto out;
 215
 216         nouveau_bo_placement_set(nvbo, memtype, 0);
 217
 218         ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
 219         if (ret == 0) {
 220                 switch (bo->mem.mem_type) {
 221                 case TTM_PL_VRAM:
 222                         dev_priv->fb_aper_free -= bo->mem.size;
 223                         break;
 224                 case TTM_PL_TT:
 225                         dev_priv->gart_info.aper_free -= bo->mem.size;
 226                         break;
 227                 default:
 228                         break;
 229                 }
 230         }
 231         ttm_bo_unreserve(bo);
 232 out:
 233         if (unlikely(ret))
 234                 nvbo->pin_refcnt--;
 235         return ret;
 236 }
 237
 238 int
 239 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 240 {
 241         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 242         struct ttm_buffer_object *bo = &nvbo->bo;
 243         int ret;
 244
 245         if (--nvbo->pin_refcnt)
 246                 return 0;
 247
 248         ret = ttm_bo_reserve(bo, false, false, false, 0);
 249         if (ret)
 250                 return ret;
 251
 252         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 253
 254         ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
 255         if (ret == 0) {
 256                 switch (bo->mem.mem_type) {
 257                 case TTM_PL_VRAM:
 258                         dev_priv->fb_aper_free += bo->mem.size;
 259                         break;
 260                 case TTM_PL_TT:
 261                         dev_priv->gart_info.aper_free += bo->mem.size;
 262                         break;
 263                 default:
 264                         break;
 265                 }
 266         }
 267
 268         ttm_bo_unreserve(bo);
 269         return ret;
 270 }
 271
 272 int
 273 nouveau_bo_map(struct nouveau_bo *nvbo)
 274 {
 275         int ret;
 276
 277         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
 278         if (ret)
 279                 return ret;
 280
 281         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 282         ttm_bo_unreserve(&nvbo->bo);
 283         return ret;
 284 }
 285
 286 void
 287 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 288 {
 289         if (nvbo)
 290                 ttm_bo_kunmap(&nvbo->kmap);
 291 }
 292
 293 u16
 294 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
 295 {
 296         bool is_iomem;
 297         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 298         mem = &mem[index];
 299         if (is_iomem)
 300                 return ioread16_native((void __force __iomem *)mem);
 301         else
 302                 return *mem;
 303 }
 304
 305 void
 306 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 307 {
 308         bool is_iomem;
 309         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 310         mem = &mem[index];
 311         if (is_iomem)
 312                 iowrite16_native(val, (void __force __iomem *)mem);
 313         else
 314                 *mem = val;
 315 }
 316
 317 u32
 318 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 319 {
 320         bool is_iomem;
 321         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 322         mem = &mem[index];
 323         if (is_iomem)
 324                 return ioread32_native((void __force __iomem *)mem);
 325         else
 326                 return *mem;
 327 }
 328
 329 void
 330 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 331 {
 332         bool is_iomem;
 333         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 334         mem = &mem[index];
 335         if (is_iomem)
 336                 iowrite32_native(val, (void __force __iomem *)mem);
 337         else
 338                 *mem = val;
 339 }
 340
 341 static struct ttm_backend *
 342 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
 343 {
 344         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 345         struct drm_device *dev = dev_priv->dev;
 346
 347         switch (dev_priv->gart_info.type) {
 348 #if __OS_HAS_AGP
 349         case NOUVEAU_GART_AGP:
 350                 return ttm_agp_backend_init(bdev, dev->agp->bridge);
 351 #endif
 352         case NOUVEAU_GART_SGDMA:
 353                 return nouveau_sgdma_init_ttm(dev);
 354         default:
 355                 NV_ERROR(dev, "Unknown GART type %d\n",
 356                          dev_priv->gart_info.type);
 357                 break;
 358         }
 359
 360         return NULL;
 361 }
 362
 363 static int
 364 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 365 {
 366         /* We'll do this from user space. */
 367         return 0;
 368 }
 369
 370 static int
 371 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 372                          struct ttm_mem_type_manager *man)
 373 {
 374         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 375         struct drm_device *dev = dev_priv->dev;
 376
 377         switch (type) {
 378         case TTM_PL_SYSTEM:
 379                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 380                 man->available_caching = TTM_PL_MASK_CACHING;
 381                 man->default_caching = TTM_PL_FLAG_CACHED;
 382                 break;
 383         case TTM_PL_VRAM:
 384                 man->func = &ttm_bo_manager_func;
 385                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 386                              TTM_MEMTYPE_FLAG_MAPPABLE;
 387                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 388                                          TTM_PL_FLAG_WC;
 389                 man->default_caching = TTM_PL_FLAG_WC;
 390                 if (dev_priv->card_type == NV_50)
 391                         man->gpu_offset = 0x40000000;
 392                 else
 393                         man->gpu_offset = 0;
 394                 break;
 395         case TTM_PL_TT:
 396                 man->func = &ttm_bo_manager_func;
 397                 switch (dev_priv->gart_info.type) {
 398                 case NOUVEAU_GART_AGP:
 399                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 400                         man->available_caching = TTM_PL_FLAG_UNCACHED;
 401                         man->default_caching = TTM_PL_FLAG_UNCACHED;
 402                         break;
 403                 case NOUVEAU_GART_SGDMA:
 404                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 405                                      TTM_MEMTYPE_FLAG_CMA;
 406                         man->available_caching = TTM_PL_MASK_CACHING;
 407                         man->default_caching = TTM_PL_FLAG_CACHED;
 408                         break;
 409                 default:
 410                         NV_ERROR(dev, "Unknown GART type: %d\n",
 411                                  dev_priv->gart_info.type);
 412                         return -EINVAL;
 413                 }
 414                 man->gpu_offset = dev_priv->vm_gart_base;
 415                 break;
 416         default:
 417                 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
 418                 return -EINVAL;
 419         }
 420         return 0;
 421 }
 422
 423 static void
 424 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 425 {
 426         struct nouveau_bo *nvbo = nouveau_bo(bo);
 427
 428         switch (bo->mem.mem_type) {
 429         case TTM_PL_VRAM:
 430                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 431                                          TTM_PL_FLAG_SYSTEM);
 432                 break;
 433         default:
 434                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 435                 break;
 436         }
 437
 438         *pl = nvbo->placement;
 439 }
 440
 441
 442 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
 443  * TTM_PL_{VRAM,TT} directly.
 444  */
 445
 446 static int
 447 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
 448                               struct nouveau_bo *nvbo, bool evict,
 449                               bool no_wait_reserve, bool no_wait_gpu,
 450                               struct ttm_mem_reg *new_mem)
 451 {
 452         struct nouveau_fence *fence = NULL;
 453         int ret;
 454
 455         ret = nouveau_fence_new(chan, &fence, true);
 456         if (ret)
 457                 return ret;
 458
 459         if (nvbo->channel) {
 460                 ret = nouveau_fence_sync(fence, nvbo->channel);
 461                 if (ret)
 462                         goto out;
 463         }
 464
 465         ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
 466                                         no_wait_reserve, no_wait_gpu, new_mem);
 467 out:
 468         nouveau_fence_unref((void *)&fence);
 469         return ret;
 470 }
 471
 472 static inline uint32_t
 473 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 474                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 475 {
 476         struct nouveau_bo *nvbo = nouveau_bo(bo);
 477
 478         if (nvbo->no_vm) {
 479                 if (mem->mem_type == TTM_PL_TT)
 480                         return NvDmaGART;
 481                 return NvDmaVRAM;
 482         }
 483
 484         if (mem->mem_type == TTM_PL_TT)
 485                 return chan->gart_handle;
 486         return chan->vram_handle;
 487 }
 488
 489 static int
 490 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 491                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 492 {
 493         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 494         struct nouveau_bo *nvbo = nouveau_bo(bo);
 495         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 496         u64 src_offset, dst_offset;
 497         int ret;
 498
 499         src_offset = old_mem->start << PAGE_SHIFT;
 500         dst_offset = new_mem->start << PAGE_SHIFT;
 501         if (!nvbo->no_vm) {
 502                 if (old_mem->mem_type == TTM_PL_VRAM)
 503                         src_offset += dev_priv->vm_vram_base;
 504                 else
 505                         src_offset += dev_priv->vm_gart_base;
 506
 507                 if (new_mem->mem_type == TTM_PL_VRAM)
 508                         dst_offset += dev_priv->vm_vram_base;
 509                 else
 510                         dst_offset += dev_priv->vm_gart_base;
 511         }
 512
 513         ret = RING_SPACE(chan, 3);
 514         if (ret)
 515                 return ret;
 516
 517         BEGIN_RING(chan, NvSubM2MF, 0x0184, 2);
 518         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 519         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 520
 521         while (length) {
 522                 u32 amount, stride, height;
 523
 524                 amount  = min(length, (u64)(4 * 1024 * 1024));
 525                 stride  = 16 * 4;
 526                 height  = amount / stride;
 527
 528                 if (new_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) {
 529                         ret = RING_SPACE(chan, 8);
 530                         if (ret)
 531                                 return ret;
 532
 533                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
 534                         OUT_RING  (chan, 0);
 535                         OUT_RING  (chan, 0);
 536                         OUT_RING  (chan, stride);
 537                         OUT_RING  (chan, height);
 538                         OUT_RING  (chan, 1);
 539                         OUT_RING  (chan, 0);
 540                         OUT_RING  (chan, 0);
 541                 } else {
 542                         ret = RING_SPACE(chan, 2);
 543                         if (ret)
 544                                 return ret;
 545
 546                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
 547                         OUT_RING  (chan, 1);
 548                 }
 549                 if (old_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) {
 550                         ret = RING_SPACE(chan, 8);
 551                         if (ret)
 552                                 return ret;
 553
 554                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
 555                         OUT_RING  (chan, 0);
 556                         OUT_RING  (chan, 0);
 557                         OUT_RING  (chan, stride);
 558                         OUT_RING  (chan, height);
 559                         OUT_RING  (chan, 1);
 560                         OUT_RING  (chan, 0);
 561                         OUT_RING  (chan, 0);
 562                 } else {
 563                         ret = RING_SPACE(chan, 2);
 564                         if (ret)
 565                                 return ret;
 566
 567                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
 568                         OUT_RING  (chan, 1);
 569                 }
 570
 571                 ret = RING_SPACE(chan, 14);
 572                 if (ret)
 573                         return ret;
 574
 575                 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
 576                 OUT_RING  (chan, upper_32_bits(src_offset));
 577                 OUT_RING  (chan, upper_32_bits(dst_offset));
 578                 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
 579                 OUT_RING  (chan, lower_32_bits(src_offset));
 580                 OUT_RING  (chan, lower_32_bits(dst_offset));
 581                 OUT_RING  (chan, stride);
 582                 OUT_RING  (chan, stride);
 583                 OUT_RING  (chan, stride);
 584                 OUT_RING  (chan, height);
 585                 OUT_RING  (chan, 0x00000101);
 586                 OUT_RING  (chan, 0x00000000);
 587                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 588                 OUT_RING  (chan, 0);
 589
 590                 length -= amount;
 591                 src_offset += amount;
 592                 dst_offset += amount;
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int
 599 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 600                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 601 {
 602         u32 src_offset = old_mem->start << PAGE_SHIFT;
 603         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 604         u32 page_count = new_mem->num_pages;
 605         int ret;
 606
 607         ret = RING_SPACE(chan, 3);
 608         if (ret)
 609                 return ret;
 610
 611         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 612         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 613         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 614
 615         page_count = new_mem->num_pages;
 616         while (page_count) {
 617                 int line_count = (page_count > 2047) ? 2047 : page_count;
 618
 619                 ret = RING_SPACE(chan, 11);
 620                 if (ret)
 621                         return ret;
 622
 623                 BEGIN_RING(chan, NvSubM2MF,
 624                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 625                 OUT_RING  (chan, src_offset);
 626                 OUT_RING  (chan, dst_offset);
 627                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 628                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 629                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 630                 OUT_RING  (chan, line_count);
 631                 OUT_RING  (chan, 0x00000101);
 632                 OUT_RING  (chan, 0x00000000);
 633                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 634                 OUT_RING  (chan, 0);
 635
 636                 page_count -= line_count;
 637                 src_offset += (PAGE_SIZE * line_count);
 638                 dst_offset += (PAGE_SIZE * line_count);
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int
 645 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 646                      bool no_wait_reserve, bool no_wait_gpu,
 647                      struct ttm_mem_reg *new_mem)
 648 {
 649         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 650         struct nouveau_bo *nvbo = nouveau_bo(bo);
 651         struct nouveau_channel *chan;
 652         int ret;
 653
 654         chan = nvbo->channel;
 655         if (!chan || nvbo->no_vm)
 656                 chan = dev_priv->channel;
 657
 658         if (dev_priv->card_type < NV_50)
 659                 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 660         else
 661                 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 662         if (ret)
 663                 return ret;
 664
 665         return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 666 }
 667
 668 static int
 669 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 670                       bool no_wait_reserve, bool no_wait_gpu,
 671                       struct ttm_mem_reg *new_mem)
 672 {
 673         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 674         struct ttm_placement placement;
 675         struct ttm_mem_reg tmp_mem;
 676         int ret;
 677
 678         placement.fpfn = placement.lpfn = 0;
 679         placement.num_placement = placement.num_busy_placement = 1;
 680         placement.placement = placement.busy_placement = &placement_memtype;
 681
 682         tmp_mem = *new_mem;
 683         tmp_mem.mm_node = NULL;
 684         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 685         if (ret)
 686                 return ret;
 687
 688         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
 689         if (ret)
 690                 goto out;
 691
 692         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
 693         if (ret)
 694                 goto out;
 695
 696         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 697 out:
 698         ttm_bo_mem_put(bo, &tmp_mem);
 699         return ret;
 700 }
 701
 702 static int
 703 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 704                       bool no_wait_reserve, bool no_wait_gpu,
 705                       struct ttm_mem_reg *new_mem)
 706 {
 707         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 708         struct ttm_placement placement;
 709         struct ttm_mem_reg tmp_mem;
 710         int ret;
 711
 712         placement.fpfn = placement.lpfn = 0;
 713         placement.num_placement = placement.num_busy_placement = 1;
 714         placement.placement = placement.busy_placement = &placement_memtype;
 715
 716         tmp_mem = *new_mem;
 717         tmp_mem.mm_node = NULL;
 718         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 719         if (ret)
 720                 return ret;
 721
 722         ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
 723         if (ret)
 724                 goto out;
 725
 726         ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 727         if (ret)
 728                 goto out;
 729
 730 out:
 731         ttm_bo_mem_put(bo, &tmp_mem);
 732         return ret;
 733 }
 734
 735 static int
 736 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
 737                    struct nouveau_tile_reg **new_tile)
 738 {
 739         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 740         struct drm_device *dev = dev_priv->dev;
 741         struct nouveau_bo *nvbo = nouveau_bo(bo);
 742         uint64_t offset;
 743         int ret;
 744
 745         if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
 746                 /* Nothing to do. */
 747                 *new_tile = NULL;
 748                 return 0;
 749         }
 750
 751         offset = new_mem->start << PAGE_SHIFT;
 752
 753         if (dev_priv->card_type == NV_50) {
 754                 ret = nv50_mem_vm_bind_linear(dev,
 755                                               offset + dev_priv->vm_vram_base,
 756                                               new_mem->size, nvbo->tile_flags,
 757                                               offset);
 758                 if (ret)
 759                         return ret;
 760
 761         } else if (dev_priv->card_type >= NV_10) {
 762                 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
 763                                                 nvbo->tile_mode);
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void
 770 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
 771                       struct nouveau_tile_reg *new_tile,
 772                       struct nouveau_tile_reg **old_tile)
 773 {
 774         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 775         struct drm_device *dev = dev_priv->dev;
 776
 777         if (dev_priv->card_type >= NV_10 &&
 778             dev_priv->card_type < NV_50) {
 779                 if (*old_tile)
 780                         nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
 781
 782                 *old_tile = new_tile;
 783         }
 784 }
 785
 786 static int
 787 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
 788                 bool no_wait_reserve, bool no_wait_gpu,
 789                 struct ttm_mem_reg *new_mem)
 790 {
 791         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 792         struct nouveau_bo *nvbo = nouveau_bo(bo);
 793         struct ttm_mem_reg *old_mem = &bo->mem;
 794         struct nouveau_tile_reg *new_tile = NULL;
 795         int ret = 0;
 796
 797         ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
 798         if (ret)
 799                 return ret;
 800
 801         /* Fake bo copy. */
 802         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
 803                 BUG_ON(bo->mem.mm_node != NULL);
 804                 bo->mem = *new_mem;
 805                 new_mem->mm_node = NULL;
 806                 goto out;
 807         }
 808
 809         /* Software copy if the card isn't up and running yet. */
 810         if (!dev_priv->channel) {
 811                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 812                 goto out;
 813         }
 814
 815         /* Hardware assisted copy. */
 816         if (new_mem->mem_type == TTM_PL_SYSTEM)
 817                 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 818         else if (old_mem->mem_type == TTM_PL_SYSTEM)
 819                 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 820         else
 821                 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 822
 823         if (!ret)
 824                 goto out;
 825
 826         /* Fallback to software copy. */
 827         ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 828
 829 out:
 830         if (ret)
 831                 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
 832         else
 833                 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
 834
 835         return ret;
 836 }
 837
 838 static int
 839 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 840 {
 841         return 0;
 842 }
 843
 844 static int
 845 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 846 {
 847         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 848         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 849         struct drm_device *dev = dev_priv->dev;
 850
 851         mem->bus.addr = NULL;
 852         mem->bus.offset = 0;
 853         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 854         mem->bus.base = 0;
 855         mem->bus.is_iomem = false;
 856         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 857                 return -EINVAL;
 858         switch (mem->mem_type) {
 859         case TTM_PL_SYSTEM:
 860                 /* System memory */
 861                 return 0;
 862         case TTM_PL_TT:
 863 #if __OS_HAS_AGP
 864                 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
 865                         mem->bus.offset = mem->start << PAGE_SHIFT;
 866                         mem->bus.base = dev_priv->gart_info.aper_base;
 867                         mem->bus.is_iomem = true;
 868                 }
 869 #endif
 870                 break;
 871         case TTM_PL_VRAM:
 872                 mem->bus.offset = mem->start << PAGE_SHIFT;
 873                 mem->bus.base = pci_resource_start(dev->pdev, 1);
 874                 mem->bus.is_iomem = true;
 875                 break;
 876         default:
 877                 return -EINVAL;
 878         }
 879         return 0;
 880 }
 881
 882 static void
 883 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 884 {
 885 }
 886
 887 static int
 888 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
 889 {
 890         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 891         struct nouveau_bo *nvbo = nouveau_bo(bo);
 892
 893         /* as long as the bo isn't in vram, and isn't tiled, we've got
 894          * nothing to do here.
 895          */
 896         if (bo->mem.mem_type != TTM_PL_VRAM) {
 897                 if (dev_priv->card_type < NV_50 || !nvbo->tile_flags)
 898                         return 0;
 899         }
 900
 901         /* make sure bo is in mappable vram */
 902         if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
 903                 return 0;
 904
 905
 906         nvbo->placement.fpfn = 0;
 907         nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
 908         nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
 909         return ttm_bo_validate(bo, &nvbo->placement, false, true, false);
 910 }
 911
 912 struct ttm_bo_driver nouveau_bo_driver = {
 913         .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
 914         .invalidate_caches = nouveau_bo_invalidate_caches,
 915         .init_mem_type = nouveau_bo_init_mem_type,
 916         .evict_flags = nouveau_bo_evict_flags,
 917         .move = nouveau_bo_move,
 918         .verify_access = nouveau_bo_verify_access,
 919         .sync_obj_signaled = nouveau_fence_signalled,
 920         .sync_obj_wait = nouveau_fence_wait,
 921         .sync_obj_flush = nouveau_fence_flush,
 922         .sync_obj_unref = nouveau_fence_unref,
 923         .sync_obj_ref = nouveau_fence_ref,
 924         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
 925         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
 926         .io_mem_free = &nouveau_ttm_io_mem_free,
 927 };
 928