drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/kernel.h>
  29 #include "drmP.h"
  30 #include "intel_drv.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "intel_dp.h"
  34
  35 #include "drm_crtc_helper.h"
  36
  37 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  38 static void intel_update_watermarks(struct drm_device *dev);
  39
  40 typedef struct {
  41     /* given values */
  42     int n;
  43     int m1, m2;
  44     int p1, p2;
  45     /* derived values */
  46     int dot;
  47     int vco;
  48     int m;
  49     int p;
  50 } intel_clock_t;
  51
  52 typedef struct {
  53     int min, max;
  54 } intel_range_t;
  55
  56 typedef struct {
  57     int dot_limit;
  58     int p2_slow, p2_fast;
  59 } intel_p2_t;
  60
  61 #define INTEL_P2_NUM                  2
  62 typedef struct intel_limit intel_limit_t;
  63 struct intel_limit {
  64     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  65     intel_p2_t      p2;
  66     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  67                       int, int, intel_clock_t *);
  68 };
  69
  70 #define I8XX_DOT_MIN              25000
  71 #define I8XX_DOT_MAX             350000
  72 #define I8XX_VCO_MIN             930000
  73 #define I8XX_VCO_MAX            1400000
  74 #define I8XX_N_MIN                    3
  75 #define I8XX_N_MAX                   16
  76 #define I8XX_M_MIN                   96
  77 #define I8XX_M_MAX                  140
  78 #define I8XX_M1_MIN                  18
  79 #define I8XX_M1_MAX                  26
  80 #define I8XX_M2_MIN                   6
  81 #define I8XX_M2_MAX                  16
  82 #define I8XX_P_MIN                    4
  83 #define I8XX_P_MAX                  128
  84 #define I8XX_P1_MIN                   2
  85 #define I8XX_P1_MAX                  33
  86 #define I8XX_P1_LVDS_MIN              1
  87 #define I8XX_P1_LVDS_MAX              6
  88 #define I8XX_P2_SLOW                  4
  89 #define I8XX_P2_FAST                  2
  90 #define I8XX_P2_LVDS_SLOW             14
  91 #define I8XX_P2_LVDS_FAST             14 /* No fast option */
  92 #define I8XX_P2_SLOW_LIMIT       165000
  93
  94 #define I9XX_DOT_MIN              20000
  95 #define I9XX_DOT_MAX             400000
  96 #define I9XX_VCO_MIN            1400000
  97 #define I9XX_VCO_MAX            2800000
  98 #define IGD_VCO_MIN             1700000
  99 #define IGD_VCO_MAX             3500000
 100 #define I9XX_N_MIN                    1
 101 #define I9XX_N_MAX                    6
 102 /* IGD's Ncounter is a ring counter */
 103 #define IGD_N_MIN                     3
 104 #define IGD_N_MAX                     6
 105 #define I9XX_M_MIN                   70
 106 #define I9XX_M_MAX                  120
 107 #define IGD_M_MIN                     2
 108 #define IGD_M_MAX                   256
 109 #define I9XX_M1_MIN                  10
 110 #define I9XX_M1_MAX                  22
 111 #define I9XX_M2_MIN                   5
 112 #define I9XX_M2_MAX                   9
 113 /* IGD M1 is reserved, and must be 0 */
 114 #define IGD_M1_MIN                    0
 115 #define IGD_M1_MAX                    0
 116 #define IGD_M2_MIN                    0
 117 #define IGD_M2_MAX                    254
 118 #define I9XX_P_SDVO_DAC_MIN           5
 119 #define I9XX_P_SDVO_DAC_MAX          80
 120 #define I9XX_P_LVDS_MIN               7
 121 #define I9XX_P_LVDS_MAX              98
 122 #define IGD_P_LVDS_MIN                7
 123 #define IGD_P_LVDS_MAX               112
 124 #define I9XX_P1_MIN                   1
 125 #define I9XX_P1_MAX                   8
 126 #define I9XX_P2_SDVO_DAC_SLOW                10
 127 #define I9XX_P2_SDVO_DAC_FAST                 5
 128 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 129 #define I9XX_P2_LVDS_SLOW                    14
 130 #define I9XX_P2_LVDS_FAST                     7
 131 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 132
 133 /*The parameter is for SDVO on G4x platform*/
 134 #define G4X_DOT_SDVO_MIN           25000
 135 #define G4X_DOT_SDVO_MAX           270000
 136 #define G4X_VCO_MIN                1750000
 137 #define G4X_VCO_MAX                3500000
 138 #define G4X_N_SDVO_MIN             1
 139 #define G4X_N_SDVO_MAX             4
 140 #define G4X_M_SDVO_MIN             104
 141 #define G4X_M_SDVO_MAX             138
 142 #define G4X_M1_SDVO_MIN            17
 143 #define G4X_M1_SDVO_MAX            23
 144 #define G4X_M2_SDVO_MIN            5
 145 #define G4X_M2_SDVO_MAX            11
 146 #define G4X_P_SDVO_MIN             10
 147 #define G4X_P_SDVO_MAX             30
 148 #define G4X_P1_SDVO_MIN            1
 149 #define G4X_P1_SDVO_MAX            3
 150 #define G4X_P2_SDVO_SLOW           10
 151 #define G4X_P2_SDVO_FAST           10
 152 #define G4X_P2_SDVO_LIMIT          270000
 153
 154 /*The parameter is for HDMI_DAC on G4x platform*/
 155 #define G4X_DOT_HDMI_DAC_MIN           22000
 156 #define G4X_DOT_HDMI_DAC_MAX           400000
 157 #define G4X_N_HDMI_DAC_MIN             1
 158 #define G4X_N_HDMI_DAC_MAX             4
 159 #define G4X_M_HDMI_DAC_MIN             104
 160 #define G4X_M_HDMI_DAC_MAX             138
 161 #define G4X_M1_HDMI_DAC_MIN            16
 162 #define G4X_M1_HDMI_DAC_MAX            23
 163 #define G4X_M2_HDMI_DAC_MIN            5
 164 #define G4X_M2_HDMI_DAC_MAX            11
 165 #define G4X_P_HDMI_DAC_MIN             5
 166 #define G4X_P_HDMI_DAC_MAX             80
 167 #define G4X_P1_HDMI_DAC_MIN            1
 168 #define G4X_P1_HDMI_DAC_MAX            8
 169 #define G4X_P2_HDMI_DAC_SLOW           10
 170 #define G4X_P2_HDMI_DAC_FAST           5
 171 #define G4X_P2_HDMI_DAC_LIMIT          165000
 172
 173 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 174 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 175 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 176 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 177 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 178 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 179 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 180 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 181 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 182 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 183 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 184 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 185 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 186 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 187 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 188 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 189 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 190 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 191
 192 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 193 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 194 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 195 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 196 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 197 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 198 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 199 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 200 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 201 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 202 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 203 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 204 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 205 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 206 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 207 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 208 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 209 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 210
 211 /*The parameter is for DISPLAY PORT on G4x platform*/
 212 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 213 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 214 #define G4X_N_DISPLAY_PORT_MIN             1
 215 #define G4X_N_DISPLAY_PORT_MAX             2
 216 #define G4X_M_DISPLAY_PORT_MIN             97
 217 #define G4X_M_DISPLAY_PORT_MAX             108
 218 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 219 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 220 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 221 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 222 #define G4X_P_DISPLAY_PORT_MIN             10
 223 #define G4X_P_DISPLAY_PORT_MAX             20
 224 #define G4X_P1_DISPLAY_PORT_MIN            1
 225 #define G4X_P1_DISPLAY_PORT_MAX            2
 226 #define G4X_P2_DISPLAY_PORT_SLOW           10
 227 #define G4X_P2_DISPLAY_PORT_FAST           10
 228 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 229
 230 /* IGDNG */
 231 /* as we calculate clock using (register_value + 2) for
 232    N/M1/M2, so here the range value for them is (actual_value-2).
 233  */
 234 #define IGDNG_DOT_MIN         25000
 235 #define IGDNG_DOT_MAX         350000
 236 #define IGDNG_VCO_MIN         1760000
 237 #define IGDNG_VCO_MAX         3510000
 238 #define IGDNG_N_MIN           1
 239 #define IGDNG_N_MAX           5
 240 #define IGDNG_M_MIN           79
 241 #define IGDNG_M_MAX           118
 242 #define IGDNG_M1_MIN          12
 243 #define IGDNG_M1_MAX          23
 244 #define IGDNG_M2_MIN          5
 245 #define IGDNG_M2_MAX          9
 246 #define IGDNG_P_SDVO_DAC_MIN  5
 247 #define IGDNG_P_SDVO_DAC_MAX  80
 248 #define IGDNG_P_LVDS_MIN      28
 249 #define IGDNG_P_LVDS_MAX      112
 250 #define IGDNG_P1_MIN          1
 251 #define IGDNG_P1_MAX          8
 252 #define IGDNG_P2_SDVO_DAC_SLOW 10
 253 #define IGDNG_P2_SDVO_DAC_FAST 5
 254 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 255 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 256 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 257
 258 static bool
 259 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 260                     int target, int refclk, intel_clock_t *best_clock);
 261 static bool
 262 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 263                         int target, int refclk, intel_clock_t *best_clock);
 264 static bool
 265 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 266                         int target, int refclk, intel_clock_t *best_clock);
 267
 268 static bool
 269 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 270                       int target, int refclk, intel_clock_t *best_clock);
 271
 272 static const intel_limit_t intel_limits_i8xx_dvo = {
 273         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 274         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 275         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 276         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 277         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 278         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 279         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 280         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 281         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 282                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 283         .find_pll = intel_find_best_PLL,
 284 };
 285
 286 static const intel_limit_t intel_limits_i8xx_lvds = {
 287         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 288         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 289         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 290         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 291         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 292         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 293         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 294         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 295         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 296                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 297         .find_pll = intel_find_best_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i9xx_sdvo = {
 301         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 302         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 303         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 304         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 305         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 306         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 307         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 308         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 309         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 310                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 311         .find_pll = intel_find_best_PLL,
 312 };
 313
 314 static const intel_limit_t intel_limits_i9xx_lvds = {
 315         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 316         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 317         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 318         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 319         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 320         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 321         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 322         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 323         /* The single-channel range is 25-112Mhz, and dual-channel
 324          * is 80-224Mhz.  Prefer single channel as much as possible.
 325          */
 326         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 327                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 328         .find_pll = intel_find_best_PLL,
 329 };
 330
 331     /* below parameter and function is for G4X Chipset Family*/
 332 static const intel_limit_t intel_limits_g4x_sdvo = {
 333         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 334         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 335         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 336         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 337         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 338         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 339         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 340         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 341         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 342                  .p2_slow = G4X_P2_SDVO_SLOW,
 343                  .p2_fast = G4X_P2_SDVO_FAST
 344         },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 static const intel_limit_t intel_limits_g4x_hdmi = {
 349         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 350         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 351         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 352         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 353         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 354         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 355         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 356         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 357         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 358                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 359                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 360         },
 361         .find_pll = intel_g4x_find_best_PLL,
 362 };
 363
 364 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 365         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 366                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 367         .vco = { .min = G4X_VCO_MIN,
 368                  .max = G4X_VCO_MAX },
 369         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 370                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 371         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 372                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 373         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 374                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 375         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 376                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 377         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 378                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 379         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 380                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 381         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 382                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 383                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 384         },
 385         .find_pll = intel_g4x_find_best_PLL,
 386 };
 387
 388 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 389         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 390                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 391         .vco = { .min = G4X_VCO_MIN,
 392                  .max = G4X_VCO_MAX },
 393         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 394                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 395         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 396                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 397         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 398                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 399         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 400                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 401         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 402                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 403         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 404                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 405         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 406                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 407                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 408         },
 409         .find_pll = intel_g4x_find_best_PLL,
 410 };
 411
 412 static const intel_limit_t intel_limits_g4x_display_port = {
 413         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 414                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 415         .vco = { .min = G4X_VCO_MIN,
 416                  .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 418                  .max = G4X_N_DISPLAY_PORT_MAX },
 419         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 420                  .max = G4X_M_DISPLAY_PORT_MAX },
 421         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 422                  .max = G4X_M1_DISPLAY_PORT_MAX },
 423         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 424                  .max = G4X_M2_DISPLAY_PORT_MAX },
 425         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 426                  .max = G4X_P_DISPLAY_PORT_MAX },
 427         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 428                  .max = G4X_P1_DISPLAY_PORT_MAX},
 429         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 430                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 431                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 432         .find_pll = intel_find_pll_g4x_dp,
 433 };
 434
 435 static const intel_limit_t intel_limits_igd_sdvo = {
 436         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 437         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 438         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 439         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 440         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 441         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 442         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 443         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 444         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 445                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 446         .find_pll = intel_find_best_PLL,
 447 };
 448
 449 static const intel_limit_t intel_limits_igd_lvds = {
 450         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 451         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 452         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 453         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 454         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 455         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 456         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 457         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 458         /* IGD only supports single-channel mode. */
 459         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 460                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 461         .find_pll = intel_find_best_PLL,
 462 };
 463
 464 static const intel_limit_t intel_limits_igdng_sdvo = {
 465         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 466         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 467         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 468         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 469         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 470         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 471         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 472         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 473         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 474                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 475                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 476         .find_pll = intel_igdng_find_best_PLL,
 477 };
 478
 479 static const intel_limit_t intel_limits_igdng_lvds = {
 480         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 481         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 482         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 483         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 484         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 485         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 486         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 487         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 488         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 489                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 490                  .p2_fast = IGDNG_P2_LVDS_FAST },
 491         .find_pll = intel_igdng_find_best_PLL,
 492 };
 493
 494 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 495 {
 496         const intel_limit_t *limit;
 497         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 498                 limit = &intel_limits_igdng_lvds;
 499         else
 500                 limit = &intel_limits_igdng_sdvo;
 501
 502         return limit;
 503 }
 504
 505 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 506 {
 507         struct drm_device *dev = crtc->dev;
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         const intel_limit_t *limit;
 510
 511         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 512                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 513                     LVDS_CLKB_POWER_UP)
 514                         /* LVDS with dual channel */
 515                         limit = &intel_limits_g4x_dual_channel_lvds;
 516                 else
 517                         /* LVDS with dual channel */
 518                         limit = &intel_limits_g4x_single_channel_lvds;
 519         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 520                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 521                 limit = &intel_limits_g4x_hdmi;
 522         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 523                 limit = &intel_limits_g4x_sdvo;
 524         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 525                 limit = &intel_limits_g4x_display_port;
 526         } else /* The option is for other outputs */
 527                 limit = &intel_limits_i9xx_sdvo;
 528
 529         return limit;
 530 }
 531
 532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 533 {
 534         struct drm_device *dev = crtc->dev;
 535         const intel_limit_t *limit;
 536
 537         if (IS_IGDNG(dev))
 538                 limit = intel_igdng_limit(crtc);
 539         else if (IS_G4X(dev)) {
 540                 limit = intel_g4x_limit(crtc);
 541         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 542                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 543                         limit = &intel_limits_i9xx_lvds;
 544                 else
 545                         limit = &intel_limits_i9xx_sdvo;
 546         } else if (IS_IGD(dev)) {
 547                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 548                         limit = &intel_limits_igd_lvds;
 549                 else
 550                         limit = &intel_limits_igd_sdvo;
 551         } else {
 552                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 553                         limit = &intel_limits_i8xx_lvds;
 554                 else
 555                         limit = &intel_limits_i8xx_dvo;
 556         }
 557         return limit;
 558 }
 559
 560 /* m1 is reserved as 0 in IGD, n is a ring counter */
 561 static void igd_clock(int refclk, intel_clock_t *clock)
 562 {
 563         clock->m = clock->m2 + 2;
 564         clock->p = clock->p1 * clock->p2;
 565         clock->vco = refclk * clock->m / clock->n;
 566         clock->dot = clock->vco / clock->p;
 567 }
 568
 569 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 570 {
 571         if (IS_IGD(dev)) {
 572                 igd_clock(refclk, clock);
 573                 return;
 574         }
 575         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 576         clock->p = clock->p1 * clock->p2;
 577         clock->vco = refclk * clock->m / (clock->n + 2);
 578         clock->dot = clock->vco / clock->p;
 579 }
 580
 581 /**
 582  * Returns whether any output on the specified pipe is of the specified type
 583  */
 584 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 585 {
 586     struct drm_device *dev = crtc->dev;
 587     struct drm_mode_config *mode_config = &dev->mode_config;
 588     struct drm_connector *l_entry;
 589
 590     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 591             if (l_entry->encoder &&
 592                 l_entry->encoder->crtc == crtc) {
 593                     struct intel_output *intel_output = to_intel_output(l_entry);
 594                     if (intel_output->type == type)
 595                             return true;
 596             }
 597     }
 598     return false;
 599 }
 600
 601 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 602 /**
 603  * Returns whether the given set of divisors are valid for a given refclk with
 604  * the given connectors.
 605  */
 606
 607 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 608 {
 609         const intel_limit_t *limit = intel_limit (crtc);
 610         struct drm_device *dev = crtc->dev;
 611
 612         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 613                 INTELPllInvalid ("p1 out of range\n");
 614         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 615                 INTELPllInvalid ("p out of range\n");
 616         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 617                 INTELPllInvalid ("m2 out of range\n");
 618         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 619                 INTELPllInvalid ("m1 out of range\n");
 620         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 621                 INTELPllInvalid ("m1 <= m2\n");
 622         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 623                 INTELPllInvalid ("m out of range\n");
 624         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 625                 INTELPllInvalid ("n out of range\n");
 626         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 627                 INTELPllInvalid ("vco out of range\n");
 628         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 629          * connector, etc., rather than just a single range.
 630          */
 631         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 632                 INTELPllInvalid ("dot out of range\n");
 633
 634         return true;
 635 }
 636
 637 static bool
 638 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 639                     int target, int refclk, intel_clock_t *best_clock)
 640
 641 {
 642         struct drm_device *dev = crtc->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         intel_clock_t clock;
 645         int err = target;
 646
 647         if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 648             (I915_READ(LVDS)) != 0) {
 649                 /*
 650                  * For LVDS, if the panel is on, just rely on its current
 651                  * settings for dual-channel.  We haven't figured out how to
 652                  * reliably set up different single/dual channel state, if we
 653                  * even can.
 654                  */
 655                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 656                     LVDS_CLKB_POWER_UP)
 657                         clock.p2 = limit->p2.p2_fast;
 658                 else
 659                         clock.p2 = limit->p2.p2_slow;
 660         } else {
 661                 if (target < limit->p2.dot_limit)
 662                         clock.p2 = limit->p2.p2_slow;
 663                 else
 664                         clock.p2 = limit->p2.p2_fast;
 665         }
 666
 667         memset (best_clock, 0, sizeof (*best_clock));
 668
 669         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 670                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 671                         /* m1 is always 0 in IGD */
 672                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 673                                 break;
 674                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 675                              clock.n++) {
 676                                 for (clock.p1 = limit->p1.min;
 677                                      clock.p1 <= limit->p1.max; clock.p1++) {
 678                                         int this_err;
 679
 680                                         intel_clock(dev, refclk, &clock);
 681
 682                                         if (!intel_PLL_is_valid(crtc, &clock))
 683                                                 continue;
 684
 685                                         this_err = abs(clock.dot - target);
 686                                         if (this_err < err) {
 687                                                 *best_clock = clock;
 688                                                 err = this_err;
 689                                         }
 690                                 }
 691                         }
 692                 }
 693         }
 694
 695         return (err != target);
 696 }
 697
 698 static bool
 699 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 700                         int target, int refclk, intel_clock_t *best_clock)
 701 {
 702         struct drm_device *dev = crtc->dev;
 703         struct drm_i915_private *dev_priv = dev->dev_private;
 704         intel_clock_t clock;
 705         int max_n;
 706         bool found;
 707         /* approximately equals target * 0.00488 */
 708         int err_most = (target >> 8) + (target >> 10);
 709         found = false;
 710
 711         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 712                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 713                     LVDS_CLKB_POWER_UP)
 714                         clock.p2 = limit->p2.p2_fast;
 715                 else
 716                         clock.p2 = limit->p2.p2_slow;
 717         } else {
 718                 if (target < limit->p2.dot_limit)
 719                         clock.p2 = limit->p2.p2_slow;
 720                 else
 721                         clock.p2 = limit->p2.p2_fast;
 722         }
 723
 724         memset(best_clock, 0, sizeof(*best_clock));
 725         max_n = limit->n.max;
 726         /* based on hardware requriment prefer smaller n to precision */
 727         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 728                 /* based on hardware requirment prefere larger m1,m2, p1 */
 729                 for (clock.m1 = limit->m1.max;
 730                      clock.m1 >= limit->m1.min; clock.m1--) {
 731                         for (clock.m2 = limit->m2.max;
 732                              clock.m2 >= limit->m2.min; clock.m2--) {
 733                                 for (clock.p1 = limit->p1.max;
 734                                      clock.p1 >= limit->p1.min; clock.p1--) {
 735                                         int this_err;
 736
 737                                         intel_clock(dev, refclk, &clock);
 738                                         if (!intel_PLL_is_valid(crtc, &clock))
 739                                                 continue;
 740                                         this_err = abs(clock.dot - target) ;
 741                                         if (this_err < err_most) {
 742                                                 *best_clock = clock;
 743                                                 err_most = this_err;
 744                                                 max_n = clock.n;
 745                                                 found = true;
 746                                         }
 747                                 }
 748                         }
 749                 }
 750         }
 751         return found;
 752 }
 753
 754 static bool
 755 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 756                         int target, int refclk, intel_clock_t *best_clock)
 757 {
 758         struct drm_device *dev = crtc->dev;
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         intel_clock_t clock;
 761         int max_n;
 762         bool found;
 763         int err_most = 47;
 764         found = false;
 765
 766         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 767                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 768                     LVDS_CLKB_POWER_UP)
 769                         clock.p2 = limit->p2.p2_fast;
 770                 else
 771                         clock.p2 = limit->p2.p2_slow;
 772         } else {
 773                 if (target < limit->p2.dot_limit)
 774                         clock.p2 = limit->p2.p2_slow;
 775                 else
 776                         clock.p2 = limit->p2.p2_fast;
 777         }
 778
 779         memset(best_clock, 0, sizeof(*best_clock));
 780         max_n = limit->n.max;
 781         /* based on hardware requriment prefer smaller n to precision */
 782         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 783                 /* based on hardware requirment prefere larger m1,m2, p1 */
 784                 for (clock.m1 = limit->m1.max;
 785                      clock.m1 >= limit->m1.min; clock.m1--) {
 786                         for (clock.m2 = limit->m2.max;
 787                              clock.m2 >= limit->m2.min; clock.m2--) {
 788                                 for (clock.p1 = limit->p1.max;
 789                                      clock.p1 >= limit->p1.min; clock.p1--) {
 790                                         int this_err;
 791
 792                                         intel_clock(dev, refclk, &clock);
 793                                         if (!intel_PLL_is_valid(crtc, &clock))
 794                                                 continue;
 795                                         this_err = abs((10000 - (target*10000/clock.dot)));
 796                                         if (this_err < err_most) {
 797                                                 *best_clock = clock;
 798                                                 err_most = this_err;
 799                                                 max_n = clock.n;
 800                                                 found = true;
 801                                                 /* found on first matching */
 802                                                 goto out;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808 out:
 809         return found;
 810 }
 811
 812 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 813 static bool
 814 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 815                       int target, int refclk, intel_clock_t *best_clock)
 816 {
 817     intel_clock_t clock;
 818     if (target < 200000) {
 819         clock.p1 = 2;
 820         clock.p2 = 10;
 821         clock.n = 2;
 822         clock.m1 = 23;
 823         clock.m2 = 8;
 824     } else {
 825         clock.p1 = 1;
 826         clock.p2 = 10;
 827         clock.n = 1;
 828         clock.m1 = 14;
 829         clock.m2 = 2;
 830     }
 831     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 832     clock.p = (clock.p1 * clock.p2);
 833     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 834     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 835     return true;
 836 }
 837
 838 void
 839 intel_wait_for_vblank(struct drm_device *dev)
 840 {
 841         /* Wait for 20ms, i.e. one cycle at 50hz. */
 842         mdelay(20);
 843 }
 844
 845 static int
 846 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 847                     struct drm_framebuffer *old_fb)
 848 {
 849         struct drm_device *dev = crtc->dev;
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         struct drm_i915_master_private *master_priv;
 852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 853         struct intel_framebuffer *intel_fb;
 854         struct drm_i915_gem_object *obj_priv;
 855         struct drm_gem_object *obj;
 856         int pipe = intel_crtc->pipe;
 857         unsigned long Start, Offset;
 858         int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
 859         int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
 860         int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
 861         int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
 862         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
 863         u32 dspcntr, alignment;
 864         int ret;
 865
 866         /* no fb bound */
 867         if (!crtc->fb) {
 868                 DRM_DEBUG("No FB bound\n");
 869                 return 0;
 870         }
 871
 872         switch (pipe) {
 873         case 0:
 874         case 1:
 875                 break;
 876         default:
 877                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
 878                 return -EINVAL;
 879         }
 880
 881         intel_fb = to_intel_framebuffer(crtc->fb);
 882         obj = intel_fb->obj;
 883         obj_priv = obj->driver_private;
 884
 885         switch (obj_priv->tiling_mode) {
 886         case I915_TILING_NONE:
 887                 alignment = 64 * 1024;
 888                 break;
 889         case I915_TILING_X:
 890                 /* pin() will align the object as required by fence */
 891                 alignment = 0;
 892                 break;
 893         case I915_TILING_Y:
 894                 /* FIXME: Is this true? */
 895                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
 896                 return -EINVAL;
 897         default:
 898                 BUG();
 899         }
 900
 901         mutex_lock(&dev->struct_mutex);
 902         ret = i915_gem_object_pin(obj, alignment);
 903         if (ret != 0) {
 904                 mutex_unlock(&dev->struct_mutex);
 905                 return ret;
 906         }
 907
 908         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 909         if (ret != 0) {
 910                 i915_gem_object_unpin(obj);
 911                 mutex_unlock(&dev->struct_mutex);
 912                 return ret;
 913         }
 914
 915         /* Pre-i965 needs to install a fence for tiled scan-out */
 916         if (!IS_I965G(dev) &&
 917             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
 918             obj_priv->tiling_mode != I915_TILING_NONE) {
 919                 ret = i915_gem_object_get_fence_reg(obj);
 920                 if (ret != 0) {
 921                         i915_gem_object_unpin(obj);
 922                         mutex_unlock(&dev->struct_mutex);
 923                         return ret;
 924                 }
 925         }
 926
 927         dspcntr = I915_READ(dspcntr_reg);
 928         /* Mask out pixel format bits in case we change it */
 929         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 930         switch (crtc->fb->bits_per_pixel) {
 931         case 8:
 932                 dspcntr |= DISPPLANE_8BPP;
 933                 break;
 934         case 16:
 935                 if (crtc->fb->depth == 15)
 936                         dspcntr |= DISPPLANE_15_16BPP;
 937                 else
 938                         dspcntr |= DISPPLANE_16BPP;
 939                 break;
 940         case 24:
 941         case 32:
 942                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 943                 break;
 944         default:
 945                 DRM_ERROR("Unknown color depth\n");
 946                 i915_gem_object_unpin(obj);
 947                 mutex_unlock(&dev->struct_mutex);
 948                 return -EINVAL;
 949         }
 950         if (IS_I965G(dev)) {
 951                 if (obj_priv->tiling_mode != I915_TILING_NONE)
 952                         dspcntr |= DISPPLANE_TILED;
 953                 else
 954                         dspcntr &= ~DISPPLANE_TILED;
 955         }
 956
 957         I915_WRITE(dspcntr_reg, dspcntr);
 958
 959         Start = obj_priv->gtt_offset;
 960         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
 961
 962         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
 963         I915_WRITE(dspstride, crtc->fb->pitch);
 964         if (IS_I965G(dev)) {
 965                 I915_WRITE(dspbase, Offset);
 966                 I915_READ(dspbase);
 967                 I915_WRITE(dspsurf, Start);
 968                 I915_READ(dspsurf);
 969                 I915_WRITE(dsptileoff, (y << 16) | x);
 970         } else {
 971                 I915_WRITE(dspbase, Start + Offset);
 972                 I915_READ(dspbase);
 973         }
 974
 975         intel_wait_for_vblank(dev);
 976
 977         if (old_fb) {
 978                 intel_fb = to_intel_framebuffer(old_fb);
 979                 i915_gem_object_unpin(intel_fb->obj);
 980         }
 981         mutex_unlock(&dev->struct_mutex);
 982
 983         if (!dev->primary->master)
 984                 return 0;
 985
 986         master_priv = dev->primary->master->driver_priv;
 987         if (!master_priv->sarea_priv)
 988                 return 0;
 989
 990         if (pipe) {
 991                 master_priv->sarea_priv->pipeB_x = x;
 992                 master_priv->sarea_priv->pipeB_y = y;
 993         } else {
 994                 master_priv->sarea_priv->pipeA_x = x;
 995                 master_priv->sarea_priv->pipeA_y = y;
 996         }
 997
 998         return 0;
 999 }
1000
1001 /* Disable the VGA plane that we never use */
1002 static void i915_disable_vga (struct drm_device *dev)
1003 {
1004         struct drm_i915_private *dev_priv = dev->dev_private;
1005         u8 sr1;
1006         u32 vga_reg;
1007
1008         if (IS_IGDNG(dev))
1009                 vga_reg = CPU_VGACNTRL;
1010         else
1011                 vga_reg = VGACNTRL;
1012
1013         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1014                 return;
1015
1016         I915_WRITE8(VGA_SR_INDEX, 1);
1017         sr1 = I915_READ8(VGA_SR_DATA);
1018         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1019         udelay(100);
1020
1021         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1022 }
1023
1024 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1025 {
1026         struct drm_device *dev = crtc->dev;
1027         struct drm_i915_private *dev_priv = dev->dev_private;
1028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1029         int pipe = intel_crtc->pipe;
1030         int plane = intel_crtc->plane;
1031         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1032         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1033         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1034         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1035         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1036         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1037         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1038         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1039         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1040         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1041         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1042         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1043         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1044         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1045         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1046         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1047         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1048         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1049         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1050         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1051         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1052         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1053         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1054         u32 temp;
1055         int tries = 5, j, n;
1056
1057         /* XXX: When our outputs are all unaware of DPMS modes other than off
1058          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1059          */
1060         switch (mode) {
1061         case DRM_MODE_DPMS_ON:
1062         case DRM_MODE_DPMS_STANDBY:
1063         case DRM_MODE_DPMS_SUSPEND:
1064                 DRM_DEBUG("crtc %d dpms on\n", pipe);
1065                 /* enable PCH DPLL */
1066                 temp = I915_READ(pch_dpll_reg);
1067                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1068                         I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1069                         I915_READ(pch_dpll_reg);
1070                 }
1071
1072                 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1073                 temp = I915_READ(fdi_rx_reg);
1074                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1075                                 FDI_SEL_PCDCLK |
1076                                 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1077                 I915_READ(fdi_rx_reg);
1078                 udelay(200);
1079
1080                 /* Enable CPU FDI TX PLL, always on for IGDNG */
1081                 temp = I915_READ(fdi_tx_reg);
1082                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1083                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1084                         I915_READ(fdi_tx_reg);
1085                         udelay(100);
1086                 }
1087
1088                 /* Enable CPU pipe */
1089                 temp = I915_READ(pipeconf_reg);
1090                 if ((temp & PIPEACONF_ENABLE) == 0) {
1091                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1092                         I915_READ(pipeconf_reg);
1093                         udelay(100);
1094                 }
1095
1096                 /* configure and enable CPU plane */
1097                 temp = I915_READ(dspcntr_reg);
1098                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1099                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1100                         /* Flush the plane changes */
1101                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1102                 }
1103
1104                 /* enable CPU FDI TX and PCH FDI RX */
1105                 temp = I915_READ(fdi_tx_reg);
1106                 temp |= FDI_TX_ENABLE;
1107                 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1108                 temp &= ~FDI_LINK_TRAIN_NONE;
1109                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1110                 I915_WRITE(fdi_tx_reg, temp);
1111                 I915_READ(fdi_tx_reg);
1112
1113                 temp = I915_READ(fdi_rx_reg);
1114                 temp &= ~FDI_LINK_TRAIN_NONE;
1115                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1116                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1117                 I915_READ(fdi_rx_reg);
1118
1119                 udelay(150);
1120
1121                 /* Train FDI. */
1122                 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1123                    for train result */
1124                 temp = I915_READ(fdi_rx_imr_reg);
1125                 temp &= ~FDI_RX_SYMBOL_LOCK;
1126                 temp &= ~FDI_RX_BIT_LOCK;
1127                 I915_WRITE(fdi_rx_imr_reg, temp);
1128                 I915_READ(fdi_rx_imr_reg);
1129                 udelay(150);
1130
1131                 temp = I915_READ(fdi_rx_iir_reg);
1132                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1133
1134                 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1135                         for (j = 0; j < tries; j++) {
1136                                 temp = I915_READ(fdi_rx_iir_reg);
1137                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1138                                 if (temp & FDI_RX_BIT_LOCK)
1139                                         break;
1140                                 udelay(200);
1141                         }
1142                         if (j != tries)
1143                                 I915_WRITE(fdi_rx_iir_reg,
1144                                                 temp | FDI_RX_BIT_LOCK);
1145                         else
1146                                 DRM_DEBUG("train 1 fail\n");
1147                 } else {
1148                         I915_WRITE(fdi_rx_iir_reg,
1149                                         temp | FDI_RX_BIT_LOCK);
1150                         DRM_DEBUG("train 1 ok 2!\n");
1151                 }
1152                 temp = I915_READ(fdi_tx_reg);
1153                 temp &= ~FDI_LINK_TRAIN_NONE;
1154                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1155                 I915_WRITE(fdi_tx_reg, temp);
1156
1157                 temp = I915_READ(fdi_rx_reg);
1158                 temp &= ~FDI_LINK_TRAIN_NONE;
1159                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1160                 I915_WRITE(fdi_rx_reg, temp);
1161
1162                 udelay(150);
1163
1164                 temp = I915_READ(fdi_rx_iir_reg);
1165                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1166
1167                 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1168                         for (j = 0; j < tries; j++) {
1169                                 temp = I915_READ(fdi_rx_iir_reg);
1170                                 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1171                                 if (temp & FDI_RX_SYMBOL_LOCK)
1172                                         break;
1173                                 udelay(200);
1174                         }
1175                         if (j != tries) {
1176                                 I915_WRITE(fdi_rx_iir_reg,
1177                                                 temp | FDI_RX_SYMBOL_LOCK);
1178                                 DRM_DEBUG("train 2 ok 1!\n");
1179                         } else
1180                                 DRM_DEBUG("train 2 fail\n");
1181                 } else {
1182                         I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1183                         DRM_DEBUG("train 2 ok 2!\n");
1184                 }
1185                 DRM_DEBUG("train done\n");
1186
1187                 /* set transcoder timing */
1188                 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1189                 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1190                 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1191
1192                 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1193                 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1194                 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1195
1196                 /* enable PCH transcoder */
1197                 temp = I915_READ(transconf_reg);
1198                 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1199                 I915_READ(transconf_reg);
1200
1201                 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1202                         ;
1203
1204                 /* enable normal */
1205
1206                 temp = I915_READ(fdi_tx_reg);
1207                 temp &= ~FDI_LINK_TRAIN_NONE;
1208                 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1209                                 FDI_TX_ENHANCE_FRAME_ENABLE);
1210                 I915_READ(fdi_tx_reg);
1211
1212                 temp = I915_READ(fdi_rx_reg);
1213                 temp &= ~FDI_LINK_TRAIN_NONE;
1214                 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1215                                 FDI_RX_ENHANCE_FRAME_ENABLE);
1216                 I915_READ(fdi_rx_reg);
1217
1218                 /* wait one idle pattern time */
1219                 udelay(100);
1220
1221                 intel_crtc_load_lut(crtc);
1222
1223         break;
1224         case DRM_MODE_DPMS_OFF:
1225                 DRM_DEBUG("crtc %d dpms off\n", pipe);
1226
1227                 i915_disable_vga(dev);
1228
1229                 /* Disable display plane */
1230                 temp = I915_READ(dspcntr_reg);
1231                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1232                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1233                         /* Flush the plane changes */
1234                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1235                         I915_READ(dspbase_reg);
1236                 }
1237
1238                 /* disable cpu pipe, disable after all planes disabled */
1239                 temp = I915_READ(pipeconf_reg);
1240                 if ((temp & PIPEACONF_ENABLE) != 0) {
1241                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1242                         I915_READ(pipeconf_reg);
1243                         n = 0;
1244                         /* wait for cpu pipe off, pipe state */
1245                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1246                                 n++;
1247                                 if (n < 60) {
1248                                         udelay(500);
1249                                         continue;
1250                                 } else {
1251                                         DRM_DEBUG("pipe %d off delay\n", pipe);
1252                                         break;
1253                                 }
1254                         }
1255                 } else
1256                         DRM_DEBUG("crtc %d is disabled\n", pipe);
1257
1258                 /* disable CPU FDI tx and PCH FDI rx */
1259                 temp = I915_READ(fdi_tx_reg);
1260                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1261                 I915_READ(fdi_tx_reg);
1262
1263                 temp = I915_READ(fdi_rx_reg);
1264                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1265                 I915_READ(fdi_rx_reg);
1266
1267                 udelay(100);
1268
1269                 /* still set train pattern 1 */
1270                 temp = I915_READ(fdi_tx_reg);
1271                 temp &= ~FDI_LINK_TRAIN_NONE;
1272                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1273                 I915_WRITE(fdi_tx_reg, temp);
1274
1275                 temp = I915_READ(fdi_rx_reg);
1276                 temp &= ~FDI_LINK_TRAIN_NONE;
1277                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1278                 I915_WRITE(fdi_rx_reg, temp);
1279
1280                 udelay(100);
1281
1282                 /* disable PCH transcoder */
1283                 temp = I915_READ(transconf_reg);
1284                 if ((temp & TRANS_ENABLE) != 0) {
1285                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1286                         I915_READ(transconf_reg);
1287                         n = 0;
1288                         /* wait for PCH transcoder off, transcoder state */
1289                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1290                                 n++;
1291                                 if (n < 60) {
1292                                         udelay(500);
1293                                         continue;
1294                                 } else {
1295                                         DRM_DEBUG("transcoder %d off delay\n", pipe);
1296                                         break;
1297                                 }
1298                         }
1299                 }
1300
1301                 /* disable PCH DPLL */
1302                 temp = I915_READ(pch_dpll_reg);
1303                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1304                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1305                         I915_READ(pch_dpll_reg);
1306                 }
1307
1308                 temp = I915_READ(fdi_rx_reg);
1309                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1310                         temp &= ~FDI_SEL_PCDCLK;
1311                         temp &= ~FDI_RX_PLL_ENABLE;
1312                         I915_WRITE(fdi_rx_reg, temp);
1313                         I915_READ(fdi_rx_reg);
1314                 }
1315
1316                 /* Disable CPU FDI TX PLL */
1317                 temp = I915_READ(fdi_tx_reg);
1318                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1319                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1320                         I915_READ(fdi_tx_reg);
1321                         udelay(100);
1322                 }
1323
1324                 /* Disable PF */
1325                 temp = I915_READ(pf_ctl_reg);
1326                 if ((temp & PF_ENABLE) != 0) {
1327                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1328                         I915_READ(pf_ctl_reg);
1329                 }
1330                 I915_WRITE(pf_win_size, 0);
1331
1332                 /* Wait for the clocks to turn off. */
1333                 udelay(150);
1334                 break;
1335         }
1336 }
1337
1338 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1339 {
1340         struct drm_device *dev = crtc->dev;
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1343         int pipe = intel_crtc->pipe;
1344         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1345         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1346         int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1347         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1348         u32 temp;
1349
1350         /* XXX: When our outputs are all unaware of DPMS modes other than off
1351          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1352          */
1353         switch (mode) {
1354         case DRM_MODE_DPMS_ON:
1355         case DRM_MODE_DPMS_STANDBY:
1356         case DRM_MODE_DPMS_SUSPEND:
1357                 /* Enable the DPLL */
1358                 temp = I915_READ(dpll_reg);
1359                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1360                         I915_WRITE(dpll_reg, temp);
1361                         I915_READ(dpll_reg);
1362                         /* Wait for the clocks to stabilize. */
1363                         udelay(150);
1364                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1365                         I915_READ(dpll_reg);
1366                         /* Wait for the clocks to stabilize. */
1367                         udelay(150);
1368                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1369                         I915_READ(dpll_reg);
1370                         /* Wait for the clocks to stabilize. */
1371                         udelay(150);
1372                 }
1373
1374                 /* Enable the pipe */
1375                 temp = I915_READ(pipeconf_reg);
1376                 if ((temp & PIPEACONF_ENABLE) == 0)
1377                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1378
1379                 /* Enable the plane */
1380                 temp = I915_READ(dspcntr_reg);
1381                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1382                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1383                         /* Flush the plane changes */
1384                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1385                 }
1386
1387                 intel_crtc_load_lut(crtc);
1388
1389                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1390                 //intel_crtc_dpms_video(crtc, true); TODO
1391                 intel_update_watermarks(dev);
1392         break;
1393         case DRM_MODE_DPMS_OFF:
1394                 intel_update_watermarks(dev);
1395                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1396                 //intel_crtc_dpms_video(crtc, FALSE); TODO
1397
1398                 /* Disable the VGA plane that we never use */
1399                 i915_disable_vga(dev);
1400
1401                 /* Disable display plane */
1402                 temp = I915_READ(dspcntr_reg);
1403                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1404                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1405                         /* Flush the plane changes */
1406                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1407                         I915_READ(dspbase_reg);
1408                 }
1409
1410                 if (!IS_I9XX(dev)) {
1411                         /* Wait for vblank for the disable to take effect */
1412                         intel_wait_for_vblank(dev);
1413                 }
1414
1415                 /* Next, disable display pipes */
1416                 temp = I915_READ(pipeconf_reg);
1417                 if ((temp & PIPEACONF_ENABLE) != 0) {
1418                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1419                         I915_READ(pipeconf_reg);
1420                 }
1421
1422                 /* Wait for vblank for the disable to take effect. */
1423                 intel_wait_for_vblank(dev);
1424
1425                 temp = I915_READ(dpll_reg);
1426                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1427                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1428                         I915_READ(dpll_reg);
1429                 }
1430
1431                 /* Wait for the clocks to turn off. */
1432                 udelay(150);
1433                 break;
1434         }
1435 }
1436
1437 /**
1438  * Sets the power management mode of the pipe and plane.
1439  *
1440  * This code should probably grow support for turning the cursor off and back
1441  * on appropriately at the same time as we're turning the pipe off/on.
1442  */
1443 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1444 {
1445         struct drm_device *dev = crtc->dev;
1446         struct drm_i915_master_private *master_priv;
1447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1448         int pipe = intel_crtc->pipe;
1449         bool enabled;
1450
1451         if (IS_IGDNG(dev))
1452                 igdng_crtc_dpms(crtc, mode);
1453         else
1454                 i9xx_crtc_dpms(crtc, mode);
1455
1456         if (!dev->primary->master)
1457                 return;
1458
1459         master_priv = dev->primary->master->driver_priv;
1460         if (!master_priv->sarea_priv)
1461                 return;
1462
1463         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1464
1465         switch (pipe) {
1466         case 0:
1467                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1468                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1469                 break;
1470         case 1:
1471                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1472                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1473                 break;
1474         default:
1475                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1476                 break;
1477         }
1478
1479         intel_crtc->dpms_mode = mode;
1480 }
1481
1482 static void intel_crtc_prepare (struct drm_crtc *crtc)
1483 {
1484         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1485         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1486 }
1487
1488 static void intel_crtc_commit (struct drm_crtc *crtc)
1489 {
1490         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1491         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1492 }
1493
1494 void intel_encoder_prepare (struct drm_encoder *encoder)
1495 {
1496         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1497         /* lvds has its own version of prepare see intel_lvds_prepare */
1498         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1499 }
1500
1501 void intel_encoder_commit (struct drm_encoder *encoder)
1502 {
1503         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1504         /* lvds has its own version of commit see intel_lvds_commit */
1505         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1506 }
1507
1508 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1509                                   struct drm_display_mode *mode,
1510                                   struct drm_display_mode *adjusted_mode)
1511 {
1512         struct drm_device *dev = crtc->dev;
1513         if (IS_IGDNG(dev)) {
1514                 /* FDI link clock is fixed at 2.7G */
1515                 if (mode->clock * 3 > 27000 * 4)
1516                         return MODE_CLOCK_HIGH;
1517         }
1518         return true;
1519 }
1520
1521
1522 /** Returns the core display clock speed for i830 - i945 */
1523 static int intel_get_core_clock_speed(struct drm_device *dev)
1524 {
1525
1526         /* Core clock values taken from the published datasheets.
1527          * The 830 may go up to 166 Mhz, which we should check.
1528          */
1529         if (IS_I945G(dev))
1530                 return 400000;
1531         else if (IS_I915G(dev))
1532                 return 333000;
1533         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1534                 return 200000;
1535         else if (IS_I915GM(dev)) {
1536                 u16 gcfgc = 0;
1537
1538                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1539
1540                 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1541                         return 133000;
1542                 else {
1543                         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1544                         case GC_DISPLAY_CLOCK_333_MHZ:
1545                                 return 333000;
1546                         default:
1547                         case GC_DISPLAY_CLOCK_190_200_MHZ:
1548                                 return 190000;
1549                         }
1550                 }
1551         } else if (IS_I865G(dev))
1552                 return 266000;
1553         else if (IS_I855(dev)) {
1554                 u16 hpllcc = 0;
1555                 /* Assume that the hardware is in the high speed state.  This
1556                  * should be the default.
1557                  */
1558                 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1559                 case GC_CLOCK_133_200:
1560                 case GC_CLOCK_100_200:
1561                         return 200000;
1562                 case GC_CLOCK_166_250:
1563                         return 250000;
1564                 case GC_CLOCK_100_133:
1565                         return 133000;
1566                 }
1567         } else /* 852, 830 */
1568                 return 133000;
1569
1570         return 0; /* Silence gcc warning */
1571 }
1572
1573 /**
1574  * Return the pipe currently connected to the panel fitter,
1575  * or -1 if the panel fitter is not present or not in use
1576  */
1577 static int intel_panel_fitter_pipe (struct drm_device *dev)
1578 {
1579         struct drm_i915_private *dev_priv = dev->dev_private;
1580         u32  pfit_control;
1581
1582         /* i830 doesn't have a panel fitter */
1583         if (IS_I830(dev))
1584                 return -1;
1585
1586         pfit_control = I915_READ(PFIT_CONTROL);
1587
1588         /* See if the panel fitter is in use */
1589         if ((pfit_control & PFIT_ENABLE) == 0)
1590                 return -1;
1591
1592         /* 965 can place panel fitter on either pipe */
1593         if (IS_I965G(dev))
1594                 return (pfit_control >> 29) & 0x3;
1595
1596         /* older chips can only use pipe 1 */
1597         return 1;
1598 }
1599
1600 struct fdi_m_n {
1601         u32        tu;
1602         u32        gmch_m;
1603         u32        gmch_n;
1604         u32        link_m;
1605         u32        link_n;
1606 };
1607
1608 static void
1609 fdi_reduce_ratio(u32 *num, u32 *den)
1610 {
1611         while (*num > 0xffffff || *den > 0xffffff) {
1612                 *num >>= 1;
1613                 *den >>= 1;
1614         }
1615 }
1616
1617 #define DATA_N 0x800000
1618 #define LINK_N 0x80000
1619
1620 static void
1621 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1622                 int pixel_clock, int link_clock,
1623                 struct fdi_m_n *m_n)
1624 {
1625         u64 temp;
1626
1627         m_n->tu = 64; /* default size */
1628
1629         temp = (u64) DATA_N * pixel_clock;
1630         temp = div_u64(temp, link_clock);
1631         m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
1632         m_n->gmch_n = DATA_N;
1633         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1634
1635         temp = (u64) LINK_N * pixel_clock;
1636         m_n->link_m = div_u64(temp, link_clock);
1637         m_n->link_n = LINK_N;
1638         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1639 }
1640
1641
1642 struct intel_watermark_params {
1643         unsigned long fifo_size;
1644         unsigned long max_wm;
1645         unsigned long default_wm;
1646         unsigned long guard_size;
1647         unsigned long cacheline_size;
1648 };
1649
1650 /* IGD has different values for various configs */
1651 static struct intel_watermark_params igd_display_wm = {
1652         IGD_DISPLAY_FIFO,
1653         IGD_MAX_WM,
1654         IGD_DFT_WM,
1655         IGD_GUARD_WM,
1656         IGD_FIFO_LINE_SIZE
1657 };
1658 static struct intel_watermark_params igd_display_hplloff_wm = {
1659         IGD_DISPLAY_FIFO,
1660         IGD_MAX_WM,
1661         IGD_DFT_HPLLOFF_WM,
1662         IGD_GUARD_WM,
1663         IGD_FIFO_LINE_SIZE
1664 };
1665 static struct intel_watermark_params igd_cursor_wm = {
1666         IGD_CURSOR_FIFO,
1667         IGD_CURSOR_MAX_WM,
1668         IGD_CURSOR_DFT_WM,
1669         IGD_CURSOR_GUARD_WM,
1670         IGD_FIFO_LINE_SIZE,
1671 };
1672 static struct intel_watermark_params igd_cursor_hplloff_wm = {
1673         IGD_CURSOR_FIFO,
1674         IGD_CURSOR_MAX_WM,
1675         IGD_CURSOR_DFT_WM,
1676         IGD_CURSOR_GUARD_WM,
1677         IGD_FIFO_LINE_SIZE
1678 };
1679 static struct intel_watermark_params i945_wm_info = {
1680         I945_FIFO_SIZE,
1681         I915_MAX_WM,
1682         1,
1683         2,
1684         I915_FIFO_LINE_SIZE
1685 };
1686 static struct intel_watermark_params i915_wm_info = {
1687         I915_FIFO_SIZE,
1688         I915_MAX_WM,
1689         1,
1690         2,
1691         I915_FIFO_LINE_SIZE
1692 };
1693 static struct intel_watermark_params i855_wm_info = {
1694         I855GM_FIFO_SIZE,
1695         I915_MAX_WM,
1696         1,
1697         2,
1698         I830_FIFO_LINE_SIZE
1699 };
1700 static struct intel_watermark_params i830_wm_info = {
1701         I830_FIFO_SIZE,
1702         I915_MAX_WM,
1703         1,
1704         2,
1705         I830_FIFO_LINE_SIZE
1706 };
1707
1708 /**
1709  * intel_calculate_wm - calculate watermark level
1710  * @clock_in_khz: pixel clock
1711  * @wm: chip FIFO params
1712  * @pixel_size: display pixel size
1713  * @latency_ns: memory latency for the platform
1714  *
1715  * Calculate the watermark level (the level at which the display plane will
1716  * start fetching from memory again).  Each chip has a different display
1717  * FIFO size and allocation, so the caller needs to figure that out and pass
1718  * in the correct intel_watermark_params structure.
1719  *
1720  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1721  * on the pixel size.  When it reaches the watermark level, it'll start
1722  * fetching FIFO line sized based chunks from memory until the FIFO fills
1723  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1724  * will occur, and a display engine hang could result.
1725  */
1726 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1727                                         struct intel_watermark_params *wm,
1728                                         int pixel_size,
1729                                         unsigned long latency_ns)
1730 {
1731         long entries_required, wm_size;
1732
1733         entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1734         entries_required /= wm->cacheline_size;
1735
1736         DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
1737
1738         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
1739
1740         DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
1741
1742         /* Don't promote wm_size to unsigned... */
1743         if (wm_size > (long)wm->max_wm)
1744                 wm_size = wm->max_wm;
1745         if (wm_size <= 0)
1746                 wm_size = wm->default_wm;
1747         return wm_size;
1748 }
1749
1750 struct cxsr_latency {
1751         int is_desktop;
1752         unsigned long fsb_freq;
1753         unsigned long mem_freq;
1754         unsigned long display_sr;
1755         unsigned long display_hpll_disable;
1756         unsigned long cursor_sr;
1757         unsigned long cursor_hpll_disable;
1758 };
1759
1760 static struct cxsr_latency cxsr_latency_table[] = {
1761         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
1762         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
1763         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
1764
1765         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
1766         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
1767         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
1768
1769         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
1770         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
1771         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
1772
1773         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
1774         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
1775         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
1776
1777         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
1778         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
1779         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
1780
1781         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
1782         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
1783         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
1784 };
1785
1786 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
1787                                                    int mem)
1788 {
1789         int i;
1790         struct cxsr_latency *latency;
1791
1792         if (fsb == 0 || mem == 0)
1793                 return NULL;
1794
1795         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1796                 latency = &cxsr_latency_table[i];
1797                 if (is_desktop == latency->is_desktop &&
1798                         fsb == latency->fsb_freq && mem == latency->mem_freq)
1799                         break;
1800         }
1801         if (i >= ARRAY_SIZE(cxsr_latency_table)) {
1802                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1803                 return NULL;
1804         }
1805         return latency;
1806 }
1807
1808 static void igd_disable_cxsr(struct drm_device *dev)
1809 {
1810         struct drm_i915_private *dev_priv = dev->dev_private;
1811         u32 reg;
1812
1813         /* deactivate cxsr */
1814         reg = I915_READ(DSPFW3);
1815         reg &= ~(IGD_SELF_REFRESH_EN);
1816         I915_WRITE(DSPFW3, reg);
1817         DRM_INFO("Big FIFO is disabled\n");
1818 }
1819
1820 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
1821                             int pixel_size)
1822 {
1823         struct drm_i915_private *dev_priv = dev->dev_private;
1824         u32 reg;
1825         unsigned long wm;
1826         struct cxsr_latency *latency;
1827
1828         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
1829                 dev_priv->mem_freq);
1830         if (!latency) {
1831                 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1832                 igd_disable_cxsr(dev);
1833                 return;
1834         }
1835
1836         /* Display SR */
1837         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
1838                                 latency->display_sr);
1839         reg = I915_READ(DSPFW1);
1840         reg &= 0x7fffff;
1841         reg |= wm << 23;
1842         I915_WRITE(DSPFW1, reg);
1843         DRM_DEBUG("DSPFW1 register is %x\n", reg);
1844
1845         /* cursor SR */
1846         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
1847                                 latency->cursor_sr);
1848         reg = I915_READ(DSPFW3);
1849         reg &= ~(0x3f << 24);
1850         reg |= (wm & 0x3f) << 24;
1851         I915_WRITE(DSPFW3, reg);
1852
1853         /* Display HPLL off SR */
1854         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
1855                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
1856         reg = I915_READ(DSPFW3);
1857         reg &= 0xfffffe00;
1858         reg |= wm & 0x1ff;
1859         I915_WRITE(DSPFW3, reg);
1860
1861         /* cursor HPLL off SR */
1862         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
1863                                 latency->cursor_hpll_disable);
1864         reg = I915_READ(DSPFW3);
1865         reg &= ~(0x3f << 16);
1866         reg |= (wm & 0x3f) << 16;
1867         I915_WRITE(DSPFW3, reg);
1868         DRM_DEBUG("DSPFW3 register is %x\n", reg);
1869
1870         /* activate cxsr */
1871         reg = I915_READ(DSPFW3);
1872         reg |= IGD_SELF_REFRESH_EN;
1873         I915_WRITE(DSPFW3, reg);
1874
1875         DRM_INFO("Big FIFO is enabled\n");
1876
1877         return;
1878 }
1879
1880 const static int latency_ns = 3000; /* default for non-igd platforms */
1881
1882 static int intel_get_fifo_size(struct drm_device *dev, int plane)
1883 {
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         uint32_t dsparb = I915_READ(DSPARB);
1886         int size;
1887
1888         if (IS_I9XX(dev)) {
1889                 if (plane == 0)
1890                         size = dsparb & 0x7f;
1891                 else
1892                         size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
1893                                 (dsparb & 0x7f);
1894         } else if (IS_I85X(dev)) {
1895                 if (plane == 0)
1896                         size = dsparb & 0x1ff;
1897                 else
1898                         size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
1899                                 (dsparb & 0x1ff);
1900                 size >>= 1; /* Convert to cachelines */
1901         } else {
1902                 size = dsparb & 0x7f;
1903                 size >>= 1; /* Convert to cachelines */
1904         }
1905
1906         DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
1907                   size);
1908
1909         return size;
1910 }
1911
1912 static void i965_update_wm(struct drm_device *dev)
1913 {
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915
1916         DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
1917
1918         /* 965 has limitations... */
1919         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
1920         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1921 }
1922
1923 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1924                            int planeb_clock, int sr_hdisplay, int pixel_size)
1925 {
1926         struct drm_i915_private *dev_priv = dev->dev_private;
1927         uint32_t fwater_lo;
1928         uint32_t fwater_hi;
1929         int total_size, cacheline_size, cwm, srwm = 1;
1930         int planea_wm, planeb_wm;
1931         struct intel_watermark_params planea_params, planeb_params;
1932         unsigned long line_time_us;
1933         int sr_clock, sr_entries = 0;
1934
1935         /* Create copies of the base settings for each pipe */
1936         if (IS_I965GM(dev) || IS_I945GM(dev))
1937                 planea_params = planeb_params = i945_wm_info;
1938         else if (IS_I9XX(dev))
1939                 planea_params = planeb_params = i915_wm_info;
1940         else
1941                 planea_params = planeb_params = i855_wm_info;
1942
1943         /* Grab a couple of global values before we overwrite them */
1944         total_size = planea_params.fifo_size;
1945         cacheline_size = planea_params.cacheline_size;
1946
1947         /* Update per-plane FIFO sizes */
1948         planea_params.fifo_size = intel_get_fifo_size(dev, 0);
1949         planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
1950
1951         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
1952                                        pixel_size, latency_ns);
1953         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
1954                                        pixel_size, latency_ns);
1955         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1956
1957         /*
1958          * Overlay gets an aggressive default since video jitter is bad.
1959          */
1960         cwm = 2;
1961
1962         /* Calc sr entries for one plane configs */
1963         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
1964                 /* self-refresh has much higher latency */
1965                 const static int sr_latency_ns = 6000;
1966
1967                 sr_clock = planea_clock ? planea_clock : planeb_clock;
1968                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
1969
1970                 /* Use ns/us then divide to preserve precision */
1971                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
1972                               pixel_size * sr_hdisplay) / 1000;
1973                 sr_entries = roundup(sr_entries / cacheline_size, 1);
1974                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
1975                 srwm = total_size - sr_entries;
1976                 if (srwm < 0)
1977                         srwm = 1;
1978                 if (IS_I9XX(dev))
1979                         I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
1980         }
1981
1982         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1983                   planea_wm, planeb_wm, cwm, srwm);
1984
1985         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1986         fwater_hi = (cwm & 0x1f);
1987
1988         /* Set request length to 8 cachelines per fetch */
1989         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1990         fwater_hi = fwater_hi | (1 << 8);
1991
1992         I915_WRITE(FW_BLC, fwater_lo);
1993         I915_WRITE(FW_BLC2, fwater_hi);
1994 }
1995
1996 static void i830_update_wm(struct drm_device *dev, int planea_clock,
1997                            int pixel_size)
1998 {
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
2001         int planea_wm;
2002
2003         i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
2004
2005         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2006                                        pixel_size, latency_ns);
2007         fwater_lo = fwater_lo | planea_wm;
2008
2009         I915_WRITE(FW_BLC, fwater_lo);
2010 }
2011
2012 /**
2013  * intel_update_watermarks - update FIFO watermark values based on current modes
2014  *
2015  * Calculate watermark values for the various WM regs based on current mode
2016  * and plane configuration.
2017  *
2018  * There are several cases to deal with here:
2019  *   - normal (i.e. non-self-refresh)
2020  *   - self-refresh (SR) mode
2021  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2022  *   - lines are small relative to FIFO size (buffer can hold more than 2
2023  *     lines), so need to account for TLB latency
2024  *
2025  *   The normal calculation is:
2026  *     watermark = dotclock * bytes per pixel * latency
2027  *   where latency is platform & configuration dependent (we assume pessimal
2028  *   values here).
2029  *
2030  *   The SR calculation is:
2031  *     watermark = (trunc(latency/line time)+1) * surface width *
2032  *       bytes per pixel
2033  *   where
2034  *     line time = htotal / dotclock
2035  *   and latency is assumed to be high, as above.
2036  *
2037  * The final value programmed to the register should always be rounded up,
2038  * and include an extra 2 entries to account for clock crossings.
2039  *
2040  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2041  * to set the non-SR watermarks to 8.
2042   */
2043 static void intel_update_watermarks(struct drm_device *dev)
2044 {
2045         struct drm_crtc *crtc;
2046         struct intel_crtc *intel_crtc;
2047         int sr_hdisplay = 0;
2048         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2049         int enabled = 0, pixel_size = 0;
2050
2051         if (DSPARB_HWCONTROL(dev))
2052                 return;
2053
2054         /* Get the clock config from both planes */
2055         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2056                 intel_crtc = to_intel_crtc(crtc);
2057                 if (crtc->enabled) {
2058                         enabled++;
2059                         if (intel_crtc->plane == 0) {
2060                                 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2061                                           intel_crtc->pipe, crtc->mode.clock);
2062                                 planea_clock = crtc->mode.clock;
2063                         } else {
2064                                 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2065                                           intel_crtc->pipe, crtc->mode.clock);
2066                                 planeb_clock = crtc->mode.clock;
2067                         }
2068                         sr_hdisplay = crtc->mode.hdisplay;
2069                         sr_clock = crtc->mode.clock;
2070                         if (crtc->fb)
2071                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2072                         else
2073                                 pixel_size = 4; /* by default */
2074                 }
2075         }
2076
2077         if (enabled <= 0)
2078                 return;
2079
2080         /* Single plane configs can enable self refresh */
2081         if (enabled == 1 && IS_IGD(dev))
2082                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2083         else if (IS_IGD(dev))
2084                 igd_disable_cxsr(dev);
2085
2086         if (IS_I965G(dev))
2087                 i965_update_wm(dev);
2088         else if (IS_I9XX(dev) || IS_MOBILE(dev))
2089                 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2090                                pixel_size);
2091         else
2092                 i830_update_wm(dev, planea_clock, pixel_size);
2093 }
2094
2095 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2096                                struct drm_display_mode *mode,
2097                                struct drm_display_mode *adjusted_mode,
2098                                int x, int y,
2099                                struct drm_framebuffer *old_fb)
2100 {
2101         struct drm_device *dev = crtc->dev;
2102         struct drm_i915_private *dev_priv = dev->dev_private;
2103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104         int pipe = intel_crtc->pipe;
2105         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2106         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2107         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2108         int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
2109         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2110         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2111         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2112         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2113         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2114         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2115         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2116         int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
2117         int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2118         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2119         int refclk, num_outputs = 0;
2120         intel_clock_t clock;
2121         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2122         bool ok, is_sdvo = false, is_dvo = false;
2123         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2124         struct drm_mode_config *mode_config = &dev->mode_config;
2125         struct drm_connector *connector;
2126         const intel_limit_t *limit;
2127         int ret;
2128         struct fdi_m_n m_n = {0};
2129         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2130         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2131         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2132         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2133         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2134         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2135         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2136         int lvds_reg = LVDS;
2137         u32 temp;
2138         int sdvo_pixel_multiply;
2139
2140         drm_vblank_pre_modeset(dev, pipe);
2141
2142         list_for_each_entry(connector, &mode_config->connector_list, head) {
2143                 struct intel_output *intel_output = to_intel_output(connector);
2144
2145                 if (!connector->encoder || connector->encoder->crtc != crtc)
2146                         continue;
2147
2148                 switch (intel_output->type) {
2149                 case INTEL_OUTPUT_LVDS:
2150                         is_lvds = true;
2151                         break;
2152                 case INTEL_OUTPUT_SDVO:
2153                 case INTEL_OUTPUT_HDMI:
2154                         is_sdvo = true;
2155                         if (intel_output->needs_tv_clock)
2156                                 is_tv = true;
2157                         break;
2158                 case INTEL_OUTPUT_DVO:
2159                         is_dvo = true;
2160                         break;
2161                 case INTEL_OUTPUT_TVOUT:
2162                         is_tv = true;
2163                         break;
2164                 case INTEL_OUTPUT_ANALOG:
2165                         is_crt = true;
2166                         break;
2167                 case INTEL_OUTPUT_DISPLAYPORT:
2168                         is_dp = true;
2169                         break;
2170                 }
2171
2172                 num_outputs++;
2173         }
2174
2175         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2176                 refclk = dev_priv->lvds_ssc_freq * 1000;
2177                 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2178         } else if (IS_I9XX(dev)) {
2179                 refclk = 96000;
2180                 if (IS_IGDNG(dev))
2181                         refclk = 120000; /* 120Mhz refclk */
2182         } else {
2183                 refclk = 48000;
2184         }
2185
2186
2187         /*
2188          * Returns a set of divisors for the desired target clock with the given
2189          * refclk, or FALSE.  The returned values represent the clock equation:
2190          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2191          */
2192         limit = intel_limit(crtc);
2193         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2194         if (!ok) {
2195                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2196                 drm_vblank_post_modeset(dev, pipe);
2197                 return -EINVAL;
2198         }
2199
2200         /* SDVO TV has fixed PLL values depend on its clock range,
2201            this mirrors vbios setting. */
2202         if (is_sdvo && is_tv) {
2203                 if (adjusted_mode->clock >= 100000
2204                                 && adjusted_mode->clock < 140500) {
2205                         clock.p1 = 2;
2206                         clock.p2 = 10;
2207                         clock.n = 3;
2208                         clock.m1 = 16;
2209                         clock.m2 = 8;
2210                 } else if (adjusted_mode->clock >= 140500
2211                                 && adjusted_mode->clock <= 200000) {
2212                         clock.p1 = 1;
2213                         clock.p2 = 10;
2214                         clock.n = 6;
2215                         clock.m1 = 12;
2216                         clock.m2 = 8;
2217                 }
2218         }
2219
2220         /* FDI link */
2221         if (IS_IGDNG(dev))
2222                 igdng_compute_m_n(3, 4, /* lane num 4 */
2223                                 adjusted_mode->clock,
2224                                 270000, /* lane clock */
2225                                 &m_n);
2226
2227         if (IS_IGD(dev))
2228                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2229         else
2230                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2231
2232         if (!IS_IGDNG(dev))
2233                 dpll = DPLL_VGA_MODE_DIS;
2234
2235         if (IS_I9XX(dev)) {
2236                 if (is_lvds)
2237                         dpll |= DPLLB_MODE_LVDS;
2238                 else
2239                         dpll |= DPLLB_MODE_DAC_SERIAL;
2240                 if (is_sdvo) {
2241                         dpll |= DPLL_DVO_HIGH_SPEED;
2242                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2243                         if (IS_I945G(dev) || IS_I945GM(dev))
2244                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2245                         else if (IS_IGDNG(dev))
2246                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2247                 }
2248                 if (is_dp)
2249                         dpll |= DPLL_DVO_HIGH_SPEED;
2250
2251                 /* compute bitmask from p1 value */
2252                 if (IS_IGD(dev))
2253                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2254                 else {
2255                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2256                         /* also FPA1 */
2257                         if (IS_IGDNG(dev))
2258                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2259                 }
2260                 switch (clock.p2) {
2261                 case 5:
2262                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2263                         break;
2264                 case 7:
2265                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2266                         break;
2267                 case 10:
2268                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2269                         break;
2270                 case 14:
2271                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2272                         break;
2273                 }
2274                 if (IS_I965G(dev) && !IS_IGDNG(dev))
2275                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2276         } else {
2277                 if (is_lvds) {
2278                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2279                 } else {
2280                         if (clock.p1 == 2)
2281                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
2282                         else
2283                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2284                         if (clock.p2 == 4)
2285                                 dpll |= PLL_P2_DIVIDE_BY_4;
2286                 }
2287         }
2288
2289         if (is_sdvo && is_tv)
2290                 dpll |= PLL_REF_INPUT_TVCLKINBC;
2291         else if (is_tv)
2292                 /* XXX: just matching BIOS for now */
2293                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
2294                 dpll |= 3;
2295         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2296                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2297         else
2298                 dpll |= PLL_REF_INPUT_DREFCLK;
2299
2300         /* setup pipeconf */
2301         pipeconf = I915_READ(pipeconf_reg);
2302
2303         /* Set up the display plane register */
2304         dspcntr = DISPPLANE_GAMMA_ENABLE;
2305
2306         /* IGDNG's plane is forced to pipe, bit 24 is to
2307            enable color space conversion */
2308         if (!IS_IGDNG(dev)) {
2309                 if (pipe == 0)
2310                         dspcntr |= DISPPLANE_SEL_PIPE_A;
2311                 else
2312                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2313         }
2314
2315         if (pipe == 0 && !IS_I965G(dev)) {
2316                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2317                  * core speed.
2318                  *
2319                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2320                  * pipe == 0 check?
2321                  */
2322                 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2323                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
2324                 else
2325                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2326         }
2327
2328         dspcntr |= DISPLAY_PLANE_ENABLE;
2329         pipeconf |= PIPEACONF_ENABLE;
2330         dpll |= DPLL_VCO_ENABLE;
2331
2332
2333         /* Disable the panel fitter if it was on our pipe */
2334         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2335                 I915_WRITE(PFIT_CONTROL, 0);
2336
2337         DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2338         drm_mode_debug_printmodeline(mode);
2339
2340         /* assign to IGDNG registers */
2341         if (IS_IGDNG(dev)) {
2342                 fp_reg = pch_fp_reg;
2343                 dpll_reg = pch_dpll_reg;
2344         }
2345
2346         if (dpll & DPLL_VCO_ENABLE) {
2347                 I915_WRITE(fp_reg, fp);
2348                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2349                 I915_READ(dpll_reg);
2350                 udelay(150);
2351         }
2352
2353         if (IS_IGDNG(dev)) {
2354                 /* enable PCH clock reference source */
2355                 /* XXX need to change the setting for other outputs */
2356                 u32 temp;
2357                 temp = I915_READ(PCH_DREF_CONTROL);
2358                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2359                 temp |= DREF_NONSPREAD_CK505_ENABLE;
2360                 temp &= ~DREF_SSC_SOURCE_MASK;
2361                 temp |= DREF_SSC_SOURCE_ENABLE;
2362                 temp &= ~DREF_SSC1_ENABLE;
2363                 /* if no eDP, disable source output to CPU */
2364                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2365                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2366                 I915_WRITE(PCH_DREF_CONTROL, temp);
2367         }
2368
2369         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2370          * This is an exception to the general rule that mode_set doesn't turn
2371          * things on.
2372          */
2373         if (is_lvds) {
2374                 u32 lvds;
2375
2376                 if (IS_IGDNG(dev))
2377                         lvds_reg = PCH_LVDS;
2378
2379                 lvds = I915_READ(lvds_reg);
2380                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2381                 /* Set the B0-B3 data pairs corresponding to whether we're going to
2382                  * set the DPLLs for dual-channel mode or not.
2383                  */
2384                 if (clock.p2 == 7)
2385                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2386                 else
2387                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2388
2389                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2390                  * appropriately here, but we need to look more thoroughly into how
2391                  * panels behave in the two modes.
2392                  */
2393
2394                 I915_WRITE(lvds_reg, lvds);
2395                 I915_READ(lvds_reg);
2396         }
2397         if (is_dp)
2398                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2399
2400         I915_WRITE(fp_reg, fp);
2401         I915_WRITE(dpll_reg, dpll);
2402         I915_READ(dpll_reg);
2403         /* Wait for the clocks to stabilize. */
2404         udelay(150);
2405
2406         if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2407                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2408                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2409                            ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2410         } else {
2411                 /* write it again -- the BIOS does, after all */
2412                 I915_WRITE(dpll_reg, dpll);
2413         }
2414         I915_READ(dpll_reg);
2415         /* Wait for the clocks to stabilize. */
2416         udelay(150);
2417
2418         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2419                    ((adjusted_mode->crtc_htotal - 1) << 16));
2420         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2421                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
2422         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2423                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
2424         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2425                    ((adjusted_mode->crtc_vtotal - 1) << 16));
2426         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2427                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
2428         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2429                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
2430         /* pipesrc and dspsize control the size that is scaled from, which should
2431          * always be the user's requested size.
2432          */
2433         if (!IS_IGDNG(dev)) {
2434                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2435                                 (mode->hdisplay - 1));
2436                 I915_WRITE(dsppos_reg, 0);
2437         }
2438         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2439
2440         if (IS_IGDNG(dev)) {
2441                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2442                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2443                 I915_WRITE(link_m1_reg, m_n.link_m);
2444                 I915_WRITE(link_n1_reg, m_n.link_n);
2445
2446                  /* enable FDI RX PLL too */
2447                 temp = I915_READ(fdi_rx_reg);
2448                 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2449                 udelay(200);
2450         }
2451
2452         I915_WRITE(pipeconf_reg, pipeconf);
2453         I915_READ(pipeconf_reg);
2454
2455         intel_wait_for_vblank(dev);
2456
2457         I915_WRITE(dspcntr_reg, dspcntr);
2458
2459         /* Flush the plane changes */
2460         ret = intel_pipe_set_base(crtc, x, y, old_fb);
2461
2462         intel_update_watermarks(dev);
2463
2464         drm_vblank_post_modeset(dev, pipe);
2465
2466         return ret;
2467 }
2468
2469 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2470 void intel_crtc_load_lut(struct drm_crtc *crtc)
2471 {
2472         struct drm_device *dev = crtc->dev;
2473         struct drm_i915_private *dev_priv = dev->dev_private;
2474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2475         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2476         int i;
2477
2478         /* The clocks have to be on to load the palette. */
2479         if (!crtc->enabled)
2480                 return;
2481
2482         /* use legacy palette for IGDNG */
2483         if (IS_IGDNG(dev))
2484                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2485                                                    LGC_PALETTE_B;
2486
2487         for (i = 0; i < 256; i++) {
2488                 I915_WRITE(palreg + 4 * i,
2489                            (intel_crtc->lut_r[i] << 16) |
2490                            (intel_crtc->lut_g[i] << 8) |
2491                            intel_crtc->lut_b[i]);
2492         }
2493 }
2494
2495 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2496                                  struct drm_file *file_priv,
2497                                  uint32_t handle,
2498                                  uint32_t width, uint32_t height)
2499 {
2500         struct drm_device *dev = crtc->dev;
2501         struct drm_i915_private *dev_priv = dev->dev_private;
2502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503         struct drm_gem_object *bo;
2504         struct drm_i915_gem_object *obj_priv;
2505         int pipe = intel_crtc->pipe;
2506         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2507         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2508         uint32_t temp = I915_READ(control);
2509         size_t addr;
2510         int ret;
2511
2512         DRM_DEBUG("\n");
2513
2514         /* if we want to turn off the cursor ignore width and height */
2515         if (!handle) {
2516                 DRM_DEBUG("cursor off\n");
2517                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2518                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2519                         temp |= CURSOR_MODE_DISABLE;
2520                 } else {
2521                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2522                 }
2523                 addr = 0;
2524                 bo = NULL;
2525                 mutex_lock(&dev->struct_mutex);
2526                 goto finish;
2527         }
2528
2529         /* Currently we only support 64x64 cursors */
2530         if (width != 64 || height != 64) {
2531                 DRM_ERROR("we currently only support 64x64 cursors\n");
2532                 return -EINVAL;
2533         }
2534
2535         bo = drm_gem_object_lookup(dev, file_priv, handle);
2536         if (!bo)
2537                 return -ENOENT;
2538
2539         obj_priv = bo->driver_private;
2540
2541         if (bo->size < width * height * 4) {
2542                 DRM_ERROR("buffer is to small\n");
2543                 ret = -ENOMEM;
2544                 goto fail;
2545         }
2546
2547         /* we only need to pin inside GTT if cursor is non-phy */
2548         mutex_lock(&dev->struct_mutex);
2549         if (!dev_priv->cursor_needs_physical) {
2550                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2551                 if (ret) {
2552                         DRM_ERROR("failed to pin cursor bo\n");
2553                         goto fail_locked;
2554                 }
2555                 addr = obj_priv->gtt_offset;
2556         } else {
2557                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2558                 if (ret) {
2559                         DRM_ERROR("failed to attach phys object\n");
2560                         goto fail_locked;
2561                 }
2562                 addr = obj_priv->phys_obj->handle->busaddr;
2563         }
2564
2565         if (!IS_I9XX(dev))
2566                 I915_WRITE(CURSIZE, (height << 12) | width);
2567
2568         /* Hooray for CUR*CNTR differences */
2569         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2570                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2571                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2572                 temp |= (pipe << 28); /* Connect to correct pipe */
2573         } else {
2574                 temp &= ~(CURSOR_FORMAT_MASK);
2575                 temp |= CURSOR_ENABLE;
2576                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2577         }
2578
2579  finish:
2580         I915_WRITE(control, temp);
2581         I915_WRITE(base, addr);
2582
2583         if (intel_crtc->cursor_bo) {
2584                 if (dev_priv->cursor_needs_physical) {
2585                         if (intel_crtc->cursor_bo != bo)
2586                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2587                 } else
2588                         i915_gem_object_unpin(intel_crtc->cursor_bo);
2589                 drm_gem_object_unreference(intel_crtc->cursor_bo);
2590         }
2591         mutex_unlock(&dev->struct_mutex);
2592
2593         intel_crtc->cursor_addr = addr;
2594         intel_crtc->cursor_bo = bo;
2595
2596         return 0;
2597 fail:
2598         mutex_lock(&dev->struct_mutex);
2599 fail_locked:
2600         drm_gem_object_unreference(bo);
2601         mutex_unlock(&dev->struct_mutex);
2602         return ret;
2603 }
2604
2605 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2606 {
2607         struct drm_device *dev = crtc->dev;
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2610         int pipe = intel_crtc->pipe;
2611         uint32_t temp = 0;
2612         uint32_t adder;
2613
2614         if (x < 0) {
2615                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2616                 x = -x;
2617         }
2618         if (y < 0) {
2619                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2620                 y = -y;
2621         }
2622
2623         temp |= x << CURSOR_X_SHIFT;
2624         temp |= y << CURSOR_Y_SHIFT;
2625
2626         adder = intel_crtc->cursor_addr;
2627         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2628         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2629
2630         return 0;
2631 }
2632
2633 /** Sets the color ramps on behalf of RandR */
2634 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2635                                  u16 blue, int regno)
2636 {
2637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638
2639         intel_crtc->lut_r[regno] = red >> 8;
2640         intel_crtc->lut_g[regno] = green >> 8;
2641         intel_crtc->lut_b[regno] = blue >> 8;
2642 }
2643
2644 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2645                                  u16 *blue, uint32_t size)
2646 {
2647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2648         int i;
2649
2650         if (size != 256)
2651                 return;
2652
2653         for (i = 0; i < 256; i++) {
2654                 intel_crtc->lut_r[i] = red[i] >> 8;
2655                 intel_crtc->lut_g[i] = green[i] >> 8;
2656                 intel_crtc->lut_b[i] = blue[i] >> 8;
2657         }
2658
2659         intel_crtc_load_lut(crtc);
2660 }
2661
2662 /**
2663  * Get a pipe with a simple mode set on it for doing load-based monitor
2664  * detection.
2665  *
2666  * It will be up to the load-detect code to adjust the pipe as appropriate for
2667  * its requirements.  The pipe will be connected to no other outputs.
2668  *
2669  * Currently this code will only succeed if there is a pipe with no outputs
2670  * configured for it.  In the future, it could choose to temporarily disable
2671  * some outputs to free up a pipe for its use.
2672  *
2673  * \return crtc, or NULL if no pipes are available.
2674  */
2675
2676 /* VESA 640x480x72Hz mode to set on the pipe */
2677 static struct drm_display_mode load_detect_mode = {
2678         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2679                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2680 };
2681
2682 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2683                                             struct drm_display_mode *mode,
2684                                             int *dpms_mode)
2685 {
2686         struct intel_crtc *intel_crtc;
2687         struct drm_crtc *possible_crtc;
2688         struct drm_crtc *supported_crtc =NULL;
2689         struct drm_encoder *encoder = &intel_output->enc;
2690         struct drm_crtc *crtc = NULL;
2691         struct drm_device *dev = encoder->dev;
2692         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2693         struct drm_crtc_helper_funcs *crtc_funcs;
2694         int i = -1;
2695
2696         /*
2697          * Algorithm gets a little messy:
2698          *   - if the connector already has an assigned crtc, use it (but make
2699          *     sure it's on first)
2700          *   - try to find the first unused crtc that can drive this connector,
2701          *     and use that if we find one
2702          *   - if there are no unused crtcs available, try to use the first
2703          *     one we found that supports the connector
2704          */
2705
2706         /* See if we already have a CRTC for this connector */
2707         if (encoder->crtc) {
2708                 crtc = encoder->crtc;
2709                 /* Make sure the crtc and connector are running */
2710                 intel_crtc = to_intel_crtc(crtc);
2711                 *dpms_mode = intel_crtc->dpms_mode;
2712                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2713                         crtc_funcs = crtc->helper_private;
2714                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2715                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2716                 }
2717                 return crtc;
2718         }
2719
2720         /* Find an unused one (if possible) */
2721         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2722                 i++;
2723                 if (!(encoder->possible_crtcs & (1 << i)))
2724                         continue;
2725                 if (!possible_crtc->enabled) {
2726                         crtc = possible_crtc;
2727                         break;
2728                 }
2729                 if (!supported_crtc)
2730                         supported_crtc = possible_crtc;
2731         }
2732
2733         /*
2734          * If we didn't find an unused CRTC, don't use any.
2735          */
2736         if (!crtc) {
2737                 return NULL;
2738         }
2739
2740         encoder->crtc = crtc;
2741         intel_output->base.encoder = encoder;
2742         intel_output->load_detect_temp = true;
2743
2744         intel_crtc = to_intel_crtc(crtc);
2745         *dpms_mode = intel_crtc->dpms_mode;
2746
2747         if (!crtc->enabled) {
2748                 if (!mode)
2749                         mode = &load_detect_mode;
2750                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2751         } else {
2752                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2753                         crtc_funcs = crtc->helper_private;
2754                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2755                 }
2756
2757                 /* Add this connector to the crtc */
2758                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2759                 encoder_funcs->commit(encoder);
2760         }
2761         /* let the connector get through one full cycle before testing */
2762         intel_wait_for_vblank(dev);
2763
2764         return crtc;
2765 }
2766
2767 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2768 {
2769         struct drm_encoder *encoder = &intel_output->enc;
2770         struct drm_device *dev = encoder->dev;
2771         struct drm_crtc *crtc = encoder->crtc;
2772         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2773         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2774
2775         if (intel_output->load_detect_temp) {
2776                 encoder->crtc = NULL;
2777                 intel_output->base.encoder = NULL;
2778                 intel_output->load_detect_temp = false;
2779                 crtc->enabled = drm_helper_crtc_in_use(crtc);
2780                 drm_helper_disable_unused_functions(dev);
2781         }
2782
2783         /* Switch crtc and output back off if necessary */
2784         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2785                 if (encoder->crtc == crtc)
2786                         encoder_funcs->dpms(encoder, dpms_mode);
2787                 crtc_funcs->dpms(crtc, dpms_mode);
2788         }
2789 }
2790
2791 /* Returns the clock of the currently programmed mode of the given pipe. */
2792 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2793 {
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2796         int pipe = intel_crtc->pipe;
2797         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2798         u32 fp;
2799         intel_clock_t clock;
2800
2801         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2802                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2803         else
2804                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2805
2806         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2807         if (IS_IGD(dev)) {
2808                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2809                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2810         } else {
2811                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2812                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2813         }
2814
2815         if (IS_I9XX(dev)) {
2816                 if (IS_IGD(dev))
2817                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2818                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2819                 else
2820                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2821                                DPLL_FPA01_P1_POST_DIV_SHIFT);
2822
2823                 switch (dpll & DPLL_MODE_MASK) {
2824                 case DPLLB_MODE_DAC_SERIAL:
2825                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2826                                 5 : 10;
2827                         break;
2828                 case DPLLB_MODE_LVDS:
2829                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2830                                 7 : 14;
2831                         break;
2832                 default:
2833                         DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2834                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
2835                         return 0;
2836                 }
2837
2838                 /* XXX: Handle the 100Mhz refclk */
2839                 intel_clock(dev, 96000, &clock);
2840         } else {
2841                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2842
2843                 if (is_lvds) {
2844                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2845                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
2846                         clock.p2 = 14;
2847
2848                         if ((dpll & PLL_REF_INPUT_MASK) ==
2849                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2850                                 /* XXX: might not be 66MHz */
2851                                 intel_clock(dev, 66000, &clock);
2852                         } else
2853                                 intel_clock(dev, 48000, &clock);
2854                 } else {
2855                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
2856                                 clock.p1 = 2;
2857                         else {
2858                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2859                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2860                         }
2861                         if (dpll & PLL_P2_DIVIDE_BY_4)
2862                                 clock.p2 = 4;
2863                         else
2864                                 clock.p2 = 2;
2865
2866                         intel_clock(dev, 48000, &clock);
2867                 }
2868         }
2869
2870         /* XXX: It would be nice to validate the clocks, but we can't reuse
2871          * i830PllIsValid() because it relies on the xf86_config connector
2872          * configuration being accurate, which it isn't necessarily.
2873          */
2874
2875         return clock.dot;
2876 }
2877
2878 /** Returns the currently programmed mode of the given pipe. */
2879 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2880                                              struct drm_crtc *crtc)
2881 {
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2884         int pipe = intel_crtc->pipe;
2885         struct drm_display_mode *mode;
2886         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2887         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2888         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2889         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2890
2891         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2892         if (!mode)
2893                 return NULL;
2894
2895         mode->clock = intel_crtc_clock_get(dev, crtc);
2896         mode->hdisplay = (htot & 0xffff) + 1;
2897         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2898         mode->hsync_start = (hsync & 0xffff) + 1;
2899         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2900         mode->vdisplay = (vtot & 0xffff) + 1;
2901         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2902         mode->vsync_start = (vsync & 0xffff) + 1;
2903         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2904
2905         drm_mode_set_name(mode);
2906         drm_mode_set_crtcinfo(mode, 0);
2907
2908         return mode;
2909 }
2910
2911 static void intel_crtc_destroy(struct drm_crtc *crtc)
2912 {
2913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2914
2915         if (intel_crtc->mode_set.mode)
2916                 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
2917         drm_crtc_cleanup(crtc);
2918         kfree(intel_crtc);
2919 }
2920
2921 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2922         .dpms = intel_crtc_dpms,
2923         .mode_fixup = intel_crtc_mode_fixup,
2924         .mode_set = intel_crtc_mode_set,
2925         .mode_set_base = intel_pipe_set_base,
2926         .prepare = intel_crtc_prepare,
2927         .commit = intel_crtc_commit,
2928 };
2929
2930 static const struct drm_crtc_funcs intel_crtc_funcs = {
2931         .cursor_set = intel_crtc_cursor_set,
2932         .cursor_move = intel_crtc_cursor_move,
2933         .gamma_set = intel_crtc_gamma_set,
2934         .set_config = drm_crtc_helper_set_config,
2935         .destroy = intel_crtc_destroy,
2936 };
2937
2938
2939 static void intel_crtc_init(struct drm_device *dev, int pipe)
2940 {
2941         struct intel_crtc *intel_crtc;
2942         int i;
2943
2944         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2945         if (intel_crtc == NULL)
2946                 return;
2947
2948         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2949
2950         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2951         intel_crtc->pipe = pipe;
2952         intel_crtc->plane = pipe;
2953         for (i = 0; i < 256; i++) {
2954                 intel_crtc->lut_r[i] = i;
2955                 intel_crtc->lut_g[i] = i;
2956                 intel_crtc->lut_b[i] = i;
2957         }
2958
2959         intel_crtc->cursor_addr = 0;
2960         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2961         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2962
2963         intel_crtc->mode_set.crtc = &intel_crtc->base;
2964         intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2965         intel_crtc->mode_set.num_connectors = 0;
2966
2967         if (i915_fbpercrtc) {
2968
2969
2970
2971         }
2972 }
2973
2974 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2975                                 struct drm_file *file_priv)
2976 {
2977         drm_i915_private_t *dev_priv = dev->dev_private;
2978         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2979         struct drm_crtc *crtc = NULL;
2980         int pipe = -1;
2981
2982         if (!dev_priv) {
2983                 DRM_ERROR("called with no initialization\n");
2984                 return -EINVAL;
2985         }
2986
2987         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2988                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2989                 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2990                         pipe = intel_crtc->pipe;
2991                         break;
2992                 }
2993         }
2994
2995         if (pipe == -1) {
2996                 DRM_ERROR("no such CRTC id\n");
2997                 return -EINVAL;
2998         }
2999
3000         pipe_from_crtc_id->pipe = pipe;
3001
3002        return 0;
3003 }
3004
3005 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
3006 {
3007         struct drm_crtc *crtc = NULL;
3008
3009         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3010                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011                 if (intel_crtc->pipe == pipe)
3012                         break;
3013         }
3014         return crtc;
3015 }
3016
3017 static int intel_connector_clones(struct drm_device *dev, int type_mask)
3018 {
3019         int index_mask = 0;
3020         struct drm_connector *connector;
3021         int entry = 0;
3022
3023         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3024                 struct intel_output *intel_output = to_intel_output(connector);
3025                 if (type_mask & (1 << intel_output->type))
3026                         index_mask |= (1 << entry);
3027                 entry++;
3028         }
3029         return index_mask;
3030 }
3031
3032
3033 static void intel_setup_outputs(struct drm_device *dev)
3034 {
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct drm_connector *connector;
3037
3038         intel_crt_init(dev);
3039
3040         /* Set up integrated LVDS */
3041         if (IS_MOBILE(dev) && !IS_I830(dev))
3042                 intel_lvds_init(dev);
3043
3044         if (IS_IGDNG(dev)) {
3045                 int found;
3046
3047                 if (I915_READ(HDMIB) & PORT_DETECTED) {
3048                         /* check SDVOB */
3049                         /* found = intel_sdvo_init(dev, HDMIB); */
3050                         found = 0;
3051                         if (!found)
3052                                 intel_hdmi_init(dev, HDMIB);
3053                 }
3054
3055                 if (I915_READ(HDMIC) & PORT_DETECTED)
3056                         intel_hdmi_init(dev, HDMIC);
3057
3058                 if (I915_READ(HDMID) & PORT_DETECTED)
3059                         intel_hdmi_init(dev, HDMID);
3060
3061         } else if (IS_I9XX(dev)) {
3062                 int found;
3063                 u32 reg;
3064
3065                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3066                         found = intel_sdvo_init(dev, SDVOB);
3067                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3068                                 intel_hdmi_init(dev, SDVOB);
3069                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3070                                 intel_dp_init(dev, DP_B);
3071                 }
3072
3073                 /* Before G4X SDVOC doesn't have its own detect register */
3074                 if (IS_G4X(dev))
3075                         reg = SDVOC;
3076                 else
3077                         reg = SDVOB;
3078
3079                 if (I915_READ(reg) & SDVO_DETECTED) {
3080                         found = intel_sdvo_init(dev, SDVOC);
3081                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3082                                 intel_hdmi_init(dev, SDVOC);
3083                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
3084                                 intel_dp_init(dev, DP_C);
3085                 }
3086                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3087                         intel_dp_init(dev, DP_D);
3088         } else
3089                 intel_dvo_init(dev);
3090
3091         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3092                 intel_tv_init(dev);
3093
3094         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3095                 struct intel_output *intel_output = to_intel_output(connector);
3096                 struct drm_encoder *encoder = &intel_output->enc;
3097                 int crtc_mask = 0, clone_mask = 0;
3098
3099                 /* valid crtcs */
3100                 switch(intel_output->type) {
3101                 case INTEL_OUTPUT_HDMI:
3102                         crtc_mask = ((1 << 0)|
3103                                      (1 << 1));
3104                         clone_mask = ((1 << INTEL_OUTPUT_HDMI));
3105                         break;
3106                 case INTEL_OUTPUT_DVO:
3107                 case INTEL_OUTPUT_SDVO:
3108                         crtc_mask = ((1 << 0)|
3109                                      (1 << 1));
3110                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3111                                       (1 << INTEL_OUTPUT_DVO) |
3112                                       (1 << INTEL_OUTPUT_SDVO));
3113                         break;
3114                 case INTEL_OUTPUT_ANALOG:
3115                         crtc_mask = ((1 << 0)|
3116                                      (1 << 1));
3117                         clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3118                                       (1 << INTEL_OUTPUT_DVO) |
3119                                       (1 << INTEL_OUTPUT_SDVO));
3120                         break;
3121                 case INTEL_OUTPUT_LVDS:
3122                         crtc_mask = (1 << 1);
3123                         clone_mask = (1 << INTEL_OUTPUT_LVDS);
3124                         break;
3125                 case INTEL_OUTPUT_TVOUT:
3126                         crtc_mask = ((1 << 0) |
3127                                      (1 << 1));
3128                         clone_mask = (1 << INTEL_OUTPUT_TVOUT);
3129                         break;
3130                 case INTEL_OUTPUT_DISPLAYPORT:
3131                         crtc_mask = ((1 << 0) |
3132                                      (1 << 1));
3133                         clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3134                         break;
3135                 }
3136                 encoder->possible_crtcs = crtc_mask;
3137                 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
3138         }
3139 }
3140
3141 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3142 {
3143         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3144         struct drm_device *dev = fb->dev;
3145
3146         if (fb->fbdev)
3147                 intelfb_remove(dev, fb);
3148
3149         drm_framebuffer_cleanup(fb);
3150         mutex_lock(&dev->struct_mutex);
3151         drm_gem_object_unreference(intel_fb->obj);
3152         mutex_unlock(&dev->struct_mutex);
3153
3154         kfree(intel_fb);
3155 }
3156
3157 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3158                                                 struct drm_file *file_priv,
3159                                                 unsigned int *handle)
3160 {
3161         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3162         struct drm_gem_object *object = intel_fb->obj;
3163
3164         return drm_gem_handle_create(file_priv, object, handle);
3165 }
3166
3167 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3168         .destroy = intel_user_framebuffer_destroy,
3169         .create_handle = intel_user_framebuffer_create_handle,
3170 };
3171
3172 int intel_framebuffer_create(struct drm_device *dev,
3173                              struct drm_mode_fb_cmd *mode_cmd,
3174                              struct drm_framebuffer **fb,
3175                              struct drm_gem_object *obj)
3176 {
3177         struct intel_framebuffer *intel_fb;
3178         int ret;
3179
3180         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3181         if (!intel_fb)
3182                 return -ENOMEM;
3183
3184         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3185         if (ret) {
3186                 DRM_ERROR("framebuffer init failed %d\n", ret);
3187                 return ret;
3188         }
3189
3190         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3191
3192         intel_fb->obj = obj;
3193
3194         *fb = &intel_fb->base;
3195
3196         return 0;
3197 }
3198
3199
3200 static struct drm_framebuffer *
3201 intel_user_framebuffer_create(struct drm_device *dev,
3202                               struct drm_file *filp,
3203                               struct drm_mode_fb_cmd *mode_cmd)
3204 {
3205         struct drm_gem_object *obj;
3206         struct drm_framebuffer *fb;
3207         int ret;
3208
3209         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3210         if (!obj)
3211                 return NULL;
3212
3213         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3214         if (ret) {
3215                 mutex_lock(&dev->struct_mutex);
3216                 drm_gem_object_unreference(obj);
3217                 mutex_unlock(&dev->struct_mutex);
3218                 return NULL;
3219         }
3220
3221         return fb;
3222 }
3223
3224 static const struct drm_mode_config_funcs intel_mode_funcs = {
3225         .fb_create = intel_user_framebuffer_create,
3226         .fb_changed = intelfb_probe,
3227 };
3228
3229 void intel_modeset_init(struct drm_device *dev)
3230 {
3231         int num_pipe;
3232         int i;
3233
3234         drm_mode_config_init(dev);
3235
3236         dev->mode_config.min_width = 0;
3237         dev->mode_config.min_height = 0;
3238
3239         dev->mode_config.funcs = (void *)&intel_mode_funcs;
3240
3241         if (IS_I965G(dev)) {
3242                 dev->mode_config.max_width = 8192;
3243                 dev->mode_config.max_height = 8192;
3244         } else if (IS_I9XX(dev)) {
3245                 dev->mode_config.max_width = 4096;
3246                 dev->mode_config.max_height = 4096;
3247         } else {
3248                 dev->mode_config.max_width = 2048;
3249                 dev->mode_config.max_height = 2048;
3250         }
3251
3252         /* set memory base */
3253         if (IS_I9XX(dev))
3254                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
3255         else
3256                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
3257
3258         if (IS_MOBILE(dev) || IS_I9XX(dev))
3259                 num_pipe = 2;
3260         else
3261                 num_pipe = 1;
3262         DRM_DEBUG("%d display pipe%s available.\n",
3263                   num_pipe, num_pipe > 1 ? "s" : "");
3264
3265         for (i = 0; i < num_pipe; i++) {
3266                 intel_crtc_init(dev, i);
3267         }
3268
3269         intel_setup_outputs(dev);
3270 }
3271
3272 void intel_modeset_cleanup(struct drm_device *dev)
3273 {
3274         drm_mode_config_cleanup(dev);
3275 }
3276
3277
3278 /* current intel driver doesn't take advantage of encoders
3279    always give back the encoder for the connector
3280 */
3281 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3282 {
3283         struct intel_output *intel_output = to_intel_output(connector);
3284
3285         return &intel_output->enc;
3286 }