drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static const intel_limit_t intel_limits_i8xx_dvo = {
 346         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 347         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 348         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 349         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 350         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 351         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 352         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 353         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 354         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 355                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 356         .find_pll = intel_find_best_PLL,
 357 };
 358
 359 static const intel_limit_t intel_limits_i8xx_lvds = {
 360         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 361         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 362         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 363         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 364         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 365         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 366         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 367         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 368         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 369                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 370         .find_pll = intel_find_best_PLL,
 371 };
 372
 373 static const intel_limit_t intel_limits_i9xx_sdvo = {
 374         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 375         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 376         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 377         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 378         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 379         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 380         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 381         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 382         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 383                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 384         .find_pll = intel_find_best_PLL,
 385 };
 386
 387 static const intel_limit_t intel_limits_i9xx_lvds = {
 388         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 389         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 390         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 391         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 392         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 393         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 394         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 395         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 396         /* The single-channel range is 25-112Mhz, and dual-channel
 397          * is 80-224Mhz.  Prefer single channel as much as possible.
 398          */
 399         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 400                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 401         .find_pll = intel_find_best_PLL,
 402 };
 403
 404     /* below parameter and function is for G4X Chipset Family*/
 405 static const intel_limit_t intel_limits_g4x_sdvo = {
 406         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 407         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 408         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 409         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 410         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 411         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 412         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 413         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 414         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 415                  .p2_slow = G4X_P2_SDVO_SLOW,
 416                  .p2_fast = G4X_P2_SDVO_FAST
 417         },
 418         .find_pll = intel_g4x_find_best_PLL,
 419 };
 420
 421 static const intel_limit_t intel_limits_g4x_hdmi = {
 422         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 423         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 424         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 425         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 426         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 427         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 428         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 429         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 430         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 431                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 432                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 433         },
 434         .find_pll = intel_g4x_find_best_PLL,
 435 };
 436
 437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 438         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 439                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 440         .vco = { .min = G4X_VCO_MIN,
 441                  .max = G4X_VCO_MAX },
 442         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 443                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 444         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 445                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 446         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 447                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 448         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 449                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 450         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 451                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 452         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 453                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 454         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 455                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 456                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 457         },
 458         .find_pll = intel_g4x_find_best_PLL,
 459 };
 460
 461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 462         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 463                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 464         .vco = { .min = G4X_VCO_MIN,
 465                  .max = G4X_VCO_MAX },
 466         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 467                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 468         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 469                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 470         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 471                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 472         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 473                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 474         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 475                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 476         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 477                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 478         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 479                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 480                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 481         },
 482         .find_pll = intel_g4x_find_best_PLL,
 483 };
 484
 485 static const intel_limit_t intel_limits_g4x_display_port = {
 486         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 487                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 488         .vco = { .min = G4X_VCO_MIN,
 489                  .max = G4X_VCO_MAX},
 490         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 491                  .max = G4X_N_DISPLAY_PORT_MAX },
 492         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 493                  .max = G4X_M_DISPLAY_PORT_MAX },
 494         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 495                  .max = G4X_M1_DISPLAY_PORT_MAX },
 496         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 497                  .max = G4X_M2_DISPLAY_PORT_MAX },
 498         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 499                  .max = G4X_P_DISPLAY_PORT_MAX },
 500         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 501                  .max = G4X_P1_DISPLAY_PORT_MAX},
 502         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 503                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 504                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 505         .find_pll = intel_find_pll_g4x_dp,
 506 };
 507
 508 static const intel_limit_t intel_limits_pineview_sdvo = {
 509         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 510         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 511         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 512         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 513         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 514         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 515         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 516         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 517         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 518                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 519         .find_pll = intel_find_best_PLL,
 520 };
 521
 522 static const intel_limit_t intel_limits_pineview_lvds = {
 523         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 524         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 525         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 526         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 527         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 528         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 529         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 530         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 531         /* Pineview only supports single-channel mode. */
 532         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 533                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 534         .find_pll = intel_find_best_PLL,
 535 };
 536
 537 static const intel_limit_t intel_limits_ironlake_dac = {
 538         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 539         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 540         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 541         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 542         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 543         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 544         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 545         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 546         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 547                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 548                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 549         .find_pll = intel_g4x_find_best_PLL,
 550 };
 551
 552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 553         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 554         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 555         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 556         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 557         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 558         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 559         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 560         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 561         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 562                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 563                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 564         .find_pll = intel_g4x_find_best_PLL,
 565 };
 566
 567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 568         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 569         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 570         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 571         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 572         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 573         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 574         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 575         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 576         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 577                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 578                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 579         .find_pll = intel_g4x_find_best_PLL,
 580 };
 581
 582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 583         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 584         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 585         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 586         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 587         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 588         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 589         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 590         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 591         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 592                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 593                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 594         .find_pll = intel_g4x_find_best_PLL,
 595 };
 596
 597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 598         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 599         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 600         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 601         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 602         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 603         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 604         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 605         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 606         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 607                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 608                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 609         .find_pll = intel_g4x_find_best_PLL,
 610 };
 611
 612 static const intel_limit_t intel_limits_ironlake_display_port = {
 613         .dot = { .min = IRONLAKE_DOT_MIN,
 614                  .max = IRONLAKE_DOT_MAX },
 615         .vco = { .min = IRONLAKE_VCO_MIN,
 616                  .max = IRONLAKE_VCO_MAX},
 617         .n   = { .min = IRONLAKE_DP_N_MIN,
 618                  .max = IRONLAKE_DP_N_MAX },
 619         .m   = { .min = IRONLAKE_DP_M_MIN,
 620                  .max = IRONLAKE_DP_M_MAX },
 621         .m1  = { .min = IRONLAKE_M1_MIN,
 622                  .max = IRONLAKE_M1_MAX },
 623         .m2  = { .min = IRONLAKE_M2_MIN,
 624                  .max = IRONLAKE_M2_MAX },
 625         .p   = { .min = IRONLAKE_DP_P_MIN,
 626                  .max = IRONLAKE_DP_P_MAX },
 627         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 628                  .max = IRONLAKE_DP_P1_MAX},
 629         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 630                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 631                  .p2_fast = IRONLAKE_DP_P2_FAST },
 632         .find_pll = intel_find_pll_ironlake_dp,
 633 };
 634
 635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 636 {
 637         struct drm_device *dev = crtc->dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         const intel_limit_t *limit;
 640         int refclk = 120;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 644                         refclk = 100;
 645
 646                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 647                     LVDS_CLKB_POWER_UP) {
 648                         /* LVDS dual channel */
 649                         if (refclk == 100)
 650                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 651                         else
 652                                 limit = &intel_limits_ironlake_dual_lvds;
 653                 } else {
 654                         if (refclk == 100)
 655                                 limit = &intel_limits_ironlake_single_lvds_100m;
 656                         else
 657                                 limit = &intel_limits_ironlake_single_lvds;
 658                 }
 659         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 660                         HAS_eDP)
 661                 limit = &intel_limits_ironlake_display_port;
 662         else
 663                 limit = &intel_limits_ironlake_dac;
 664
 665         return limit;
 666 }
 667
 668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 669 {
 670         struct drm_device *dev = crtc->dev;
 671         struct drm_i915_private *dev_priv = dev->dev_private;
 672         const intel_limit_t *limit;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 676                     LVDS_CLKB_POWER_UP)
 677                         /* LVDS with dual channel */
 678                         limit = &intel_limits_g4x_dual_channel_lvds;
 679                 else
 680                         /* LVDS with dual channel */
 681                         limit = &intel_limits_g4x_single_channel_lvds;
 682         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 683                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 684                 limit = &intel_limits_g4x_hdmi;
 685         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 686                 limit = &intel_limits_g4x_sdvo;
 687         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 688                 limit = &intel_limits_g4x_display_port;
 689         } else /* The option is for other outputs */
 690                 limit = &intel_limits_i9xx_sdvo;
 691
 692         return limit;
 693 }
 694
 695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 696 {
 697         struct drm_device *dev = crtc->dev;
 698         const intel_limit_t *limit;
 699
 700         if (HAS_PCH_SPLIT(dev))
 701                 limit = intel_ironlake_limit(crtc);
 702         else if (IS_G4X(dev)) {
 703                 limit = intel_g4x_limit(crtc);
 704         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 705                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 706                         limit = &intel_limits_i9xx_lvds;
 707                 else
 708                         limit = &intel_limits_i9xx_sdvo;
 709         } else if (IS_PINEVIEW(dev)) {
 710                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 711                         limit = &intel_limits_pineview_lvds;
 712                 else
 713                         limit = &intel_limits_pineview_sdvo;
 714         } else {
 715                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 716                         limit = &intel_limits_i8xx_lvds;
 717                 else
 718                         limit = &intel_limits_i8xx_dvo;
 719         }
 720         return limit;
 721 }
 722
 723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 724 static void pineview_clock(int refclk, intel_clock_t *clock)
 725 {
 726         clock->m = clock->m2 + 2;
 727         clock->p = clock->p1 * clock->p2;
 728         clock->vco = refclk * clock->m / clock->n;
 729         clock->dot = clock->vco / clock->p;
 730 }
 731
 732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 733 {
 734         if (IS_PINEVIEW(dev)) {
 735                 pineview_clock(refclk, clock);
 736                 return;
 737         }
 738         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 739         clock->p = clock->p1 * clock->p2;
 740         clock->vco = refclk * clock->m / (clock->n + 2);
 741         clock->dot = clock->vco / clock->p;
 742 }
 743
 744 /**
 745  * Returns whether any output on the specified pipe is of the specified type
 746  */
 747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 748 {
 749     struct drm_device *dev = crtc->dev;
 750     struct drm_mode_config *mode_config = &dev->mode_config;
 751     struct drm_encoder *l_entry;
 752
 753     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 754             if (l_entry && l_entry->crtc == crtc) {
 755                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 756                     if (intel_encoder->type == type)
 757                             return true;
 758             }
 759     }
 760     return false;
 761 }
 762
 763 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 764 /**
 765  * Returns whether the given set of divisors are valid for a given refclk with
 766  * the given connectors.
 767  */
 768
 769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 770 {
 771         const intel_limit_t *limit = intel_limit (crtc);
 772         struct drm_device *dev = crtc->dev;
 773
 774         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 775                 INTELPllInvalid ("p1 out of range\n");
 776         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 777                 INTELPllInvalid ("p out of range\n");
 778         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 779                 INTELPllInvalid ("m2 out of range\n");
 780         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 781                 INTELPllInvalid ("m1 out of range\n");
 782         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 783                 INTELPllInvalid ("m1 <= m2\n");
 784         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 785                 INTELPllInvalid ("m out of range\n");
 786         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 787                 INTELPllInvalid ("n out of range\n");
 788         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 789                 INTELPllInvalid ("vco out of range\n");
 790         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 791          * connector, etc., rather than just a single range.
 792          */
 793         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 794                 INTELPllInvalid ("dot out of range\n");
 795
 796         return true;
 797 }
 798
 799 static bool
 800 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 801                     int target, int refclk, intel_clock_t *best_clock)
 802
 803 {
 804         struct drm_device *dev = crtc->dev;
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         intel_clock_t clock;
 807         int err = target;
 808
 809         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 810             (I915_READ(LVDS)) != 0) {
 811                 /*
 812                  * For LVDS, if the panel is on, just rely on its current
 813                  * settings for dual-channel.  We haven't figured out how to
 814                  * reliably set up different single/dual channel state, if we
 815                  * even can.
 816                  */
 817                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 818                     LVDS_CLKB_POWER_UP)
 819                         clock.p2 = limit->p2.p2_fast;
 820                 else
 821                         clock.p2 = limit->p2.p2_slow;
 822         } else {
 823                 if (target < limit->p2.dot_limit)
 824                         clock.p2 = limit->p2.p2_slow;
 825                 else
 826                         clock.p2 = limit->p2.p2_fast;
 827         }
 828
 829         memset (best_clock, 0, sizeof (*best_clock));
 830
 831         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 832              clock.m1++) {
 833                 for (clock.m2 = limit->m2.min;
 834                      clock.m2 <= limit->m2.max; clock.m2++) {
 835                         /* m1 is always 0 in Pineview */
 836                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 837                                 break;
 838                         for (clock.n = limit->n.min;
 839                              clock.n <= limit->n.max; clock.n++) {
 840                                 for (clock.p1 = limit->p1.min;
 841                                         clock.p1 <= limit->p1.max; clock.p1++) {
 842                                         int this_err;
 843
 844                                         intel_clock(dev, refclk, &clock);
 845
 846                                         if (!intel_PLL_is_valid(crtc, &clock))
 847                                                 continue;
 848
 849                                         this_err = abs(clock.dot - target);
 850                                         if (this_err < err) {
 851                                                 *best_clock = clock;
 852                                                 err = this_err;
 853                                         }
 854                                 }
 855                         }
 856                 }
 857         }
 858
 859         return (err != target);
 860 }
 861
 862 static bool
 863 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 864                         int target, int refclk, intel_clock_t *best_clock)
 865 {
 866         struct drm_device *dev = crtc->dev;
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868         intel_clock_t clock;
 869         int max_n;
 870         bool found;
 871         /* approximately equals target * 0.00585 */
 872         int err_most = (target >> 8) + (target >> 9);
 873         found = false;
 874
 875         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 876                 int lvds_reg;
 877
 878                 if (HAS_PCH_SPLIT(dev))
 879                         lvds_reg = PCH_LVDS;
 880                 else
 881                         lvds_reg = LVDS;
 882                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 883                     LVDS_CLKB_POWER_UP)
 884                         clock.p2 = limit->p2.p2_fast;
 885                 else
 886                         clock.p2 = limit->p2.p2_slow;
 887         } else {
 888                 if (target < limit->p2.dot_limit)
 889                         clock.p2 = limit->p2.p2_slow;
 890                 else
 891                         clock.p2 = limit->p2.p2_fast;
 892         }
 893
 894         memset(best_clock, 0, sizeof(*best_clock));
 895         max_n = limit->n.max;
 896         /* based on hardware requirement, prefer smaller n to precision */
 897         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 898                 /* based on hardware requirement, prefere larger m1,m2 */
 899                 for (clock.m1 = limit->m1.max;
 900                      clock.m1 >= limit->m1.min; clock.m1--) {
 901                         for (clock.m2 = limit->m2.max;
 902                              clock.m2 >= limit->m2.min; clock.m2--) {
 903                                 for (clock.p1 = limit->p1.max;
 904                                      clock.p1 >= limit->p1.min; clock.p1--) {
 905                                         int this_err;
 906
 907                                         intel_clock(dev, refclk, &clock);
 908                                         if (!intel_PLL_is_valid(crtc, &clock))
 909                                                 continue;
 910                                         this_err = abs(clock.dot - target) ;
 911                                         if (this_err < err_most) {
 912                                                 *best_clock = clock;
 913                                                 err_most = this_err;
 914                                                 max_n = clock.n;
 915                                                 found = true;
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         return found;
 922 }
 923
 924 static bool
 925 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 926                            int target, int refclk, intel_clock_t *best_clock)
 927 {
 928         struct drm_device *dev = crtc->dev;
 929         intel_clock_t clock;
 930
 931         /* return directly when it is eDP */
 932         if (HAS_eDP)
 933                 return true;
 934
 935         if (target < 200000) {
 936                 clock.n = 1;
 937                 clock.p1 = 2;
 938                 clock.p2 = 10;
 939                 clock.m1 = 12;
 940                 clock.m2 = 9;
 941         } else {
 942                 clock.n = 2;
 943                 clock.p1 = 1;
 944                 clock.p2 = 10;
 945                 clock.m1 = 14;
 946                 clock.m2 = 8;
 947         }
 948         intel_clock(dev, refclk, &clock);
 949         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 950         return true;
 951 }
 952
 953 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 954 static bool
 955 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 956                       int target, int refclk, intel_clock_t *best_clock)
 957 {
 958     intel_clock_t clock;
 959     if (target < 200000) {
 960         clock.p1 = 2;
 961         clock.p2 = 10;
 962         clock.n = 2;
 963         clock.m1 = 23;
 964         clock.m2 = 8;
 965     } else {
 966         clock.p1 = 1;
 967         clock.p2 = 10;
 968         clock.n = 1;
 969         clock.m1 = 14;
 970         clock.m2 = 2;
 971     }
 972     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 973     clock.p = (clock.p1 * clock.p2);
 974     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 975     clock.vco = 0;
 976     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 977     return true;
 978 }
 979
 980 /**
 981  * intel_wait_for_vblank - wait for vblank on a given pipe
 982  * @dev: drm device
 983  * @pipe: pipe to wait for
 984  *
 985  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 986  * mode setting code.
 987  */
 988 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 989 {
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 992
 993         /* Clear existing vblank status. Note this will clear any other
 994          * sticky status fields as well.
 995          *
 996          * This races with i915_driver_irq_handler() with the result
 997          * that either function could miss a vblank event.  Here it is not
 998          * fatal, as we will either wait upon the next vblank interrupt or
 999          * timeout.  Generally speaking intel_wait_for_vblank() is only
1000          * called during modeset at which time the GPU should be idle and
1001          * should *not* be performing page flips and thus not waiting on
1002          * vblanks...
1003          * Currently, the result of us stealing a vblank from the irq
1004          * handler is that a single frame will be skipped during swapbuffers.
1005          */
1006         I915_WRITE(pipestat_reg,
1007                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009         /* Wait for vblank interrupt bit to set */
1010         if (wait_for((I915_READ(pipestat_reg) &
1011                       PIPE_VBLANK_INTERRUPT_STATUS),
1012                      50, 0))
1013                 DRM_DEBUG_KMS("vblank wait timed out\n");
1014 }
1015
1016 /**
1017  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1018  * @dev: drm device
1019  * @pipe: pipe to wait for
1020  *
1021  * After disabling a pipe, we can't wait for vblank in the usual way,
1022  * spinning on the vblank interrupt status bit, since we won't actually
1023  * see an interrupt when the pipe is disabled.
1024  *
1025  * So this function waits for the display line value to settle (it
1026  * usually ends up stopping at the start of the next frame).
1027  */
1028 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1029 {
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1032         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033         u32 last_line;
1034
1035         /* Wait for the display line to settle */
1036         do {
1037                 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1038                 mdelay(5);
1039         } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1040                  time_after(timeout, jiffies));
1041
1042         if (time_after(jiffies, timeout))
1043                 DRM_DEBUG_KMS("vblank wait timed out\n");
1044 }
1045
1046 /* Parameters have changed, update FBC info */
1047 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1048 {
1049         struct drm_device *dev = crtc->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         struct drm_framebuffer *fb = crtc->fb;
1052         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1053         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1055         int plane, i;
1056         u32 fbc_ctl, fbc_ctl2;
1057
1058         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1059
1060         if (fb->pitch < dev_priv->cfb_pitch)
1061                 dev_priv->cfb_pitch = fb->pitch;
1062
1063         /* FBC_CTL wants 64B units */
1064         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1065         dev_priv->cfb_fence = obj_priv->fence_reg;
1066         dev_priv->cfb_plane = intel_crtc->plane;
1067         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1068
1069         /* Clear old tags */
1070         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1071                 I915_WRITE(FBC_TAG + (i * 4), 0);
1072
1073         /* Set it up... */
1074         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1075         if (obj_priv->tiling_mode != I915_TILING_NONE)
1076                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1077         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1078         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1079
1080         /* enable it... */
1081         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1082         if (IS_I945GM(dev))
1083                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1084         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1085         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1086         if (obj_priv->tiling_mode != I915_TILING_NONE)
1087                 fbc_ctl |= dev_priv->cfb_fence;
1088         I915_WRITE(FBC_CONTROL, fbc_ctl);
1089
1090         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1091                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1092 }
1093
1094 void i8xx_disable_fbc(struct drm_device *dev)
1095 {
1096         struct drm_i915_private *dev_priv = dev->dev_private;
1097         u32 fbc_ctl;
1098
1099         if (!I915_HAS_FBC(dev))
1100                 return;
1101
1102         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1103                 return; /* Already off, just return */
1104
1105         /* Disable compression */
1106         fbc_ctl = I915_READ(FBC_CONTROL);
1107         fbc_ctl &= ~FBC_CTL_EN;
1108         I915_WRITE(FBC_CONTROL, fbc_ctl);
1109
1110         /* Wait for compressing bit to clear */
1111         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1112                 DRM_DEBUG_KMS("FBC idle timed out\n");
1113                 return;
1114         }
1115
1116         DRM_DEBUG_KMS("disabled FBC\n");
1117 }
1118
1119 static bool i8xx_fbc_enabled(struct drm_device *dev)
1120 {
1121         struct drm_i915_private *dev_priv = dev->dev_private;
1122
1123         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1124 }
1125
1126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127 {
1128         struct drm_device *dev = crtc->dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130         struct drm_framebuffer *fb = crtc->fb;
1131         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1132         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1134         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1135                      DPFC_CTL_PLANEB);
1136         unsigned long stall_watermark = 200;
1137         u32 dpfc_ctl;
1138
1139         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1140         dev_priv->cfb_fence = obj_priv->fence_reg;
1141         dev_priv->cfb_plane = intel_crtc->plane;
1142
1143         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1144         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1145                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1146                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1147         } else {
1148                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1149         }
1150
1151         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1152         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1153                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1154                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1155         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1156
1157         /* enable it... */
1158         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1159
1160         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1161 }
1162
1163 void g4x_disable_fbc(struct drm_device *dev)
1164 {
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         u32 dpfc_ctl;
1167
1168         /* Disable compression */
1169         dpfc_ctl = I915_READ(DPFC_CONTROL);
1170         dpfc_ctl &= ~DPFC_CTL_EN;
1171         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1172
1173         DRM_DEBUG_KMS("disabled FBC\n");
1174 }
1175
1176 static bool g4x_fbc_enabled(struct drm_device *dev)
1177 {
1178         struct drm_i915_private *dev_priv = dev->dev_private;
1179
1180         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1181 }
1182
1183 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1184 {
1185         struct drm_device *dev = crtc->dev;
1186         struct drm_i915_private *dev_priv = dev->dev_private;
1187         struct drm_framebuffer *fb = crtc->fb;
1188         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1189         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1191         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1192                                                DPFC_CTL_PLANEB;
1193         unsigned long stall_watermark = 200;
1194         u32 dpfc_ctl;
1195
1196         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1197         dev_priv->cfb_fence = obj_priv->fence_reg;
1198         dev_priv->cfb_plane = intel_crtc->plane;
1199
1200         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1201         dpfc_ctl &= DPFC_RESERVED;
1202         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1203         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1204                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1205                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1206         } else {
1207                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1208         }
1209
1210         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1211         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1212                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1213                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1214         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1215         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1216         /* enable it... */
1217         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1218                    DPFC_CTL_EN);
1219
1220         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1221 }
1222
1223 void ironlake_disable_fbc(struct drm_device *dev)
1224 {
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226         u32 dpfc_ctl;
1227
1228         /* Disable compression */
1229         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1230         dpfc_ctl &= ~DPFC_CTL_EN;
1231         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1232
1233         DRM_DEBUG_KMS("disabled FBC\n");
1234 }
1235
1236 static bool ironlake_fbc_enabled(struct drm_device *dev)
1237 {
1238         struct drm_i915_private *dev_priv = dev->dev_private;
1239
1240         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1241 }
1242
1243 bool intel_fbc_enabled(struct drm_device *dev)
1244 {
1245         struct drm_i915_private *dev_priv = dev->dev_private;
1246
1247         if (!dev_priv->display.fbc_enabled)
1248                 return false;
1249
1250         return dev_priv->display.fbc_enabled(dev);
1251 }
1252
1253 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1254 {
1255         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1256
1257         if (!dev_priv->display.enable_fbc)
1258                 return;
1259
1260         dev_priv->display.enable_fbc(crtc, interval);
1261 }
1262
1263 void intel_disable_fbc(struct drm_device *dev)
1264 {
1265         struct drm_i915_private *dev_priv = dev->dev_private;
1266
1267         if (!dev_priv->display.disable_fbc)
1268                 return;
1269
1270         dev_priv->display.disable_fbc(dev);
1271 }
1272
1273 /**
1274  * intel_update_fbc - enable/disable FBC as needed
1275  * @crtc: CRTC to point the compressor at
1276  * @mode: mode in use
1277  *
1278  * Set up the framebuffer compression hardware at mode set time.  We
1279  * enable it if possible:
1280  *   - plane A only (on pre-965)
1281  *   - no pixel mulitply/line duplication
1282  *   - no alpha buffer discard
1283  *   - no dual wide
1284  *   - framebuffer <= 2048 in width, 1536 in height
1285  *
1286  * We can't assume that any compression will take place (worst case),
1287  * so the compressed buffer has to be the same size as the uncompressed
1288  * one.  It also must reside (along with the line length buffer) in
1289  * stolen memory.
1290  *
1291  * We need to enable/disable FBC on a global basis.
1292  */
1293 static void intel_update_fbc(struct drm_crtc *crtc,
1294                              struct drm_display_mode *mode)
1295 {
1296         struct drm_device *dev = crtc->dev;
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298         struct drm_framebuffer *fb = crtc->fb;
1299         struct intel_framebuffer *intel_fb;
1300         struct drm_i915_gem_object *obj_priv;
1301         struct drm_crtc *tmp_crtc;
1302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1303         int plane = intel_crtc->plane;
1304         int crtcs_enabled = 0;
1305
1306         DRM_DEBUG_KMS("\n");
1307
1308         if (!i915_powersave)
1309                 return;
1310
1311         if (!I915_HAS_FBC(dev))
1312                 return;
1313
1314         if (!crtc->fb)
1315                 return;
1316
1317         intel_fb = to_intel_framebuffer(fb);
1318         obj_priv = to_intel_bo(intel_fb->obj);
1319
1320         /*
1321          * If FBC is already on, we just have to verify that we can
1322          * keep it that way...
1323          * Need to disable if:
1324          *   - more than one pipe is active
1325          *   - changing FBC params (stride, fence, mode)
1326          *   - new fb is too large to fit in compressed buffer
1327          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1328          */
1329         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1330                 if (tmp_crtc->enabled)
1331                         crtcs_enabled++;
1332         }
1333         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1334         if (crtcs_enabled > 1) {
1335                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1336                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1337                 goto out_disable;
1338         }
1339         if (intel_fb->obj->size > dev_priv->cfb_size) {
1340                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1341                                 "compression\n");
1342                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1343                 goto out_disable;
1344         }
1345         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1346             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1347                 DRM_DEBUG_KMS("mode incompatible with compression, "
1348                                 "disabling\n");
1349                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1350                 goto out_disable;
1351         }
1352         if ((mode->hdisplay > 2048) ||
1353             (mode->vdisplay > 1536)) {
1354                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1355                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1356                 goto out_disable;
1357         }
1358         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1359                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1360                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1361                 goto out_disable;
1362         }
1363         if (obj_priv->tiling_mode != I915_TILING_X) {
1364                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1365                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1366                 goto out_disable;
1367         }
1368
1369         /* If the kernel debugger is active, always disable compression */
1370         if (in_dbg_master())
1371                 goto out_disable;
1372
1373         if (intel_fbc_enabled(dev)) {
1374                 /* We can re-enable it in this case, but need to update pitch */
1375                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1376                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1377                     (plane != dev_priv->cfb_plane))
1378                         intel_disable_fbc(dev);
1379         }
1380
1381         /* Now try to turn it back on if possible */
1382         if (!intel_fbc_enabled(dev))
1383                 intel_enable_fbc(crtc, 500);
1384
1385         return;
1386
1387 out_disable:
1388         /* Multiple disables should be harmless */
1389         if (intel_fbc_enabled(dev)) {
1390                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1391                 intel_disable_fbc(dev);
1392         }
1393 }
1394
1395 int
1396 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1397 {
1398         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1399         u32 alignment;
1400         int ret;
1401
1402         switch (obj_priv->tiling_mode) {
1403         case I915_TILING_NONE:
1404                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1405                         alignment = 128 * 1024;
1406                 else if (IS_I965G(dev))
1407                         alignment = 4 * 1024;
1408                 else
1409                         alignment = 64 * 1024;
1410                 break;
1411         case I915_TILING_X:
1412                 /* pin() will align the object as required by fence */
1413                 alignment = 0;
1414                 break;
1415         case I915_TILING_Y:
1416                 /* FIXME: Is this true? */
1417                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1418                 return -EINVAL;
1419         default:
1420                 BUG();
1421         }
1422
1423         ret = i915_gem_object_pin(obj, alignment);
1424         if (ret != 0)
1425                 return ret;
1426
1427         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1428          * fence, whereas 965+ only requires a fence if using
1429          * framebuffer compression.  For simplicity, we always install
1430          * a fence as the cost is not that onerous.
1431          */
1432         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1433             obj_priv->tiling_mode != I915_TILING_NONE) {
1434                 ret = i915_gem_object_get_fence_reg(obj);
1435                 if (ret != 0) {
1436                         i915_gem_object_unpin(obj);
1437                         return ret;
1438                 }
1439         }
1440
1441         return 0;
1442 }
1443
1444 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1445 static int
1446 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1447                            int x, int y)
1448 {
1449         struct drm_device *dev = crtc->dev;
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1452         struct intel_framebuffer *intel_fb;
1453         struct drm_i915_gem_object *obj_priv;
1454         struct drm_gem_object *obj;
1455         int plane = intel_crtc->plane;
1456         unsigned long Start, Offset;
1457         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1458         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1459         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1460         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1461         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1462         u32 dspcntr;
1463
1464         switch (plane) {
1465         case 0:
1466         case 1:
1467                 break;
1468         default:
1469                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1470                 return -EINVAL;
1471         }
1472
1473         intel_fb = to_intel_framebuffer(fb);
1474         obj = intel_fb->obj;
1475         obj_priv = to_intel_bo(obj);
1476
1477         dspcntr = I915_READ(dspcntr_reg);
1478         /* Mask out pixel format bits in case we change it */
1479         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1480         switch (fb->bits_per_pixel) {
1481         case 8:
1482                 dspcntr |= DISPPLANE_8BPP;
1483                 break;
1484         case 16:
1485                 if (fb->depth == 15)
1486                         dspcntr |= DISPPLANE_15_16BPP;
1487                 else
1488                         dspcntr |= DISPPLANE_16BPP;
1489                 break;
1490         case 24:
1491         case 32:
1492                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1493                 break;
1494         default:
1495                 DRM_ERROR("Unknown color depth\n");
1496                 return -EINVAL;
1497         }
1498         if (IS_I965G(dev)) {
1499                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1500                         dspcntr |= DISPPLANE_TILED;
1501                 else
1502                         dspcntr &= ~DISPPLANE_TILED;
1503         }
1504
1505         if (IS_IRONLAKE(dev))
1506                 /* must disable */
1507                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1508
1509         I915_WRITE(dspcntr_reg, dspcntr);
1510
1511         Start = obj_priv->gtt_offset;
1512         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1513
1514         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1515         I915_WRITE(dspstride, fb->pitch);
1516         if (IS_I965G(dev)) {
1517                 I915_WRITE(dspbase, Offset);
1518                 I915_READ(dspbase);
1519                 I915_WRITE(dspsurf, Start);
1520                 I915_READ(dspsurf);
1521                 I915_WRITE(dsptileoff, (y << 16) | x);
1522         } else {
1523                 I915_WRITE(dspbase, Start + Offset);
1524                 I915_READ(dspbase);
1525         }
1526
1527         if ((IS_I965G(dev) || plane == 0))
1528                 intel_update_fbc(crtc, &crtc->mode);
1529
1530         intel_wait_for_vblank(dev, intel_crtc->pipe);
1531         intel_increase_pllclock(crtc, true);
1532
1533         return 0;
1534 }
1535
1536 static int
1537 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1538                     struct drm_framebuffer *old_fb)
1539 {
1540         struct drm_device *dev = crtc->dev;
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         struct drm_i915_master_private *master_priv;
1543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1544         struct intel_framebuffer *intel_fb;
1545         struct drm_i915_gem_object *obj_priv;
1546         struct drm_gem_object *obj;
1547         int pipe = intel_crtc->pipe;
1548         int plane = intel_crtc->plane;
1549         unsigned long Start, Offset;
1550         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1551         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1552         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1553         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1554         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1555         u32 dspcntr;
1556         int ret;
1557
1558         /* no fb bound */
1559         if (!crtc->fb) {
1560                 DRM_DEBUG_KMS("No FB bound\n");
1561                 return 0;
1562         }
1563
1564         switch (plane) {
1565         case 0:
1566         case 1:
1567                 break;
1568         default:
1569                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1570                 return -EINVAL;
1571         }
1572
1573         intel_fb = to_intel_framebuffer(crtc->fb);
1574         obj = intel_fb->obj;
1575         obj_priv = to_intel_bo(obj);
1576
1577         mutex_lock(&dev->struct_mutex);
1578         ret = intel_pin_and_fence_fb_obj(dev, obj);
1579         if (ret != 0) {
1580                 mutex_unlock(&dev->struct_mutex);
1581                 return ret;
1582         }
1583
1584         ret = i915_gem_object_set_to_display_plane(obj);
1585         if (ret != 0) {
1586                 i915_gem_object_unpin(obj);
1587                 mutex_unlock(&dev->struct_mutex);
1588                 return ret;
1589         }
1590
1591         dspcntr = I915_READ(dspcntr_reg);
1592         /* Mask out pixel format bits in case we change it */
1593         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1594         switch (crtc->fb->bits_per_pixel) {
1595         case 8:
1596                 dspcntr |= DISPPLANE_8BPP;
1597                 break;
1598         case 16:
1599                 if (crtc->fb->depth == 15)
1600                         dspcntr |= DISPPLANE_15_16BPP;
1601                 else
1602                         dspcntr |= DISPPLANE_16BPP;
1603                 break;
1604         case 24:
1605         case 32:
1606                 if (crtc->fb->depth == 30)
1607                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1608                 else
1609                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1610                 break;
1611         default:
1612                 DRM_ERROR("Unknown color depth\n");
1613                 i915_gem_object_unpin(obj);
1614                 mutex_unlock(&dev->struct_mutex);
1615                 return -EINVAL;
1616         }
1617         if (IS_I965G(dev)) {
1618                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1619                         dspcntr |= DISPPLANE_TILED;
1620                 else
1621                         dspcntr &= ~DISPPLANE_TILED;
1622         }
1623
1624         if (HAS_PCH_SPLIT(dev))
1625                 /* must disable */
1626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1627
1628         I915_WRITE(dspcntr_reg, dspcntr);
1629
1630         Start = obj_priv->gtt_offset;
1631         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1632
1633         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1634                       Start, Offset, x, y, crtc->fb->pitch);
1635         I915_WRITE(dspstride, crtc->fb->pitch);
1636         if (IS_I965G(dev)) {
1637                 I915_WRITE(dspsurf, Start);
1638                 I915_WRITE(dsptileoff, (y << 16) | x);
1639                 I915_WRITE(dspbase, Offset);
1640         } else {
1641                 I915_WRITE(dspbase, Start + Offset);
1642         }
1643         POSTING_READ(dspbase);
1644
1645         if ((IS_I965G(dev) || plane == 0))
1646                 intel_update_fbc(crtc, &crtc->mode);
1647
1648         intel_wait_for_vblank(dev, pipe);
1649
1650         if (old_fb) {
1651                 intel_fb = to_intel_framebuffer(old_fb);
1652                 obj_priv = to_intel_bo(intel_fb->obj);
1653                 i915_gem_object_unpin(intel_fb->obj);
1654         }
1655         intel_increase_pllclock(crtc, true);
1656
1657         mutex_unlock(&dev->struct_mutex);
1658
1659         if (!dev->primary->master)
1660                 return 0;
1661
1662         master_priv = dev->primary->master->driver_priv;
1663         if (!master_priv->sarea_priv)
1664                 return 0;
1665
1666         if (pipe) {
1667                 master_priv->sarea_priv->pipeB_x = x;
1668                 master_priv->sarea_priv->pipeB_y = y;
1669         } else {
1670                 master_priv->sarea_priv->pipeA_x = x;
1671                 master_priv->sarea_priv->pipeA_y = y;
1672         }
1673
1674         return 0;
1675 }
1676
1677 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1678 {
1679         struct drm_device *dev = crtc->dev;
1680         struct drm_i915_private *dev_priv = dev->dev_private;
1681         u32 dpa_ctl;
1682
1683         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1684         dpa_ctl = I915_READ(DP_A);
1685         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1686
1687         if (clock < 200000) {
1688                 u32 temp;
1689                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1690                 /* workaround for 160Mhz:
1691                    1) program 0x4600c bits 15:0 = 0x8124
1692                    2) program 0x46010 bit 0 = 1
1693                    3) program 0x46034 bit 24 = 1
1694                    4) program 0x64000 bit 14 = 1
1695                    */
1696                 temp = I915_READ(0x4600c);
1697                 temp &= 0xffff0000;
1698                 I915_WRITE(0x4600c, temp | 0x8124);
1699
1700                 temp = I915_READ(0x46010);
1701                 I915_WRITE(0x46010, temp | 1);
1702
1703                 temp = I915_READ(0x46034);
1704                 I915_WRITE(0x46034, temp | (1 << 24));
1705         } else {
1706                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1707         }
1708         I915_WRITE(DP_A, dpa_ctl);
1709
1710         udelay(500);
1711 }
1712
1713 /* The FDI link training functions for ILK/Ibexpeak. */
1714 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1715 {
1716         struct drm_device *dev = crtc->dev;
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1719         int pipe = intel_crtc->pipe;
1720         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1721         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1722         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1723         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1724         u32 temp, tries = 0;
1725
1726         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1727            for train result */
1728         temp = I915_READ(fdi_rx_imr_reg);
1729         temp &= ~FDI_RX_SYMBOL_LOCK;
1730         temp &= ~FDI_RX_BIT_LOCK;
1731         I915_WRITE(fdi_rx_imr_reg, temp);
1732         I915_READ(fdi_rx_imr_reg);
1733         udelay(150);
1734
1735         /* enable CPU FDI TX and PCH FDI RX */
1736         temp = I915_READ(fdi_tx_reg);
1737         temp |= FDI_TX_ENABLE;
1738         temp &= ~(7 << 19);
1739         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1740         temp &= ~FDI_LINK_TRAIN_NONE;
1741         temp |= FDI_LINK_TRAIN_PATTERN_1;
1742         I915_WRITE(fdi_tx_reg, temp);
1743         I915_READ(fdi_tx_reg);
1744
1745         temp = I915_READ(fdi_rx_reg);
1746         temp &= ~FDI_LINK_TRAIN_NONE;
1747         temp |= FDI_LINK_TRAIN_PATTERN_1;
1748         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1749         I915_READ(fdi_rx_reg);
1750         udelay(150);
1751
1752         for (tries = 0; tries < 5; tries++) {
1753                 temp = I915_READ(fdi_rx_iir_reg);
1754                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1755
1756                 if ((temp & FDI_RX_BIT_LOCK)) {
1757                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1758                         I915_WRITE(fdi_rx_iir_reg,
1759                                    temp | FDI_RX_BIT_LOCK);
1760                         break;
1761                 }
1762         }
1763         if (tries == 5)
1764                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1765
1766         /* Train 2 */
1767         temp = I915_READ(fdi_tx_reg);
1768         temp &= ~FDI_LINK_TRAIN_NONE;
1769         temp |= FDI_LINK_TRAIN_PATTERN_2;
1770         I915_WRITE(fdi_tx_reg, temp);
1771
1772         temp = I915_READ(fdi_rx_reg);
1773         temp &= ~FDI_LINK_TRAIN_NONE;
1774         temp |= FDI_LINK_TRAIN_PATTERN_2;
1775         I915_WRITE(fdi_rx_reg, temp);
1776         udelay(150);
1777
1778         tries = 0;
1779
1780         for (tries = 0; tries < 5; tries++) {
1781                 temp = I915_READ(fdi_rx_iir_reg);
1782                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1783
1784                 if (temp & FDI_RX_SYMBOL_LOCK) {
1785                         I915_WRITE(fdi_rx_iir_reg,
1786                                    temp | FDI_RX_SYMBOL_LOCK);
1787                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1788                         break;
1789                 }
1790         }
1791         if (tries == 5)
1792                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1793
1794         DRM_DEBUG_KMS("FDI train done\n");
1795 }
1796
1797 static int snb_b_fdi_train_param [] = {
1798         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1799         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1800         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1801         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1802 };
1803
1804 /* The FDI link training functions for SNB/Cougarpoint. */
1805 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1806 {
1807         struct drm_device *dev = crtc->dev;
1808         struct drm_i915_private *dev_priv = dev->dev_private;
1809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810         int pipe = intel_crtc->pipe;
1811         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1812         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1813         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1814         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1815         u32 temp, i;
1816
1817         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1818            for train result */
1819         temp = I915_READ(fdi_rx_imr_reg);
1820         temp &= ~FDI_RX_SYMBOL_LOCK;
1821         temp &= ~FDI_RX_BIT_LOCK;
1822         I915_WRITE(fdi_rx_imr_reg, temp);
1823         I915_READ(fdi_rx_imr_reg);
1824         udelay(150);
1825
1826         /* enable CPU FDI TX and PCH FDI RX */
1827         temp = I915_READ(fdi_tx_reg);
1828         temp |= FDI_TX_ENABLE;
1829         temp &= ~(7 << 19);
1830         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1831         temp &= ~FDI_LINK_TRAIN_NONE;
1832         temp |= FDI_LINK_TRAIN_PATTERN_1;
1833         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1834         /* SNB-B */
1835         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1836         I915_WRITE(fdi_tx_reg, temp);
1837         I915_READ(fdi_tx_reg);
1838
1839         temp = I915_READ(fdi_rx_reg);
1840         if (HAS_PCH_CPT(dev)) {
1841                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1842                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1843         } else {
1844                 temp &= ~FDI_LINK_TRAIN_NONE;
1845                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1846         }
1847         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1848         I915_READ(fdi_rx_reg);
1849         udelay(150);
1850
1851         for (i = 0; i < 4; i++ ) {
1852                 temp = I915_READ(fdi_tx_reg);
1853                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1854                 temp |= snb_b_fdi_train_param[i];
1855                 I915_WRITE(fdi_tx_reg, temp);
1856                 udelay(500);
1857
1858                 temp = I915_READ(fdi_rx_iir_reg);
1859                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1860
1861                 if (temp & FDI_RX_BIT_LOCK) {
1862                         I915_WRITE(fdi_rx_iir_reg,
1863                                    temp | FDI_RX_BIT_LOCK);
1864                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1865                         break;
1866                 }
1867         }
1868         if (i == 4)
1869                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1870
1871         /* Train 2 */
1872         temp = I915_READ(fdi_tx_reg);
1873         temp &= ~FDI_LINK_TRAIN_NONE;
1874         temp |= FDI_LINK_TRAIN_PATTERN_2;
1875         if (IS_GEN6(dev)) {
1876                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1877                 /* SNB-B */
1878                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1879         }
1880         I915_WRITE(fdi_tx_reg, temp);
1881
1882         temp = I915_READ(fdi_rx_reg);
1883         if (HAS_PCH_CPT(dev)) {
1884                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1885                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1886         } else {
1887                 temp &= ~FDI_LINK_TRAIN_NONE;
1888                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1889         }
1890         I915_WRITE(fdi_rx_reg, temp);
1891         udelay(150);
1892
1893         for (i = 0; i < 4; i++ ) {
1894                 temp = I915_READ(fdi_tx_reg);
1895                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1896                 temp |= snb_b_fdi_train_param[i];
1897                 I915_WRITE(fdi_tx_reg, temp);
1898                 udelay(500);
1899
1900                 temp = I915_READ(fdi_rx_iir_reg);
1901                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1902
1903                 if (temp & FDI_RX_SYMBOL_LOCK) {
1904                         I915_WRITE(fdi_rx_iir_reg,
1905                                    temp | FDI_RX_SYMBOL_LOCK);
1906                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1907                         break;
1908                 }
1909         }
1910         if (i == 4)
1911                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1912
1913         DRM_DEBUG_KMS("FDI train done.\n");
1914 }
1915
1916 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1917 {
1918         struct drm_device *dev = crtc->dev;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1921         int pipe = intel_crtc->pipe;
1922         int plane = intel_crtc->plane;
1923         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1924         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1925         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1926         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1927         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1928         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1929         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1930         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1931         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1932         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1933         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1934         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1935         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1936         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1937         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1938         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1939         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1940         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1941         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1942         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1943         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1944         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1945         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1946         u32 temp;
1947         u32 pipe_bpc;
1948
1949         temp = I915_READ(pipeconf_reg);
1950         pipe_bpc = temp & PIPE_BPC_MASK;
1951
1952         /* XXX: When our outputs are all unaware of DPMS modes other than off
1953          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1954          */
1955         switch (mode) {
1956         case DRM_MODE_DPMS_ON:
1957         case DRM_MODE_DPMS_STANDBY:
1958         case DRM_MODE_DPMS_SUSPEND:
1959                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1960
1961                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1962                         temp = I915_READ(PCH_LVDS);
1963                         if ((temp & LVDS_PORT_EN) == 0) {
1964                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1965                                 POSTING_READ(PCH_LVDS);
1966                         }
1967                 }
1968
1969                 if (!HAS_eDP) {
1970
1971                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1972                         temp = I915_READ(fdi_rx_reg);
1973                         /*
1974                          * make the BPC in FDI Rx be consistent with that in
1975                          * pipeconf reg.
1976                          */
1977                         temp &= ~(0x7 << 16);
1978                         temp |= (pipe_bpc << 11);
1979                         temp &= ~(7 << 19);
1980                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1981                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1982                         I915_READ(fdi_rx_reg);
1983                         udelay(200);
1984
1985                         /* Switch from Rawclk to PCDclk */
1986                         temp = I915_READ(fdi_rx_reg);
1987                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1988                         I915_READ(fdi_rx_reg);
1989                         udelay(200);
1990
1991                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1992                         temp = I915_READ(fdi_tx_reg);
1993                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1994                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1995                                 I915_READ(fdi_tx_reg);
1996                                 udelay(100);
1997                         }
1998                 }
1999
2000                 /* Enable panel fitting for LVDS */
2001                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2002                     || HAS_eDP || intel_pch_has_edp(crtc)) {
2003                         if (dev_priv->pch_pf_size) {
2004                                 temp = I915_READ(pf_ctl_reg);
2005                                 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
2006                                 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
2007                                 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
2008                         } else
2009                                 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2010                 }
2011
2012                 /* Enable CPU pipe */
2013                 temp = I915_READ(pipeconf_reg);
2014                 if ((temp & PIPEACONF_ENABLE) == 0) {
2015                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2016                         I915_READ(pipeconf_reg);
2017                         udelay(100);
2018                 }
2019
2020                 /* configure and enable CPU plane */
2021                 temp = I915_READ(dspcntr_reg);
2022                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2023                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2024                         /* Flush the plane changes */
2025                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2026                 }
2027
2028                 if (!HAS_eDP) {
2029                         /* For PCH output, training FDI link */
2030                         if (IS_GEN6(dev))
2031                                 gen6_fdi_link_train(crtc);
2032                         else
2033                                 ironlake_fdi_link_train(crtc);
2034
2035                         /* enable PCH DPLL */
2036                         temp = I915_READ(pch_dpll_reg);
2037                         if ((temp & DPLL_VCO_ENABLE) == 0) {
2038                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2039                                 I915_READ(pch_dpll_reg);
2040                         }
2041                         udelay(200);
2042
2043                         if (HAS_PCH_CPT(dev)) {
2044                                 /* Be sure PCH DPLL SEL is set */
2045                                 temp = I915_READ(PCH_DPLL_SEL);
2046                                 if (trans_dpll_sel == 0 &&
2047                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
2048                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2049                                 else if (trans_dpll_sel == 1 &&
2050                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
2051                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2052                                 I915_WRITE(PCH_DPLL_SEL, temp);
2053                                 I915_READ(PCH_DPLL_SEL);
2054                         }
2055
2056                         /* set transcoder timing */
2057                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2058                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2059                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2060
2061                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2062                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2063                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2064
2065                         /* enable normal train */
2066                         temp = I915_READ(fdi_tx_reg);
2067                         temp &= ~FDI_LINK_TRAIN_NONE;
2068                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2069                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2070                         I915_READ(fdi_tx_reg);
2071
2072                         temp = I915_READ(fdi_rx_reg);
2073                         if (HAS_PCH_CPT(dev)) {
2074                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2075                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2076                         } else {
2077                                 temp &= ~FDI_LINK_TRAIN_NONE;
2078                                 temp |= FDI_LINK_TRAIN_NONE;
2079                         }
2080                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2081                         I915_READ(fdi_rx_reg);
2082
2083                         /* wait one idle pattern time */
2084                         udelay(100);
2085
2086                         /* For PCH DP, enable TRANS_DP_CTL */
2087                         if (HAS_PCH_CPT(dev) &&
2088                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2089                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2090                                 int reg;
2091
2092                                 reg = I915_READ(trans_dp_ctl);
2093                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2094                                          TRANS_DP_SYNC_MASK);
2095                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2096                                         TRANS_DP_ENH_FRAMING);
2097
2098                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2099                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2100                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2101                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2102
2103                                 switch (intel_trans_dp_port_sel(crtc)) {
2104                                 case PCH_DP_B:
2105                                         reg |= TRANS_DP_PORT_SEL_B;
2106                                         break;
2107                                 case PCH_DP_C:
2108                                         reg |= TRANS_DP_PORT_SEL_C;
2109                                         break;
2110                                 case PCH_DP_D:
2111                                         reg |= TRANS_DP_PORT_SEL_D;
2112                                         break;
2113                                 default:
2114                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2115                                         reg |= TRANS_DP_PORT_SEL_B;
2116                                         break;
2117                                 }
2118
2119                                 I915_WRITE(trans_dp_ctl, reg);
2120                                 POSTING_READ(trans_dp_ctl);
2121                         }
2122
2123                         /* enable PCH transcoder */
2124                         temp = I915_READ(transconf_reg);
2125                         /*
2126                          * make the BPC in transcoder be consistent with
2127                          * that in pipeconf reg.
2128                          */
2129                         temp &= ~PIPE_BPC_MASK;
2130                         temp |= pipe_bpc;
2131                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2132                         I915_READ(transconf_reg);
2133
2134                         if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
2135                                 DRM_ERROR("failed to enable transcoder\n");
2136                 }
2137
2138                 intel_crtc_load_lut(crtc);
2139
2140                 intel_update_fbc(crtc, &crtc->mode);
2141                 break;
2142
2143         case DRM_MODE_DPMS_OFF:
2144                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2145
2146                 drm_vblank_off(dev, pipe);
2147                 /* Disable display plane */
2148                 temp = I915_READ(dspcntr_reg);
2149                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2150                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2151                         /* Flush the plane changes */
2152                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2153                         I915_READ(dspbase_reg);
2154                 }
2155
2156                 if (dev_priv->cfb_plane == plane &&
2157                     dev_priv->display.disable_fbc)
2158                         dev_priv->display.disable_fbc(dev);
2159
2160                 /* disable cpu pipe, disable after all planes disabled */
2161                 temp = I915_READ(pipeconf_reg);
2162                 if ((temp & PIPEACONF_ENABLE) != 0) {
2163                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2164
2165                         /* wait for cpu pipe off, pipe state */
2166                         if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2167                                 DRM_ERROR("failed to turn off cpu pipe\n");
2168                 } else
2169                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2170
2171                 udelay(100);
2172
2173                 /* Disable PF */
2174                 temp = I915_READ(pf_ctl_reg);
2175                 if ((temp & PF_ENABLE) != 0) {
2176                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2177                         I915_READ(pf_ctl_reg);
2178                 }
2179                 I915_WRITE(pf_win_size, 0);
2180                 POSTING_READ(pf_win_size);
2181
2182
2183                 /* disable CPU FDI tx and PCH FDI rx */
2184                 temp = I915_READ(fdi_tx_reg);
2185                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2186                 I915_READ(fdi_tx_reg);
2187
2188                 temp = I915_READ(fdi_rx_reg);
2189                 /* BPC in FDI rx is consistent with that in pipeconf */
2190                 temp &= ~(0x07 << 16);
2191                 temp |= (pipe_bpc << 11);
2192                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2193                 I915_READ(fdi_rx_reg);
2194
2195                 udelay(100);
2196
2197                 /* still set train pattern 1 */
2198                 temp = I915_READ(fdi_tx_reg);
2199                 temp &= ~FDI_LINK_TRAIN_NONE;
2200                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2201                 I915_WRITE(fdi_tx_reg, temp);
2202                 POSTING_READ(fdi_tx_reg);
2203
2204                 temp = I915_READ(fdi_rx_reg);
2205                 if (HAS_PCH_CPT(dev)) {
2206                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2207                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2208                 } else {
2209                         temp &= ~FDI_LINK_TRAIN_NONE;
2210                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2211                 }
2212                 I915_WRITE(fdi_rx_reg, temp);
2213                 POSTING_READ(fdi_rx_reg);
2214
2215                 udelay(100);
2216
2217                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2218                         temp = I915_READ(PCH_LVDS);
2219                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2220                         I915_READ(PCH_LVDS);
2221                         udelay(100);
2222                 }
2223
2224                 /* disable PCH transcoder */
2225                 temp = I915_READ(transconf_reg);
2226                 if ((temp & TRANS_ENABLE) != 0) {
2227                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2228
2229                         /* wait for PCH transcoder off, transcoder state */
2230                         if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2231                                 DRM_ERROR("failed to disable transcoder\n");
2232                 }
2233
2234                 temp = I915_READ(transconf_reg);
2235                 /* BPC in transcoder is consistent with that in pipeconf */
2236                 temp &= ~PIPE_BPC_MASK;
2237                 temp |= pipe_bpc;
2238                 I915_WRITE(transconf_reg, temp);
2239                 I915_READ(transconf_reg);
2240                 udelay(100);
2241
2242                 if (HAS_PCH_CPT(dev)) {
2243                         /* disable TRANS_DP_CTL */
2244                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2245                         int reg;
2246
2247                         reg = I915_READ(trans_dp_ctl);
2248                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2249                         I915_WRITE(trans_dp_ctl, reg);
2250                         POSTING_READ(trans_dp_ctl);
2251
2252                         /* disable DPLL_SEL */
2253                         temp = I915_READ(PCH_DPLL_SEL);
2254                         if (trans_dpll_sel == 0)
2255                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2256                         else
2257                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2258                         I915_WRITE(PCH_DPLL_SEL, temp);
2259                         I915_READ(PCH_DPLL_SEL);
2260
2261                 }
2262
2263                 /* disable PCH DPLL */
2264                 temp = I915_READ(pch_dpll_reg);
2265                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2266                 I915_READ(pch_dpll_reg);
2267
2268                 /* Switch from PCDclk to Rawclk */
2269                 temp = I915_READ(fdi_rx_reg);
2270                 temp &= ~FDI_SEL_PCDCLK;
2271                 I915_WRITE(fdi_rx_reg, temp);
2272                 I915_READ(fdi_rx_reg);
2273
2274                 /* Disable CPU FDI TX PLL */
2275                 temp = I915_READ(fdi_tx_reg);
2276                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2277                 I915_READ(fdi_tx_reg);
2278                 udelay(100);
2279
2280                 temp = I915_READ(fdi_rx_reg);
2281                 temp &= ~FDI_RX_PLL_ENABLE;
2282                 I915_WRITE(fdi_rx_reg, temp);
2283                 I915_READ(fdi_rx_reg);
2284
2285                 /* Wait for the clocks to turn off. */
2286                 udelay(100);
2287                 break;
2288         }
2289 }
2290
2291 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2292 {
2293         struct intel_overlay *overlay;
2294         int ret;
2295
2296         if (!enable && intel_crtc->overlay) {
2297                 overlay = intel_crtc->overlay;
2298                 mutex_lock(&overlay->dev->struct_mutex);
2299                 for (;;) {
2300                         ret = intel_overlay_switch_off(overlay);
2301                         if (ret == 0)
2302                                 break;
2303
2304                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2305                         if (ret != 0) {
2306                                 /* overlay doesn't react anymore. Usually
2307                                  * results in a black screen and an unkillable
2308                                  * X server. */
2309                                 BUG();
2310                                 overlay->hw_wedged = HW_WEDGED;
2311                                 break;
2312                         }
2313                 }
2314                 mutex_unlock(&overlay->dev->struct_mutex);
2315         }
2316         /* Let userspace switch the overlay on again. In most cases userspace
2317          * has to recompute where to put it anyway. */
2318
2319         return;
2320 }
2321
2322 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2323 {
2324         struct drm_device *dev = crtc->dev;
2325         struct drm_i915_private *dev_priv = dev->dev_private;
2326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2327         int pipe = intel_crtc->pipe;
2328         int plane = intel_crtc->plane;
2329         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2330         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2331         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2332         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2333         u32 temp;
2334
2335         /* XXX: When our outputs are all unaware of DPMS modes other than off
2336          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2337          */
2338         switch (mode) {
2339         case DRM_MODE_DPMS_ON:
2340         case DRM_MODE_DPMS_STANDBY:
2341         case DRM_MODE_DPMS_SUSPEND:
2342                 /* Enable the DPLL */
2343                 temp = I915_READ(dpll_reg);
2344                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2345                         I915_WRITE(dpll_reg, temp);
2346                         I915_READ(dpll_reg);
2347                         /* Wait for the clocks to stabilize. */
2348                         udelay(150);
2349                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2350                         I915_READ(dpll_reg);
2351                         /* Wait for the clocks to stabilize. */
2352                         udelay(150);
2353                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2354                         I915_READ(dpll_reg);
2355                         /* Wait for the clocks to stabilize. */
2356                         udelay(150);
2357                 }
2358
2359                 /* Enable the pipe */
2360                 temp = I915_READ(pipeconf_reg);
2361                 if ((temp & PIPEACONF_ENABLE) == 0)
2362                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2363
2364                 /* Enable the plane */
2365                 temp = I915_READ(dspcntr_reg);
2366                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2367                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2368                         /* Flush the plane changes */
2369                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2370                 }
2371
2372                 intel_crtc_load_lut(crtc);
2373
2374                 if ((IS_I965G(dev) || plane == 0))
2375                         intel_update_fbc(crtc, &crtc->mode);
2376
2377                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2378                 intel_crtc_dpms_overlay(intel_crtc, true);
2379         break;
2380         case DRM_MODE_DPMS_OFF:
2381                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2382                 intel_crtc_dpms_overlay(intel_crtc, false);
2383                 drm_vblank_off(dev, pipe);
2384
2385                 if (dev_priv->cfb_plane == plane &&
2386                     dev_priv->display.disable_fbc)
2387                         dev_priv->display.disable_fbc(dev);
2388
2389                 /* Disable display plane */
2390                 temp = I915_READ(dspcntr_reg);
2391                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2392                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2393                         /* Flush the plane changes */
2394                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2395                         I915_READ(dspbase_reg);
2396                 }
2397
2398                 /* Wait for vblank for the disable to take effect */
2399                 intel_wait_for_vblank_off(dev, pipe);
2400
2401                 /* Don't disable pipe A or pipe A PLLs if needed */
2402                 if (pipeconf_reg == PIPEACONF &&
2403                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2404                         goto skip_pipe_off;
2405
2406                 /* Next, disable display pipes */
2407                 temp = I915_READ(pipeconf_reg);
2408                 if ((temp & PIPEACONF_ENABLE) != 0) {
2409                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2410                         I915_READ(pipeconf_reg);
2411                 }
2412
2413                 /* Wait for vblank for the disable to take effect. */
2414                 intel_wait_for_vblank_off(dev, pipe);
2415
2416                 temp = I915_READ(dpll_reg);
2417                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2418                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2419                         I915_READ(dpll_reg);
2420                 }
2421         skip_pipe_off:
2422                 /* Wait for the clocks to turn off. */
2423                 udelay(150);
2424                 break;
2425         }
2426 }
2427
2428 /**
2429  * Sets the power management mode of the pipe and plane.
2430  */
2431 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct drm_i915_master_private *master_priv;
2436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2437         int pipe = intel_crtc->pipe;
2438         bool enabled;
2439
2440         intel_crtc->dpms_mode = mode;
2441         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2442
2443         /* When switching on the display, ensure that SR is disabled
2444          * with multiple pipes prior to enabling to new pipe.
2445          *
2446          * When switching off the display, make sure the cursor is
2447          * properly hidden prior to disabling the pipe.
2448          */
2449         if (mode == DRM_MODE_DPMS_ON)
2450                 intel_update_watermarks(dev);
2451         else
2452                 intel_crtc_update_cursor(crtc);
2453
2454         dev_priv->display.dpms(crtc, mode);
2455
2456         if (mode == DRM_MODE_DPMS_ON)
2457                 intel_crtc_update_cursor(crtc);
2458         else
2459                 intel_update_watermarks(dev);
2460
2461         if (!dev->primary->master)
2462                 return;
2463
2464         master_priv = dev->primary->master->driver_priv;
2465         if (!master_priv->sarea_priv)
2466                 return;
2467
2468         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2469
2470         switch (pipe) {
2471         case 0:
2472                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2473                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2474                 break;
2475         case 1:
2476                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2477                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2478                 break;
2479         default:
2480                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2481                 break;
2482         }
2483 }
2484
2485 static void intel_crtc_prepare (struct drm_crtc *crtc)
2486 {
2487         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2488         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2489 }
2490
2491 static void intel_crtc_commit (struct drm_crtc *crtc)
2492 {
2493         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2494         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2495 }
2496
2497 void intel_encoder_prepare (struct drm_encoder *encoder)
2498 {
2499         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2500         /* lvds has its own version of prepare see intel_lvds_prepare */
2501         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2502 }
2503
2504 void intel_encoder_commit (struct drm_encoder *encoder)
2505 {
2506         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2507         /* lvds has its own version of commit see intel_lvds_commit */
2508         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2509 }
2510
2511 void intel_encoder_destroy(struct drm_encoder *encoder)
2512 {
2513         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2514
2515         if (intel_encoder->ddc_bus)
2516                 intel_i2c_destroy(intel_encoder->ddc_bus);
2517
2518         if (intel_encoder->i2c_bus)
2519                 intel_i2c_destroy(intel_encoder->i2c_bus);
2520
2521         drm_encoder_cleanup(encoder);
2522         kfree(intel_encoder);
2523 }
2524
2525 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2526                                   struct drm_display_mode *mode,
2527                                   struct drm_display_mode *adjusted_mode)
2528 {
2529         struct drm_device *dev = crtc->dev;
2530         if (HAS_PCH_SPLIT(dev)) {
2531                 /* FDI link clock is fixed at 2.7G */
2532                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2533                         return false;
2534         }
2535         return true;
2536 }
2537
2538 static int i945_get_display_clock_speed(struct drm_device *dev)
2539 {
2540         return 400000;
2541 }
2542
2543 static int i915_get_display_clock_speed(struct drm_device *dev)
2544 {
2545         return 333000;
2546 }
2547
2548 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2549 {
2550         return 200000;
2551 }
2552
2553 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2554 {
2555         u16 gcfgc = 0;
2556
2557         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2558
2559         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2560                 return 133000;
2561         else {
2562                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2563                 case GC_DISPLAY_CLOCK_333_MHZ:
2564                         return 333000;
2565                 default:
2566                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2567                         return 190000;
2568                 }
2569         }
2570 }
2571
2572 static int i865_get_display_clock_speed(struct drm_device *dev)
2573 {
2574         return 266000;
2575 }
2576
2577 static int i855_get_display_clock_speed(struct drm_device *dev)
2578 {
2579         u16 hpllcc = 0;
2580         /* Assume that the hardware is in the high speed state.  This
2581          * should be the default.
2582          */
2583         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2584         case GC_CLOCK_133_200:
2585         case GC_CLOCK_100_200:
2586                 return 200000;
2587         case GC_CLOCK_166_250:
2588                 return 250000;
2589         case GC_CLOCK_100_133:
2590                 return 133000;
2591         }
2592
2593         /* Shouldn't happen */
2594         return 0;
2595 }
2596
2597 static int i830_get_display_clock_speed(struct drm_device *dev)
2598 {
2599         return 133000;
2600 }
2601
2602 /**
2603  * Return the pipe currently connected to the panel fitter,
2604  * or -1 if the panel fitter is not present or not in use
2605  */
2606 int intel_panel_fitter_pipe (struct drm_device *dev)
2607 {
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         u32  pfit_control;
2610
2611         /* i830 doesn't have a panel fitter */
2612         if (IS_I830(dev))
2613                 return -1;
2614
2615         pfit_control = I915_READ(PFIT_CONTROL);
2616
2617         /* See if the panel fitter is in use */
2618         if ((pfit_control & PFIT_ENABLE) == 0)
2619                 return -1;
2620
2621         /* 965 can place panel fitter on either pipe */
2622         if (IS_I965G(dev))
2623                 return (pfit_control >> 29) & 0x3;
2624
2625         /* older chips can only use pipe 1 */
2626         return 1;
2627 }
2628
2629 struct fdi_m_n {
2630         u32        tu;
2631         u32        gmch_m;
2632         u32        gmch_n;
2633         u32        link_m;
2634         u32        link_n;
2635 };
2636
2637 static void
2638 fdi_reduce_ratio(u32 *num, u32 *den)
2639 {
2640         while (*num > 0xffffff || *den > 0xffffff) {
2641                 *num >>= 1;
2642                 *den >>= 1;
2643         }
2644 }
2645
2646 #define DATA_N 0x800000
2647 #define LINK_N 0x80000
2648
2649 static void
2650 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2651                      int link_clock, struct fdi_m_n *m_n)
2652 {
2653         u64 temp;
2654
2655         m_n->tu = 64; /* default size */
2656
2657         temp = (u64) DATA_N * pixel_clock;
2658         temp = div_u64(temp, link_clock);
2659         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2660         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2661         m_n->gmch_n = DATA_N;
2662         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2663
2664         temp = (u64) LINK_N * pixel_clock;
2665         m_n->link_m = div_u64(temp, link_clock);
2666         m_n->link_n = LINK_N;
2667         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2668 }
2669
2670
2671 struct intel_watermark_params {
2672         unsigned long fifo_size;
2673         unsigned long max_wm;
2674         unsigned long default_wm;
2675         unsigned long guard_size;
2676         unsigned long cacheline_size;
2677 };
2678
2679 /* Pineview has different values for various configs */
2680 static struct intel_watermark_params pineview_display_wm = {
2681         PINEVIEW_DISPLAY_FIFO,
2682         PINEVIEW_MAX_WM,
2683         PINEVIEW_DFT_WM,
2684         PINEVIEW_GUARD_WM,
2685         PINEVIEW_FIFO_LINE_SIZE
2686 };
2687 static struct intel_watermark_params pineview_display_hplloff_wm = {
2688         PINEVIEW_DISPLAY_FIFO,
2689         PINEVIEW_MAX_WM,
2690         PINEVIEW_DFT_HPLLOFF_WM,
2691         PINEVIEW_GUARD_WM,
2692         PINEVIEW_FIFO_LINE_SIZE
2693 };
2694 static struct intel_watermark_params pineview_cursor_wm = {
2695         PINEVIEW_CURSOR_FIFO,
2696         PINEVIEW_CURSOR_MAX_WM,
2697         PINEVIEW_CURSOR_DFT_WM,
2698         PINEVIEW_CURSOR_GUARD_WM,
2699         PINEVIEW_FIFO_LINE_SIZE,
2700 };
2701 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2702         PINEVIEW_CURSOR_FIFO,
2703         PINEVIEW_CURSOR_MAX_WM,
2704         PINEVIEW_CURSOR_DFT_WM,
2705         PINEVIEW_CURSOR_GUARD_WM,
2706         PINEVIEW_FIFO_LINE_SIZE
2707 };
2708 static struct intel_watermark_params g4x_wm_info = {
2709         G4X_FIFO_SIZE,
2710         G4X_MAX_WM,
2711         G4X_MAX_WM,
2712         2,
2713         G4X_FIFO_LINE_SIZE,
2714 };
2715 static struct intel_watermark_params g4x_cursor_wm_info = {
2716         I965_CURSOR_FIFO,
2717         I965_CURSOR_MAX_WM,
2718         I965_CURSOR_DFT_WM,
2719         2,
2720         G4X_FIFO_LINE_SIZE,
2721 };
2722 static struct intel_watermark_params i965_cursor_wm_info = {
2723         I965_CURSOR_FIFO,
2724         I965_CURSOR_MAX_WM,
2725         I965_CURSOR_DFT_WM,
2726         2,
2727         I915_FIFO_LINE_SIZE,
2728 };
2729 static struct intel_watermark_params i945_wm_info = {
2730         I945_FIFO_SIZE,
2731         I915_MAX_WM,
2732         1,
2733         2,
2734         I915_FIFO_LINE_SIZE
2735 };
2736 static struct intel_watermark_params i915_wm_info = {
2737         I915_FIFO_SIZE,
2738         I915_MAX_WM,
2739         1,
2740         2,
2741         I915_FIFO_LINE_SIZE
2742 };
2743 static struct intel_watermark_params i855_wm_info = {
2744         I855GM_FIFO_SIZE,
2745         I915_MAX_WM,
2746         1,
2747         2,
2748         I830_FIFO_LINE_SIZE
2749 };
2750 static struct intel_watermark_params i830_wm_info = {
2751         I830_FIFO_SIZE,
2752         I915_MAX_WM,
2753         1,
2754         2,
2755         I830_FIFO_LINE_SIZE
2756 };
2757
2758 static struct intel_watermark_params ironlake_display_wm_info = {
2759         ILK_DISPLAY_FIFO,
2760         ILK_DISPLAY_MAXWM,
2761         ILK_DISPLAY_DFTWM,
2762         2,
2763         ILK_FIFO_LINE_SIZE
2764 };
2765
2766 static struct intel_watermark_params ironlake_cursor_wm_info = {
2767         ILK_CURSOR_FIFO,
2768         ILK_CURSOR_MAXWM,
2769         ILK_CURSOR_DFTWM,
2770         2,
2771         ILK_FIFO_LINE_SIZE
2772 };
2773
2774 static struct intel_watermark_params ironlake_display_srwm_info = {
2775         ILK_DISPLAY_SR_FIFO,
2776         ILK_DISPLAY_MAX_SRWM,
2777         ILK_DISPLAY_DFT_SRWM,
2778         2,
2779         ILK_FIFO_LINE_SIZE
2780 };
2781
2782 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2783         ILK_CURSOR_SR_FIFO,
2784         ILK_CURSOR_MAX_SRWM,
2785         ILK_CURSOR_DFT_SRWM,
2786         2,
2787         ILK_FIFO_LINE_SIZE
2788 };
2789
2790 /**
2791  * intel_calculate_wm - calculate watermark level
2792  * @clock_in_khz: pixel clock
2793  * @wm: chip FIFO params
2794  * @pixel_size: display pixel size
2795  * @latency_ns: memory latency for the platform
2796  *
2797  * Calculate the watermark level (the level at which the display plane will
2798  * start fetching from memory again).  Each chip has a different display
2799  * FIFO size and allocation, so the caller needs to figure that out and pass
2800  * in the correct intel_watermark_params structure.
2801  *
2802  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2803  * on the pixel size.  When it reaches the watermark level, it'll start
2804  * fetching FIFO line sized based chunks from memory until the FIFO fills
2805  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2806  * will occur, and a display engine hang could result.
2807  */
2808 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2809                                         struct intel_watermark_params *wm,
2810                                         int pixel_size,
2811                                         unsigned long latency_ns)
2812 {
2813         long entries_required, wm_size;
2814
2815         /*
2816          * Note: we need to make sure we don't overflow for various clock &
2817          * latency values.
2818          * clocks go from a few thousand to several hundred thousand.
2819          * latency is usually a few thousand
2820          */
2821         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2822                 1000;
2823         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2824
2825         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2826
2827         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2828
2829         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2830
2831         /* Don't promote wm_size to unsigned... */
2832         if (wm_size > (long)wm->max_wm)
2833                 wm_size = wm->max_wm;
2834         if (wm_size <= 0) {
2835                 wm_size = wm->default_wm;
2836                 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2837                           " entries required = %ld, available = %lu.\n",
2838                           entries_required + wm->guard_size,
2839                           wm->fifo_size);
2840         }
2841
2842         return wm_size;
2843 }
2844
2845 struct cxsr_latency {
2846         int is_desktop;
2847         int is_ddr3;
2848         unsigned long fsb_freq;
2849         unsigned long mem_freq;
2850         unsigned long display_sr;
2851         unsigned long display_hpll_disable;
2852         unsigned long cursor_sr;
2853         unsigned long cursor_hpll_disable;
2854 };
2855
2856 static const struct cxsr_latency cxsr_latency_table[] = {
2857         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2858         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2859         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2860         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2861         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2862
2863         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2864         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2865         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2866         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2867         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2868
2869         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2870         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2871         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2872         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2873         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2874
2875         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2876         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2877         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2878         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2879         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2880
2881         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2882         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2883         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2884         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2885         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2886
2887         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2888         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2889         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2890         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2891         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2892 };
2893
2894 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2895                                                          int is_ddr3,
2896                                                          int fsb,
2897                                                          int mem)
2898 {
2899         const struct cxsr_latency *latency;
2900         int i;
2901
2902         if (fsb == 0 || mem == 0)
2903                 return NULL;
2904
2905         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2906                 latency = &cxsr_latency_table[i];
2907                 if (is_desktop == latency->is_desktop &&
2908                     is_ddr3 == latency->is_ddr3 &&
2909                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2910                         return latency;
2911         }
2912
2913         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2914
2915         return NULL;
2916 }
2917
2918 static void pineview_disable_cxsr(struct drm_device *dev)
2919 {
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921
2922         /* deactivate cxsr */
2923         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2924 }
2925
2926 /*
2927  * Latency for FIFO fetches is dependent on several factors:
2928  *   - memory configuration (speed, channels)
2929  *   - chipset
2930  *   - current MCH state
2931  * It can be fairly high in some situations, so here we assume a fairly
2932  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2933  * set this value too high, the FIFO will fetch frequently to stay full)
2934  * and power consumption (set it too low to save power and we might see
2935  * FIFO underruns and display "flicker").
2936  *
2937  * A value of 5us seems to be a good balance; safe for very low end
2938  * platforms but not overly aggressive on lower latency configs.
2939  */
2940 static const int latency_ns = 5000;
2941
2942 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2943 {
2944         struct drm_i915_private *dev_priv = dev->dev_private;
2945         uint32_t dsparb = I915_READ(DSPARB);
2946         int size;
2947
2948         size = dsparb & 0x7f;
2949         if (plane)
2950                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2951
2952         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2953                         plane ? "B" : "A", size);
2954
2955         return size;
2956 }
2957
2958 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2959 {
2960         struct drm_i915_private *dev_priv = dev->dev_private;
2961         uint32_t dsparb = I915_READ(DSPARB);
2962         int size;
2963
2964         size = dsparb & 0x1ff;
2965         if (plane)
2966                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2967         size >>= 1; /* Convert to cachelines */
2968
2969         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2970                         plane ? "B" : "A", size);
2971
2972         return size;
2973 }
2974
2975 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2976 {
2977         struct drm_i915_private *dev_priv = dev->dev_private;
2978         uint32_t dsparb = I915_READ(DSPARB);
2979         int size;
2980
2981         size = dsparb & 0x7f;
2982         size >>= 2; /* Convert to cachelines */
2983
2984         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2985                         plane ? "B" : "A",
2986                   size);
2987
2988         return size;
2989 }
2990
2991 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2992 {
2993         struct drm_i915_private *dev_priv = dev->dev_private;
2994         uint32_t dsparb = I915_READ(DSPARB);
2995         int size;
2996
2997         size = dsparb & 0x7f;
2998         size >>= 1; /* Convert to cachelines */
2999
3000         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3001                         plane ? "B" : "A", size);
3002
3003         return size;
3004 }
3005
3006 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3007                           int planeb_clock, int sr_hdisplay, int unused,
3008                           int pixel_size)
3009 {
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         const struct cxsr_latency *latency;
3012         u32 reg;
3013         unsigned long wm;
3014         int sr_clock;
3015
3016         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3017                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3018         if (!latency) {
3019                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3020                 pineview_disable_cxsr(dev);
3021                 return;
3022         }
3023
3024         if (!planea_clock || !planeb_clock) {
3025                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3026
3027                 /* Display SR */
3028                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3029                                         pixel_size, latency->display_sr);
3030                 reg = I915_READ(DSPFW1);
3031                 reg &= ~DSPFW_SR_MASK;
3032                 reg |= wm << DSPFW_SR_SHIFT;
3033                 I915_WRITE(DSPFW1, reg);
3034                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3035
3036                 /* cursor SR */
3037                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3038                                         pixel_size, latency->cursor_sr);
3039                 reg = I915_READ(DSPFW3);
3040                 reg &= ~DSPFW_CURSOR_SR_MASK;
3041                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3042                 I915_WRITE(DSPFW3, reg);
3043
3044                 /* Display HPLL off SR */
3045                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3046                                         pixel_size, latency->display_hpll_disable);
3047                 reg = I915_READ(DSPFW3);
3048                 reg &= ~DSPFW_HPLL_SR_MASK;
3049                 reg |= wm & DSPFW_HPLL_SR_MASK;
3050                 I915_WRITE(DSPFW3, reg);
3051
3052                 /* cursor HPLL off SR */
3053                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3054                                         pixel_size, latency->cursor_hpll_disable);
3055                 reg = I915_READ(DSPFW3);
3056                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3057                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3058                 I915_WRITE(DSPFW3, reg);
3059                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3060
3061                 /* activate cxsr */
3062                 I915_WRITE(DSPFW3,
3063                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3064                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3065         } else {
3066                 pineview_disable_cxsr(dev);
3067                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3068         }
3069 }
3070
3071 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3072                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3073                           int pixel_size)
3074 {
3075         struct drm_i915_private *dev_priv = dev->dev_private;
3076         int total_size, cacheline_size;
3077         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3078         struct intel_watermark_params planea_params, planeb_params;
3079         unsigned long line_time_us;
3080         int sr_clock, sr_entries = 0, entries_required;
3081
3082         /* Create copies of the base settings for each pipe */
3083         planea_params = planeb_params = g4x_wm_info;
3084
3085         /* Grab a couple of global values before we overwrite them */
3086         total_size = planea_params.fifo_size;
3087         cacheline_size = planea_params.cacheline_size;
3088
3089         /*
3090          * Note: we need to make sure we don't overflow for various clock &
3091          * latency values.
3092          * clocks go from a few thousand to several hundred thousand.
3093          * latency is usually a few thousand
3094          */
3095         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3096                 1000;
3097         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3098         planea_wm = entries_required + planea_params.guard_size;
3099
3100         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3101                 1000;
3102         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3103         planeb_wm = entries_required + planeb_params.guard_size;
3104
3105         cursora_wm = cursorb_wm = 16;
3106         cursor_sr = 32;
3107
3108         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3109
3110         /* Calc sr entries for one plane configs */
3111         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3112                 /* self-refresh has much higher latency */
3113                 static const int sr_latency_ns = 12000;
3114
3115                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3116                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3117
3118                 /* Use ns/us then divide to preserve precision */
3119                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3120                               pixel_size * sr_hdisplay;
3121                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3122
3123                 entries_required = (((sr_latency_ns / line_time_us) +
3124                                      1000) / 1000) * pixel_size * 64;
3125                 entries_required = DIV_ROUND_UP(entries_required,
3126                                            g4x_cursor_wm_info.cacheline_size);
3127                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3128
3129                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3130                         cursor_sr = g4x_cursor_wm_info.max_wm;
3131                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3132                               "cursor %d\n", sr_entries, cursor_sr);
3133
3134                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3135         } else {
3136                 /* Turn off self refresh if both pipes are enabled */
3137                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3138                                         & ~FW_BLC_SELF_EN);
3139         }
3140
3141         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3142                   planea_wm, planeb_wm, sr_entries);
3143
3144         planea_wm &= 0x3f;
3145         planeb_wm &= 0x3f;
3146
3147         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3148                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3149                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3150         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3151                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3152         /* HPLL off in SR has some issues on G4x... disable it */
3153         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3154                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3155 }
3156
3157 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3158                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3159                            int pixel_size)
3160 {
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162         unsigned long line_time_us;
3163         int sr_clock, sr_entries, srwm = 1;
3164         int cursor_sr = 16;
3165
3166         /* Calc sr entries for one plane configs */
3167         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3168                 /* self-refresh has much higher latency */
3169                 static const int sr_latency_ns = 12000;
3170
3171                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3172                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3173
3174                 /* Use ns/us then divide to preserve precision */
3175                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3176                               pixel_size * sr_hdisplay;
3177                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3178                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3179                 srwm = I965_FIFO_SIZE - sr_entries;
3180                 if (srwm < 0)
3181                         srwm = 1;
3182                 srwm &= 0x1ff;
3183
3184                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3185                              pixel_size * 64;
3186                 sr_entries = DIV_ROUND_UP(sr_entries,
3187                                           i965_cursor_wm_info.cacheline_size);
3188                 cursor_sr = i965_cursor_wm_info.fifo_size -
3189                             (sr_entries + i965_cursor_wm_info.guard_size);
3190
3191                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3192                         cursor_sr = i965_cursor_wm_info.max_wm;
3193
3194                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3195                               "cursor %d\n", srwm, cursor_sr);
3196
3197                 if (IS_I965GM(dev))
3198                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3199         } else {
3200                 /* Turn off self refresh if both pipes are enabled */
3201                 if (IS_I965GM(dev))
3202                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3203                                    & ~FW_BLC_SELF_EN);
3204         }
3205
3206         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3207                       srwm);
3208
3209         /* 965 has limitations... */
3210         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3211                    (8 << 0));
3212         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3213         /* update cursor SR watermark */
3214         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3215 }
3216
3217 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3218                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3219                            int pixel_size)
3220 {
3221         struct drm_i915_private *dev_priv = dev->dev_private;
3222         uint32_t fwater_lo;
3223         uint32_t fwater_hi;
3224         int total_size, cacheline_size, cwm, srwm = 1;
3225         int planea_wm, planeb_wm;
3226         struct intel_watermark_params planea_params, planeb_params;
3227         unsigned long line_time_us;
3228         int sr_clock, sr_entries = 0;
3229
3230         /* Create copies of the base settings for each pipe */
3231         if (IS_I965GM(dev) || IS_I945GM(dev))
3232                 planea_params = planeb_params = i945_wm_info;
3233         else if (IS_I9XX(dev))
3234                 planea_params = planeb_params = i915_wm_info;
3235         else
3236                 planea_params = planeb_params = i855_wm_info;
3237
3238         /* Grab a couple of global values before we overwrite them */
3239         total_size = planea_params.fifo_size;
3240         cacheline_size = planea_params.cacheline_size;
3241
3242         /* Update per-plane FIFO sizes */
3243         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3244         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3245
3246         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3247                                        pixel_size, latency_ns);
3248         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3249                                        pixel_size, latency_ns);
3250         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3251
3252         /*
3253          * Overlay gets an aggressive default since video jitter is bad.
3254          */
3255         cwm = 2;
3256
3257         /* Calc sr entries for one plane configs */
3258         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3259             (!planea_clock || !planeb_clock)) {
3260                 /* self-refresh has much higher latency */
3261                 static const int sr_latency_ns = 6000;
3262
3263                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3264                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3265
3266                 /* Use ns/us then divide to preserve precision */
3267                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3268                               pixel_size * sr_hdisplay;
3269                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3270                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3271                 srwm = total_size - sr_entries;
3272                 if (srwm < 0)
3273                         srwm = 1;
3274
3275                 if (IS_I945G(dev) || IS_I945GM(dev))
3276                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3277                 else if (IS_I915GM(dev)) {
3278                         /* 915M has a smaller SRWM field */
3279                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3280                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3281                 }
3282         } else {
3283                 /* Turn off self refresh if both pipes are enabled */
3284                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3285                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3286                                    & ~FW_BLC_SELF_EN);
3287                 } else if (IS_I915GM(dev)) {
3288                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3289                 }
3290         }
3291
3292         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3293                   planea_wm, planeb_wm, cwm, srwm);
3294
3295         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3296         fwater_hi = (cwm & 0x1f);
3297
3298         /* Set request length to 8 cachelines per fetch */
3299         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3300         fwater_hi = fwater_hi | (1 << 8);
3301
3302         I915_WRITE(FW_BLC, fwater_lo);
3303         I915_WRITE(FW_BLC2, fwater_hi);
3304 }
3305
3306 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3307                            int unused2, int unused3, int pixel_size)
3308 {
3309         struct drm_i915_private *dev_priv = dev->dev_private;
3310         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3311         int planea_wm;
3312
3313         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3314
3315         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3316                                        pixel_size, latency_ns);
3317         fwater_lo |= (3<<8) | planea_wm;
3318
3319         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3320
3321         I915_WRITE(FW_BLC, fwater_lo);
3322 }
3323
3324 #define ILK_LP0_PLANE_LATENCY           700
3325 #define ILK_LP0_CURSOR_LATENCY          1300
3326
3327 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3328                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3329                        int pixel_size)
3330 {
3331         struct drm_i915_private *dev_priv = dev->dev_private;
3332         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3333         int sr_wm, cursor_wm;
3334         unsigned long line_time_us;
3335         int sr_clock, entries_required;
3336         u32 reg_value;
3337         int line_count;
3338         int planea_htotal = 0, planeb_htotal = 0;
3339         struct drm_crtc *crtc;
3340
3341         /* Need htotal for all active display plane */
3342         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3343                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3344                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3345                         if (intel_crtc->plane == 0)
3346                                 planea_htotal = crtc->mode.htotal;
3347                         else
3348                                 planeb_htotal = crtc->mode.htotal;
3349                 }
3350         }
3351
3352         /* Calculate and update the watermark for plane A */
3353         if (planea_clock) {
3354                 entries_required = ((planea_clock / 1000) * pixel_size *
3355                                      ILK_LP0_PLANE_LATENCY) / 1000;
3356                 entries_required = DIV_ROUND_UP(entries_required,
3357                                                 ironlake_display_wm_info.cacheline_size);
3358                 planea_wm = entries_required +
3359                             ironlake_display_wm_info.guard_size;
3360
3361                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3362                         planea_wm = ironlake_display_wm_info.max_wm;
3363
3364                 /* Use the large buffer method to calculate cursor watermark */
3365                 line_time_us = (planea_htotal * 1000) / planea_clock;
3366
3367                 /* Use ns/us then divide to preserve precision */
3368                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3369
3370                 /* calculate the cursor watermark for cursor A */
3371                 entries_required = line_count * 64 * pixel_size;
3372                 entries_required = DIV_ROUND_UP(entries_required,
3373                                                 ironlake_cursor_wm_info.cacheline_size);
3374                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3375                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3376                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3377
3378                 reg_value = I915_READ(WM0_PIPEA_ILK);
3379                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3380                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3381                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3382                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3383                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3384                                 "cursor: %d\n", planea_wm, cursora_wm);
3385         }
3386         /* Calculate and update the watermark for plane B */
3387         if (planeb_clock) {
3388                 entries_required = ((planeb_clock / 1000) * pixel_size *
3389                                      ILK_LP0_PLANE_LATENCY) / 1000;
3390                 entries_required = DIV_ROUND_UP(entries_required,
3391                                                 ironlake_display_wm_info.cacheline_size);
3392                 planeb_wm = entries_required +
3393                             ironlake_display_wm_info.guard_size;
3394
3395                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3396                         planeb_wm = ironlake_display_wm_info.max_wm;
3397
3398                 /* Use the large buffer method to calculate cursor watermark */
3399                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3400
3401                 /* Use ns/us then divide to preserve precision */
3402                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3403
3404                 /* calculate the cursor watermark for cursor B */
3405                 entries_required = line_count * 64 * pixel_size;
3406                 entries_required = DIV_ROUND_UP(entries_required,
3407                                                 ironlake_cursor_wm_info.cacheline_size);
3408                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3409                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3410                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3411
3412                 reg_value = I915_READ(WM0_PIPEB_ILK);
3413                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3414                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3415                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3416                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3417                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3418                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3419         }
3420
3421         /*
3422          * Calculate and update the self-refresh watermark only when one
3423          * display plane is used.
3424          */
3425         if (!planea_clock || !planeb_clock) {
3426
3427                 /* Read the self-refresh latency. The unit is 0.5us */
3428                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3429
3430                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3431                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3432
3433                 /* Use ns/us then divide to preserve precision */
3434                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3435                                / 1000;
3436
3437                 /* calculate the self-refresh watermark for display plane */
3438                 entries_required = line_count * sr_hdisplay * pixel_size;
3439                 entries_required = DIV_ROUND_UP(entries_required,
3440                                                 ironlake_display_srwm_info.cacheline_size);
3441                 sr_wm = entries_required +
3442                         ironlake_display_srwm_info.guard_size;
3443
3444                 /* calculate the self-refresh watermark for display cursor */
3445                 entries_required = line_count * pixel_size * 64;
3446                 entries_required = DIV_ROUND_UP(entries_required,
3447                                                 ironlake_cursor_srwm_info.cacheline_size);
3448                 cursor_wm = entries_required +
3449                             ironlake_cursor_srwm_info.guard_size;
3450
3451                 /* configure watermark and enable self-refresh */
3452                 reg_value = I915_READ(WM1_LP_ILK);
3453                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3454                                WM1_LP_CURSOR_MASK);
3455                 reg_value |= WM1_LP_SR_EN |
3456                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3457                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3458
3459                 I915_WRITE(WM1_LP_ILK, reg_value);
3460                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3461                                 "cursor %d\n", sr_wm, cursor_wm);
3462
3463         } else {
3464                 /* Turn off self refresh if both pipes are enabled */
3465                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3466         }
3467 }
3468 /**
3469  * intel_update_watermarks - update FIFO watermark values based on current modes
3470  *
3471  * Calculate watermark values for the various WM regs based on current mode
3472  * and plane configuration.
3473  *
3474  * There are several cases to deal with here:
3475  *   - normal (i.e. non-self-refresh)
3476  *   - self-refresh (SR) mode
3477  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3478  *   - lines are small relative to FIFO size (buffer can hold more than 2
3479  *     lines), so need to account for TLB latency
3480  *
3481  *   The normal calculation is:
3482  *     watermark = dotclock * bytes per pixel * latency
3483  *   where latency is platform & configuration dependent (we assume pessimal
3484  *   values here).
3485  *
3486  *   The SR calculation is:
3487  *     watermark = (trunc(latency/line time)+1) * surface width *
3488  *       bytes per pixel
3489  *   where
3490  *     line time = htotal / dotclock
3491  *     surface width = hdisplay for normal plane and 64 for cursor
3492  *   and latency is assumed to be high, as above.
3493  *
3494  * The final value programmed to the register should always be rounded up,
3495  * and include an extra 2 entries to account for clock crossings.
3496  *
3497  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3498  * to set the non-SR watermarks to 8.
3499   */
3500 static void intel_update_watermarks(struct drm_device *dev)
3501 {
3502         struct drm_i915_private *dev_priv = dev->dev_private;
3503         struct drm_crtc *crtc;
3504         int sr_hdisplay = 0;
3505         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3506         int enabled = 0, pixel_size = 0;
3507         int sr_htotal = 0;
3508
3509         if (!dev_priv->display.update_wm)
3510                 return;
3511
3512         /* Get the clock config from both planes */
3513         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3514                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3515                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3516                         enabled++;
3517                         if (intel_crtc->plane == 0) {
3518                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3519                                           intel_crtc->pipe, crtc->mode.clock);
3520                                 planea_clock = crtc->mode.clock;
3521                         } else {
3522                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3523                                           intel_crtc->pipe, crtc->mode.clock);
3524                                 planeb_clock = crtc->mode.clock;
3525                         }
3526                         sr_hdisplay = crtc->mode.hdisplay;
3527                         sr_clock = crtc->mode.clock;
3528                         sr_htotal = crtc->mode.htotal;
3529                         if (crtc->fb)
3530                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3531                         else
3532                                 pixel_size = 4; /* by default */
3533                 }
3534         }
3535
3536         if (enabled <= 0)
3537                 return;
3538
3539         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3540                                     sr_hdisplay, sr_htotal, pixel_size);
3541 }
3542
3543 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3544                                struct drm_display_mode *mode,
3545                                struct drm_display_mode *adjusted_mode,
3546                                int x, int y,
3547                                struct drm_framebuffer *old_fb)
3548 {
3549         struct drm_device *dev = crtc->dev;
3550         struct drm_i915_private *dev_priv = dev->dev_private;
3551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552         int pipe = intel_crtc->pipe;
3553         int plane = intel_crtc->plane;
3554         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3555         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3556         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3557         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3558         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3559         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3560         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3561         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3562         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3563         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3564         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3565         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3566         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3567         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3568         int refclk, num_connectors = 0;
3569         intel_clock_t clock, reduced_clock;
3570         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3571         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3572         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3573         bool is_edp = false;
3574         struct drm_mode_config *mode_config = &dev->mode_config;
3575         struct drm_encoder *encoder;
3576         struct intel_encoder *intel_encoder = NULL;
3577         const intel_limit_t *limit;
3578         int ret;
3579         struct fdi_m_n m_n = {0};
3580         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3581         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3582         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3583         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3584         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3585         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3586         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3587         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3588         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3589         int lvds_reg = LVDS;
3590         u32 temp;
3591         int sdvo_pixel_multiply;
3592         int target_clock;
3593
3594         drm_vblank_pre_modeset(dev, pipe);
3595
3596         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3597
3598                 if (!encoder || encoder->crtc != crtc)
3599                         continue;
3600
3601                 intel_encoder = enc_to_intel_encoder(encoder);
3602
3603                 switch (intel_encoder->type) {
3604                 case INTEL_OUTPUT_LVDS:
3605                         is_lvds = true;
3606                         break;
3607                 case INTEL_OUTPUT_SDVO:
3608                 case INTEL_OUTPUT_HDMI:
3609                         is_sdvo = true;
3610                         if (intel_encoder->needs_tv_clock)
3611                                 is_tv = true;
3612                         break;
3613                 case INTEL_OUTPUT_DVO:
3614                         is_dvo = true;
3615                         break;
3616                 case INTEL_OUTPUT_TVOUT:
3617                         is_tv = true;
3618                         break;
3619                 case INTEL_OUTPUT_ANALOG:
3620                         is_crt = true;
3621                         break;
3622                 case INTEL_OUTPUT_DISPLAYPORT:
3623                         is_dp = true;
3624                         break;
3625                 case INTEL_OUTPUT_EDP:
3626                         is_edp = true;
3627                         break;
3628                 }
3629
3630                 num_connectors++;
3631         }
3632
3633         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3634                 refclk = dev_priv->lvds_ssc_freq * 1000;
3635                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3636                                         refclk / 1000);
3637         } else if (IS_I9XX(dev)) {
3638                 refclk = 96000;
3639                 if (HAS_PCH_SPLIT(dev))
3640                         refclk = 120000; /* 120Mhz refclk */
3641         } else {
3642                 refclk = 48000;
3643         }
3644
3645
3646         /*
3647          * Returns a set of divisors for the desired target clock with the given
3648          * refclk, or FALSE.  The returned values represent the clock equation:
3649          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3650          */
3651         limit = intel_limit(crtc);
3652         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3653         if (!ok) {
3654                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3655                 drm_vblank_post_modeset(dev, pipe);
3656                 return -EINVAL;
3657         }
3658
3659         /* Ensure that the cursor is valid for the new mode before changing... */
3660         intel_crtc_update_cursor(crtc);
3661
3662         if (is_lvds && dev_priv->lvds_downclock_avail) {
3663                 has_reduced_clock = limit->find_pll(limit, crtc,
3664                                                             dev_priv->lvds_downclock,
3665                                                             refclk,
3666                                                             &reduced_clock);
3667                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3668                         /*
3669                          * If the different P is found, it means that we can't
3670                          * switch the display clock by using the FP0/FP1.
3671                          * In such case we will disable the LVDS downclock
3672                          * feature.
3673                          */
3674                         DRM_DEBUG_KMS("Different P is found for "
3675                                                 "LVDS clock/downclock\n");
3676                         has_reduced_clock = 0;
3677                 }
3678         }
3679         /* SDVO TV has fixed PLL values depend on its clock range,
3680            this mirrors vbios setting. */
3681         if (is_sdvo && is_tv) {
3682                 if (adjusted_mode->clock >= 100000
3683                                 && adjusted_mode->clock < 140500) {
3684                         clock.p1 = 2;
3685                         clock.p2 = 10;
3686                         clock.n = 3;
3687                         clock.m1 = 16;
3688                         clock.m2 = 8;
3689                 } else if (adjusted_mode->clock >= 140500
3690                                 && adjusted_mode->clock <= 200000) {
3691                         clock.p1 = 1;
3692                         clock.p2 = 10;
3693                         clock.n = 6;
3694                         clock.m1 = 12;
3695                         clock.m2 = 8;
3696                 }
3697         }
3698
3699         /* FDI link */
3700         if (HAS_PCH_SPLIT(dev)) {
3701                 int lane = 0, link_bw, bpp;
3702                 /* eDP doesn't require FDI link, so just set DP M/N
3703                    according to current link config */
3704                 if (is_edp) {
3705                         target_clock = mode->clock;
3706                         intel_edp_link_config(intel_encoder,
3707                                         &lane, &link_bw);
3708                 } else {
3709                         /* DP over FDI requires target mode clock
3710                            instead of link clock */
3711                         if (is_dp)
3712                                 target_clock = mode->clock;
3713                         else
3714                                 target_clock = adjusted_mode->clock;
3715                         link_bw = 270000;
3716                 }
3717
3718                 /* determine panel color depth */
3719                 temp = I915_READ(pipeconf_reg);
3720                 temp &= ~PIPE_BPC_MASK;
3721                 if (is_lvds) {
3722                         int lvds_reg = I915_READ(PCH_LVDS);
3723                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3724                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3725                                 temp |= PIPE_8BPC;
3726                         else
3727                                 temp |= PIPE_6BPC;
3728                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3729                         switch (dev_priv->edp_bpp/3) {
3730                         case 8:
3731                                 temp |= PIPE_8BPC;
3732                                 break;
3733                         case 10:
3734                                 temp |= PIPE_10BPC;
3735                                 break;
3736                         case 6:
3737                                 temp |= PIPE_6BPC;
3738                                 break;
3739                         case 12:
3740                                 temp |= PIPE_12BPC;
3741                                 break;
3742                         }
3743                 } else
3744                         temp |= PIPE_8BPC;
3745                 I915_WRITE(pipeconf_reg, temp);
3746                 I915_READ(pipeconf_reg);
3747
3748                 switch (temp & PIPE_BPC_MASK) {
3749                 case PIPE_8BPC:
3750                         bpp = 24;
3751                         break;
3752                 case PIPE_10BPC:
3753                         bpp = 30;
3754                         break;
3755                 case PIPE_6BPC:
3756                         bpp = 18;
3757                         break;
3758                 case PIPE_12BPC:
3759                         bpp = 36;
3760                         break;
3761                 default:
3762                         DRM_ERROR("unknown pipe bpc value\n");
3763                         bpp = 24;
3764                 }
3765
3766                 if (!lane) {
3767                         /*
3768                          * Account for spread spectrum to avoid
3769                          * oversubscribing the link. Max center spread
3770                          * is 2.5%; use 5% for safety's sake.
3771                          */
3772                         u32 bps = target_clock * bpp * 21 / 20;
3773                         lane = bps / (link_bw * 8) + 1;
3774                 }
3775
3776                 intel_crtc->fdi_lanes = lane;
3777
3778                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3779         }
3780
3781         /* Ironlake: try to setup display ref clock before DPLL
3782          * enabling. This is only under driver's control after
3783          * PCH B stepping, previous chipset stepping should be
3784          * ignoring this setting.
3785          */
3786         if (HAS_PCH_SPLIT(dev)) {
3787                 temp = I915_READ(PCH_DREF_CONTROL);
3788                 /* Always enable nonspread source */
3789                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3790                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3791                 I915_WRITE(PCH_DREF_CONTROL, temp);
3792                 POSTING_READ(PCH_DREF_CONTROL);
3793
3794                 temp &= ~DREF_SSC_SOURCE_MASK;
3795                 temp |= DREF_SSC_SOURCE_ENABLE;
3796                 I915_WRITE(PCH_DREF_CONTROL, temp);
3797                 POSTING_READ(PCH_DREF_CONTROL);
3798
3799                 udelay(200);
3800
3801                 if (is_edp) {
3802                         if (dev_priv->lvds_use_ssc) {
3803                                 temp |= DREF_SSC1_ENABLE;
3804                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3805                                 POSTING_READ(PCH_DREF_CONTROL);
3806
3807                                 udelay(200);
3808
3809                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3810                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3811                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3812                                 POSTING_READ(PCH_DREF_CONTROL);
3813                         } else {
3814                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3815                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3816                                 POSTING_READ(PCH_DREF_CONTROL);
3817                         }
3818                 }
3819         }
3820
3821         if (IS_PINEVIEW(dev)) {
3822                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3823                 if (has_reduced_clock)
3824                         fp2 = (1 << reduced_clock.n) << 16 |
3825                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3826         } else {
3827                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3828                 if (has_reduced_clock)
3829                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3830                                 reduced_clock.m2;
3831         }
3832
3833         if (!HAS_PCH_SPLIT(dev))
3834                 dpll = DPLL_VGA_MODE_DIS;
3835
3836         if (IS_I9XX(dev)) {
3837                 if (is_lvds)
3838                         dpll |= DPLLB_MODE_LVDS;
3839                 else
3840                         dpll |= DPLLB_MODE_DAC_SERIAL;
3841                 if (is_sdvo) {
3842                         dpll |= DPLL_DVO_HIGH_SPEED;
3843                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3844                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3845                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3846                         else if (HAS_PCH_SPLIT(dev))
3847                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3848                 }
3849                 if (is_dp)
3850                         dpll |= DPLL_DVO_HIGH_SPEED;
3851
3852                 /* compute bitmask from p1 value */
3853                 if (IS_PINEVIEW(dev))
3854                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3855                 else {
3856                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3857                         /* also FPA1 */
3858                         if (HAS_PCH_SPLIT(dev))
3859                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3860                         if (IS_G4X(dev) && has_reduced_clock)
3861                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3862                 }
3863                 switch (clock.p2) {
3864                 case 5:
3865                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3866                         break;
3867                 case 7:
3868                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3869                         break;
3870                 case 10:
3871                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3872                         break;
3873                 case 14:
3874                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3875                         break;
3876                 }
3877                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3878                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3879         } else {
3880                 if (is_lvds) {
3881                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3882                 } else {
3883                         if (clock.p1 == 2)
3884                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3885                         else
3886                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3887                         if (clock.p2 == 4)
3888                                 dpll |= PLL_P2_DIVIDE_BY_4;
3889                 }
3890         }
3891
3892         if (is_sdvo && is_tv)
3893                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3894         else if (is_tv)
3895                 /* XXX: just matching BIOS for now */
3896                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3897                 dpll |= 3;
3898         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3899                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3900         else
3901                 dpll |= PLL_REF_INPUT_DREFCLK;
3902
3903         /* setup pipeconf */
3904         pipeconf = I915_READ(pipeconf_reg);
3905
3906         /* Set up the display plane register */
3907         dspcntr = DISPPLANE_GAMMA_ENABLE;
3908
3909         /* Ironlake's plane is forced to pipe, bit 24 is to
3910            enable color space conversion */
3911         if (!HAS_PCH_SPLIT(dev)) {
3912                 if (pipe == 0)
3913                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3914                 else
3915                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3916         }
3917
3918         if (pipe == 0 && !IS_I965G(dev)) {
3919                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3920                  * core speed.
3921                  *
3922                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3923                  * pipe == 0 check?
3924                  */
3925                 if (mode->clock >
3926                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3927                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3928                 else
3929                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3930         }
3931
3932         dspcntr |= DISPLAY_PLANE_ENABLE;
3933         pipeconf |= PIPEACONF_ENABLE;
3934         dpll |= DPLL_VCO_ENABLE;
3935
3936
3937         /* Disable the panel fitter if it was on our pipe */
3938         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3939                 I915_WRITE(PFIT_CONTROL, 0);
3940
3941         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3942         drm_mode_debug_printmodeline(mode);
3943
3944         /* assign to Ironlake registers */
3945         if (HAS_PCH_SPLIT(dev)) {
3946                 fp_reg = pch_fp_reg;
3947                 dpll_reg = pch_dpll_reg;
3948         }
3949
3950         if (!is_edp) {
3951                 I915_WRITE(fp_reg, fp);
3952                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3953                 I915_READ(dpll_reg);
3954                 udelay(150);
3955         }
3956
3957         /* enable transcoder DPLL */
3958         if (HAS_PCH_CPT(dev)) {
3959                 temp = I915_READ(PCH_DPLL_SEL);
3960                 if (trans_dpll_sel == 0)
3961                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3962                 else
3963                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3964                 I915_WRITE(PCH_DPLL_SEL, temp);
3965                 I915_READ(PCH_DPLL_SEL);
3966                 udelay(150);
3967         }
3968
3969         if (HAS_PCH_SPLIT(dev)) {
3970                 pipeconf &= ~PIPE_ENABLE_DITHER;
3971                 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3972         }
3973
3974         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3975          * This is an exception to the general rule that mode_set doesn't turn
3976          * things on.
3977          */
3978         if (is_lvds) {
3979                 u32 lvds;
3980
3981                 if (HAS_PCH_SPLIT(dev))
3982                         lvds_reg = PCH_LVDS;
3983
3984                 lvds = I915_READ(lvds_reg);
3985                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3986                 if (pipe == 1) {
3987                         if (HAS_PCH_CPT(dev))
3988                                 lvds |= PORT_TRANS_B_SEL_CPT;
3989                         else
3990                                 lvds |= LVDS_PIPEB_SELECT;
3991                 } else {
3992                         if (HAS_PCH_CPT(dev))
3993                                 lvds &= ~PORT_TRANS_SEL_MASK;
3994                         else
3995                                 lvds &= ~LVDS_PIPEB_SELECT;
3996                 }
3997                 /* set the corresponsding LVDS_BORDER bit */
3998                 lvds |= dev_priv->lvds_border_bits;
3999                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4000                  * set the DPLLs for dual-channel mode or not.
4001                  */
4002                 if (clock.p2 == 7)
4003                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4004                 else
4005                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4006
4007                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4008                  * appropriately here, but we need to look more thoroughly into how
4009                  * panels behave in the two modes.
4010                  */
4011                 /* set the dithering flag */
4012                 if (IS_I965G(dev)) {
4013                         if (dev_priv->lvds_dither) {
4014                                 if (HAS_PCH_SPLIT(dev)) {
4015                                         pipeconf |= PIPE_ENABLE_DITHER;
4016                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
4017                                 } else
4018                                         lvds |= LVDS_ENABLE_DITHER;
4019                         } else {
4020                                 if (!HAS_PCH_SPLIT(dev)) {
4021                                         lvds &= ~LVDS_ENABLE_DITHER;
4022                                 }
4023                         }
4024                 }
4025                 I915_WRITE(lvds_reg, lvds);
4026                 I915_READ(lvds_reg);
4027         }
4028         if (is_dp)
4029                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4030         else if (HAS_PCH_SPLIT(dev)) {
4031                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4032                 if (pipe == 0) {
4033                         I915_WRITE(TRANSA_DATA_M1, 0);
4034                         I915_WRITE(TRANSA_DATA_N1, 0);
4035                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4036                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4037                 } else {
4038                         I915_WRITE(TRANSB_DATA_M1, 0);
4039                         I915_WRITE(TRANSB_DATA_N1, 0);
4040                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4041                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4042                 }
4043         }
4044
4045         if (!is_edp) {
4046                 I915_WRITE(fp_reg, fp);
4047                 I915_WRITE(dpll_reg, dpll);
4048                 I915_READ(dpll_reg);
4049                 /* Wait for the clocks to stabilize. */
4050                 udelay(150);
4051
4052                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4053                         if (is_sdvo) {
4054                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4055                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4056                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4057                         } else
4058                                 I915_WRITE(dpll_md_reg, 0);
4059                 } else {
4060                         /* write it again -- the BIOS does, after all */
4061                         I915_WRITE(dpll_reg, dpll);
4062                 }
4063                 I915_READ(dpll_reg);
4064                 /* Wait for the clocks to stabilize. */
4065                 udelay(150);
4066         }
4067
4068         if (is_lvds && has_reduced_clock && i915_powersave) {
4069                 I915_WRITE(fp_reg + 4, fp2);
4070                 intel_crtc->lowfreq_avail = true;
4071                 if (HAS_PIPE_CXSR(dev)) {
4072                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4073                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4074                 }
4075         } else {
4076                 I915_WRITE(fp_reg + 4, fp);
4077                 intel_crtc->lowfreq_avail = false;
4078                 if (HAS_PIPE_CXSR(dev)) {
4079                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4080                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4081                 }
4082         }
4083
4084         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4085                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4086                 /* the chip adds 2 halflines automatically */
4087                 adjusted_mode->crtc_vdisplay -= 1;
4088                 adjusted_mode->crtc_vtotal -= 1;
4089                 adjusted_mode->crtc_vblank_start -= 1;
4090                 adjusted_mode->crtc_vblank_end -= 1;
4091                 adjusted_mode->crtc_vsync_end -= 1;
4092                 adjusted_mode->crtc_vsync_start -= 1;
4093         } else
4094                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4095
4096         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4097                    ((adjusted_mode->crtc_htotal - 1) << 16));
4098         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4099                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4100         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4101                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4102         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4103                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4104         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4105                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4106         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4107                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4108         /* pipesrc and dspsize control the size that is scaled from, which should
4109          * always be the user's requested size.
4110          */
4111         if (!HAS_PCH_SPLIT(dev)) {
4112                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4113                                 (mode->hdisplay - 1));
4114                 I915_WRITE(dsppos_reg, 0);
4115         }
4116         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4117
4118         if (HAS_PCH_SPLIT(dev)) {
4119                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4120                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4121                 I915_WRITE(link_m1_reg, m_n.link_m);
4122                 I915_WRITE(link_n1_reg, m_n.link_n);
4123
4124                 if (is_edp) {
4125                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4126                 } else {
4127                         /* enable FDI RX PLL too */
4128                         temp = I915_READ(fdi_rx_reg);
4129                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4130                         I915_READ(fdi_rx_reg);
4131                         udelay(200);
4132
4133                         /* enable FDI TX PLL too */
4134                         temp = I915_READ(fdi_tx_reg);
4135                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4136                         I915_READ(fdi_tx_reg);
4137
4138                         /* enable FDI RX PCDCLK */
4139                         temp = I915_READ(fdi_rx_reg);
4140                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4141                         I915_READ(fdi_rx_reg);
4142                         udelay(200);
4143                 }
4144         }
4145
4146         I915_WRITE(pipeconf_reg, pipeconf);
4147         I915_READ(pipeconf_reg);
4148
4149         intel_wait_for_vblank(dev, pipe);
4150
4151         if (IS_IRONLAKE(dev)) {
4152                 /* enable address swizzle for tiling buffer */
4153                 temp = I915_READ(DISP_ARB_CTL);
4154                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4155         }
4156
4157         I915_WRITE(dspcntr_reg, dspcntr);
4158
4159         /* Flush the plane changes */
4160         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4161
4162         intel_update_watermarks(dev);
4163
4164         drm_vblank_post_modeset(dev, pipe);
4165
4166         return ret;
4167 }
4168
4169 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4170 void intel_crtc_load_lut(struct drm_crtc *crtc)
4171 {
4172         struct drm_device *dev = crtc->dev;
4173         struct drm_i915_private *dev_priv = dev->dev_private;
4174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4176         int i;
4177
4178         /* The clocks have to be on to load the palette. */
4179         if (!crtc->enabled)
4180                 return;
4181
4182         /* use legacy palette for Ironlake */
4183         if (HAS_PCH_SPLIT(dev))
4184                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4185                                                    LGC_PALETTE_B;
4186
4187         for (i = 0; i < 256; i++) {
4188                 I915_WRITE(palreg + 4 * i,
4189                            (intel_crtc->lut_r[i] << 16) |
4190                            (intel_crtc->lut_g[i] << 8) |
4191                            intel_crtc->lut_b[i]);
4192         }
4193 }
4194
4195 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4196 {
4197         struct drm_device *dev = crtc->dev;
4198         struct drm_i915_private *dev_priv = dev->dev_private;
4199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4200         bool visible = base != 0;
4201         u32 cntl;
4202
4203         if (intel_crtc->cursor_visible == visible)
4204                 return;
4205
4206         cntl = I915_READ(CURACNTR);
4207         if (visible) {
4208                 /* On these chipsets we can only modify the base whilst
4209                  * the cursor is disabled.
4210                  */
4211                 I915_WRITE(CURABASE, base);
4212
4213                 cntl &= ~(CURSOR_FORMAT_MASK);
4214                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4215                 cntl |= CURSOR_ENABLE |
4216                         CURSOR_GAMMA_ENABLE |
4217                         CURSOR_FORMAT_ARGB;
4218         } else
4219                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4220         I915_WRITE(CURACNTR, cntl);
4221
4222         intel_crtc->cursor_visible = visible;
4223 }
4224
4225 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4226 {
4227         struct drm_device *dev = crtc->dev;
4228         struct drm_i915_private *dev_priv = dev->dev_private;
4229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4230         int pipe = intel_crtc->pipe;
4231         bool visible = base != 0;
4232
4233         if (intel_crtc->cursor_visible != visible) {
4234                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4235                 if (base) {
4236                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4237                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4238                         cntl |= pipe << 28; /* Connect to correct pipe */
4239                 } else {
4240                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4241                         cntl |= CURSOR_MODE_DISABLE;
4242                 }
4243                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4244
4245                 intel_crtc->cursor_visible = visible;
4246         }
4247         /* and commit changes on next vblank */
4248         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4249 }
4250
4251 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4252 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4253 {
4254         struct drm_device *dev = crtc->dev;
4255         struct drm_i915_private *dev_priv = dev->dev_private;
4256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4257         int pipe = intel_crtc->pipe;
4258         int x = intel_crtc->cursor_x;
4259         int y = intel_crtc->cursor_y;
4260         u32 base, pos;
4261         bool visible;
4262
4263         pos = 0;
4264
4265         if (intel_crtc->cursor_on && crtc->fb) {
4266                 base = intel_crtc->cursor_addr;
4267                 if (x > (int) crtc->fb->width)
4268                         base = 0;
4269
4270                 if (y > (int) crtc->fb->height)
4271                         base = 0;
4272         } else
4273                 base = 0;
4274
4275         if (x < 0) {
4276                 if (x + intel_crtc->cursor_width < 0)
4277                         base = 0;
4278
4279                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4280                 x = -x;
4281         }
4282         pos |= x << CURSOR_X_SHIFT;
4283
4284         if (y < 0) {
4285                 if (y + intel_crtc->cursor_height < 0)
4286                         base = 0;
4287
4288                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4289                 y = -y;
4290         }
4291         pos |= y << CURSOR_Y_SHIFT;
4292
4293         visible = base != 0;
4294         if (!visible && !intel_crtc->cursor_visible)
4295                 return;
4296
4297         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4298         if (IS_845G(dev) || IS_I865G(dev))
4299                 i845_update_cursor(crtc, base);
4300         else
4301                 i9xx_update_cursor(crtc, base);
4302
4303         if (visible)
4304                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4305 }
4306
4307 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4308                                  struct drm_file *file_priv,
4309                                  uint32_t handle,
4310                                  uint32_t width, uint32_t height)
4311 {
4312         struct drm_device *dev = crtc->dev;
4313         struct drm_i915_private *dev_priv = dev->dev_private;
4314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4315         struct drm_gem_object *bo;
4316         struct drm_i915_gem_object *obj_priv;
4317         uint32_t addr;
4318         int ret;
4319
4320         DRM_DEBUG_KMS("\n");
4321
4322         /* if we want to turn off the cursor ignore width and height */
4323         if (!handle) {
4324                 DRM_DEBUG_KMS("cursor off\n");
4325                 addr = 0;
4326                 bo = NULL;
4327                 mutex_lock(&dev->struct_mutex);
4328                 goto finish;
4329         }
4330
4331         /* Currently we only support 64x64 cursors */
4332         if (width != 64 || height != 64) {
4333                 DRM_ERROR("we currently only support 64x64 cursors\n");
4334                 return -EINVAL;
4335         }
4336
4337         bo = drm_gem_object_lookup(dev, file_priv, handle);
4338         if (!bo)
4339                 return -ENOENT;
4340
4341         obj_priv = to_intel_bo(bo);
4342
4343         if (bo->size < width * height * 4) {
4344                 DRM_ERROR("buffer is to small\n");
4345                 ret = -ENOMEM;
4346                 goto fail;
4347         }
4348
4349         /* we only need to pin inside GTT if cursor is non-phy */
4350         mutex_lock(&dev->struct_mutex);
4351         if (!dev_priv->info->cursor_needs_physical) {
4352                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4353                 if (ret) {
4354                         DRM_ERROR("failed to pin cursor bo\n");
4355                         goto fail_locked;
4356                 }
4357
4358                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4359                 if (ret) {
4360                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4361                         goto fail_unpin;
4362                 }
4363
4364                 addr = obj_priv->gtt_offset;
4365         } else {
4366                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4367                 ret = i915_gem_attach_phys_object(dev, bo,
4368                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4369                                                   align);
4370                 if (ret) {
4371                         DRM_ERROR("failed to attach phys object\n");
4372                         goto fail_locked;
4373                 }
4374                 addr = obj_priv->phys_obj->handle->busaddr;
4375         }
4376
4377         if (!IS_I9XX(dev))
4378                 I915_WRITE(CURSIZE, (height << 12) | width);
4379
4380  finish:
4381         if (intel_crtc->cursor_bo) {
4382                 if (dev_priv->info->cursor_needs_physical) {
4383                         if (intel_crtc->cursor_bo != bo)
4384                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4385                 } else
4386                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4387                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4388         }
4389
4390         mutex_unlock(&dev->struct_mutex);
4391
4392         intel_crtc->cursor_addr = addr;
4393         intel_crtc->cursor_bo = bo;
4394         intel_crtc->cursor_width = width;
4395         intel_crtc->cursor_height = height;
4396
4397         intel_crtc_update_cursor(crtc);
4398
4399         return 0;
4400 fail_unpin:
4401         i915_gem_object_unpin(bo);
4402 fail_locked:
4403         mutex_unlock(&dev->struct_mutex);
4404 fail:
4405         drm_gem_object_unreference_unlocked(bo);
4406         return ret;
4407 }
4408
4409 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4410 {
4411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412
4413         intel_crtc->cursor_x = x;
4414         intel_crtc->cursor_y = y;
4415
4416         intel_crtc_update_cursor(crtc);
4417
4418         return 0;
4419 }
4420
4421 /** Sets the color ramps on behalf of RandR */
4422 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4423                                  u16 blue, int regno)
4424 {
4425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4426
4427         intel_crtc->lut_r[regno] = red >> 8;
4428         intel_crtc->lut_g[regno] = green >> 8;
4429         intel_crtc->lut_b[regno] = blue >> 8;
4430 }
4431
4432 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4433                              u16 *blue, int regno)
4434 {
4435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4436
4437         *red = intel_crtc->lut_r[regno] << 8;
4438         *green = intel_crtc->lut_g[regno] << 8;
4439         *blue = intel_crtc->lut_b[regno] << 8;
4440 }
4441
4442 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4443                                  u16 *blue, uint32_t start, uint32_t size)
4444 {
4445         int end = (start + size > 256) ? 256 : start + size, i;
4446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4447
4448         for (i = start; i < end; i++) {
4449                 intel_crtc->lut_r[i] = red[i] >> 8;
4450                 intel_crtc->lut_g[i] = green[i] >> 8;
4451                 intel_crtc->lut_b[i] = blue[i] >> 8;
4452         }
4453
4454         intel_crtc_load_lut(crtc);
4455 }
4456
4457 /**
4458  * Get a pipe with a simple mode set on it for doing load-based monitor
4459  * detection.
4460  *
4461  * It will be up to the load-detect code to adjust the pipe as appropriate for
4462  * its requirements.  The pipe will be connected to no other encoders.
4463  *
4464  * Currently this code will only succeed if there is a pipe with no encoders
4465  * configured for it.  In the future, it could choose to temporarily disable
4466  * some outputs to free up a pipe for its use.
4467  *
4468  * \return crtc, or NULL if no pipes are available.
4469  */
4470
4471 /* VESA 640x480x72Hz mode to set on the pipe */
4472 static struct drm_display_mode load_detect_mode = {
4473         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4474                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4475 };
4476
4477 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4478                                             struct drm_connector *connector,
4479                                             struct drm_display_mode *mode,
4480                                             int *dpms_mode)
4481 {
4482         struct intel_crtc *intel_crtc;
4483         struct drm_crtc *possible_crtc;
4484         struct drm_crtc *supported_crtc =NULL;
4485         struct drm_encoder *encoder = &intel_encoder->enc;
4486         struct drm_crtc *crtc = NULL;
4487         struct drm_device *dev = encoder->dev;
4488         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4489         struct drm_crtc_helper_funcs *crtc_funcs;
4490         int i = -1;
4491
4492         /*
4493          * Algorithm gets a little messy:
4494          *   - if the connector already has an assigned crtc, use it (but make
4495          *     sure it's on first)
4496          *   - try to find the first unused crtc that can drive this connector,
4497          *     and use that if we find one
4498          *   - if there are no unused crtcs available, try to use the first
4499          *     one we found that supports the connector
4500          */
4501
4502         /* See if we already have a CRTC for this connector */
4503         if (encoder->crtc) {
4504                 crtc = encoder->crtc;
4505                 /* Make sure the crtc and connector are running */
4506                 intel_crtc = to_intel_crtc(crtc);
4507                 *dpms_mode = intel_crtc->dpms_mode;
4508                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4509                         crtc_funcs = crtc->helper_private;
4510                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4511                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4512                 }
4513                 return crtc;
4514         }
4515
4516         /* Find an unused one (if possible) */
4517         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4518                 i++;
4519                 if (!(encoder->possible_crtcs & (1 << i)))
4520                         continue;
4521                 if (!possible_crtc->enabled) {
4522                         crtc = possible_crtc;
4523                         break;
4524                 }
4525                 if (!supported_crtc)
4526                         supported_crtc = possible_crtc;
4527         }
4528
4529         /*
4530          * If we didn't find an unused CRTC, don't use any.
4531          */
4532         if (!crtc) {
4533                 return NULL;
4534         }
4535
4536         encoder->crtc = crtc;
4537         connector->encoder = encoder;
4538         intel_encoder->load_detect_temp = true;
4539
4540         intel_crtc = to_intel_crtc(crtc);
4541         *dpms_mode = intel_crtc->dpms_mode;
4542
4543         if (!crtc->enabled) {
4544                 if (!mode)
4545                         mode = &load_detect_mode;
4546                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4547         } else {
4548                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4549                         crtc_funcs = crtc->helper_private;
4550                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4551                 }
4552
4553                 /* Add this connector to the crtc */
4554                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4555                 encoder_funcs->commit(encoder);
4556         }
4557         /* let the connector get through one full cycle before testing */
4558         intel_wait_for_vblank(dev, intel_crtc->pipe);
4559
4560         return crtc;
4561 }
4562
4563 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4564                                     struct drm_connector *connector, int dpms_mode)
4565 {
4566         struct drm_encoder *encoder = &intel_encoder->enc;
4567         struct drm_device *dev = encoder->dev;
4568         struct drm_crtc *crtc = encoder->crtc;
4569         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4570         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4571
4572         if (intel_encoder->load_detect_temp) {
4573                 encoder->crtc = NULL;
4574                 connector->encoder = NULL;
4575                 intel_encoder->load_detect_temp = false;
4576                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4577                 drm_helper_disable_unused_functions(dev);
4578         }
4579
4580         /* Switch crtc and encoder back off if necessary */
4581         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4582                 if (encoder->crtc == crtc)
4583                         encoder_funcs->dpms(encoder, dpms_mode);
4584                 crtc_funcs->dpms(crtc, dpms_mode);
4585         }
4586 }
4587
4588 /* Returns the clock of the currently programmed mode of the given pipe. */
4589 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4590 {
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593         int pipe = intel_crtc->pipe;
4594         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4595         u32 fp;
4596         intel_clock_t clock;
4597
4598         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4599                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4600         else
4601                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4602
4603         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4604         if (IS_PINEVIEW(dev)) {
4605                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4606                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4607         } else {
4608                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4609                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4610         }
4611
4612         if (IS_I9XX(dev)) {
4613                 if (IS_PINEVIEW(dev))
4614                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4615                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4616                 else
4617                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4618                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4619
4620                 switch (dpll & DPLL_MODE_MASK) {
4621                 case DPLLB_MODE_DAC_SERIAL:
4622                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4623                                 5 : 10;
4624                         break;
4625                 case DPLLB_MODE_LVDS:
4626                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4627                                 7 : 14;
4628                         break;
4629                 default:
4630                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4631                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4632                         return 0;
4633                 }
4634
4635                 /* XXX: Handle the 100Mhz refclk */
4636                 intel_clock(dev, 96000, &clock);
4637         } else {
4638                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4639
4640                 if (is_lvds) {
4641                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4642                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4643                         clock.p2 = 14;
4644
4645                         if ((dpll & PLL_REF_INPUT_MASK) ==
4646                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4647                                 /* XXX: might not be 66MHz */
4648                                 intel_clock(dev, 66000, &clock);
4649                         } else
4650                                 intel_clock(dev, 48000, &clock);
4651                 } else {
4652                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4653                                 clock.p1 = 2;
4654                         else {
4655                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4656                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4657                         }
4658                         if (dpll & PLL_P2_DIVIDE_BY_4)
4659                                 clock.p2 = 4;
4660                         else
4661                                 clock.p2 = 2;
4662
4663                         intel_clock(dev, 48000, &clock);
4664                 }
4665         }
4666
4667         /* XXX: It would be nice to validate the clocks, but we can't reuse
4668          * i830PllIsValid() because it relies on the xf86_config connector
4669          * configuration being accurate, which it isn't necessarily.
4670          */
4671
4672         return clock.dot;
4673 }
4674
4675 /** Returns the currently programmed mode of the given pipe. */
4676 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4677                                              struct drm_crtc *crtc)
4678 {
4679         struct drm_i915_private *dev_priv = dev->dev_private;
4680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4681         int pipe = intel_crtc->pipe;
4682         struct drm_display_mode *mode;
4683         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4684         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4685         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4686         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4687
4688         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4689         if (!mode)
4690                 return NULL;
4691
4692         mode->clock = intel_crtc_clock_get(dev, crtc);
4693         mode->hdisplay = (htot & 0xffff) + 1;
4694         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4695         mode->hsync_start = (hsync & 0xffff) + 1;
4696         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4697         mode->vdisplay = (vtot & 0xffff) + 1;
4698         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4699         mode->vsync_start = (vsync & 0xffff) + 1;
4700         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4701
4702         drm_mode_set_name(mode);
4703         drm_mode_set_crtcinfo(mode, 0);
4704
4705         return mode;
4706 }
4707
4708 #define GPU_IDLE_TIMEOUT 500 /* ms */
4709
4710 /* When this timer fires, we've been idle for awhile */
4711 static void intel_gpu_idle_timer(unsigned long arg)
4712 {
4713         struct drm_device *dev = (struct drm_device *)arg;
4714         drm_i915_private_t *dev_priv = dev->dev_private;
4715
4716         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4717
4718         dev_priv->busy = false;
4719
4720         queue_work(dev_priv->wq, &dev_priv->idle_work);
4721 }
4722
4723 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4724
4725 static void intel_crtc_idle_timer(unsigned long arg)
4726 {
4727         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4728         struct drm_crtc *crtc = &intel_crtc->base;
4729         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4730
4731         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4732
4733         intel_crtc->busy = false;
4734
4735         queue_work(dev_priv->wq, &dev_priv->idle_work);
4736 }
4737
4738 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4739 {
4740         struct drm_device *dev = crtc->dev;
4741         drm_i915_private_t *dev_priv = dev->dev_private;
4742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743         int pipe = intel_crtc->pipe;
4744         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4745         int dpll = I915_READ(dpll_reg);
4746
4747         if (HAS_PCH_SPLIT(dev))
4748                 return;
4749
4750         if (!dev_priv->lvds_downclock_avail)
4751                 return;
4752
4753         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4754                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4755
4756                 /* Unlock panel regs */
4757                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4758                            PANEL_UNLOCK_REGS);
4759
4760                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4761                 I915_WRITE(dpll_reg, dpll);
4762                 dpll = I915_READ(dpll_reg);
4763                 intel_wait_for_vblank(dev, pipe);
4764                 dpll = I915_READ(dpll_reg);
4765                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4766                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4767
4768                 /* ...and lock them again */
4769                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4770         }
4771
4772         /* Schedule downclock */
4773         if (schedule)
4774                 mod_timer(&intel_crtc->idle_timer, jiffies +
4775                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4776 }
4777
4778 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4779 {
4780         struct drm_device *dev = crtc->dev;
4781         drm_i915_private_t *dev_priv = dev->dev_private;
4782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4783         int pipe = intel_crtc->pipe;
4784         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4785         int dpll = I915_READ(dpll_reg);
4786
4787         if (HAS_PCH_SPLIT(dev))
4788                 return;
4789
4790         if (!dev_priv->lvds_downclock_avail)
4791                 return;
4792
4793         /*
4794          * Since this is called by a timer, we should never get here in
4795          * the manual case.
4796          */
4797         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4798                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4799
4800                 /* Unlock panel regs */
4801                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4802                            PANEL_UNLOCK_REGS);
4803
4804                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4805                 I915_WRITE(dpll_reg, dpll);
4806                 dpll = I915_READ(dpll_reg);
4807                 intel_wait_for_vblank(dev, pipe);
4808                 dpll = I915_READ(dpll_reg);
4809                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4810                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4811
4812                 /* ...and lock them again */
4813                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4814         }
4815
4816 }
4817
4818 /**
4819  * intel_idle_update - adjust clocks for idleness
4820  * @work: work struct
4821  *
4822  * Either the GPU or display (or both) went idle.  Check the busy status
4823  * here and adjust the CRTC and GPU clocks as necessary.
4824  */
4825 static void intel_idle_update(struct work_struct *work)
4826 {
4827         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4828                                                     idle_work);
4829         struct drm_device *dev = dev_priv->dev;
4830         struct drm_crtc *crtc;
4831         struct intel_crtc *intel_crtc;
4832         int enabled = 0;
4833
4834         if (!i915_powersave)
4835                 return;
4836
4837         mutex_lock(&dev->struct_mutex);
4838
4839         i915_update_gfx_val(dev_priv);
4840
4841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4842                 /* Skip inactive CRTCs */
4843                 if (!crtc->fb)
4844                         continue;
4845
4846                 enabled++;
4847                 intel_crtc = to_intel_crtc(crtc);
4848                 if (!intel_crtc->busy)
4849                         intel_decrease_pllclock(crtc);
4850         }
4851
4852         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4853                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4854                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4855         }
4856
4857         mutex_unlock(&dev->struct_mutex);
4858 }
4859
4860 /**
4861  * intel_mark_busy - mark the GPU and possibly the display busy
4862  * @dev: drm device
4863  * @obj: object we're operating on
4864  *
4865  * Callers can use this function to indicate that the GPU is busy processing
4866  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4867  * buffer), we'll also mark the display as busy, so we know to increase its
4868  * clock frequency.
4869  */
4870 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4871 {
4872         drm_i915_private_t *dev_priv = dev->dev_private;
4873         struct drm_crtc *crtc = NULL;
4874         struct intel_framebuffer *intel_fb;
4875         struct intel_crtc *intel_crtc;
4876
4877         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4878                 return;
4879
4880         if (!dev_priv->busy) {
4881                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4882                         u32 fw_blc_self;
4883
4884                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4885                         fw_blc_self = I915_READ(FW_BLC_SELF);
4886                         fw_blc_self &= ~FW_BLC_SELF_EN;
4887                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4888                 }
4889                 dev_priv->busy = true;
4890         } else
4891                 mod_timer(&dev_priv->idle_timer, jiffies +
4892                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4893
4894         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4895                 if (!crtc->fb)
4896                         continue;
4897
4898                 intel_crtc = to_intel_crtc(crtc);
4899                 intel_fb = to_intel_framebuffer(crtc->fb);
4900                 if (intel_fb->obj == obj) {
4901                         if (!intel_crtc->busy) {
4902                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4903                                         u32 fw_blc_self;
4904
4905                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4906                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4907                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4908                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4909                                 }
4910                                 /* Non-busy -> busy, upclock */
4911                                 intel_increase_pllclock(crtc, true);
4912                                 intel_crtc->busy = true;
4913                         } else {
4914                                 /* Busy -> busy, put off timer */
4915                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4916                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4917                         }
4918                 }
4919         }
4920 }
4921
4922 static void intel_crtc_destroy(struct drm_crtc *crtc)
4923 {
4924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4925
4926         drm_crtc_cleanup(crtc);
4927         kfree(intel_crtc);
4928 }
4929
4930 struct intel_unpin_work {
4931         struct work_struct work;
4932         struct drm_device *dev;
4933         struct drm_gem_object *old_fb_obj;
4934         struct drm_gem_object *pending_flip_obj;
4935         struct drm_pending_vblank_event *event;
4936         int pending;
4937 };
4938
4939 static void intel_unpin_work_fn(struct work_struct *__work)
4940 {
4941         struct intel_unpin_work *work =
4942                 container_of(__work, struct intel_unpin_work, work);
4943
4944         mutex_lock(&work->dev->struct_mutex);
4945         i915_gem_object_unpin(work->old_fb_obj);
4946         drm_gem_object_unreference(work->pending_flip_obj);
4947         drm_gem_object_unreference(work->old_fb_obj);
4948         mutex_unlock(&work->dev->struct_mutex);
4949         kfree(work);
4950 }
4951
4952 static void do_intel_finish_page_flip(struct drm_device *dev,
4953                                       struct drm_crtc *crtc)
4954 {
4955         drm_i915_private_t *dev_priv = dev->dev_private;
4956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4957         struct intel_unpin_work *work;
4958         struct drm_i915_gem_object *obj_priv;
4959         struct drm_pending_vblank_event *e;
4960         struct timeval now;
4961         unsigned long flags;
4962
4963         /* Ignore early vblank irqs */
4964         if (intel_crtc == NULL)
4965                 return;
4966
4967         spin_lock_irqsave(&dev->event_lock, flags);
4968         work = intel_crtc->unpin_work;
4969         if (work == NULL || !work->pending) {
4970                 spin_unlock_irqrestore(&dev->event_lock, flags);
4971                 return;
4972         }
4973
4974         intel_crtc->unpin_work = NULL;
4975         drm_vblank_put(dev, intel_crtc->pipe);
4976
4977         if (work->event) {
4978                 e = work->event;
4979                 do_gettimeofday(&now);
4980                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4981                 e->event.tv_sec = now.tv_sec;
4982                 e->event.tv_usec = now.tv_usec;
4983                 list_add_tail(&e->base.link,
4984                               &e->base.file_priv->event_list);
4985                 wake_up_interruptible(&e->base.file_priv->event_wait);
4986         }
4987
4988         spin_unlock_irqrestore(&dev->event_lock, flags);
4989
4990         obj_priv = to_intel_bo(work->pending_flip_obj);
4991
4992         /* Initial scanout buffer will have a 0 pending flip count */
4993         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4994             atomic_dec_and_test(&obj_priv->pending_flip))
4995                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4996         schedule_work(&work->work);
4997
4998         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4999 }
5000
5001 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5002 {
5003         drm_i915_private_t *dev_priv = dev->dev_private;
5004         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5005
5006         do_intel_finish_page_flip(dev, crtc);
5007 }
5008
5009 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5010 {
5011         drm_i915_private_t *dev_priv = dev->dev_private;
5012         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5013
5014         do_intel_finish_page_flip(dev, crtc);
5015 }
5016
5017 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5018 {
5019         drm_i915_private_t *dev_priv = dev->dev_private;
5020         struct intel_crtc *intel_crtc =
5021                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5022         unsigned long flags;
5023
5024         spin_lock_irqsave(&dev->event_lock, flags);
5025         if (intel_crtc->unpin_work) {
5026                 intel_crtc->unpin_work->pending = 1;
5027         } else {
5028                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5029         }
5030         spin_unlock_irqrestore(&dev->event_lock, flags);
5031 }
5032
5033 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5034                                 struct drm_framebuffer *fb,
5035                                 struct drm_pending_vblank_event *event)
5036 {
5037         struct drm_device *dev = crtc->dev;
5038         struct drm_i915_private *dev_priv = dev->dev_private;
5039         struct intel_framebuffer *intel_fb;
5040         struct drm_i915_gem_object *obj_priv;
5041         struct drm_gem_object *obj;
5042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5043         struct intel_unpin_work *work;
5044         unsigned long flags, offset;
5045         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5046         int ret, pipesrc;
5047         u32 flip_mask;
5048
5049         work = kzalloc(sizeof *work, GFP_KERNEL);
5050         if (work == NULL)
5051                 return -ENOMEM;
5052
5053         work->event = event;
5054         work->dev = crtc->dev;
5055         intel_fb = to_intel_framebuffer(crtc->fb);
5056         work->old_fb_obj = intel_fb->obj;
5057         INIT_WORK(&work->work, intel_unpin_work_fn);
5058
5059         /* We borrow the event spin lock for protecting unpin_work */
5060         spin_lock_irqsave(&dev->event_lock, flags);
5061         if (intel_crtc->unpin_work) {
5062                 spin_unlock_irqrestore(&dev->event_lock, flags);
5063                 kfree(work);
5064
5065                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5066                 return -EBUSY;
5067         }
5068         intel_crtc->unpin_work = work;
5069         spin_unlock_irqrestore(&dev->event_lock, flags);
5070
5071         intel_fb = to_intel_framebuffer(fb);
5072         obj = intel_fb->obj;
5073
5074         mutex_lock(&dev->struct_mutex);
5075         ret = intel_pin_and_fence_fb_obj(dev, obj);
5076         if (ret)
5077                 goto cleanup_work;
5078
5079         /* Reference the objects for the scheduled work. */
5080         drm_gem_object_reference(work->old_fb_obj);
5081         drm_gem_object_reference(obj);
5082
5083         crtc->fb = fb;
5084         ret = i915_gem_object_flush_write_domain(obj);
5085         if (ret)
5086                 goto cleanup_objs;
5087
5088         ret = drm_vblank_get(dev, intel_crtc->pipe);
5089         if (ret)
5090                 goto cleanup_objs;
5091
5092         obj_priv = to_intel_bo(obj);
5093         atomic_inc(&obj_priv->pending_flip);
5094         work->pending_flip_obj = obj;
5095
5096         if (intel_crtc->plane)
5097                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5098         else
5099                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5100
5101         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5102                 BEGIN_LP_RING(2);
5103                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5104                 OUT_RING(0);
5105                 ADVANCE_LP_RING();
5106         }
5107
5108         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5109         offset = obj_priv->gtt_offset;
5110         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5111
5112         BEGIN_LP_RING(4);
5113         if (IS_I965G(dev)) {
5114                 OUT_RING(MI_DISPLAY_FLIP |
5115                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5116                 OUT_RING(fb->pitch);
5117                 OUT_RING(offset | obj_priv->tiling_mode);
5118                 pipesrc = I915_READ(pipesrc_reg);
5119                 OUT_RING(pipesrc & 0x0fff0fff);
5120         } else if (IS_GEN3(dev)) {
5121                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5122                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5123                 OUT_RING(fb->pitch);
5124                 OUT_RING(offset);
5125                 OUT_RING(MI_NOOP);
5126         } else {
5127                 OUT_RING(MI_DISPLAY_FLIP |
5128                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5129                 OUT_RING(fb->pitch);
5130                 OUT_RING(offset);
5131                 OUT_RING(MI_NOOP);
5132         }
5133         ADVANCE_LP_RING();
5134
5135         mutex_unlock(&dev->struct_mutex);
5136
5137         trace_i915_flip_request(intel_crtc->plane, obj);
5138
5139         return 0;
5140
5141 cleanup_objs:
5142         drm_gem_object_unreference(work->old_fb_obj);
5143         drm_gem_object_unreference(obj);
5144 cleanup_work:
5145         mutex_unlock(&dev->struct_mutex);
5146
5147         spin_lock_irqsave(&dev->event_lock, flags);
5148         intel_crtc->unpin_work = NULL;
5149         spin_unlock_irqrestore(&dev->event_lock, flags);
5150
5151         kfree(work);
5152
5153         return ret;
5154 }
5155
5156 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5157         .dpms = intel_crtc_dpms,
5158         .mode_fixup = intel_crtc_mode_fixup,
5159         .mode_set = intel_crtc_mode_set,
5160         .mode_set_base = intel_pipe_set_base,
5161         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5162         .prepare = intel_crtc_prepare,
5163         .commit = intel_crtc_commit,
5164         .load_lut = intel_crtc_load_lut,
5165 };
5166
5167 static const struct drm_crtc_funcs intel_crtc_funcs = {
5168         .cursor_set = intel_crtc_cursor_set,
5169         .cursor_move = intel_crtc_cursor_move,
5170         .gamma_set = intel_crtc_gamma_set,
5171         .set_config = drm_crtc_helper_set_config,
5172         .destroy = intel_crtc_destroy,
5173         .page_flip = intel_crtc_page_flip,
5174 };
5175
5176
5177 static void intel_crtc_init(struct drm_device *dev, int pipe)
5178 {
5179         drm_i915_private_t *dev_priv = dev->dev_private;
5180         struct intel_crtc *intel_crtc;
5181         int i;
5182
5183         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5184         if (intel_crtc == NULL)
5185                 return;
5186
5187         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5188
5189         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5190         intel_crtc->pipe = pipe;
5191         intel_crtc->plane = pipe;
5192         for (i = 0; i < 256; i++) {
5193                 intel_crtc->lut_r[i] = i;
5194                 intel_crtc->lut_g[i] = i;
5195                 intel_crtc->lut_b[i] = i;
5196         }
5197
5198         /* Swap pipes & planes for FBC on pre-965 */
5199         intel_crtc->pipe = pipe;
5200         intel_crtc->plane = pipe;
5201         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5202                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5203                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5204         }
5205
5206         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5207                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5208         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5209         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5210
5211         intel_crtc->cursor_addr = 0;
5212         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5213         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5214
5215         intel_crtc->busy = false;
5216
5217         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5218                     (unsigned long)intel_crtc);
5219 }
5220
5221 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5222                                 struct drm_file *file_priv)
5223 {
5224         drm_i915_private_t *dev_priv = dev->dev_private;
5225         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5226         struct drm_mode_object *drmmode_obj;
5227         struct intel_crtc *crtc;
5228
5229         if (!dev_priv) {
5230                 DRM_ERROR("called with no initialization\n");
5231                 return -EINVAL;
5232         }
5233
5234         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5235                         DRM_MODE_OBJECT_CRTC);
5236
5237         if (!drmmode_obj) {
5238                 DRM_ERROR("no such CRTC id\n");
5239                 return -EINVAL;
5240         }
5241
5242         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5243         pipe_from_crtc_id->pipe = crtc->pipe;
5244
5245         return 0;
5246 }
5247
5248 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5249 {
5250         struct drm_crtc *crtc = NULL;
5251
5252         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5253                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254                 if (intel_crtc->pipe == pipe)
5255                         break;
5256         }
5257         return crtc;
5258 }
5259
5260 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5261 {
5262         int index_mask = 0;
5263         struct drm_encoder *encoder;
5264         int entry = 0;
5265
5266         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5267                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5268                 if (type_mask & intel_encoder->clone_mask)
5269                         index_mask |= (1 << entry);
5270                 entry++;
5271         }
5272         return index_mask;
5273 }
5274
5275
5276 static void intel_setup_outputs(struct drm_device *dev)
5277 {
5278         struct drm_i915_private *dev_priv = dev->dev_private;
5279         struct drm_encoder *encoder;
5280         bool dpd_is_edp = false;
5281
5282         if (IS_MOBILE(dev) && !IS_I830(dev))
5283                 intel_lvds_init(dev);
5284
5285         if (HAS_PCH_SPLIT(dev)) {
5286                 dpd_is_edp = intel_dpd_is_edp(dev);
5287
5288                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5289                         intel_dp_init(dev, DP_A);
5290
5291                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5292                         intel_dp_init(dev, PCH_DP_D);
5293         }
5294
5295         intel_crt_init(dev);
5296
5297         if (HAS_PCH_SPLIT(dev)) {
5298                 int found;
5299
5300                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5301                         /* PCH SDVOB multiplex with HDMIB */
5302                         found = intel_sdvo_init(dev, PCH_SDVOB);
5303                         if (!found)
5304                                 intel_hdmi_init(dev, HDMIB);
5305                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5306                                 intel_dp_init(dev, PCH_DP_B);
5307                 }
5308
5309                 if (I915_READ(HDMIC) & PORT_DETECTED)
5310                         intel_hdmi_init(dev, HDMIC);
5311
5312                 if (I915_READ(HDMID) & PORT_DETECTED)
5313                         intel_hdmi_init(dev, HDMID);
5314
5315                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5316                         intel_dp_init(dev, PCH_DP_C);
5317
5318                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5319                         intel_dp_init(dev, PCH_DP_D);
5320
5321         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5322                 bool found = false;
5323
5324                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5325                         DRM_DEBUG_KMS("probing SDVOB\n");
5326                         found = intel_sdvo_init(dev, SDVOB);
5327                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5328                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5329                                 intel_hdmi_init(dev, SDVOB);
5330                         }
5331
5332                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5333                                 DRM_DEBUG_KMS("probing DP_B\n");
5334                                 intel_dp_init(dev, DP_B);
5335                         }
5336                 }
5337
5338                 /* Before G4X SDVOC doesn't have its own detect register */
5339
5340                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5341                         DRM_DEBUG_KMS("probing SDVOC\n");
5342                         found = intel_sdvo_init(dev, SDVOC);
5343                 }
5344
5345                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5346
5347                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5348                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5349                                 intel_hdmi_init(dev, SDVOC);
5350                         }
5351                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5352                                 DRM_DEBUG_KMS("probing DP_C\n");
5353                                 intel_dp_init(dev, DP_C);
5354                         }
5355                 }
5356
5357                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5358                     (I915_READ(DP_D) & DP_DETECTED)) {
5359                         DRM_DEBUG_KMS("probing DP_D\n");
5360                         intel_dp_init(dev, DP_D);
5361                 }
5362         } else if (IS_GEN2(dev))
5363                 intel_dvo_init(dev);
5364
5365         if (SUPPORTS_TV(dev))
5366                 intel_tv_init(dev);
5367
5368         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5369                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5370
5371                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5372                 encoder->possible_clones = intel_encoder_clones(dev,
5373                                                 intel_encoder->clone_mask);
5374         }
5375 }
5376
5377 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5378 {
5379         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5380
5381         drm_framebuffer_cleanup(fb);
5382         drm_gem_object_unreference_unlocked(intel_fb->obj);
5383
5384         kfree(intel_fb);
5385 }
5386
5387 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5388                                                 struct drm_file *file_priv,
5389                                                 unsigned int *handle)
5390 {
5391         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5392         struct drm_gem_object *object = intel_fb->obj;
5393
5394         return drm_gem_handle_create(file_priv, object, handle);
5395 }
5396
5397 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5398         .destroy = intel_user_framebuffer_destroy,
5399         .create_handle = intel_user_framebuffer_create_handle,
5400 };
5401
5402 int intel_framebuffer_init(struct drm_device *dev,
5403                            struct intel_framebuffer *intel_fb,
5404                            struct drm_mode_fb_cmd *mode_cmd,
5405                            struct drm_gem_object *obj)
5406 {
5407         int ret;
5408
5409         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5410         if (ret) {
5411                 DRM_ERROR("framebuffer init failed %d\n", ret);
5412                 return ret;
5413         }
5414
5415         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5416         intel_fb->obj = obj;
5417         return 0;
5418 }
5419
5420 static struct drm_framebuffer *
5421 intel_user_framebuffer_create(struct drm_device *dev,
5422                               struct drm_file *filp,
5423                               struct drm_mode_fb_cmd *mode_cmd)
5424 {
5425         struct drm_gem_object *obj;
5426         struct intel_framebuffer *intel_fb;
5427         int ret;
5428
5429         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5430         if (!obj)
5431                 return ERR_PTR(-ENOENT);
5432
5433         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5434         if (!intel_fb)
5435                 return ERR_PTR(-ENOMEM);
5436
5437         ret = intel_framebuffer_init(dev, intel_fb,
5438                                      mode_cmd, obj);
5439         if (ret) {
5440                 drm_gem_object_unreference_unlocked(obj);
5441                 kfree(intel_fb);
5442                 return ERR_PTR(ret);
5443         }
5444
5445         return &intel_fb->base;
5446 }
5447
5448 static const struct drm_mode_config_funcs intel_mode_funcs = {
5449         .fb_create = intel_user_framebuffer_create,
5450         .output_poll_changed = intel_fb_output_poll_changed,
5451 };
5452
5453 static struct drm_gem_object *
5454 intel_alloc_context_page(struct drm_device *dev)
5455 {
5456         struct drm_gem_object *ctx;
5457         int ret;
5458
5459         ctx = i915_gem_alloc_object(dev, 4096);
5460         if (!ctx) {
5461                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5462                 return NULL;
5463         }
5464
5465         mutex_lock(&dev->struct_mutex);
5466         ret = i915_gem_object_pin(ctx, 4096);
5467         if (ret) {
5468                 DRM_ERROR("failed to pin power context: %d\n", ret);
5469                 goto err_unref;
5470         }
5471
5472         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5473         if (ret) {
5474                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5475                 goto err_unpin;
5476         }
5477         mutex_unlock(&dev->struct_mutex);
5478
5479         return ctx;
5480
5481 err_unpin:
5482         i915_gem_object_unpin(ctx);
5483 err_unref:
5484         drm_gem_object_unreference(ctx);
5485         mutex_unlock(&dev->struct_mutex);
5486         return NULL;
5487 }
5488
5489 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5490 {
5491         struct drm_i915_private *dev_priv = dev->dev_private;
5492         u16 rgvswctl;
5493
5494         rgvswctl = I915_READ16(MEMSWCTL);
5495         if (rgvswctl & MEMCTL_CMD_STS) {
5496                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5497                 return false; /* still busy with another command */
5498         }
5499
5500         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5501                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5502         I915_WRITE16(MEMSWCTL, rgvswctl);
5503         POSTING_READ16(MEMSWCTL);
5504
5505         rgvswctl |= MEMCTL_CMD_STS;
5506         I915_WRITE16(MEMSWCTL, rgvswctl);
5507
5508         return true;
5509 }
5510
5511 void ironlake_enable_drps(struct drm_device *dev)
5512 {
5513         struct drm_i915_private *dev_priv = dev->dev_private;
5514         u32 rgvmodectl = I915_READ(MEMMODECTL);
5515         u8 fmax, fmin, fstart, vstart;
5516
5517         /* 100ms RC evaluation intervals */
5518         I915_WRITE(RCUPEI, 100000);
5519         I915_WRITE(RCDNEI, 100000);
5520
5521         /* Set max/min thresholds to 90ms and 80ms respectively */
5522         I915_WRITE(RCBMAXAVG, 90000);
5523         I915_WRITE(RCBMINAVG, 80000);
5524
5525         I915_WRITE(MEMIHYST, 1);
5526
5527         /* Set up min, max, and cur for interrupt handling */
5528         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5529         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5530         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5531                 MEMMODE_FSTART_SHIFT;
5532         fstart = fmax;
5533
5534         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5535                 PXVFREQ_PX_SHIFT;
5536
5537         dev_priv->fmax = fstart; /* IPS callback will increase this */
5538         dev_priv->fstart = fstart;
5539
5540         dev_priv->max_delay = fmax;
5541         dev_priv->min_delay = fmin;
5542         dev_priv->cur_delay = fstart;
5543
5544         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5545                          fstart);
5546
5547         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5548
5549         /*
5550          * Interrupts will be enabled in ironlake_irq_postinstall
5551          */
5552
5553         I915_WRITE(VIDSTART, vstart);
5554         POSTING_READ(VIDSTART);
5555
5556         rgvmodectl |= MEMMODE_SWMODE_EN;
5557         I915_WRITE(MEMMODECTL, rgvmodectl);
5558
5559         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5560                 DRM_ERROR("stuck trying to change perf mode\n");
5561         msleep(1);
5562
5563         ironlake_set_drps(dev, fstart);
5564
5565         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5566                 I915_READ(0x112e0);
5567         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5568         dev_priv->last_count2 = I915_READ(0x112f4);
5569         getrawmonotonic(&dev_priv->last_time2);
5570 }
5571
5572 void ironlake_disable_drps(struct drm_device *dev)
5573 {
5574         struct drm_i915_private *dev_priv = dev->dev_private;
5575         u16 rgvswctl = I915_READ16(MEMSWCTL);
5576
5577         /* Ack interrupts, disable EFC interrupt */
5578         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5579         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5580         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5581         I915_WRITE(DEIIR, DE_PCU_EVENT);
5582         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5583
5584         /* Go back to the starting frequency */
5585         ironlake_set_drps(dev, dev_priv->fstart);
5586         msleep(1);
5587         rgvswctl |= MEMCTL_CMD_STS;
5588         I915_WRITE(MEMSWCTL, rgvswctl);
5589         msleep(1);
5590
5591 }
5592
5593 static unsigned long intel_pxfreq(u32 vidfreq)
5594 {
5595         unsigned long freq;
5596         int div = (vidfreq & 0x3f0000) >> 16;
5597         int post = (vidfreq & 0x3000) >> 12;
5598         int pre = (vidfreq & 0x7);
5599
5600         if (!pre)
5601                 return 0;
5602
5603         freq = ((div * 133333) / ((1<<post) * pre));
5604
5605         return freq;
5606 }
5607
5608 void intel_init_emon(struct drm_device *dev)
5609 {
5610         struct drm_i915_private *dev_priv = dev->dev_private;
5611         u32 lcfuse;
5612         u8 pxw[16];
5613         int i;
5614
5615         /* Disable to program */
5616         I915_WRITE(ECR, 0);
5617         POSTING_READ(ECR);
5618
5619         /* Program energy weights for various events */
5620         I915_WRITE(SDEW, 0x15040d00);
5621         I915_WRITE(CSIEW0, 0x007f0000);
5622         I915_WRITE(CSIEW1, 0x1e220004);
5623         I915_WRITE(CSIEW2, 0x04000004);
5624
5625         for (i = 0; i < 5; i++)
5626                 I915_WRITE(PEW + (i * 4), 0);
5627         for (i = 0; i < 3; i++)
5628                 I915_WRITE(DEW + (i * 4), 0);
5629
5630         /* Program P-state weights to account for frequency power adjustment */
5631         for (i = 0; i < 16; i++) {
5632                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5633                 unsigned long freq = intel_pxfreq(pxvidfreq);
5634                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5635                         PXVFREQ_PX_SHIFT;
5636                 unsigned long val;
5637
5638                 val = vid * vid;
5639                 val *= (freq / 1000);
5640                 val *= 255;
5641                 val /= (127*127*900);
5642                 if (val > 0xff)
5643                         DRM_ERROR("bad pxval: %ld\n", val);
5644                 pxw[i] = val;
5645         }
5646         /* Render standby states get 0 weight */
5647         pxw[14] = 0;
5648         pxw[15] = 0;
5649
5650         for (i = 0; i < 4; i++) {
5651                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5652                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5653                 I915_WRITE(PXW + (i * 4), val);
5654         }
5655
5656         /* Adjust magic regs to magic values (more experimental results) */
5657         I915_WRITE(OGW0, 0);
5658         I915_WRITE(OGW1, 0);
5659         I915_WRITE(EG0, 0x00007f00);
5660         I915_WRITE(EG1, 0x0000000e);
5661         I915_WRITE(EG2, 0x000e0000);
5662         I915_WRITE(EG3, 0x68000300);
5663         I915_WRITE(EG4, 0x42000000);
5664         I915_WRITE(EG5, 0x00140031);
5665         I915_WRITE(EG6, 0);
5666         I915_WRITE(EG7, 0);
5667
5668         for (i = 0; i < 8; i++)
5669                 I915_WRITE(PXWL + (i * 4), 0);
5670
5671         /* Enable PMON + select events */
5672         I915_WRITE(ECR, 0x80000019);
5673
5674         lcfuse = I915_READ(LCFUSE02);
5675
5676         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5677 }
5678
5679 void intel_init_clock_gating(struct drm_device *dev)
5680 {
5681         struct drm_i915_private *dev_priv = dev->dev_private;
5682
5683         /*
5684          * Disable clock gating reported to work incorrectly according to the
5685          * specs, but enable as much else as we can.
5686          */
5687         if (HAS_PCH_SPLIT(dev)) {
5688                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5689
5690                 if (IS_IRONLAKE(dev)) {
5691                         /* Required for FBC */
5692                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5693                         /* Required for CxSR */
5694                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5695
5696                         I915_WRITE(PCH_3DCGDIS0,
5697                                    MARIUNIT_CLOCK_GATE_DISABLE |
5698                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5699                 }
5700
5701                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5702
5703                 /*
5704                  * According to the spec the following bits should be set in
5705                  * order to enable memory self-refresh
5706                  * The bit 22/21 of 0x42004
5707                  * The bit 5 of 0x42020
5708                  * The bit 15 of 0x45000
5709                  */
5710                 if (IS_IRONLAKE(dev)) {
5711                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5712                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5713                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5714                         I915_WRITE(ILK_DSPCLK_GATE,
5715                                         (I915_READ(ILK_DSPCLK_GATE) |
5716                                                 ILK_DPARB_CLK_GATE));
5717                         I915_WRITE(DISP_ARB_CTL,
5718                                         (I915_READ(DISP_ARB_CTL) |
5719                                                 DISP_FBC_WM_DIS));
5720                 }
5721                 /*
5722                  * Based on the document from hardware guys the following bits
5723                  * should be set unconditionally in order to enable FBC.
5724                  * The bit 22 of 0x42000
5725                  * The bit 22 of 0x42004
5726                  * The bit 7,8,9 of 0x42020.
5727                  */
5728                 if (IS_IRONLAKE_M(dev)) {
5729                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5730                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5731                                    ILK_FBCQ_DIS);
5732                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5733                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5734                                    ILK_DPARB_GATE);
5735                         I915_WRITE(ILK_DSPCLK_GATE,
5736                                    I915_READ(ILK_DSPCLK_GATE) |
5737                                    ILK_DPFC_DIS1 |
5738                                    ILK_DPFC_DIS2 |
5739                                    ILK_CLK_FBC);
5740                 }
5741                 if (IS_GEN6(dev))
5742                         return;
5743         } else if (IS_G4X(dev)) {
5744                 uint32_t dspclk_gate;
5745                 I915_WRITE(RENCLK_GATE_D1, 0);
5746                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5747                        GS_UNIT_CLOCK_GATE_DISABLE |
5748                        CL_UNIT_CLOCK_GATE_DISABLE);
5749                 I915_WRITE(RAMCLK_GATE_D, 0);
5750                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5751                         OVRUNIT_CLOCK_GATE_DISABLE |
5752                         OVCUNIT_CLOCK_GATE_DISABLE;
5753                 if (IS_GM45(dev))
5754                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5755                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5756         } else if (IS_I965GM(dev)) {
5757                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5758                 I915_WRITE(RENCLK_GATE_D2, 0);
5759                 I915_WRITE(DSPCLK_GATE_D, 0);
5760                 I915_WRITE(RAMCLK_GATE_D, 0);
5761                 I915_WRITE16(DEUC, 0);
5762         } else if (IS_I965G(dev)) {
5763                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5764                        I965_RCC_CLOCK_GATE_DISABLE |
5765                        I965_RCPB_CLOCK_GATE_DISABLE |
5766                        I965_ISC_CLOCK_GATE_DISABLE |
5767                        I965_FBC_CLOCK_GATE_DISABLE);
5768                 I915_WRITE(RENCLK_GATE_D2, 0);
5769         } else if (IS_I9XX(dev)) {
5770                 u32 dstate = I915_READ(D_STATE);
5771
5772                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5773                         DSTATE_DOT_CLOCK_GATING;
5774                 I915_WRITE(D_STATE, dstate);
5775         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5776                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5777         } else if (IS_I830(dev)) {
5778                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5779         }
5780
5781         /*
5782          * GPU can automatically power down the render unit if given a page
5783          * to save state.
5784          */
5785         if (IS_IRONLAKE_M(dev)) {
5786                 if (dev_priv->renderctx == NULL)
5787                         dev_priv->renderctx = intel_alloc_context_page(dev);
5788                 if (dev_priv->renderctx) {
5789                         struct drm_i915_gem_object *obj_priv;
5790                         obj_priv = to_intel_bo(dev_priv->renderctx);
5791                         if (obj_priv) {
5792                                 BEGIN_LP_RING(4);
5793                                 OUT_RING(MI_SET_CONTEXT);
5794                                 OUT_RING(obj_priv->gtt_offset |
5795                                                 MI_MM_SPACE_GTT |
5796                                                 MI_SAVE_EXT_STATE_EN |
5797                                                 MI_RESTORE_EXT_STATE_EN |
5798                                                 MI_RESTORE_INHIBIT);
5799                                 OUT_RING(MI_NOOP);
5800                                 OUT_RING(MI_FLUSH);
5801                                 ADVANCE_LP_RING();
5802                         }
5803                 } else {
5804                         DRM_DEBUG_KMS("Failed to allocate render context."
5805                                       "Disable RC6\n");
5806                         return;
5807                 }
5808         }
5809
5810         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5811                 struct drm_i915_gem_object *obj_priv = NULL;
5812
5813                 if (dev_priv->pwrctx) {
5814                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5815                 } else {
5816                         struct drm_gem_object *pwrctx;
5817
5818                         pwrctx = intel_alloc_context_page(dev);
5819                         if (pwrctx) {
5820                                 dev_priv->pwrctx = pwrctx;
5821                                 obj_priv = to_intel_bo(pwrctx);
5822                         }
5823                 }
5824
5825                 if (obj_priv) {
5826                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5827                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5828                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5829                 }
5830         }
5831 }
5832
5833 /* Set up chip specific display functions */
5834 static void intel_init_display(struct drm_device *dev)
5835 {
5836         struct drm_i915_private *dev_priv = dev->dev_private;
5837
5838         /* We always want a DPMS function */
5839         if (HAS_PCH_SPLIT(dev))
5840                 dev_priv->display.dpms = ironlake_crtc_dpms;
5841         else
5842                 dev_priv->display.dpms = i9xx_crtc_dpms;
5843
5844         if (I915_HAS_FBC(dev)) {
5845                 if (IS_IRONLAKE_M(dev)) {
5846                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5847                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5848                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5849                 } else if (IS_GM45(dev)) {
5850                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5851                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5852                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5853                 } else if (IS_I965GM(dev)) {
5854                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5855                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5856                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5857                 }
5858                 /* 855GM needs testing */
5859         }
5860
5861         /* Returns the core display clock speed */
5862         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5863                 dev_priv->display.get_display_clock_speed =
5864                         i945_get_display_clock_speed;
5865         else if (IS_I915G(dev))
5866                 dev_priv->display.get_display_clock_speed =
5867                         i915_get_display_clock_speed;
5868         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5869                 dev_priv->display.get_display_clock_speed =
5870                         i9xx_misc_get_display_clock_speed;
5871         else if (IS_I915GM(dev))
5872                 dev_priv->display.get_display_clock_speed =
5873                         i915gm_get_display_clock_speed;
5874         else if (IS_I865G(dev))
5875                 dev_priv->display.get_display_clock_speed =
5876                         i865_get_display_clock_speed;
5877         else if (IS_I85X(dev))
5878                 dev_priv->display.get_display_clock_speed =
5879                         i855_get_display_clock_speed;
5880         else /* 852, 830 */
5881                 dev_priv->display.get_display_clock_speed =
5882                         i830_get_display_clock_speed;
5883
5884         /* For FIFO watermark updates */
5885         if (HAS_PCH_SPLIT(dev)) {
5886                 if (IS_IRONLAKE(dev)) {
5887                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5888                                 dev_priv->display.update_wm = ironlake_update_wm;
5889                         else {
5890                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5891                                               "Disable CxSR\n");
5892                                 dev_priv->display.update_wm = NULL;
5893                         }
5894                 } else
5895                         dev_priv->display.update_wm = NULL;
5896         } else if (IS_PINEVIEW(dev)) {
5897                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5898                                             dev_priv->is_ddr3,
5899                                             dev_priv->fsb_freq,
5900                                             dev_priv->mem_freq)) {
5901                         DRM_INFO("failed to find known CxSR latency "
5902                                  "(found ddr%s fsb freq %d, mem freq %d), "
5903                                  "disabling CxSR\n",
5904                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5905                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5906                         /* Disable CxSR and never update its watermark again */
5907                         pineview_disable_cxsr(dev);
5908                         dev_priv->display.update_wm = NULL;
5909                 } else
5910                         dev_priv->display.update_wm = pineview_update_wm;
5911         } else if (IS_G4X(dev))
5912                 dev_priv->display.update_wm = g4x_update_wm;
5913         else if (IS_I965G(dev))
5914                 dev_priv->display.update_wm = i965_update_wm;
5915         else if (IS_I9XX(dev)) {
5916                 dev_priv->display.update_wm = i9xx_update_wm;
5917                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5918         } else if (IS_I85X(dev)) {
5919                 dev_priv->display.update_wm = i9xx_update_wm;
5920                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5921         } else {
5922                 dev_priv->display.update_wm = i830_update_wm;
5923                 if (IS_845G(dev))
5924                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5925                 else
5926                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5927         }
5928 }
5929
5930 /*
5931  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5932  * resume, or other times.  This quirk makes sure that's the case for
5933  * affected systems.
5934  */
5935 static void quirk_pipea_force (struct drm_device *dev)
5936 {
5937         struct drm_i915_private *dev_priv = dev->dev_private;
5938
5939         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5940         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5941 }
5942
5943 struct intel_quirk {
5944         int device;
5945         int subsystem_vendor;
5946         int subsystem_device;
5947         void (*hook)(struct drm_device *dev);
5948 };
5949
5950 struct intel_quirk intel_quirks[] = {
5951         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5952         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5953         /* HP Mini needs pipe A force quirk (LP: #322104) */
5954         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5955
5956         /* Thinkpad R31 needs pipe A force quirk */
5957         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5958         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5959         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5960
5961         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5962         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5963         /* ThinkPad X40 needs pipe A force quirk */
5964
5965         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5966         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5967
5968         /* 855 & before need to leave pipe A & dpll A up */
5969         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5970         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5971 };
5972
5973 static void intel_init_quirks(struct drm_device *dev)
5974 {
5975         struct pci_dev *d = dev->pdev;
5976         int i;
5977
5978         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5979                 struct intel_quirk *q = &intel_quirks[i];
5980
5981                 if (d->device == q->device &&
5982                     (d->subsystem_vendor == q->subsystem_vendor ||
5983                      q->subsystem_vendor == PCI_ANY_ID) &&
5984                     (d->subsystem_device == q->subsystem_device ||
5985                      q->subsystem_device == PCI_ANY_ID))
5986                         q->hook(dev);
5987         }
5988 }
5989
5990 /* Disable the VGA plane that we never use */
5991 static void i915_disable_vga(struct drm_device *dev)
5992 {
5993         struct drm_i915_private *dev_priv = dev->dev_private;
5994         u8 sr1;
5995         u32 vga_reg;
5996
5997         if (HAS_PCH_SPLIT(dev))
5998                 vga_reg = CPU_VGACNTRL;
5999         else
6000                 vga_reg = VGACNTRL;
6001
6002         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6003         outb(1, VGA_SR_INDEX);
6004         sr1 = inb(VGA_SR_DATA);
6005         outb(sr1 | 1<<5, VGA_SR_DATA);
6006         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6007         udelay(300);
6008
6009         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6010         POSTING_READ(vga_reg);
6011 }
6012
6013 void intel_modeset_init(struct drm_device *dev)
6014 {
6015         struct drm_i915_private *dev_priv = dev->dev_private;
6016         int i;
6017
6018         drm_mode_config_init(dev);
6019
6020         dev->mode_config.min_width = 0;
6021         dev->mode_config.min_height = 0;
6022
6023         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6024
6025         intel_init_quirks(dev);
6026
6027         intel_init_display(dev);
6028
6029         if (IS_I965G(dev)) {
6030                 dev->mode_config.max_width = 8192;
6031                 dev->mode_config.max_height = 8192;
6032         } else if (IS_I9XX(dev)) {
6033                 dev->mode_config.max_width = 4096;
6034                 dev->mode_config.max_height = 4096;
6035         } else {
6036                 dev->mode_config.max_width = 2048;
6037                 dev->mode_config.max_height = 2048;
6038         }
6039
6040         /* set memory base */
6041         if (IS_I9XX(dev))
6042                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6043         else
6044                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6045
6046         if (IS_MOBILE(dev) || IS_I9XX(dev))
6047                 dev_priv->num_pipe = 2;
6048         else
6049                 dev_priv->num_pipe = 1;
6050         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6051                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6052
6053         for (i = 0; i < dev_priv->num_pipe; i++) {
6054                 intel_crtc_init(dev, i);
6055         }
6056
6057         intel_setup_outputs(dev);
6058
6059         intel_init_clock_gating(dev);
6060
6061         /* Just disable it once at startup */
6062         i915_disable_vga(dev);
6063
6064         if (IS_IRONLAKE_M(dev)) {
6065                 ironlake_enable_drps(dev);
6066                 intel_init_emon(dev);
6067         }
6068
6069         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6070         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6071                     (unsigned long)dev);
6072
6073         intel_setup_overlay(dev);
6074 }
6075
6076 void intel_modeset_cleanup(struct drm_device *dev)
6077 {
6078         struct drm_i915_private *dev_priv = dev->dev_private;
6079         struct drm_crtc *crtc;
6080         struct intel_crtc *intel_crtc;
6081
6082         mutex_lock(&dev->struct_mutex);
6083
6084         drm_kms_helper_poll_fini(dev);
6085         intel_fbdev_fini(dev);
6086
6087         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6088                 /* Skip inactive CRTCs */
6089                 if (!crtc->fb)
6090                         continue;
6091
6092                 intel_crtc = to_intel_crtc(crtc);
6093                 intel_increase_pllclock(crtc, false);
6094                 del_timer_sync(&intel_crtc->idle_timer);
6095         }
6096
6097         del_timer_sync(&dev_priv->idle_timer);
6098
6099         if (dev_priv->display.disable_fbc)
6100                 dev_priv->display.disable_fbc(dev);
6101
6102         if (dev_priv->renderctx) {
6103                 struct drm_i915_gem_object *obj_priv;
6104
6105                 obj_priv = to_intel_bo(dev_priv->renderctx);
6106                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6107                 I915_READ(CCID);
6108                 i915_gem_object_unpin(dev_priv->renderctx);
6109                 drm_gem_object_unreference(dev_priv->renderctx);
6110         }
6111
6112         if (dev_priv->pwrctx) {
6113                 struct drm_i915_gem_object *obj_priv;
6114
6115                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6116                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6117                 I915_READ(PWRCTXA);
6118                 i915_gem_object_unpin(dev_priv->pwrctx);
6119                 drm_gem_object_unreference(dev_priv->pwrctx);
6120         }
6121
6122         if (IS_IRONLAKE_M(dev))
6123                 ironlake_disable_drps(dev);
6124
6125         mutex_unlock(&dev->struct_mutex);
6126
6127         drm_mode_config_cleanup(dev);
6128 }
6129
6130
6131 /*
6132  * Return which encoder is currently attached for connector.
6133  */
6134 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6135 {
6136         struct drm_mode_object *obj;
6137         struct drm_encoder *encoder;
6138         int i;
6139
6140         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6141                 if (connector->encoder_ids[i] == 0)
6142                         break;
6143
6144                 obj = drm_mode_object_find(connector->dev,
6145                                            connector->encoder_ids[i],
6146                                            DRM_MODE_OBJECT_ENCODER);
6147                 if (!obj)
6148                         continue;
6149
6150                 encoder = obj_to_encoder(obj);
6151                 return encoder;
6152         }
6153         return NULL;
6154 }
6155
6156 /*
6157  * set vga decode state - true == enable VGA decode
6158  */
6159 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6160 {
6161         struct drm_i915_private *dev_priv = dev->dev_private;
6162         u16 gmch_ctrl;
6163
6164         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6165         if (state)
6166                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6167         else
6168                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6169         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6170         return 0;
6171 }