drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "drm_dp_helper.h"
  38
  39 #include "drm_crtc_helper.h"
  40
  41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  42
  43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  44 static void intel_update_watermarks(struct drm_device *dev);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  47
  48 typedef struct {
  49     /* given values */
  50     int n;
  51     int m1, m2;
  52     int p1, p2;
  53     /* derived values */
  54     int dot;
  55     int vco;
  56     int m;
  57     int p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61     int min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65     int dot_limit;
  66     int p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73     intel_p2_t      p2;
  74     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                       int, int, intel_clock_t *);
  76 };
  77
  78 #define I8XX_DOT_MIN              25000
  79 #define I8XX_DOT_MAX             350000
  80 #define I8XX_VCO_MIN             930000
  81 #define I8XX_VCO_MAX            1400000
  82 #define I8XX_N_MIN                    3
  83 #define I8XX_N_MAX                   16
  84 #define I8XX_M_MIN                   96
  85 #define I8XX_M_MAX                  140
  86 #define I8XX_M1_MIN                  18
  87 #define I8XX_M1_MAX                  26
  88 #define I8XX_M2_MIN                   6
  89 #define I8XX_M2_MAX                  16
  90 #define I8XX_P_MIN                    4
  91 #define I8XX_P_MAX                  128
  92 #define I8XX_P1_MIN                   2
  93 #define I8XX_P1_MAX                  33
  94 #define I8XX_P1_LVDS_MIN              1
  95 #define I8XX_P1_LVDS_MAX              6
  96 #define I8XX_P2_SLOW                  4
  97 #define I8XX_P2_FAST                  2
  98 #define I8XX_P2_LVDS_SLOW             14
  99 #define I8XX_P2_LVDS_FAST             7
 100 #define I8XX_P2_SLOW_LIMIT       165000
 101
 102 #define I9XX_DOT_MIN              20000
 103 #define I9XX_DOT_MAX             400000
 104 #define I9XX_VCO_MIN            1400000
 105 #define I9XX_VCO_MAX            2800000
 106 #define PINEVIEW_VCO_MIN                1700000
 107 #define PINEVIEW_VCO_MAX                3500000
 108 #define I9XX_N_MIN                    1
 109 #define I9XX_N_MAX                    6
 110 /* Pineview's Ncounter is a ring counter */
 111 #define PINEVIEW_N_MIN                3
 112 #define PINEVIEW_N_MAX                6
 113 #define I9XX_M_MIN                   70
 114 #define I9XX_M_MAX                  120
 115 #define PINEVIEW_M_MIN                2
 116 #define PINEVIEW_M_MAX              256
 117 #define I9XX_M1_MIN                  10
 118 #define I9XX_M1_MAX                  22
 119 #define I9XX_M2_MIN                   5
 120 #define I9XX_M2_MAX                   9
 121 /* Pineview M1 is reserved, and must be 0 */
 122 #define PINEVIEW_M1_MIN               0
 123 #define PINEVIEW_M1_MAX               0
 124 #define PINEVIEW_M2_MIN               0
 125 #define PINEVIEW_M2_MAX               254
 126 #define I9XX_P_SDVO_DAC_MIN           5
 127 #define I9XX_P_SDVO_DAC_MAX          80
 128 #define I9XX_P_LVDS_MIN               7
 129 #define I9XX_P_LVDS_MAX              98
 130 #define PINEVIEW_P_LVDS_MIN                   7
 131 #define PINEVIEW_P_LVDS_MAX                  112
 132 #define I9XX_P1_MIN                   1
 133 #define I9XX_P1_MAX                   8
 134 #define I9XX_P2_SDVO_DAC_SLOW                10
 135 #define I9XX_P2_SDVO_DAC_FAST                 5
 136 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 137 #define I9XX_P2_LVDS_SLOW                    14
 138 #define I9XX_P2_LVDS_FAST                     7
 139 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 140
 141 /*The parameter is for SDVO on G4x platform*/
 142 #define G4X_DOT_SDVO_MIN           25000
 143 #define G4X_DOT_SDVO_MAX           270000
 144 #define G4X_VCO_MIN                1750000
 145 #define G4X_VCO_MAX                3500000
 146 #define G4X_N_SDVO_MIN             1
 147 #define G4X_N_SDVO_MAX             4
 148 #define G4X_M_SDVO_MIN             104
 149 #define G4X_M_SDVO_MAX             138
 150 #define G4X_M1_SDVO_MIN            17
 151 #define G4X_M1_SDVO_MAX            23
 152 #define G4X_M2_SDVO_MIN            5
 153 #define G4X_M2_SDVO_MAX            11
 154 #define G4X_P_SDVO_MIN             10
 155 #define G4X_P_SDVO_MAX             30
 156 #define G4X_P1_SDVO_MIN            1
 157 #define G4X_P1_SDVO_MAX            3
 158 #define G4X_P2_SDVO_SLOW           10
 159 #define G4X_P2_SDVO_FAST           10
 160 #define G4X_P2_SDVO_LIMIT          270000
 161
 162 /*The parameter is for HDMI_DAC on G4x platform*/
 163 #define G4X_DOT_HDMI_DAC_MIN           22000
 164 #define G4X_DOT_HDMI_DAC_MAX           400000
 165 #define G4X_N_HDMI_DAC_MIN             1
 166 #define G4X_N_HDMI_DAC_MAX             4
 167 #define G4X_M_HDMI_DAC_MIN             104
 168 #define G4X_M_HDMI_DAC_MAX             138
 169 #define G4X_M1_HDMI_DAC_MIN            16
 170 #define G4X_M1_HDMI_DAC_MAX            23
 171 #define G4X_M2_HDMI_DAC_MIN            5
 172 #define G4X_M2_HDMI_DAC_MAX            11
 173 #define G4X_P_HDMI_DAC_MIN             5
 174 #define G4X_P_HDMI_DAC_MAX             80
 175 #define G4X_P1_HDMI_DAC_MIN            1
 176 #define G4X_P1_HDMI_DAC_MAX            8
 177 #define G4X_P2_HDMI_DAC_SLOW           10
 178 #define G4X_P2_HDMI_DAC_FAST           5
 179 #define G4X_P2_HDMI_DAC_LIMIT          165000
 180
 181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 199
 200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 218
 219 /*The parameter is for DISPLAY PORT on G4x platform*/
 220 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 221 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 222 #define G4X_N_DISPLAY_PORT_MIN             1
 223 #define G4X_N_DISPLAY_PORT_MAX             2
 224 #define G4X_M_DISPLAY_PORT_MIN             97
 225 #define G4X_M_DISPLAY_PORT_MAX             108
 226 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 227 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 228 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 229 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 230 #define G4X_P_DISPLAY_PORT_MIN             10
 231 #define G4X_P_DISPLAY_PORT_MAX             20
 232 #define G4X_P1_DISPLAY_PORT_MIN            1
 233 #define G4X_P1_DISPLAY_PORT_MAX            2
 234 #define G4X_P2_DISPLAY_PORT_SLOW           10
 235 #define G4X_P2_DISPLAY_PORT_FAST           10
 236 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 237
 238 /* Ironlake / Sandybridge */
 239 /* as we calculate clock using (register_value + 2) for
 240    N/M1/M2, so here the range value for them is (actual_value-2).
 241  */
 242 #define IRONLAKE_DOT_MIN         25000
 243 #define IRONLAKE_DOT_MAX         350000
 244 #define IRONLAKE_VCO_MIN         1760000
 245 #define IRONLAKE_VCO_MAX         3510000
 246 #define IRONLAKE_M1_MIN          12
 247 #define IRONLAKE_M1_MAX          22
 248 #define IRONLAKE_M2_MIN          5
 249 #define IRONLAKE_M2_MAX          9
 250 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 251
 252 /* We have parameter ranges for different type of outputs. */
 253
 254 /* DAC & HDMI Refclk 120Mhz */
 255 #define IRONLAKE_DAC_N_MIN      1
 256 #define IRONLAKE_DAC_N_MAX      5
 257 #define IRONLAKE_DAC_M_MIN      79
 258 #define IRONLAKE_DAC_M_MAX      127
 259 #define IRONLAKE_DAC_P_MIN      5
 260 #define IRONLAKE_DAC_P_MAX      80
 261 #define IRONLAKE_DAC_P1_MIN     1
 262 #define IRONLAKE_DAC_P1_MAX     8
 263 #define IRONLAKE_DAC_P2_SLOW    10
 264 #define IRONLAKE_DAC_P2_FAST    5
 265
 266 /* LVDS single-channel 120Mhz refclk */
 267 #define IRONLAKE_LVDS_S_N_MIN   1
 268 #define IRONLAKE_LVDS_S_N_MAX   3
 269 #define IRONLAKE_LVDS_S_M_MIN   79
 270 #define IRONLAKE_LVDS_S_M_MAX   118
 271 #define IRONLAKE_LVDS_S_P_MIN   28
 272 #define IRONLAKE_LVDS_S_P_MAX   112
 273 #define IRONLAKE_LVDS_S_P1_MIN  2
 274 #define IRONLAKE_LVDS_S_P1_MAX  8
 275 #define IRONLAKE_LVDS_S_P2_SLOW 14
 276 #define IRONLAKE_LVDS_S_P2_FAST 14
 277
 278 /* LVDS dual-channel 120Mhz refclk */
 279 #define IRONLAKE_LVDS_D_N_MIN   1
 280 #define IRONLAKE_LVDS_D_N_MAX   3
 281 #define IRONLAKE_LVDS_D_M_MIN   79
 282 #define IRONLAKE_LVDS_D_M_MAX   127
 283 #define IRONLAKE_LVDS_D_P_MIN   14
 284 #define IRONLAKE_LVDS_D_P_MAX   56
 285 #define IRONLAKE_LVDS_D_P1_MIN  2
 286 #define IRONLAKE_LVDS_D_P1_MAX  8
 287 #define IRONLAKE_LVDS_D_P2_SLOW 7
 288 #define IRONLAKE_LVDS_D_P2_FAST 7
 289
 290 /* LVDS single-channel 100Mhz refclk */
 291 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 292 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 293 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 294 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 295 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 296 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 297 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 298 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 299 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 300 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 301
 302 /* LVDS dual-channel 100Mhz refclk */
 303 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 304 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 305 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 306 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 307 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 308 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 309 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 310 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 311 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 312 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 313
 314 /* DisplayPort */
 315 #define IRONLAKE_DP_N_MIN               1
 316 #define IRONLAKE_DP_N_MAX               2
 317 #define IRONLAKE_DP_M_MIN               81
 318 #define IRONLAKE_DP_M_MAX               90
 319 #define IRONLAKE_DP_P_MIN               10
 320 #define IRONLAKE_DP_P_MAX               20
 321 #define IRONLAKE_DP_P2_FAST             10
 322 #define IRONLAKE_DP_P2_SLOW             10
 323 #define IRONLAKE_DP_P2_LIMIT            0
 324 #define IRONLAKE_DP_P1_MIN              1
 325 #define IRONLAKE_DP_P1_MAX              2
 326
 327 /* FDI */
 328 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 329
 330 static bool
 331 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 332                     int target, int refclk, intel_clock_t *best_clock);
 333 static bool
 334 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 335                         int target, int refclk, intel_clock_t *best_clock);
 336
 337 static bool
 338 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 339                       int target, int refclk, intel_clock_t *best_clock);
 340 static bool
 341 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 342                            int target, int refclk, intel_clock_t *best_clock);
 343
 344 static const intel_limit_t intel_limits_i8xx_dvo = {
 345         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 346         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 347         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 348         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 349         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 350         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 351         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 352         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 353         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 354                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 355         .find_pll = intel_find_best_PLL,
 356 };
 357
 358 static const intel_limit_t intel_limits_i8xx_lvds = {
 359         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 360         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 361         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 362         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 363         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 364         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 365         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 366         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 367         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 368                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 369         .find_pll = intel_find_best_PLL,
 370 };
 371
 372 static const intel_limit_t intel_limits_i9xx_sdvo = {
 373         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 374         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 375         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 376         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 377         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 378         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 379         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 380         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 381         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 382                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 383         .find_pll = intel_find_best_PLL,
 384 };
 385
 386 static const intel_limit_t intel_limits_i9xx_lvds = {
 387         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 388         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 389         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 390         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 391         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 392         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 393         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 394         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 395         /* The single-channel range is 25-112Mhz, and dual-channel
 396          * is 80-224Mhz.  Prefer single channel as much as possible.
 397          */
 398         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 399                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 400         .find_pll = intel_find_best_PLL,
 401 };
 402
 403     /* below parameter and function is for G4X Chipset Family*/
 404 static const intel_limit_t intel_limits_g4x_sdvo = {
 405         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 406         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 407         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 408         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 409         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 410         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 411         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 412         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 413         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 414                  .p2_slow = G4X_P2_SDVO_SLOW,
 415                  .p2_fast = G4X_P2_SDVO_FAST
 416         },
 417         .find_pll = intel_g4x_find_best_PLL,
 418 };
 419
 420 static const intel_limit_t intel_limits_g4x_hdmi = {
 421         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 422         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 423         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 424         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 425         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 426         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 427         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 428         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 429         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 430                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 431                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 432         },
 433         .find_pll = intel_g4x_find_best_PLL,
 434 };
 435
 436 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 437         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 439         .vco = { .min = G4X_VCO_MIN,
 440                  .max = G4X_VCO_MAX },
 441         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 443         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 445         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 447         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 448                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 449         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 451         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 453         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 454                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 455                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 456         },
 457         .find_pll = intel_g4x_find_best_PLL,
 458 };
 459
 460 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 461         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 463         .vco = { .min = G4X_VCO_MIN,
 464                  .max = G4X_VCO_MAX },
 465         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 467         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 469         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 471         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 472                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 473         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 475         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 477         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 478                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 479                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 480         },
 481         .find_pll = intel_g4x_find_best_PLL,
 482 };
 483
 484 static const intel_limit_t intel_limits_g4x_display_port = {
 485         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 486                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 487         .vco = { .min = G4X_VCO_MIN,
 488                  .max = G4X_VCO_MAX},
 489         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 490                  .max = G4X_N_DISPLAY_PORT_MAX },
 491         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 492                  .max = G4X_M_DISPLAY_PORT_MAX },
 493         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 494                  .max = G4X_M1_DISPLAY_PORT_MAX },
 495         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 496                  .max = G4X_M2_DISPLAY_PORT_MAX },
 497         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 498                  .max = G4X_P_DISPLAY_PORT_MAX },
 499         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 500                  .max = G4X_P1_DISPLAY_PORT_MAX},
 501         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 502                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 503                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 504         .find_pll = intel_find_pll_g4x_dp,
 505 };
 506
 507 static const intel_limit_t intel_limits_pineview_sdvo = {
 508         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 509         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 510         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 511         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 512         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 513         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 514         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 515         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 516         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 517                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 518         .find_pll = intel_find_best_PLL,
 519 };
 520
 521 static const intel_limit_t intel_limits_pineview_lvds = {
 522         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 523         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 524         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 525         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 526         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 527         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 528         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 529         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 530         /* Pineview only supports single-channel mode. */
 531         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 532                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 533         .find_pll = intel_find_best_PLL,
 534 };
 535
 536 static const intel_limit_t intel_limits_ironlake_dac = {
 537         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 538         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 539         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 540         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 541         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 542         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 543         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 544         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 545         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 546                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 547                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 548         .find_pll = intel_g4x_find_best_PLL,
 549 };
 550
 551 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 552         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 553         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 554         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 555         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 556         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 557         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 558         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 559         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 560         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 561                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 562                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 563         .find_pll = intel_g4x_find_best_PLL,
 564 };
 565
 566 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 567         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 568         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 569         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 570         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 571         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 572         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 573         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 574         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 575         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 576                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 577                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 578         .find_pll = intel_g4x_find_best_PLL,
 579 };
 580
 581 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 582         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 583         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 584         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 585         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 586         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 587         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 588         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 589         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 590         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 591                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 592                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 593         .find_pll = intel_g4x_find_best_PLL,
 594 };
 595
 596 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 597         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 598         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 599         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 600         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 601         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 602         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 603         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 604         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 605         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 606                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 607                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 608         .find_pll = intel_g4x_find_best_PLL,
 609 };
 610
 611 static const intel_limit_t intel_limits_ironlake_display_port = {
 612         .dot = { .min = IRONLAKE_DOT_MIN,
 613                  .max = IRONLAKE_DOT_MAX },
 614         .vco = { .min = IRONLAKE_VCO_MIN,
 615                  .max = IRONLAKE_VCO_MAX},
 616         .n   = { .min = IRONLAKE_DP_N_MIN,
 617                  .max = IRONLAKE_DP_N_MAX },
 618         .m   = { .min = IRONLAKE_DP_M_MIN,
 619                  .max = IRONLAKE_DP_M_MAX },
 620         .m1  = { .min = IRONLAKE_M1_MIN,
 621                  .max = IRONLAKE_M1_MAX },
 622         .m2  = { .min = IRONLAKE_M2_MIN,
 623                  .max = IRONLAKE_M2_MAX },
 624         .p   = { .min = IRONLAKE_DP_P_MIN,
 625                  .max = IRONLAKE_DP_P_MAX },
 626         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 627                  .max = IRONLAKE_DP_P1_MAX},
 628         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 629                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 630                  .p2_fast = IRONLAKE_DP_P2_FAST },
 631         .find_pll = intel_find_pll_ironlake_dp,
 632 };
 633
 634 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 635 {
 636         struct drm_device *dev = crtc->dev;
 637         struct drm_i915_private *dev_priv = dev->dev_private;
 638         const intel_limit_t *limit;
 639         int refclk = 120;
 640
 641         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 642                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 643                         refclk = 100;
 644
 645                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 646                     LVDS_CLKB_POWER_UP) {
 647                         /* LVDS dual channel */
 648                         if (refclk == 100)
 649                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 650                         else
 651                                 limit = &intel_limits_ironlake_dual_lvds;
 652                 } else {
 653                         if (refclk == 100)
 654                                 limit = &intel_limits_ironlake_single_lvds_100m;
 655                         else
 656                                 limit = &intel_limits_ironlake_single_lvds;
 657                 }
 658         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 659                         HAS_eDP)
 660                 limit = &intel_limits_ironlake_display_port;
 661         else
 662                 limit = &intel_limits_ironlake_dac;
 663
 664         return limit;
 665 }
 666
 667 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 668 {
 669         struct drm_device *dev = crtc->dev;
 670         struct drm_i915_private *dev_priv = dev->dev_private;
 671         const intel_limit_t *limit;
 672
 673         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 674                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 675                     LVDS_CLKB_POWER_UP)
 676                         /* LVDS with dual channel */
 677                         limit = &intel_limits_g4x_dual_channel_lvds;
 678                 else
 679                         /* LVDS with dual channel */
 680                         limit = &intel_limits_g4x_single_channel_lvds;
 681         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 682                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 683                 limit = &intel_limits_g4x_hdmi;
 684         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 685                 limit = &intel_limits_g4x_sdvo;
 686         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 687                 limit = &intel_limits_g4x_display_port;
 688         } else /* The option is for other outputs */
 689                 limit = &intel_limits_i9xx_sdvo;
 690
 691         return limit;
 692 }
 693
 694 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 695 {
 696         struct drm_device *dev = crtc->dev;
 697         const intel_limit_t *limit;
 698
 699         if (HAS_PCH_SPLIT(dev))
 700                 limit = intel_ironlake_limit(crtc);
 701         else if (IS_G4X(dev)) {
 702                 limit = intel_g4x_limit(crtc);
 703         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 705                         limit = &intel_limits_i9xx_lvds;
 706                 else
 707                         limit = &intel_limits_i9xx_sdvo;
 708         } else if (IS_PINEVIEW(dev)) {
 709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 710                         limit = &intel_limits_pineview_lvds;
 711                 else
 712                         limit = &intel_limits_pineview_sdvo;
 713         } else {
 714                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 715                         limit = &intel_limits_i8xx_lvds;
 716                 else
 717                         limit = &intel_limits_i8xx_dvo;
 718         }
 719         return limit;
 720 }
 721
 722 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 723 static void pineview_clock(int refclk, intel_clock_t *clock)
 724 {
 725         clock->m = clock->m2 + 2;
 726         clock->p = clock->p1 * clock->p2;
 727         clock->vco = refclk * clock->m / clock->n;
 728         clock->dot = clock->vco / clock->p;
 729 }
 730
 731 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 732 {
 733         if (IS_PINEVIEW(dev)) {
 734                 pineview_clock(refclk, clock);
 735                 return;
 736         }
 737         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 738         clock->p = clock->p1 * clock->p2;
 739         clock->vco = refclk * clock->m / (clock->n + 2);
 740         clock->dot = clock->vco / clock->p;
 741 }
 742
 743 /**
 744  * Returns whether any output on the specified pipe is of the specified type
 745  */
 746 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 747 {
 748     struct drm_device *dev = crtc->dev;
 749     struct drm_mode_config *mode_config = &dev->mode_config;
 750     struct drm_encoder *l_entry;
 751
 752     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 753             if (l_entry && l_entry->crtc == crtc) {
 754                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 755                     if (intel_encoder->type == type)
 756                             return true;
 757             }
 758     }
 759     return false;
 760 }
 761
 762 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 763 /**
 764  * Returns whether the given set of divisors are valid for a given refclk with
 765  * the given connectors.
 766  */
 767
 768 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 769 {
 770         const intel_limit_t *limit = intel_limit (crtc);
 771         struct drm_device *dev = crtc->dev;
 772
 773         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 774                 INTELPllInvalid ("p1 out of range\n");
 775         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 776                 INTELPllInvalid ("p out of range\n");
 777         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 778                 INTELPllInvalid ("m2 out of range\n");
 779         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 780                 INTELPllInvalid ("m1 out of range\n");
 781         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 782                 INTELPllInvalid ("m1 <= m2\n");
 783         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 784                 INTELPllInvalid ("m out of range\n");
 785         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 786                 INTELPllInvalid ("n out of range\n");
 787         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 788                 INTELPllInvalid ("vco out of range\n");
 789         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 790          * connector, etc., rather than just a single range.
 791          */
 792         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 793                 INTELPllInvalid ("dot out of range\n");
 794
 795         return true;
 796 }
 797
 798 static bool
 799 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 800                     int target, int refclk, intel_clock_t *best_clock)
 801
 802 {
 803         struct drm_device *dev = crtc->dev;
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         intel_clock_t clock;
 806         int err = target;
 807
 808         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 809             (I915_READ(LVDS)) != 0) {
 810                 /*
 811                  * For LVDS, if the panel is on, just rely on its current
 812                  * settings for dual-channel.  We haven't figured out how to
 813                  * reliably set up different single/dual channel state, if we
 814                  * even can.
 815                  */
 816                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 817                     LVDS_CLKB_POWER_UP)
 818                         clock.p2 = limit->p2.p2_fast;
 819                 else
 820                         clock.p2 = limit->p2.p2_slow;
 821         } else {
 822                 if (target < limit->p2.dot_limit)
 823                         clock.p2 = limit->p2.p2_slow;
 824                 else
 825                         clock.p2 = limit->p2.p2_fast;
 826         }
 827
 828         memset (best_clock, 0, sizeof (*best_clock));
 829
 830         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 831              clock.m1++) {
 832                 for (clock.m2 = limit->m2.min;
 833                      clock.m2 <= limit->m2.max; clock.m2++) {
 834                         /* m1 is always 0 in Pineview */
 835                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 836                                 break;
 837                         for (clock.n = limit->n.min;
 838                              clock.n <= limit->n.max; clock.n++) {
 839                                 for (clock.p1 = limit->p1.min;
 840                                         clock.p1 <= limit->p1.max; clock.p1++) {
 841                                         int this_err;
 842
 843                                         intel_clock(dev, refclk, &clock);
 844
 845                                         if (!intel_PLL_is_valid(crtc, &clock))
 846                                                 continue;
 847
 848                                         this_err = abs(clock.dot - target);
 849                                         if (this_err < err) {
 850                                                 *best_clock = clock;
 851                                                 err = this_err;
 852                                         }
 853                                 }
 854                         }
 855                 }
 856         }
 857
 858         return (err != target);
 859 }
 860
 861 static bool
 862 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *best_clock)
 864 {
 865         struct drm_device *dev = crtc->dev;
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         intel_clock_t clock;
 868         int max_n;
 869         bool found;
 870         /* approximately equals target * 0.00585 */
 871         int err_most = (target >> 8) + (target >> 9);
 872         found = false;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 875                 int lvds_reg;
 876
 877                 if (HAS_PCH_SPLIT(dev))
 878                         lvds_reg = PCH_LVDS;
 879                 else
 880                         lvds_reg = LVDS;
 881                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 882                     LVDS_CLKB_POWER_UP)
 883                         clock.p2 = limit->p2.p2_fast;
 884                 else
 885                         clock.p2 = limit->p2.p2_slow;
 886         } else {
 887                 if (target < limit->p2.dot_limit)
 888                         clock.p2 = limit->p2.p2_slow;
 889                 else
 890                         clock.p2 = limit->p2.p2_fast;
 891         }
 892
 893         memset(best_clock, 0, sizeof(*best_clock));
 894         max_n = limit->n.max;
 895         /* based on hardware requirement, prefer smaller n to precision */
 896         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                 /* based on hardware requirement, prefere larger m1,m2 */
 898                 for (clock.m1 = limit->m1.max;
 899                      clock.m1 >= limit->m1.min; clock.m1--) {
 900                         for (clock.m2 = limit->m2.max;
 901                              clock.m2 >= limit->m2.min; clock.m2--) {
 902                                 for (clock.p1 = limit->p1.max;
 903                                      clock.p1 >= limit->p1.min; clock.p1--) {
 904                                         int this_err;
 905
 906                                         intel_clock(dev, refclk, &clock);
 907                                         if (!intel_PLL_is_valid(crtc, &clock))
 908                                                 continue;
 909                                         this_err = abs(clock.dot - target) ;
 910                                         if (this_err < err_most) {
 911                                                 *best_clock = clock;
 912                                                 err_most = this_err;
 913                                                 max_n = clock.n;
 914                                                 found = true;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920         return found;
 921 }
 922
 923 static bool
 924 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                            int target, int refclk, intel_clock_t *best_clock)
 926 {
 927         struct drm_device *dev = crtc->dev;
 928         intel_clock_t clock;
 929
 930         /* return directly when it is eDP */
 931         if (HAS_eDP)
 932                 return true;
 933
 934         if (target < 200000) {
 935                 clock.n = 1;
 936                 clock.p1 = 2;
 937                 clock.p2 = 10;
 938                 clock.m1 = 12;
 939                 clock.m2 = 9;
 940         } else {
 941                 clock.n = 2;
 942                 clock.p1 = 1;
 943                 clock.p2 = 10;
 944                 clock.m1 = 14;
 945                 clock.m2 = 8;
 946         }
 947         intel_clock(dev, refclk, &clock);
 948         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 949         return true;
 950 }
 951
 952 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 953 static bool
 954 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 955                       int target, int refclk, intel_clock_t *best_clock)
 956 {
 957     intel_clock_t clock;
 958     if (target < 200000) {
 959         clock.p1 = 2;
 960         clock.p2 = 10;
 961         clock.n = 2;
 962         clock.m1 = 23;
 963         clock.m2 = 8;
 964     } else {
 965         clock.p1 = 1;
 966         clock.p2 = 10;
 967         clock.n = 1;
 968         clock.m1 = 14;
 969         clock.m2 = 2;
 970     }
 971     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 972     clock.p = (clock.p1 * clock.p2);
 973     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 974     clock.vco = 0;
 975     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 976     return true;
 977 }
 978
 979 void
 980 intel_wait_for_vblank(struct drm_device *dev)
 981 {
 982         /* Wait for 20ms, i.e. one cycle at 50hz. */
 983         if (in_dbg_master())
 984                 mdelay(20); /* The kernel debugger cannot call msleep() */
 985         else
 986                 msleep(20);
 987 }
 988
 989 /* Parameters have changed, update FBC info */
 990 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 991 {
 992         struct drm_device *dev = crtc->dev;
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         struct drm_framebuffer *fb = crtc->fb;
 995         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 996         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 998         int plane, i;
 999         u32 fbc_ctl, fbc_ctl2;
1000
1001         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1002
1003         if (fb->pitch < dev_priv->cfb_pitch)
1004                 dev_priv->cfb_pitch = fb->pitch;
1005
1006         /* FBC_CTL wants 64B units */
1007         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1008         dev_priv->cfb_fence = obj_priv->fence_reg;
1009         dev_priv->cfb_plane = intel_crtc->plane;
1010         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1011
1012         /* Clear old tags */
1013         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1014                 I915_WRITE(FBC_TAG + (i * 4), 0);
1015
1016         /* Set it up... */
1017         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1018         if (obj_priv->tiling_mode != I915_TILING_NONE)
1019                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1020         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1021         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1022
1023         /* enable it... */
1024         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1025         if (IS_I945GM(dev))
1026                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1027         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1028         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1029         if (obj_priv->tiling_mode != I915_TILING_NONE)
1030                 fbc_ctl |= dev_priv->cfb_fence;
1031         I915_WRITE(FBC_CONTROL, fbc_ctl);
1032
1033         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1034                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1035 }
1036
1037 void i8xx_disable_fbc(struct drm_device *dev)
1038 {
1039         struct drm_i915_private *dev_priv = dev->dev_private;
1040         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1041         u32 fbc_ctl;
1042
1043         if (!I915_HAS_FBC(dev))
1044                 return;
1045
1046         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1047                 return; /* Already off, just return */
1048
1049         /* Disable compression */
1050         fbc_ctl = I915_READ(FBC_CONTROL);
1051         fbc_ctl &= ~FBC_CTL_EN;
1052         I915_WRITE(FBC_CONTROL, fbc_ctl);
1053
1054         /* Wait for compressing bit to clear */
1055         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1056                 if (time_after(jiffies, timeout)) {
1057                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1058                         break;
1059                 }
1060                 ; /* do nothing */
1061         }
1062
1063         intel_wait_for_vblank(dev);
1064
1065         DRM_DEBUG_KMS("disabled FBC\n");
1066 }
1067
1068 static bool i8xx_fbc_enabled(struct drm_device *dev)
1069 {
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1073 }
1074
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1076 {
1077         struct drm_device *dev = crtc->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         struct drm_framebuffer *fb = crtc->fb;
1080         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1084                      DPFC_CTL_PLANEB);
1085         unsigned long stall_watermark = 200;
1086         u32 dpfc_ctl;
1087
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091
1092         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1096         } else {
1097                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1098         }
1099
1100         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1105
1106         /* enable it... */
1107         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1108
1109         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1110 }
1111
1112 void g4x_disable_fbc(struct drm_device *dev)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         u32 dpfc_ctl;
1116
1117         /* Disable compression */
1118         dpfc_ctl = I915_READ(DPFC_CONTROL);
1119         dpfc_ctl &= ~DPFC_CTL_EN;
1120         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121         intel_wait_for_vblank(dev);
1122
1123         DRM_DEBUG_KMS("disabled FBC\n");
1124 }
1125
1126 static bool g4x_fbc_enabled(struct drm_device *dev)
1127 {
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1131 }
1132
1133 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1134 {
1135         struct drm_device *dev = crtc->dev;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         struct drm_framebuffer *fb = crtc->fb;
1138         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1139         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1141         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1142                                                DPFC_CTL_PLANEB;
1143         unsigned long stall_watermark = 200;
1144         u32 dpfc_ctl;
1145
1146         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1147         dev_priv->cfb_fence = obj_priv->fence_reg;
1148         dev_priv->cfb_plane = intel_crtc->plane;
1149
1150         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1151         dpfc_ctl &= DPFC_RESERVED;
1152         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1153         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1154                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1155                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1156         } else {
1157                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1158         }
1159
1160         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1161         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1162                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1163                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1164         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1165         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1166         /* enable it... */
1167         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1168                    DPFC_CTL_EN);
1169
1170         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1171 }
1172
1173 void ironlake_disable_fbc(struct drm_device *dev)
1174 {
1175         struct drm_i915_private *dev_priv = dev->dev_private;
1176         u32 dpfc_ctl;
1177
1178         /* Disable compression */
1179         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1180         dpfc_ctl &= ~DPFC_CTL_EN;
1181         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1182         intel_wait_for_vblank(dev);
1183
1184         DRM_DEBUG_KMS("disabled FBC\n");
1185 }
1186
1187 static bool ironlake_fbc_enabled(struct drm_device *dev)
1188 {
1189         struct drm_i915_private *dev_priv = dev->dev_private;
1190
1191         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1192 }
1193
1194 bool intel_fbc_enabled(struct drm_device *dev)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197
1198         if (!dev_priv->display.fbc_enabled)
1199                 return false;
1200
1201         return dev_priv->display.fbc_enabled(dev);
1202 }
1203
1204 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1205 {
1206         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1207
1208         if (!dev_priv->display.enable_fbc)
1209                 return;
1210
1211         dev_priv->display.enable_fbc(crtc, interval);
1212 }
1213
1214 void intel_disable_fbc(struct drm_device *dev)
1215 {
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217
1218         if (!dev_priv->display.disable_fbc)
1219                 return;
1220
1221         dev_priv->display.disable_fbc(dev);
1222 }
1223
1224 /**
1225  * intel_update_fbc - enable/disable FBC as needed
1226  * @crtc: CRTC to point the compressor at
1227  * @mode: mode in use
1228  *
1229  * Set up the framebuffer compression hardware at mode set time.  We
1230  * enable it if possible:
1231  *   - plane A only (on pre-965)
1232  *   - no pixel mulitply/line duplication
1233  *   - no alpha buffer discard
1234  *   - no dual wide
1235  *   - framebuffer <= 2048 in width, 1536 in height
1236  *
1237  * We can't assume that any compression will take place (worst case),
1238  * so the compressed buffer has to be the same size as the uncompressed
1239  * one.  It also must reside (along with the line length buffer) in
1240  * stolen memory.
1241  *
1242  * We need to enable/disable FBC on a global basis.
1243  */
1244 static void intel_update_fbc(struct drm_crtc *crtc,
1245                              struct drm_display_mode *mode)
1246 {
1247         struct drm_device *dev = crtc->dev;
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249         struct drm_framebuffer *fb = crtc->fb;
1250         struct intel_framebuffer *intel_fb;
1251         struct drm_i915_gem_object *obj_priv;
1252         struct drm_crtc *tmp_crtc;
1253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1254         int plane = intel_crtc->plane;
1255         int crtcs_enabled = 0;
1256
1257         DRM_DEBUG_KMS("\n");
1258
1259         if (!i915_powersave)
1260                 return;
1261
1262         if (!I915_HAS_FBC(dev))
1263                 return;
1264
1265         if (!crtc->fb)
1266                 return;
1267
1268         intel_fb = to_intel_framebuffer(fb);
1269         obj_priv = to_intel_bo(intel_fb->obj);
1270
1271         /*
1272          * If FBC is already on, we just have to verify that we can
1273          * keep it that way...
1274          * Need to disable if:
1275          *   - more than one pipe is active
1276          *   - changing FBC params (stride, fence, mode)
1277          *   - new fb is too large to fit in compressed buffer
1278          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1279          */
1280         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1281                 if (tmp_crtc->enabled)
1282                         crtcs_enabled++;
1283         }
1284         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1285         if (crtcs_enabled > 1) {
1286                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1287                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1288                 goto out_disable;
1289         }
1290         if (intel_fb->obj->size > dev_priv->cfb_size) {
1291                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1292                                 "compression\n");
1293                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1294                 goto out_disable;
1295         }
1296         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1297             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1298                 DRM_DEBUG_KMS("mode incompatible with compression, "
1299                                 "disabling\n");
1300                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1301                 goto out_disable;
1302         }
1303         if ((mode->hdisplay > 2048) ||
1304             (mode->vdisplay > 1536)) {
1305                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1306                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1307                 goto out_disable;
1308         }
1309         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1310                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1311                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1312                 goto out_disable;
1313         }
1314         if (obj_priv->tiling_mode != I915_TILING_X) {
1315                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1316                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1317                 goto out_disable;
1318         }
1319
1320         /* If the kernel debugger is active, always disable compression */
1321         if (in_dbg_master())
1322                 goto out_disable;
1323
1324         if (intel_fbc_enabled(dev)) {
1325                 /* We can re-enable it in this case, but need to update pitch */
1326                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1327                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1328                     (plane != dev_priv->cfb_plane))
1329                         intel_disable_fbc(dev);
1330         }
1331
1332         /* Now try to turn it back on if possible */
1333         if (!intel_fbc_enabled(dev))
1334                 intel_enable_fbc(crtc, 500);
1335
1336         return;
1337
1338 out_disable:
1339         /* Multiple disables should be harmless */
1340         if (intel_fbc_enabled(dev)) {
1341                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1342                 intel_disable_fbc(dev);
1343         }
1344 }
1345
1346 int
1347 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1348 {
1349         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1350         u32 alignment;
1351         int ret;
1352
1353         switch (obj_priv->tiling_mode) {
1354         case I915_TILING_NONE:
1355                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1356                         alignment = 128 * 1024;
1357                 else if (IS_I965G(dev))
1358                         alignment = 4 * 1024;
1359                 else
1360                         alignment = 64 * 1024;
1361                 break;
1362         case I915_TILING_X:
1363                 /* pin() will align the object as required by fence */
1364                 alignment = 0;
1365                 break;
1366         case I915_TILING_Y:
1367                 /* FIXME: Is this true? */
1368                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1369                 return -EINVAL;
1370         default:
1371                 BUG();
1372         }
1373
1374         ret = i915_gem_object_pin(obj, alignment);
1375         if (ret != 0)
1376                 return ret;
1377
1378         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1379          * fence, whereas 965+ only requires a fence if using
1380          * framebuffer compression.  For simplicity, we always install
1381          * a fence as the cost is not that onerous.
1382          */
1383         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1384             obj_priv->tiling_mode != I915_TILING_NONE) {
1385                 ret = i915_gem_object_get_fence_reg(obj);
1386                 if (ret != 0) {
1387                         i915_gem_object_unpin(obj);
1388                         return ret;
1389                 }
1390         }
1391
1392         return 0;
1393 }
1394
1395 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1396 static int
1397 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1398                            int x, int y)
1399 {
1400         struct drm_device *dev = crtc->dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1403         struct intel_framebuffer *intel_fb;
1404         struct drm_i915_gem_object *obj_priv;
1405         struct drm_gem_object *obj;
1406         int plane = intel_crtc->plane;
1407         unsigned long Start, Offset;
1408         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1409         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1410         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1411         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1412         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1413         u32 dspcntr;
1414
1415         switch (plane) {
1416         case 0:
1417         case 1:
1418                 break;
1419         default:
1420                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1421                 return -EINVAL;
1422         }
1423
1424         intel_fb = to_intel_framebuffer(fb);
1425         obj = intel_fb->obj;
1426         obj_priv = to_intel_bo(obj);
1427
1428         dspcntr = I915_READ(dspcntr_reg);
1429         /* Mask out pixel format bits in case we change it */
1430         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1431         switch (fb->bits_per_pixel) {
1432         case 8:
1433                 dspcntr |= DISPPLANE_8BPP;
1434                 break;
1435         case 16:
1436                 if (fb->depth == 15)
1437                         dspcntr |= DISPPLANE_15_16BPP;
1438                 else
1439                         dspcntr |= DISPPLANE_16BPP;
1440                 break;
1441         case 24:
1442         case 32:
1443                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1444                 break;
1445         default:
1446                 DRM_ERROR("Unknown color depth\n");
1447                 return -EINVAL;
1448         }
1449         if (IS_I965G(dev)) {
1450                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1451                         dspcntr |= DISPPLANE_TILED;
1452                 else
1453                         dspcntr &= ~DISPPLANE_TILED;
1454         }
1455
1456         if (IS_IRONLAKE(dev))
1457                 /* must disable */
1458                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1459
1460         I915_WRITE(dspcntr_reg, dspcntr);
1461
1462         Start = obj_priv->gtt_offset;
1463         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1464
1465         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1466         I915_WRITE(dspstride, fb->pitch);
1467         if (IS_I965G(dev)) {
1468                 I915_WRITE(dspbase, Offset);
1469                 I915_READ(dspbase);
1470                 I915_WRITE(dspsurf, Start);
1471                 I915_READ(dspsurf);
1472                 I915_WRITE(dsptileoff, (y << 16) | x);
1473         } else {
1474                 I915_WRITE(dspbase, Start + Offset);
1475                 I915_READ(dspbase);
1476         }
1477
1478         if ((IS_I965G(dev) || plane == 0))
1479                 intel_update_fbc(crtc, &crtc->mode);
1480
1481         intel_wait_for_vblank(dev);
1482         intel_increase_pllclock(crtc, true);
1483
1484         return 0;
1485 }
1486
1487 static int
1488 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1489                     struct drm_framebuffer *old_fb)
1490 {
1491         struct drm_device *dev = crtc->dev;
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493         struct drm_i915_master_private *master_priv;
1494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495         struct intel_framebuffer *intel_fb;
1496         struct drm_i915_gem_object *obj_priv;
1497         struct drm_gem_object *obj;
1498         int pipe = intel_crtc->pipe;
1499         int plane = intel_crtc->plane;
1500         unsigned long Start, Offset;
1501         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1502         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1503         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1504         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1505         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1506         u32 dspcntr;
1507         int ret;
1508
1509         /* no fb bound */
1510         if (!crtc->fb) {
1511                 DRM_DEBUG_KMS("No FB bound\n");
1512                 return 0;
1513         }
1514
1515         switch (plane) {
1516         case 0:
1517         case 1:
1518                 break;
1519         default:
1520                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1521                 return -EINVAL;
1522         }
1523
1524         intel_fb = to_intel_framebuffer(crtc->fb);
1525         obj = intel_fb->obj;
1526         obj_priv = to_intel_bo(obj);
1527
1528         mutex_lock(&dev->struct_mutex);
1529         ret = intel_pin_and_fence_fb_obj(dev, obj);
1530         if (ret != 0) {
1531                 mutex_unlock(&dev->struct_mutex);
1532                 return ret;
1533         }
1534
1535         ret = i915_gem_object_set_to_display_plane(obj);
1536         if (ret != 0) {
1537                 i915_gem_object_unpin(obj);
1538                 mutex_unlock(&dev->struct_mutex);
1539                 return ret;
1540         }
1541
1542         dspcntr = I915_READ(dspcntr_reg);
1543         /* Mask out pixel format bits in case we change it */
1544         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545         switch (crtc->fb->bits_per_pixel) {
1546         case 8:
1547                 dspcntr |= DISPPLANE_8BPP;
1548                 break;
1549         case 16:
1550                 if (crtc->fb->depth == 15)
1551                         dspcntr |= DISPPLANE_15_16BPP;
1552                 else
1553                         dspcntr |= DISPPLANE_16BPP;
1554                 break;
1555         case 24:
1556         case 32:
1557                 if (crtc->fb->depth == 30)
1558                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1559                 else
1560                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1561                 break;
1562         default:
1563                 DRM_ERROR("Unknown color depth\n");
1564                 i915_gem_object_unpin(obj);
1565                 mutex_unlock(&dev->struct_mutex);
1566                 return -EINVAL;
1567         }
1568         if (IS_I965G(dev)) {
1569                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1570                         dspcntr |= DISPPLANE_TILED;
1571                 else
1572                         dspcntr &= ~DISPPLANE_TILED;
1573         }
1574
1575         if (HAS_PCH_SPLIT(dev))
1576                 /* must disable */
1577                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1578
1579         I915_WRITE(dspcntr_reg, dspcntr);
1580
1581         Start = obj_priv->gtt_offset;
1582         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1583
1584         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585                       Start, Offset, x, y, crtc->fb->pitch);
1586         I915_WRITE(dspstride, crtc->fb->pitch);
1587         if (IS_I965G(dev)) {
1588                 I915_WRITE(dspsurf, Start);
1589                 I915_WRITE(dsptileoff, (y << 16) | x);
1590                 I915_WRITE(dspbase, Offset);
1591         } else {
1592                 I915_WRITE(dspbase, Start + Offset);
1593         }
1594         POSTING_READ(dspbase);
1595
1596         if ((IS_I965G(dev) || plane == 0))
1597                 intel_update_fbc(crtc, &crtc->mode);
1598
1599         intel_wait_for_vblank(dev);
1600
1601         if (old_fb) {
1602                 intel_fb = to_intel_framebuffer(old_fb);
1603                 obj_priv = to_intel_bo(intel_fb->obj);
1604                 i915_gem_object_unpin(intel_fb->obj);
1605         }
1606         intel_increase_pllclock(crtc, true);
1607
1608         mutex_unlock(&dev->struct_mutex);
1609
1610         if (!dev->primary->master)
1611                 return 0;
1612
1613         master_priv = dev->primary->master->driver_priv;
1614         if (!master_priv->sarea_priv)
1615                 return 0;
1616
1617         if (pipe) {
1618                 master_priv->sarea_priv->pipeB_x = x;
1619                 master_priv->sarea_priv->pipeB_y = y;
1620         } else {
1621                 master_priv->sarea_priv->pipeA_x = x;
1622                 master_priv->sarea_priv->pipeA_y = y;
1623         }
1624
1625         return 0;
1626 }
1627
1628 /* Disable the VGA plane that we never use */
1629 static void i915_disable_vga (struct drm_device *dev)
1630 {
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         u8 sr1;
1633         u32 vga_reg;
1634
1635         if (HAS_PCH_SPLIT(dev))
1636                 vga_reg = CPU_VGACNTRL;
1637         else
1638                 vga_reg = VGACNTRL;
1639
1640         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1641                 return;
1642
1643         I915_WRITE8(VGA_SR_INDEX, 1);
1644         sr1 = I915_READ8(VGA_SR_DATA);
1645         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1646         udelay(100);
1647
1648         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1649 }
1650
1651 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1652 {
1653         struct drm_device *dev = crtc->dev;
1654         struct drm_i915_private *dev_priv = dev->dev_private;
1655         u32 dpa_ctl;
1656
1657         DRM_DEBUG_KMS("\n");
1658         dpa_ctl = I915_READ(DP_A);
1659         dpa_ctl &= ~DP_PLL_ENABLE;
1660         I915_WRITE(DP_A, dpa_ctl);
1661 }
1662
1663 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         u32 dpa_ctl;
1668
1669         dpa_ctl = I915_READ(DP_A);
1670         dpa_ctl |= DP_PLL_ENABLE;
1671         I915_WRITE(DP_A, dpa_ctl);
1672         udelay(200);
1673 }
1674
1675
1676 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1677 {
1678         struct drm_device *dev = crtc->dev;
1679         struct drm_i915_private *dev_priv = dev->dev_private;
1680         u32 dpa_ctl;
1681
1682         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1683         dpa_ctl = I915_READ(DP_A);
1684         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1685
1686         if (clock < 200000) {
1687                 u32 temp;
1688                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1689                 /* workaround for 160Mhz:
1690                    1) program 0x4600c bits 15:0 = 0x8124
1691                    2) program 0x46010 bit 0 = 1
1692                    3) program 0x46034 bit 24 = 1
1693                    4) program 0x64000 bit 14 = 1
1694                    */
1695                 temp = I915_READ(0x4600c);
1696                 temp &= 0xffff0000;
1697                 I915_WRITE(0x4600c, temp | 0x8124);
1698
1699                 temp = I915_READ(0x46010);
1700                 I915_WRITE(0x46010, temp | 1);
1701
1702                 temp = I915_READ(0x46034);
1703                 I915_WRITE(0x46034, temp | (1 << 24));
1704         } else {
1705                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1706         }
1707         I915_WRITE(DP_A, dpa_ctl);
1708
1709         udelay(500);
1710 }
1711
1712 /* The FDI link training functions for ILK/Ibexpeak. */
1713 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1714 {
1715         struct drm_device *dev = crtc->dev;
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1718         int pipe = intel_crtc->pipe;
1719         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1720         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1721         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1722         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1723         u32 temp, tries = 0;
1724
1725         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1726            for train result */
1727         temp = I915_READ(fdi_rx_imr_reg);
1728         temp &= ~FDI_RX_SYMBOL_LOCK;
1729         temp &= ~FDI_RX_BIT_LOCK;
1730         I915_WRITE(fdi_rx_imr_reg, temp);
1731         I915_READ(fdi_rx_imr_reg);
1732         udelay(150);
1733
1734         /* enable CPU FDI TX and PCH FDI RX */
1735         temp = I915_READ(fdi_tx_reg);
1736         temp |= FDI_TX_ENABLE;
1737         temp &= ~(7 << 19);
1738         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1739         temp &= ~FDI_LINK_TRAIN_NONE;
1740         temp |= FDI_LINK_TRAIN_PATTERN_1;
1741         I915_WRITE(fdi_tx_reg, temp);
1742         I915_READ(fdi_tx_reg);
1743
1744         temp = I915_READ(fdi_rx_reg);
1745         temp &= ~FDI_LINK_TRAIN_NONE;
1746         temp |= FDI_LINK_TRAIN_PATTERN_1;
1747         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1748         I915_READ(fdi_rx_reg);
1749         udelay(150);
1750
1751         for (tries = 0; tries < 5; tries++) {
1752                 temp = I915_READ(fdi_rx_iir_reg);
1753                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1754
1755                 if ((temp & FDI_RX_BIT_LOCK)) {
1756                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1757                         I915_WRITE(fdi_rx_iir_reg,
1758                                    temp | FDI_RX_BIT_LOCK);
1759                         break;
1760                 }
1761         }
1762         if (tries == 5)
1763                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1764
1765         /* Train 2 */
1766         temp = I915_READ(fdi_tx_reg);
1767         temp &= ~FDI_LINK_TRAIN_NONE;
1768         temp |= FDI_LINK_TRAIN_PATTERN_2;
1769         I915_WRITE(fdi_tx_reg, temp);
1770
1771         temp = I915_READ(fdi_rx_reg);
1772         temp &= ~FDI_LINK_TRAIN_NONE;
1773         temp |= FDI_LINK_TRAIN_PATTERN_2;
1774         I915_WRITE(fdi_rx_reg, temp);
1775         udelay(150);
1776
1777         tries = 0;
1778
1779         for (tries = 0; tries < 5; tries++) {
1780                 temp = I915_READ(fdi_rx_iir_reg);
1781                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1782
1783                 if (temp & FDI_RX_SYMBOL_LOCK) {
1784                         I915_WRITE(fdi_rx_iir_reg,
1785                                    temp | FDI_RX_SYMBOL_LOCK);
1786                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1787                         break;
1788                 }
1789         }
1790         if (tries == 5)
1791                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1792
1793         DRM_DEBUG_KMS("FDI train done\n");
1794 }
1795
1796 static int snb_b_fdi_train_param [] = {
1797         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1798         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1799         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1800         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1801 };
1802
1803 /* The FDI link training functions for SNB/Cougarpoint. */
1804 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1805 {
1806         struct drm_device *dev = crtc->dev;
1807         struct drm_i915_private *dev_priv = dev->dev_private;
1808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1809         int pipe = intel_crtc->pipe;
1810         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1811         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1812         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1813         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1814         u32 temp, i;
1815
1816         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1817            for train result */
1818         temp = I915_READ(fdi_rx_imr_reg);
1819         temp &= ~FDI_RX_SYMBOL_LOCK;
1820         temp &= ~FDI_RX_BIT_LOCK;
1821         I915_WRITE(fdi_rx_imr_reg, temp);
1822         I915_READ(fdi_rx_imr_reg);
1823         udelay(150);
1824
1825         /* enable CPU FDI TX and PCH FDI RX */
1826         temp = I915_READ(fdi_tx_reg);
1827         temp |= FDI_TX_ENABLE;
1828         temp &= ~(7 << 19);
1829         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1830         temp &= ~FDI_LINK_TRAIN_NONE;
1831         temp |= FDI_LINK_TRAIN_PATTERN_1;
1832         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1833         /* SNB-B */
1834         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1835         I915_WRITE(fdi_tx_reg, temp);
1836         I915_READ(fdi_tx_reg);
1837
1838         temp = I915_READ(fdi_rx_reg);
1839         if (HAS_PCH_CPT(dev)) {
1840                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1841                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1842         } else {
1843                 temp &= ~FDI_LINK_TRAIN_NONE;
1844                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1845         }
1846         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1847         I915_READ(fdi_rx_reg);
1848         udelay(150);
1849
1850         for (i = 0; i < 4; i++ ) {
1851                 temp = I915_READ(fdi_tx_reg);
1852                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1853                 temp |= snb_b_fdi_train_param[i];
1854                 I915_WRITE(fdi_tx_reg, temp);
1855                 udelay(500);
1856
1857                 temp = I915_READ(fdi_rx_iir_reg);
1858                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1859
1860                 if (temp & FDI_RX_BIT_LOCK) {
1861                         I915_WRITE(fdi_rx_iir_reg,
1862                                    temp | FDI_RX_BIT_LOCK);
1863                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1864                         break;
1865                 }
1866         }
1867         if (i == 4)
1868                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1869
1870         /* Train 2 */
1871         temp = I915_READ(fdi_tx_reg);
1872         temp &= ~FDI_LINK_TRAIN_NONE;
1873         temp |= FDI_LINK_TRAIN_PATTERN_2;
1874         if (IS_GEN6(dev)) {
1875                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1876                 /* SNB-B */
1877                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1878         }
1879         I915_WRITE(fdi_tx_reg, temp);
1880
1881         temp = I915_READ(fdi_rx_reg);
1882         if (HAS_PCH_CPT(dev)) {
1883                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1884                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1885         } else {
1886                 temp &= ~FDI_LINK_TRAIN_NONE;
1887                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1888         }
1889         I915_WRITE(fdi_rx_reg, temp);
1890         udelay(150);
1891
1892         for (i = 0; i < 4; i++ ) {
1893                 temp = I915_READ(fdi_tx_reg);
1894                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1895                 temp |= snb_b_fdi_train_param[i];
1896                 I915_WRITE(fdi_tx_reg, temp);
1897                 udelay(500);
1898
1899                 temp = I915_READ(fdi_rx_iir_reg);
1900                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1901
1902                 if (temp & FDI_RX_SYMBOL_LOCK) {
1903                         I915_WRITE(fdi_rx_iir_reg,
1904                                    temp | FDI_RX_SYMBOL_LOCK);
1905                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1906                         break;
1907                 }
1908         }
1909         if (i == 4)
1910                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1911
1912         DRM_DEBUG_KMS("FDI train done.\n");
1913 }
1914
1915 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1916 {
1917         struct drm_device *dev = crtc->dev;
1918         struct drm_i915_private *dev_priv = dev->dev_private;
1919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1920         int pipe = intel_crtc->pipe;
1921         int plane = intel_crtc->plane;
1922         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1923         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1924         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1925         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1926         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1927         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1928         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1929         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1930         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1931         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1932         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1933         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1934         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1935         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1936         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1937         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1938         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1939         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1940         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1941         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1942         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1943         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1944         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1945         u32 temp;
1946         int n;
1947         u32 pipe_bpc;
1948
1949         temp = I915_READ(pipeconf_reg);
1950         pipe_bpc = temp & PIPE_BPC_MASK;
1951
1952         /* XXX: When our outputs are all unaware of DPMS modes other than off
1953          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1954          */
1955         switch (mode) {
1956         case DRM_MODE_DPMS_ON:
1957         case DRM_MODE_DPMS_STANDBY:
1958         case DRM_MODE_DPMS_SUSPEND:
1959                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1960
1961                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1962                         temp = I915_READ(PCH_LVDS);
1963                         if ((temp & LVDS_PORT_EN) == 0) {
1964                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1965                                 POSTING_READ(PCH_LVDS);
1966                         }
1967                 }
1968
1969                 if (HAS_eDP) {
1970                         /* enable eDP PLL */
1971                         ironlake_enable_pll_edp(crtc);
1972                 } else {
1973
1974                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1975                         temp = I915_READ(fdi_rx_reg);
1976                         /*
1977                          * make the BPC in FDI Rx be consistent with that in
1978                          * pipeconf reg.
1979                          */
1980                         temp &= ~(0x7 << 16);
1981                         temp |= (pipe_bpc << 11);
1982                         temp &= ~(7 << 19);
1983                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1984                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1985                         I915_READ(fdi_rx_reg);
1986                         udelay(200);
1987
1988                         /* Switch from Rawclk to PCDclk */
1989                         temp = I915_READ(fdi_rx_reg);
1990                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1991                         I915_READ(fdi_rx_reg);
1992                         udelay(200);
1993
1994                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1995                         temp = I915_READ(fdi_tx_reg);
1996                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1997                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1998                                 I915_READ(fdi_tx_reg);
1999                                 udelay(100);
2000                         }
2001                 }
2002
2003                 /* Enable panel fitting for LVDS */
2004                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2005                     || HAS_eDP || intel_pch_has_edp(crtc)) {
2006                         if (dev_priv->pch_pf_size) {
2007                                 temp = I915_READ(pf_ctl_reg);
2008                                 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
2009                                 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
2010                                 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
2011                         } else
2012                                 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2013                 }
2014
2015                 /* Enable CPU pipe */
2016                 temp = I915_READ(pipeconf_reg);
2017                 if ((temp & PIPEACONF_ENABLE) == 0) {
2018                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2019                         I915_READ(pipeconf_reg);
2020                         udelay(100);
2021                 }
2022
2023                 /* configure and enable CPU plane */
2024                 temp = I915_READ(dspcntr_reg);
2025                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2026                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2027                         /* Flush the plane changes */
2028                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2029                 }
2030
2031                 if (!HAS_eDP) {
2032                         /* For PCH output, training FDI link */
2033                         if (IS_GEN6(dev))
2034                                 gen6_fdi_link_train(crtc);
2035                         else
2036                                 ironlake_fdi_link_train(crtc);
2037
2038                         /* enable PCH DPLL */
2039                         temp = I915_READ(pch_dpll_reg);
2040                         if ((temp & DPLL_VCO_ENABLE) == 0) {
2041                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2042                                 I915_READ(pch_dpll_reg);
2043                         }
2044                         udelay(200);
2045
2046                         if (HAS_PCH_CPT(dev)) {
2047                                 /* Be sure PCH DPLL SEL is set */
2048                                 temp = I915_READ(PCH_DPLL_SEL);
2049                                 if (trans_dpll_sel == 0 &&
2050                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
2051                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2052                                 else if (trans_dpll_sel == 1 &&
2053                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
2054                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2055                                 I915_WRITE(PCH_DPLL_SEL, temp);
2056                                 I915_READ(PCH_DPLL_SEL);
2057                         }
2058
2059                         /* set transcoder timing */
2060                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2061                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2062                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2063
2064                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2065                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2066                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2067
2068                         /* enable normal train */
2069                         temp = I915_READ(fdi_tx_reg);
2070                         temp &= ~FDI_LINK_TRAIN_NONE;
2071                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2072                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2073                         I915_READ(fdi_tx_reg);
2074
2075                         temp = I915_READ(fdi_rx_reg);
2076                         if (HAS_PCH_CPT(dev)) {
2077                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2078                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2079                         } else {
2080                                 temp &= ~FDI_LINK_TRAIN_NONE;
2081                                 temp |= FDI_LINK_TRAIN_NONE;
2082                         }
2083                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2084                         I915_READ(fdi_rx_reg);
2085
2086                         /* wait one idle pattern time */
2087                         udelay(100);
2088
2089                         /* For PCH DP, enable TRANS_DP_CTL */
2090                         if (HAS_PCH_CPT(dev) &&
2091                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2092                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2093                                 int reg;
2094
2095                                 reg = I915_READ(trans_dp_ctl);
2096                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2097                                          TRANS_DP_SYNC_MASK);
2098                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2099                                         TRANS_DP_ENH_FRAMING);
2100
2101                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2102                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2103                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2104                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2105
2106                                 switch (intel_trans_dp_port_sel(crtc)) {
2107                                 case PCH_DP_B:
2108                                         reg |= TRANS_DP_PORT_SEL_B;
2109                                         break;
2110                                 case PCH_DP_C:
2111                                         reg |= TRANS_DP_PORT_SEL_C;
2112                                         break;
2113                                 case PCH_DP_D:
2114                                         reg |= TRANS_DP_PORT_SEL_D;
2115                                         break;
2116                                 default:
2117                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2118                                         reg |= TRANS_DP_PORT_SEL_B;
2119                                         break;
2120                                 }
2121
2122                                 I915_WRITE(trans_dp_ctl, reg);
2123                                 POSTING_READ(trans_dp_ctl);
2124                         }
2125
2126                         /* enable PCH transcoder */
2127                         temp = I915_READ(transconf_reg);
2128                         /*
2129                          * make the BPC in transcoder be consistent with
2130                          * that in pipeconf reg.
2131                          */
2132                         temp &= ~PIPE_BPC_MASK;
2133                         temp |= pipe_bpc;
2134                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2135                         I915_READ(transconf_reg);
2136
2137                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2138                                 ;
2139
2140                 }
2141
2142                 intel_crtc_load_lut(crtc);
2143
2144                 intel_update_fbc(crtc, &crtc->mode);
2145
2146         break;
2147         case DRM_MODE_DPMS_OFF:
2148                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2149
2150                 drm_vblank_off(dev, pipe);
2151                 /* Disable display plane */
2152                 temp = I915_READ(dspcntr_reg);
2153                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2154                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2155                         /* Flush the plane changes */
2156                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2157                         I915_READ(dspbase_reg);
2158                 }
2159
2160                 if (dev_priv->cfb_plane == plane &&
2161                     dev_priv->display.disable_fbc)
2162                         dev_priv->display.disable_fbc(dev);
2163
2164                 i915_disable_vga(dev);
2165
2166                 /* disable cpu pipe, disable after all planes disabled */
2167                 temp = I915_READ(pipeconf_reg);
2168                 if ((temp & PIPEACONF_ENABLE) != 0) {
2169                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2170                         I915_READ(pipeconf_reg);
2171                         n = 0;
2172                         /* wait for cpu pipe off, pipe state */
2173                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2174                                 n++;
2175                                 if (n < 60) {
2176                                         udelay(500);
2177                                         continue;
2178                                 } else {
2179                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2180                                                                 pipe);
2181                                         break;
2182                                 }
2183                         }
2184                 } else
2185                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2186
2187                 udelay(100);
2188
2189                 /* Disable PF */
2190                 temp = I915_READ(pf_ctl_reg);
2191                 if ((temp & PF_ENABLE) != 0) {
2192                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2193                         I915_READ(pf_ctl_reg);
2194                 }
2195                 I915_WRITE(pf_win_size, 0);
2196                 POSTING_READ(pf_win_size);
2197
2198
2199                 /* disable CPU FDI tx and PCH FDI rx */
2200                 temp = I915_READ(fdi_tx_reg);
2201                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2202                 I915_READ(fdi_tx_reg);
2203
2204                 temp = I915_READ(fdi_rx_reg);
2205                 /* BPC in FDI rx is consistent with that in pipeconf */
2206                 temp &= ~(0x07 << 16);
2207                 temp |= (pipe_bpc << 11);
2208                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2209                 I915_READ(fdi_rx_reg);
2210
2211                 udelay(100);
2212
2213                 /* still set train pattern 1 */
2214                 temp = I915_READ(fdi_tx_reg);
2215                 temp &= ~FDI_LINK_TRAIN_NONE;
2216                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2217                 I915_WRITE(fdi_tx_reg, temp);
2218                 POSTING_READ(fdi_tx_reg);
2219
2220                 temp = I915_READ(fdi_rx_reg);
2221                 if (HAS_PCH_CPT(dev)) {
2222                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2223                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2224                 } else {
2225                         temp &= ~FDI_LINK_TRAIN_NONE;
2226                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2227                 }
2228                 I915_WRITE(fdi_rx_reg, temp);
2229                 POSTING_READ(fdi_rx_reg);
2230
2231                 udelay(100);
2232
2233                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2234                         temp = I915_READ(PCH_LVDS);
2235                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2236                         I915_READ(PCH_LVDS);
2237                         udelay(100);
2238                 }
2239
2240                 /* disable PCH transcoder */
2241                 temp = I915_READ(transconf_reg);
2242                 if ((temp & TRANS_ENABLE) != 0) {
2243                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2244                         I915_READ(transconf_reg);
2245                         n = 0;
2246                         /* wait for PCH transcoder off, transcoder state */
2247                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2248                                 n++;
2249                                 if (n < 60) {
2250                                         udelay(500);
2251                                         continue;
2252                                 } else {
2253                                         DRM_DEBUG_KMS("transcoder %d off "
2254                                                         "delay\n", pipe);
2255                                         break;
2256                                 }
2257                         }
2258                 }
2259
2260                 temp = I915_READ(transconf_reg);
2261                 /* BPC in transcoder is consistent with that in pipeconf */
2262                 temp &= ~PIPE_BPC_MASK;
2263                 temp |= pipe_bpc;
2264                 I915_WRITE(transconf_reg, temp);
2265                 I915_READ(transconf_reg);
2266                 udelay(100);
2267
2268                 if (HAS_PCH_CPT(dev)) {
2269                         /* disable TRANS_DP_CTL */
2270                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2271                         int reg;
2272
2273                         reg = I915_READ(trans_dp_ctl);
2274                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2275                         I915_WRITE(trans_dp_ctl, reg);
2276                         POSTING_READ(trans_dp_ctl);
2277
2278                         /* disable DPLL_SEL */
2279                         temp = I915_READ(PCH_DPLL_SEL);
2280                         if (trans_dpll_sel == 0)
2281                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2282                         else
2283                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2284                         I915_WRITE(PCH_DPLL_SEL, temp);
2285                         I915_READ(PCH_DPLL_SEL);
2286
2287                 }
2288
2289                 /* disable PCH DPLL */
2290                 temp = I915_READ(pch_dpll_reg);
2291                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2292                 I915_READ(pch_dpll_reg);
2293
2294                 if (HAS_eDP) {
2295                         ironlake_disable_pll_edp(crtc);
2296                 }
2297
2298                 /* Switch from PCDclk to Rawclk */
2299                 temp = I915_READ(fdi_rx_reg);
2300                 temp &= ~FDI_SEL_PCDCLK;
2301                 I915_WRITE(fdi_rx_reg, temp);
2302                 I915_READ(fdi_rx_reg);
2303
2304                 /* Disable CPU FDI TX PLL */
2305                 temp = I915_READ(fdi_tx_reg);
2306                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2307                 I915_READ(fdi_tx_reg);
2308                 udelay(100);
2309
2310                 temp = I915_READ(fdi_rx_reg);
2311                 temp &= ~FDI_RX_PLL_ENABLE;
2312                 I915_WRITE(fdi_rx_reg, temp);
2313                 I915_READ(fdi_rx_reg);
2314
2315                 /* Wait for the clocks to turn off. */
2316                 udelay(100);
2317                 break;
2318         }
2319 }
2320
2321 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2322 {
2323         struct intel_overlay *overlay;
2324         int ret;
2325
2326         if (!enable && intel_crtc->overlay) {
2327                 overlay = intel_crtc->overlay;
2328                 mutex_lock(&overlay->dev->struct_mutex);
2329                 for (;;) {
2330                         ret = intel_overlay_switch_off(overlay);
2331                         if (ret == 0)
2332                                 break;
2333
2334                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2335                         if (ret != 0) {
2336                                 /* overlay doesn't react anymore. Usually
2337                                  * results in a black screen and an unkillable
2338                                  * X server. */
2339                                 BUG();
2340                                 overlay->hw_wedged = HW_WEDGED;
2341                                 break;
2342                         }
2343                 }
2344                 mutex_unlock(&overlay->dev->struct_mutex);
2345         }
2346         /* Let userspace switch the overlay on again. In most cases userspace
2347          * has to recompute where to put it anyway. */
2348
2349         return;
2350 }
2351
2352 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2353 {
2354         struct drm_device *dev = crtc->dev;
2355         struct drm_i915_private *dev_priv = dev->dev_private;
2356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2357         int pipe = intel_crtc->pipe;
2358         int plane = intel_crtc->plane;
2359         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2360         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2361         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2362         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2363         u32 temp;
2364
2365         /* XXX: When our outputs are all unaware of DPMS modes other than off
2366          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2367          */
2368         switch (mode) {
2369         case DRM_MODE_DPMS_ON:
2370         case DRM_MODE_DPMS_STANDBY:
2371         case DRM_MODE_DPMS_SUSPEND:
2372                 intel_update_watermarks(dev);
2373
2374                 /* Enable the DPLL */
2375                 temp = I915_READ(dpll_reg);
2376                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2377                         I915_WRITE(dpll_reg, temp);
2378                         I915_READ(dpll_reg);
2379                         /* Wait for the clocks to stabilize. */
2380                         udelay(150);
2381                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2382                         I915_READ(dpll_reg);
2383                         /* Wait for the clocks to stabilize. */
2384                         udelay(150);
2385                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2386                         I915_READ(dpll_reg);
2387                         /* Wait for the clocks to stabilize. */
2388                         udelay(150);
2389                 }
2390
2391                 /* Enable the pipe */
2392                 temp = I915_READ(pipeconf_reg);
2393                 if ((temp & PIPEACONF_ENABLE) == 0)
2394                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2395
2396                 /* Enable the plane */
2397                 temp = I915_READ(dspcntr_reg);
2398                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2399                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2400                         /* Flush the plane changes */
2401                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2402                 }
2403
2404                 intel_crtc_load_lut(crtc);
2405
2406                 if ((IS_I965G(dev) || plane == 0))
2407                         intel_update_fbc(crtc, &crtc->mode);
2408
2409                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2410                 intel_crtc_dpms_overlay(intel_crtc, true);
2411         break;
2412         case DRM_MODE_DPMS_OFF:
2413                 intel_update_watermarks(dev);
2414
2415                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2416                 intel_crtc_dpms_overlay(intel_crtc, false);
2417                 drm_vblank_off(dev, pipe);
2418
2419                 if (dev_priv->cfb_plane == plane &&
2420                     dev_priv->display.disable_fbc)
2421                         dev_priv->display.disable_fbc(dev);
2422
2423                 /* Disable the VGA plane that we never use */
2424                 i915_disable_vga(dev);
2425
2426                 /* Disable display plane */
2427                 temp = I915_READ(dspcntr_reg);
2428                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2429                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2430                         /* Flush the plane changes */
2431                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2432                         I915_READ(dspbase_reg);
2433                 }
2434
2435                 if (!IS_I9XX(dev)) {
2436                         /* Wait for vblank for the disable to take effect */
2437                         intel_wait_for_vblank(dev);
2438                 }
2439
2440                 /* Don't disable pipe A or pipe A PLLs if needed */
2441                 if (pipeconf_reg == PIPEACONF &&
2442                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2443                         goto skip_pipe_off;
2444
2445                 /* Next, disable display pipes */
2446                 temp = I915_READ(pipeconf_reg);
2447                 if ((temp & PIPEACONF_ENABLE) != 0) {
2448                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2449                         I915_READ(pipeconf_reg);
2450                 }
2451
2452                 /* Wait for vblank for the disable to take effect. */
2453                 intel_wait_for_vblank(dev);
2454
2455                 temp = I915_READ(dpll_reg);
2456                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2457                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2458                         I915_READ(dpll_reg);
2459                 }
2460         skip_pipe_off:
2461                 /* Wait for the clocks to turn off. */
2462                 udelay(150);
2463                 break;
2464         }
2465 }
2466
2467 /**
2468  * Sets the power management mode of the pipe and plane.
2469  */
2470 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2471 {
2472         struct drm_device *dev = crtc->dev;
2473         struct drm_i915_private *dev_priv = dev->dev_private;
2474         struct drm_i915_master_private *master_priv;
2475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476         int pipe = intel_crtc->pipe;
2477         bool enabled;
2478
2479         dev_priv->display.dpms(crtc, mode);
2480
2481         intel_crtc->dpms_mode = mode;
2482
2483         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2484         intel_crtc_update_cursor(crtc);
2485
2486         if (!dev->primary->master)
2487                 return;
2488
2489         master_priv = dev->primary->master->driver_priv;
2490         if (!master_priv->sarea_priv)
2491                 return;
2492
2493         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2494
2495         switch (pipe) {
2496         case 0:
2497                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2498                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2499                 break;
2500         case 1:
2501                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2502                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2503                 break;
2504         default:
2505                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2506                 break;
2507         }
2508 }
2509
2510 static void intel_crtc_prepare (struct drm_crtc *crtc)
2511 {
2512         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2513         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2514 }
2515
2516 static void intel_crtc_commit (struct drm_crtc *crtc)
2517 {
2518         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2519         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2520 }
2521
2522 void intel_encoder_prepare (struct drm_encoder *encoder)
2523 {
2524         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2525         /* lvds has its own version of prepare see intel_lvds_prepare */
2526         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2527 }
2528
2529 void intel_encoder_commit (struct drm_encoder *encoder)
2530 {
2531         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2532         /* lvds has its own version of commit see intel_lvds_commit */
2533         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2534 }
2535
2536 void intel_encoder_destroy(struct drm_encoder *encoder)
2537 {
2538         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2539
2540         if (intel_encoder->ddc_bus)
2541                 intel_i2c_destroy(intel_encoder->ddc_bus);
2542
2543         if (intel_encoder->i2c_bus)
2544                 intel_i2c_destroy(intel_encoder->i2c_bus);
2545
2546         drm_encoder_cleanup(encoder);
2547         kfree(intel_encoder);
2548 }
2549
2550 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2551                                   struct drm_display_mode *mode,
2552                                   struct drm_display_mode *adjusted_mode)
2553 {
2554         struct drm_device *dev = crtc->dev;
2555         if (HAS_PCH_SPLIT(dev)) {
2556                 /* FDI link clock is fixed at 2.7G */
2557                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2558                         return false;
2559         }
2560         return true;
2561 }
2562
2563 static int i945_get_display_clock_speed(struct drm_device *dev)
2564 {
2565         return 400000;
2566 }
2567
2568 static int i915_get_display_clock_speed(struct drm_device *dev)
2569 {
2570         return 333000;
2571 }
2572
2573 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2574 {
2575         return 200000;
2576 }
2577
2578 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2579 {
2580         u16 gcfgc = 0;
2581
2582         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2583
2584         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2585                 return 133000;
2586         else {
2587                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2588                 case GC_DISPLAY_CLOCK_333_MHZ:
2589                         return 333000;
2590                 default:
2591                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2592                         return 190000;
2593                 }
2594         }
2595 }
2596
2597 static int i865_get_display_clock_speed(struct drm_device *dev)
2598 {
2599         return 266000;
2600 }
2601
2602 static int i855_get_display_clock_speed(struct drm_device *dev)
2603 {
2604         u16 hpllcc = 0;
2605         /* Assume that the hardware is in the high speed state.  This
2606          * should be the default.
2607          */
2608         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2609         case GC_CLOCK_133_200:
2610         case GC_CLOCK_100_200:
2611                 return 200000;
2612         case GC_CLOCK_166_250:
2613                 return 250000;
2614         case GC_CLOCK_100_133:
2615                 return 133000;
2616         }
2617
2618         /* Shouldn't happen */
2619         return 0;
2620 }
2621
2622 static int i830_get_display_clock_speed(struct drm_device *dev)
2623 {
2624         return 133000;
2625 }
2626
2627 /**
2628  * Return the pipe currently connected to the panel fitter,
2629  * or -1 if the panel fitter is not present or not in use
2630  */
2631 int intel_panel_fitter_pipe (struct drm_device *dev)
2632 {
2633         struct drm_i915_private *dev_priv = dev->dev_private;
2634         u32  pfit_control;
2635
2636         /* i830 doesn't have a panel fitter */
2637         if (IS_I830(dev))
2638                 return -1;
2639
2640         pfit_control = I915_READ(PFIT_CONTROL);
2641
2642         /* See if the panel fitter is in use */
2643         if ((pfit_control & PFIT_ENABLE) == 0)
2644                 return -1;
2645
2646         /* 965 can place panel fitter on either pipe */
2647         if (IS_I965G(dev))
2648                 return (pfit_control >> 29) & 0x3;
2649
2650         /* older chips can only use pipe 1 */
2651         return 1;
2652 }
2653
2654 struct fdi_m_n {
2655         u32        tu;
2656         u32        gmch_m;
2657         u32        gmch_n;
2658         u32        link_m;
2659         u32        link_n;
2660 };
2661
2662 static void
2663 fdi_reduce_ratio(u32 *num, u32 *den)
2664 {
2665         while (*num > 0xffffff || *den > 0xffffff) {
2666                 *num >>= 1;
2667                 *den >>= 1;
2668         }
2669 }
2670
2671 #define DATA_N 0x800000
2672 #define LINK_N 0x80000
2673
2674 static void
2675 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2676                      int link_clock, struct fdi_m_n *m_n)
2677 {
2678         u64 temp;
2679
2680         m_n->tu = 64; /* default size */
2681
2682         temp = (u64) DATA_N * pixel_clock;
2683         temp = div_u64(temp, link_clock);
2684         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2685         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2686         m_n->gmch_n = DATA_N;
2687         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2688
2689         temp = (u64) LINK_N * pixel_clock;
2690         m_n->link_m = div_u64(temp, link_clock);
2691         m_n->link_n = LINK_N;
2692         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2693 }
2694
2695
2696 struct intel_watermark_params {
2697         unsigned long fifo_size;
2698         unsigned long max_wm;
2699         unsigned long default_wm;
2700         unsigned long guard_size;
2701         unsigned long cacheline_size;
2702 };
2703
2704 /* Pineview has different values for various configs */
2705 static struct intel_watermark_params pineview_display_wm = {
2706         PINEVIEW_DISPLAY_FIFO,
2707         PINEVIEW_MAX_WM,
2708         PINEVIEW_DFT_WM,
2709         PINEVIEW_GUARD_WM,
2710         PINEVIEW_FIFO_LINE_SIZE
2711 };
2712 static struct intel_watermark_params pineview_display_hplloff_wm = {
2713         PINEVIEW_DISPLAY_FIFO,
2714         PINEVIEW_MAX_WM,
2715         PINEVIEW_DFT_HPLLOFF_WM,
2716         PINEVIEW_GUARD_WM,
2717         PINEVIEW_FIFO_LINE_SIZE
2718 };
2719 static struct intel_watermark_params pineview_cursor_wm = {
2720         PINEVIEW_CURSOR_FIFO,
2721         PINEVIEW_CURSOR_MAX_WM,
2722         PINEVIEW_CURSOR_DFT_WM,
2723         PINEVIEW_CURSOR_GUARD_WM,
2724         PINEVIEW_FIFO_LINE_SIZE,
2725 };
2726 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2727         PINEVIEW_CURSOR_FIFO,
2728         PINEVIEW_CURSOR_MAX_WM,
2729         PINEVIEW_CURSOR_DFT_WM,
2730         PINEVIEW_CURSOR_GUARD_WM,
2731         PINEVIEW_FIFO_LINE_SIZE
2732 };
2733 static struct intel_watermark_params g4x_wm_info = {
2734         G4X_FIFO_SIZE,
2735         G4X_MAX_WM,
2736         G4X_MAX_WM,
2737         2,
2738         G4X_FIFO_LINE_SIZE,
2739 };
2740 static struct intel_watermark_params g4x_cursor_wm_info = {
2741         I965_CURSOR_FIFO,
2742         I965_CURSOR_MAX_WM,
2743         I965_CURSOR_DFT_WM,
2744         2,
2745         G4X_FIFO_LINE_SIZE,
2746 };
2747 static struct intel_watermark_params i965_cursor_wm_info = {
2748         I965_CURSOR_FIFO,
2749         I965_CURSOR_MAX_WM,
2750         I965_CURSOR_DFT_WM,
2751         2,
2752         I915_FIFO_LINE_SIZE,
2753 };
2754 static struct intel_watermark_params i945_wm_info = {
2755         I945_FIFO_SIZE,
2756         I915_MAX_WM,
2757         1,
2758         2,
2759         I915_FIFO_LINE_SIZE
2760 };
2761 static struct intel_watermark_params i915_wm_info = {
2762         I915_FIFO_SIZE,
2763         I915_MAX_WM,
2764         1,
2765         2,
2766         I915_FIFO_LINE_SIZE
2767 };
2768 static struct intel_watermark_params i855_wm_info = {
2769         I855GM_FIFO_SIZE,
2770         I915_MAX_WM,
2771         1,
2772         2,
2773         I830_FIFO_LINE_SIZE
2774 };
2775 static struct intel_watermark_params i830_wm_info = {
2776         I830_FIFO_SIZE,
2777         I915_MAX_WM,
2778         1,
2779         2,
2780         I830_FIFO_LINE_SIZE
2781 };
2782
2783 static struct intel_watermark_params ironlake_display_wm_info = {
2784         ILK_DISPLAY_FIFO,
2785         ILK_DISPLAY_MAXWM,
2786         ILK_DISPLAY_DFTWM,
2787         2,
2788         ILK_FIFO_LINE_SIZE
2789 };
2790
2791 static struct intel_watermark_params ironlake_cursor_wm_info = {
2792         ILK_CURSOR_FIFO,
2793         ILK_CURSOR_MAXWM,
2794         ILK_CURSOR_DFTWM,
2795         2,
2796         ILK_FIFO_LINE_SIZE
2797 };
2798
2799 static struct intel_watermark_params ironlake_display_srwm_info = {
2800         ILK_DISPLAY_SR_FIFO,
2801         ILK_DISPLAY_MAX_SRWM,
2802         ILK_DISPLAY_DFT_SRWM,
2803         2,
2804         ILK_FIFO_LINE_SIZE
2805 };
2806
2807 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2808         ILK_CURSOR_SR_FIFO,
2809         ILK_CURSOR_MAX_SRWM,
2810         ILK_CURSOR_DFT_SRWM,
2811         2,
2812         ILK_FIFO_LINE_SIZE
2813 };
2814
2815 /**
2816  * intel_calculate_wm - calculate watermark level
2817  * @clock_in_khz: pixel clock
2818  * @wm: chip FIFO params
2819  * @pixel_size: display pixel size
2820  * @latency_ns: memory latency for the platform
2821  *
2822  * Calculate the watermark level (the level at which the display plane will
2823  * start fetching from memory again).  Each chip has a different display
2824  * FIFO size and allocation, so the caller needs to figure that out and pass
2825  * in the correct intel_watermark_params structure.
2826  *
2827  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2828  * on the pixel size.  When it reaches the watermark level, it'll start
2829  * fetching FIFO line sized based chunks from memory until the FIFO fills
2830  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2831  * will occur, and a display engine hang could result.
2832  */
2833 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2834                                         struct intel_watermark_params *wm,
2835                                         int pixel_size,
2836                                         unsigned long latency_ns)
2837 {
2838         long entries_required, wm_size;
2839
2840         /*
2841          * Note: we need to make sure we don't overflow for various clock &
2842          * latency values.
2843          * clocks go from a few thousand to several hundred thousand.
2844          * latency is usually a few thousand
2845          */
2846         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2847                 1000;
2848         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2849
2850         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2851
2852         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2853
2854         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2855
2856         /* Don't promote wm_size to unsigned... */
2857         if (wm_size > (long)wm->max_wm)
2858                 wm_size = wm->max_wm;
2859         if (wm_size <= 0) {
2860                 wm_size = wm->default_wm;
2861                 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2862                           " entries required = %ld, available = %lu.\n",
2863                           entries_required + wm->guard_size,
2864                           wm->fifo_size);
2865         }
2866
2867         return wm_size;
2868 }
2869
2870 struct cxsr_latency {
2871         int is_desktop;
2872         int is_ddr3;
2873         unsigned long fsb_freq;
2874         unsigned long mem_freq;
2875         unsigned long display_sr;
2876         unsigned long display_hpll_disable;
2877         unsigned long cursor_sr;
2878         unsigned long cursor_hpll_disable;
2879 };
2880
2881 static const struct cxsr_latency cxsr_latency_table[] = {
2882         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2883         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2884         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2885         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2886         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2887
2888         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2889         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2890         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2891         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2892         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2893
2894         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2895         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2896         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2897         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2898         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2899
2900         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2901         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2902         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2903         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2904         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2905
2906         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2907         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2908         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2909         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2910         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2911
2912         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2913         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2914         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2915         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2916         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2917 };
2918
2919 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2920                                                          int is_ddr3,
2921                                                          int fsb,
2922                                                          int mem)
2923 {
2924         const struct cxsr_latency *latency;
2925         int i;
2926
2927         if (fsb == 0 || mem == 0)
2928                 return NULL;
2929
2930         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2931                 latency = &cxsr_latency_table[i];
2932                 if (is_desktop == latency->is_desktop &&
2933                     is_ddr3 == latency->is_ddr3 &&
2934                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2935                         return latency;
2936         }
2937
2938         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2939
2940         return NULL;
2941 }
2942
2943 static void pineview_disable_cxsr(struct drm_device *dev)
2944 {
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946
2947         /* deactivate cxsr */
2948         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2949 }
2950
2951 /*
2952  * Latency for FIFO fetches is dependent on several factors:
2953  *   - memory configuration (speed, channels)
2954  *   - chipset
2955  *   - current MCH state
2956  * It can be fairly high in some situations, so here we assume a fairly
2957  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2958  * set this value too high, the FIFO will fetch frequently to stay full)
2959  * and power consumption (set it too low to save power and we might see
2960  * FIFO underruns and display "flicker").
2961  *
2962  * A value of 5us seems to be a good balance; safe for very low end
2963  * platforms but not overly aggressive on lower latency configs.
2964  */
2965 static const int latency_ns = 5000;
2966
2967 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2968 {
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         uint32_t dsparb = I915_READ(DSPARB);
2971         int size;
2972
2973         size = dsparb & 0x7f;
2974         if (plane)
2975                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2976
2977         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2978                         plane ? "B" : "A", size);
2979
2980         return size;
2981 }
2982
2983 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2984 {
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986         uint32_t dsparb = I915_READ(DSPARB);
2987         int size;
2988
2989         size = dsparb & 0x1ff;
2990         if (plane)
2991                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2992         size >>= 1; /* Convert to cachelines */
2993
2994         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2995                         plane ? "B" : "A", size);
2996
2997         return size;
2998 }
2999
3000 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3001 {
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         uint32_t dsparb = I915_READ(DSPARB);
3004         int size;
3005
3006         size = dsparb & 0x7f;
3007         size >>= 2; /* Convert to cachelines */
3008
3009         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3010                         plane ? "B" : "A",
3011                   size);
3012
3013         return size;
3014 }
3015
3016 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3017 {
3018         struct drm_i915_private *dev_priv = dev->dev_private;
3019         uint32_t dsparb = I915_READ(DSPARB);
3020         int size;
3021
3022         size = dsparb & 0x7f;
3023         size >>= 1; /* Convert to cachelines */
3024
3025         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3026                         plane ? "B" : "A", size);
3027
3028         return size;
3029 }
3030
3031 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3032                           int planeb_clock, int sr_hdisplay, int unused,
3033                           int pixel_size)
3034 {
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         const struct cxsr_latency *latency;
3037         u32 reg;
3038         unsigned long wm;
3039         int sr_clock;
3040
3041         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3042                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3043         if (!latency) {
3044                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3045                 pineview_disable_cxsr(dev);
3046                 return;
3047         }
3048
3049         if (!planea_clock || !planeb_clock) {
3050                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3051
3052                 /* Display SR */
3053                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3054                                         pixel_size, latency->display_sr);
3055                 reg = I915_READ(DSPFW1);
3056                 reg &= ~DSPFW_SR_MASK;
3057                 reg |= wm << DSPFW_SR_SHIFT;
3058                 I915_WRITE(DSPFW1, reg);
3059                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3060
3061                 /* cursor SR */
3062                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3063                                         pixel_size, latency->cursor_sr);
3064                 reg = I915_READ(DSPFW3);
3065                 reg &= ~DSPFW_CURSOR_SR_MASK;
3066                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3067                 I915_WRITE(DSPFW3, reg);
3068
3069                 /* Display HPLL off SR */
3070                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3071                                         pixel_size, latency->display_hpll_disable);
3072                 reg = I915_READ(DSPFW3);
3073                 reg &= ~DSPFW_HPLL_SR_MASK;
3074                 reg |= wm & DSPFW_HPLL_SR_MASK;
3075                 I915_WRITE(DSPFW3, reg);
3076
3077                 /* cursor HPLL off SR */
3078                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3079                                         pixel_size, latency->cursor_hpll_disable);
3080                 reg = I915_READ(DSPFW3);
3081                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3082                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3083                 I915_WRITE(DSPFW3, reg);
3084                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3085
3086                 /* activate cxsr */
3087                 I915_WRITE(DSPFW3,
3088                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3089                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3090         } else {
3091                 pineview_disable_cxsr(dev);
3092                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3093         }
3094 }
3095
3096 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3097                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3098                           int pixel_size)
3099 {
3100         struct drm_i915_private *dev_priv = dev->dev_private;
3101         int total_size, cacheline_size;
3102         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3103         struct intel_watermark_params planea_params, planeb_params;
3104         unsigned long line_time_us;
3105         int sr_clock, sr_entries = 0, entries_required;
3106
3107         /* Create copies of the base settings for each pipe */
3108         planea_params = planeb_params = g4x_wm_info;
3109
3110         /* Grab a couple of global values before we overwrite them */
3111         total_size = planea_params.fifo_size;
3112         cacheline_size = planea_params.cacheline_size;
3113
3114         /*
3115          * Note: we need to make sure we don't overflow for various clock &
3116          * latency values.
3117          * clocks go from a few thousand to several hundred thousand.
3118          * latency is usually a few thousand
3119          */
3120         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3121                 1000;
3122         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3123         planea_wm = entries_required + planea_params.guard_size;
3124
3125         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3126                 1000;
3127         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3128         planeb_wm = entries_required + planeb_params.guard_size;
3129
3130         cursora_wm = cursorb_wm = 16;
3131         cursor_sr = 32;
3132
3133         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3134
3135         /* Calc sr entries for one plane configs */
3136         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3137                 /* self-refresh has much higher latency */
3138                 static const int sr_latency_ns = 12000;
3139
3140                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3141                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3142
3143                 /* Use ns/us then divide to preserve precision */
3144                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3145                               pixel_size * sr_hdisplay;
3146                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3147
3148                 entries_required = (((sr_latency_ns / line_time_us) +
3149                                      1000) / 1000) * pixel_size * 64;
3150                 entries_required = DIV_ROUND_UP(entries_required,
3151                                            g4x_cursor_wm_info.cacheline_size);
3152                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3153
3154                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3155                         cursor_sr = g4x_cursor_wm_info.max_wm;
3156                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3157                               "cursor %d\n", sr_entries, cursor_sr);
3158
3159                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3160         } else {
3161                 /* Turn off self refresh if both pipes are enabled */
3162                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3163                                         & ~FW_BLC_SELF_EN);
3164         }
3165
3166         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3167                   planea_wm, planeb_wm, sr_entries);
3168
3169         planea_wm &= 0x3f;
3170         planeb_wm &= 0x3f;
3171
3172         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3173                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3174                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3175         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3176                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3177         /* HPLL off in SR has some issues on G4x... disable it */
3178         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3179                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3180 }
3181
3182 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3183                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3184                            int pixel_size)
3185 {
3186         struct drm_i915_private *dev_priv = dev->dev_private;
3187         unsigned long line_time_us;
3188         int sr_clock, sr_entries, srwm = 1;
3189         int cursor_sr = 16;
3190
3191         /* Calc sr entries for one plane configs */
3192         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3193                 /* self-refresh has much higher latency */
3194                 static const int sr_latency_ns = 12000;
3195
3196                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3197                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3198
3199                 /* Use ns/us then divide to preserve precision */
3200                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3201                               pixel_size * sr_hdisplay;
3202                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3203                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3204                 srwm = I965_FIFO_SIZE - sr_entries;
3205                 if (srwm < 0)
3206                         srwm = 1;
3207                 srwm &= 0x1ff;
3208
3209                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3210                              pixel_size * 64;
3211                 sr_entries = DIV_ROUND_UP(sr_entries,
3212                                           i965_cursor_wm_info.cacheline_size);
3213                 cursor_sr = i965_cursor_wm_info.fifo_size -
3214                             (sr_entries + i965_cursor_wm_info.guard_size);
3215
3216                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3217                         cursor_sr = i965_cursor_wm_info.max_wm;
3218
3219                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3220                               "cursor %d\n", srwm, cursor_sr);
3221
3222                 if (IS_I965GM(dev))
3223                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3224         } else {
3225                 /* Turn off self refresh if both pipes are enabled */
3226                 if (IS_I965GM(dev))
3227                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3228                                    & ~FW_BLC_SELF_EN);
3229         }
3230
3231         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3232                       srwm);
3233
3234         /* 965 has limitations... */
3235         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3236                    (8 << 0));
3237         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3238         /* update cursor SR watermark */
3239         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3240 }
3241
3242 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3243                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3244                            int pixel_size)
3245 {
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         uint32_t fwater_lo;
3248         uint32_t fwater_hi;
3249         int total_size, cacheline_size, cwm, srwm = 1;
3250         int planea_wm, planeb_wm;
3251         struct intel_watermark_params planea_params, planeb_params;
3252         unsigned long line_time_us;
3253         int sr_clock, sr_entries = 0;
3254
3255         /* Create copies of the base settings for each pipe */
3256         if (IS_I965GM(dev) || IS_I945GM(dev))
3257                 planea_params = planeb_params = i945_wm_info;
3258         else if (IS_I9XX(dev))
3259                 planea_params = planeb_params = i915_wm_info;
3260         else
3261                 planea_params = planeb_params = i855_wm_info;
3262
3263         /* Grab a couple of global values before we overwrite them */
3264         total_size = planea_params.fifo_size;
3265         cacheline_size = planea_params.cacheline_size;
3266
3267         /* Update per-plane FIFO sizes */
3268         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3269         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3270
3271         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3272                                        pixel_size, latency_ns);
3273         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3274                                        pixel_size, latency_ns);
3275         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3276
3277         /*
3278          * Overlay gets an aggressive default since video jitter is bad.
3279          */
3280         cwm = 2;
3281
3282         /* Calc sr entries for one plane configs */
3283         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3284             (!planea_clock || !planeb_clock)) {
3285                 /* self-refresh has much higher latency */
3286                 static const int sr_latency_ns = 6000;
3287
3288                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3289                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3290
3291                 /* Use ns/us then divide to preserve precision */
3292                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3293                               pixel_size * sr_hdisplay;
3294                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3295                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3296                 srwm = total_size - sr_entries;
3297                 if (srwm < 0)
3298                         srwm = 1;
3299
3300                 if (IS_I945G(dev) || IS_I945GM(dev))
3301                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3302                 else if (IS_I915GM(dev)) {
3303                         /* 915M has a smaller SRWM field */
3304                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3305                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3306                 }
3307         } else {
3308                 /* Turn off self refresh if both pipes are enabled */
3309                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3310                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3311                                    & ~FW_BLC_SELF_EN);
3312                 } else if (IS_I915GM(dev)) {
3313                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3314                 }
3315         }
3316
3317         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3318                   planea_wm, planeb_wm, cwm, srwm);
3319
3320         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3321         fwater_hi = (cwm & 0x1f);
3322
3323         /* Set request length to 8 cachelines per fetch */
3324         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3325         fwater_hi = fwater_hi | (1 << 8);
3326
3327         I915_WRITE(FW_BLC, fwater_lo);
3328         I915_WRITE(FW_BLC2, fwater_hi);
3329 }
3330
3331 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3332                            int unused2, int unused3, int pixel_size)
3333 {
3334         struct drm_i915_private *dev_priv = dev->dev_private;
3335         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3336         int planea_wm;
3337
3338         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3339
3340         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3341                                        pixel_size, latency_ns);
3342         fwater_lo |= (3<<8) | planea_wm;
3343
3344         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3345
3346         I915_WRITE(FW_BLC, fwater_lo);
3347 }
3348
3349 #define ILK_LP0_PLANE_LATENCY           700
3350 #define ILK_LP0_CURSOR_LATENCY          1300
3351
3352 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3353                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3354                        int pixel_size)
3355 {
3356         struct drm_i915_private *dev_priv = dev->dev_private;
3357         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3358         int sr_wm, cursor_wm;
3359         unsigned long line_time_us;
3360         int sr_clock, entries_required;
3361         u32 reg_value;
3362         int line_count;
3363         int planea_htotal = 0, planeb_htotal = 0;
3364         struct drm_crtc *crtc;
3365         struct intel_crtc *intel_crtc;
3366
3367         /* Need htotal for all active display plane */
3368         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3369                 intel_crtc = to_intel_crtc(crtc);
3370                 if (crtc->enabled) {
3371                         if (intel_crtc->plane == 0)
3372                                 planea_htotal = crtc->mode.htotal;
3373                         else
3374                                 planeb_htotal = crtc->mode.htotal;
3375                 }
3376         }
3377
3378         /* Calculate and update the watermark for plane A */
3379         if (planea_clock) {
3380                 entries_required = ((planea_clock / 1000) * pixel_size *
3381                                      ILK_LP0_PLANE_LATENCY) / 1000;
3382                 entries_required = DIV_ROUND_UP(entries_required,
3383                                                 ironlake_display_wm_info.cacheline_size);
3384                 planea_wm = entries_required +
3385                             ironlake_display_wm_info.guard_size;
3386
3387                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3388                         planea_wm = ironlake_display_wm_info.max_wm;
3389
3390                 /* Use the large buffer method to calculate cursor watermark */
3391                 line_time_us = (planea_htotal * 1000) / planea_clock;
3392
3393                 /* Use ns/us then divide to preserve precision */
3394                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3395
3396                 /* calculate the cursor watermark for cursor A */
3397                 entries_required = line_count * 64 * pixel_size;
3398                 entries_required = DIV_ROUND_UP(entries_required,
3399                                                 ironlake_cursor_wm_info.cacheline_size);
3400                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3401                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3402                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3403
3404                 reg_value = I915_READ(WM0_PIPEA_ILK);
3405                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3406                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3407                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3408                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3409                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3410                                 "cursor: %d\n", planea_wm, cursora_wm);
3411         }
3412         /* Calculate and update the watermark for plane B */
3413         if (planeb_clock) {
3414                 entries_required = ((planeb_clock / 1000) * pixel_size *
3415                                      ILK_LP0_PLANE_LATENCY) / 1000;
3416                 entries_required = DIV_ROUND_UP(entries_required,
3417                                                 ironlake_display_wm_info.cacheline_size);
3418                 planeb_wm = entries_required +
3419                             ironlake_display_wm_info.guard_size;
3420
3421                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3422                         planeb_wm = ironlake_display_wm_info.max_wm;
3423
3424                 /* Use the large buffer method to calculate cursor watermark */
3425                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3426
3427                 /* Use ns/us then divide to preserve precision */
3428                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3429
3430                 /* calculate the cursor watermark for cursor B */
3431                 entries_required = line_count * 64 * pixel_size;
3432                 entries_required = DIV_ROUND_UP(entries_required,
3433                                                 ironlake_cursor_wm_info.cacheline_size);
3434                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3435                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3436                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3437
3438                 reg_value = I915_READ(WM0_PIPEB_ILK);
3439                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3440                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3441                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3442                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3443                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3444                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3445         }
3446
3447         /*
3448          * Calculate and update the self-refresh watermark only when one
3449          * display plane is used.
3450          */
3451         if (!planea_clock || !planeb_clock) {
3452
3453                 /* Read the self-refresh latency. The unit is 0.5us */
3454                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3455
3456                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3457                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3458
3459                 /* Use ns/us then divide to preserve precision */
3460                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3461                                / 1000;
3462
3463                 /* calculate the self-refresh watermark for display plane */
3464                 entries_required = line_count * sr_hdisplay * pixel_size;
3465                 entries_required = DIV_ROUND_UP(entries_required,
3466                                                 ironlake_display_srwm_info.cacheline_size);
3467                 sr_wm = entries_required +
3468                         ironlake_display_srwm_info.guard_size;
3469
3470                 /* calculate the self-refresh watermark for display cursor */
3471                 entries_required = line_count * pixel_size * 64;
3472                 entries_required = DIV_ROUND_UP(entries_required,
3473                                                 ironlake_cursor_srwm_info.cacheline_size);
3474                 cursor_wm = entries_required +
3475                             ironlake_cursor_srwm_info.guard_size;
3476
3477                 /* configure watermark and enable self-refresh */
3478                 reg_value = I915_READ(WM1_LP_ILK);
3479                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3480                                WM1_LP_CURSOR_MASK);
3481                 reg_value |= WM1_LP_SR_EN |
3482                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3483                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3484
3485                 I915_WRITE(WM1_LP_ILK, reg_value);
3486                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3487                                 "cursor %d\n", sr_wm, cursor_wm);
3488
3489         } else {
3490                 /* Turn off self refresh if both pipes are enabled */
3491                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3492         }
3493 }
3494 /**
3495  * intel_update_watermarks - update FIFO watermark values based on current modes
3496  *
3497  * Calculate watermark values for the various WM regs based on current mode
3498  * and plane configuration.
3499  *
3500  * There are several cases to deal with here:
3501  *   - normal (i.e. non-self-refresh)
3502  *   - self-refresh (SR) mode
3503  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3504  *   - lines are small relative to FIFO size (buffer can hold more than 2
3505  *     lines), so need to account for TLB latency
3506  *
3507  *   The normal calculation is:
3508  *     watermark = dotclock * bytes per pixel * latency
3509  *   where latency is platform & configuration dependent (we assume pessimal
3510  *   values here).
3511  *
3512  *   The SR calculation is:
3513  *     watermark = (trunc(latency/line time)+1) * surface width *
3514  *       bytes per pixel
3515  *   where
3516  *     line time = htotal / dotclock
3517  *     surface width = hdisplay for normal plane and 64 for cursor
3518  *   and latency is assumed to be high, as above.
3519  *
3520  * The final value programmed to the register should always be rounded up,
3521  * and include an extra 2 entries to account for clock crossings.
3522  *
3523  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3524  * to set the non-SR watermarks to 8.
3525   */
3526 static void intel_update_watermarks(struct drm_device *dev)
3527 {
3528         struct drm_i915_private *dev_priv = dev->dev_private;
3529         struct drm_crtc *crtc;
3530         struct intel_crtc *intel_crtc;
3531         int sr_hdisplay = 0;
3532         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3533         int enabled = 0, pixel_size = 0;
3534         int sr_htotal = 0;
3535
3536         if (!dev_priv->display.update_wm)
3537                 return;
3538
3539         /* Get the clock config from both planes */
3540         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3541                 intel_crtc = to_intel_crtc(crtc);
3542                 if (crtc->enabled) {
3543                         enabled++;
3544                         if (intel_crtc->plane == 0) {
3545                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3546                                           intel_crtc->pipe, crtc->mode.clock);
3547                                 planea_clock = crtc->mode.clock;
3548                         } else {
3549                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3550                                           intel_crtc->pipe, crtc->mode.clock);
3551                                 planeb_clock = crtc->mode.clock;
3552                         }
3553                         sr_hdisplay = crtc->mode.hdisplay;
3554                         sr_clock = crtc->mode.clock;
3555                         sr_htotal = crtc->mode.htotal;
3556                         if (crtc->fb)
3557                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3558                         else
3559                                 pixel_size = 4; /* by default */
3560                 }
3561         }
3562
3563         if (enabled <= 0)
3564                 return;
3565
3566         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3567                                     sr_hdisplay, sr_htotal, pixel_size);
3568 }
3569
3570 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3571                                struct drm_display_mode *mode,
3572                                struct drm_display_mode *adjusted_mode,
3573                                int x, int y,
3574                                struct drm_framebuffer *old_fb)
3575 {
3576         struct drm_device *dev = crtc->dev;
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3579         int pipe = intel_crtc->pipe;
3580         int plane = intel_crtc->plane;
3581         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3582         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3583         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3584         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3585         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3586         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3587         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3588         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3589         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3590         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3591         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3592         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3593         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3594         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3595         int refclk, num_connectors = 0;
3596         intel_clock_t clock, reduced_clock;
3597         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3598         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3599         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3600         bool is_edp = false;
3601         struct drm_mode_config *mode_config = &dev->mode_config;
3602         struct drm_encoder *encoder;
3603         struct intel_encoder *intel_encoder = NULL;
3604         const intel_limit_t *limit;
3605         int ret;
3606         struct fdi_m_n m_n = {0};
3607         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3608         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3609         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3610         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3611         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3612         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3613         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3614         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3615         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3616         int lvds_reg = LVDS;
3617         u32 temp;
3618         int sdvo_pixel_multiply;
3619         int target_clock;
3620
3621         drm_vblank_pre_modeset(dev, pipe);
3622
3623         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3624
3625                 if (!encoder || encoder->crtc != crtc)
3626                         continue;
3627
3628                 intel_encoder = enc_to_intel_encoder(encoder);
3629
3630                 switch (intel_encoder->type) {
3631                 case INTEL_OUTPUT_LVDS:
3632                         is_lvds = true;
3633                         break;
3634                 case INTEL_OUTPUT_SDVO:
3635                 case INTEL_OUTPUT_HDMI:
3636                         is_sdvo = true;
3637                         if (intel_encoder->needs_tv_clock)
3638                                 is_tv = true;
3639                         break;
3640                 case INTEL_OUTPUT_DVO:
3641                         is_dvo = true;
3642                         break;
3643                 case INTEL_OUTPUT_TVOUT:
3644                         is_tv = true;
3645                         break;
3646                 case INTEL_OUTPUT_ANALOG:
3647                         is_crt = true;
3648                         break;
3649                 case INTEL_OUTPUT_DISPLAYPORT:
3650                         is_dp = true;
3651                         break;
3652                 case INTEL_OUTPUT_EDP:
3653                         is_edp = true;
3654                         break;
3655                 }
3656
3657                 num_connectors++;
3658         }
3659
3660         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3661                 refclk = dev_priv->lvds_ssc_freq * 1000;
3662                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3663                                         refclk / 1000);
3664         } else if (IS_I9XX(dev)) {
3665                 refclk = 96000;
3666                 if (HAS_PCH_SPLIT(dev))
3667                         refclk = 120000; /* 120Mhz refclk */
3668         } else {
3669                 refclk = 48000;
3670         }
3671
3672
3673         /*
3674          * Returns a set of divisors for the desired target clock with the given
3675          * refclk, or FALSE.  The returned values represent the clock equation:
3676          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3677          */
3678         limit = intel_limit(crtc);
3679         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3680         if (!ok) {
3681                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3682                 drm_vblank_post_modeset(dev, pipe);
3683                 return -EINVAL;
3684         }
3685
3686         /* Ensure that the cursor is valid for the new mode before changing... */
3687         intel_crtc_update_cursor(crtc);
3688
3689         if (is_lvds && dev_priv->lvds_downclock_avail) {
3690                 has_reduced_clock = limit->find_pll(limit, crtc,
3691                                                             dev_priv->lvds_downclock,
3692                                                             refclk,
3693                                                             &reduced_clock);
3694                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3695                         /*
3696                          * If the different P is found, it means that we can't
3697                          * switch the display clock by using the FP0/FP1.
3698                          * In such case we will disable the LVDS downclock
3699                          * feature.
3700                          */
3701                         DRM_DEBUG_KMS("Different P is found for "
3702                                                 "LVDS clock/downclock\n");
3703                         has_reduced_clock = 0;
3704                 }
3705         }
3706         /* SDVO TV has fixed PLL values depend on its clock range,
3707            this mirrors vbios setting. */
3708         if (is_sdvo && is_tv) {
3709                 if (adjusted_mode->clock >= 100000
3710                                 && adjusted_mode->clock < 140500) {
3711                         clock.p1 = 2;
3712                         clock.p2 = 10;
3713                         clock.n = 3;
3714                         clock.m1 = 16;
3715                         clock.m2 = 8;
3716                 } else if (adjusted_mode->clock >= 140500
3717                                 && adjusted_mode->clock <= 200000) {
3718                         clock.p1 = 1;
3719                         clock.p2 = 10;
3720                         clock.n = 6;
3721                         clock.m1 = 12;
3722                         clock.m2 = 8;
3723                 }
3724         }
3725
3726         /* FDI link */
3727         if (HAS_PCH_SPLIT(dev)) {
3728                 int lane = 0, link_bw, bpp;
3729                 /* eDP doesn't require FDI link, so just set DP M/N
3730                    according to current link config */
3731                 if (is_edp) {
3732                         target_clock = mode->clock;
3733                         intel_edp_link_config(intel_encoder,
3734                                         &lane, &link_bw);
3735                 } else {
3736                         /* DP over FDI requires target mode clock
3737                            instead of link clock */
3738                         if (is_dp)
3739                                 target_clock = mode->clock;
3740                         else
3741                                 target_clock = adjusted_mode->clock;
3742                         link_bw = 270000;
3743                 }
3744
3745                 /* determine panel color depth */
3746                 temp = I915_READ(pipeconf_reg);
3747                 temp &= ~PIPE_BPC_MASK;
3748                 if (is_lvds) {
3749                         int lvds_reg = I915_READ(PCH_LVDS);
3750                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3751                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3752                                 temp |= PIPE_8BPC;
3753                         else
3754                                 temp |= PIPE_6BPC;
3755                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3756                         switch (dev_priv->edp_bpp/3) {
3757                         case 8:
3758                                 temp |= PIPE_8BPC;
3759                                 break;
3760                         case 10:
3761                                 temp |= PIPE_10BPC;
3762                                 break;
3763                         case 6:
3764                                 temp |= PIPE_6BPC;
3765                                 break;
3766                         case 12:
3767                                 temp |= PIPE_12BPC;
3768                                 break;
3769                         }
3770                 } else
3771                         temp |= PIPE_8BPC;
3772                 I915_WRITE(pipeconf_reg, temp);
3773                 I915_READ(pipeconf_reg);
3774
3775                 switch (temp & PIPE_BPC_MASK) {
3776                 case PIPE_8BPC:
3777                         bpp = 24;
3778                         break;
3779                 case PIPE_10BPC:
3780                         bpp = 30;
3781                         break;
3782                 case PIPE_6BPC:
3783                         bpp = 18;
3784                         break;
3785                 case PIPE_12BPC:
3786                         bpp = 36;
3787                         break;
3788                 default:
3789                         DRM_ERROR("unknown pipe bpc value\n");
3790                         bpp = 24;
3791                 }
3792
3793                 if (!lane) {
3794                         /*
3795                          * Account for spread spectrum to avoid
3796                          * oversubscribing the link. Max center spread
3797                          * is 2.5%; use 5% for safety's sake.
3798                          */
3799                         u32 bps = target_clock * bpp * 21 / 20;
3800                         lane = bps / (link_bw * 8) + 1;
3801                 }
3802
3803                 intel_crtc->fdi_lanes = lane;
3804
3805                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3806         }
3807
3808         /* Ironlake: try to setup display ref clock before DPLL
3809          * enabling. This is only under driver's control after
3810          * PCH B stepping, previous chipset stepping should be
3811          * ignoring this setting.
3812          */
3813         if (HAS_PCH_SPLIT(dev)) {
3814                 temp = I915_READ(PCH_DREF_CONTROL);
3815                 /* Always enable nonspread source */
3816                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3817                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3818                 I915_WRITE(PCH_DREF_CONTROL, temp);
3819                 POSTING_READ(PCH_DREF_CONTROL);
3820
3821                 temp &= ~DREF_SSC_SOURCE_MASK;
3822                 temp |= DREF_SSC_SOURCE_ENABLE;
3823                 I915_WRITE(PCH_DREF_CONTROL, temp);
3824                 POSTING_READ(PCH_DREF_CONTROL);
3825
3826                 udelay(200);
3827
3828                 if (is_edp) {
3829                         if (dev_priv->lvds_use_ssc) {
3830                                 temp |= DREF_SSC1_ENABLE;
3831                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3832                                 POSTING_READ(PCH_DREF_CONTROL);
3833
3834                                 udelay(200);
3835
3836                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3837                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3838                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3839                                 POSTING_READ(PCH_DREF_CONTROL);
3840                         } else {
3841                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3842                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3843                                 POSTING_READ(PCH_DREF_CONTROL);
3844                         }
3845                 }
3846         }
3847
3848         if (IS_PINEVIEW(dev)) {
3849                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3850                 if (has_reduced_clock)
3851                         fp2 = (1 << reduced_clock.n) << 16 |
3852                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3853         } else {
3854                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3855                 if (has_reduced_clock)
3856                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3857                                 reduced_clock.m2;
3858         }
3859
3860         if (!HAS_PCH_SPLIT(dev))
3861                 dpll = DPLL_VGA_MODE_DIS;
3862
3863         if (IS_I9XX(dev)) {
3864                 if (is_lvds)
3865                         dpll |= DPLLB_MODE_LVDS;
3866                 else
3867                         dpll |= DPLLB_MODE_DAC_SERIAL;
3868                 if (is_sdvo) {
3869                         dpll |= DPLL_DVO_HIGH_SPEED;
3870                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3871                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3872                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3873                         else if (HAS_PCH_SPLIT(dev))
3874                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3875                 }
3876                 if (is_dp)
3877                         dpll |= DPLL_DVO_HIGH_SPEED;
3878
3879                 /* compute bitmask from p1 value */
3880                 if (IS_PINEVIEW(dev))
3881                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3882                 else {
3883                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3884                         /* also FPA1 */
3885                         if (HAS_PCH_SPLIT(dev))
3886                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3887                         if (IS_G4X(dev) && has_reduced_clock)
3888                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3889                 }
3890                 switch (clock.p2) {
3891                 case 5:
3892                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3893                         break;
3894                 case 7:
3895                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3896                         break;
3897                 case 10:
3898                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3899                         break;
3900                 case 14:
3901                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3902                         break;
3903                 }
3904                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3905                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3906         } else {
3907                 if (is_lvds) {
3908                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3909                 } else {
3910                         if (clock.p1 == 2)
3911                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3912                         else
3913                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3914                         if (clock.p2 == 4)
3915                                 dpll |= PLL_P2_DIVIDE_BY_4;
3916                 }
3917         }
3918
3919         if (is_sdvo && is_tv)
3920                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3921         else if (is_tv)
3922                 /* XXX: just matching BIOS for now */
3923                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3924                 dpll |= 3;
3925         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3926                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3927         else
3928                 dpll |= PLL_REF_INPUT_DREFCLK;
3929
3930         /* setup pipeconf */
3931         pipeconf = I915_READ(pipeconf_reg);
3932
3933         /* Set up the display plane register */
3934         dspcntr = DISPPLANE_GAMMA_ENABLE;
3935
3936         /* Ironlake's plane is forced to pipe, bit 24 is to
3937            enable color space conversion */
3938         if (!HAS_PCH_SPLIT(dev)) {
3939                 if (pipe == 0)
3940                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3941                 else
3942                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3943         }
3944
3945         if (pipe == 0 && !IS_I965G(dev)) {
3946                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3947                  * core speed.
3948                  *
3949                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3950                  * pipe == 0 check?
3951                  */
3952                 if (mode->clock >
3953                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3954                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3955                 else
3956                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3957         }
3958
3959         dspcntr |= DISPLAY_PLANE_ENABLE;
3960         pipeconf |= PIPEACONF_ENABLE;
3961         dpll |= DPLL_VCO_ENABLE;
3962
3963
3964         /* Disable the panel fitter if it was on our pipe */
3965         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3966                 I915_WRITE(PFIT_CONTROL, 0);
3967
3968         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3969         drm_mode_debug_printmodeline(mode);
3970
3971         /* assign to Ironlake registers */
3972         if (HAS_PCH_SPLIT(dev)) {
3973                 fp_reg = pch_fp_reg;
3974                 dpll_reg = pch_dpll_reg;
3975         }
3976
3977         if (is_edp) {
3978                 ironlake_disable_pll_edp(crtc);
3979         } else if ((dpll & DPLL_VCO_ENABLE)) {
3980                 I915_WRITE(fp_reg, fp);
3981                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3982                 I915_READ(dpll_reg);
3983                 udelay(150);
3984         }
3985
3986         /* enable transcoder DPLL */
3987         if (HAS_PCH_CPT(dev)) {
3988                 temp = I915_READ(PCH_DPLL_SEL);
3989                 if (trans_dpll_sel == 0)
3990                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3991                 else
3992                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3993                 I915_WRITE(PCH_DPLL_SEL, temp);
3994                 I915_READ(PCH_DPLL_SEL);
3995                 udelay(150);
3996         }
3997
3998         if (HAS_PCH_SPLIT(dev)) {
3999                 pipeconf &= ~PIPE_ENABLE_DITHER;
4000                 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
4001         }
4002
4003         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4004          * This is an exception to the general rule that mode_set doesn't turn
4005          * things on.
4006          */
4007         if (is_lvds) {
4008                 u32 lvds;
4009
4010                 if (HAS_PCH_SPLIT(dev))
4011                         lvds_reg = PCH_LVDS;
4012
4013                 lvds = I915_READ(lvds_reg);
4014                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4015                 if (pipe == 1) {
4016                         if (HAS_PCH_CPT(dev))
4017                                 lvds |= PORT_TRANS_B_SEL_CPT;
4018                         else
4019                                 lvds |= LVDS_PIPEB_SELECT;
4020                 } else {
4021                         if (HAS_PCH_CPT(dev))
4022                                 lvds &= ~PORT_TRANS_SEL_MASK;
4023                         else
4024                                 lvds &= ~LVDS_PIPEB_SELECT;
4025                 }
4026                 /* set the corresponsding LVDS_BORDER bit */
4027                 lvds |= dev_priv->lvds_border_bits;
4028                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4029                  * set the DPLLs for dual-channel mode or not.
4030                  */
4031                 if (clock.p2 == 7)
4032                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4033                 else
4034                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4035
4036                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4037                  * appropriately here, but we need to look more thoroughly into how
4038                  * panels behave in the two modes.
4039                  */
4040                 /* set the dithering flag */
4041                 if (IS_I965G(dev)) {
4042                         if (dev_priv->lvds_dither) {
4043                                 if (HAS_PCH_SPLIT(dev)) {
4044                                         pipeconf |= PIPE_ENABLE_DITHER;
4045                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
4046                                 } else
4047                                         lvds |= LVDS_ENABLE_DITHER;
4048                         } else {
4049                                 if (!HAS_PCH_SPLIT(dev)) {
4050                                         lvds &= ~LVDS_ENABLE_DITHER;
4051                                 }
4052                         }
4053                 }
4054                 I915_WRITE(lvds_reg, lvds);
4055                 I915_READ(lvds_reg);
4056         }
4057         if (is_dp)
4058                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4059         else if (HAS_PCH_SPLIT(dev)) {
4060                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4061                 if (pipe == 0) {
4062                         I915_WRITE(TRANSA_DATA_M1, 0);
4063                         I915_WRITE(TRANSA_DATA_N1, 0);
4064                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4065                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4066                 } else {
4067                         I915_WRITE(TRANSB_DATA_M1, 0);
4068                         I915_WRITE(TRANSB_DATA_N1, 0);
4069                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4070                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4071                 }
4072         }
4073
4074         if (!is_edp) {
4075                 I915_WRITE(fp_reg, fp);
4076                 I915_WRITE(dpll_reg, dpll);
4077                 I915_READ(dpll_reg);
4078                 /* Wait for the clocks to stabilize. */
4079                 udelay(150);
4080
4081                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4082                         if (is_sdvo) {
4083                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4084                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4085                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4086                         } else
4087                                 I915_WRITE(dpll_md_reg, 0);
4088                 } else {
4089                         /* write it again -- the BIOS does, after all */
4090                         I915_WRITE(dpll_reg, dpll);
4091                 }
4092                 I915_READ(dpll_reg);
4093                 /* Wait for the clocks to stabilize. */
4094                 udelay(150);
4095         }
4096
4097         if (is_lvds && has_reduced_clock && i915_powersave) {
4098                 I915_WRITE(fp_reg + 4, fp2);
4099                 intel_crtc->lowfreq_avail = true;
4100                 if (HAS_PIPE_CXSR(dev)) {
4101                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4102                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4103                 }
4104         } else {
4105                 I915_WRITE(fp_reg + 4, fp);
4106                 intel_crtc->lowfreq_avail = false;
4107                 if (HAS_PIPE_CXSR(dev)) {
4108                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4109                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4110                 }
4111         }
4112
4113         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4114                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4115                 /* the chip adds 2 halflines automatically */
4116                 adjusted_mode->crtc_vdisplay -= 1;
4117                 adjusted_mode->crtc_vtotal -= 1;
4118                 adjusted_mode->crtc_vblank_start -= 1;
4119                 adjusted_mode->crtc_vblank_end -= 1;
4120                 adjusted_mode->crtc_vsync_end -= 1;
4121                 adjusted_mode->crtc_vsync_start -= 1;
4122         } else
4123                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4124
4125         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4126                    ((adjusted_mode->crtc_htotal - 1) << 16));
4127         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4128                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4129         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4130                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4131         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4132                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4133         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4134                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4135         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4136                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4137         /* pipesrc and dspsize control the size that is scaled from, which should
4138          * always be the user's requested size.
4139          */
4140         if (!HAS_PCH_SPLIT(dev)) {
4141                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4142                                 (mode->hdisplay - 1));
4143                 I915_WRITE(dsppos_reg, 0);
4144         }
4145         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4146
4147         if (HAS_PCH_SPLIT(dev)) {
4148                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4149                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4150                 I915_WRITE(link_m1_reg, m_n.link_m);
4151                 I915_WRITE(link_n1_reg, m_n.link_n);
4152
4153                 if (is_edp) {
4154                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4155                 } else {
4156                         /* enable FDI RX PLL too */
4157                         temp = I915_READ(fdi_rx_reg);
4158                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4159                         I915_READ(fdi_rx_reg);
4160                         udelay(200);
4161
4162                         /* enable FDI TX PLL too */
4163                         temp = I915_READ(fdi_tx_reg);
4164                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4165                         I915_READ(fdi_tx_reg);
4166
4167                         /* enable FDI RX PCDCLK */
4168                         temp = I915_READ(fdi_rx_reg);
4169                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4170                         I915_READ(fdi_rx_reg);
4171                         udelay(200);
4172                 }
4173         }
4174
4175         I915_WRITE(pipeconf_reg, pipeconf);
4176         I915_READ(pipeconf_reg);
4177
4178         intel_wait_for_vblank(dev);
4179
4180         if (IS_IRONLAKE(dev)) {
4181                 /* enable address swizzle for tiling buffer */
4182                 temp = I915_READ(DISP_ARB_CTL);
4183                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4184         }
4185
4186         I915_WRITE(dspcntr_reg, dspcntr);
4187
4188         /* Flush the plane changes */
4189         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4190
4191         if ((IS_I965G(dev) || plane == 0))
4192                 intel_update_fbc(crtc, &crtc->mode);
4193
4194         intel_update_watermarks(dev);
4195
4196         drm_vblank_post_modeset(dev, pipe);
4197
4198         return ret;
4199 }
4200
4201 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4202 void intel_crtc_load_lut(struct drm_crtc *crtc)
4203 {
4204         struct drm_device *dev = crtc->dev;
4205         struct drm_i915_private *dev_priv = dev->dev_private;
4206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4208         int i;
4209
4210         /* The clocks have to be on to load the palette. */
4211         if (!crtc->enabled)
4212                 return;
4213
4214         /* use legacy palette for Ironlake */
4215         if (HAS_PCH_SPLIT(dev))
4216                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4217                                                    LGC_PALETTE_B;
4218
4219         for (i = 0; i < 256; i++) {
4220                 I915_WRITE(palreg + 4 * i,
4221                            (intel_crtc->lut_r[i] << 16) |
4222                            (intel_crtc->lut_g[i] << 8) |
4223                            intel_crtc->lut_b[i]);
4224         }
4225 }
4226
4227 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4228 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         int pipe = intel_crtc->pipe;
4234         int x = intel_crtc->cursor_x;
4235         int y = intel_crtc->cursor_y;
4236         uint32_t base, pos;
4237         bool visible;
4238
4239         pos = 0;
4240
4241         if (intel_crtc->cursor_on && crtc->fb) {
4242                 base = intel_crtc->cursor_addr;
4243                 if (x > (int) crtc->fb->width)
4244                         base = 0;
4245
4246                 if (y > (int) crtc->fb->height)
4247                         base = 0;
4248         } else
4249                 base = 0;
4250
4251         if (x < 0) {
4252                 if (x + intel_crtc->cursor_width < 0)
4253                         base = 0;
4254
4255                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4256                 x = -x;
4257         }
4258         pos |= x << CURSOR_X_SHIFT;
4259
4260         if (y < 0) {
4261                 if (y + intel_crtc->cursor_height < 0)
4262                         base = 0;
4263
4264                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4265                 y = -y;
4266         }
4267         pos |= y << CURSOR_Y_SHIFT;
4268
4269         visible = base != 0;
4270         if (!visible && !intel_crtc->cursor_visble)
4271                 return;
4272
4273         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4274         if (intel_crtc->cursor_visble != visible) {
4275                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4276                 if (base) {
4277                         /* Hooray for CUR*CNTR differences */
4278                         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4279                                 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4280                                 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4281                                 cntl |= pipe << 28; /* Connect to correct pipe */
4282                         } else {
4283                                 cntl &= ~(CURSOR_FORMAT_MASK);
4284                                 cntl |= CURSOR_ENABLE;
4285                                 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4286                         }
4287                 } else {
4288                         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4289                                 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4290                                 cntl |= CURSOR_MODE_DISABLE;
4291                         } else {
4292                                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4293                         }
4294                 }
4295                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4296
4297                 intel_crtc->cursor_visble = visible;
4298         }
4299         /* and commit changes on next vblank */
4300         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4301
4302         if (visible)
4303                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4304 }
4305
4306 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4307                                  struct drm_file *file_priv,
4308                                  uint32_t handle,
4309                                  uint32_t width, uint32_t height)
4310 {
4311         struct drm_device *dev = crtc->dev;
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4314         struct drm_gem_object *bo;
4315         struct drm_i915_gem_object *obj_priv;
4316         uint32_t addr;
4317         int ret;
4318
4319         DRM_DEBUG_KMS("\n");
4320
4321         /* if we want to turn off the cursor ignore width and height */
4322         if (!handle) {
4323                 DRM_DEBUG_KMS("cursor off\n");
4324                 addr = 0;
4325                 bo = NULL;
4326                 mutex_lock(&dev->struct_mutex);
4327                 goto finish;
4328         }
4329
4330         /* Currently we only support 64x64 cursors */
4331         if (width != 64 || height != 64) {
4332                 DRM_ERROR("we currently only support 64x64 cursors\n");
4333                 return -EINVAL;
4334         }
4335
4336         bo = drm_gem_object_lookup(dev, file_priv, handle);
4337         if (!bo)
4338                 return -ENOENT;
4339
4340         obj_priv = to_intel_bo(bo);
4341
4342         if (bo->size < width * height * 4) {
4343                 DRM_ERROR("buffer is to small\n");
4344                 ret = -ENOMEM;
4345                 goto fail;
4346         }
4347
4348         /* we only need to pin inside GTT if cursor is non-phy */
4349         mutex_lock(&dev->struct_mutex);
4350         if (!dev_priv->info->cursor_needs_physical) {
4351                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4352                 if (ret) {
4353                         DRM_ERROR("failed to pin cursor bo\n");
4354                         goto fail_locked;
4355                 }
4356
4357                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4358                 if (ret) {
4359                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4360                         goto fail_unpin;
4361                 }
4362
4363                 addr = obj_priv->gtt_offset;
4364         } else {
4365                 ret = i915_gem_attach_phys_object(dev, bo,
4366                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4367                 if (ret) {
4368                         DRM_ERROR("failed to attach phys object\n");
4369                         goto fail_locked;
4370                 }
4371                 addr = obj_priv->phys_obj->handle->busaddr;
4372         }
4373
4374         if (!IS_I9XX(dev))
4375                 I915_WRITE(CURSIZE, (height << 12) | width);
4376
4377  finish:
4378         if (intel_crtc->cursor_bo) {
4379                 if (dev_priv->info->cursor_needs_physical) {
4380                         if (intel_crtc->cursor_bo != bo)
4381                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4382                 } else
4383                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4384                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4385         }
4386
4387         mutex_unlock(&dev->struct_mutex);
4388
4389         intel_crtc->cursor_addr = addr;
4390         intel_crtc->cursor_bo = bo;
4391         intel_crtc->cursor_width = width;
4392         intel_crtc->cursor_height = height;
4393
4394         intel_crtc_update_cursor(crtc);
4395
4396         return 0;
4397 fail_unpin:
4398         i915_gem_object_unpin(bo);
4399 fail_locked:
4400         mutex_unlock(&dev->struct_mutex);
4401 fail:
4402         drm_gem_object_unreference_unlocked(bo);
4403         return ret;
4404 }
4405
4406 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4407 {
4408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4409
4410         intel_crtc->cursor_x = x;
4411         intel_crtc->cursor_y = y;
4412
4413         intel_crtc_update_cursor(crtc);
4414
4415         return 0;
4416 }
4417
4418 /** Sets the color ramps on behalf of RandR */
4419 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4420                                  u16 blue, int regno)
4421 {
4422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423
4424         intel_crtc->lut_r[regno] = red >> 8;
4425         intel_crtc->lut_g[regno] = green >> 8;
4426         intel_crtc->lut_b[regno] = blue >> 8;
4427 }
4428
4429 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4430                              u16 *blue, int regno)
4431 {
4432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4433
4434         *red = intel_crtc->lut_r[regno] << 8;
4435         *green = intel_crtc->lut_g[regno] << 8;
4436         *blue = intel_crtc->lut_b[regno] << 8;
4437 }
4438
4439 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4440                                  u16 *blue, uint32_t size)
4441 {
4442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4443         int i;
4444
4445         if (size != 256)
4446                 return;
4447
4448         for (i = 0; i < 256; i++) {
4449                 intel_crtc->lut_r[i] = red[i] >> 8;
4450                 intel_crtc->lut_g[i] = green[i] >> 8;
4451                 intel_crtc->lut_b[i] = blue[i] >> 8;
4452         }
4453
4454         intel_crtc_load_lut(crtc);
4455 }
4456
4457 /**
4458  * Get a pipe with a simple mode set on it for doing load-based monitor
4459  * detection.
4460  *
4461  * It will be up to the load-detect code to adjust the pipe as appropriate for
4462  * its requirements.  The pipe will be connected to no other encoders.
4463  *
4464  * Currently this code will only succeed if there is a pipe with no encoders
4465  * configured for it.  In the future, it could choose to temporarily disable
4466  * some outputs to free up a pipe for its use.
4467  *
4468  * \return crtc, or NULL if no pipes are available.
4469  */
4470
4471 /* VESA 640x480x72Hz mode to set on the pipe */
4472 static struct drm_display_mode load_detect_mode = {
4473         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4474                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4475 };
4476
4477 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4478                                             struct drm_connector *connector,
4479                                             struct drm_display_mode *mode,
4480                                             int *dpms_mode)
4481 {
4482         struct intel_crtc *intel_crtc;
4483         struct drm_crtc *possible_crtc;
4484         struct drm_crtc *supported_crtc =NULL;
4485         struct drm_encoder *encoder = &intel_encoder->enc;
4486         struct drm_crtc *crtc = NULL;
4487         struct drm_device *dev = encoder->dev;
4488         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4489         struct drm_crtc_helper_funcs *crtc_funcs;
4490         int i = -1;
4491
4492         /*
4493          * Algorithm gets a little messy:
4494          *   - if the connector already has an assigned crtc, use it (but make
4495          *     sure it's on first)
4496          *   - try to find the first unused crtc that can drive this connector,
4497          *     and use that if we find one
4498          *   - if there are no unused crtcs available, try to use the first
4499          *     one we found that supports the connector
4500          */
4501
4502         /* See if we already have a CRTC for this connector */
4503         if (encoder->crtc) {
4504                 crtc = encoder->crtc;
4505                 /* Make sure the crtc and connector are running */
4506                 intel_crtc = to_intel_crtc(crtc);
4507                 *dpms_mode = intel_crtc->dpms_mode;
4508                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4509                         crtc_funcs = crtc->helper_private;
4510                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4511                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4512                 }
4513                 return crtc;
4514         }
4515
4516         /* Find an unused one (if possible) */
4517         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4518                 i++;
4519                 if (!(encoder->possible_crtcs & (1 << i)))
4520                         continue;
4521                 if (!possible_crtc->enabled) {
4522                         crtc = possible_crtc;
4523                         break;
4524                 }
4525                 if (!supported_crtc)
4526                         supported_crtc = possible_crtc;
4527         }
4528
4529         /*
4530          * If we didn't find an unused CRTC, don't use any.
4531          */
4532         if (!crtc) {
4533                 return NULL;
4534         }
4535
4536         encoder->crtc = crtc;
4537         connector->encoder = encoder;
4538         intel_encoder->load_detect_temp = true;
4539
4540         intel_crtc = to_intel_crtc(crtc);
4541         *dpms_mode = intel_crtc->dpms_mode;
4542
4543         if (!crtc->enabled) {
4544                 if (!mode)
4545                         mode = &load_detect_mode;
4546                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4547         } else {
4548                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4549                         crtc_funcs = crtc->helper_private;
4550                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4551                 }
4552
4553                 /* Add this connector to the crtc */
4554                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4555                 encoder_funcs->commit(encoder);
4556         }
4557         /* let the connector get through one full cycle before testing */
4558         intel_wait_for_vblank(dev);
4559
4560         return crtc;
4561 }
4562
4563 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4564                                     struct drm_connector *connector, int dpms_mode)
4565 {
4566         struct drm_encoder *encoder = &intel_encoder->enc;
4567         struct drm_device *dev = encoder->dev;
4568         struct drm_crtc *crtc = encoder->crtc;
4569         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4570         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4571
4572         if (intel_encoder->load_detect_temp) {
4573                 encoder->crtc = NULL;
4574                 connector->encoder = NULL;
4575                 intel_encoder->load_detect_temp = false;
4576                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4577                 drm_helper_disable_unused_functions(dev);
4578         }
4579
4580         /* Switch crtc and encoder back off if necessary */
4581         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4582                 if (encoder->crtc == crtc)
4583                         encoder_funcs->dpms(encoder, dpms_mode);
4584                 crtc_funcs->dpms(crtc, dpms_mode);
4585         }
4586 }
4587
4588 /* Returns the clock of the currently programmed mode of the given pipe. */
4589 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4590 {
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593         int pipe = intel_crtc->pipe;
4594         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4595         u32 fp;
4596         intel_clock_t clock;
4597
4598         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4599                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4600         else
4601                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4602
4603         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4604         if (IS_PINEVIEW(dev)) {
4605                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4606                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4607         } else {
4608                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4609                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4610         }
4611
4612         if (IS_I9XX(dev)) {
4613                 if (IS_PINEVIEW(dev))
4614                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4615                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4616                 else
4617                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4618                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4619
4620                 switch (dpll & DPLL_MODE_MASK) {
4621                 case DPLLB_MODE_DAC_SERIAL:
4622                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4623                                 5 : 10;
4624                         break;
4625                 case DPLLB_MODE_LVDS:
4626                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4627                                 7 : 14;
4628                         break;
4629                 default:
4630                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4631                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4632                         return 0;
4633                 }
4634
4635                 /* XXX: Handle the 100Mhz refclk */
4636                 intel_clock(dev, 96000, &clock);
4637         } else {
4638                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4639
4640                 if (is_lvds) {
4641                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4642                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4643                         clock.p2 = 14;
4644
4645                         if ((dpll & PLL_REF_INPUT_MASK) ==
4646                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4647                                 /* XXX: might not be 66MHz */
4648                                 intel_clock(dev, 66000, &clock);
4649                         } else
4650                                 intel_clock(dev, 48000, &clock);
4651                 } else {
4652                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4653                                 clock.p1 = 2;
4654                         else {
4655                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4656                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4657                         }
4658                         if (dpll & PLL_P2_DIVIDE_BY_4)
4659                                 clock.p2 = 4;
4660                         else
4661                                 clock.p2 = 2;
4662
4663                         intel_clock(dev, 48000, &clock);
4664                 }
4665         }
4666
4667         /* XXX: It would be nice to validate the clocks, but we can't reuse
4668          * i830PllIsValid() because it relies on the xf86_config connector
4669          * configuration being accurate, which it isn't necessarily.
4670          */
4671
4672         return clock.dot;
4673 }
4674
4675 /** Returns the currently programmed mode of the given pipe. */
4676 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4677                                              struct drm_crtc *crtc)
4678 {
4679         struct drm_i915_private *dev_priv = dev->dev_private;
4680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4681         int pipe = intel_crtc->pipe;
4682         struct drm_display_mode *mode;
4683         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4684         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4685         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4686         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4687
4688         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4689         if (!mode)
4690                 return NULL;
4691
4692         mode->clock = intel_crtc_clock_get(dev, crtc);
4693         mode->hdisplay = (htot & 0xffff) + 1;
4694         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4695         mode->hsync_start = (hsync & 0xffff) + 1;
4696         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4697         mode->vdisplay = (vtot & 0xffff) + 1;
4698         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4699         mode->vsync_start = (vsync & 0xffff) + 1;
4700         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4701
4702         drm_mode_set_name(mode);
4703         drm_mode_set_crtcinfo(mode, 0);
4704
4705         return mode;
4706 }
4707
4708 #define GPU_IDLE_TIMEOUT 500 /* ms */
4709
4710 /* When this timer fires, we've been idle for awhile */
4711 static void intel_gpu_idle_timer(unsigned long arg)
4712 {
4713         struct drm_device *dev = (struct drm_device *)arg;
4714         drm_i915_private_t *dev_priv = dev->dev_private;
4715
4716         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4717
4718         dev_priv->busy = false;
4719
4720         queue_work(dev_priv->wq, &dev_priv->idle_work);
4721 }
4722
4723 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4724
4725 static void intel_crtc_idle_timer(unsigned long arg)
4726 {
4727         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4728         struct drm_crtc *crtc = &intel_crtc->base;
4729         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4730
4731         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4732
4733         intel_crtc->busy = false;
4734
4735         queue_work(dev_priv->wq, &dev_priv->idle_work);
4736 }
4737
4738 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4739 {
4740         struct drm_device *dev = crtc->dev;
4741         drm_i915_private_t *dev_priv = dev->dev_private;
4742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743         int pipe = intel_crtc->pipe;
4744         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4745         int dpll = I915_READ(dpll_reg);
4746
4747         if (HAS_PCH_SPLIT(dev))
4748                 return;
4749
4750         if (!dev_priv->lvds_downclock_avail)
4751                 return;
4752
4753         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4754                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4755
4756                 /* Unlock panel regs */
4757                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4758                            PANEL_UNLOCK_REGS);
4759
4760                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4761                 I915_WRITE(dpll_reg, dpll);
4762                 dpll = I915_READ(dpll_reg);
4763                 intel_wait_for_vblank(dev);
4764                 dpll = I915_READ(dpll_reg);
4765                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4766                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4767
4768                 /* ...and lock them again */
4769                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4770         }
4771
4772         /* Schedule downclock */
4773         if (schedule)
4774                 mod_timer(&intel_crtc->idle_timer, jiffies +
4775                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4776 }
4777
4778 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4779 {
4780         struct drm_device *dev = crtc->dev;
4781         drm_i915_private_t *dev_priv = dev->dev_private;
4782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4783         int pipe = intel_crtc->pipe;
4784         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4785         int dpll = I915_READ(dpll_reg);
4786
4787         if (HAS_PCH_SPLIT(dev))
4788                 return;
4789
4790         if (!dev_priv->lvds_downclock_avail)
4791                 return;
4792
4793         /*
4794          * Since this is called by a timer, we should never get here in
4795          * the manual case.
4796          */
4797         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4798                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4799
4800                 /* Unlock panel regs */
4801                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4802                            PANEL_UNLOCK_REGS);
4803
4804                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4805                 I915_WRITE(dpll_reg, dpll);
4806                 dpll = I915_READ(dpll_reg);
4807                 intel_wait_for_vblank(dev);
4808                 dpll = I915_READ(dpll_reg);
4809                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4810                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4811
4812                 /* ...and lock them again */
4813                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4814         }
4815
4816 }
4817
4818 /**
4819  * intel_idle_update - adjust clocks for idleness
4820  * @work: work struct
4821  *
4822  * Either the GPU or display (or both) went idle.  Check the busy status
4823  * here and adjust the CRTC and GPU clocks as necessary.
4824  */
4825 static void intel_idle_update(struct work_struct *work)
4826 {
4827         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4828                                                     idle_work);
4829         struct drm_device *dev = dev_priv->dev;
4830         struct drm_crtc *crtc;
4831         struct intel_crtc *intel_crtc;
4832         int enabled = 0;
4833
4834         if (!i915_powersave)
4835                 return;
4836
4837         mutex_lock(&dev->struct_mutex);
4838
4839         i915_update_gfx_val(dev_priv);
4840
4841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4842                 /* Skip inactive CRTCs */
4843                 if (!crtc->fb)
4844                         continue;
4845
4846                 enabled++;
4847                 intel_crtc = to_intel_crtc(crtc);
4848                 if (!intel_crtc->busy)
4849                         intel_decrease_pllclock(crtc);
4850         }
4851
4852         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4853                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4854                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4855         }
4856
4857         mutex_unlock(&dev->struct_mutex);
4858 }
4859
4860 /**
4861  * intel_mark_busy - mark the GPU and possibly the display busy
4862  * @dev: drm device
4863  * @obj: object we're operating on
4864  *
4865  * Callers can use this function to indicate that the GPU is busy processing
4866  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4867  * buffer), we'll also mark the display as busy, so we know to increase its
4868  * clock frequency.
4869  */
4870 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4871 {
4872         drm_i915_private_t *dev_priv = dev->dev_private;
4873         struct drm_crtc *crtc = NULL;
4874         struct intel_framebuffer *intel_fb;
4875         struct intel_crtc *intel_crtc;
4876
4877         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4878                 return;
4879
4880         if (!dev_priv->busy) {
4881                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4882                         u32 fw_blc_self;
4883
4884                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4885                         fw_blc_self = I915_READ(FW_BLC_SELF);
4886                         fw_blc_self &= ~FW_BLC_SELF_EN;
4887                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4888                 }
4889                 dev_priv->busy = true;
4890         } else
4891                 mod_timer(&dev_priv->idle_timer, jiffies +
4892                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4893
4894         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4895                 if (!crtc->fb)
4896                         continue;
4897
4898                 intel_crtc = to_intel_crtc(crtc);
4899                 intel_fb = to_intel_framebuffer(crtc->fb);
4900                 if (intel_fb->obj == obj) {
4901                         if (!intel_crtc->busy) {
4902                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4903                                         u32 fw_blc_self;
4904
4905                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4906                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4907                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4908                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4909                                 }
4910                                 /* Non-busy -> busy, upclock */
4911                                 intel_increase_pllclock(crtc, true);
4912                                 intel_crtc->busy = true;
4913                         } else {
4914                                 /* Busy -> busy, put off timer */
4915                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4916                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4917                         }
4918                 }
4919         }
4920 }
4921
4922 static void intel_crtc_destroy(struct drm_crtc *crtc)
4923 {
4924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4925
4926         drm_crtc_cleanup(crtc);
4927         kfree(intel_crtc);
4928 }
4929
4930 struct intel_unpin_work {
4931         struct work_struct work;
4932         struct drm_device *dev;
4933         struct drm_gem_object *old_fb_obj;
4934         struct drm_gem_object *pending_flip_obj;
4935         struct drm_pending_vblank_event *event;
4936         int pending;
4937 };
4938
4939 static void intel_unpin_work_fn(struct work_struct *__work)
4940 {
4941         struct intel_unpin_work *work =
4942                 container_of(__work, struct intel_unpin_work, work);
4943
4944         mutex_lock(&work->dev->struct_mutex);
4945         i915_gem_object_unpin(work->old_fb_obj);
4946         drm_gem_object_unreference(work->pending_flip_obj);
4947         drm_gem_object_unreference(work->old_fb_obj);
4948         mutex_unlock(&work->dev->struct_mutex);
4949         kfree(work);
4950 }
4951
4952 static void do_intel_finish_page_flip(struct drm_device *dev,
4953                                       struct drm_crtc *crtc)
4954 {
4955         drm_i915_private_t *dev_priv = dev->dev_private;
4956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4957         struct intel_unpin_work *work;
4958         struct drm_i915_gem_object *obj_priv;
4959         struct drm_pending_vblank_event *e;
4960         struct timeval now;
4961         unsigned long flags;
4962
4963         /* Ignore early vblank irqs */
4964         if (intel_crtc == NULL)
4965                 return;
4966
4967         spin_lock_irqsave(&dev->event_lock, flags);
4968         work = intel_crtc->unpin_work;
4969         if (work == NULL || !work->pending) {
4970                 spin_unlock_irqrestore(&dev->event_lock, flags);
4971                 return;
4972         }
4973
4974         intel_crtc->unpin_work = NULL;
4975         drm_vblank_put(dev, intel_crtc->pipe);
4976
4977         if (work->event) {
4978                 e = work->event;
4979                 do_gettimeofday(&now);
4980                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4981                 e->event.tv_sec = now.tv_sec;
4982                 e->event.tv_usec = now.tv_usec;
4983                 list_add_tail(&e->base.link,
4984                               &e->base.file_priv->event_list);
4985                 wake_up_interruptible(&e->base.file_priv->event_wait);
4986         }
4987
4988         spin_unlock_irqrestore(&dev->event_lock, flags);
4989
4990         obj_priv = to_intel_bo(work->pending_flip_obj);
4991
4992         /* Initial scanout buffer will have a 0 pending flip count */
4993         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4994             atomic_dec_and_test(&obj_priv->pending_flip))
4995                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4996         schedule_work(&work->work);
4997
4998         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4999 }
5000
5001 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5002 {
5003         drm_i915_private_t *dev_priv = dev->dev_private;
5004         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5005
5006         do_intel_finish_page_flip(dev, crtc);
5007 }
5008
5009 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5010 {
5011         drm_i915_private_t *dev_priv = dev->dev_private;
5012         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5013
5014         do_intel_finish_page_flip(dev, crtc);
5015 }
5016
5017 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5018 {
5019         drm_i915_private_t *dev_priv = dev->dev_private;
5020         struct intel_crtc *intel_crtc =
5021                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5022         unsigned long flags;
5023
5024         spin_lock_irqsave(&dev->event_lock, flags);
5025         if (intel_crtc->unpin_work) {
5026                 intel_crtc->unpin_work->pending = 1;
5027         } else {
5028                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5029         }
5030         spin_unlock_irqrestore(&dev->event_lock, flags);
5031 }
5032
5033 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5034                                 struct drm_framebuffer *fb,
5035                                 struct drm_pending_vblank_event *event)
5036 {
5037         struct drm_device *dev = crtc->dev;
5038         struct drm_i915_private *dev_priv = dev->dev_private;
5039         struct intel_framebuffer *intel_fb;
5040         struct drm_i915_gem_object *obj_priv;
5041         struct drm_gem_object *obj;
5042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5043         struct intel_unpin_work *work;
5044         unsigned long flags, offset;
5045         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5046         int ret, pipesrc;
5047         u32 flip_mask;
5048
5049         work = kzalloc(sizeof *work, GFP_KERNEL);
5050         if (work == NULL)
5051                 return -ENOMEM;
5052
5053         work->event = event;
5054         work->dev = crtc->dev;
5055         intel_fb = to_intel_framebuffer(crtc->fb);
5056         work->old_fb_obj = intel_fb->obj;
5057         INIT_WORK(&work->work, intel_unpin_work_fn);
5058
5059         /* We borrow the event spin lock for protecting unpin_work */
5060         spin_lock_irqsave(&dev->event_lock, flags);
5061         if (intel_crtc->unpin_work) {
5062                 spin_unlock_irqrestore(&dev->event_lock, flags);
5063                 kfree(work);
5064
5065                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5066                 return -EBUSY;
5067         }
5068         intel_crtc->unpin_work = work;
5069         spin_unlock_irqrestore(&dev->event_lock, flags);
5070
5071         intel_fb = to_intel_framebuffer(fb);
5072         obj = intel_fb->obj;
5073
5074         mutex_lock(&dev->struct_mutex);
5075         ret = intel_pin_and_fence_fb_obj(dev, obj);
5076         if (ret)
5077                 goto cleanup_work;
5078
5079         /* Reference the objects for the scheduled work. */
5080         drm_gem_object_reference(work->old_fb_obj);
5081         drm_gem_object_reference(obj);
5082
5083         crtc->fb = fb;
5084         ret = i915_gem_object_flush_write_domain(obj);
5085         if (ret)
5086                 goto cleanup_objs;
5087
5088         ret = drm_vblank_get(dev, intel_crtc->pipe);
5089         if (ret)
5090                 goto cleanup_objs;
5091
5092         obj_priv = to_intel_bo(obj);
5093         atomic_inc(&obj_priv->pending_flip);
5094         work->pending_flip_obj = obj;
5095
5096         if (intel_crtc->plane)
5097                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5098         else
5099                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5100
5101         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5102                 BEGIN_LP_RING(2);
5103                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5104                 OUT_RING(0);
5105                 ADVANCE_LP_RING();
5106         }
5107
5108         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5109         offset = obj_priv->gtt_offset;
5110         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5111
5112         BEGIN_LP_RING(4);
5113         if (IS_I965G(dev)) {
5114                 OUT_RING(MI_DISPLAY_FLIP |
5115                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5116                 OUT_RING(fb->pitch);
5117                 OUT_RING(offset | obj_priv->tiling_mode);
5118                 pipesrc = I915_READ(pipesrc_reg);
5119                 OUT_RING(pipesrc & 0x0fff0fff);
5120         } else if (IS_GEN3(dev)) {
5121                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5122                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5123                 OUT_RING(fb->pitch);
5124                 OUT_RING(offset);
5125                 OUT_RING(MI_NOOP);
5126         } else {
5127                 OUT_RING(MI_DISPLAY_FLIP |
5128                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5129                 OUT_RING(fb->pitch);
5130                 OUT_RING(offset);
5131                 OUT_RING(MI_NOOP);
5132         }
5133         ADVANCE_LP_RING();
5134
5135         mutex_unlock(&dev->struct_mutex);
5136
5137         trace_i915_flip_request(intel_crtc->plane, obj);
5138
5139         return 0;
5140
5141 cleanup_objs:
5142         drm_gem_object_unreference(work->old_fb_obj);
5143         drm_gem_object_unreference(obj);
5144 cleanup_work:
5145         mutex_unlock(&dev->struct_mutex);
5146
5147         spin_lock_irqsave(&dev->event_lock, flags);
5148         intel_crtc->unpin_work = NULL;
5149         spin_unlock_irqrestore(&dev->event_lock, flags);
5150
5151         kfree(work);
5152
5153         return ret;
5154 }
5155
5156 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5157         .dpms = intel_crtc_dpms,
5158         .mode_fixup = intel_crtc_mode_fixup,
5159         .mode_set = intel_crtc_mode_set,
5160         .mode_set_base = intel_pipe_set_base,
5161         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5162         .prepare = intel_crtc_prepare,
5163         .commit = intel_crtc_commit,
5164         .load_lut = intel_crtc_load_lut,
5165 };
5166
5167 static const struct drm_crtc_funcs intel_crtc_funcs = {
5168         .cursor_set = intel_crtc_cursor_set,
5169         .cursor_move = intel_crtc_cursor_move,
5170         .gamma_set = intel_crtc_gamma_set,
5171         .set_config = drm_crtc_helper_set_config,
5172         .destroy = intel_crtc_destroy,
5173         .page_flip = intel_crtc_page_flip,
5174 };
5175
5176
5177 static void intel_crtc_init(struct drm_device *dev, int pipe)
5178 {
5179         drm_i915_private_t *dev_priv = dev->dev_private;
5180         struct intel_crtc *intel_crtc;
5181         int i;
5182
5183         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5184         if (intel_crtc == NULL)
5185                 return;
5186
5187         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5188
5189         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5190         intel_crtc->pipe = pipe;
5191         intel_crtc->plane = pipe;
5192         for (i = 0; i < 256; i++) {
5193                 intel_crtc->lut_r[i] = i;
5194                 intel_crtc->lut_g[i] = i;
5195                 intel_crtc->lut_b[i] = i;
5196         }
5197
5198         /* Swap pipes & planes for FBC on pre-965 */
5199         intel_crtc->pipe = pipe;
5200         intel_crtc->plane = pipe;
5201         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5202                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5203                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5204         }
5205
5206         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5207                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5208         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5209         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5210
5211         intel_crtc->cursor_addr = 0;
5212         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5213         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5214
5215         intel_crtc->busy = false;
5216
5217         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5218                     (unsigned long)intel_crtc);
5219 }
5220
5221 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5222                                 struct drm_file *file_priv)
5223 {
5224         drm_i915_private_t *dev_priv = dev->dev_private;
5225         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5226         struct drm_mode_object *drmmode_obj;
5227         struct intel_crtc *crtc;
5228
5229         if (!dev_priv) {
5230                 DRM_ERROR("called with no initialization\n");
5231                 return -EINVAL;
5232         }
5233
5234         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5235                         DRM_MODE_OBJECT_CRTC);
5236
5237         if (!drmmode_obj) {
5238                 DRM_ERROR("no such CRTC id\n");
5239                 return -EINVAL;
5240         }
5241
5242         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5243         pipe_from_crtc_id->pipe = crtc->pipe;
5244
5245         return 0;
5246 }
5247
5248 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5249 {
5250         struct drm_crtc *crtc = NULL;
5251
5252         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5253                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254                 if (intel_crtc->pipe == pipe)
5255                         break;
5256         }
5257         return crtc;
5258 }
5259
5260 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5261 {
5262         int index_mask = 0;
5263         struct drm_encoder *encoder;
5264         int entry = 0;
5265
5266         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5267                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5268                 if (type_mask & intel_encoder->clone_mask)
5269                         index_mask |= (1 << entry);
5270                 entry++;
5271         }
5272         return index_mask;
5273 }
5274
5275
5276 static void intel_setup_outputs(struct drm_device *dev)
5277 {
5278         struct drm_i915_private *dev_priv = dev->dev_private;
5279         struct drm_encoder *encoder;
5280         bool dpd_is_edp = false;
5281
5282         if (IS_MOBILE(dev) && !IS_I830(dev))
5283                 intel_lvds_init(dev);
5284
5285         if (HAS_PCH_SPLIT(dev)) {
5286                 dpd_is_edp = intel_dpd_is_edp(dev);
5287
5288                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5289                         intel_dp_init(dev, DP_A);
5290
5291                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5292                         intel_dp_init(dev, PCH_DP_D);
5293         }
5294
5295         intel_crt_init(dev);
5296
5297         if (HAS_PCH_SPLIT(dev)) {
5298                 int found;
5299
5300                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5301                         /* PCH SDVOB multiplex with HDMIB */
5302                         found = intel_sdvo_init(dev, PCH_SDVOB);
5303                         if (!found)
5304                                 intel_hdmi_init(dev, HDMIB);
5305                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5306                                 intel_dp_init(dev, PCH_DP_B);
5307                 }
5308
5309                 if (I915_READ(HDMIC) & PORT_DETECTED)
5310                         intel_hdmi_init(dev, HDMIC);
5311
5312                 if (I915_READ(HDMID) & PORT_DETECTED)
5313                         intel_hdmi_init(dev, HDMID);
5314
5315                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5316                         intel_dp_init(dev, PCH_DP_C);
5317
5318                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5319                         intel_dp_init(dev, PCH_DP_D);
5320
5321         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5322                 bool found = false;
5323
5324                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5325                         DRM_DEBUG_KMS("probing SDVOB\n");
5326                         found = intel_sdvo_init(dev, SDVOB);
5327                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5328                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5329                                 intel_hdmi_init(dev, SDVOB);
5330                         }
5331
5332                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5333                                 DRM_DEBUG_KMS("probing DP_B\n");
5334                                 intel_dp_init(dev, DP_B);
5335                         }
5336                 }
5337
5338                 /* Before G4X SDVOC doesn't have its own detect register */
5339
5340                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5341                         DRM_DEBUG_KMS("probing SDVOC\n");
5342                         found = intel_sdvo_init(dev, SDVOC);
5343                 }
5344
5345                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5346
5347                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5348                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5349                                 intel_hdmi_init(dev, SDVOC);
5350                         }
5351                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5352                                 DRM_DEBUG_KMS("probing DP_C\n");
5353                                 intel_dp_init(dev, DP_C);
5354                         }
5355                 }
5356
5357                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5358                     (I915_READ(DP_D) & DP_DETECTED)) {
5359                         DRM_DEBUG_KMS("probing DP_D\n");
5360                         intel_dp_init(dev, DP_D);
5361                 }
5362         } else if (IS_GEN2(dev))
5363                 intel_dvo_init(dev);
5364
5365         if (SUPPORTS_TV(dev))
5366                 intel_tv_init(dev);
5367
5368         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5369                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5370
5371                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5372                 encoder->possible_clones = intel_encoder_clones(dev,
5373                                                 intel_encoder->clone_mask);
5374         }
5375 }
5376
5377 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5378 {
5379         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5380
5381         drm_framebuffer_cleanup(fb);
5382         drm_gem_object_unreference_unlocked(intel_fb->obj);
5383
5384         kfree(intel_fb);
5385 }
5386
5387 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5388                                                 struct drm_file *file_priv,
5389                                                 unsigned int *handle)
5390 {
5391         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5392         struct drm_gem_object *object = intel_fb->obj;
5393
5394         return drm_gem_handle_create(file_priv, object, handle);
5395 }
5396
5397 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5398         .destroy = intel_user_framebuffer_destroy,
5399         .create_handle = intel_user_framebuffer_create_handle,
5400 };
5401
5402 int intel_framebuffer_init(struct drm_device *dev,
5403                            struct intel_framebuffer *intel_fb,
5404                            struct drm_mode_fb_cmd *mode_cmd,
5405                            struct drm_gem_object *obj)
5406 {
5407         int ret;
5408
5409         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5410         if (ret) {
5411                 DRM_ERROR("framebuffer init failed %d\n", ret);
5412                 return ret;
5413         }
5414
5415         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5416         intel_fb->obj = obj;
5417         return 0;
5418 }
5419
5420 static struct drm_framebuffer *
5421 intel_user_framebuffer_create(struct drm_device *dev,
5422                               struct drm_file *filp,
5423                               struct drm_mode_fb_cmd *mode_cmd)
5424 {
5425         struct drm_gem_object *obj;
5426         struct intel_framebuffer *intel_fb;
5427         int ret;
5428
5429         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5430         if (!obj)
5431                 return NULL;
5432
5433         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5434         if (!intel_fb)
5435                 return NULL;
5436
5437         ret = intel_framebuffer_init(dev, intel_fb,
5438                                      mode_cmd, obj);
5439         if (ret) {
5440                 drm_gem_object_unreference_unlocked(obj);
5441                 kfree(intel_fb);
5442                 return NULL;
5443         }
5444
5445         return &intel_fb->base;
5446 }
5447
5448 static const struct drm_mode_config_funcs intel_mode_funcs = {
5449         .fb_create = intel_user_framebuffer_create,
5450         .output_poll_changed = intel_fb_output_poll_changed,
5451 };
5452
5453 static struct drm_gem_object *
5454 intel_alloc_power_context(struct drm_device *dev)
5455 {
5456         struct drm_gem_object *pwrctx;
5457         int ret;
5458
5459         pwrctx = i915_gem_alloc_object(dev, 4096);
5460         if (!pwrctx) {
5461                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5462                 return NULL;
5463         }
5464
5465         mutex_lock(&dev->struct_mutex);
5466         ret = i915_gem_object_pin(pwrctx, 4096);
5467         if (ret) {
5468                 DRM_ERROR("failed to pin power context: %d\n", ret);
5469                 goto err_unref;
5470         }
5471
5472         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5473         if (ret) {
5474                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5475                 goto err_unpin;
5476         }
5477         mutex_unlock(&dev->struct_mutex);
5478
5479         return pwrctx;
5480
5481 err_unpin:
5482         i915_gem_object_unpin(pwrctx);
5483 err_unref:
5484         drm_gem_object_unreference(pwrctx);
5485         mutex_unlock(&dev->struct_mutex);
5486         return NULL;
5487 }
5488
5489 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5490 {
5491         struct drm_i915_private *dev_priv = dev->dev_private;
5492         u16 rgvswctl;
5493
5494         rgvswctl = I915_READ16(MEMSWCTL);
5495         if (rgvswctl & MEMCTL_CMD_STS) {
5496                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5497                 return false; /* still busy with another command */
5498         }
5499
5500         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5501                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5502         I915_WRITE16(MEMSWCTL, rgvswctl);
5503         POSTING_READ16(MEMSWCTL);
5504
5505         rgvswctl |= MEMCTL_CMD_STS;
5506         I915_WRITE16(MEMSWCTL, rgvswctl);
5507
5508         return true;
5509 }
5510
5511 void ironlake_enable_drps(struct drm_device *dev)
5512 {
5513         struct drm_i915_private *dev_priv = dev->dev_private;
5514         u32 rgvmodectl = I915_READ(MEMMODECTL);
5515         u8 fmax, fmin, fstart, vstart;
5516         int i = 0;
5517
5518         /* 100ms RC evaluation intervals */
5519         I915_WRITE(RCUPEI, 100000);
5520         I915_WRITE(RCDNEI, 100000);
5521
5522         /* Set max/min thresholds to 90ms and 80ms respectively */
5523         I915_WRITE(RCBMAXAVG, 90000);
5524         I915_WRITE(RCBMINAVG, 80000);
5525
5526         I915_WRITE(MEMIHYST, 1);
5527
5528         /* Set up min, max, and cur for interrupt handling */
5529         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5530         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5531         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5532                 MEMMODE_FSTART_SHIFT;
5533         fstart = fmax;
5534
5535         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5536                 PXVFREQ_PX_SHIFT;
5537
5538         dev_priv->fmax = fstart; /* IPS callback will increase this */
5539         dev_priv->fstart = fstart;
5540
5541         dev_priv->max_delay = fmax;
5542         dev_priv->min_delay = fmin;
5543         dev_priv->cur_delay = fstart;
5544
5545         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5546                          fstart);
5547
5548         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5549
5550         /*
5551          * Interrupts will be enabled in ironlake_irq_postinstall
5552          */
5553
5554         I915_WRITE(VIDSTART, vstart);
5555         POSTING_READ(VIDSTART);
5556
5557         rgvmodectl |= MEMMODE_SWMODE_EN;
5558         I915_WRITE(MEMMODECTL, rgvmodectl);
5559
5560         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5561                 if (i++ > 100) {
5562                         DRM_ERROR("stuck trying to change perf mode\n");
5563                         break;
5564                 }
5565                 msleep(1);
5566         }
5567         msleep(1);
5568
5569         ironlake_set_drps(dev, fstart);
5570
5571         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5572                 I915_READ(0x112e0);
5573         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5574         dev_priv->last_count2 = I915_READ(0x112f4);
5575         getrawmonotonic(&dev_priv->last_time2);
5576 }
5577
5578 void ironlake_disable_drps(struct drm_device *dev)
5579 {
5580         struct drm_i915_private *dev_priv = dev->dev_private;
5581         u16 rgvswctl = I915_READ16(MEMSWCTL);
5582
5583         /* Ack interrupts, disable EFC interrupt */
5584         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5585         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5586         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5587         I915_WRITE(DEIIR, DE_PCU_EVENT);
5588         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5589
5590         /* Go back to the starting frequency */
5591         ironlake_set_drps(dev, dev_priv->fstart);
5592         msleep(1);
5593         rgvswctl |= MEMCTL_CMD_STS;
5594         I915_WRITE(MEMSWCTL, rgvswctl);
5595         msleep(1);
5596
5597 }
5598
5599 static unsigned long intel_pxfreq(u32 vidfreq)
5600 {
5601         unsigned long freq;
5602         int div = (vidfreq & 0x3f0000) >> 16;
5603         int post = (vidfreq & 0x3000) >> 12;
5604         int pre = (vidfreq & 0x7);
5605
5606         if (!pre)
5607                 return 0;
5608
5609         freq = ((div * 133333) / ((1<<post) * pre));
5610
5611         return freq;
5612 }
5613
5614 void intel_init_emon(struct drm_device *dev)
5615 {
5616         struct drm_i915_private *dev_priv = dev->dev_private;
5617         u32 lcfuse;
5618         u8 pxw[16];
5619         int i;
5620
5621         /* Disable to program */
5622         I915_WRITE(ECR, 0);
5623         POSTING_READ(ECR);
5624
5625         /* Program energy weights for various events */
5626         I915_WRITE(SDEW, 0x15040d00);
5627         I915_WRITE(CSIEW0, 0x007f0000);
5628         I915_WRITE(CSIEW1, 0x1e220004);
5629         I915_WRITE(CSIEW2, 0x04000004);
5630
5631         for (i = 0; i < 5; i++)
5632                 I915_WRITE(PEW + (i * 4), 0);
5633         for (i = 0; i < 3; i++)
5634                 I915_WRITE(DEW + (i * 4), 0);
5635
5636         /* Program P-state weights to account for frequency power adjustment */
5637         for (i = 0; i < 16; i++) {
5638                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5639                 unsigned long freq = intel_pxfreq(pxvidfreq);
5640                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5641                         PXVFREQ_PX_SHIFT;
5642                 unsigned long val;
5643
5644                 val = vid * vid;
5645                 val *= (freq / 1000);
5646                 val *= 255;
5647                 val /= (127*127*900);
5648                 if (val > 0xff)
5649                         DRM_ERROR("bad pxval: %ld\n", val);
5650                 pxw[i] = val;
5651         }
5652         /* Render standby states get 0 weight */
5653         pxw[14] = 0;
5654         pxw[15] = 0;
5655
5656         for (i = 0; i < 4; i++) {
5657                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5658                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5659                 I915_WRITE(PXW + (i * 4), val);
5660         }
5661
5662         /* Adjust magic regs to magic values (more experimental results) */
5663         I915_WRITE(OGW0, 0);
5664         I915_WRITE(OGW1, 0);
5665         I915_WRITE(EG0, 0x00007f00);
5666         I915_WRITE(EG1, 0x0000000e);
5667         I915_WRITE(EG2, 0x000e0000);
5668         I915_WRITE(EG3, 0x68000300);
5669         I915_WRITE(EG4, 0x42000000);
5670         I915_WRITE(EG5, 0x00140031);
5671         I915_WRITE(EG6, 0);
5672         I915_WRITE(EG7, 0);
5673
5674         for (i = 0; i < 8; i++)
5675                 I915_WRITE(PXWL + (i * 4), 0);
5676
5677         /* Enable PMON + select events */
5678         I915_WRITE(ECR, 0x80000019);
5679
5680         lcfuse = I915_READ(LCFUSE02);
5681
5682         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5683 }
5684
5685 void intel_init_clock_gating(struct drm_device *dev)
5686 {
5687         struct drm_i915_private *dev_priv = dev->dev_private;
5688
5689         /*
5690          * Disable clock gating reported to work incorrectly according to the
5691          * specs, but enable as much else as we can.
5692          */
5693         if (HAS_PCH_SPLIT(dev)) {
5694                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5695
5696                 if (IS_IRONLAKE(dev)) {
5697                         /* Required for FBC */
5698                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5699                         /* Required for CxSR */
5700                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5701
5702                         I915_WRITE(PCH_3DCGDIS0,
5703                                    MARIUNIT_CLOCK_GATE_DISABLE |
5704                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5705                 }
5706
5707                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5708
5709                 /*
5710                  * According to the spec the following bits should be set in
5711                  * order to enable memory self-refresh
5712                  * The bit 22/21 of 0x42004
5713                  * The bit 5 of 0x42020
5714                  * The bit 15 of 0x45000
5715                  */
5716                 if (IS_IRONLAKE(dev)) {
5717                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5718                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5719                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5720                         I915_WRITE(ILK_DSPCLK_GATE,
5721                                         (I915_READ(ILK_DSPCLK_GATE) |
5722                                                 ILK_DPARB_CLK_GATE));
5723                         I915_WRITE(DISP_ARB_CTL,
5724                                         (I915_READ(DISP_ARB_CTL) |
5725                                                 DISP_FBC_WM_DIS));
5726                 }
5727                 /*
5728                  * Based on the document from hardware guys the following bits
5729                  * should be set unconditionally in order to enable FBC.
5730                  * The bit 22 of 0x42000
5731                  * The bit 22 of 0x42004
5732                  * The bit 7,8,9 of 0x42020.
5733                  */
5734                 if (IS_IRONLAKE_M(dev)) {
5735                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5736                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5737                                    ILK_FBCQ_DIS);
5738                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5739                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5740                                    ILK_DPARB_GATE);
5741                         I915_WRITE(ILK_DSPCLK_GATE,
5742                                    I915_READ(ILK_DSPCLK_GATE) |
5743                                    ILK_DPFC_DIS1 |
5744                                    ILK_DPFC_DIS2 |
5745                                    ILK_CLK_FBC);
5746                 }
5747                 return;
5748         } else if (IS_G4X(dev)) {
5749                 uint32_t dspclk_gate;
5750                 I915_WRITE(RENCLK_GATE_D1, 0);
5751                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5752                        GS_UNIT_CLOCK_GATE_DISABLE |
5753                        CL_UNIT_CLOCK_GATE_DISABLE);
5754                 I915_WRITE(RAMCLK_GATE_D, 0);
5755                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5756                         OVRUNIT_CLOCK_GATE_DISABLE |
5757                         OVCUNIT_CLOCK_GATE_DISABLE;
5758                 if (IS_GM45(dev))
5759                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5760                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5761         } else if (IS_I965GM(dev)) {
5762                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5763                 I915_WRITE(RENCLK_GATE_D2, 0);
5764                 I915_WRITE(DSPCLK_GATE_D, 0);
5765                 I915_WRITE(RAMCLK_GATE_D, 0);
5766                 I915_WRITE16(DEUC, 0);
5767         } else if (IS_I965G(dev)) {
5768                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5769                        I965_RCC_CLOCK_GATE_DISABLE |
5770                        I965_RCPB_CLOCK_GATE_DISABLE |
5771                        I965_ISC_CLOCK_GATE_DISABLE |
5772                        I965_FBC_CLOCK_GATE_DISABLE);
5773                 I915_WRITE(RENCLK_GATE_D2, 0);
5774         } else if (IS_I9XX(dev)) {
5775                 u32 dstate = I915_READ(D_STATE);
5776
5777                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5778                         DSTATE_DOT_CLOCK_GATING;
5779                 I915_WRITE(D_STATE, dstate);
5780         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5781                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5782         } else if (IS_I830(dev)) {
5783                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5784         }
5785
5786         /*
5787          * GPU can automatically power down the render unit if given a page
5788          * to save state.
5789          */
5790         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5791                 struct drm_i915_gem_object *obj_priv = NULL;
5792
5793                 if (dev_priv->pwrctx) {
5794                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5795                 } else {
5796                         struct drm_gem_object *pwrctx;
5797
5798                         pwrctx = intel_alloc_power_context(dev);
5799                         if (pwrctx) {
5800                                 dev_priv->pwrctx = pwrctx;
5801                                 obj_priv = to_intel_bo(pwrctx);
5802                         }
5803                 }
5804
5805                 if (obj_priv) {
5806                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5807                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5808                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5809                 }
5810         }
5811 }
5812
5813 /* Set up chip specific display functions */
5814 static void intel_init_display(struct drm_device *dev)
5815 {
5816         struct drm_i915_private *dev_priv = dev->dev_private;
5817
5818         /* We always want a DPMS function */
5819         if (HAS_PCH_SPLIT(dev))
5820                 dev_priv->display.dpms = ironlake_crtc_dpms;
5821         else
5822                 dev_priv->display.dpms = i9xx_crtc_dpms;
5823
5824         if (I915_HAS_FBC(dev)) {
5825                 if (IS_IRONLAKE_M(dev)) {
5826                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5827                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5828                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5829                 } else if (IS_GM45(dev)) {
5830                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5831                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5832                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5833                 } else if (IS_I965GM(dev)) {
5834                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5835                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5836                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5837                 }
5838                 /* 855GM needs testing */
5839         }
5840
5841         /* Returns the core display clock speed */
5842         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5843                 dev_priv->display.get_display_clock_speed =
5844                         i945_get_display_clock_speed;
5845         else if (IS_I915G(dev))
5846                 dev_priv->display.get_display_clock_speed =
5847                         i915_get_display_clock_speed;
5848         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5849                 dev_priv->display.get_display_clock_speed =
5850                         i9xx_misc_get_display_clock_speed;
5851         else if (IS_I915GM(dev))
5852                 dev_priv->display.get_display_clock_speed =
5853                         i915gm_get_display_clock_speed;
5854         else if (IS_I865G(dev))
5855                 dev_priv->display.get_display_clock_speed =
5856                         i865_get_display_clock_speed;
5857         else if (IS_I85X(dev))
5858                 dev_priv->display.get_display_clock_speed =
5859                         i855_get_display_clock_speed;
5860         else /* 852, 830 */
5861                 dev_priv->display.get_display_clock_speed =
5862                         i830_get_display_clock_speed;
5863
5864         /* For FIFO watermark updates */
5865         if (HAS_PCH_SPLIT(dev)) {
5866                 if (IS_IRONLAKE(dev)) {
5867                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5868                                 dev_priv->display.update_wm = ironlake_update_wm;
5869                         else {
5870                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5871                                               "Disable CxSR\n");
5872                                 dev_priv->display.update_wm = NULL;
5873                         }
5874                 } else
5875                         dev_priv->display.update_wm = NULL;
5876         } else if (IS_PINEVIEW(dev)) {
5877                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5878                                             dev_priv->is_ddr3,
5879                                             dev_priv->fsb_freq,
5880                                             dev_priv->mem_freq)) {
5881                         DRM_INFO("failed to find known CxSR latency "
5882                                  "(found ddr%s fsb freq %d, mem freq %d), "
5883                                  "disabling CxSR\n",
5884                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5885                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5886                         /* Disable CxSR and never update its watermark again */
5887                         pineview_disable_cxsr(dev);
5888                         dev_priv->display.update_wm = NULL;
5889                 } else
5890                         dev_priv->display.update_wm = pineview_update_wm;
5891         } else if (IS_G4X(dev))
5892                 dev_priv->display.update_wm = g4x_update_wm;
5893         else if (IS_I965G(dev))
5894                 dev_priv->display.update_wm = i965_update_wm;
5895         else if (IS_I9XX(dev)) {
5896                 dev_priv->display.update_wm = i9xx_update_wm;
5897                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5898         } else if (IS_I85X(dev)) {
5899                 dev_priv->display.update_wm = i9xx_update_wm;
5900                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5901         } else {
5902                 dev_priv->display.update_wm = i830_update_wm;
5903                 if (IS_845G(dev))
5904                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5905                 else
5906                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5907         }
5908 }
5909
5910 /*
5911  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5912  * resume, or other times.  This quirk makes sure that's the case for
5913  * affected systems.
5914  */
5915 static void quirk_pipea_force (struct drm_device *dev)
5916 {
5917         struct drm_i915_private *dev_priv = dev->dev_private;
5918
5919         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5920         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5921 }
5922
5923 struct intel_quirk {
5924         int device;
5925         int subsystem_vendor;
5926         int subsystem_device;
5927         void (*hook)(struct drm_device *dev);
5928 };
5929
5930 struct intel_quirk intel_quirks[] = {
5931         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5932         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5933         /* HP Mini needs pipe A force quirk (LP: #322104) */
5934         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5935
5936         /* Thinkpad R31 needs pipe A force quirk */
5937         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5938         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5939         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5940
5941         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5942         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5943         /* ThinkPad X40 needs pipe A force quirk */
5944
5945         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5946         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5947
5948         /* 855 & before need to leave pipe A & dpll A up */
5949         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5950         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5951 };
5952
5953 static void intel_init_quirks(struct drm_device *dev)
5954 {
5955         struct pci_dev *d = dev->pdev;
5956         int i;
5957
5958         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5959                 struct intel_quirk *q = &intel_quirks[i];
5960
5961                 if (d->device == q->device &&
5962                     (d->subsystem_vendor == q->subsystem_vendor ||
5963                      q->subsystem_vendor == PCI_ANY_ID) &&
5964                     (d->subsystem_device == q->subsystem_device ||
5965                      q->subsystem_device == PCI_ANY_ID))
5966                         q->hook(dev);
5967         }
5968 }
5969
5970 void intel_modeset_init(struct drm_device *dev)
5971 {
5972         struct drm_i915_private *dev_priv = dev->dev_private;
5973         int i;
5974
5975         drm_mode_config_init(dev);
5976
5977         dev->mode_config.min_width = 0;
5978         dev->mode_config.min_height = 0;
5979
5980         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5981
5982         intel_init_quirks(dev);
5983
5984         intel_init_display(dev);
5985
5986         if (IS_I965G(dev)) {
5987                 dev->mode_config.max_width = 8192;
5988                 dev->mode_config.max_height = 8192;
5989         } else if (IS_I9XX(dev)) {
5990                 dev->mode_config.max_width = 4096;
5991                 dev->mode_config.max_height = 4096;
5992         } else {
5993                 dev->mode_config.max_width = 2048;
5994                 dev->mode_config.max_height = 2048;
5995         }
5996
5997         /* set memory base */
5998         if (IS_I9XX(dev))
5999                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6000         else
6001                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6002
6003         if (IS_MOBILE(dev) || IS_I9XX(dev))
6004                 dev_priv->num_pipe = 2;
6005         else
6006                 dev_priv->num_pipe = 1;
6007         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6008                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6009
6010         for (i = 0; i < dev_priv->num_pipe; i++) {
6011                 intel_crtc_init(dev, i);
6012         }
6013
6014         intel_setup_outputs(dev);
6015
6016         intel_init_clock_gating(dev);
6017
6018         if (IS_IRONLAKE_M(dev)) {
6019                 ironlake_enable_drps(dev);
6020                 intel_init_emon(dev);
6021         }
6022
6023         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6024         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6025                     (unsigned long)dev);
6026
6027         intel_setup_overlay(dev);
6028 }
6029
6030 void intel_modeset_cleanup(struct drm_device *dev)
6031 {
6032         struct drm_i915_private *dev_priv = dev->dev_private;
6033         struct drm_crtc *crtc;
6034         struct intel_crtc *intel_crtc;
6035
6036         mutex_lock(&dev->struct_mutex);
6037
6038         drm_kms_helper_poll_fini(dev);
6039         intel_fbdev_fini(dev);
6040
6041         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6042                 /* Skip inactive CRTCs */
6043                 if (!crtc->fb)
6044                         continue;
6045
6046                 intel_crtc = to_intel_crtc(crtc);
6047                 intel_increase_pllclock(crtc, false);
6048                 del_timer_sync(&intel_crtc->idle_timer);
6049         }
6050
6051         del_timer_sync(&dev_priv->idle_timer);
6052
6053         if (dev_priv->display.disable_fbc)
6054                 dev_priv->display.disable_fbc(dev);
6055
6056         if (dev_priv->pwrctx) {
6057                 struct drm_i915_gem_object *obj_priv;
6058
6059                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6060                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6061                 I915_READ(PWRCTXA);
6062                 i915_gem_object_unpin(dev_priv->pwrctx);
6063                 drm_gem_object_unreference(dev_priv->pwrctx);
6064         }
6065
6066         if (IS_IRONLAKE_M(dev))
6067                 ironlake_disable_drps(dev);
6068
6069         mutex_unlock(&dev->struct_mutex);
6070
6071         drm_mode_config_cleanup(dev);
6072 }
6073
6074
6075 /*
6076  * Return which encoder is currently attached for connector.
6077  */
6078 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6079 {
6080         struct drm_mode_object *obj;
6081         struct drm_encoder *encoder;
6082         int i;
6083
6084         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6085                 if (connector->encoder_ids[i] == 0)
6086                         break;
6087
6088                 obj = drm_mode_object_find(connector->dev,
6089                                            connector->encoder_ids[i],
6090                                            DRM_MODE_OBJECT_ENCODER);
6091                 if (!obj)
6092                         continue;
6093
6094                 encoder = obj_to_encoder(obj);
6095                 return encoder;
6096         }
6097         return NULL;
6098 }
6099
6100 /*
6101  * set vga decode state - true == enable VGA decode
6102  */
6103 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6104 {
6105         struct drm_i915_private *dev_priv = dev->dev_private;
6106         u16 gmch_ctrl;
6107
6108         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6109         if (state)
6110                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6111         else
6112                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6113         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6114         return 0;
6115 }