drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_dp.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73     bool (* find_reduced_pll)(const intel_limit_t *, struct drm_crtc *,
  74                               int, int, intel_clock_t *);
  75 };
  76
  77 #define I8XX_DOT_MIN              25000
  78 #define I8XX_DOT_MAX             350000
  79 #define I8XX_VCO_MIN             930000
  80 #define I8XX_VCO_MAX            1400000
  81 #define I8XX_N_MIN                    3
  82 #define I8XX_N_MAX                   16
  83 #define I8XX_M_MIN                   96
  84 #define I8XX_M_MAX                  140
  85 #define I8XX_M1_MIN                  18
  86 #define I8XX_M1_MAX                  26
  87 #define I8XX_M2_MIN                   6
  88 #define I8XX_M2_MAX                  16
  89 #define I8XX_P_MIN                    4
  90 #define I8XX_P_MAX                  128
  91 #define I8XX_P1_MIN                   2
  92 #define I8XX_P1_MAX                  33
  93 #define I8XX_P1_LVDS_MIN              1
  94 #define I8XX_P1_LVDS_MAX              6
  95 #define I8XX_P2_SLOW                  4
  96 #define I8XX_P2_FAST                  2
  97 #define I8XX_P2_LVDS_SLOW             14
  98 #define I8XX_P2_LVDS_FAST             7
  99 #define I8XX_P2_SLOW_LIMIT       165000
 100
 101 #define I9XX_DOT_MIN              20000
 102 #define I9XX_DOT_MAX             400000
 103 #define I9XX_VCO_MIN            1400000
 104 #define I9XX_VCO_MAX            2800000
 105 #define IGD_VCO_MIN             1700000
 106 #define IGD_VCO_MAX             3500000
 107 #define I9XX_N_MIN                    1
 108 #define I9XX_N_MAX                    6
 109 /* IGD's Ncounter is a ring counter */
 110 #define IGD_N_MIN                     3
 111 #define IGD_N_MAX                     6
 112 #define I9XX_M_MIN                   70
 113 #define I9XX_M_MAX                  120
 114 #define IGD_M_MIN                     2
 115 #define IGD_M_MAX                   256
 116 #define I9XX_M1_MIN                  10
 117 #define I9XX_M1_MAX                  22
 118 #define I9XX_M2_MIN                   5
 119 #define I9XX_M2_MAX                   9
 120 /* IGD M1 is reserved, and must be 0 */
 121 #define IGD_M1_MIN                    0
 122 #define IGD_M1_MAX                    0
 123 #define IGD_M2_MIN                    0
 124 #define IGD_M2_MAX                    254
 125 #define I9XX_P_SDVO_DAC_MIN           5
 126 #define I9XX_P_SDVO_DAC_MAX          80
 127 #define I9XX_P_LVDS_MIN               7
 128 #define I9XX_P_LVDS_MAX              98
 129 #define IGD_P_LVDS_MIN                7
 130 #define IGD_P_LVDS_MAX               112
 131 #define I9XX_P1_MIN                   1
 132 #define I9XX_P1_MAX                   8
 133 #define I9XX_P2_SDVO_DAC_SLOW                10
 134 #define I9XX_P2_SDVO_DAC_FAST                 5
 135 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 136 #define I9XX_P2_LVDS_SLOW                    14
 137 #define I9XX_P2_LVDS_FAST                     7
 138 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 139
 140 /*The parameter is for SDVO on G4x platform*/
 141 #define G4X_DOT_SDVO_MIN           25000
 142 #define G4X_DOT_SDVO_MAX           270000
 143 #define G4X_VCO_MIN                1750000
 144 #define G4X_VCO_MAX                3500000
 145 #define G4X_N_SDVO_MIN             1
 146 #define G4X_N_SDVO_MAX             4
 147 #define G4X_M_SDVO_MIN             104
 148 #define G4X_M_SDVO_MAX             138
 149 #define G4X_M1_SDVO_MIN            17
 150 #define G4X_M1_SDVO_MAX            23
 151 #define G4X_M2_SDVO_MIN            5
 152 #define G4X_M2_SDVO_MAX            11
 153 #define G4X_P_SDVO_MIN             10
 154 #define G4X_P_SDVO_MAX             30
 155 #define G4X_P1_SDVO_MIN            1
 156 #define G4X_P1_SDVO_MAX            3
 157 #define G4X_P2_SDVO_SLOW           10
 158 #define G4X_P2_SDVO_FAST           10
 159 #define G4X_P2_SDVO_LIMIT          270000
 160
 161 /*The parameter is for HDMI_DAC on G4x platform*/
 162 #define G4X_DOT_HDMI_DAC_MIN           22000
 163 #define G4X_DOT_HDMI_DAC_MAX           400000
 164 #define G4X_N_HDMI_DAC_MIN             1
 165 #define G4X_N_HDMI_DAC_MAX             4
 166 #define G4X_M_HDMI_DAC_MIN             104
 167 #define G4X_M_HDMI_DAC_MAX             138
 168 #define G4X_M1_HDMI_DAC_MIN            16
 169 #define G4X_M1_HDMI_DAC_MAX            23
 170 #define G4X_M2_HDMI_DAC_MIN            5
 171 #define G4X_M2_HDMI_DAC_MAX            11
 172 #define G4X_P_HDMI_DAC_MIN             5
 173 #define G4X_P_HDMI_DAC_MAX             80
 174 #define G4X_P1_HDMI_DAC_MIN            1
 175 #define G4X_P1_HDMI_DAC_MAX            8
 176 #define G4X_P2_HDMI_DAC_SLOW           10
 177 #define G4X_P2_HDMI_DAC_FAST           5
 178 #define G4X_P2_HDMI_DAC_LIMIT          165000
 179
 180 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 183 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 185 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 191 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 198
 199 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 202 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 204 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 206 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 208 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 210 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 212 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 217
 218 /*The parameter is for DISPLAY PORT on G4x platform*/
 219 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 220 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 221 #define G4X_N_DISPLAY_PORT_MIN             1
 222 #define G4X_N_DISPLAY_PORT_MAX             2
 223 #define G4X_M_DISPLAY_PORT_MIN             97
 224 #define G4X_M_DISPLAY_PORT_MAX             108
 225 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 226 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 227 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 228 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 229 #define G4X_P_DISPLAY_PORT_MIN             10
 230 #define G4X_P_DISPLAY_PORT_MAX             20
 231 #define G4X_P1_DISPLAY_PORT_MIN            1
 232 #define G4X_P1_DISPLAY_PORT_MAX            2
 233 #define G4X_P2_DISPLAY_PORT_SLOW           10
 234 #define G4X_P2_DISPLAY_PORT_FAST           10
 235 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 236
 237 /* IGDNG */
 238 /* as we calculate clock using (register_value + 2) for
 239    N/M1/M2, so here the range value for them is (actual_value-2).
 240  */
 241 #define IGDNG_DOT_MIN         25000
 242 #define IGDNG_DOT_MAX         350000
 243 #define IGDNG_VCO_MIN         1760000
 244 #define IGDNG_VCO_MAX         3510000
 245 #define IGDNG_N_MIN           1
 246 #define IGDNG_N_MAX           5
 247 #define IGDNG_M_MIN           79
 248 #define IGDNG_M_MAX           118
 249 #define IGDNG_M1_MIN          12
 250 #define IGDNG_M1_MAX          23
 251 #define IGDNG_M2_MIN          5
 252 #define IGDNG_M2_MAX          9
 253 #define IGDNG_P_SDVO_DAC_MIN  5
 254 #define IGDNG_P_SDVO_DAC_MAX  80
 255 #define IGDNG_P_LVDS_MIN      28
 256 #define IGDNG_P_LVDS_MAX      112
 257 #define IGDNG_P1_MIN          1
 258 #define IGDNG_P1_MAX          8
 259 #define IGDNG_P2_SDVO_DAC_SLOW 10
 260 #define IGDNG_P2_SDVO_DAC_FAST 5
 261 #define IGDNG_P2_LVDS_SLOW    14 /* single channel */
 262 #define IGDNG_P2_LVDS_FAST    7  /* double channel */
 263 #define IGDNG_P2_DOT_LIMIT    225000 /* 225Mhz */
 264
 265 static bool
 266 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 267                     int target, int refclk, intel_clock_t *best_clock);
 268 static bool
 269 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 270                             int target, int refclk, intel_clock_t *best_clock);
 271 static bool
 272 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 273                         int target, int refclk, intel_clock_t *best_clock);
 274 static bool
 275 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 276                         int target, int refclk, intel_clock_t *best_clock);
 277
 278 static bool
 279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 280                       int target, int refclk, intel_clock_t *best_clock);
 281 static bool
 282 intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
 283                       int target, int refclk, intel_clock_t *best_clock);
 284
 285 static const intel_limit_t intel_limits_i8xx_dvo = {
 286         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 287         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 288         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 289         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 290         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 291         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 292         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 293         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 294         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 295                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 296         .find_pll = intel_find_best_PLL,
 297         .find_reduced_pll = intel_find_best_reduced_PLL,
 298 };
 299
 300 static const intel_limit_t intel_limits_i8xx_lvds = {
 301         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 302         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 303         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 304         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 305         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 306         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 307         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 308         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 309         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 310                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 311         .find_pll = intel_find_best_PLL,
 312         .find_reduced_pll = intel_find_best_reduced_PLL,
 313 };
 314
 315 static const intel_limit_t intel_limits_i9xx_sdvo = {
 316         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 317         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 318         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 319         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 320         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 321         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 322         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 323         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 324         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 325                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 326         .find_pll = intel_find_best_PLL,
 327         .find_reduced_pll = intel_find_best_reduced_PLL,
 328 };
 329
 330 static const intel_limit_t intel_limits_i9xx_lvds = {
 331         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 332         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 333         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 334         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 335         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 336         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 337         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 338         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 339         /* The single-channel range is 25-112Mhz, and dual-channel
 340          * is 80-224Mhz.  Prefer single channel as much as possible.
 341          */
 342         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 343                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 344         .find_pll = intel_find_best_PLL,
 345         .find_reduced_pll = intel_find_best_reduced_PLL,
 346 };
 347
 348     /* below parameter and function is for G4X Chipset Family*/
 349 static const intel_limit_t intel_limits_g4x_sdvo = {
 350         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 351         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 352         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 353         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 354         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 355         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 356         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 357         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 358         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 359                  .p2_slow = G4X_P2_SDVO_SLOW,
 360                  .p2_fast = G4X_P2_SDVO_FAST
 361         },
 362         .find_pll = intel_g4x_find_best_PLL,
 363         .find_reduced_pll = intel_g4x_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_g4x_hdmi = {
 367         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 368         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 369         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 370         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 371         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 372         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 373         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 374         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 375         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 376                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 377                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 378         },
 379         .find_pll = intel_g4x_find_best_PLL,
 380         .find_reduced_pll = intel_g4x_find_best_PLL,
 381 };
 382
 383 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 384         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 385                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 386         .vco = { .min = G4X_VCO_MIN,
 387                  .max = G4X_VCO_MAX },
 388         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 389                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 390         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 391                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 392         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 393                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 394         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 395                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 396         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 397                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 398         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 399                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 400         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 401                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 402                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 403         },
 404         .find_pll = intel_g4x_find_best_PLL,
 405         .find_reduced_pll = intel_g4x_find_best_PLL,
 406 };
 407
 408 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 409         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 410                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 411         .vco = { .min = G4X_VCO_MIN,
 412                  .max = G4X_VCO_MAX },
 413         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 414                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 415         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 416                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 417         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 418                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 419         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 420                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 421         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 422                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 423         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 424                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 425         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 426                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 427                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 428         },
 429         .find_pll = intel_g4x_find_best_PLL,
 430         .find_reduced_pll = intel_g4x_find_best_PLL,
 431 };
 432
 433 static const intel_limit_t intel_limits_g4x_display_port = {
 434         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 435                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 436         .vco = { .min = G4X_VCO_MIN,
 437                  .max = G4X_VCO_MAX},
 438         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 439                  .max = G4X_N_DISPLAY_PORT_MAX },
 440         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 441                  .max = G4X_M_DISPLAY_PORT_MAX },
 442         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 443                  .max = G4X_M1_DISPLAY_PORT_MAX },
 444         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 445                  .max = G4X_M2_DISPLAY_PORT_MAX },
 446         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 447                  .max = G4X_P_DISPLAY_PORT_MAX },
 448         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 449                  .max = G4X_P1_DISPLAY_PORT_MAX},
 450         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 451                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 452                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 453         .find_pll = intel_find_pll_g4x_dp,
 454 };
 455
 456 static const intel_limit_t intel_limits_igd_sdvo = {
 457         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 458         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 459         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 460         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 461         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 462         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 463         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 464         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 465         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 466                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 467         .find_pll = intel_find_best_PLL,
 468         .find_reduced_pll = intel_find_best_reduced_PLL,
 469 };
 470
 471 static const intel_limit_t intel_limits_igd_lvds = {
 472         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 473         .vco = { .min = IGD_VCO_MIN,            .max = IGD_VCO_MAX },
 474         .n   = { .min = IGD_N_MIN,              .max = IGD_N_MAX },
 475         .m   = { .min = IGD_M_MIN,              .max = IGD_M_MAX },
 476         .m1  = { .min = IGD_M1_MIN,             .max = IGD_M1_MAX },
 477         .m2  = { .min = IGD_M2_MIN,             .max = IGD_M2_MAX },
 478         .p   = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
 479         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 480         /* IGD only supports single-channel mode. */
 481         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 482                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 483         .find_pll = intel_find_best_PLL,
 484         .find_reduced_pll = intel_find_best_reduced_PLL,
 485 };
 486
 487 static const intel_limit_t intel_limits_igdng_sdvo = {
 488         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 489         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 490         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 491         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 492         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 493         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 494         .p   = { .min = IGDNG_P_SDVO_DAC_MIN,   .max = IGDNG_P_SDVO_DAC_MAX },
 495         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 496         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 497                  .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
 498                  .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
 499         .find_pll = intel_igdng_find_best_PLL,
 500 };
 501
 502 static const intel_limit_t intel_limits_igdng_lvds = {
 503         .dot = { .min = IGDNG_DOT_MIN,          .max = IGDNG_DOT_MAX },
 504         .vco = { .min = IGDNG_VCO_MIN,          .max = IGDNG_VCO_MAX },
 505         .n   = { .min = IGDNG_N_MIN,            .max = IGDNG_N_MAX },
 506         .m   = { .min = IGDNG_M_MIN,            .max = IGDNG_M_MAX },
 507         .m1  = { .min = IGDNG_M1_MIN,           .max = IGDNG_M1_MAX },
 508         .m2  = { .min = IGDNG_M2_MIN,           .max = IGDNG_M2_MAX },
 509         .p   = { .min = IGDNG_P_LVDS_MIN,       .max = IGDNG_P_LVDS_MAX },
 510         .p1  = { .min = IGDNG_P1_MIN,           .max = IGDNG_P1_MAX },
 511         .p2  = { .dot_limit = IGDNG_P2_DOT_LIMIT,
 512                  .p2_slow = IGDNG_P2_LVDS_SLOW,
 513                  .p2_fast = IGDNG_P2_LVDS_FAST },
 514         .find_pll = intel_igdng_find_best_PLL,
 515 };
 516
 517 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
 518 {
 519         const intel_limit_t *limit;
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 521                 limit = &intel_limits_igdng_lvds;
 522         else
 523                 limit = &intel_limits_igdng_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         const intel_limit_t *limit;
 533
 534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 535                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 536                     LVDS_CLKB_POWER_UP)
 537                         /* LVDS with dual channel */
 538                         limit = &intel_limits_g4x_dual_channel_lvds;
 539                 else
 540                         /* LVDS with dual channel */
 541                         limit = &intel_limits_g4x_single_channel_lvds;
 542         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 543                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 544                 limit = &intel_limits_g4x_hdmi;
 545         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 546                 limit = &intel_limits_g4x_sdvo;
 547         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 548                 limit = &intel_limits_g4x_display_port;
 549         } else /* The option is for other outputs */
 550                 limit = &intel_limits_i9xx_sdvo;
 551
 552         return limit;
 553 }
 554
 555 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         const intel_limit_t *limit;
 559
 560         if (IS_IGDNG(dev))
 561                 limit = intel_igdng_limit(crtc);
 562         else if (IS_G4X(dev)) {
 563                 limit = intel_g4x_limit(crtc);
 564         } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
 565                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 566                         limit = &intel_limits_i9xx_lvds;
 567                 else
 568                         limit = &intel_limits_i9xx_sdvo;
 569         } else if (IS_IGD(dev)) {
 570                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 571                         limit = &intel_limits_igd_lvds;
 572                 else
 573                         limit = &intel_limits_igd_sdvo;
 574         } else {
 575                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 576                         limit = &intel_limits_i8xx_lvds;
 577                 else
 578                         limit = &intel_limits_i8xx_dvo;
 579         }
 580         return limit;
 581 }
 582
 583 /* m1 is reserved as 0 in IGD, n is a ring counter */
 584 static void igd_clock(int refclk, intel_clock_t *clock)
 585 {
 586         clock->m = clock->m2 + 2;
 587         clock->p = clock->p1 * clock->p2;
 588         clock->vco = refclk * clock->m / clock->n;
 589         clock->dot = clock->vco / clock->p;
 590 }
 591
 592 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 593 {
 594         if (IS_IGD(dev)) {
 595                 igd_clock(refclk, clock);
 596                 return;
 597         }
 598         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 599         clock->p = clock->p1 * clock->p2;
 600         clock->vco = refclk * clock->m / (clock->n + 2);
 601         clock->dot = clock->vco / clock->p;
 602 }
 603
 604 /**
 605  * Returns whether any output on the specified pipe is of the specified type
 606  */
 607 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 608 {
 609     struct drm_device *dev = crtc->dev;
 610     struct drm_mode_config *mode_config = &dev->mode_config;
 611     struct drm_connector *l_entry;
 612
 613     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 614             if (l_entry->encoder &&
 615                 l_entry->encoder->crtc == crtc) {
 616                     struct intel_output *intel_output = to_intel_output(l_entry);
 617                     if (intel_output->type == type)
 618                             return true;
 619             }
 620     }
 621     return false;
 622 }
 623
 624 struct drm_connector *
 625 intel_pipe_get_output (struct drm_crtc *crtc)
 626 {
 627     struct drm_device *dev = crtc->dev;
 628     struct drm_mode_config *mode_config = &dev->mode_config;
 629     struct drm_connector *l_entry, *ret = NULL;
 630
 631     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 632             if (l_entry->encoder &&
 633                 l_entry->encoder->crtc == crtc) {
 634                     ret = l_entry;
 635                     break;
 636             }
 637     }
 638     return ret;
 639 }
 640
 641 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 642 /**
 643  * Returns whether the given set of divisors are valid for a given refclk with
 644  * the given connectors.
 645  */
 646
 647 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 648 {
 649         const intel_limit_t *limit = intel_limit (crtc);
 650         struct drm_device *dev = crtc->dev;
 651
 652         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 653                 INTELPllInvalid ("p1 out of range\n");
 654         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 655                 INTELPllInvalid ("p out of range\n");
 656         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 657                 INTELPllInvalid ("m2 out of range\n");
 658         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 659                 INTELPllInvalid ("m1 out of range\n");
 660         if (clock->m1 <= clock->m2 && !IS_IGD(dev))
 661                 INTELPllInvalid ("m1 <= m2\n");
 662         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 663                 INTELPllInvalid ("m out of range\n");
 664         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 665                 INTELPllInvalid ("n out of range\n");
 666         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 667                 INTELPllInvalid ("vco out of range\n");
 668         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 669          * connector, etc., rather than just a single range.
 670          */
 671         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 672                 INTELPllInvalid ("dot out of range\n");
 673
 674         return true;
 675 }
 676
 677 static bool
 678 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 679                     int target, int refclk, intel_clock_t *best_clock)
 680
 681 {
 682         struct drm_device *dev = crtc->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 688             (I915_READ(LVDS)) != 0) {
 689                 /*
 690                  * For LVDS, if the panel is on, just rely on its current
 691                  * settings for dual-channel.  We haven't figured out how to
 692                  * reliably set up different single/dual channel state, if we
 693                  * even can.
 694                  */
 695                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 696                     LVDS_CLKB_POWER_UP)
 697                         clock.p2 = limit->p2.p2_fast;
 698                 else
 699                         clock.p2 = limit->p2.p2_slow;
 700         } else {
 701                 if (target < limit->p2.dot_limit)
 702                         clock.p2 = limit->p2.p2_slow;
 703                 else
 704                         clock.p2 = limit->p2.p2_fast;
 705         }
 706
 707         memset (best_clock, 0, sizeof (*best_clock));
 708
 709         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 710                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 711                      clock.m1++) {
 712                         for (clock.m2 = limit->m2.min;
 713                              clock.m2 <= limit->m2.max; clock.m2++) {
 714                                 /* m1 is always 0 in IGD */
 715                                 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 716                                         break;
 717                                 for (clock.n = limit->n.min;
 718                                      clock.n <= limit->n.max; clock.n++) {
 719                                         int this_err;
 720
 721                                         intel_clock(dev, refclk, &clock);
 722
 723                                         if (!intel_PLL_is_valid(crtc, &clock))
 724                                                 continue;
 725
 726                                         this_err = abs(clock.dot - target);
 727                                         if (this_err < err) {
 728                                                 *best_clock = clock;
 729                                                 err = this_err;
 730                                         }
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         return (err != target);
 737 }
 738
 739
 740 static bool
 741 intel_find_best_reduced_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                             int target, int refclk, intel_clock_t *best_clock)
 743
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         intel_clock_t clock;
 747         int err = target;
 748         bool found = false;
 749
 750         memcpy(&clock, best_clock, sizeof(intel_clock_t));
 751
 752         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 753                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
 754                         /* m1 is always 0 in IGD */
 755                         if (clock.m2 >= clock.m1 && !IS_IGD(dev))
 756                                 break;
 757                         for (clock.n = limit->n.min; clock.n <= limit->n.max;
 758                              clock.n++) {
 759                                 int this_err;
 760
 761                                 intel_clock(dev, refclk, &clock);
 762
 763                                 if (!intel_PLL_is_valid(crtc, &clock))
 764                                         continue;
 765
 766                                 this_err = abs(clock.dot - target);
 767                                 if (this_err < err) {
 768                                         *best_clock = clock;
 769                                         err = this_err;
 770                                         found = true;
 771                                 }
 772                         }
 773                 }
 774         }
 775
 776         return found;
 777 }
 778
 779 static bool
 780 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 781                         int target, int refclk, intel_clock_t *best_clock)
 782 {
 783         struct drm_device *dev = crtc->dev;
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         intel_clock_t clock;
 786         int max_n;
 787         bool found;
 788         /* approximately equals target * 0.00488 */
 789         int err_most = (target >> 8) + (target >> 10);
 790         found = false;
 791
 792         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 793                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 794                     LVDS_CLKB_POWER_UP)
 795                         clock.p2 = limit->p2.p2_fast;
 796                 else
 797                         clock.p2 = limit->p2.p2_slow;
 798         } else {
 799                 if (target < limit->p2.dot_limit)
 800                         clock.p2 = limit->p2.p2_slow;
 801                 else
 802                         clock.p2 = limit->p2.p2_fast;
 803         }
 804
 805         memset(best_clock, 0, sizeof(*best_clock));
 806         max_n = limit->n.max;
 807         /* based on hardware requriment prefer smaller n to precision */
 808         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 809                 /* based on hardware requirment prefere larger m1,m2 */
 810                 for (clock.m1 = limit->m1.max;
 811                      clock.m1 >= limit->m1.min; clock.m1--) {
 812                         for (clock.m2 = limit->m2.max;
 813                              clock.m2 >= limit->m2.min; clock.m2--) {
 814                                 for (clock.p1 = limit->p1.max;
 815                                      clock.p1 >= limit->p1.min; clock.p1--) {
 816                                         int this_err;
 817
 818                                         intel_clock(dev, refclk, &clock);
 819                                         if (!intel_PLL_is_valid(crtc, &clock))
 820                                                 continue;
 821                                         this_err = abs(clock.dot - target) ;
 822                                         if (this_err < err_most) {
 823                                                 *best_clock = clock;
 824                                                 err_most = this_err;
 825                                                 max_n = clock.n;
 826                                                 found = true;
 827                                         }
 828                                 }
 829                         }
 830                 }
 831         }
 832         return found;
 833 }
 834
 835 static bool
 836 intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *best_clock)
 838 {
 839         struct drm_device *dev = crtc->dev;
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.n = 1;
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.m1 = 12;
 846                 clock.m2 = 9;
 847         } else {
 848                 clock.n = 2;
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.m1 = 14;
 852                 clock.m2 = 8;
 853         }
 854         intel_clock(dev, refclk, &clock);
 855         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 856         return true;
 857 }
 858
 859 static bool
 860 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 861                         int target, int refclk, intel_clock_t *best_clock)
 862 {
 863         struct drm_device *dev = crtc->dev;
 864         struct drm_i915_private *dev_priv = dev->dev_private;
 865         intel_clock_t clock;
 866         int err_most = 47;
 867         int err_min = 10000;
 868
 869         /* eDP has only 2 clock choice, no n/m/p setting */
 870         if (HAS_eDP)
 871                 return true;
 872
 873         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 874                 return intel_find_pll_igdng_dp(limit, crtc, target,
 875                                                refclk, best_clock);
 876
 877         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 878                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 879                     LVDS_CLKB_POWER_UP)
 880                         clock.p2 = limit->p2.p2_fast;
 881                 else
 882                         clock.p2 = limit->p2.p2_slow;
 883         } else {
 884                 if (target < limit->p2.dot_limit)
 885                         clock.p2 = limit->p2.p2_slow;
 886                 else
 887                         clock.p2 = limit->p2.p2_fast;
 888         }
 889
 890         memset(best_clock, 0, sizeof(*best_clock));
 891         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 892                 /* based on hardware requriment prefer smaller n to precision */
 893                 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 894                         /* based on hardware requirment prefere larger m1,m2 */
 895                         for (clock.m1 = limit->m1.max;
 896                              clock.m1 >= limit->m1.min; clock.m1--) {
 897                                 for (clock.m2 = limit->m2.max;
 898                                      clock.m2 >= limit->m2.min; clock.m2--) {
 899                                         int this_err;
 900
 901                                         intel_clock(dev, refclk, &clock);
 902                                         if (!intel_PLL_is_valid(crtc, &clock))
 903                                                 continue;
 904                                         this_err = abs((10000 - (target*10000/clock.dot)));
 905                                         if (this_err < err_most) {
 906                                                 *best_clock = clock;
 907                                                 /* found on first matching */
 908                                                 goto out;
 909                                         } else if (this_err < err_min) {
 910                                                 *best_clock = clock;
 911                                                 err_min = this_err;
 912                                         }
 913                                 }
 914                         }
 915                 }
 916         }
 917 out:
 918         return true;
 919 }
 920
 921 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 922 static bool
 923 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 924                       int target, int refclk, intel_clock_t *best_clock)
 925 {
 926     intel_clock_t clock;
 927     if (target < 200000) {
 928         clock.p1 = 2;
 929         clock.p2 = 10;
 930         clock.n = 2;
 931         clock.m1 = 23;
 932         clock.m2 = 8;
 933     } else {
 934         clock.p1 = 1;
 935         clock.p2 = 10;
 936         clock.n = 1;
 937         clock.m1 = 14;
 938         clock.m2 = 2;
 939     }
 940     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 941     clock.p = (clock.p1 * clock.p2);
 942     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 943     clock.vco = 0;
 944     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 945     return true;
 946 }
 947
 948 void
 949 intel_wait_for_vblank(struct drm_device *dev)
 950 {
 951         /* Wait for 20ms, i.e. one cycle at 50hz. */
 952         mdelay(20);
 953 }
 954
 955 /* Parameters have changed, update FBC info */
 956 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 957 {
 958         struct drm_device *dev = crtc->dev;
 959         struct drm_i915_private *dev_priv = dev->dev_private;
 960         struct drm_framebuffer *fb = crtc->fb;
 961         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 962         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
 963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 964         int plane, i;
 965         u32 fbc_ctl, fbc_ctl2;
 966
 967         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
 968
 969         if (fb->pitch < dev_priv->cfb_pitch)
 970                 dev_priv->cfb_pitch = fb->pitch;
 971
 972         /* FBC_CTL wants 64B units */
 973         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
 974         dev_priv->cfb_fence = obj_priv->fence_reg;
 975         dev_priv->cfb_plane = intel_crtc->plane;
 976         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
 977
 978         /* Clear old tags */
 979         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 980                 I915_WRITE(FBC_TAG + (i * 4), 0);
 981
 982         /* Set it up... */
 983         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
 984         if (obj_priv->tiling_mode != I915_TILING_NONE)
 985                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 986         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 987         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 988
 989         /* enable it... */
 990         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 991         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 992         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 993         if (obj_priv->tiling_mode != I915_TILING_NONE)
 994                 fbc_ctl |= dev_priv->cfb_fence;
 995         I915_WRITE(FBC_CONTROL, fbc_ctl);
 996
 997         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
 998                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
 999 }
1000
1001 void i8xx_disable_fbc(struct drm_device *dev)
1002 {
1003         struct drm_i915_private *dev_priv = dev->dev_private;
1004         u32 fbc_ctl;
1005
1006         if (!I915_HAS_FBC(dev))
1007                 return;
1008
1009         /* Disable compression */
1010         fbc_ctl = I915_READ(FBC_CONTROL);
1011         fbc_ctl &= ~FBC_CTL_EN;
1012         I915_WRITE(FBC_CONTROL, fbc_ctl);
1013
1014         /* Wait for compressing bit to clear */
1015         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1016                 ; /* nothing */
1017
1018         intel_wait_for_vblank(dev);
1019
1020         DRM_DEBUG_KMS("disabled FBC\n");
1021 }
1022
1023 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1024 {
1025         struct drm_device *dev = crtc->dev;
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027
1028         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1029 }
1030
1031 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1032 {
1033         struct drm_device *dev = crtc->dev;
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         struct drm_framebuffer *fb = crtc->fb;
1036         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1037         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1039         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1040                      DPFC_CTL_PLANEB);
1041         unsigned long stall_watermark = 200;
1042         u32 dpfc_ctl;
1043
1044         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1045         dev_priv->cfb_fence = obj_priv->fence_reg;
1046         dev_priv->cfb_plane = intel_crtc->plane;
1047
1048         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1049         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1050                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1051                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1052         } else {
1053                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1054         }
1055
1056         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1057         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1058                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1059                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1060         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1061
1062         /* enable it... */
1063         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1064
1065         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1066 }
1067
1068 void g4x_disable_fbc(struct drm_device *dev)
1069 {
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071         u32 dpfc_ctl;
1072
1073         /* Disable compression */
1074         dpfc_ctl = I915_READ(DPFC_CONTROL);
1075         dpfc_ctl &= ~DPFC_CTL_EN;
1076         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1077         intel_wait_for_vblank(dev);
1078
1079         DRM_DEBUG_KMS("disabled FBC\n");
1080 }
1081
1082 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1083 {
1084         struct drm_device *dev = crtc->dev;
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086
1087         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1088 }
1089
1090 /**
1091  * intel_update_fbc - enable/disable FBC as needed
1092  * @crtc: CRTC to point the compressor at
1093  * @mode: mode in use
1094  *
1095  * Set up the framebuffer compression hardware at mode set time.  We
1096  * enable it if possible:
1097  *   - plane A only (on pre-965)
1098  *   - no pixel mulitply/line duplication
1099  *   - no alpha buffer discard
1100  *   - no dual wide
1101  *   - framebuffer <= 2048 in width, 1536 in height
1102  *
1103  * We can't assume that any compression will take place (worst case),
1104  * so the compressed buffer has to be the same size as the uncompressed
1105  * one.  It also must reside (along with the line length buffer) in
1106  * stolen memory.
1107  *
1108  * We need to enable/disable FBC on a global basis.
1109  */
1110 static void intel_update_fbc(struct drm_crtc *crtc,
1111                              struct drm_display_mode *mode)
1112 {
1113         struct drm_device *dev = crtc->dev;
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         struct drm_framebuffer *fb = crtc->fb;
1116         struct intel_framebuffer *intel_fb;
1117         struct drm_i915_gem_object *obj_priv;
1118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1119         int plane = intel_crtc->plane;
1120
1121         if (!i915_powersave)
1122                 return;
1123
1124         if (!dev_priv->display.fbc_enabled ||
1125             !dev_priv->display.enable_fbc ||
1126             !dev_priv->display.disable_fbc)
1127                 return;
1128
1129         if (!crtc->fb)
1130                 return;
1131
1132         intel_fb = to_intel_framebuffer(fb);
1133         obj_priv = intel_fb->obj->driver_private;
1134
1135         /*
1136          * If FBC is already on, we just have to verify that we can
1137          * keep it that way...
1138          * Need to disable if:
1139          *   - changing FBC params (stride, fence, mode)
1140          *   - new fb is too large to fit in compressed buffer
1141          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1142          */
1143         if (intel_fb->obj->size > dev_priv->cfb_size) {
1144                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1145                                 "compression\n");
1146                 goto out_disable;
1147         }
1148         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1149             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1150                 DRM_DEBUG_KMS("mode incompatible with compression, "
1151                                 "disabling\n");
1152                 goto out_disable;
1153         }
1154         if ((mode->hdisplay > 2048) ||
1155             (mode->vdisplay > 1536)) {
1156                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1157                 goto out_disable;
1158         }
1159         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1160                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1161                 goto out_disable;
1162         }
1163         if (obj_priv->tiling_mode != I915_TILING_X) {
1164                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1165                 goto out_disable;
1166         }
1167
1168         if (dev_priv->display.fbc_enabled(crtc)) {
1169                 /* We can re-enable it in this case, but need to update pitch */
1170                 if (fb->pitch > dev_priv->cfb_pitch)
1171                         dev_priv->display.disable_fbc(dev);
1172                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1173                         dev_priv->display.disable_fbc(dev);
1174                 if (plane != dev_priv->cfb_plane)
1175                         dev_priv->display.disable_fbc(dev);
1176         }
1177
1178         if (!dev_priv->display.fbc_enabled(crtc)) {
1179                 /* Now try to turn it back on if possible */
1180                 dev_priv->display.enable_fbc(crtc, 500);
1181         }
1182
1183         return;
1184
1185 out_disable:
1186         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1187         /* Multiple disables should be harmless */
1188         if (dev_priv->display.fbc_enabled(crtc))
1189                 dev_priv->display.disable_fbc(dev);
1190 }
1191
1192 static int
1193 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1194                     struct drm_framebuffer *old_fb)
1195 {
1196         struct drm_device *dev = crtc->dev;
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         struct drm_i915_master_private *master_priv;
1199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1200         struct intel_framebuffer *intel_fb;
1201         struct drm_i915_gem_object *obj_priv;
1202         struct drm_gem_object *obj;
1203         int pipe = intel_crtc->pipe;
1204         int plane = intel_crtc->plane;
1205         unsigned long Start, Offset;
1206         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1207         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1208         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1209         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1210         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1211         u32 dspcntr, alignment;
1212         int ret;
1213
1214         /* no fb bound */
1215         if (!crtc->fb) {
1216                 DRM_DEBUG_KMS("No FB bound\n");
1217                 return 0;
1218         }
1219
1220         switch (plane) {
1221         case 0:
1222         case 1:
1223                 break;
1224         default:
1225                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1226                 return -EINVAL;
1227         }
1228
1229         intel_fb = to_intel_framebuffer(crtc->fb);
1230         obj = intel_fb->obj;
1231         obj_priv = obj->driver_private;
1232
1233         switch (obj_priv->tiling_mode) {
1234         case I915_TILING_NONE:
1235                 alignment = 64 * 1024;
1236                 break;
1237         case I915_TILING_X:
1238                 /* pin() will align the object as required by fence */
1239                 alignment = 0;
1240                 break;
1241         case I915_TILING_Y:
1242                 /* FIXME: Is this true? */
1243                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1244                 return -EINVAL;
1245         default:
1246                 BUG();
1247         }
1248
1249         mutex_lock(&dev->struct_mutex);
1250         ret = i915_gem_object_pin(obj, alignment);
1251         if (ret != 0) {
1252                 mutex_unlock(&dev->struct_mutex);
1253                 return ret;
1254         }
1255
1256         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1257         if (ret != 0) {
1258                 i915_gem_object_unpin(obj);
1259                 mutex_unlock(&dev->struct_mutex);
1260                 return ret;
1261         }
1262
1263         /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1264          * whereas 965+ only requires a fence if using framebuffer compression.
1265          * For simplicity, we always install a fence as the cost is not that onerous.
1266          */
1267         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1268             obj_priv->tiling_mode != I915_TILING_NONE) {
1269                 ret = i915_gem_object_get_fence_reg(obj);
1270                 if (ret != 0) {
1271                         i915_gem_object_unpin(obj);
1272                         mutex_unlock(&dev->struct_mutex);
1273                         return ret;
1274                 }
1275         }
1276
1277         dspcntr = I915_READ(dspcntr_reg);
1278         /* Mask out pixel format bits in case we change it */
1279         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1280         switch (crtc->fb->bits_per_pixel) {
1281         case 8:
1282                 dspcntr |= DISPPLANE_8BPP;
1283                 break;
1284         case 16:
1285                 if (crtc->fb->depth == 15)
1286                         dspcntr |= DISPPLANE_15_16BPP;
1287                 else
1288                         dspcntr |= DISPPLANE_16BPP;
1289                 break;
1290         case 24:
1291         case 32:
1292                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1293                 break;
1294         default:
1295                 DRM_ERROR("Unknown color depth\n");
1296                 i915_gem_object_unpin(obj);
1297                 mutex_unlock(&dev->struct_mutex);
1298                 return -EINVAL;
1299         }
1300         if (IS_I965G(dev)) {
1301                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1302                         dspcntr |= DISPPLANE_TILED;
1303                 else
1304                         dspcntr &= ~DISPPLANE_TILED;
1305         }
1306
1307         if (IS_IGDNG(dev))
1308                 /* must disable */
1309                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1310
1311         I915_WRITE(dspcntr_reg, dspcntr);
1312
1313         Start = obj_priv->gtt_offset;
1314         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1315
1316         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1317         I915_WRITE(dspstride, crtc->fb->pitch);
1318         if (IS_I965G(dev)) {
1319                 I915_WRITE(dspbase, Offset);
1320                 I915_READ(dspbase);
1321                 I915_WRITE(dspsurf, Start);
1322                 I915_READ(dspsurf);
1323                 I915_WRITE(dsptileoff, (y << 16) | x);
1324         } else {
1325                 I915_WRITE(dspbase, Start + Offset);
1326                 I915_READ(dspbase);
1327         }
1328
1329         if ((IS_I965G(dev) || plane == 0))
1330                 intel_update_fbc(crtc, &crtc->mode);
1331
1332         intel_wait_for_vblank(dev);
1333
1334         if (old_fb) {
1335                 intel_fb = to_intel_framebuffer(old_fb);
1336                 obj_priv = intel_fb->obj->driver_private;
1337                 i915_gem_object_unpin(intel_fb->obj);
1338         }
1339         intel_increase_pllclock(crtc, true);
1340
1341         mutex_unlock(&dev->struct_mutex);
1342
1343         if (!dev->primary->master)
1344                 return 0;
1345
1346         master_priv = dev->primary->master->driver_priv;
1347         if (!master_priv->sarea_priv)
1348                 return 0;
1349
1350         if (pipe) {
1351                 master_priv->sarea_priv->pipeB_x = x;
1352                 master_priv->sarea_priv->pipeB_y = y;
1353         } else {
1354                 master_priv->sarea_priv->pipeA_x = x;
1355                 master_priv->sarea_priv->pipeA_y = y;
1356         }
1357
1358         return 0;
1359 }
1360
1361 /* Disable the VGA plane that we never use */
1362 static void i915_disable_vga (struct drm_device *dev)
1363 {
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         u8 sr1;
1366         u32 vga_reg;
1367
1368         if (IS_IGDNG(dev))
1369                 vga_reg = CPU_VGACNTRL;
1370         else
1371                 vga_reg = VGACNTRL;
1372
1373         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1374                 return;
1375
1376         I915_WRITE8(VGA_SR_INDEX, 1);
1377         sr1 = I915_READ8(VGA_SR_DATA);
1378         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1379         udelay(100);
1380
1381         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1382 }
1383
1384 static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1385 {
1386         struct drm_device *dev = crtc->dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         u32 dpa_ctl;
1389
1390         DRM_DEBUG_KMS("\n");
1391         dpa_ctl = I915_READ(DP_A);
1392         dpa_ctl &= ~DP_PLL_ENABLE;
1393         I915_WRITE(DP_A, dpa_ctl);
1394 }
1395
1396 static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1397 {
1398         struct drm_device *dev = crtc->dev;
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         u32 dpa_ctl;
1401
1402         dpa_ctl = I915_READ(DP_A);
1403         dpa_ctl |= DP_PLL_ENABLE;
1404         I915_WRITE(DP_A, dpa_ctl);
1405         udelay(200);
1406 }
1407
1408
1409 static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1410 {
1411         struct drm_device *dev = crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         u32 dpa_ctl;
1414
1415         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1416         dpa_ctl = I915_READ(DP_A);
1417         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1418
1419         if (clock < 200000) {
1420                 u32 temp;
1421                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1422                 /* workaround for 160Mhz:
1423                    1) program 0x4600c bits 15:0 = 0x8124
1424                    2) program 0x46010 bit 0 = 1
1425                    3) program 0x46034 bit 24 = 1
1426                    4) program 0x64000 bit 14 = 1
1427                    */
1428                 temp = I915_READ(0x4600c);
1429                 temp &= 0xffff0000;
1430                 I915_WRITE(0x4600c, temp | 0x8124);
1431
1432                 temp = I915_READ(0x46010);
1433                 I915_WRITE(0x46010, temp | 1);
1434
1435                 temp = I915_READ(0x46034);
1436                 I915_WRITE(0x46034, temp | (1 << 24));
1437         } else {
1438                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1439         }
1440         I915_WRITE(DP_A, dpa_ctl);
1441
1442         udelay(500);
1443 }
1444
1445 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1446 {
1447         struct drm_device *dev = crtc->dev;
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1450         int pipe = intel_crtc->pipe;
1451         int plane = intel_crtc->plane;
1452         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1453         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1454         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1455         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1456         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1457         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1458         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1459         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1460         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1461         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1462         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1463         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1464         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1465         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1466         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1467         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1468         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1469         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1470         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1471         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1472         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1473         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1474         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1475         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1476         u32 temp;
1477         int tries = 5, j, n;
1478
1479         /* XXX: When our outputs are all unaware of DPMS modes other than off
1480          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1481          */
1482         switch (mode) {
1483         case DRM_MODE_DPMS_ON:
1484         case DRM_MODE_DPMS_STANDBY:
1485         case DRM_MODE_DPMS_SUSPEND:
1486                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1487                 if (HAS_eDP) {
1488                         /* enable eDP PLL */
1489                         igdng_enable_pll_edp(crtc);
1490                 } else {
1491                         /* enable PCH DPLL */
1492                         temp = I915_READ(pch_dpll_reg);
1493                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1494                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1495                                 I915_READ(pch_dpll_reg);
1496                         }
1497
1498                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1499                         temp = I915_READ(fdi_rx_reg);
1500                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1501                                         FDI_SEL_PCDCLK |
1502                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1503                         I915_READ(fdi_rx_reg);
1504                         udelay(200);
1505
1506                         /* Enable CPU FDI TX PLL, always on for IGDNG */
1507                         temp = I915_READ(fdi_tx_reg);
1508                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1509                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1510                                 I915_READ(fdi_tx_reg);
1511                                 udelay(100);
1512                         }
1513                 }
1514
1515                 /* Enable panel fitting for LVDS */
1516                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1517                         temp = I915_READ(pf_ctl_reg);
1518                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1519
1520                         /* currently full aspect */
1521                         I915_WRITE(pf_win_pos, 0);
1522
1523                         I915_WRITE(pf_win_size,
1524                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1525                                    (dev_priv->panel_fixed_mode->vdisplay));
1526                 }
1527
1528                 /* Enable CPU pipe */
1529                 temp = I915_READ(pipeconf_reg);
1530                 if ((temp & PIPEACONF_ENABLE) == 0) {
1531                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1532                         I915_READ(pipeconf_reg);
1533                         udelay(100);
1534                 }
1535
1536                 /* configure and enable CPU plane */
1537                 temp = I915_READ(dspcntr_reg);
1538                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1539                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1540                         /* Flush the plane changes */
1541                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1542                 }
1543
1544                 if (!HAS_eDP) {
1545                         /* enable CPU FDI TX and PCH FDI RX */
1546                         temp = I915_READ(fdi_tx_reg);
1547                         temp |= FDI_TX_ENABLE;
1548                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1549                         temp &= ~FDI_LINK_TRAIN_NONE;
1550                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1551                         I915_WRITE(fdi_tx_reg, temp);
1552                         I915_READ(fdi_tx_reg);
1553
1554                         temp = I915_READ(fdi_rx_reg);
1555                         temp &= ~FDI_LINK_TRAIN_NONE;
1556                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1557                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1558                         I915_READ(fdi_rx_reg);
1559
1560                         udelay(150);
1561
1562                         /* Train FDI. */
1563                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1564                            for train result */
1565                         temp = I915_READ(fdi_rx_imr_reg);
1566                         temp &= ~FDI_RX_SYMBOL_LOCK;
1567                         temp &= ~FDI_RX_BIT_LOCK;
1568                         I915_WRITE(fdi_rx_imr_reg, temp);
1569                         I915_READ(fdi_rx_imr_reg);
1570                         udelay(150);
1571
1572                         temp = I915_READ(fdi_rx_iir_reg);
1573                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1574
1575                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1576                                 for (j = 0; j < tries; j++) {
1577                                         temp = I915_READ(fdi_rx_iir_reg);
1578                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1579                                                                 temp);
1580                                         if (temp & FDI_RX_BIT_LOCK)
1581                                                 break;
1582                                         udelay(200);
1583                                 }
1584                                 if (j != tries)
1585                                         I915_WRITE(fdi_rx_iir_reg,
1586                                                         temp | FDI_RX_BIT_LOCK);
1587                                 else
1588                                         DRM_DEBUG_KMS("train 1 fail\n");
1589                         } else {
1590                                 I915_WRITE(fdi_rx_iir_reg,
1591                                                 temp | FDI_RX_BIT_LOCK);
1592                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1593                         }
1594                         temp = I915_READ(fdi_tx_reg);
1595                         temp &= ~FDI_LINK_TRAIN_NONE;
1596                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1597                         I915_WRITE(fdi_tx_reg, temp);
1598
1599                         temp = I915_READ(fdi_rx_reg);
1600                         temp &= ~FDI_LINK_TRAIN_NONE;
1601                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1602                         I915_WRITE(fdi_rx_reg, temp);
1603
1604                         udelay(150);
1605
1606                         temp = I915_READ(fdi_rx_iir_reg);
1607                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1608
1609                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1610                                 for (j = 0; j < tries; j++) {
1611                                         temp = I915_READ(fdi_rx_iir_reg);
1612                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1613                                                                 temp);
1614                                         if (temp & FDI_RX_SYMBOL_LOCK)
1615                                                 break;
1616                                         udelay(200);
1617                                 }
1618                                 if (j != tries) {
1619                                         I915_WRITE(fdi_rx_iir_reg,
1620                                                         temp | FDI_RX_SYMBOL_LOCK);
1621                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1622                                 } else
1623                                         DRM_DEBUG_KMS("train 2 fail\n");
1624                         } else {
1625                                 I915_WRITE(fdi_rx_iir_reg,
1626                                                 temp | FDI_RX_SYMBOL_LOCK);
1627                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1628                         }
1629                         DRM_DEBUG_KMS("train done\n");
1630
1631                         /* set transcoder timing */
1632                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1633                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1634                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1635
1636                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1637                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1638                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1639
1640                         /* enable PCH transcoder */
1641                         temp = I915_READ(transconf_reg);
1642                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1643                         I915_READ(transconf_reg);
1644
1645                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1646                                 ;
1647
1648                         /* enable normal */
1649
1650                         temp = I915_READ(fdi_tx_reg);
1651                         temp &= ~FDI_LINK_TRAIN_NONE;
1652                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1653                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1654                         I915_READ(fdi_tx_reg);
1655
1656                         temp = I915_READ(fdi_rx_reg);
1657                         temp &= ~FDI_LINK_TRAIN_NONE;
1658                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1659                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1660                         I915_READ(fdi_rx_reg);
1661
1662                         /* wait one idle pattern time */
1663                         udelay(100);
1664
1665                 }
1666
1667                 intel_crtc_load_lut(crtc);
1668
1669         break;
1670         case DRM_MODE_DPMS_OFF:
1671                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1672
1673                 i915_disable_vga(dev);
1674
1675                 /* Disable display plane */
1676                 temp = I915_READ(dspcntr_reg);
1677                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1678                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1679                         /* Flush the plane changes */
1680                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1681                         I915_READ(dspbase_reg);
1682                 }
1683
1684                 /* disable cpu pipe, disable after all planes disabled */
1685                 temp = I915_READ(pipeconf_reg);
1686                 if ((temp & PIPEACONF_ENABLE) != 0) {
1687                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1688                         I915_READ(pipeconf_reg);
1689                         n = 0;
1690                         /* wait for cpu pipe off, pipe state */
1691                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1692                                 n++;
1693                                 if (n < 60) {
1694                                         udelay(500);
1695                                         continue;
1696                                 } else {
1697                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1698                                                                 pipe);
1699                                         break;
1700                                 }
1701                         }
1702                 } else
1703                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1704
1705                 if (HAS_eDP) {
1706                         igdng_disable_pll_edp(crtc);
1707                 }
1708
1709                 /* disable CPU FDI tx and PCH FDI rx */
1710                 temp = I915_READ(fdi_tx_reg);
1711                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1712                 I915_READ(fdi_tx_reg);
1713
1714                 temp = I915_READ(fdi_rx_reg);
1715                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1716                 I915_READ(fdi_rx_reg);
1717
1718                 udelay(100);
1719
1720                 /* still set train pattern 1 */
1721                 temp = I915_READ(fdi_tx_reg);
1722                 temp &= ~FDI_LINK_TRAIN_NONE;
1723                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1724                 I915_WRITE(fdi_tx_reg, temp);
1725
1726                 temp = I915_READ(fdi_rx_reg);
1727                 temp &= ~FDI_LINK_TRAIN_NONE;
1728                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1729                 I915_WRITE(fdi_rx_reg, temp);
1730
1731                 udelay(100);
1732
1733                 /* disable PCH transcoder */
1734                 temp = I915_READ(transconf_reg);
1735                 if ((temp & TRANS_ENABLE) != 0) {
1736                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1737                         I915_READ(transconf_reg);
1738                         n = 0;
1739                         /* wait for PCH transcoder off, transcoder state */
1740                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1741                                 n++;
1742                                 if (n < 60) {
1743                                         udelay(500);
1744                                         continue;
1745                                 } else {
1746                                         DRM_DEBUG_KMS("transcoder %d off "
1747                                                         "delay\n", pipe);
1748                                         break;
1749                                 }
1750                         }
1751                 }
1752
1753                 /* disable PCH DPLL */
1754                 temp = I915_READ(pch_dpll_reg);
1755                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1756                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1757                         I915_READ(pch_dpll_reg);
1758                 }
1759
1760                 temp = I915_READ(fdi_rx_reg);
1761                 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1762                         temp &= ~FDI_SEL_PCDCLK;
1763                         temp &= ~FDI_RX_PLL_ENABLE;
1764                         I915_WRITE(fdi_rx_reg, temp);
1765                         I915_READ(fdi_rx_reg);
1766                 }
1767
1768                 /* Disable CPU FDI TX PLL */
1769                 temp = I915_READ(fdi_tx_reg);
1770                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1771                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1772                         I915_READ(fdi_tx_reg);
1773                         udelay(100);
1774                 }
1775
1776                 /* Disable PF */
1777                 temp = I915_READ(pf_ctl_reg);
1778                 if ((temp & PF_ENABLE) != 0) {
1779                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1780                         I915_READ(pf_ctl_reg);
1781                 }
1782                 I915_WRITE(pf_win_size, 0);
1783
1784                 /* Wait for the clocks to turn off. */
1785                 udelay(150);
1786                 break;
1787         }
1788 }
1789
1790 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1791 {
1792         struct intel_overlay *overlay;
1793         int ret;
1794
1795         if (!enable && intel_crtc->overlay) {
1796                 overlay = intel_crtc->overlay;
1797                 mutex_lock(&overlay->dev->struct_mutex);
1798                 for (;;) {
1799                         ret = intel_overlay_switch_off(overlay);
1800                         if (ret == 0)
1801                                 break;
1802
1803                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1804                         if (ret != 0) {
1805                                 /* overlay doesn't react anymore. Usually
1806                                  * results in a black screen and an unkillable
1807                                  * X server. */
1808                                 BUG();
1809                                 overlay->hw_wedged = HW_WEDGED;
1810                                 break;
1811                         }
1812                 }
1813                 mutex_unlock(&overlay->dev->struct_mutex);
1814         }
1815         /* Let userspace switch the overlay on again. In most cases userspace
1816          * has to recompute where to put it anyway. */
1817
1818         return;
1819 }
1820
1821 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1822 {
1823         struct drm_device *dev = crtc->dev;
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1826         int pipe = intel_crtc->pipe;
1827         int plane = intel_crtc->plane;
1828         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1829         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1830         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1831         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1832         u32 temp;
1833
1834         /* XXX: When our outputs are all unaware of DPMS modes other than off
1835          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1836          */
1837         switch (mode) {
1838         case DRM_MODE_DPMS_ON:
1839         case DRM_MODE_DPMS_STANDBY:
1840         case DRM_MODE_DPMS_SUSPEND:
1841                 intel_update_watermarks(dev);
1842
1843                 /* Enable the DPLL */
1844                 temp = I915_READ(dpll_reg);
1845                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1846                         I915_WRITE(dpll_reg, temp);
1847                         I915_READ(dpll_reg);
1848                         /* Wait for the clocks to stabilize. */
1849                         udelay(150);
1850                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1851                         I915_READ(dpll_reg);
1852                         /* Wait for the clocks to stabilize. */
1853                         udelay(150);
1854                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1855                         I915_READ(dpll_reg);
1856                         /* Wait for the clocks to stabilize. */
1857                         udelay(150);
1858                 }
1859
1860                 /* Enable the pipe */
1861                 temp = I915_READ(pipeconf_reg);
1862                 if ((temp & PIPEACONF_ENABLE) == 0)
1863                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1864
1865                 /* Enable the plane */
1866                 temp = I915_READ(dspcntr_reg);
1867                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1868                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1869                         /* Flush the plane changes */
1870                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1871                 }
1872
1873                 intel_crtc_load_lut(crtc);
1874
1875                 if ((IS_I965G(dev) || plane == 0))
1876                         intel_update_fbc(crtc, &crtc->mode);
1877
1878                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1879                 intel_crtc_dpms_overlay(intel_crtc, true);
1880         break;
1881         case DRM_MODE_DPMS_OFF:
1882                 intel_update_watermarks(dev);
1883
1884                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1885                 intel_crtc_dpms_overlay(intel_crtc, false);
1886
1887                 if (dev_priv->cfb_plane == plane &&
1888                     dev_priv->display.disable_fbc)
1889                         dev_priv->display.disable_fbc(dev);
1890
1891                 /* Disable the VGA plane that we never use */
1892                 i915_disable_vga(dev);
1893
1894                 /* Disable display plane */
1895                 temp = I915_READ(dspcntr_reg);
1896                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1897                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1898                         /* Flush the plane changes */
1899                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1900                         I915_READ(dspbase_reg);
1901                 }
1902
1903                 if (!IS_I9XX(dev)) {
1904                         /* Wait for vblank for the disable to take effect */
1905                         intel_wait_for_vblank(dev);
1906                 }
1907
1908                 /* Next, disable display pipes */
1909                 temp = I915_READ(pipeconf_reg);
1910                 if ((temp & PIPEACONF_ENABLE) != 0) {
1911                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1912                         I915_READ(pipeconf_reg);
1913                 }
1914
1915                 /* Wait for vblank for the disable to take effect. */
1916                 intel_wait_for_vblank(dev);
1917
1918                 temp = I915_READ(dpll_reg);
1919                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1920                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1921                         I915_READ(dpll_reg);
1922                 }
1923
1924                 /* Wait for the clocks to turn off. */
1925                 udelay(150);
1926                 break;
1927         }
1928 }
1929
1930 /**
1931  * Sets the power management mode of the pipe and plane.
1932  *
1933  * This code should probably grow support for turning the cursor off and back
1934  * on appropriately at the same time as we're turning the pipe off/on.
1935  */
1936 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1937 {
1938         struct drm_device *dev = crtc->dev;
1939         struct drm_i915_private *dev_priv = dev->dev_private;
1940         struct drm_i915_master_private *master_priv;
1941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1942         int pipe = intel_crtc->pipe;
1943         bool enabled;
1944
1945         dev_priv->display.dpms(crtc, mode);
1946
1947         intel_crtc->dpms_mode = mode;
1948
1949         if (!dev->primary->master)
1950                 return;
1951
1952         master_priv = dev->primary->master->driver_priv;
1953         if (!master_priv->sarea_priv)
1954                 return;
1955
1956         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1957
1958         switch (pipe) {
1959         case 0:
1960                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1961                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1962                 break;
1963         case 1:
1964                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1965                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1966                 break;
1967         default:
1968                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1969                 break;
1970         }
1971 }
1972
1973 static void intel_crtc_prepare (struct drm_crtc *crtc)
1974 {
1975         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1976         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1977 }
1978
1979 static void intel_crtc_commit (struct drm_crtc *crtc)
1980 {
1981         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1982         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1983 }
1984
1985 void intel_encoder_prepare (struct drm_encoder *encoder)
1986 {
1987         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1988         /* lvds has its own version of prepare see intel_lvds_prepare */
1989         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1990 }
1991
1992 void intel_encoder_commit (struct drm_encoder *encoder)
1993 {
1994         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1995         /* lvds has its own version of commit see intel_lvds_commit */
1996         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1997 }
1998
1999 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2000                                   struct drm_display_mode *mode,
2001                                   struct drm_display_mode *adjusted_mode)
2002 {
2003         struct drm_device *dev = crtc->dev;
2004         if (IS_IGDNG(dev)) {
2005                 /* FDI link clock is fixed at 2.7G */
2006                 if (mode->clock * 3 > 27000 * 4)
2007                         return MODE_CLOCK_HIGH;
2008         }
2009         return true;
2010 }
2011
2012 static int i945_get_display_clock_speed(struct drm_device *dev)
2013 {
2014         return 400000;
2015 }
2016
2017 static int i915_get_display_clock_speed(struct drm_device *dev)
2018 {
2019         return 333000;
2020 }
2021
2022 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2023 {
2024         return 200000;
2025 }
2026
2027 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2028 {
2029         u16 gcfgc = 0;
2030
2031         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2032
2033         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2034                 return 133000;
2035         else {
2036                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2037                 case GC_DISPLAY_CLOCK_333_MHZ:
2038                         return 333000;
2039                 default:
2040                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2041                         return 190000;
2042                 }
2043         }
2044 }
2045
2046 static int i865_get_display_clock_speed(struct drm_device *dev)
2047 {
2048         return 266000;
2049 }
2050
2051 static int i855_get_display_clock_speed(struct drm_device *dev)
2052 {
2053         u16 hpllcc = 0;
2054         /* Assume that the hardware is in the high speed state.  This
2055          * should be the default.
2056          */
2057         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2058         case GC_CLOCK_133_200:
2059         case GC_CLOCK_100_200:
2060                 return 200000;
2061         case GC_CLOCK_166_250:
2062                 return 250000;
2063         case GC_CLOCK_100_133:
2064                 return 133000;
2065         }
2066
2067         /* Shouldn't happen */
2068         return 0;
2069 }
2070
2071 static int i830_get_display_clock_speed(struct drm_device *dev)
2072 {
2073         return 133000;
2074 }
2075
2076 /**
2077  * Return the pipe currently connected to the panel fitter,
2078  * or -1 if the panel fitter is not present or not in use
2079  */
2080 int intel_panel_fitter_pipe (struct drm_device *dev)
2081 {
2082         struct drm_i915_private *dev_priv = dev->dev_private;
2083         u32  pfit_control;
2084
2085         /* i830 doesn't have a panel fitter */
2086         if (IS_I830(dev))
2087                 return -1;
2088
2089         pfit_control = I915_READ(PFIT_CONTROL);
2090
2091         /* See if the panel fitter is in use */
2092         if ((pfit_control & PFIT_ENABLE) == 0)
2093                 return -1;
2094
2095         /* 965 can place panel fitter on either pipe */
2096         if (IS_I965G(dev))
2097                 return (pfit_control >> 29) & 0x3;
2098
2099         /* older chips can only use pipe 1 */
2100         return 1;
2101 }
2102
2103 struct fdi_m_n {
2104         u32        tu;
2105         u32        gmch_m;
2106         u32        gmch_n;
2107         u32        link_m;
2108         u32        link_n;
2109 };
2110
2111 static void
2112 fdi_reduce_ratio(u32 *num, u32 *den)
2113 {
2114         while (*num > 0xffffff || *den > 0xffffff) {
2115                 *num >>= 1;
2116                 *den >>= 1;
2117         }
2118 }
2119
2120 #define DATA_N 0x800000
2121 #define LINK_N 0x80000
2122
2123 static void
2124 igdng_compute_m_n(int bits_per_pixel, int nlanes,
2125                 int pixel_clock, int link_clock,
2126                 struct fdi_m_n *m_n)
2127 {
2128         u64 temp;
2129
2130         m_n->tu = 64; /* default size */
2131
2132         temp = (u64) DATA_N * pixel_clock;
2133         temp = div_u64(temp, link_clock);
2134         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2135         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2136         m_n->gmch_n = DATA_N;
2137         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2138
2139         temp = (u64) LINK_N * pixel_clock;
2140         m_n->link_m = div_u64(temp, link_clock);
2141         m_n->link_n = LINK_N;
2142         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2143 }
2144
2145
2146 struct intel_watermark_params {
2147         unsigned long fifo_size;
2148         unsigned long max_wm;
2149         unsigned long default_wm;
2150         unsigned long guard_size;
2151         unsigned long cacheline_size;
2152 };
2153
2154 /* IGD has different values for various configs */
2155 static struct intel_watermark_params igd_display_wm = {
2156         IGD_DISPLAY_FIFO,
2157         IGD_MAX_WM,
2158         IGD_DFT_WM,
2159         IGD_GUARD_WM,
2160         IGD_FIFO_LINE_SIZE
2161 };
2162 static struct intel_watermark_params igd_display_hplloff_wm = {
2163         IGD_DISPLAY_FIFO,
2164         IGD_MAX_WM,
2165         IGD_DFT_HPLLOFF_WM,
2166         IGD_GUARD_WM,
2167         IGD_FIFO_LINE_SIZE
2168 };
2169 static struct intel_watermark_params igd_cursor_wm = {
2170         IGD_CURSOR_FIFO,
2171         IGD_CURSOR_MAX_WM,
2172         IGD_CURSOR_DFT_WM,
2173         IGD_CURSOR_GUARD_WM,
2174         IGD_FIFO_LINE_SIZE,
2175 };
2176 static struct intel_watermark_params igd_cursor_hplloff_wm = {
2177         IGD_CURSOR_FIFO,
2178         IGD_CURSOR_MAX_WM,
2179         IGD_CURSOR_DFT_WM,
2180         IGD_CURSOR_GUARD_WM,
2181         IGD_FIFO_LINE_SIZE
2182 };
2183 static struct intel_watermark_params g4x_wm_info = {
2184         G4X_FIFO_SIZE,
2185         G4X_MAX_WM,
2186         G4X_MAX_WM,
2187         2,
2188         G4X_FIFO_LINE_SIZE,
2189 };
2190 static struct intel_watermark_params i945_wm_info = {
2191         I945_FIFO_SIZE,
2192         I915_MAX_WM,
2193         1,
2194         2,
2195         I915_FIFO_LINE_SIZE
2196 };
2197 static struct intel_watermark_params i915_wm_info = {
2198         I915_FIFO_SIZE,
2199         I915_MAX_WM,
2200         1,
2201         2,
2202         I915_FIFO_LINE_SIZE
2203 };
2204 static struct intel_watermark_params i855_wm_info = {
2205         I855GM_FIFO_SIZE,
2206         I915_MAX_WM,
2207         1,
2208         2,
2209         I830_FIFO_LINE_SIZE
2210 };
2211 static struct intel_watermark_params i830_wm_info = {
2212         I830_FIFO_SIZE,
2213         I915_MAX_WM,
2214         1,
2215         2,
2216         I830_FIFO_LINE_SIZE
2217 };
2218
2219 /**
2220  * intel_calculate_wm - calculate watermark level
2221  * @clock_in_khz: pixel clock
2222  * @wm: chip FIFO params
2223  * @pixel_size: display pixel size
2224  * @latency_ns: memory latency for the platform
2225  *
2226  * Calculate the watermark level (the level at which the display plane will
2227  * start fetching from memory again).  Each chip has a different display
2228  * FIFO size and allocation, so the caller needs to figure that out and pass
2229  * in the correct intel_watermark_params structure.
2230  *
2231  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2232  * on the pixel size.  When it reaches the watermark level, it'll start
2233  * fetching FIFO line sized based chunks from memory until the FIFO fills
2234  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2235  * will occur, and a display engine hang could result.
2236  */
2237 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2238                                         struct intel_watermark_params *wm,
2239                                         int pixel_size,
2240                                         unsigned long latency_ns)
2241 {
2242         long entries_required, wm_size;
2243
2244         /*
2245          * Note: we need to make sure we don't overflow for various clock &
2246          * latency values.
2247          * clocks go from a few thousand to several hundred thousand.
2248          * latency is usually a few thousand
2249          */
2250         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2251                 1000;
2252         entries_required /= wm->cacheline_size;
2253
2254         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2255
2256         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2257
2258         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2259
2260         /* Don't promote wm_size to unsigned... */
2261         if (wm_size > (long)wm->max_wm)
2262                 wm_size = wm->max_wm;
2263         if (wm_size <= 0)
2264                 wm_size = wm->default_wm;
2265         return wm_size;
2266 }
2267
2268 struct cxsr_latency {
2269         int is_desktop;
2270         unsigned long fsb_freq;
2271         unsigned long mem_freq;
2272         unsigned long display_sr;
2273         unsigned long display_hpll_disable;
2274         unsigned long cursor_sr;
2275         unsigned long cursor_hpll_disable;
2276 };
2277
2278 static struct cxsr_latency cxsr_latency_table[] = {
2279         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2280         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2281         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2282
2283         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2284         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2285         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2286
2287         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2288         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2289         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2290
2291         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2292         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2293         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2294
2295         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2296         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2297         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2298
2299         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2300         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2301         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2302 };
2303
2304 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2305                                                    int mem)
2306 {
2307         int i;
2308         struct cxsr_latency *latency;
2309
2310         if (fsb == 0 || mem == 0)
2311                 return NULL;
2312
2313         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2314                 latency = &cxsr_latency_table[i];
2315                 if (is_desktop == latency->is_desktop &&
2316                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2317                         return latency;
2318         }
2319
2320         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2321
2322         return NULL;
2323 }
2324
2325 static void igd_disable_cxsr(struct drm_device *dev)
2326 {
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328         u32 reg;
2329
2330         /* deactivate cxsr */
2331         reg = I915_READ(DSPFW3);
2332         reg &= ~(IGD_SELF_REFRESH_EN);
2333         I915_WRITE(DSPFW3, reg);
2334         DRM_INFO("Big FIFO is disabled\n");
2335 }
2336
2337 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
2338                             int pixel_size)
2339 {
2340         struct drm_i915_private *dev_priv = dev->dev_private;
2341         u32 reg;
2342         unsigned long wm;
2343         struct cxsr_latency *latency;
2344
2345         latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
2346                 dev_priv->mem_freq);
2347         if (!latency) {
2348                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2349                 igd_disable_cxsr(dev);
2350                 return;
2351         }
2352
2353         /* Display SR */
2354         wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
2355                                 latency->display_sr);
2356         reg = I915_READ(DSPFW1);
2357         reg &= 0x7fffff;
2358         reg |= wm << 23;
2359         I915_WRITE(DSPFW1, reg);
2360         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2361
2362         /* cursor SR */
2363         wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
2364                                 latency->cursor_sr);
2365         reg = I915_READ(DSPFW3);
2366         reg &= ~(0x3f << 24);
2367         reg |= (wm & 0x3f) << 24;
2368         I915_WRITE(DSPFW3, reg);
2369
2370         /* Display HPLL off SR */
2371         wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
2372                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2373         reg = I915_READ(DSPFW3);
2374         reg &= 0xfffffe00;
2375         reg |= wm & 0x1ff;
2376         I915_WRITE(DSPFW3, reg);
2377
2378         /* cursor HPLL off SR */
2379         wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
2380                                 latency->cursor_hpll_disable);
2381         reg = I915_READ(DSPFW3);
2382         reg &= ~(0x3f << 16);
2383         reg |= (wm & 0x3f) << 16;
2384         I915_WRITE(DSPFW3, reg);
2385         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2386
2387         /* activate cxsr */
2388         reg = I915_READ(DSPFW3);
2389         reg |= IGD_SELF_REFRESH_EN;
2390         I915_WRITE(DSPFW3, reg);
2391
2392         DRM_INFO("Big FIFO is enabled\n");
2393
2394         return;
2395 }
2396
2397 /*
2398  * Latency for FIFO fetches is dependent on several factors:
2399  *   - memory configuration (speed, channels)
2400  *   - chipset
2401  *   - current MCH state
2402  * It can be fairly high in some situations, so here we assume a fairly
2403  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2404  * set this value too high, the FIFO will fetch frequently to stay full)
2405  * and power consumption (set it too low to save power and we might see
2406  * FIFO underruns and display "flicker").
2407  *
2408  * A value of 5us seems to be a good balance; safe for very low end
2409  * platforms but not overly aggressive on lower latency configs.
2410  */
2411 const static int latency_ns = 5000;
2412
2413 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2414 {
2415         struct drm_i915_private *dev_priv = dev->dev_private;
2416         uint32_t dsparb = I915_READ(DSPARB);
2417         int size;
2418
2419         if (plane == 0)
2420                 size = dsparb & 0x7f;
2421         else
2422                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2423                         (dsparb & 0x7f);
2424
2425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2426                         plane ? "B" : "A", size);
2427
2428         return size;
2429 }
2430
2431 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2432 {
2433         struct drm_i915_private *dev_priv = dev->dev_private;
2434         uint32_t dsparb = I915_READ(DSPARB);
2435         int size;
2436
2437         if (plane == 0)
2438                 size = dsparb & 0x1ff;
2439         else
2440                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2441                         (dsparb & 0x1ff);
2442         size >>= 1; /* Convert to cachelines */
2443
2444         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2445                         plane ? "B" : "A", size);
2446
2447         return size;
2448 }
2449
2450 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2451 {
2452         struct drm_i915_private *dev_priv = dev->dev_private;
2453         uint32_t dsparb = I915_READ(DSPARB);
2454         int size;
2455
2456         size = dsparb & 0x7f;
2457         size >>= 2; /* Convert to cachelines */
2458
2459         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2460                         plane ? "B" : "A",
2461                   size);
2462
2463         return size;
2464 }
2465
2466 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2467 {
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         uint32_t dsparb = I915_READ(DSPARB);
2470         int size;
2471
2472         size = dsparb & 0x7f;
2473         size >>= 1; /* Convert to cachelines */
2474
2475         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2476                         plane ? "B" : "A", size);
2477
2478         return size;
2479 }
2480
2481 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2482                           int planeb_clock, int sr_hdisplay, int pixel_size)
2483 {
2484         struct drm_i915_private *dev_priv = dev->dev_private;
2485         int total_size, cacheline_size;
2486         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2487         struct intel_watermark_params planea_params, planeb_params;
2488         unsigned long line_time_us;
2489         int sr_clock, sr_entries = 0, entries_required;
2490
2491         /* Create copies of the base settings for each pipe */
2492         planea_params = planeb_params = g4x_wm_info;
2493
2494         /* Grab a couple of global values before we overwrite them */
2495         total_size = planea_params.fifo_size;
2496         cacheline_size = planea_params.cacheline_size;
2497
2498         /*
2499          * Note: we need to make sure we don't overflow for various clock &
2500          * latency values.
2501          * clocks go from a few thousand to several hundred thousand.
2502          * latency is usually a few thousand
2503          */
2504         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2505                 1000;
2506         entries_required /= G4X_FIFO_LINE_SIZE;
2507         planea_wm = entries_required + planea_params.guard_size;
2508
2509         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2510                 1000;
2511         entries_required /= G4X_FIFO_LINE_SIZE;
2512         planeb_wm = entries_required + planeb_params.guard_size;
2513
2514         cursora_wm = cursorb_wm = 16;
2515         cursor_sr = 32;
2516
2517         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2518
2519         /* Calc sr entries for one plane configs */
2520         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2521                 /* self-refresh has much higher latency */
2522                 const static int sr_latency_ns = 12000;
2523
2524                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2525                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2526
2527                 /* Use ns/us then divide to preserve precision */
2528                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2529                               pixel_size * sr_hdisplay) / 1000;
2530                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2531                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2532                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2533         }
2534
2535         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2536                   planea_wm, planeb_wm, sr_entries);
2537
2538         planea_wm &= 0x3f;
2539         planeb_wm &= 0x3f;
2540
2541         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2542                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2543                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2544         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2545                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2546         /* HPLL off in SR has some issues on G4x... disable it */
2547         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2548                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2549 }
2550
2551 static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
2552                            int unused3, int unused4)
2553 {
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555
2556         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2557
2558         /* 965 has limitations... */
2559         I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
2560         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2561 }
2562
2563 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2564                            int planeb_clock, int sr_hdisplay, int pixel_size)
2565 {
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         uint32_t fwater_lo;
2568         uint32_t fwater_hi;
2569         int total_size, cacheline_size, cwm, srwm = 1;
2570         int planea_wm, planeb_wm;
2571         struct intel_watermark_params planea_params, planeb_params;
2572         unsigned long line_time_us;
2573         int sr_clock, sr_entries = 0;
2574
2575         /* Create copies of the base settings for each pipe */
2576         if (IS_I965GM(dev) || IS_I945GM(dev))
2577                 planea_params = planeb_params = i945_wm_info;
2578         else if (IS_I9XX(dev))
2579                 planea_params = planeb_params = i915_wm_info;
2580         else
2581                 planea_params = planeb_params = i855_wm_info;
2582
2583         /* Grab a couple of global values before we overwrite them */
2584         total_size = planea_params.fifo_size;
2585         cacheline_size = planea_params.cacheline_size;
2586
2587         /* Update per-plane FIFO sizes */
2588         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2589         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2590
2591         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2592                                        pixel_size, latency_ns);
2593         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2594                                        pixel_size, latency_ns);
2595         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2596
2597         /*
2598          * Overlay gets an aggressive default since video jitter is bad.
2599          */
2600         cwm = 2;
2601
2602         /* Calc sr entries for one plane configs */
2603         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2604             (!planea_clock || !planeb_clock)) {
2605                 /* self-refresh has much higher latency */
2606                 const static int sr_latency_ns = 6000;
2607
2608                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2609                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2610
2611                 /* Use ns/us then divide to preserve precision */
2612                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2613                               pixel_size * sr_hdisplay) / 1000;
2614                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2615                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2616                 srwm = total_size - sr_entries;
2617                 if (srwm < 0)
2618                         srwm = 1;
2619                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2620         }
2621
2622         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2623                   planea_wm, planeb_wm, cwm, srwm);
2624
2625         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2626         fwater_hi = (cwm & 0x1f);
2627
2628         /* Set request length to 8 cachelines per fetch */
2629         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2630         fwater_hi = fwater_hi | (1 << 8);
2631
2632         I915_WRITE(FW_BLC, fwater_lo);
2633         I915_WRITE(FW_BLC2, fwater_hi);
2634 }
2635
2636 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2637                            int unused2, int pixel_size)
2638 {
2639         struct drm_i915_private *dev_priv = dev->dev_private;
2640         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2641         int planea_wm;
2642
2643         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2644
2645         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2646                                        pixel_size, latency_ns);
2647         fwater_lo |= (3<<8) | planea_wm;
2648
2649         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2650
2651         I915_WRITE(FW_BLC, fwater_lo);
2652 }
2653
2654 /**
2655  * intel_update_watermarks - update FIFO watermark values based on current modes
2656  *
2657  * Calculate watermark values for the various WM regs based on current mode
2658  * and plane configuration.
2659  *
2660  * There are several cases to deal with here:
2661  *   - normal (i.e. non-self-refresh)
2662  *   - self-refresh (SR) mode
2663  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2664  *   - lines are small relative to FIFO size (buffer can hold more than 2
2665  *     lines), so need to account for TLB latency
2666  *
2667  *   The normal calculation is:
2668  *     watermark = dotclock * bytes per pixel * latency
2669  *   where latency is platform & configuration dependent (we assume pessimal
2670  *   values here).
2671  *
2672  *   The SR calculation is:
2673  *     watermark = (trunc(latency/line time)+1) * surface width *
2674  *       bytes per pixel
2675  *   where
2676  *     line time = htotal / dotclock
2677  *   and latency is assumed to be high, as above.
2678  *
2679  * The final value programmed to the register should always be rounded up,
2680  * and include an extra 2 entries to account for clock crossings.
2681  *
2682  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2683  * to set the non-SR watermarks to 8.
2684   */
2685 static void intel_update_watermarks(struct drm_device *dev)
2686 {
2687         struct drm_i915_private *dev_priv = dev->dev_private;
2688         struct drm_crtc *crtc;
2689         struct intel_crtc *intel_crtc;
2690         int sr_hdisplay = 0;
2691         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2692         int enabled = 0, pixel_size = 0;
2693
2694         if (!dev_priv->display.update_wm)
2695                 return;
2696
2697         /* Get the clock config from both planes */
2698         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2699                 intel_crtc = to_intel_crtc(crtc);
2700                 if (crtc->enabled) {
2701                         enabled++;
2702                         if (intel_crtc->plane == 0) {
2703                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2704                                           intel_crtc->pipe, crtc->mode.clock);
2705                                 planea_clock = crtc->mode.clock;
2706                         } else {
2707                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2708                                           intel_crtc->pipe, crtc->mode.clock);
2709                                 planeb_clock = crtc->mode.clock;
2710                         }
2711                         sr_hdisplay = crtc->mode.hdisplay;
2712                         sr_clock = crtc->mode.clock;
2713                         if (crtc->fb)
2714                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2715                         else
2716                                 pixel_size = 4; /* by default */
2717                 }
2718         }
2719
2720         if (enabled <= 0)
2721                 return;
2722
2723         /* Single plane configs can enable self refresh */
2724         if (enabled == 1 && IS_IGD(dev))
2725                 igd_enable_cxsr(dev, sr_clock, pixel_size);
2726         else if (IS_IGD(dev))
2727                 igd_disable_cxsr(dev);
2728
2729         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2730                                     sr_hdisplay, pixel_size);
2731 }
2732
2733 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2734                                struct drm_display_mode *mode,
2735                                struct drm_display_mode *adjusted_mode,
2736                                int x, int y,
2737                                struct drm_framebuffer *old_fb)
2738 {
2739         struct drm_device *dev = crtc->dev;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742         int pipe = intel_crtc->pipe;
2743         int plane = intel_crtc->plane;
2744         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2745         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2746         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2747         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2748         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2749         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2750         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2751         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2752         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2753         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2754         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2755         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2756         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2757         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2758         int refclk, num_outputs = 0;
2759         intel_clock_t clock, reduced_clock;
2760         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2761         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2762         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2763         bool is_edp = false;
2764         struct drm_mode_config *mode_config = &dev->mode_config;
2765         struct drm_connector *connector;
2766         const intel_limit_t *limit;
2767         int ret;
2768         struct fdi_m_n m_n = {0};
2769         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2770         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2771         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2772         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2773         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2774         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2775         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2776         int lvds_reg = LVDS;
2777         u32 temp;
2778         int sdvo_pixel_multiply;
2779         int target_clock;
2780
2781         drm_vblank_pre_modeset(dev, pipe);
2782
2783         list_for_each_entry(connector, &mode_config->connector_list, head) {
2784                 struct intel_output *intel_output = to_intel_output(connector);
2785
2786                 if (!connector->encoder || connector->encoder->crtc != crtc)
2787                         continue;
2788
2789                 switch (intel_output->type) {
2790                 case INTEL_OUTPUT_LVDS:
2791                         is_lvds = true;
2792                         break;
2793                 case INTEL_OUTPUT_SDVO:
2794                 case INTEL_OUTPUT_HDMI:
2795                         is_sdvo = true;
2796                         if (intel_output->needs_tv_clock)
2797                                 is_tv = true;
2798                         break;
2799                 case INTEL_OUTPUT_DVO:
2800                         is_dvo = true;
2801                         break;
2802                 case INTEL_OUTPUT_TVOUT:
2803                         is_tv = true;
2804                         break;
2805                 case INTEL_OUTPUT_ANALOG:
2806                         is_crt = true;
2807                         break;
2808                 case INTEL_OUTPUT_DISPLAYPORT:
2809                         is_dp = true;
2810                         break;
2811                 case INTEL_OUTPUT_EDP:
2812                         is_edp = true;
2813                         break;
2814                 }
2815
2816                 num_outputs++;
2817         }
2818
2819         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2820                 refclk = dev_priv->lvds_ssc_freq * 1000;
2821                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2822                                         refclk / 1000);
2823         } else if (IS_I9XX(dev)) {
2824                 refclk = 96000;
2825                 if (IS_IGDNG(dev))
2826                         refclk = 120000; /* 120Mhz refclk */
2827         } else {
2828                 refclk = 48000;
2829         }
2830
2831
2832         /*
2833          * Returns a set of divisors for the desired target clock with the given
2834          * refclk, or FALSE.  The returned values represent the clock equation:
2835          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2836          */
2837         limit = intel_limit(crtc);
2838         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2839         if (!ok) {
2840                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2841                 drm_vblank_post_modeset(dev, pipe);
2842                 return -EINVAL;
2843         }
2844
2845         if (limit->find_reduced_pll && dev_priv->lvds_downclock_avail) {
2846                 memcpy(&reduced_clock, &clock, sizeof(intel_clock_t));
2847                 has_reduced_clock = limit->find_reduced_pll(limit, crtc,
2848                                                             (adjusted_mode->clock*3/4),
2849                                                             refclk,
2850                                                             &reduced_clock);
2851         }
2852
2853         /* SDVO TV has fixed PLL values depend on its clock range,
2854            this mirrors vbios setting. */
2855         if (is_sdvo && is_tv) {
2856                 if (adjusted_mode->clock >= 100000
2857                                 && adjusted_mode->clock < 140500) {
2858                         clock.p1 = 2;
2859                         clock.p2 = 10;
2860                         clock.n = 3;
2861                         clock.m1 = 16;
2862                         clock.m2 = 8;
2863                 } else if (adjusted_mode->clock >= 140500
2864                                 && adjusted_mode->clock <= 200000) {
2865                         clock.p1 = 1;
2866                         clock.p2 = 10;
2867                         clock.n = 6;
2868                         clock.m1 = 12;
2869                         clock.m2 = 8;
2870                 }
2871         }
2872
2873         /* FDI link */
2874         if (IS_IGDNG(dev)) {
2875                 int lane, link_bw, bpp;
2876                 /* eDP doesn't require FDI link, so just set DP M/N
2877                    according to current link config */
2878                 if (is_edp) {
2879                         struct drm_connector *edp;
2880                         target_clock = mode->clock;
2881                         edp = intel_pipe_get_output(crtc);
2882                         intel_edp_link_config(to_intel_output(edp),
2883                                         &lane, &link_bw);
2884                 } else {
2885                         /* DP over FDI requires target mode clock
2886                            instead of link clock */
2887                         if (is_dp)
2888                                 target_clock = mode->clock;
2889                         else
2890                                 target_clock = adjusted_mode->clock;
2891                         lane = 4;
2892                         link_bw = 270000;
2893                 }
2894
2895                 /* determine panel color depth */
2896                 temp = I915_READ(pipeconf_reg);
2897
2898                 switch (temp & PIPE_BPC_MASK) {
2899                 case PIPE_8BPC:
2900                         bpp = 24;
2901                         break;
2902                 case PIPE_10BPC:
2903                         bpp = 30;
2904                         break;
2905                 case PIPE_6BPC:
2906                         bpp = 18;
2907                         break;
2908                 case PIPE_12BPC:
2909                         bpp = 36;
2910                         break;
2911                 default:
2912                         DRM_ERROR("unknown pipe bpc value\n");
2913                         bpp = 24;
2914                 }
2915
2916                 igdng_compute_m_n(bpp, lane, target_clock,
2917                                   link_bw, &m_n);
2918         }
2919
2920         /* Ironlake: try to setup display ref clock before DPLL
2921          * enabling. This is only under driver's control after
2922          * PCH B stepping, previous chipset stepping should be
2923          * ignoring this setting.
2924          */
2925         if (IS_IGDNG(dev)) {
2926                 temp = I915_READ(PCH_DREF_CONTROL);
2927                 /* Always enable nonspread source */
2928                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2929                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2930                 I915_WRITE(PCH_DREF_CONTROL, temp);
2931                 POSTING_READ(PCH_DREF_CONTROL);
2932
2933                 temp &= ~DREF_SSC_SOURCE_MASK;
2934                 temp |= DREF_SSC_SOURCE_ENABLE;
2935                 I915_WRITE(PCH_DREF_CONTROL, temp);
2936                 POSTING_READ(PCH_DREF_CONTROL);
2937
2938                 udelay(200);
2939
2940                 if (is_edp) {
2941                         if (dev_priv->lvds_use_ssc) {
2942                                 temp |= DREF_SSC1_ENABLE;
2943                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2944                                 POSTING_READ(PCH_DREF_CONTROL);
2945
2946                                 udelay(200);
2947
2948                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2949                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2950                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2951                                 POSTING_READ(PCH_DREF_CONTROL);
2952                         } else {
2953                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2954                                 I915_WRITE(PCH_DREF_CONTROL, temp);
2955                                 POSTING_READ(PCH_DREF_CONTROL);
2956                         }
2957                 }
2958         }
2959
2960         if (IS_IGD(dev)) {
2961                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2962                 if (has_reduced_clock)
2963                         fp2 = (1 << reduced_clock.n) << 16 |
2964                                 reduced_clock.m1 << 8 | reduced_clock.m2;
2965         } else {
2966                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2967                 if (has_reduced_clock)
2968                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
2969                                 reduced_clock.m2;
2970         }
2971
2972         if (!IS_IGDNG(dev))
2973                 dpll = DPLL_VGA_MODE_DIS;
2974
2975         if (IS_I9XX(dev)) {
2976                 if (is_lvds)
2977                         dpll |= DPLLB_MODE_LVDS;
2978                 else
2979                         dpll |= DPLLB_MODE_DAC_SERIAL;
2980                 if (is_sdvo) {
2981                         dpll |= DPLL_DVO_HIGH_SPEED;
2982                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2983                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
2984                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2985                         else if (IS_IGDNG(dev))
2986                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2987                 }
2988                 if (is_dp)
2989                         dpll |= DPLL_DVO_HIGH_SPEED;
2990
2991                 /* compute bitmask from p1 value */
2992                 if (IS_IGD(dev))
2993                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2994                 else {
2995                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2996                         /* also FPA1 */
2997                         if (IS_IGDNG(dev))
2998                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2999                         if (IS_G4X(dev) && has_reduced_clock)
3000                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3001                 }
3002                 switch (clock.p2) {
3003                 case 5:
3004                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3005                         break;
3006                 case 7:
3007                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3008                         break;
3009                 case 10:
3010                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3011                         break;
3012                 case 14:
3013                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3014                         break;
3015                 }
3016                 if (IS_I965G(dev) && !IS_IGDNG(dev))
3017                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3018         } else {
3019                 if (is_lvds) {
3020                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3021                 } else {
3022                         if (clock.p1 == 2)
3023                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3024                         else
3025                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3026                         if (clock.p2 == 4)
3027                                 dpll |= PLL_P2_DIVIDE_BY_4;
3028                 }
3029         }
3030
3031         if (is_sdvo && is_tv)
3032                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3033         else if (is_tv)
3034                 /* XXX: just matching BIOS for now */
3035                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3036                 dpll |= 3;
3037         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3038                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3039         else
3040                 dpll |= PLL_REF_INPUT_DREFCLK;
3041
3042         /* setup pipeconf */
3043         pipeconf = I915_READ(pipeconf_reg);
3044
3045         /* Set up the display plane register */
3046         dspcntr = DISPPLANE_GAMMA_ENABLE;
3047
3048         /* IGDNG's plane is forced to pipe, bit 24 is to
3049            enable color space conversion */
3050         if (!IS_IGDNG(dev)) {
3051                 if (pipe == 0)
3052                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3053                 else
3054                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3055         }
3056
3057         if (pipe == 0 && !IS_I965G(dev)) {
3058                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3059                  * core speed.
3060                  *
3061                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3062                  * pipe == 0 check?
3063                  */
3064                 if (mode->clock >
3065                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3066                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3067                 else
3068                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3069         }
3070
3071         dspcntr |= DISPLAY_PLANE_ENABLE;
3072         pipeconf |= PIPEACONF_ENABLE;
3073         dpll |= DPLL_VCO_ENABLE;
3074
3075
3076         /* Disable the panel fitter if it was on our pipe */
3077         if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
3078                 I915_WRITE(PFIT_CONTROL, 0);
3079
3080         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3081         drm_mode_debug_printmodeline(mode);
3082
3083         /* assign to IGDNG registers */
3084         if (IS_IGDNG(dev)) {
3085                 fp_reg = pch_fp_reg;
3086                 dpll_reg = pch_dpll_reg;
3087         }
3088
3089         if (is_edp) {
3090                 igdng_disable_pll_edp(crtc);
3091         } else if ((dpll & DPLL_VCO_ENABLE)) {
3092                 I915_WRITE(fp_reg, fp);
3093                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3094                 I915_READ(dpll_reg);
3095                 udelay(150);
3096         }
3097
3098         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3099          * This is an exception to the general rule that mode_set doesn't turn
3100          * things on.
3101          */
3102         if (is_lvds) {
3103                 u32 lvds;
3104
3105                 if (IS_IGDNG(dev))
3106                         lvds_reg = PCH_LVDS;
3107
3108                 lvds = I915_READ(lvds_reg);
3109                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3110                 /* set the corresponsding LVDS_BORDER bit */
3111                 lvds |= dev_priv->lvds_border_bits;
3112                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3113                  * set the DPLLs for dual-channel mode or not.
3114                  */
3115                 if (clock.p2 == 7)
3116                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3117                 else
3118                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3119
3120                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3121                  * appropriately here, but we need to look more thoroughly into how
3122                  * panels behave in the two modes.
3123                  */
3124
3125                 I915_WRITE(lvds_reg, lvds);
3126                 I915_READ(lvds_reg);
3127         }
3128         if (is_dp)
3129                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3130
3131         if (!is_edp) {
3132                 I915_WRITE(fp_reg, fp);
3133                 I915_WRITE(dpll_reg, dpll);
3134                 I915_READ(dpll_reg);
3135                 /* Wait for the clocks to stabilize. */
3136                 udelay(150);
3137
3138                 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
3139                         if (is_sdvo) {
3140                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3141                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3142                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3143                         } else
3144                                 I915_WRITE(dpll_md_reg, 0);
3145                 } else {
3146                         /* write it again -- the BIOS does, after all */
3147                         I915_WRITE(dpll_reg, dpll);
3148                 }
3149                 I915_READ(dpll_reg);
3150                 /* Wait for the clocks to stabilize. */
3151                 udelay(150);
3152         }
3153
3154         if (is_lvds && has_reduced_clock && i915_powersave) {
3155                 I915_WRITE(fp_reg + 4, fp2);
3156                 intel_crtc->lowfreq_avail = true;
3157                 if (HAS_PIPE_CXSR(dev)) {
3158                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3159                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3160                 }
3161         } else {
3162                 I915_WRITE(fp_reg + 4, fp);
3163                 intel_crtc->lowfreq_avail = false;
3164                 if (HAS_PIPE_CXSR(dev)) {
3165                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3166                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3167                 }
3168         }
3169
3170         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3171                    ((adjusted_mode->crtc_htotal - 1) << 16));
3172         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3173                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3174         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3175                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3176         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3177                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3178         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3179                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3180         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3181                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3182         /* pipesrc and dspsize control the size that is scaled from, which should
3183          * always be the user's requested size.
3184          */
3185         if (!IS_IGDNG(dev)) {
3186                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3187                                 (mode->hdisplay - 1));
3188                 I915_WRITE(dsppos_reg, 0);
3189         }
3190         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3191
3192         if (IS_IGDNG(dev)) {
3193                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3194                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3195                 I915_WRITE(link_m1_reg, m_n.link_m);
3196                 I915_WRITE(link_n1_reg, m_n.link_n);
3197
3198                 if (is_edp) {
3199                         igdng_set_pll_edp(crtc, adjusted_mode->clock);
3200                 } else {
3201                         /* enable FDI RX PLL too */
3202                         temp = I915_READ(fdi_rx_reg);
3203                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3204                         udelay(200);
3205                 }
3206         }
3207
3208         I915_WRITE(pipeconf_reg, pipeconf);
3209         I915_READ(pipeconf_reg);
3210
3211         intel_wait_for_vblank(dev);
3212
3213         if (IS_IGDNG(dev)) {
3214                 /* enable address swizzle for tiling buffer */
3215                 temp = I915_READ(DISP_ARB_CTL);
3216                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3217         }
3218
3219         I915_WRITE(dspcntr_reg, dspcntr);
3220
3221         /* Flush the plane changes */
3222         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3223
3224         if ((IS_I965G(dev) || plane == 0))
3225                 intel_update_fbc(crtc, &crtc->mode);
3226
3227         intel_update_watermarks(dev);
3228
3229         drm_vblank_post_modeset(dev, pipe);
3230
3231         return ret;
3232 }
3233
3234 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3235 void intel_crtc_load_lut(struct drm_crtc *crtc)
3236 {
3237         struct drm_device *dev = crtc->dev;
3238         struct drm_i915_private *dev_priv = dev->dev_private;
3239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3241         int i;
3242
3243         /* The clocks have to be on to load the palette. */
3244         if (!crtc->enabled)
3245                 return;
3246
3247         /* use legacy palette for IGDNG */
3248         if (IS_IGDNG(dev))
3249                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3250                                                    LGC_PALETTE_B;
3251
3252         for (i = 0; i < 256; i++) {
3253                 I915_WRITE(palreg + 4 * i,
3254                            (intel_crtc->lut_r[i] << 16) |
3255                            (intel_crtc->lut_g[i] << 8) |
3256                            intel_crtc->lut_b[i]);
3257         }
3258 }
3259
3260 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3261                                  struct drm_file *file_priv,
3262                                  uint32_t handle,
3263                                  uint32_t width, uint32_t height)
3264 {
3265         struct drm_device *dev = crtc->dev;
3266         struct drm_i915_private *dev_priv = dev->dev_private;
3267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3268         struct drm_gem_object *bo;
3269         struct drm_i915_gem_object *obj_priv;
3270         int pipe = intel_crtc->pipe;
3271         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3272         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3273         uint32_t temp = I915_READ(control);
3274         size_t addr;
3275         int ret;
3276
3277         DRM_DEBUG_KMS("\n");
3278
3279         /* if we want to turn off the cursor ignore width and height */
3280         if (!handle) {
3281                 DRM_DEBUG_KMS("cursor off\n");
3282                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3283                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3284                         temp |= CURSOR_MODE_DISABLE;
3285                 } else {
3286                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3287                 }
3288                 addr = 0;
3289                 bo = NULL;
3290                 mutex_lock(&dev->struct_mutex);
3291                 goto finish;
3292         }
3293
3294         /* Currently we only support 64x64 cursors */
3295         if (width != 64 || height != 64) {
3296                 DRM_ERROR("we currently only support 64x64 cursors\n");
3297                 return -EINVAL;
3298         }
3299
3300         bo = drm_gem_object_lookup(dev, file_priv, handle);
3301         if (!bo)
3302                 return -ENOENT;
3303
3304         obj_priv = bo->driver_private;
3305
3306         if (bo->size < width * height * 4) {
3307                 DRM_ERROR("buffer is to small\n");
3308                 ret = -ENOMEM;
3309                 goto fail;
3310         }
3311
3312         /* we only need to pin inside GTT if cursor is non-phy */
3313         mutex_lock(&dev->struct_mutex);
3314         if (!dev_priv->cursor_needs_physical) {
3315                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3316                 if (ret) {
3317                         DRM_ERROR("failed to pin cursor bo\n");
3318                         goto fail_locked;
3319                 }
3320                 addr = obj_priv->gtt_offset;
3321         } else {
3322                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3323                 if (ret) {
3324                         DRM_ERROR("failed to attach phys object\n");
3325                         goto fail_locked;
3326                 }
3327                 addr = obj_priv->phys_obj->handle->busaddr;
3328         }
3329
3330         if (!IS_I9XX(dev))
3331                 I915_WRITE(CURSIZE, (height << 12) | width);
3332
3333         /* Hooray for CUR*CNTR differences */
3334         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3335                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3336                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3337                 temp |= (pipe << 28); /* Connect to correct pipe */
3338         } else {
3339                 temp &= ~(CURSOR_FORMAT_MASK);
3340                 temp |= CURSOR_ENABLE;
3341                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3342         }
3343
3344  finish:
3345         I915_WRITE(control, temp);
3346         I915_WRITE(base, addr);
3347
3348         if (intel_crtc->cursor_bo) {
3349                 if (dev_priv->cursor_needs_physical) {
3350                         if (intel_crtc->cursor_bo != bo)
3351                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3352                 } else
3353                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3354                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3355         }
3356
3357         mutex_unlock(&dev->struct_mutex);
3358
3359         intel_crtc->cursor_addr = addr;
3360         intel_crtc->cursor_bo = bo;
3361
3362         return 0;
3363 fail:
3364         mutex_lock(&dev->struct_mutex);
3365 fail_locked:
3366         drm_gem_object_unreference(bo);
3367         mutex_unlock(&dev->struct_mutex);
3368         return ret;
3369 }
3370
3371 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3372 {
3373         struct drm_device *dev = crtc->dev;
3374         struct drm_i915_private *dev_priv = dev->dev_private;
3375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3376         struct intel_framebuffer *intel_fb;
3377         int pipe = intel_crtc->pipe;
3378         uint32_t temp = 0;
3379         uint32_t adder;
3380
3381         if (crtc->fb) {
3382                 intel_fb = to_intel_framebuffer(crtc->fb);
3383                 intel_mark_busy(dev, intel_fb->obj);
3384         }
3385
3386         if (x < 0) {
3387                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3388                 x = -x;
3389         }
3390         if (y < 0) {
3391                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3392                 y = -y;
3393         }
3394
3395         temp |= x << CURSOR_X_SHIFT;
3396         temp |= y << CURSOR_Y_SHIFT;
3397
3398         adder = intel_crtc->cursor_addr;
3399         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3400         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3401
3402         return 0;
3403 }
3404
3405 /** Sets the color ramps on behalf of RandR */
3406 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3407                                  u16 blue, int regno)
3408 {
3409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3410
3411         intel_crtc->lut_r[regno] = red >> 8;
3412         intel_crtc->lut_g[regno] = green >> 8;
3413         intel_crtc->lut_b[regno] = blue >> 8;
3414 }
3415
3416 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3417                              u16 *blue, int regno)
3418 {
3419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3420
3421         *red = intel_crtc->lut_r[regno] << 8;
3422         *green = intel_crtc->lut_g[regno] << 8;
3423         *blue = intel_crtc->lut_b[regno] << 8;
3424 }
3425
3426 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3427                                  u16 *blue, uint32_t size)
3428 {
3429         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3430         int i;
3431
3432         if (size != 256)
3433                 return;
3434
3435         for (i = 0; i < 256; i++) {
3436                 intel_crtc->lut_r[i] = red[i] >> 8;
3437                 intel_crtc->lut_g[i] = green[i] >> 8;
3438                 intel_crtc->lut_b[i] = blue[i] >> 8;
3439         }
3440
3441         intel_crtc_load_lut(crtc);
3442 }
3443
3444 /**
3445  * Get a pipe with a simple mode set on it for doing load-based monitor
3446  * detection.
3447  *
3448  * It will be up to the load-detect code to adjust the pipe as appropriate for
3449  * its requirements.  The pipe will be connected to no other outputs.
3450  *
3451  * Currently this code will only succeed if there is a pipe with no outputs
3452  * configured for it.  In the future, it could choose to temporarily disable
3453  * some outputs to free up a pipe for its use.
3454  *
3455  * \return crtc, or NULL if no pipes are available.
3456  */
3457
3458 /* VESA 640x480x72Hz mode to set on the pipe */
3459 static struct drm_display_mode load_detect_mode = {
3460         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3461                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3462 };
3463
3464 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3465                                             struct drm_display_mode *mode,
3466                                             int *dpms_mode)
3467 {
3468         struct intel_crtc *intel_crtc;
3469         struct drm_crtc *possible_crtc;
3470         struct drm_crtc *supported_crtc =NULL;
3471         struct drm_encoder *encoder = &intel_output->enc;
3472         struct drm_crtc *crtc = NULL;
3473         struct drm_device *dev = encoder->dev;
3474         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3475         struct drm_crtc_helper_funcs *crtc_funcs;
3476         int i = -1;
3477
3478         /*
3479          * Algorithm gets a little messy:
3480          *   - if the connector already has an assigned crtc, use it (but make
3481          *     sure it's on first)
3482          *   - try to find the first unused crtc that can drive this connector,
3483          *     and use that if we find one
3484          *   - if there are no unused crtcs available, try to use the first
3485          *     one we found that supports the connector
3486          */
3487
3488         /* See if we already have a CRTC for this connector */
3489         if (encoder->crtc) {
3490                 crtc = encoder->crtc;
3491                 /* Make sure the crtc and connector are running */
3492                 intel_crtc = to_intel_crtc(crtc);
3493                 *dpms_mode = intel_crtc->dpms_mode;
3494                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3495                         crtc_funcs = crtc->helper_private;
3496                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3497                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3498                 }
3499                 return crtc;
3500         }
3501
3502         /* Find an unused one (if possible) */
3503         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3504                 i++;
3505                 if (!(encoder->possible_crtcs & (1 << i)))
3506                         continue;
3507                 if (!possible_crtc->enabled) {
3508                         crtc = possible_crtc;
3509                         break;
3510                 }
3511                 if (!supported_crtc)
3512                         supported_crtc = possible_crtc;
3513         }
3514
3515         /*
3516          * If we didn't find an unused CRTC, don't use any.
3517          */
3518         if (!crtc) {
3519                 return NULL;
3520         }
3521
3522         encoder->crtc = crtc;
3523         intel_output->base.encoder = encoder;
3524         intel_output->load_detect_temp = true;
3525
3526         intel_crtc = to_intel_crtc(crtc);
3527         *dpms_mode = intel_crtc->dpms_mode;
3528
3529         if (!crtc->enabled) {
3530                 if (!mode)
3531                         mode = &load_detect_mode;
3532                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3533         } else {
3534                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3535                         crtc_funcs = crtc->helper_private;
3536                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3537                 }
3538
3539                 /* Add this connector to the crtc */
3540                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3541                 encoder_funcs->commit(encoder);
3542         }
3543         /* let the connector get through one full cycle before testing */
3544         intel_wait_for_vblank(dev);
3545
3546         return crtc;
3547 }
3548
3549 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3550 {
3551         struct drm_encoder *encoder = &intel_output->enc;
3552         struct drm_device *dev = encoder->dev;
3553         struct drm_crtc *crtc = encoder->crtc;
3554         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3555         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3556
3557         if (intel_output->load_detect_temp) {
3558                 encoder->crtc = NULL;
3559                 intel_output->base.encoder = NULL;
3560                 intel_output->load_detect_temp = false;
3561                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3562                 drm_helper_disable_unused_functions(dev);
3563         }
3564
3565         /* Switch crtc and output back off if necessary */
3566         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3567                 if (encoder->crtc == crtc)
3568                         encoder_funcs->dpms(encoder, dpms_mode);
3569                 crtc_funcs->dpms(crtc, dpms_mode);
3570         }
3571 }
3572
3573 /* Returns the clock of the currently programmed mode of the given pipe. */
3574 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3575 {
3576         struct drm_i915_private *dev_priv = dev->dev_private;
3577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3578         int pipe = intel_crtc->pipe;
3579         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3580         u32 fp;
3581         intel_clock_t clock;
3582
3583         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3584                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3585         else
3586                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3587
3588         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3589         if (IS_IGD(dev)) {
3590                 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3591                 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
3592         } else {
3593                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3594                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3595         }
3596
3597         if (IS_I9XX(dev)) {
3598                 if (IS_IGD(dev))
3599                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
3600                                 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
3601                 else
3602                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3603                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3604
3605                 switch (dpll & DPLL_MODE_MASK) {
3606                 case DPLLB_MODE_DAC_SERIAL:
3607                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3608                                 5 : 10;
3609                         break;
3610                 case DPLLB_MODE_LVDS:
3611                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3612                                 7 : 14;
3613                         break;
3614                 default:
3615                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3616                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3617                         return 0;
3618                 }
3619
3620                 /* XXX: Handle the 100Mhz refclk */
3621                 intel_clock(dev, 96000, &clock);
3622         } else {
3623                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3624
3625                 if (is_lvds) {
3626                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3627                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3628                         clock.p2 = 14;
3629
3630                         if ((dpll & PLL_REF_INPUT_MASK) ==
3631                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3632                                 /* XXX: might not be 66MHz */
3633                                 intel_clock(dev, 66000, &clock);
3634                         } else
3635                                 intel_clock(dev, 48000, &clock);
3636                 } else {
3637                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3638                                 clock.p1 = 2;
3639                         else {
3640                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3641                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3642                         }
3643                         if (dpll & PLL_P2_DIVIDE_BY_4)
3644                                 clock.p2 = 4;
3645                         else
3646                                 clock.p2 = 2;
3647
3648                         intel_clock(dev, 48000, &clock);
3649                 }
3650         }
3651
3652         /* XXX: It would be nice to validate the clocks, but we can't reuse
3653          * i830PllIsValid() because it relies on the xf86_config connector
3654          * configuration being accurate, which it isn't necessarily.
3655          */
3656
3657         return clock.dot;
3658 }
3659
3660 /** Returns the currently programmed mode of the given pipe. */
3661 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3662                                              struct drm_crtc *crtc)
3663 {
3664         struct drm_i915_private *dev_priv = dev->dev_private;
3665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3666         int pipe = intel_crtc->pipe;
3667         struct drm_display_mode *mode;
3668         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3669         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3670         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3671         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3672
3673         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3674         if (!mode)
3675                 return NULL;
3676
3677         mode->clock = intel_crtc_clock_get(dev, crtc);
3678         mode->hdisplay = (htot & 0xffff) + 1;
3679         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3680         mode->hsync_start = (hsync & 0xffff) + 1;
3681         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3682         mode->vdisplay = (vtot & 0xffff) + 1;
3683         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3684         mode->vsync_start = (vsync & 0xffff) + 1;
3685         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3686
3687         drm_mode_set_name(mode);
3688         drm_mode_set_crtcinfo(mode, 0);
3689
3690         return mode;
3691 }
3692
3693 #define GPU_IDLE_TIMEOUT 500 /* ms */
3694
3695 /* When this timer fires, we've been idle for awhile */
3696 static void intel_gpu_idle_timer(unsigned long arg)
3697 {
3698         struct drm_device *dev = (struct drm_device *)arg;
3699         drm_i915_private_t *dev_priv = dev->dev_private;
3700
3701         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3702
3703         dev_priv->busy = false;
3704
3705         queue_work(dev_priv->wq, &dev_priv->idle_work);
3706 }
3707
3708 void intel_increase_renderclock(struct drm_device *dev, bool schedule)
3709 {
3710         drm_i915_private_t *dev_priv = dev->dev_private;
3711
3712         if (IS_IGDNG(dev))
3713                 return;
3714
3715         if (!dev_priv->render_reclock_avail) {
3716                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3717                 return;
3718         }
3719
3720         /* Restore render clock frequency to original value */
3721         if (IS_G4X(dev) || IS_I9XX(dev))
3722                 pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
3723         else if (IS_I85X(dev))
3724                 pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
3725         DRM_DEBUG_DRIVER("increasing render clock frequency\n");
3726
3727         /* Schedule downclock */
3728         if (schedule)
3729                 mod_timer(&dev_priv->idle_timer, jiffies +
3730                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3731 }
3732
3733 void intel_decrease_renderclock(struct drm_device *dev)
3734 {
3735         drm_i915_private_t *dev_priv = dev->dev_private;
3736
3737         if (IS_IGDNG(dev))
3738                 return;
3739
3740         if (!dev_priv->render_reclock_avail) {
3741                 DRM_DEBUG_DRIVER("not reclocking render clock\n");
3742                 return;
3743         }
3744
3745         if (IS_G4X(dev)) {
3746                 u16 gcfgc;
3747
3748                 /* Adjust render clock... */
3749                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3750
3751                 /* Down to minimum... */
3752                 gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
3753                 gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
3754
3755                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3756         } else if (IS_I965G(dev)) {
3757                 u16 gcfgc;
3758
3759                 /* Adjust render clock... */
3760                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3761
3762                 /* Down to minimum... */
3763                 gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
3764                 gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
3765
3766                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3767         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
3768                 u16 gcfgc;
3769
3770                 /* Adjust render clock... */
3771                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3772
3773                 /* Down to minimum... */
3774                 gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
3775                 gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
3776
3777                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3778         } else if (IS_I915G(dev)) {
3779                 u16 gcfgc;
3780
3781                 /* Adjust render clock... */
3782                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3783
3784                 /* Down to minimum... */
3785                 gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
3786                 gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
3787
3788                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3789         } else if (IS_I85X(dev)) {
3790                 u16 hpllcc;
3791
3792                 /* Adjust render clock... */
3793                 pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
3794
3795                 /* Up to maximum... */
3796                 hpllcc &= ~GC_CLOCK_CONTROL_MASK;
3797                 hpllcc |= GC_CLOCK_133_200;
3798
3799                 pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
3800         }
3801         DRM_DEBUG_DRIVER("decreasing render clock frequency\n");
3802 }
3803
3804 /* Note that no increase function is needed for this - increase_renderclock()
3805  *  will also rewrite these bits
3806  */
3807 void intel_decrease_displayclock(struct drm_device *dev)
3808 {
3809         if (IS_IGDNG(dev))
3810                 return;
3811
3812         if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
3813             IS_I915GM(dev)) {
3814                 u16 gcfgc;
3815
3816                 /* Adjust render clock... */
3817                 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3818
3819                 /* Down to minimum... */
3820                 gcfgc &= ~0xf0;
3821                 gcfgc |= 0x80;
3822
3823                 pci_write_config_word(dev->pdev, GCFGC, gcfgc);
3824         }
3825 }
3826
3827 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3828
3829 static void intel_crtc_idle_timer(unsigned long arg)
3830 {
3831         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3832         struct drm_crtc *crtc = &intel_crtc->base;
3833         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3834
3835         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3836
3837         intel_crtc->busy = false;
3838
3839         queue_work(dev_priv->wq, &dev_priv->idle_work);
3840 }
3841
3842 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3843 {
3844         struct drm_device *dev = crtc->dev;
3845         drm_i915_private_t *dev_priv = dev->dev_private;
3846         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3847         int pipe = intel_crtc->pipe;
3848         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3849         int dpll = I915_READ(dpll_reg);
3850
3851         if (IS_IGDNG(dev))
3852                 return;
3853
3854         if (!dev_priv->lvds_downclock_avail)
3855                 return;
3856
3857         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3858                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3859
3860                 /* Unlock panel regs */
3861                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3862
3863                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3864                 I915_WRITE(dpll_reg, dpll);
3865                 dpll = I915_READ(dpll_reg);
3866                 intel_wait_for_vblank(dev);
3867                 dpll = I915_READ(dpll_reg);
3868                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3869                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3870
3871                 /* ...and lock them again */
3872                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3873         }
3874
3875         /* Schedule downclock */
3876         if (schedule)
3877                 mod_timer(&intel_crtc->idle_timer, jiffies +
3878                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3879 }
3880
3881 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3882 {
3883         struct drm_device *dev = crtc->dev;
3884         drm_i915_private_t *dev_priv = dev->dev_private;
3885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3886         int pipe = intel_crtc->pipe;
3887         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3888         int dpll = I915_READ(dpll_reg);
3889
3890         if (IS_IGDNG(dev))
3891                 return;
3892
3893         if (!dev_priv->lvds_downclock_avail)
3894                 return;
3895
3896         /*
3897          * Since this is called by a timer, we should never get here in
3898          * the manual case.
3899          */
3900         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3901                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3902
3903                 /* Unlock panel regs */
3904                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3905
3906                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3907                 I915_WRITE(dpll_reg, dpll);
3908                 dpll = I915_READ(dpll_reg);
3909                 intel_wait_for_vblank(dev);
3910                 dpll = I915_READ(dpll_reg);
3911                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3912                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3913
3914                 /* ...and lock them again */
3915                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3916         }
3917
3918 }
3919
3920 /**
3921  * intel_idle_update - adjust clocks for idleness
3922  * @work: work struct
3923  *
3924  * Either the GPU or display (or both) went idle.  Check the busy status
3925  * here and adjust the CRTC and GPU clocks as necessary.
3926  */
3927 static void intel_idle_update(struct work_struct *work)
3928 {
3929         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3930                                                     idle_work);
3931         struct drm_device *dev = dev_priv->dev;
3932         struct drm_crtc *crtc;
3933         struct intel_crtc *intel_crtc;
3934
3935         if (!i915_powersave)
3936                 return;
3937
3938         mutex_lock(&dev->struct_mutex);
3939
3940         /* GPU isn't processing, downclock it. */
3941         if (!dev_priv->busy) {
3942                 intel_decrease_renderclock(dev);
3943                 intel_decrease_displayclock(dev);
3944         }
3945
3946         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3947                 /* Skip inactive CRTCs */
3948                 if (!crtc->fb)
3949                         continue;
3950
3951                 intel_crtc = to_intel_crtc(crtc);
3952                 if (!intel_crtc->busy)
3953                         intel_decrease_pllclock(crtc);
3954         }
3955
3956         mutex_unlock(&dev->struct_mutex);
3957 }
3958
3959 /**
3960  * intel_mark_busy - mark the GPU and possibly the display busy
3961  * @dev: drm device
3962  * @obj: object we're operating on
3963  *
3964  * Callers can use this function to indicate that the GPU is busy processing
3965  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
3966  * buffer), we'll also mark the display as busy, so we know to increase its
3967  * clock frequency.
3968  */
3969 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3970 {
3971         drm_i915_private_t *dev_priv = dev->dev_private;
3972         struct drm_crtc *crtc = NULL;
3973         struct intel_framebuffer *intel_fb;
3974         struct intel_crtc *intel_crtc;
3975
3976         if (!drm_core_check_feature(dev, DRIVER_MODESET))
3977                 return;
3978
3979         dev_priv->busy = true;
3980         intel_increase_renderclock(dev, true);
3981
3982         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3983                 if (!crtc->fb)
3984                         continue;
3985
3986                 intel_crtc = to_intel_crtc(crtc);
3987                 intel_fb = to_intel_framebuffer(crtc->fb);
3988                 if (intel_fb->obj == obj) {
3989                         if (!intel_crtc->busy) {
3990                                 /* Non-busy -> busy, upclock */
3991                                 intel_increase_pllclock(crtc, true);
3992                                 intel_crtc->busy = true;
3993                         } else {
3994                                 /* Busy -> busy, put off timer */
3995                                 mod_timer(&intel_crtc->idle_timer, jiffies +
3996                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3997                         }
3998                 }
3999         }
4000 }
4001
4002 static void intel_crtc_destroy(struct drm_crtc *crtc)
4003 {
4004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4005
4006         drm_crtc_cleanup(crtc);
4007         kfree(intel_crtc);
4008 }
4009
4010 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4011         .dpms = intel_crtc_dpms,
4012         .mode_fixup = intel_crtc_mode_fixup,
4013         .mode_set = intel_crtc_mode_set,
4014         .mode_set_base = intel_pipe_set_base,
4015         .prepare = intel_crtc_prepare,
4016         .commit = intel_crtc_commit,
4017         .load_lut = intel_crtc_load_lut,
4018 };
4019
4020 static const struct drm_crtc_funcs intel_crtc_funcs = {
4021         .cursor_set = intel_crtc_cursor_set,
4022         .cursor_move = intel_crtc_cursor_move,
4023         .gamma_set = intel_crtc_gamma_set,
4024         .set_config = drm_crtc_helper_set_config,
4025         .destroy = intel_crtc_destroy,
4026 };
4027
4028
4029 static void intel_crtc_init(struct drm_device *dev, int pipe)
4030 {
4031         struct intel_crtc *intel_crtc;
4032         int i;
4033
4034         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4035         if (intel_crtc == NULL)
4036                 return;
4037
4038         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4039
4040         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4041         intel_crtc->pipe = pipe;
4042         intel_crtc->plane = pipe;
4043         for (i = 0; i < 256; i++) {
4044                 intel_crtc->lut_r[i] = i;
4045                 intel_crtc->lut_g[i] = i;
4046                 intel_crtc->lut_b[i] = i;
4047         }
4048
4049         /* Swap pipes & planes for FBC on pre-965 */
4050         intel_crtc->pipe = pipe;
4051         intel_crtc->plane = pipe;
4052         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4053                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4054                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4055         }
4056
4057         intel_crtc->cursor_addr = 0;
4058         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4059         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4060
4061         intel_crtc->busy = false;
4062
4063         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4064                     (unsigned long)intel_crtc);
4065 }
4066
4067 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4068                                 struct drm_file *file_priv)
4069 {
4070         drm_i915_private_t *dev_priv = dev->dev_private;
4071         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4072         struct drm_mode_object *drmmode_obj;
4073         struct intel_crtc *crtc;
4074
4075         if (!dev_priv) {
4076                 DRM_ERROR("called with no initialization\n");
4077                 return -EINVAL;
4078         }
4079
4080         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4081                         DRM_MODE_OBJECT_CRTC);
4082
4083         if (!drmmode_obj) {
4084                 DRM_ERROR("no such CRTC id\n");
4085                 return -EINVAL;
4086         }
4087
4088         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4089         pipe_from_crtc_id->pipe = crtc->pipe;
4090
4091         return 0;
4092 }
4093
4094 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4095 {
4096         struct drm_crtc *crtc = NULL;
4097
4098         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4099                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4100                 if (intel_crtc->pipe == pipe)
4101                         break;
4102         }
4103         return crtc;
4104 }
4105
4106 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4107 {
4108         int index_mask = 0;
4109         struct drm_connector *connector;
4110         int entry = 0;
4111
4112         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4113                 struct intel_output *intel_output = to_intel_output(connector);
4114                 if (type_mask & intel_output->clone_mask)
4115                         index_mask |= (1 << entry);
4116                 entry++;
4117         }
4118         return index_mask;
4119 }
4120
4121
4122 static void intel_setup_outputs(struct drm_device *dev)
4123 {
4124         struct drm_i915_private *dev_priv = dev->dev_private;
4125         struct drm_connector *connector;
4126
4127         intel_crt_init(dev);
4128
4129         /* Set up integrated LVDS */
4130         if (IS_MOBILE(dev) && !IS_I830(dev))
4131                 intel_lvds_init(dev);
4132
4133         if (IS_IGDNG(dev)) {
4134                 int found;
4135
4136                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4137                         intel_dp_init(dev, DP_A);
4138
4139                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4140                         /* check SDVOB */
4141                         /* found = intel_sdvo_init(dev, HDMIB); */
4142                         found = 0;
4143                         if (!found)
4144                                 intel_hdmi_init(dev, HDMIB);
4145                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4146                                 intel_dp_init(dev, PCH_DP_B);
4147                 }
4148
4149                 if (I915_READ(HDMIC) & PORT_DETECTED)
4150                         intel_hdmi_init(dev, HDMIC);
4151
4152                 if (I915_READ(HDMID) & PORT_DETECTED)
4153                         intel_hdmi_init(dev, HDMID);
4154
4155                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4156                         intel_dp_init(dev, PCH_DP_C);
4157
4158                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4159                         intel_dp_init(dev, PCH_DP_D);
4160
4161         } else if (IS_I9XX(dev)) {
4162                 bool found = false;
4163
4164                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4165                         found = intel_sdvo_init(dev, SDVOB);
4166                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
4167                                 intel_hdmi_init(dev, SDVOB);
4168
4169                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
4170                                 intel_dp_init(dev, DP_B);
4171                 }
4172
4173                 /* Before G4X SDVOC doesn't have its own detect register */
4174
4175                 if (I915_READ(SDVOB) & SDVO_DETECTED)
4176                         found = intel_sdvo_init(dev, SDVOC);
4177
4178                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4179
4180                         if (SUPPORTS_INTEGRATED_HDMI(dev))
4181                                 intel_hdmi_init(dev, SDVOC);
4182                         if (SUPPORTS_INTEGRATED_DP(dev))
4183                                 intel_dp_init(dev, DP_C);
4184                 }
4185
4186                 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
4187                         intel_dp_init(dev, DP_D);
4188         } else
4189                 intel_dvo_init(dev);
4190
4191         if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
4192                 intel_tv_init(dev);
4193
4194         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4195                 struct intel_output *intel_output = to_intel_output(connector);
4196                 struct drm_encoder *encoder = &intel_output->enc;
4197
4198                 encoder->possible_crtcs = intel_output->crtc_mask;
4199                 encoder->possible_clones = intel_connector_clones(dev,
4200                                                 intel_output->clone_mask);
4201         }
4202 }
4203
4204 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4205 {
4206         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4207         struct drm_device *dev = fb->dev;
4208
4209         if (fb->fbdev)
4210                 intelfb_remove(dev, fb);
4211
4212         drm_framebuffer_cleanup(fb);
4213         mutex_lock(&dev->struct_mutex);
4214         drm_gem_object_unreference(intel_fb->obj);
4215         mutex_unlock(&dev->struct_mutex);
4216
4217         kfree(intel_fb);
4218 }
4219
4220 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4221                                                 struct drm_file *file_priv,
4222                                                 unsigned int *handle)
4223 {
4224         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4225         struct drm_gem_object *object = intel_fb->obj;
4226
4227         return drm_gem_handle_create(file_priv, object, handle);
4228 }
4229
4230 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4231         .destroy = intel_user_framebuffer_destroy,
4232         .create_handle = intel_user_framebuffer_create_handle,
4233 };
4234
4235 int intel_framebuffer_create(struct drm_device *dev,
4236                              struct drm_mode_fb_cmd *mode_cmd,
4237                              struct drm_framebuffer **fb,
4238                              struct drm_gem_object *obj)
4239 {
4240         struct intel_framebuffer *intel_fb;
4241         int ret;
4242
4243         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4244         if (!intel_fb)
4245                 return -ENOMEM;
4246
4247         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4248         if (ret) {
4249                 DRM_ERROR("framebuffer init failed %d\n", ret);
4250                 return ret;
4251         }
4252
4253         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4254
4255         intel_fb->obj = obj;
4256
4257         *fb = &intel_fb->base;
4258
4259         return 0;
4260 }
4261
4262
4263 static struct drm_framebuffer *
4264 intel_user_framebuffer_create(struct drm_device *dev,
4265                               struct drm_file *filp,
4266                               struct drm_mode_fb_cmd *mode_cmd)
4267 {
4268         struct drm_gem_object *obj;
4269         struct drm_framebuffer *fb;
4270         int ret;
4271
4272         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4273         if (!obj)
4274                 return NULL;
4275
4276         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4277         if (ret) {
4278                 mutex_lock(&dev->struct_mutex);
4279                 drm_gem_object_unreference(obj);
4280                 mutex_unlock(&dev->struct_mutex);
4281                 return NULL;
4282         }
4283
4284         return fb;
4285 }
4286
4287 static const struct drm_mode_config_funcs intel_mode_funcs = {
4288         .fb_create = intel_user_framebuffer_create,
4289         .fb_changed = intelfb_probe,
4290 };
4291
4292 void intel_init_clock_gating(struct drm_device *dev)
4293 {
4294         struct drm_i915_private *dev_priv = dev->dev_private;
4295
4296         /*
4297          * Disable clock gating reported to work incorrectly according to the
4298          * specs, but enable as much else as we can.
4299          */
4300         if (IS_IGDNG(dev)) {
4301                 return;
4302         } else if (IS_G4X(dev)) {
4303                 uint32_t dspclk_gate;
4304                 I915_WRITE(RENCLK_GATE_D1, 0);
4305                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4306                        GS_UNIT_CLOCK_GATE_DISABLE |
4307                        CL_UNIT_CLOCK_GATE_DISABLE);
4308                 I915_WRITE(RAMCLK_GATE_D, 0);
4309                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4310                         OVRUNIT_CLOCK_GATE_DISABLE |
4311                         OVCUNIT_CLOCK_GATE_DISABLE;
4312                 if (IS_GM45(dev))
4313                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4314                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4315         } else if (IS_I965GM(dev)) {
4316                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4317                 I915_WRITE(RENCLK_GATE_D2, 0);
4318                 I915_WRITE(DSPCLK_GATE_D, 0);
4319                 I915_WRITE(RAMCLK_GATE_D, 0);
4320                 I915_WRITE16(DEUC, 0);
4321         } else if (IS_I965G(dev)) {
4322                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4323                        I965_RCC_CLOCK_GATE_DISABLE |
4324                        I965_RCPB_CLOCK_GATE_DISABLE |
4325                        I965_ISC_CLOCK_GATE_DISABLE |
4326                        I965_FBC_CLOCK_GATE_DISABLE);
4327                 I915_WRITE(RENCLK_GATE_D2, 0);
4328         } else if (IS_I9XX(dev)) {
4329                 u32 dstate = I915_READ(D_STATE);
4330
4331                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4332                         DSTATE_DOT_CLOCK_GATING;
4333                 I915_WRITE(D_STATE, dstate);
4334         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4335                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4336         } else if (IS_I830(dev)) {
4337                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4338         }
4339
4340         /*
4341          * GPU can automatically power down the render unit if given a page
4342          * to save state.
4343          */
4344         if (I915_HAS_RC6(dev)) {
4345                 struct drm_gem_object *pwrctx;
4346                 struct drm_i915_gem_object *obj_priv;
4347                 int ret;
4348
4349                 pwrctx = drm_gem_object_alloc(dev, 4096);
4350                 if (!pwrctx) {
4351                         DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4352                         goto out;
4353                 }
4354
4355                 ret = i915_gem_object_pin(pwrctx, 4096);
4356                 if (ret) {
4357                         DRM_ERROR("failed to pin power context: %d\n", ret);
4358                         drm_gem_object_unreference(pwrctx);
4359                         goto out;
4360                 }
4361
4362                 i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4363
4364                 obj_priv = pwrctx->driver_private;
4365
4366                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4367                 I915_WRITE(MCHBAR_RENDER_STANDBY,
4368                            I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4369
4370                 dev_priv->pwrctx = pwrctx;
4371         }
4372
4373 out:
4374         return;
4375 }
4376
4377 /* Set up chip specific display functions */
4378 static void intel_init_display(struct drm_device *dev)
4379 {
4380         struct drm_i915_private *dev_priv = dev->dev_private;
4381
4382         /* We always want a DPMS function */
4383         if (IS_IGDNG(dev))
4384                 dev_priv->display.dpms = igdng_crtc_dpms;
4385         else
4386                 dev_priv->display.dpms = i9xx_crtc_dpms;
4387
4388         /* Only mobile has FBC, leave pointers NULL for other chips */
4389         if (IS_MOBILE(dev)) {
4390                 if (IS_GM45(dev)) {
4391                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4392                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4393                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4394                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4395                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4396                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4397                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4398                 }
4399                 /* 855GM needs testing */
4400         }
4401
4402         /* Returns the core display clock speed */
4403         if (IS_I945G(dev))
4404                 dev_priv->display.get_display_clock_speed =
4405                         i945_get_display_clock_speed;
4406         else if (IS_I915G(dev))
4407                 dev_priv->display.get_display_clock_speed =
4408                         i915_get_display_clock_speed;
4409         else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
4410                 dev_priv->display.get_display_clock_speed =
4411                         i9xx_misc_get_display_clock_speed;
4412         else if (IS_I915GM(dev))
4413                 dev_priv->display.get_display_clock_speed =
4414                         i915gm_get_display_clock_speed;
4415         else if (IS_I865G(dev))
4416                 dev_priv->display.get_display_clock_speed =
4417                         i865_get_display_clock_speed;
4418         else if (IS_I85X(dev))
4419                 dev_priv->display.get_display_clock_speed =
4420                         i855_get_display_clock_speed;
4421         else /* 852, 830 */
4422                 dev_priv->display.get_display_clock_speed =
4423                         i830_get_display_clock_speed;
4424
4425         /* For FIFO watermark updates */
4426         if (IS_IGDNG(dev))
4427                 dev_priv->display.update_wm = NULL;
4428         else if (IS_G4X(dev))
4429                 dev_priv->display.update_wm = g4x_update_wm;
4430         else if (IS_I965G(dev))
4431                 dev_priv->display.update_wm = i965_update_wm;
4432         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4433                 dev_priv->display.update_wm = i9xx_update_wm;
4434                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4435         } else {
4436                 if (IS_I85X(dev))
4437                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4438                 else if (IS_845G(dev))
4439                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4440                 else
4441                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4442                 dev_priv->display.update_wm = i830_update_wm;
4443         }
4444 }
4445
4446 void intel_modeset_init(struct drm_device *dev)
4447 {
4448         struct drm_i915_private *dev_priv = dev->dev_private;
4449         int num_pipe;
4450         int i;
4451
4452         drm_mode_config_init(dev);
4453
4454         dev->mode_config.min_width = 0;
4455         dev->mode_config.min_height = 0;
4456
4457         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4458
4459         intel_init_display(dev);
4460
4461         if (IS_I965G(dev)) {
4462                 dev->mode_config.max_width = 8192;
4463                 dev->mode_config.max_height = 8192;
4464         } else if (IS_I9XX(dev)) {
4465                 dev->mode_config.max_width = 4096;
4466                 dev->mode_config.max_height = 4096;
4467         } else {
4468                 dev->mode_config.max_width = 2048;
4469                 dev->mode_config.max_height = 2048;
4470         }
4471
4472         /* set memory base */
4473         if (IS_I9XX(dev))
4474                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4475         else
4476                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4477
4478         if (IS_MOBILE(dev) || IS_I9XX(dev))
4479                 num_pipe = 2;
4480         else
4481                 num_pipe = 1;
4482         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4483                   num_pipe, num_pipe > 1 ? "s" : "");
4484
4485         if (IS_I85X(dev))
4486                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4487         else if (IS_I9XX(dev) || IS_G4X(dev))
4488                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4489
4490         for (i = 0; i < num_pipe; i++) {
4491                 intel_crtc_init(dev, i);
4492         }
4493
4494         intel_setup_outputs(dev);
4495
4496         intel_init_clock_gating(dev);
4497
4498         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4499         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4500                     (unsigned long)dev);
4501
4502         intel_setup_overlay(dev);
4503 }
4504
4505 void intel_modeset_cleanup(struct drm_device *dev)
4506 {
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct drm_crtc *crtc;
4509         struct intel_crtc *intel_crtc;
4510
4511         mutex_lock(&dev->struct_mutex);
4512
4513         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4514                 /* Skip inactive CRTCs */
4515                 if (!crtc->fb)
4516                         continue;
4517
4518                 intel_crtc = to_intel_crtc(crtc);
4519                 intel_increase_pllclock(crtc, false);
4520                 del_timer_sync(&intel_crtc->idle_timer);
4521         }
4522
4523         intel_increase_renderclock(dev, false);
4524         del_timer_sync(&dev_priv->idle_timer);
4525
4526         mutex_unlock(&dev->struct_mutex);
4527
4528         if (dev_priv->display.disable_fbc)
4529                 dev_priv->display.disable_fbc(dev);
4530
4531         if (dev_priv->pwrctx) {
4532                 i915_gem_object_unpin(dev_priv->pwrctx);
4533                 drm_gem_object_unreference(dev_priv->pwrctx);
4534         }
4535
4536         drm_mode_config_cleanup(dev);
4537 }
4538
4539
4540 /* current intel driver doesn't take advantage of encoders
4541    always give back the encoder for the connector
4542 */
4543 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4544 {
4545         struct intel_output *intel_output = to_intel_output(connector);
4546
4547         return &intel_output->enc;
4548 }
4549
4550 /*
4551  * set vga decode state - true == enable VGA decode
4552  */
4553 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4554 {
4555         struct drm_i915_private *dev_priv = dev->dev_private;
4556         u16 gmch_ctrl;
4557
4558         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4559         if (state)
4560                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4561         else
4562                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4563         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4564         return 0;
4565 }