drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include "drmP.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "drm_dp_helper.h"
  38
  39 #include "drm_crtc_helper.h"
  40
  41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  42
  43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  44 static void intel_update_watermarks(struct drm_device *dev);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  47
  48 typedef struct {
  49     /* given values */
  50     int n;
  51     int m1, m2;
  52     int p1, p2;
  53     /* derived values */
  54     int dot;
  55     int vco;
  56     int m;
  57     int p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61     int min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65     int dot_limit;
  66     int p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73     intel_p2_t      p2;
  74     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                       int, int, intel_clock_t *);
  76 };
  77
  78 #define I8XX_DOT_MIN              25000
  79 #define I8XX_DOT_MAX             350000
  80 #define I8XX_VCO_MIN             930000
  81 #define I8XX_VCO_MAX            1400000
  82 #define I8XX_N_MIN                    3
  83 #define I8XX_N_MAX                   16
  84 #define I8XX_M_MIN                   96
  85 #define I8XX_M_MAX                  140
  86 #define I8XX_M1_MIN                  18
  87 #define I8XX_M1_MAX                  26
  88 #define I8XX_M2_MIN                   6
  89 #define I8XX_M2_MAX                  16
  90 #define I8XX_P_MIN                    4
  91 #define I8XX_P_MAX                  128
  92 #define I8XX_P1_MIN                   2
  93 #define I8XX_P1_MAX                  33
  94 #define I8XX_P1_LVDS_MIN              1
  95 #define I8XX_P1_LVDS_MAX              6
  96 #define I8XX_P2_SLOW                  4
  97 #define I8XX_P2_FAST                  2
  98 #define I8XX_P2_LVDS_SLOW             14
  99 #define I8XX_P2_LVDS_FAST             7
 100 #define I8XX_P2_SLOW_LIMIT       165000
 101
 102 #define I9XX_DOT_MIN              20000
 103 #define I9XX_DOT_MAX             400000
 104 #define I9XX_VCO_MIN            1400000
 105 #define I9XX_VCO_MAX            2800000
 106 #define PINEVIEW_VCO_MIN                1700000
 107 #define PINEVIEW_VCO_MAX                3500000
 108 #define I9XX_N_MIN                    1
 109 #define I9XX_N_MAX                    6
 110 /* Pineview's Ncounter is a ring counter */
 111 #define PINEVIEW_N_MIN                3
 112 #define PINEVIEW_N_MAX                6
 113 #define I9XX_M_MIN                   70
 114 #define I9XX_M_MAX                  120
 115 #define PINEVIEW_M_MIN                2
 116 #define PINEVIEW_M_MAX              256
 117 #define I9XX_M1_MIN                  10
 118 #define I9XX_M1_MAX                  22
 119 #define I9XX_M2_MIN                   5
 120 #define I9XX_M2_MAX                   9
 121 /* Pineview M1 is reserved, and must be 0 */
 122 #define PINEVIEW_M1_MIN               0
 123 #define PINEVIEW_M1_MAX               0
 124 #define PINEVIEW_M2_MIN               0
 125 #define PINEVIEW_M2_MAX               254
 126 #define I9XX_P_SDVO_DAC_MIN           5
 127 #define I9XX_P_SDVO_DAC_MAX          80
 128 #define I9XX_P_LVDS_MIN               7
 129 #define I9XX_P_LVDS_MAX              98
 130 #define PINEVIEW_P_LVDS_MIN                   7
 131 #define PINEVIEW_P_LVDS_MAX                  112
 132 #define I9XX_P1_MIN                   1
 133 #define I9XX_P1_MAX                   8
 134 #define I9XX_P2_SDVO_DAC_SLOW                10
 135 #define I9XX_P2_SDVO_DAC_FAST                 5
 136 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 137 #define I9XX_P2_LVDS_SLOW                    14
 138 #define I9XX_P2_LVDS_FAST                     7
 139 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 140
 141 /*The parameter is for SDVO on G4x platform*/
 142 #define G4X_DOT_SDVO_MIN           25000
 143 #define G4X_DOT_SDVO_MAX           270000
 144 #define G4X_VCO_MIN                1750000
 145 #define G4X_VCO_MAX                3500000
 146 #define G4X_N_SDVO_MIN             1
 147 #define G4X_N_SDVO_MAX             4
 148 #define G4X_M_SDVO_MIN             104
 149 #define G4X_M_SDVO_MAX             138
 150 #define G4X_M1_SDVO_MIN            17
 151 #define G4X_M1_SDVO_MAX            23
 152 #define G4X_M2_SDVO_MIN            5
 153 #define G4X_M2_SDVO_MAX            11
 154 #define G4X_P_SDVO_MIN             10
 155 #define G4X_P_SDVO_MAX             30
 156 #define G4X_P1_SDVO_MIN            1
 157 #define G4X_P1_SDVO_MAX            3
 158 #define G4X_P2_SDVO_SLOW           10
 159 #define G4X_P2_SDVO_FAST           10
 160 #define G4X_P2_SDVO_LIMIT          270000
 161
 162 /*The parameter is for HDMI_DAC on G4x platform*/
 163 #define G4X_DOT_HDMI_DAC_MIN           22000
 164 #define G4X_DOT_HDMI_DAC_MAX           400000
 165 #define G4X_N_HDMI_DAC_MIN             1
 166 #define G4X_N_HDMI_DAC_MAX             4
 167 #define G4X_M_HDMI_DAC_MIN             104
 168 #define G4X_M_HDMI_DAC_MAX             138
 169 #define G4X_M1_HDMI_DAC_MIN            16
 170 #define G4X_M1_HDMI_DAC_MAX            23
 171 #define G4X_M2_HDMI_DAC_MIN            5
 172 #define G4X_M2_HDMI_DAC_MAX            11
 173 #define G4X_P_HDMI_DAC_MIN             5
 174 #define G4X_P_HDMI_DAC_MAX             80
 175 #define G4X_P1_HDMI_DAC_MIN            1
 176 #define G4X_P1_HDMI_DAC_MAX            8
 177 #define G4X_P2_HDMI_DAC_SLOW           10
 178 #define G4X_P2_HDMI_DAC_FAST           5
 179 #define G4X_P2_HDMI_DAC_LIMIT          165000
 180
 181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 199
 200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 218
 219 /*The parameter is for DISPLAY PORT on G4x platform*/
 220 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 221 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 222 #define G4X_N_DISPLAY_PORT_MIN             1
 223 #define G4X_N_DISPLAY_PORT_MAX             2
 224 #define G4X_M_DISPLAY_PORT_MIN             97
 225 #define G4X_M_DISPLAY_PORT_MAX             108
 226 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 227 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 228 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 229 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 230 #define G4X_P_DISPLAY_PORT_MIN             10
 231 #define G4X_P_DISPLAY_PORT_MAX             20
 232 #define G4X_P1_DISPLAY_PORT_MIN            1
 233 #define G4X_P1_DISPLAY_PORT_MAX            2
 234 #define G4X_P2_DISPLAY_PORT_SLOW           10
 235 #define G4X_P2_DISPLAY_PORT_FAST           10
 236 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 237
 238 /* Ironlake / Sandybridge */
 239 /* as we calculate clock using (register_value + 2) for
 240    N/M1/M2, so here the range value for them is (actual_value-2).
 241  */
 242 #define IRONLAKE_DOT_MIN         25000
 243 #define IRONLAKE_DOT_MAX         350000
 244 #define IRONLAKE_VCO_MIN         1760000
 245 #define IRONLAKE_VCO_MAX         3510000
 246 #define IRONLAKE_M1_MIN          12
 247 #define IRONLAKE_M1_MAX          22
 248 #define IRONLAKE_M2_MIN          5
 249 #define IRONLAKE_M2_MAX          9
 250 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 251
 252 /* We have parameter ranges for different type of outputs. */
 253
 254 /* DAC & HDMI Refclk 120Mhz */
 255 #define IRONLAKE_DAC_N_MIN      1
 256 #define IRONLAKE_DAC_N_MAX      5
 257 #define IRONLAKE_DAC_M_MIN      79
 258 #define IRONLAKE_DAC_M_MAX      127
 259 #define IRONLAKE_DAC_P_MIN      5
 260 #define IRONLAKE_DAC_P_MAX      80
 261 #define IRONLAKE_DAC_P1_MIN     1
 262 #define IRONLAKE_DAC_P1_MAX     8
 263 #define IRONLAKE_DAC_P2_SLOW    10
 264 #define IRONLAKE_DAC_P2_FAST    5
 265
 266 /* LVDS single-channel 120Mhz refclk */
 267 #define IRONLAKE_LVDS_S_N_MIN   1
 268 #define IRONLAKE_LVDS_S_N_MAX   3
 269 #define IRONLAKE_LVDS_S_M_MIN   79
 270 #define IRONLAKE_LVDS_S_M_MAX   118
 271 #define IRONLAKE_LVDS_S_P_MIN   28
 272 #define IRONLAKE_LVDS_S_P_MAX   112
 273 #define IRONLAKE_LVDS_S_P1_MIN  2
 274 #define IRONLAKE_LVDS_S_P1_MAX  8
 275 #define IRONLAKE_LVDS_S_P2_SLOW 14
 276 #define IRONLAKE_LVDS_S_P2_FAST 14
 277
 278 /* LVDS dual-channel 120Mhz refclk */
 279 #define IRONLAKE_LVDS_D_N_MIN   1
 280 #define IRONLAKE_LVDS_D_N_MAX   3
 281 #define IRONLAKE_LVDS_D_M_MIN   79
 282 #define IRONLAKE_LVDS_D_M_MAX   127
 283 #define IRONLAKE_LVDS_D_P_MIN   14
 284 #define IRONLAKE_LVDS_D_P_MAX   56
 285 #define IRONLAKE_LVDS_D_P1_MIN  2
 286 #define IRONLAKE_LVDS_D_P1_MAX  8
 287 #define IRONLAKE_LVDS_D_P2_SLOW 7
 288 #define IRONLAKE_LVDS_D_P2_FAST 7
 289
 290 /* LVDS single-channel 100Mhz refclk */
 291 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 292 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 293 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 294 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 295 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 296 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 297 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 298 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 299 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 300 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 301
 302 /* LVDS dual-channel 100Mhz refclk */
 303 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 304 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 305 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 306 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 307 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 308 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 309 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 310 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 311 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 312 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 313
 314 /* DisplayPort */
 315 #define IRONLAKE_DP_N_MIN               1
 316 #define IRONLAKE_DP_N_MAX               2
 317 #define IRONLAKE_DP_M_MIN               81
 318 #define IRONLAKE_DP_M_MAX               90
 319 #define IRONLAKE_DP_P_MIN               10
 320 #define IRONLAKE_DP_P_MAX               20
 321 #define IRONLAKE_DP_P2_FAST             10
 322 #define IRONLAKE_DP_P2_SLOW             10
 323 #define IRONLAKE_DP_P2_LIMIT            0
 324 #define IRONLAKE_DP_P1_MIN              1
 325 #define IRONLAKE_DP_P1_MAX              2
 326
 327 /* FDI */
 328 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 329
 330 static bool
 331 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 332                     int target, int refclk, intel_clock_t *best_clock);
 333 static bool
 334 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 335                         int target, int refclk, intel_clock_t *best_clock);
 336
 337 static bool
 338 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 339                       int target, int refclk, intel_clock_t *best_clock);
 340 static bool
 341 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 342                            int target, int refclk, intel_clock_t *best_clock);
 343
 344 static const intel_limit_t intel_limits_i8xx_dvo = {
 345         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 346         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 347         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 348         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 349         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 350         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 351         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 352         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 353         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 354                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 355         .find_pll = intel_find_best_PLL,
 356 };
 357
 358 static const intel_limit_t intel_limits_i8xx_lvds = {
 359         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 360         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 361         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 362         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 363         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 364         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 365         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 366         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 367         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 368                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 369         .find_pll = intel_find_best_PLL,
 370 };
 371
 372 static const intel_limit_t intel_limits_i9xx_sdvo = {
 373         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 374         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 375         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 376         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 377         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 378         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 379         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 380         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 381         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 382                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 383         .find_pll = intel_find_best_PLL,
 384 };
 385
 386 static const intel_limit_t intel_limits_i9xx_lvds = {
 387         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 388         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 389         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 390         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 391         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 392         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 393         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 394         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 395         /* The single-channel range is 25-112Mhz, and dual-channel
 396          * is 80-224Mhz.  Prefer single channel as much as possible.
 397          */
 398         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 399                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 400         .find_pll = intel_find_best_PLL,
 401 };
 402
 403     /* below parameter and function is for G4X Chipset Family*/
 404 static const intel_limit_t intel_limits_g4x_sdvo = {
 405         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 406         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 407         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 408         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 409         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 410         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 411         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 412         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 413         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 414                  .p2_slow = G4X_P2_SDVO_SLOW,
 415                  .p2_fast = G4X_P2_SDVO_FAST
 416         },
 417         .find_pll = intel_g4x_find_best_PLL,
 418 };
 419
 420 static const intel_limit_t intel_limits_g4x_hdmi = {
 421         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 422         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 423         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 424         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 425         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 426         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 427         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 428         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 429         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 430                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 431                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 432         },
 433         .find_pll = intel_g4x_find_best_PLL,
 434 };
 435
 436 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 437         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 439         .vco = { .min = G4X_VCO_MIN,
 440                  .max = G4X_VCO_MAX },
 441         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 443         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 445         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 447         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 448                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 449         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 451         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 453         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 454                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 455                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 456         },
 457         .find_pll = intel_g4x_find_best_PLL,
 458 };
 459
 460 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 461         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 463         .vco = { .min = G4X_VCO_MIN,
 464                  .max = G4X_VCO_MAX },
 465         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 467         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 469         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 471         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 472                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 473         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 475         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 477         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 478                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 479                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 480         },
 481         .find_pll = intel_g4x_find_best_PLL,
 482 };
 483
 484 static const intel_limit_t intel_limits_g4x_display_port = {
 485         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 486                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 487         .vco = { .min = G4X_VCO_MIN,
 488                  .max = G4X_VCO_MAX},
 489         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 490                  .max = G4X_N_DISPLAY_PORT_MAX },
 491         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 492                  .max = G4X_M_DISPLAY_PORT_MAX },
 493         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 494                  .max = G4X_M1_DISPLAY_PORT_MAX },
 495         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 496                  .max = G4X_M2_DISPLAY_PORT_MAX },
 497         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 498                  .max = G4X_P_DISPLAY_PORT_MAX },
 499         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 500                  .max = G4X_P1_DISPLAY_PORT_MAX},
 501         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 502                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 503                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 504         .find_pll = intel_find_pll_g4x_dp,
 505 };
 506
 507 static const intel_limit_t intel_limits_pineview_sdvo = {
 508         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 509         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 510         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 511         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 512         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 513         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 514         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 515         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 516         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 517                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 518         .find_pll = intel_find_best_PLL,
 519 };
 520
 521 static const intel_limit_t intel_limits_pineview_lvds = {
 522         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 523         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 524         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 525         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 526         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 527         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 528         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 529         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 530         /* Pineview only supports single-channel mode. */
 531         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 532                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 533         .find_pll = intel_find_best_PLL,
 534 };
 535
 536 static const intel_limit_t intel_limits_ironlake_dac = {
 537         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 538         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 539         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 540         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 541         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 542         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 543         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 544         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 545         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 546                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 547                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 548         .find_pll = intel_g4x_find_best_PLL,
 549 };
 550
 551 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 552         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 553         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 554         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 555         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 556         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 557         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 558         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 559         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 560         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 561                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 562                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 563         .find_pll = intel_g4x_find_best_PLL,
 564 };
 565
 566 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 567         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 568         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 569         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 570         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 571         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 572         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 573         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 574         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 575         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 576                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 577                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 578         .find_pll = intel_g4x_find_best_PLL,
 579 };
 580
 581 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 582         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 583         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 584         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 585         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 586         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 587         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 588         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 589         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 590         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 591                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 592                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 593         .find_pll = intel_g4x_find_best_PLL,
 594 };
 595
 596 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 597         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 598         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 599         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 600         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 601         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 602         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 603         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 604         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 605         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 606                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 607                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 608         .find_pll = intel_g4x_find_best_PLL,
 609 };
 610
 611 static const intel_limit_t intel_limits_ironlake_display_port = {
 612         .dot = { .min = IRONLAKE_DOT_MIN,
 613                  .max = IRONLAKE_DOT_MAX },
 614         .vco = { .min = IRONLAKE_VCO_MIN,
 615                  .max = IRONLAKE_VCO_MAX},
 616         .n   = { .min = IRONLAKE_DP_N_MIN,
 617                  .max = IRONLAKE_DP_N_MAX },
 618         .m   = { .min = IRONLAKE_DP_M_MIN,
 619                  .max = IRONLAKE_DP_M_MAX },
 620         .m1  = { .min = IRONLAKE_M1_MIN,
 621                  .max = IRONLAKE_M1_MAX },
 622         .m2  = { .min = IRONLAKE_M2_MIN,
 623                  .max = IRONLAKE_M2_MAX },
 624         .p   = { .min = IRONLAKE_DP_P_MIN,
 625                  .max = IRONLAKE_DP_P_MAX },
 626         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 627                  .max = IRONLAKE_DP_P1_MAX},
 628         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 629                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 630                  .p2_fast = IRONLAKE_DP_P2_FAST },
 631         .find_pll = intel_find_pll_ironlake_dp,
 632 };
 633
 634 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 635 {
 636         struct drm_device *dev = crtc->dev;
 637         struct drm_i915_private *dev_priv = dev->dev_private;
 638         const intel_limit_t *limit;
 639         int refclk = 120;
 640
 641         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 642                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 643                         refclk = 100;
 644
 645                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 646                     LVDS_CLKB_POWER_UP) {
 647                         /* LVDS dual channel */
 648                         if (refclk == 100)
 649                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 650                         else
 651                                 limit = &intel_limits_ironlake_dual_lvds;
 652                 } else {
 653                         if (refclk == 100)
 654                                 limit = &intel_limits_ironlake_single_lvds_100m;
 655                         else
 656                                 limit = &intel_limits_ironlake_single_lvds;
 657                 }
 658         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 659                         HAS_eDP)
 660                 limit = &intel_limits_ironlake_display_port;
 661         else
 662                 limit = &intel_limits_ironlake_dac;
 663
 664         return limit;
 665 }
 666
 667 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 668 {
 669         struct drm_device *dev = crtc->dev;
 670         struct drm_i915_private *dev_priv = dev->dev_private;
 671         const intel_limit_t *limit;
 672
 673         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 674                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 675                     LVDS_CLKB_POWER_UP)
 676                         /* LVDS with dual channel */
 677                         limit = &intel_limits_g4x_dual_channel_lvds;
 678                 else
 679                         /* LVDS with dual channel */
 680                         limit = &intel_limits_g4x_single_channel_lvds;
 681         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 682                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 683                 limit = &intel_limits_g4x_hdmi;
 684         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 685                 limit = &intel_limits_g4x_sdvo;
 686         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 687                 limit = &intel_limits_g4x_display_port;
 688         } else /* The option is for other outputs */
 689                 limit = &intel_limits_i9xx_sdvo;
 690
 691         return limit;
 692 }
 693
 694 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 695 {
 696         struct drm_device *dev = crtc->dev;
 697         const intel_limit_t *limit;
 698
 699         if (HAS_PCH_SPLIT(dev))
 700                 limit = intel_ironlake_limit(crtc);
 701         else if (IS_G4X(dev)) {
 702                 limit = intel_g4x_limit(crtc);
 703         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 704                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 705                         limit = &intel_limits_i9xx_lvds;
 706                 else
 707                         limit = &intel_limits_i9xx_sdvo;
 708         } else if (IS_PINEVIEW(dev)) {
 709                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 710                         limit = &intel_limits_pineview_lvds;
 711                 else
 712                         limit = &intel_limits_pineview_sdvo;
 713         } else {
 714                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 715                         limit = &intel_limits_i8xx_lvds;
 716                 else
 717                         limit = &intel_limits_i8xx_dvo;
 718         }
 719         return limit;
 720 }
 721
 722 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 723 static void pineview_clock(int refclk, intel_clock_t *clock)
 724 {
 725         clock->m = clock->m2 + 2;
 726         clock->p = clock->p1 * clock->p2;
 727         clock->vco = refclk * clock->m / clock->n;
 728         clock->dot = clock->vco / clock->p;
 729 }
 730
 731 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 732 {
 733         if (IS_PINEVIEW(dev)) {
 734                 pineview_clock(refclk, clock);
 735                 return;
 736         }
 737         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 738         clock->p = clock->p1 * clock->p2;
 739         clock->vco = refclk * clock->m / (clock->n + 2);
 740         clock->dot = clock->vco / clock->p;
 741 }
 742
 743 /**
 744  * Returns whether any output on the specified pipe is of the specified type
 745  */
 746 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 747 {
 748     struct drm_device *dev = crtc->dev;
 749     struct drm_mode_config *mode_config = &dev->mode_config;
 750     struct drm_encoder *l_entry;
 751
 752     list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
 753             if (l_entry && l_entry->crtc == crtc) {
 754                     struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
 755                     if (intel_encoder->type == type)
 756                             return true;
 757             }
 758     }
 759     return false;
 760 }
 761
 762 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 763 /**
 764  * Returns whether the given set of divisors are valid for a given refclk with
 765  * the given connectors.
 766  */
 767
 768 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 769 {
 770         const intel_limit_t *limit = intel_limit (crtc);
 771         struct drm_device *dev = crtc->dev;
 772
 773         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 774                 INTELPllInvalid ("p1 out of range\n");
 775         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 776                 INTELPllInvalid ("p out of range\n");
 777         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 778                 INTELPllInvalid ("m2 out of range\n");
 779         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 780                 INTELPllInvalid ("m1 out of range\n");
 781         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 782                 INTELPllInvalid ("m1 <= m2\n");
 783         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 784                 INTELPllInvalid ("m out of range\n");
 785         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 786                 INTELPllInvalid ("n out of range\n");
 787         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 788                 INTELPllInvalid ("vco out of range\n");
 789         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 790          * connector, etc., rather than just a single range.
 791          */
 792         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 793                 INTELPllInvalid ("dot out of range\n");
 794
 795         return true;
 796 }
 797
 798 static bool
 799 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 800                     int target, int refclk, intel_clock_t *best_clock)
 801
 802 {
 803         struct drm_device *dev = crtc->dev;
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         intel_clock_t clock;
 806         int err = target;
 807
 808         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 809             (I915_READ(LVDS)) != 0) {
 810                 /*
 811                  * For LVDS, if the panel is on, just rely on its current
 812                  * settings for dual-channel.  We haven't figured out how to
 813                  * reliably set up different single/dual channel state, if we
 814                  * even can.
 815                  */
 816                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 817                     LVDS_CLKB_POWER_UP)
 818                         clock.p2 = limit->p2.p2_fast;
 819                 else
 820                         clock.p2 = limit->p2.p2_slow;
 821         } else {
 822                 if (target < limit->p2.dot_limit)
 823                         clock.p2 = limit->p2.p2_slow;
 824                 else
 825                         clock.p2 = limit->p2.p2_fast;
 826         }
 827
 828         memset (best_clock, 0, sizeof (*best_clock));
 829
 830         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 831              clock.m1++) {
 832                 for (clock.m2 = limit->m2.min;
 833                      clock.m2 <= limit->m2.max; clock.m2++) {
 834                         /* m1 is always 0 in Pineview */
 835                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 836                                 break;
 837                         for (clock.n = limit->n.min;
 838                              clock.n <= limit->n.max; clock.n++) {
 839                                 for (clock.p1 = limit->p1.min;
 840                                         clock.p1 <= limit->p1.max; clock.p1++) {
 841                                         int this_err;
 842
 843                                         intel_clock(dev, refclk, &clock);
 844
 845                                         if (!intel_PLL_is_valid(crtc, &clock))
 846                                                 continue;
 847
 848                                         this_err = abs(clock.dot - target);
 849                                         if (this_err < err) {
 850                                                 *best_clock = clock;
 851                                                 err = this_err;
 852                                         }
 853                                 }
 854                         }
 855                 }
 856         }
 857
 858         return (err != target);
 859 }
 860
 861 static bool
 862 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *best_clock)
 864 {
 865         struct drm_device *dev = crtc->dev;
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         intel_clock_t clock;
 868         int max_n;
 869         bool found;
 870         /* approximately equals target * 0.00585 */
 871         int err_most = (target >> 8) + (target >> 9);
 872         found = false;
 873
 874         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 875                 int lvds_reg;
 876
 877                 if (HAS_PCH_SPLIT(dev))
 878                         lvds_reg = PCH_LVDS;
 879                 else
 880                         lvds_reg = LVDS;
 881                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 882                     LVDS_CLKB_POWER_UP)
 883                         clock.p2 = limit->p2.p2_fast;
 884                 else
 885                         clock.p2 = limit->p2.p2_slow;
 886         } else {
 887                 if (target < limit->p2.dot_limit)
 888                         clock.p2 = limit->p2.p2_slow;
 889                 else
 890                         clock.p2 = limit->p2.p2_fast;
 891         }
 892
 893         memset(best_clock, 0, sizeof(*best_clock));
 894         max_n = limit->n.max;
 895         /* based on hardware requirement, prefer smaller n to precision */
 896         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 897                 /* based on hardware requirement, prefere larger m1,m2 */
 898                 for (clock.m1 = limit->m1.max;
 899                      clock.m1 >= limit->m1.min; clock.m1--) {
 900                         for (clock.m2 = limit->m2.max;
 901                              clock.m2 >= limit->m2.min; clock.m2--) {
 902                                 for (clock.p1 = limit->p1.max;
 903                                      clock.p1 >= limit->p1.min; clock.p1--) {
 904                                         int this_err;
 905
 906                                         intel_clock(dev, refclk, &clock);
 907                                         if (!intel_PLL_is_valid(crtc, &clock))
 908                                                 continue;
 909                                         this_err = abs(clock.dot - target) ;
 910                                         if (this_err < err_most) {
 911                                                 *best_clock = clock;
 912                                                 err_most = this_err;
 913                                                 max_n = clock.n;
 914                                                 found = true;
 915                                         }
 916                                 }
 917                         }
 918                 }
 919         }
 920         return found;
 921 }
 922
 923 static bool
 924 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 925                            int target, int refclk, intel_clock_t *best_clock)
 926 {
 927         struct drm_device *dev = crtc->dev;
 928         intel_clock_t clock;
 929
 930         /* return directly when it is eDP */
 931         if (HAS_eDP)
 932                 return true;
 933
 934         if (target < 200000) {
 935                 clock.n = 1;
 936                 clock.p1 = 2;
 937                 clock.p2 = 10;
 938                 clock.m1 = 12;
 939                 clock.m2 = 9;
 940         } else {
 941                 clock.n = 2;
 942                 clock.p1 = 1;
 943                 clock.p2 = 10;
 944                 clock.m1 = 14;
 945                 clock.m2 = 8;
 946         }
 947         intel_clock(dev, refclk, &clock);
 948         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 949         return true;
 950 }
 951
 952 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 953 static bool
 954 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 955                       int target, int refclk, intel_clock_t *best_clock)
 956 {
 957     intel_clock_t clock;
 958     if (target < 200000) {
 959         clock.p1 = 2;
 960         clock.p2 = 10;
 961         clock.n = 2;
 962         clock.m1 = 23;
 963         clock.m2 = 8;
 964     } else {
 965         clock.p1 = 1;
 966         clock.p2 = 10;
 967         clock.n = 1;
 968         clock.m1 = 14;
 969         clock.m2 = 2;
 970     }
 971     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 972     clock.p = (clock.p1 * clock.p2);
 973     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 974     clock.vco = 0;
 975     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 976     return true;
 977 }
 978
 979 void
 980 intel_wait_for_vblank(struct drm_device *dev)
 981 {
 982         /* Wait for 20ms, i.e. one cycle at 50hz. */
 983         if (in_dbg_master())
 984                 mdelay(20); /* The kernel debugger cannot call msleep() */
 985         else
 986                 msleep(20);
 987 }
 988
 989 /* Parameters have changed, update FBC info */
 990 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 991 {
 992         struct drm_device *dev = crtc->dev;
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         struct drm_framebuffer *fb = crtc->fb;
 995         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 996         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
 997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 998         int plane, i;
 999         u32 fbc_ctl, fbc_ctl2;
1000
1001         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1002
1003         if (fb->pitch < dev_priv->cfb_pitch)
1004                 dev_priv->cfb_pitch = fb->pitch;
1005
1006         /* FBC_CTL wants 64B units */
1007         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1008         dev_priv->cfb_fence = obj_priv->fence_reg;
1009         dev_priv->cfb_plane = intel_crtc->plane;
1010         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1011
1012         /* Clear old tags */
1013         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1014                 I915_WRITE(FBC_TAG + (i * 4), 0);
1015
1016         /* Set it up... */
1017         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1018         if (obj_priv->tiling_mode != I915_TILING_NONE)
1019                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1020         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1021         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1022
1023         /* enable it... */
1024         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1025         if (IS_I945GM(dev))
1026                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1027         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1028         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1029         if (obj_priv->tiling_mode != I915_TILING_NONE)
1030                 fbc_ctl |= dev_priv->cfb_fence;
1031         I915_WRITE(FBC_CONTROL, fbc_ctl);
1032
1033         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1034                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1035 }
1036
1037 void i8xx_disable_fbc(struct drm_device *dev)
1038 {
1039         struct drm_i915_private *dev_priv = dev->dev_private;
1040         unsigned long timeout = jiffies + msecs_to_jiffies(1);
1041         u32 fbc_ctl;
1042
1043         if (!I915_HAS_FBC(dev))
1044                 return;
1045
1046         if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1047                 return; /* Already off, just return */
1048
1049         /* Disable compression */
1050         fbc_ctl = I915_READ(FBC_CONTROL);
1051         fbc_ctl &= ~FBC_CTL_EN;
1052         I915_WRITE(FBC_CONTROL, fbc_ctl);
1053
1054         /* Wait for compressing bit to clear */
1055         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1056                 if (time_after(jiffies, timeout)) {
1057                         DRM_DEBUG_DRIVER("FBC idle timed out\n");
1058                         break;
1059                 }
1060                 ; /* do nothing */
1061         }
1062
1063         intel_wait_for_vblank(dev);
1064
1065         DRM_DEBUG_KMS("disabled FBC\n");
1066 }
1067
1068 static bool i8xx_fbc_enabled(struct drm_device *dev)
1069 {
1070         struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1073 }
1074
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1076 {
1077         struct drm_device *dev = crtc->dev;
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         struct drm_framebuffer *fb = crtc->fb;
1080         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1084                      DPFC_CTL_PLANEB);
1085         unsigned long stall_watermark = 200;
1086         u32 dpfc_ctl;
1087
1088         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089         dev_priv->cfb_fence = obj_priv->fence_reg;
1090         dev_priv->cfb_plane = intel_crtc->plane;
1091
1092         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1096         } else {
1097                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1098         }
1099
1100         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1105
1106         /* enable it... */
1107         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1108
1109         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1110 }
1111
1112 void g4x_disable_fbc(struct drm_device *dev)
1113 {
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         u32 dpfc_ctl;
1116
1117         /* Disable compression */
1118         dpfc_ctl = I915_READ(DPFC_CONTROL);
1119         dpfc_ctl &= ~DPFC_CTL_EN;
1120         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121         intel_wait_for_vblank(dev);
1122
1123         DRM_DEBUG_KMS("disabled FBC\n");
1124 }
1125
1126 static bool g4x_fbc_enabled(struct drm_device *dev)
1127 {
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1131 }
1132
1133 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1134 {
1135         struct drm_device *dev = crtc->dev;
1136         struct drm_i915_private *dev_priv = dev->dev_private;
1137         struct drm_framebuffer *fb = crtc->fb;
1138         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1139         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1141         int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1142                                                DPFC_CTL_PLANEB;
1143         unsigned long stall_watermark = 200;
1144         u32 dpfc_ctl;
1145
1146         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1147         dev_priv->cfb_fence = obj_priv->fence_reg;
1148         dev_priv->cfb_plane = intel_crtc->plane;
1149
1150         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1151         dpfc_ctl &= DPFC_RESERVED;
1152         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1153         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1154                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1155                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1156         } else {
1157                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1158         }
1159
1160         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1161         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1162                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1163                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1164         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1165         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1166         /* enable it... */
1167         I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1168                    DPFC_CTL_EN);
1169
1170         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1171 }
1172
1173 void ironlake_disable_fbc(struct drm_device *dev)
1174 {
1175         struct drm_i915_private *dev_priv = dev->dev_private;
1176         u32 dpfc_ctl;
1177
1178         /* Disable compression */
1179         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1180         dpfc_ctl &= ~DPFC_CTL_EN;
1181         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1182         intel_wait_for_vblank(dev);
1183
1184         DRM_DEBUG_KMS("disabled FBC\n");
1185 }
1186
1187 static bool ironlake_fbc_enabled(struct drm_device *dev)
1188 {
1189         struct drm_i915_private *dev_priv = dev->dev_private;
1190
1191         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1192 }
1193
1194 bool intel_fbc_enabled(struct drm_device *dev)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197
1198         if (!dev_priv->display.fbc_enabled)
1199                 return false;
1200
1201         return dev_priv->display.fbc_enabled(dev);
1202 }
1203
1204 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1205 {
1206         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1207
1208         if (!dev_priv->display.enable_fbc)
1209                 return;
1210
1211         dev_priv->display.enable_fbc(crtc, interval);
1212 }
1213
1214 void intel_disable_fbc(struct drm_device *dev)
1215 {
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217
1218         if (!dev_priv->display.disable_fbc)
1219                 return;
1220
1221         dev_priv->display.disable_fbc(dev);
1222 }
1223
1224 /**
1225  * intel_update_fbc - enable/disable FBC as needed
1226  * @crtc: CRTC to point the compressor at
1227  * @mode: mode in use
1228  *
1229  * Set up the framebuffer compression hardware at mode set time.  We
1230  * enable it if possible:
1231  *   - plane A only (on pre-965)
1232  *   - no pixel mulitply/line duplication
1233  *   - no alpha buffer discard
1234  *   - no dual wide
1235  *   - framebuffer <= 2048 in width, 1536 in height
1236  *
1237  * We can't assume that any compression will take place (worst case),
1238  * so the compressed buffer has to be the same size as the uncompressed
1239  * one.  It also must reside (along with the line length buffer) in
1240  * stolen memory.
1241  *
1242  * We need to enable/disable FBC on a global basis.
1243  */
1244 static void intel_update_fbc(struct drm_crtc *crtc,
1245                              struct drm_display_mode *mode)
1246 {
1247         struct drm_device *dev = crtc->dev;
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249         struct drm_framebuffer *fb = crtc->fb;
1250         struct intel_framebuffer *intel_fb;
1251         struct drm_i915_gem_object *obj_priv;
1252         struct drm_crtc *tmp_crtc;
1253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1254         int plane = intel_crtc->plane;
1255         int crtcs_enabled = 0;
1256
1257         DRM_DEBUG_KMS("\n");
1258
1259         if (!i915_powersave)
1260                 return;
1261
1262         if (!I915_HAS_FBC(dev))
1263                 return;
1264
1265         if (!crtc->fb)
1266                 return;
1267
1268         intel_fb = to_intel_framebuffer(fb);
1269         obj_priv = to_intel_bo(intel_fb->obj);
1270
1271         /*
1272          * If FBC is already on, we just have to verify that we can
1273          * keep it that way...
1274          * Need to disable if:
1275          *   - more than one pipe is active
1276          *   - changing FBC params (stride, fence, mode)
1277          *   - new fb is too large to fit in compressed buffer
1278          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1279          */
1280         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1281                 if (tmp_crtc->enabled)
1282                         crtcs_enabled++;
1283         }
1284         DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1285         if (crtcs_enabled > 1) {
1286                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1287                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1288                 goto out_disable;
1289         }
1290         if (intel_fb->obj->size > dev_priv->cfb_size) {
1291                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1292                                 "compression\n");
1293                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1294                 goto out_disable;
1295         }
1296         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1297             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1298                 DRM_DEBUG_KMS("mode incompatible with compression, "
1299                                 "disabling\n");
1300                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1301                 goto out_disable;
1302         }
1303         if ((mode->hdisplay > 2048) ||
1304             (mode->vdisplay > 1536)) {
1305                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1306                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1307                 goto out_disable;
1308         }
1309         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1310                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1311                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1312                 goto out_disable;
1313         }
1314         if (obj_priv->tiling_mode != I915_TILING_X) {
1315                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1316                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1317                 goto out_disable;
1318         }
1319
1320         /* If the kernel debugger is active, always disable compression */
1321         if (in_dbg_master())
1322                 goto out_disable;
1323
1324         if (intel_fbc_enabled(dev)) {
1325                 /* We can re-enable it in this case, but need to update pitch */
1326                 if ((fb->pitch > dev_priv->cfb_pitch) ||
1327                     (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1328                     (plane != dev_priv->cfb_plane))
1329                         intel_disable_fbc(dev);
1330         }
1331
1332         /* Now try to turn it back on if possible */
1333         if (!intel_fbc_enabled(dev))
1334                 intel_enable_fbc(crtc, 500);
1335
1336         return;
1337
1338 out_disable:
1339         /* Multiple disables should be harmless */
1340         if (intel_fbc_enabled(dev)) {
1341                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1342                 intel_disable_fbc(dev);
1343         }
1344 }
1345
1346 int
1347 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1348 {
1349         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1350         u32 alignment;
1351         int ret;
1352
1353         switch (obj_priv->tiling_mode) {
1354         case I915_TILING_NONE:
1355                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1356                         alignment = 128 * 1024;
1357                 else if (IS_I965G(dev))
1358                         alignment = 4 * 1024;
1359                 else
1360                         alignment = 64 * 1024;
1361                 break;
1362         case I915_TILING_X:
1363                 /* pin() will align the object as required by fence */
1364                 alignment = 0;
1365                 break;
1366         case I915_TILING_Y:
1367                 /* FIXME: Is this true? */
1368                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1369                 return -EINVAL;
1370         default:
1371                 BUG();
1372         }
1373
1374         ret = i915_gem_object_pin(obj, alignment);
1375         if (ret != 0)
1376                 return ret;
1377
1378         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1379          * fence, whereas 965+ only requires a fence if using
1380          * framebuffer compression.  For simplicity, we always install
1381          * a fence as the cost is not that onerous.
1382          */
1383         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1384             obj_priv->tiling_mode != I915_TILING_NONE) {
1385                 ret = i915_gem_object_get_fence_reg(obj);
1386                 if (ret != 0) {
1387                         i915_gem_object_unpin(obj);
1388                         return ret;
1389                 }
1390         }
1391
1392         return 0;
1393 }
1394
1395 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1396 static int
1397 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1398                            int x, int y)
1399 {
1400         struct drm_device *dev = crtc->dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1403         struct intel_framebuffer *intel_fb;
1404         struct drm_i915_gem_object *obj_priv;
1405         struct drm_gem_object *obj;
1406         int plane = intel_crtc->plane;
1407         unsigned long Start, Offset;
1408         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1409         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1410         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1411         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1412         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1413         u32 dspcntr;
1414
1415         switch (plane) {
1416         case 0:
1417         case 1:
1418                 break;
1419         default:
1420                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1421                 return -EINVAL;
1422         }
1423
1424         intel_fb = to_intel_framebuffer(fb);
1425         obj = intel_fb->obj;
1426         obj_priv = to_intel_bo(obj);
1427
1428         dspcntr = I915_READ(dspcntr_reg);
1429         /* Mask out pixel format bits in case we change it */
1430         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1431         switch (fb->bits_per_pixel) {
1432         case 8:
1433                 dspcntr |= DISPPLANE_8BPP;
1434                 break;
1435         case 16:
1436                 if (fb->depth == 15)
1437                         dspcntr |= DISPPLANE_15_16BPP;
1438                 else
1439                         dspcntr |= DISPPLANE_16BPP;
1440                 break;
1441         case 24:
1442         case 32:
1443                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1444                 break;
1445         default:
1446                 DRM_ERROR("Unknown color depth\n");
1447                 return -EINVAL;
1448         }
1449         if (IS_I965G(dev)) {
1450                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1451                         dspcntr |= DISPPLANE_TILED;
1452                 else
1453                         dspcntr &= ~DISPPLANE_TILED;
1454         }
1455
1456         if (IS_IRONLAKE(dev))
1457                 /* must disable */
1458                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1459
1460         I915_WRITE(dspcntr_reg, dspcntr);
1461
1462         Start = obj_priv->gtt_offset;
1463         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1464
1465         DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1466         I915_WRITE(dspstride, fb->pitch);
1467         if (IS_I965G(dev)) {
1468                 I915_WRITE(dspbase, Offset);
1469                 I915_READ(dspbase);
1470                 I915_WRITE(dspsurf, Start);
1471                 I915_READ(dspsurf);
1472                 I915_WRITE(dsptileoff, (y << 16) | x);
1473         } else {
1474                 I915_WRITE(dspbase, Start + Offset);
1475                 I915_READ(dspbase);
1476         }
1477
1478         if ((IS_I965G(dev) || plane == 0))
1479                 intel_update_fbc(crtc, &crtc->mode);
1480
1481         intel_wait_for_vblank(dev);
1482         intel_increase_pllclock(crtc, true);
1483
1484         return 0;
1485 }
1486
1487 static int
1488 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1489                     struct drm_framebuffer *old_fb)
1490 {
1491         struct drm_device *dev = crtc->dev;
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493         struct drm_i915_master_private *master_priv;
1494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495         struct intel_framebuffer *intel_fb;
1496         struct drm_i915_gem_object *obj_priv;
1497         struct drm_gem_object *obj;
1498         int pipe = intel_crtc->pipe;
1499         int plane = intel_crtc->plane;
1500         unsigned long Start, Offset;
1501         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1502         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1503         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1504         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1505         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1506         u32 dspcntr;
1507         int ret;
1508
1509         /* no fb bound */
1510         if (!crtc->fb) {
1511                 DRM_DEBUG_KMS("No FB bound\n");
1512                 return 0;
1513         }
1514
1515         switch (plane) {
1516         case 0:
1517         case 1:
1518                 break;
1519         default:
1520                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1521                 return -EINVAL;
1522         }
1523
1524         intel_fb = to_intel_framebuffer(crtc->fb);
1525         obj = intel_fb->obj;
1526         obj_priv = to_intel_bo(obj);
1527
1528         mutex_lock(&dev->struct_mutex);
1529         ret = intel_pin_and_fence_fb_obj(dev, obj);
1530         if (ret != 0) {
1531                 mutex_unlock(&dev->struct_mutex);
1532                 return ret;
1533         }
1534
1535         ret = i915_gem_object_set_to_display_plane(obj);
1536         if (ret != 0) {
1537                 i915_gem_object_unpin(obj);
1538                 mutex_unlock(&dev->struct_mutex);
1539                 return ret;
1540         }
1541
1542         dspcntr = I915_READ(dspcntr_reg);
1543         /* Mask out pixel format bits in case we change it */
1544         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545         switch (crtc->fb->bits_per_pixel) {
1546         case 8:
1547                 dspcntr |= DISPPLANE_8BPP;
1548                 break;
1549         case 16:
1550                 if (crtc->fb->depth == 15)
1551                         dspcntr |= DISPPLANE_15_16BPP;
1552                 else
1553                         dspcntr |= DISPPLANE_16BPP;
1554                 break;
1555         case 24:
1556         case 32:
1557                 if (crtc->fb->depth == 30)
1558                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1559                 else
1560                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1561                 break;
1562         default:
1563                 DRM_ERROR("Unknown color depth\n");
1564                 i915_gem_object_unpin(obj);
1565                 mutex_unlock(&dev->struct_mutex);
1566                 return -EINVAL;
1567         }
1568         if (IS_I965G(dev)) {
1569                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1570                         dspcntr |= DISPPLANE_TILED;
1571                 else
1572                         dspcntr &= ~DISPPLANE_TILED;
1573         }
1574
1575         if (HAS_PCH_SPLIT(dev))
1576                 /* must disable */
1577                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1578
1579         I915_WRITE(dspcntr_reg, dspcntr);
1580
1581         Start = obj_priv->gtt_offset;
1582         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1583
1584         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585                       Start, Offset, x, y, crtc->fb->pitch);
1586         I915_WRITE(dspstride, crtc->fb->pitch);
1587         if (IS_I965G(dev)) {
1588                 I915_WRITE(dspbase, Offset);
1589                 I915_READ(dspbase);
1590                 I915_WRITE(dspsurf, Start);
1591                 I915_READ(dspsurf);
1592                 I915_WRITE(dsptileoff, (y << 16) | x);
1593         } else {
1594                 I915_WRITE(dspbase, Start + Offset);
1595                 I915_READ(dspbase);
1596         }
1597
1598         if ((IS_I965G(dev) || plane == 0))
1599                 intel_update_fbc(crtc, &crtc->mode);
1600
1601         intel_wait_for_vblank(dev);
1602
1603         if (old_fb) {
1604                 intel_fb = to_intel_framebuffer(old_fb);
1605                 obj_priv = to_intel_bo(intel_fb->obj);
1606                 i915_gem_object_unpin(intel_fb->obj);
1607         }
1608         intel_increase_pllclock(crtc, true);
1609
1610         mutex_unlock(&dev->struct_mutex);
1611
1612         if (!dev->primary->master)
1613                 return 0;
1614
1615         master_priv = dev->primary->master->driver_priv;
1616         if (!master_priv->sarea_priv)
1617                 return 0;
1618
1619         if (pipe) {
1620                 master_priv->sarea_priv->pipeB_x = x;
1621                 master_priv->sarea_priv->pipeB_y = y;
1622         } else {
1623                 master_priv->sarea_priv->pipeA_x = x;
1624                 master_priv->sarea_priv->pipeA_y = y;
1625         }
1626
1627         return 0;
1628 }
1629
1630 /* Disable the VGA plane that we never use */
1631 static void i915_disable_vga (struct drm_device *dev)
1632 {
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634         u8 sr1;
1635         u32 vga_reg;
1636
1637         if (HAS_PCH_SPLIT(dev))
1638                 vga_reg = CPU_VGACNTRL;
1639         else
1640                 vga_reg = VGACNTRL;
1641
1642         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1643                 return;
1644
1645         I915_WRITE8(VGA_SR_INDEX, 1);
1646         sr1 = I915_READ8(VGA_SR_DATA);
1647         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1648         udelay(100);
1649
1650         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1651 }
1652
1653 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1654 {
1655         struct drm_device *dev = crtc->dev;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657         u32 dpa_ctl;
1658
1659         DRM_DEBUG_KMS("\n");
1660         dpa_ctl = I915_READ(DP_A);
1661         dpa_ctl &= ~DP_PLL_ENABLE;
1662         I915_WRITE(DP_A, dpa_ctl);
1663 }
1664
1665 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1666 {
1667         struct drm_device *dev = crtc->dev;
1668         struct drm_i915_private *dev_priv = dev->dev_private;
1669         u32 dpa_ctl;
1670
1671         dpa_ctl = I915_READ(DP_A);
1672         dpa_ctl |= DP_PLL_ENABLE;
1673         I915_WRITE(DP_A, dpa_ctl);
1674         udelay(200);
1675 }
1676
1677
1678 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1679 {
1680         struct drm_device *dev = crtc->dev;
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682         u32 dpa_ctl;
1683
1684         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1685         dpa_ctl = I915_READ(DP_A);
1686         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1687
1688         if (clock < 200000) {
1689                 u32 temp;
1690                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1691                 /* workaround for 160Mhz:
1692                    1) program 0x4600c bits 15:0 = 0x8124
1693                    2) program 0x46010 bit 0 = 1
1694                    3) program 0x46034 bit 24 = 1
1695                    4) program 0x64000 bit 14 = 1
1696                    */
1697                 temp = I915_READ(0x4600c);
1698                 temp &= 0xffff0000;
1699                 I915_WRITE(0x4600c, temp | 0x8124);
1700
1701                 temp = I915_READ(0x46010);
1702                 I915_WRITE(0x46010, temp | 1);
1703
1704                 temp = I915_READ(0x46034);
1705                 I915_WRITE(0x46034, temp | (1 << 24));
1706         } else {
1707                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1708         }
1709         I915_WRITE(DP_A, dpa_ctl);
1710
1711         udelay(500);
1712 }
1713
1714 /* The FDI link training functions for ILK/Ibexpeak. */
1715 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1716 {
1717         struct drm_device *dev = crtc->dev;
1718         struct drm_i915_private *dev_priv = dev->dev_private;
1719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1720         int pipe = intel_crtc->pipe;
1721         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1722         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1723         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1724         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1725         u32 temp, tries = 0;
1726
1727         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1728            for train result */
1729         temp = I915_READ(fdi_rx_imr_reg);
1730         temp &= ~FDI_RX_SYMBOL_LOCK;
1731         temp &= ~FDI_RX_BIT_LOCK;
1732         I915_WRITE(fdi_rx_imr_reg, temp);
1733         I915_READ(fdi_rx_imr_reg);
1734         udelay(150);
1735
1736         /* enable CPU FDI TX and PCH FDI RX */
1737         temp = I915_READ(fdi_tx_reg);
1738         temp |= FDI_TX_ENABLE;
1739         temp &= ~(7 << 19);
1740         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1741         temp &= ~FDI_LINK_TRAIN_NONE;
1742         temp |= FDI_LINK_TRAIN_PATTERN_1;
1743         I915_WRITE(fdi_tx_reg, temp);
1744         I915_READ(fdi_tx_reg);
1745
1746         temp = I915_READ(fdi_rx_reg);
1747         temp &= ~FDI_LINK_TRAIN_NONE;
1748         temp |= FDI_LINK_TRAIN_PATTERN_1;
1749         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1750         I915_READ(fdi_rx_reg);
1751         udelay(150);
1752
1753         for (tries = 0; tries < 5; tries++) {
1754                 temp = I915_READ(fdi_rx_iir_reg);
1755                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1756
1757                 if ((temp & FDI_RX_BIT_LOCK)) {
1758                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1759                         I915_WRITE(fdi_rx_iir_reg,
1760                                    temp | FDI_RX_BIT_LOCK);
1761                         break;
1762                 }
1763         }
1764         if (tries == 5)
1765                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1766
1767         /* Train 2 */
1768         temp = I915_READ(fdi_tx_reg);
1769         temp &= ~FDI_LINK_TRAIN_NONE;
1770         temp |= FDI_LINK_TRAIN_PATTERN_2;
1771         I915_WRITE(fdi_tx_reg, temp);
1772
1773         temp = I915_READ(fdi_rx_reg);
1774         temp &= ~FDI_LINK_TRAIN_NONE;
1775         temp |= FDI_LINK_TRAIN_PATTERN_2;
1776         I915_WRITE(fdi_rx_reg, temp);
1777         udelay(150);
1778
1779         tries = 0;
1780
1781         for (tries = 0; tries < 5; tries++) {
1782                 temp = I915_READ(fdi_rx_iir_reg);
1783                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1784
1785                 if (temp & FDI_RX_SYMBOL_LOCK) {
1786                         I915_WRITE(fdi_rx_iir_reg,
1787                                    temp | FDI_RX_SYMBOL_LOCK);
1788                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1789                         break;
1790                 }
1791         }
1792         if (tries == 5)
1793                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1794
1795         DRM_DEBUG_KMS("FDI train done\n");
1796 }
1797
1798 static int snb_b_fdi_train_param [] = {
1799         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1800         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1801         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1802         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1803 };
1804
1805 /* The FDI link training functions for SNB/Cougarpoint. */
1806 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1807 {
1808         struct drm_device *dev = crtc->dev;
1809         struct drm_i915_private *dev_priv = dev->dev_private;
1810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1811         int pipe = intel_crtc->pipe;
1812         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1813         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1814         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1815         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1816         u32 temp, i;
1817
1818         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1819            for train result */
1820         temp = I915_READ(fdi_rx_imr_reg);
1821         temp &= ~FDI_RX_SYMBOL_LOCK;
1822         temp &= ~FDI_RX_BIT_LOCK;
1823         I915_WRITE(fdi_rx_imr_reg, temp);
1824         I915_READ(fdi_rx_imr_reg);
1825         udelay(150);
1826
1827         /* enable CPU FDI TX and PCH FDI RX */
1828         temp = I915_READ(fdi_tx_reg);
1829         temp |= FDI_TX_ENABLE;
1830         temp &= ~(7 << 19);
1831         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1832         temp &= ~FDI_LINK_TRAIN_NONE;
1833         temp |= FDI_LINK_TRAIN_PATTERN_1;
1834         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1835         /* SNB-B */
1836         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1837         I915_WRITE(fdi_tx_reg, temp);
1838         I915_READ(fdi_tx_reg);
1839
1840         temp = I915_READ(fdi_rx_reg);
1841         if (HAS_PCH_CPT(dev)) {
1842                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1843                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1844         } else {
1845                 temp &= ~FDI_LINK_TRAIN_NONE;
1846                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1847         }
1848         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1849         I915_READ(fdi_rx_reg);
1850         udelay(150);
1851
1852         for (i = 0; i < 4; i++ ) {
1853                 temp = I915_READ(fdi_tx_reg);
1854                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1855                 temp |= snb_b_fdi_train_param[i];
1856                 I915_WRITE(fdi_tx_reg, temp);
1857                 udelay(500);
1858
1859                 temp = I915_READ(fdi_rx_iir_reg);
1860                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1861
1862                 if (temp & FDI_RX_BIT_LOCK) {
1863                         I915_WRITE(fdi_rx_iir_reg,
1864                                    temp | FDI_RX_BIT_LOCK);
1865                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1866                         break;
1867                 }
1868         }
1869         if (i == 4)
1870                 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1871
1872         /* Train 2 */
1873         temp = I915_READ(fdi_tx_reg);
1874         temp &= ~FDI_LINK_TRAIN_NONE;
1875         temp |= FDI_LINK_TRAIN_PATTERN_2;
1876         if (IS_GEN6(dev)) {
1877                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1878                 /* SNB-B */
1879                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1880         }
1881         I915_WRITE(fdi_tx_reg, temp);
1882
1883         temp = I915_READ(fdi_rx_reg);
1884         if (HAS_PCH_CPT(dev)) {
1885                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1886                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1887         } else {
1888                 temp &= ~FDI_LINK_TRAIN_NONE;
1889                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1890         }
1891         I915_WRITE(fdi_rx_reg, temp);
1892         udelay(150);
1893
1894         for (i = 0; i < 4; i++ ) {
1895                 temp = I915_READ(fdi_tx_reg);
1896                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1897                 temp |= snb_b_fdi_train_param[i];
1898                 I915_WRITE(fdi_tx_reg, temp);
1899                 udelay(500);
1900
1901                 temp = I915_READ(fdi_rx_iir_reg);
1902                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1903
1904                 if (temp & FDI_RX_SYMBOL_LOCK) {
1905                         I915_WRITE(fdi_rx_iir_reg,
1906                                    temp | FDI_RX_SYMBOL_LOCK);
1907                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1908                         break;
1909                 }
1910         }
1911         if (i == 4)
1912                 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1913
1914         DRM_DEBUG_KMS("FDI train done.\n");
1915 }
1916
1917 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1918 {
1919         struct drm_device *dev = crtc->dev;
1920         struct drm_i915_private *dev_priv = dev->dev_private;
1921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922         int pipe = intel_crtc->pipe;
1923         int plane = intel_crtc->plane;
1924         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1925         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1926         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1927         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1928         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1929         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1930         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1931         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1932         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1933         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1934         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1935         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1936         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1937         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1938         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1939         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1940         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1941         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1942         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1943         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1944         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1945         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1946         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1947         u32 temp;
1948         int n;
1949         u32 pipe_bpc;
1950
1951         temp = I915_READ(pipeconf_reg);
1952         pipe_bpc = temp & PIPE_BPC_MASK;
1953
1954         /* XXX: When our outputs are all unaware of DPMS modes other than off
1955          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1956          */
1957         switch (mode) {
1958         case DRM_MODE_DPMS_ON:
1959         case DRM_MODE_DPMS_STANDBY:
1960         case DRM_MODE_DPMS_SUSPEND:
1961                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1962
1963                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1964                         temp = I915_READ(PCH_LVDS);
1965                         if ((temp & LVDS_PORT_EN) == 0) {
1966                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1967                                 POSTING_READ(PCH_LVDS);
1968                         }
1969                 }
1970
1971                 if (HAS_eDP) {
1972                         /* enable eDP PLL */
1973                         ironlake_enable_pll_edp(crtc);
1974                 } else {
1975
1976                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1977                         temp = I915_READ(fdi_rx_reg);
1978                         /*
1979                          * make the BPC in FDI Rx be consistent with that in
1980                          * pipeconf reg.
1981                          */
1982                         temp &= ~(0x7 << 16);
1983                         temp |= (pipe_bpc << 11);
1984                         temp &= ~(7 << 19);
1985                         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1986                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1987                         I915_READ(fdi_rx_reg);
1988                         udelay(200);
1989
1990                         /* Switch from Rawclk to PCDclk */
1991                         temp = I915_READ(fdi_rx_reg);
1992                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1993                         I915_READ(fdi_rx_reg);
1994                         udelay(200);
1995
1996                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1997                         temp = I915_READ(fdi_tx_reg);
1998                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1999                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
2000                                 I915_READ(fdi_tx_reg);
2001                                 udelay(100);
2002                         }
2003                 }
2004
2005                 /* Enable panel fitting for LVDS */
2006                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2007                     || HAS_eDP || intel_pch_has_edp(crtc)) {
2008                         if (dev_priv->pch_pf_size) {
2009                                 temp = I915_READ(pf_ctl_reg);
2010                                 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
2011                                 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
2012                                 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
2013                         } else
2014                                 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2015                 }
2016
2017                 /* Enable CPU pipe */
2018                 temp = I915_READ(pipeconf_reg);
2019                 if ((temp & PIPEACONF_ENABLE) == 0) {
2020                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2021                         I915_READ(pipeconf_reg);
2022                         udelay(100);
2023                 }
2024
2025                 /* configure and enable CPU plane */
2026                 temp = I915_READ(dspcntr_reg);
2027                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2028                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2029                         /* Flush the plane changes */
2030                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2031                 }
2032
2033                 if (!HAS_eDP) {
2034                         /* For PCH output, training FDI link */
2035                         if (IS_GEN6(dev))
2036                                 gen6_fdi_link_train(crtc);
2037                         else
2038                                 ironlake_fdi_link_train(crtc);
2039
2040                         /* enable PCH DPLL */
2041                         temp = I915_READ(pch_dpll_reg);
2042                         if ((temp & DPLL_VCO_ENABLE) == 0) {
2043                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2044                                 I915_READ(pch_dpll_reg);
2045                         }
2046                         udelay(200);
2047
2048                         if (HAS_PCH_CPT(dev)) {
2049                                 /* Be sure PCH DPLL SEL is set */
2050                                 temp = I915_READ(PCH_DPLL_SEL);
2051                                 if (trans_dpll_sel == 0 &&
2052                                                 (temp & TRANSA_DPLL_ENABLE) == 0)
2053                                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2054                                 else if (trans_dpll_sel == 1 &&
2055                                                 (temp & TRANSB_DPLL_ENABLE) == 0)
2056                                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2057                                 I915_WRITE(PCH_DPLL_SEL, temp);
2058                                 I915_READ(PCH_DPLL_SEL);
2059                         }
2060
2061                         /* set transcoder timing */
2062                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2063                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2064                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2065
2066                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2067                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2068                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2069
2070                         /* enable normal train */
2071                         temp = I915_READ(fdi_tx_reg);
2072                         temp &= ~FDI_LINK_TRAIN_NONE;
2073                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2074                                         FDI_TX_ENHANCE_FRAME_ENABLE);
2075                         I915_READ(fdi_tx_reg);
2076
2077                         temp = I915_READ(fdi_rx_reg);
2078                         if (HAS_PCH_CPT(dev)) {
2079                                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2080                                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2081                         } else {
2082                                 temp &= ~FDI_LINK_TRAIN_NONE;
2083                                 temp |= FDI_LINK_TRAIN_NONE;
2084                         }
2085                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2086                         I915_READ(fdi_rx_reg);
2087
2088                         /* wait one idle pattern time */
2089                         udelay(100);
2090
2091                         /* For PCH DP, enable TRANS_DP_CTL */
2092                         if (HAS_PCH_CPT(dev) &&
2093                             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2094                                 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2095                                 int reg;
2096
2097                                 reg = I915_READ(trans_dp_ctl);
2098                                 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2099                                          TRANS_DP_SYNC_MASK);
2100                                 reg |= (TRANS_DP_OUTPUT_ENABLE |
2101                                         TRANS_DP_ENH_FRAMING);
2102
2103                                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2104                                       reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2105                                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2106                                       reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2107
2108                                 switch (intel_trans_dp_port_sel(crtc)) {
2109                                 case PCH_DP_B:
2110                                         reg |= TRANS_DP_PORT_SEL_B;
2111                                         break;
2112                                 case PCH_DP_C:
2113                                         reg |= TRANS_DP_PORT_SEL_C;
2114                                         break;
2115                                 case PCH_DP_D:
2116                                         reg |= TRANS_DP_PORT_SEL_D;
2117                                         break;
2118                                 default:
2119                                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2120                                         reg |= TRANS_DP_PORT_SEL_B;
2121                                         break;
2122                                 }
2123
2124                                 I915_WRITE(trans_dp_ctl, reg);
2125                                 POSTING_READ(trans_dp_ctl);
2126                         }
2127
2128                         /* enable PCH transcoder */
2129                         temp = I915_READ(transconf_reg);
2130                         /*
2131                          * make the BPC in transcoder be consistent with
2132                          * that in pipeconf reg.
2133                          */
2134                         temp &= ~PIPE_BPC_MASK;
2135                         temp |= pipe_bpc;
2136                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2137                         I915_READ(transconf_reg);
2138
2139                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2140                                 ;
2141
2142                 }
2143
2144                 intel_crtc_load_lut(crtc);
2145
2146                 intel_update_fbc(crtc, &crtc->mode);
2147
2148         break;
2149         case DRM_MODE_DPMS_OFF:
2150                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
2151
2152                 drm_vblank_off(dev, pipe);
2153                 /* Disable display plane */
2154                 temp = I915_READ(dspcntr_reg);
2155                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2156                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2157                         /* Flush the plane changes */
2158                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2159                         I915_READ(dspbase_reg);
2160                 }
2161
2162                 if (dev_priv->cfb_plane == plane &&
2163                     dev_priv->display.disable_fbc)
2164                         dev_priv->display.disable_fbc(dev);
2165
2166                 i915_disable_vga(dev);
2167
2168                 /* disable cpu pipe, disable after all planes disabled */
2169                 temp = I915_READ(pipeconf_reg);
2170                 if ((temp & PIPEACONF_ENABLE) != 0) {
2171                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2172                         I915_READ(pipeconf_reg);
2173                         n = 0;
2174                         /* wait for cpu pipe off, pipe state */
2175                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2176                                 n++;
2177                                 if (n < 60) {
2178                                         udelay(500);
2179                                         continue;
2180                                 } else {
2181                                         DRM_DEBUG_KMS("pipe %d off delay\n",
2182                                                                 pipe);
2183                                         break;
2184                                 }
2185                         }
2186                 } else
2187                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2188
2189                 udelay(100);
2190
2191                 /* Disable PF */
2192                 temp = I915_READ(pf_ctl_reg);
2193                 if ((temp & PF_ENABLE) != 0) {
2194                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2195                         I915_READ(pf_ctl_reg);
2196                 }
2197                 I915_WRITE(pf_win_size, 0);
2198                 POSTING_READ(pf_win_size);
2199
2200
2201                 /* disable CPU FDI tx and PCH FDI rx */
2202                 temp = I915_READ(fdi_tx_reg);
2203                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2204                 I915_READ(fdi_tx_reg);
2205
2206                 temp = I915_READ(fdi_rx_reg);
2207                 /* BPC in FDI rx is consistent with that in pipeconf */
2208                 temp &= ~(0x07 << 16);
2209                 temp |= (pipe_bpc << 11);
2210                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2211                 I915_READ(fdi_rx_reg);
2212
2213                 udelay(100);
2214
2215                 /* still set train pattern 1 */
2216                 temp = I915_READ(fdi_tx_reg);
2217                 temp &= ~FDI_LINK_TRAIN_NONE;
2218                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2219                 I915_WRITE(fdi_tx_reg, temp);
2220                 POSTING_READ(fdi_tx_reg);
2221
2222                 temp = I915_READ(fdi_rx_reg);
2223                 if (HAS_PCH_CPT(dev)) {
2224                         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2225                         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2226                 } else {
2227                         temp &= ~FDI_LINK_TRAIN_NONE;
2228                         temp |= FDI_LINK_TRAIN_PATTERN_1;
2229                 }
2230                 I915_WRITE(fdi_rx_reg, temp);
2231                 POSTING_READ(fdi_rx_reg);
2232
2233                 udelay(100);
2234
2235                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2236                         temp = I915_READ(PCH_LVDS);
2237                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2238                         I915_READ(PCH_LVDS);
2239                         udelay(100);
2240                 }
2241
2242                 /* disable PCH transcoder */
2243                 temp = I915_READ(transconf_reg);
2244                 if ((temp & TRANS_ENABLE) != 0) {
2245                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2246                         I915_READ(transconf_reg);
2247                         n = 0;
2248                         /* wait for PCH transcoder off, transcoder state */
2249                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2250                                 n++;
2251                                 if (n < 60) {
2252                                         udelay(500);
2253                                         continue;
2254                                 } else {
2255                                         DRM_DEBUG_KMS("transcoder %d off "
2256                                                         "delay\n", pipe);
2257                                         break;
2258                                 }
2259                         }
2260                 }
2261
2262                 temp = I915_READ(transconf_reg);
2263                 /* BPC in transcoder is consistent with that in pipeconf */
2264                 temp &= ~PIPE_BPC_MASK;
2265                 temp |= pipe_bpc;
2266                 I915_WRITE(transconf_reg, temp);
2267                 I915_READ(transconf_reg);
2268                 udelay(100);
2269
2270                 if (HAS_PCH_CPT(dev)) {
2271                         /* disable TRANS_DP_CTL */
2272                         int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2273                         int reg;
2274
2275                         reg = I915_READ(trans_dp_ctl);
2276                         reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2277                         I915_WRITE(trans_dp_ctl, reg);
2278                         POSTING_READ(trans_dp_ctl);
2279
2280                         /* disable DPLL_SEL */
2281                         temp = I915_READ(PCH_DPLL_SEL);
2282                         if (trans_dpll_sel == 0)
2283                                 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2284                         else
2285                                 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2286                         I915_WRITE(PCH_DPLL_SEL, temp);
2287                         I915_READ(PCH_DPLL_SEL);
2288
2289                 }
2290
2291                 /* disable PCH DPLL */
2292                 temp = I915_READ(pch_dpll_reg);
2293                 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2294                 I915_READ(pch_dpll_reg);
2295
2296                 if (HAS_eDP) {
2297                         ironlake_disable_pll_edp(crtc);
2298                 }
2299
2300                 /* Switch from PCDclk to Rawclk */
2301                 temp = I915_READ(fdi_rx_reg);
2302                 temp &= ~FDI_SEL_PCDCLK;
2303                 I915_WRITE(fdi_rx_reg, temp);
2304                 I915_READ(fdi_rx_reg);
2305
2306                 /* Disable CPU FDI TX PLL */
2307                 temp = I915_READ(fdi_tx_reg);
2308                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2309                 I915_READ(fdi_tx_reg);
2310                 udelay(100);
2311
2312                 temp = I915_READ(fdi_rx_reg);
2313                 temp &= ~FDI_RX_PLL_ENABLE;
2314                 I915_WRITE(fdi_rx_reg, temp);
2315                 I915_READ(fdi_rx_reg);
2316
2317                 /* Wait for the clocks to turn off. */
2318                 udelay(100);
2319                 break;
2320         }
2321 }
2322
2323 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2324 {
2325         struct intel_overlay *overlay;
2326         int ret;
2327
2328         if (!enable && intel_crtc->overlay) {
2329                 overlay = intel_crtc->overlay;
2330                 mutex_lock(&overlay->dev->struct_mutex);
2331                 for (;;) {
2332                         ret = intel_overlay_switch_off(overlay);
2333                         if (ret == 0)
2334                                 break;
2335
2336                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
2337                         if (ret != 0) {
2338                                 /* overlay doesn't react anymore. Usually
2339                                  * results in a black screen and an unkillable
2340                                  * X server. */
2341                                 BUG();
2342                                 overlay->hw_wedged = HW_WEDGED;
2343                                 break;
2344                         }
2345                 }
2346                 mutex_unlock(&overlay->dev->struct_mutex);
2347         }
2348         /* Let userspace switch the overlay on again. In most cases userspace
2349          * has to recompute where to put it anyway. */
2350
2351         return;
2352 }
2353
2354 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2355 {
2356         struct drm_device *dev = crtc->dev;
2357         struct drm_i915_private *dev_priv = dev->dev_private;
2358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2359         int pipe = intel_crtc->pipe;
2360         int plane = intel_crtc->plane;
2361         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2362         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2363         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2364         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2365         u32 temp;
2366
2367         /* XXX: When our outputs are all unaware of DPMS modes other than off
2368          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2369          */
2370         switch (mode) {
2371         case DRM_MODE_DPMS_ON:
2372         case DRM_MODE_DPMS_STANDBY:
2373         case DRM_MODE_DPMS_SUSPEND:
2374                 intel_update_watermarks(dev);
2375
2376                 /* Enable the DPLL */
2377                 temp = I915_READ(dpll_reg);
2378                 if ((temp & DPLL_VCO_ENABLE) == 0) {
2379                         I915_WRITE(dpll_reg, temp);
2380                         I915_READ(dpll_reg);
2381                         /* Wait for the clocks to stabilize. */
2382                         udelay(150);
2383                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2384                         I915_READ(dpll_reg);
2385                         /* Wait for the clocks to stabilize. */
2386                         udelay(150);
2387                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2388                         I915_READ(dpll_reg);
2389                         /* Wait for the clocks to stabilize. */
2390                         udelay(150);
2391                 }
2392
2393                 /* Enable the pipe */
2394                 temp = I915_READ(pipeconf_reg);
2395                 if ((temp & PIPEACONF_ENABLE) == 0)
2396                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2397
2398                 /* Enable the plane */
2399                 temp = I915_READ(dspcntr_reg);
2400                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2401                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2402                         /* Flush the plane changes */
2403                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2404                 }
2405
2406                 intel_crtc_load_lut(crtc);
2407
2408                 if ((IS_I965G(dev) || plane == 0))
2409                         intel_update_fbc(crtc, &crtc->mode);
2410
2411                 /* Give the overlay scaler a chance to enable if it's on this pipe */
2412                 intel_crtc_dpms_overlay(intel_crtc, true);
2413         break;
2414         case DRM_MODE_DPMS_OFF:
2415                 intel_update_watermarks(dev);
2416
2417                 /* Give the overlay scaler a chance to disable if it's on this pipe */
2418                 intel_crtc_dpms_overlay(intel_crtc, false);
2419                 drm_vblank_off(dev, pipe);
2420
2421                 if (dev_priv->cfb_plane == plane &&
2422                     dev_priv->display.disable_fbc)
2423                         dev_priv->display.disable_fbc(dev);
2424
2425                 /* Disable the VGA plane that we never use */
2426                 i915_disable_vga(dev);
2427
2428                 /* Disable display plane */
2429                 temp = I915_READ(dspcntr_reg);
2430                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2431                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2432                         /* Flush the plane changes */
2433                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2434                         I915_READ(dspbase_reg);
2435                 }
2436
2437                 if (!IS_I9XX(dev)) {
2438                         /* Wait for vblank for the disable to take effect */
2439                         intel_wait_for_vblank(dev);
2440                 }
2441
2442                 /* Don't disable pipe A or pipe A PLLs if needed */
2443                 if (pipeconf_reg == PIPEACONF &&
2444                     (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2445                         goto skip_pipe_off;
2446
2447                 /* Next, disable display pipes */
2448                 temp = I915_READ(pipeconf_reg);
2449                 if ((temp & PIPEACONF_ENABLE) != 0) {
2450                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2451                         I915_READ(pipeconf_reg);
2452                 }
2453
2454                 /* Wait for vblank for the disable to take effect. */
2455                 intel_wait_for_vblank(dev);
2456
2457                 temp = I915_READ(dpll_reg);
2458                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2459                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2460                         I915_READ(dpll_reg);
2461                 }
2462         skip_pipe_off:
2463                 /* Wait for the clocks to turn off. */
2464                 udelay(150);
2465                 break;
2466         }
2467 }
2468
2469 /**
2470  * Sets the power management mode of the pipe and plane.
2471  */
2472 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2473 {
2474         struct drm_device *dev = crtc->dev;
2475         struct drm_i915_private *dev_priv = dev->dev_private;
2476         struct drm_i915_master_private *master_priv;
2477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2478         int pipe = intel_crtc->pipe;
2479         bool enabled;
2480
2481         dev_priv->display.dpms(crtc, mode);
2482
2483         intel_crtc->dpms_mode = mode;
2484
2485         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2486         intel_crtc_update_cursor(crtc);
2487
2488         if (!dev->primary->master)
2489                 return;
2490
2491         master_priv = dev->primary->master->driver_priv;
2492         if (!master_priv->sarea_priv)
2493                 return;
2494
2495         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2496
2497         switch (pipe) {
2498         case 0:
2499                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2500                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2501                 break;
2502         case 1:
2503                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2504                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2505                 break;
2506         default:
2507                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2508                 break;
2509         }
2510 }
2511
2512 static void intel_crtc_prepare (struct drm_crtc *crtc)
2513 {
2514         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2515         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2516 }
2517
2518 static void intel_crtc_commit (struct drm_crtc *crtc)
2519 {
2520         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2521         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2522 }
2523
2524 void intel_encoder_prepare (struct drm_encoder *encoder)
2525 {
2526         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2527         /* lvds has its own version of prepare see intel_lvds_prepare */
2528         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2529 }
2530
2531 void intel_encoder_commit (struct drm_encoder *encoder)
2532 {
2533         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2534         /* lvds has its own version of commit see intel_lvds_commit */
2535         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2536 }
2537
2538 void intel_encoder_destroy(struct drm_encoder *encoder)
2539 {
2540         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2541
2542         if (intel_encoder->ddc_bus)
2543                 intel_i2c_destroy(intel_encoder->ddc_bus);
2544
2545         if (intel_encoder->i2c_bus)
2546                 intel_i2c_destroy(intel_encoder->i2c_bus);
2547
2548         drm_encoder_cleanup(encoder);
2549         kfree(intel_encoder);
2550 }
2551
2552 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2553                                   struct drm_display_mode *mode,
2554                                   struct drm_display_mode *adjusted_mode)
2555 {
2556         struct drm_device *dev = crtc->dev;
2557         if (HAS_PCH_SPLIT(dev)) {
2558                 /* FDI link clock is fixed at 2.7G */
2559                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2560                         return false;
2561         }
2562         return true;
2563 }
2564
2565 static int i945_get_display_clock_speed(struct drm_device *dev)
2566 {
2567         return 400000;
2568 }
2569
2570 static int i915_get_display_clock_speed(struct drm_device *dev)
2571 {
2572         return 333000;
2573 }
2574
2575 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2576 {
2577         return 200000;
2578 }
2579
2580 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2581 {
2582         u16 gcfgc = 0;
2583
2584         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2585
2586         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2587                 return 133000;
2588         else {
2589                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2590                 case GC_DISPLAY_CLOCK_333_MHZ:
2591                         return 333000;
2592                 default:
2593                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2594                         return 190000;
2595                 }
2596         }
2597 }
2598
2599 static int i865_get_display_clock_speed(struct drm_device *dev)
2600 {
2601         return 266000;
2602 }
2603
2604 static int i855_get_display_clock_speed(struct drm_device *dev)
2605 {
2606         u16 hpllcc = 0;
2607         /* Assume that the hardware is in the high speed state.  This
2608          * should be the default.
2609          */
2610         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2611         case GC_CLOCK_133_200:
2612         case GC_CLOCK_100_200:
2613                 return 200000;
2614         case GC_CLOCK_166_250:
2615                 return 250000;
2616         case GC_CLOCK_100_133:
2617                 return 133000;
2618         }
2619
2620         /* Shouldn't happen */
2621         return 0;
2622 }
2623
2624 static int i830_get_display_clock_speed(struct drm_device *dev)
2625 {
2626         return 133000;
2627 }
2628
2629 /**
2630  * Return the pipe currently connected to the panel fitter,
2631  * or -1 if the panel fitter is not present or not in use
2632  */
2633 int intel_panel_fitter_pipe (struct drm_device *dev)
2634 {
2635         struct drm_i915_private *dev_priv = dev->dev_private;
2636         u32  pfit_control;
2637
2638         /* i830 doesn't have a panel fitter */
2639         if (IS_I830(dev))
2640                 return -1;
2641
2642         pfit_control = I915_READ(PFIT_CONTROL);
2643
2644         /* See if the panel fitter is in use */
2645         if ((pfit_control & PFIT_ENABLE) == 0)
2646                 return -1;
2647
2648         /* 965 can place panel fitter on either pipe */
2649         if (IS_I965G(dev))
2650                 return (pfit_control >> 29) & 0x3;
2651
2652         /* older chips can only use pipe 1 */
2653         return 1;
2654 }
2655
2656 struct fdi_m_n {
2657         u32        tu;
2658         u32        gmch_m;
2659         u32        gmch_n;
2660         u32        link_m;
2661         u32        link_n;
2662 };
2663
2664 static void
2665 fdi_reduce_ratio(u32 *num, u32 *den)
2666 {
2667         while (*num > 0xffffff || *den > 0xffffff) {
2668                 *num >>= 1;
2669                 *den >>= 1;
2670         }
2671 }
2672
2673 #define DATA_N 0x800000
2674 #define LINK_N 0x80000
2675
2676 static void
2677 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2678                      int link_clock, struct fdi_m_n *m_n)
2679 {
2680         u64 temp;
2681
2682         m_n->tu = 64; /* default size */
2683
2684         temp = (u64) DATA_N * pixel_clock;
2685         temp = div_u64(temp, link_clock);
2686         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2687         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2688         m_n->gmch_n = DATA_N;
2689         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2690
2691         temp = (u64) LINK_N * pixel_clock;
2692         m_n->link_m = div_u64(temp, link_clock);
2693         m_n->link_n = LINK_N;
2694         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2695 }
2696
2697
2698 struct intel_watermark_params {
2699         unsigned long fifo_size;
2700         unsigned long max_wm;
2701         unsigned long default_wm;
2702         unsigned long guard_size;
2703         unsigned long cacheline_size;
2704 };
2705
2706 /* Pineview has different values for various configs */
2707 static struct intel_watermark_params pineview_display_wm = {
2708         PINEVIEW_DISPLAY_FIFO,
2709         PINEVIEW_MAX_WM,
2710         PINEVIEW_DFT_WM,
2711         PINEVIEW_GUARD_WM,
2712         PINEVIEW_FIFO_LINE_SIZE
2713 };
2714 static struct intel_watermark_params pineview_display_hplloff_wm = {
2715         PINEVIEW_DISPLAY_FIFO,
2716         PINEVIEW_MAX_WM,
2717         PINEVIEW_DFT_HPLLOFF_WM,
2718         PINEVIEW_GUARD_WM,
2719         PINEVIEW_FIFO_LINE_SIZE
2720 };
2721 static struct intel_watermark_params pineview_cursor_wm = {
2722         PINEVIEW_CURSOR_FIFO,
2723         PINEVIEW_CURSOR_MAX_WM,
2724         PINEVIEW_CURSOR_DFT_WM,
2725         PINEVIEW_CURSOR_GUARD_WM,
2726         PINEVIEW_FIFO_LINE_SIZE,
2727 };
2728 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2729         PINEVIEW_CURSOR_FIFO,
2730         PINEVIEW_CURSOR_MAX_WM,
2731         PINEVIEW_CURSOR_DFT_WM,
2732         PINEVIEW_CURSOR_GUARD_WM,
2733         PINEVIEW_FIFO_LINE_SIZE
2734 };
2735 static struct intel_watermark_params g4x_wm_info = {
2736         G4X_FIFO_SIZE,
2737         G4X_MAX_WM,
2738         G4X_MAX_WM,
2739         2,
2740         G4X_FIFO_LINE_SIZE,
2741 };
2742 static struct intel_watermark_params g4x_cursor_wm_info = {
2743         I965_CURSOR_FIFO,
2744         I965_CURSOR_MAX_WM,
2745         I965_CURSOR_DFT_WM,
2746         2,
2747         G4X_FIFO_LINE_SIZE,
2748 };
2749 static struct intel_watermark_params i965_cursor_wm_info = {
2750         I965_CURSOR_FIFO,
2751         I965_CURSOR_MAX_WM,
2752         I965_CURSOR_DFT_WM,
2753         2,
2754         I915_FIFO_LINE_SIZE,
2755 };
2756 static struct intel_watermark_params i945_wm_info = {
2757         I945_FIFO_SIZE,
2758         I915_MAX_WM,
2759         1,
2760         2,
2761         I915_FIFO_LINE_SIZE
2762 };
2763 static struct intel_watermark_params i915_wm_info = {
2764         I915_FIFO_SIZE,
2765         I915_MAX_WM,
2766         1,
2767         2,
2768         I915_FIFO_LINE_SIZE
2769 };
2770 static struct intel_watermark_params i855_wm_info = {
2771         I855GM_FIFO_SIZE,
2772         I915_MAX_WM,
2773         1,
2774         2,
2775         I830_FIFO_LINE_SIZE
2776 };
2777 static struct intel_watermark_params i830_wm_info = {
2778         I830_FIFO_SIZE,
2779         I915_MAX_WM,
2780         1,
2781         2,
2782         I830_FIFO_LINE_SIZE
2783 };
2784
2785 static struct intel_watermark_params ironlake_display_wm_info = {
2786         ILK_DISPLAY_FIFO,
2787         ILK_DISPLAY_MAXWM,
2788         ILK_DISPLAY_DFTWM,
2789         2,
2790         ILK_FIFO_LINE_SIZE
2791 };
2792
2793 static struct intel_watermark_params ironlake_cursor_wm_info = {
2794         ILK_CURSOR_FIFO,
2795         ILK_CURSOR_MAXWM,
2796         ILK_CURSOR_DFTWM,
2797         2,
2798         ILK_FIFO_LINE_SIZE
2799 };
2800
2801 static struct intel_watermark_params ironlake_display_srwm_info = {
2802         ILK_DISPLAY_SR_FIFO,
2803         ILK_DISPLAY_MAX_SRWM,
2804         ILK_DISPLAY_DFT_SRWM,
2805         2,
2806         ILK_FIFO_LINE_SIZE
2807 };
2808
2809 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2810         ILK_CURSOR_SR_FIFO,
2811         ILK_CURSOR_MAX_SRWM,
2812         ILK_CURSOR_DFT_SRWM,
2813         2,
2814         ILK_FIFO_LINE_SIZE
2815 };
2816
2817 /**
2818  * intel_calculate_wm - calculate watermark level
2819  * @clock_in_khz: pixel clock
2820  * @wm: chip FIFO params
2821  * @pixel_size: display pixel size
2822  * @latency_ns: memory latency for the platform
2823  *
2824  * Calculate the watermark level (the level at which the display plane will
2825  * start fetching from memory again).  Each chip has a different display
2826  * FIFO size and allocation, so the caller needs to figure that out and pass
2827  * in the correct intel_watermark_params structure.
2828  *
2829  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2830  * on the pixel size.  When it reaches the watermark level, it'll start
2831  * fetching FIFO line sized based chunks from memory until the FIFO fills
2832  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2833  * will occur, and a display engine hang could result.
2834  */
2835 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2836                                         struct intel_watermark_params *wm,
2837                                         int pixel_size,
2838                                         unsigned long latency_ns)
2839 {
2840         long entries_required, wm_size;
2841
2842         /*
2843          * Note: we need to make sure we don't overflow for various clock &
2844          * latency values.
2845          * clocks go from a few thousand to several hundred thousand.
2846          * latency is usually a few thousand
2847          */
2848         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2849                 1000;
2850         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2851
2852         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2853
2854         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2855
2856         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2857
2858         /* Don't promote wm_size to unsigned... */
2859         if (wm_size > (long)wm->max_wm)
2860                 wm_size = wm->max_wm;
2861         if (wm_size <= 0) {
2862                 wm_size = wm->default_wm;
2863                 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2864                           " entries required = %ld, available = %lu.\n",
2865                           entries_required + wm->guard_size,
2866                           wm->fifo_size);
2867         }
2868
2869         return wm_size;
2870 }
2871
2872 struct cxsr_latency {
2873         int is_desktop;
2874         int is_ddr3;
2875         unsigned long fsb_freq;
2876         unsigned long mem_freq;
2877         unsigned long display_sr;
2878         unsigned long display_hpll_disable;
2879         unsigned long cursor_sr;
2880         unsigned long cursor_hpll_disable;
2881 };
2882
2883 static const struct cxsr_latency cxsr_latency_table[] = {
2884         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2885         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2886         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2887         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2888         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2889
2890         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2891         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2892         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2893         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2894         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2895
2896         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2897         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2898         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2899         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2900         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2901
2902         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2903         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2904         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2905         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2906         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2907
2908         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2909         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2910         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2911         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2912         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2913
2914         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2915         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2916         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2917         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2918         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2919 };
2920
2921 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2922                                                          int is_ddr3,
2923                                                          int fsb,
2924                                                          int mem)
2925 {
2926         const struct cxsr_latency *latency;
2927         int i;
2928
2929         if (fsb == 0 || mem == 0)
2930                 return NULL;
2931
2932         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2933                 latency = &cxsr_latency_table[i];
2934                 if (is_desktop == latency->is_desktop &&
2935                     is_ddr3 == latency->is_ddr3 &&
2936                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2937                         return latency;
2938         }
2939
2940         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2941
2942         return NULL;
2943 }
2944
2945 static void pineview_disable_cxsr(struct drm_device *dev)
2946 {
2947         struct drm_i915_private *dev_priv = dev->dev_private;
2948
2949         /* deactivate cxsr */
2950         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2951 }
2952
2953 /*
2954  * Latency for FIFO fetches is dependent on several factors:
2955  *   - memory configuration (speed, channels)
2956  *   - chipset
2957  *   - current MCH state
2958  * It can be fairly high in some situations, so here we assume a fairly
2959  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2960  * set this value too high, the FIFO will fetch frequently to stay full)
2961  * and power consumption (set it too low to save power and we might see
2962  * FIFO underruns and display "flicker").
2963  *
2964  * A value of 5us seems to be a good balance; safe for very low end
2965  * platforms but not overly aggressive on lower latency configs.
2966  */
2967 static const int latency_ns = 5000;
2968
2969 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2970 {
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972         uint32_t dsparb = I915_READ(DSPARB);
2973         int size;
2974
2975         size = dsparb & 0x7f;
2976         if (plane)
2977                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2978
2979         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2980                         plane ? "B" : "A", size);
2981
2982         return size;
2983 }
2984
2985 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2986 {
2987         struct drm_i915_private *dev_priv = dev->dev_private;
2988         uint32_t dsparb = I915_READ(DSPARB);
2989         int size;
2990
2991         size = dsparb & 0x1ff;
2992         if (plane)
2993                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2994         size >>= 1; /* Convert to cachelines */
2995
2996         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2997                         plane ? "B" : "A", size);
2998
2999         return size;
3000 }
3001
3002 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3003 {
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         uint32_t dsparb = I915_READ(DSPARB);
3006         int size;
3007
3008         size = dsparb & 0x7f;
3009         size >>= 2; /* Convert to cachelines */
3010
3011         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3012                         plane ? "B" : "A",
3013                   size);
3014
3015         return size;
3016 }
3017
3018 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3019 {
3020         struct drm_i915_private *dev_priv = dev->dev_private;
3021         uint32_t dsparb = I915_READ(DSPARB);
3022         int size;
3023
3024         size = dsparb & 0x7f;
3025         size >>= 1; /* Convert to cachelines */
3026
3027         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3028                         plane ? "B" : "A", size);
3029
3030         return size;
3031 }
3032
3033 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3034                           int planeb_clock, int sr_hdisplay, int unused,
3035                           int pixel_size)
3036 {
3037         struct drm_i915_private *dev_priv = dev->dev_private;
3038         const struct cxsr_latency *latency;
3039         u32 reg;
3040         unsigned long wm;
3041         int sr_clock;
3042
3043         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3044                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3045         if (!latency) {
3046                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3047                 pineview_disable_cxsr(dev);
3048                 return;
3049         }
3050
3051         if (!planea_clock || !planeb_clock) {
3052                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3053
3054                 /* Display SR */
3055                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3056                                         pixel_size, latency->display_sr);
3057                 reg = I915_READ(DSPFW1);
3058                 reg &= ~DSPFW_SR_MASK;
3059                 reg |= wm << DSPFW_SR_SHIFT;
3060                 I915_WRITE(DSPFW1, reg);
3061                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3062
3063                 /* cursor SR */
3064                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3065                                         pixel_size, latency->cursor_sr);
3066                 reg = I915_READ(DSPFW3);
3067                 reg &= ~DSPFW_CURSOR_SR_MASK;
3068                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3069                 I915_WRITE(DSPFW3, reg);
3070
3071                 /* Display HPLL off SR */
3072                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3073                                         pixel_size, latency->display_hpll_disable);
3074                 reg = I915_READ(DSPFW3);
3075                 reg &= ~DSPFW_HPLL_SR_MASK;
3076                 reg |= wm & DSPFW_HPLL_SR_MASK;
3077                 I915_WRITE(DSPFW3, reg);
3078
3079                 /* cursor HPLL off SR */
3080                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3081                                         pixel_size, latency->cursor_hpll_disable);
3082                 reg = I915_READ(DSPFW3);
3083                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3084                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3085                 I915_WRITE(DSPFW3, reg);
3086                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3087
3088                 /* activate cxsr */
3089                 I915_WRITE(DSPFW3,
3090                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3091                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3092         } else {
3093                 pineview_disable_cxsr(dev);
3094                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3095         }
3096 }
3097
3098 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3099                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3100                           int pixel_size)
3101 {
3102         struct drm_i915_private *dev_priv = dev->dev_private;
3103         int total_size, cacheline_size;
3104         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3105         struct intel_watermark_params planea_params, planeb_params;
3106         unsigned long line_time_us;
3107         int sr_clock, sr_entries = 0, entries_required;
3108
3109         /* Create copies of the base settings for each pipe */
3110         planea_params = planeb_params = g4x_wm_info;
3111
3112         /* Grab a couple of global values before we overwrite them */
3113         total_size = planea_params.fifo_size;
3114         cacheline_size = planea_params.cacheline_size;
3115
3116         /*
3117          * Note: we need to make sure we don't overflow for various clock &
3118          * latency values.
3119          * clocks go from a few thousand to several hundred thousand.
3120          * latency is usually a few thousand
3121          */
3122         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3123                 1000;
3124         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3125         planea_wm = entries_required + planea_params.guard_size;
3126
3127         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3128                 1000;
3129         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3130         planeb_wm = entries_required + planeb_params.guard_size;
3131
3132         cursora_wm = cursorb_wm = 16;
3133         cursor_sr = 32;
3134
3135         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3136
3137         /* Calc sr entries for one plane configs */
3138         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3139                 /* self-refresh has much higher latency */
3140                 static const int sr_latency_ns = 12000;
3141
3142                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3143                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3144
3145                 /* Use ns/us then divide to preserve precision */
3146                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3147                               pixel_size * sr_hdisplay;
3148                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3149
3150                 entries_required = (((sr_latency_ns / line_time_us) +
3151                                      1000) / 1000) * pixel_size * 64;
3152                 entries_required = DIV_ROUND_UP(entries_required,
3153                                            g4x_cursor_wm_info.cacheline_size);
3154                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3155
3156                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3157                         cursor_sr = g4x_cursor_wm_info.max_wm;
3158                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3159                               "cursor %d\n", sr_entries, cursor_sr);
3160
3161                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3162         } else {
3163                 /* Turn off self refresh if both pipes are enabled */
3164                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3165                                         & ~FW_BLC_SELF_EN);
3166         }
3167
3168         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3169                   planea_wm, planeb_wm, sr_entries);
3170
3171         planea_wm &= 0x3f;
3172         planeb_wm &= 0x3f;
3173
3174         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3175                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3176                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3177         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3178                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3179         /* HPLL off in SR has some issues on G4x... disable it */
3180         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3181                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3182 }
3183
3184 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3185                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3186                            int pixel_size)
3187 {
3188         struct drm_i915_private *dev_priv = dev->dev_private;
3189         unsigned long line_time_us;
3190         int sr_clock, sr_entries, srwm = 1;
3191         int cursor_sr = 16;
3192
3193         /* Calc sr entries for one plane configs */
3194         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3195                 /* self-refresh has much higher latency */
3196                 static const int sr_latency_ns = 12000;
3197
3198                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3199                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3200
3201                 /* Use ns/us then divide to preserve precision */
3202                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3203                               pixel_size * sr_hdisplay;
3204                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3205                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3206                 srwm = I965_FIFO_SIZE - sr_entries;
3207                 if (srwm < 0)
3208                         srwm = 1;
3209                 srwm &= 0x1ff;
3210
3211                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3212                              pixel_size * 64;
3213                 sr_entries = DIV_ROUND_UP(sr_entries,
3214                                           i965_cursor_wm_info.cacheline_size);
3215                 cursor_sr = i965_cursor_wm_info.fifo_size -
3216                             (sr_entries + i965_cursor_wm_info.guard_size);
3217
3218                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3219                         cursor_sr = i965_cursor_wm_info.max_wm;
3220
3221                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3222                               "cursor %d\n", srwm, cursor_sr);
3223
3224                 if (IS_I965GM(dev))
3225                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3226         } else {
3227                 /* Turn off self refresh if both pipes are enabled */
3228                 if (IS_I965GM(dev))
3229                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3230                                    & ~FW_BLC_SELF_EN);
3231         }
3232
3233         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3234                       srwm);
3235
3236         /* 965 has limitations... */
3237         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3238                    (8 << 0));
3239         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3240         /* update cursor SR watermark */
3241         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3242 }
3243
3244 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3245                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3246                            int pixel_size)
3247 {
3248         struct drm_i915_private *dev_priv = dev->dev_private;
3249         uint32_t fwater_lo;
3250         uint32_t fwater_hi;
3251         int total_size, cacheline_size, cwm, srwm = 1;
3252         int planea_wm, planeb_wm;
3253         struct intel_watermark_params planea_params, planeb_params;
3254         unsigned long line_time_us;
3255         int sr_clock, sr_entries = 0;
3256
3257         /* Create copies of the base settings for each pipe */
3258         if (IS_I965GM(dev) || IS_I945GM(dev))
3259                 planea_params = planeb_params = i945_wm_info;
3260         else if (IS_I9XX(dev))
3261                 planea_params = planeb_params = i915_wm_info;
3262         else
3263                 planea_params = planeb_params = i855_wm_info;
3264
3265         /* Grab a couple of global values before we overwrite them */
3266         total_size = planea_params.fifo_size;
3267         cacheline_size = planea_params.cacheline_size;
3268
3269         /* Update per-plane FIFO sizes */
3270         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3271         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3272
3273         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3274                                        pixel_size, latency_ns);
3275         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3276                                        pixel_size, latency_ns);
3277         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3278
3279         /*
3280          * Overlay gets an aggressive default since video jitter is bad.
3281          */
3282         cwm = 2;
3283
3284         /* Calc sr entries for one plane configs */
3285         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3286             (!planea_clock || !planeb_clock)) {
3287                 /* self-refresh has much higher latency */
3288                 static const int sr_latency_ns = 6000;
3289
3290                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3291                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3292
3293                 /* Use ns/us then divide to preserve precision */
3294                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3295                               pixel_size * sr_hdisplay;
3296                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3297                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3298                 srwm = total_size - sr_entries;
3299                 if (srwm < 0)
3300                         srwm = 1;
3301
3302                 if (IS_I945G(dev) || IS_I945GM(dev))
3303                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3304                 else if (IS_I915GM(dev)) {
3305                         /* 915M has a smaller SRWM field */
3306                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3307                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3308                 }
3309         } else {
3310                 /* Turn off self refresh if both pipes are enabled */
3311                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3312                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3313                                    & ~FW_BLC_SELF_EN);
3314                 } else if (IS_I915GM(dev)) {
3315                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3316                 }
3317         }
3318
3319         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3320                   planea_wm, planeb_wm, cwm, srwm);
3321
3322         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3323         fwater_hi = (cwm & 0x1f);
3324
3325         /* Set request length to 8 cachelines per fetch */
3326         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3327         fwater_hi = fwater_hi | (1 << 8);
3328
3329         I915_WRITE(FW_BLC, fwater_lo);
3330         I915_WRITE(FW_BLC2, fwater_hi);
3331 }
3332
3333 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3334                            int unused2, int unused3, int pixel_size)
3335 {
3336         struct drm_i915_private *dev_priv = dev->dev_private;
3337         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3338         int planea_wm;
3339
3340         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3341
3342         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3343                                        pixel_size, latency_ns);
3344         fwater_lo |= (3<<8) | planea_wm;
3345
3346         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3347
3348         I915_WRITE(FW_BLC, fwater_lo);
3349 }
3350
3351 #define ILK_LP0_PLANE_LATENCY           700
3352 #define ILK_LP0_CURSOR_LATENCY          1300
3353
3354 static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
3355                        int planeb_clock, int sr_hdisplay, int sr_htotal,
3356                        int pixel_size)
3357 {
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3360         int sr_wm, cursor_wm;
3361         unsigned long line_time_us;
3362         int sr_clock, entries_required;
3363         u32 reg_value;
3364         int line_count;
3365         int planea_htotal = 0, planeb_htotal = 0;
3366         struct drm_crtc *crtc;
3367         struct intel_crtc *intel_crtc;
3368
3369         /* Need htotal for all active display plane */
3370         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3371                 intel_crtc = to_intel_crtc(crtc);
3372                 if (crtc->enabled) {
3373                         if (intel_crtc->plane == 0)
3374                                 planea_htotal = crtc->mode.htotal;
3375                         else
3376                                 planeb_htotal = crtc->mode.htotal;
3377                 }
3378         }
3379
3380         /* Calculate and update the watermark for plane A */
3381         if (planea_clock) {
3382                 entries_required = ((planea_clock / 1000) * pixel_size *
3383                                      ILK_LP0_PLANE_LATENCY) / 1000;
3384                 entries_required = DIV_ROUND_UP(entries_required,
3385                                                 ironlake_display_wm_info.cacheline_size);
3386                 planea_wm = entries_required +
3387                             ironlake_display_wm_info.guard_size;
3388
3389                 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3390                         planea_wm = ironlake_display_wm_info.max_wm;
3391
3392                 /* Use the large buffer method to calculate cursor watermark */
3393                 line_time_us = (planea_htotal * 1000) / planea_clock;
3394
3395                 /* Use ns/us then divide to preserve precision */
3396                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3397
3398                 /* calculate the cursor watermark for cursor A */
3399                 entries_required = line_count * 64 * pixel_size;
3400                 entries_required = DIV_ROUND_UP(entries_required,
3401                                                 ironlake_cursor_wm_info.cacheline_size);
3402                 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3403                 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3404                         cursora_wm = ironlake_cursor_wm_info.max_wm;
3405
3406                 reg_value = I915_READ(WM0_PIPEA_ILK);
3407                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3408                 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3409                              (cursora_wm & WM0_PIPE_CURSOR_MASK);
3410                 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3411                 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3412                                 "cursor: %d\n", planea_wm, cursora_wm);
3413         }
3414         /* Calculate and update the watermark for plane B */
3415         if (planeb_clock) {
3416                 entries_required = ((planeb_clock / 1000) * pixel_size *
3417                                      ILK_LP0_PLANE_LATENCY) / 1000;
3418                 entries_required = DIV_ROUND_UP(entries_required,
3419                                                 ironlake_display_wm_info.cacheline_size);
3420                 planeb_wm = entries_required +
3421                             ironlake_display_wm_info.guard_size;
3422
3423                 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3424                         planeb_wm = ironlake_display_wm_info.max_wm;
3425
3426                 /* Use the large buffer method to calculate cursor watermark */
3427                 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3428
3429                 /* Use ns/us then divide to preserve precision */
3430                 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3431
3432                 /* calculate the cursor watermark for cursor B */
3433                 entries_required = line_count * 64 * pixel_size;
3434                 entries_required = DIV_ROUND_UP(entries_required,
3435                                                 ironlake_cursor_wm_info.cacheline_size);
3436                 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3437                 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3438                         cursorb_wm = ironlake_cursor_wm_info.max_wm;
3439
3440                 reg_value = I915_READ(WM0_PIPEB_ILK);
3441                 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3442                 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3443                              (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3444                 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3445                 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3446                                 "cursor: %d\n", planeb_wm, cursorb_wm);
3447         }
3448
3449         /*
3450          * Calculate and update the self-refresh watermark only when one
3451          * display plane is used.
3452          */
3453         if (!planea_clock || !planeb_clock) {
3454
3455                 /* Read the self-refresh latency. The unit is 0.5us */
3456                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3457
3458                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3459                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3460
3461                 /* Use ns/us then divide to preserve precision */
3462                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3463                                / 1000;
3464
3465                 /* calculate the self-refresh watermark for display plane */
3466                 entries_required = line_count * sr_hdisplay * pixel_size;
3467                 entries_required = DIV_ROUND_UP(entries_required,
3468                                                 ironlake_display_srwm_info.cacheline_size);
3469                 sr_wm = entries_required +
3470                         ironlake_display_srwm_info.guard_size;
3471
3472                 /* calculate the self-refresh watermark for display cursor */
3473                 entries_required = line_count * pixel_size * 64;
3474                 entries_required = DIV_ROUND_UP(entries_required,
3475                                                 ironlake_cursor_srwm_info.cacheline_size);
3476                 cursor_wm = entries_required +
3477                             ironlake_cursor_srwm_info.guard_size;
3478
3479                 /* configure watermark and enable self-refresh */
3480                 reg_value = I915_READ(WM1_LP_ILK);
3481                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3482                                WM1_LP_CURSOR_MASK);
3483                 reg_value |= WM1_LP_SR_EN |
3484                              (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3485                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3486
3487                 I915_WRITE(WM1_LP_ILK, reg_value);
3488                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3489                                 "cursor %d\n", sr_wm, cursor_wm);
3490
3491         } else {
3492                 /* Turn off self refresh if both pipes are enabled */
3493                 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3494         }
3495 }
3496 /**
3497  * intel_update_watermarks - update FIFO watermark values based on current modes
3498  *
3499  * Calculate watermark values for the various WM regs based on current mode
3500  * and plane configuration.
3501  *
3502  * There are several cases to deal with here:
3503  *   - normal (i.e. non-self-refresh)
3504  *   - self-refresh (SR) mode
3505  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3506  *   - lines are small relative to FIFO size (buffer can hold more than 2
3507  *     lines), so need to account for TLB latency
3508  *
3509  *   The normal calculation is:
3510  *     watermark = dotclock * bytes per pixel * latency
3511  *   where latency is platform & configuration dependent (we assume pessimal
3512  *   values here).
3513  *
3514  *   The SR calculation is:
3515  *     watermark = (trunc(latency/line time)+1) * surface width *
3516  *       bytes per pixel
3517  *   where
3518  *     line time = htotal / dotclock
3519  *     surface width = hdisplay for normal plane and 64 for cursor
3520  *   and latency is assumed to be high, as above.
3521  *
3522  * The final value programmed to the register should always be rounded up,
3523  * and include an extra 2 entries to account for clock crossings.
3524  *
3525  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3526  * to set the non-SR watermarks to 8.
3527   */
3528 static void intel_update_watermarks(struct drm_device *dev)
3529 {
3530         struct drm_i915_private *dev_priv = dev->dev_private;
3531         struct drm_crtc *crtc;
3532         struct intel_crtc *intel_crtc;
3533         int sr_hdisplay = 0;
3534         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3535         int enabled = 0, pixel_size = 0;
3536         int sr_htotal = 0;
3537
3538         if (!dev_priv->display.update_wm)
3539                 return;
3540
3541         /* Get the clock config from both planes */
3542         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3543                 intel_crtc = to_intel_crtc(crtc);
3544                 if (crtc->enabled) {
3545                         enabled++;
3546                         if (intel_crtc->plane == 0) {
3547                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3548                                           intel_crtc->pipe, crtc->mode.clock);
3549                                 planea_clock = crtc->mode.clock;
3550                         } else {
3551                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3552                                           intel_crtc->pipe, crtc->mode.clock);
3553                                 planeb_clock = crtc->mode.clock;
3554                         }
3555                         sr_hdisplay = crtc->mode.hdisplay;
3556                         sr_clock = crtc->mode.clock;
3557                         sr_htotal = crtc->mode.htotal;
3558                         if (crtc->fb)
3559                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3560                         else
3561                                 pixel_size = 4; /* by default */
3562                 }
3563         }
3564
3565         if (enabled <= 0)
3566                 return;
3567
3568         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3569                                     sr_hdisplay, sr_htotal, pixel_size);
3570 }
3571
3572 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3573                                struct drm_display_mode *mode,
3574                                struct drm_display_mode *adjusted_mode,
3575                                int x, int y,
3576                                struct drm_framebuffer *old_fb)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3581         int pipe = intel_crtc->pipe;
3582         int plane = intel_crtc->plane;
3583         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3584         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3585         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3586         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3587         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3588         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3589         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3590         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3591         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3592         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3593         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3594         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3595         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3596         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3597         int refclk, num_connectors = 0;
3598         intel_clock_t clock, reduced_clock;
3599         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3600         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3601         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3602         bool is_edp = false;
3603         struct drm_mode_config *mode_config = &dev->mode_config;
3604         struct drm_encoder *encoder;
3605         struct intel_encoder *intel_encoder = NULL;
3606         const intel_limit_t *limit;
3607         int ret;
3608         struct fdi_m_n m_n = {0};
3609         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3610         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3611         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3612         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3613         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3614         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3615         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3616         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3617         int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3618         int lvds_reg = LVDS;
3619         u32 temp;
3620         int sdvo_pixel_multiply;
3621         int target_clock;
3622
3623         drm_vblank_pre_modeset(dev, pipe);
3624
3625         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3626
3627                 if (!encoder || encoder->crtc != crtc)
3628                         continue;
3629
3630                 intel_encoder = enc_to_intel_encoder(encoder);
3631
3632                 switch (intel_encoder->type) {
3633                 case INTEL_OUTPUT_LVDS:
3634                         is_lvds = true;
3635                         break;
3636                 case INTEL_OUTPUT_SDVO:
3637                 case INTEL_OUTPUT_HDMI:
3638                         is_sdvo = true;
3639                         if (intel_encoder->needs_tv_clock)
3640                                 is_tv = true;
3641                         break;
3642                 case INTEL_OUTPUT_DVO:
3643                         is_dvo = true;
3644                         break;
3645                 case INTEL_OUTPUT_TVOUT:
3646                         is_tv = true;
3647                         break;
3648                 case INTEL_OUTPUT_ANALOG:
3649                         is_crt = true;
3650                         break;
3651                 case INTEL_OUTPUT_DISPLAYPORT:
3652                         is_dp = true;
3653                         break;
3654                 case INTEL_OUTPUT_EDP:
3655                         is_edp = true;
3656                         break;
3657                 }
3658
3659                 num_connectors++;
3660         }
3661
3662         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3663                 refclk = dev_priv->lvds_ssc_freq * 1000;
3664                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3665                                         refclk / 1000);
3666         } else if (IS_I9XX(dev)) {
3667                 refclk = 96000;
3668                 if (HAS_PCH_SPLIT(dev))
3669                         refclk = 120000; /* 120Mhz refclk */
3670         } else {
3671                 refclk = 48000;
3672         }
3673
3674
3675         /*
3676          * Returns a set of divisors for the desired target clock with the given
3677          * refclk, or FALSE.  The returned values represent the clock equation:
3678          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3679          */
3680         limit = intel_limit(crtc);
3681         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3682         if (!ok) {
3683                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3684                 drm_vblank_post_modeset(dev, pipe);
3685                 return -EINVAL;
3686         }
3687
3688         /* Ensure that the cursor is valid for the new mode before changing... */
3689         intel_crtc_update_cursor(crtc);
3690
3691         if (is_lvds && dev_priv->lvds_downclock_avail) {
3692                 has_reduced_clock = limit->find_pll(limit, crtc,
3693                                                             dev_priv->lvds_downclock,
3694                                                             refclk,
3695                                                             &reduced_clock);
3696                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3697                         /*
3698                          * If the different P is found, it means that we can't
3699                          * switch the display clock by using the FP0/FP1.
3700                          * In such case we will disable the LVDS downclock
3701                          * feature.
3702                          */
3703                         DRM_DEBUG_KMS("Different P is found for "
3704                                                 "LVDS clock/downclock\n");
3705                         has_reduced_clock = 0;
3706                 }
3707         }
3708         /* SDVO TV has fixed PLL values depend on its clock range,
3709            this mirrors vbios setting. */
3710         if (is_sdvo && is_tv) {
3711                 if (adjusted_mode->clock >= 100000
3712                                 && adjusted_mode->clock < 140500) {
3713                         clock.p1 = 2;
3714                         clock.p2 = 10;
3715                         clock.n = 3;
3716                         clock.m1 = 16;
3717                         clock.m2 = 8;
3718                 } else if (adjusted_mode->clock >= 140500
3719                                 && adjusted_mode->clock <= 200000) {
3720                         clock.p1 = 1;
3721                         clock.p2 = 10;
3722                         clock.n = 6;
3723                         clock.m1 = 12;
3724                         clock.m2 = 8;
3725                 }
3726         }
3727
3728         /* FDI link */
3729         if (HAS_PCH_SPLIT(dev)) {
3730                 int lane = 0, link_bw, bpp;
3731                 /* eDP doesn't require FDI link, so just set DP M/N
3732                    according to current link config */
3733                 if (is_edp) {
3734                         target_clock = mode->clock;
3735                         intel_edp_link_config(intel_encoder,
3736                                         &lane, &link_bw);
3737                 } else {
3738                         /* DP over FDI requires target mode clock
3739                            instead of link clock */
3740                         if (is_dp)
3741                                 target_clock = mode->clock;
3742                         else
3743                                 target_clock = adjusted_mode->clock;
3744                         link_bw = 270000;
3745                 }
3746
3747                 /* determine panel color depth */
3748                 temp = I915_READ(pipeconf_reg);
3749                 temp &= ~PIPE_BPC_MASK;
3750                 if (is_lvds) {
3751                         int lvds_reg = I915_READ(PCH_LVDS);
3752                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3753                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3754                                 temp |= PIPE_8BPC;
3755                         else
3756                                 temp |= PIPE_6BPC;
3757                 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3758                         switch (dev_priv->edp_bpp/3) {
3759                         case 8:
3760                                 temp |= PIPE_8BPC;
3761                                 break;
3762                         case 10:
3763                                 temp |= PIPE_10BPC;
3764                                 break;
3765                         case 6:
3766                                 temp |= PIPE_6BPC;
3767                                 break;
3768                         case 12:
3769                                 temp |= PIPE_12BPC;
3770                                 break;
3771                         }
3772                 } else
3773                         temp |= PIPE_8BPC;
3774                 I915_WRITE(pipeconf_reg, temp);
3775                 I915_READ(pipeconf_reg);
3776
3777                 switch (temp & PIPE_BPC_MASK) {
3778                 case PIPE_8BPC:
3779                         bpp = 24;
3780                         break;
3781                 case PIPE_10BPC:
3782                         bpp = 30;
3783                         break;
3784                 case PIPE_6BPC:
3785                         bpp = 18;
3786                         break;
3787                 case PIPE_12BPC:
3788                         bpp = 36;
3789                         break;
3790                 default:
3791                         DRM_ERROR("unknown pipe bpc value\n");
3792                         bpp = 24;
3793                 }
3794
3795                 if (!lane) {
3796                         /*
3797                          * Account for spread spectrum to avoid
3798                          * oversubscribing the link. Max center spread
3799                          * is 2.5%; use 5% for safety's sake.
3800                          */
3801                         u32 bps = target_clock * bpp * 21 / 20;
3802                         lane = bps / (link_bw * 8) + 1;
3803                 }
3804
3805                 intel_crtc->fdi_lanes = lane;
3806
3807                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3808         }
3809
3810         /* Ironlake: try to setup display ref clock before DPLL
3811          * enabling. This is only under driver's control after
3812          * PCH B stepping, previous chipset stepping should be
3813          * ignoring this setting.
3814          */
3815         if (HAS_PCH_SPLIT(dev)) {
3816                 temp = I915_READ(PCH_DREF_CONTROL);
3817                 /* Always enable nonspread source */
3818                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3819                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3820                 I915_WRITE(PCH_DREF_CONTROL, temp);
3821                 POSTING_READ(PCH_DREF_CONTROL);
3822
3823                 temp &= ~DREF_SSC_SOURCE_MASK;
3824                 temp |= DREF_SSC_SOURCE_ENABLE;
3825                 I915_WRITE(PCH_DREF_CONTROL, temp);
3826                 POSTING_READ(PCH_DREF_CONTROL);
3827
3828                 udelay(200);
3829
3830                 if (is_edp) {
3831                         if (dev_priv->lvds_use_ssc) {
3832                                 temp |= DREF_SSC1_ENABLE;
3833                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3834                                 POSTING_READ(PCH_DREF_CONTROL);
3835
3836                                 udelay(200);
3837
3838                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3839                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3840                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3841                                 POSTING_READ(PCH_DREF_CONTROL);
3842                         } else {
3843                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3844                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3845                                 POSTING_READ(PCH_DREF_CONTROL);
3846                         }
3847                 }
3848         }
3849
3850         if (IS_PINEVIEW(dev)) {
3851                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3852                 if (has_reduced_clock)
3853                         fp2 = (1 << reduced_clock.n) << 16 |
3854                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3855         } else {
3856                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3857                 if (has_reduced_clock)
3858                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3859                                 reduced_clock.m2;
3860         }
3861
3862         if (!HAS_PCH_SPLIT(dev))
3863                 dpll = DPLL_VGA_MODE_DIS;
3864
3865         if (IS_I9XX(dev)) {
3866                 if (is_lvds)
3867                         dpll |= DPLLB_MODE_LVDS;
3868                 else
3869                         dpll |= DPLLB_MODE_DAC_SERIAL;
3870                 if (is_sdvo) {
3871                         dpll |= DPLL_DVO_HIGH_SPEED;
3872                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3873                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3874                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3875                         else if (HAS_PCH_SPLIT(dev))
3876                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3877                 }
3878                 if (is_dp)
3879                         dpll |= DPLL_DVO_HIGH_SPEED;
3880
3881                 /* compute bitmask from p1 value */
3882                 if (IS_PINEVIEW(dev))
3883                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3884                 else {
3885                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3886                         /* also FPA1 */
3887                         if (HAS_PCH_SPLIT(dev))
3888                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3889                         if (IS_G4X(dev) && has_reduced_clock)
3890                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3891                 }
3892                 switch (clock.p2) {
3893                 case 5:
3894                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3895                         break;
3896                 case 7:
3897                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3898                         break;
3899                 case 10:
3900                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3901                         break;
3902                 case 14:
3903                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3904                         break;
3905                 }
3906                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3907                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3908         } else {
3909                 if (is_lvds) {
3910                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3911                 } else {
3912                         if (clock.p1 == 2)
3913                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3914                         else
3915                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3916                         if (clock.p2 == 4)
3917                                 dpll |= PLL_P2_DIVIDE_BY_4;
3918                 }
3919         }
3920
3921         if (is_sdvo && is_tv)
3922                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3923         else if (is_tv)
3924                 /* XXX: just matching BIOS for now */
3925                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3926                 dpll |= 3;
3927         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3928                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3929         else
3930                 dpll |= PLL_REF_INPUT_DREFCLK;
3931
3932         /* setup pipeconf */
3933         pipeconf = I915_READ(pipeconf_reg);
3934
3935         /* Set up the display plane register */
3936         dspcntr = DISPPLANE_GAMMA_ENABLE;
3937
3938         /* Ironlake's plane is forced to pipe, bit 24 is to
3939            enable color space conversion */
3940         if (!HAS_PCH_SPLIT(dev)) {
3941                 if (pipe == 0)
3942                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3943                 else
3944                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3945         }
3946
3947         if (pipe == 0 && !IS_I965G(dev)) {
3948                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3949                  * core speed.
3950                  *
3951                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3952                  * pipe == 0 check?
3953                  */
3954                 if (mode->clock >
3955                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3956                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3957                 else
3958                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3959         }
3960
3961         dspcntr |= DISPLAY_PLANE_ENABLE;
3962         pipeconf |= PIPEACONF_ENABLE;
3963         dpll |= DPLL_VCO_ENABLE;
3964
3965
3966         /* Disable the panel fitter if it was on our pipe */
3967         if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3968                 I915_WRITE(PFIT_CONTROL, 0);
3969
3970         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3971         drm_mode_debug_printmodeline(mode);
3972
3973         /* assign to Ironlake registers */
3974         if (HAS_PCH_SPLIT(dev)) {
3975                 fp_reg = pch_fp_reg;
3976                 dpll_reg = pch_dpll_reg;
3977         }
3978
3979         if (is_edp) {
3980                 ironlake_disable_pll_edp(crtc);
3981         } else if ((dpll & DPLL_VCO_ENABLE)) {
3982                 I915_WRITE(fp_reg, fp);
3983                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3984                 I915_READ(dpll_reg);
3985                 udelay(150);
3986         }
3987
3988         /* enable transcoder DPLL */
3989         if (HAS_PCH_CPT(dev)) {
3990                 temp = I915_READ(PCH_DPLL_SEL);
3991                 if (trans_dpll_sel == 0)
3992                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3993                 else
3994                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3995                 I915_WRITE(PCH_DPLL_SEL, temp);
3996                 I915_READ(PCH_DPLL_SEL);
3997                 udelay(150);
3998         }
3999
4000         if (HAS_PCH_SPLIT(dev)) {
4001                 pipeconf &= ~PIPE_ENABLE_DITHER;
4002                 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
4003         }
4004
4005         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4006          * This is an exception to the general rule that mode_set doesn't turn
4007          * things on.
4008          */
4009         if (is_lvds) {
4010                 u32 lvds;
4011
4012                 if (HAS_PCH_SPLIT(dev))
4013                         lvds_reg = PCH_LVDS;
4014
4015                 lvds = I915_READ(lvds_reg);
4016                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4017                 if (pipe == 1) {
4018                         if (HAS_PCH_CPT(dev))
4019                                 lvds |= PORT_TRANS_B_SEL_CPT;
4020                         else
4021                                 lvds |= LVDS_PIPEB_SELECT;
4022                 } else {
4023                         if (HAS_PCH_CPT(dev))
4024                                 lvds &= ~PORT_TRANS_SEL_MASK;
4025                         else
4026                                 lvds &= ~LVDS_PIPEB_SELECT;
4027                 }
4028                 /* set the corresponsding LVDS_BORDER bit */
4029                 lvds |= dev_priv->lvds_border_bits;
4030                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4031                  * set the DPLLs for dual-channel mode or not.
4032                  */
4033                 if (clock.p2 == 7)
4034                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4035                 else
4036                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4037
4038                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4039                  * appropriately here, but we need to look more thoroughly into how
4040                  * panels behave in the two modes.
4041                  */
4042                 /* set the dithering flag */
4043                 if (IS_I965G(dev)) {
4044                         if (dev_priv->lvds_dither) {
4045                                 if (HAS_PCH_SPLIT(dev)) {
4046                                         pipeconf |= PIPE_ENABLE_DITHER;
4047                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
4048                                 } else
4049                                         lvds |= LVDS_ENABLE_DITHER;
4050                         } else {
4051                                 if (!HAS_PCH_SPLIT(dev)) {
4052                                         lvds &= ~LVDS_ENABLE_DITHER;
4053                                 }
4054                         }
4055                 }
4056                 I915_WRITE(lvds_reg, lvds);
4057                 I915_READ(lvds_reg);
4058         }
4059         if (is_dp)
4060                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4061         else if (HAS_PCH_SPLIT(dev)) {
4062                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4063                 if (pipe == 0) {
4064                         I915_WRITE(TRANSA_DATA_M1, 0);
4065                         I915_WRITE(TRANSA_DATA_N1, 0);
4066                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
4067                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
4068                 } else {
4069                         I915_WRITE(TRANSB_DATA_M1, 0);
4070                         I915_WRITE(TRANSB_DATA_N1, 0);
4071                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
4072                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4073                 }
4074         }
4075
4076         if (!is_edp) {
4077                 I915_WRITE(fp_reg, fp);
4078                 I915_WRITE(dpll_reg, dpll);
4079                 I915_READ(dpll_reg);
4080                 /* Wait for the clocks to stabilize. */
4081                 udelay(150);
4082
4083                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4084                         if (is_sdvo) {
4085                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4086                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4087                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4088                         } else
4089                                 I915_WRITE(dpll_md_reg, 0);
4090                 } else {
4091                         /* write it again -- the BIOS does, after all */
4092                         I915_WRITE(dpll_reg, dpll);
4093                 }
4094                 I915_READ(dpll_reg);
4095                 /* Wait for the clocks to stabilize. */
4096                 udelay(150);
4097         }
4098
4099         if (is_lvds && has_reduced_clock && i915_powersave) {
4100                 I915_WRITE(fp_reg + 4, fp2);
4101                 intel_crtc->lowfreq_avail = true;
4102                 if (HAS_PIPE_CXSR(dev)) {
4103                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4104                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4105                 }
4106         } else {
4107                 I915_WRITE(fp_reg + 4, fp);
4108                 intel_crtc->lowfreq_avail = false;
4109                 if (HAS_PIPE_CXSR(dev)) {
4110                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4111                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4112                 }
4113         }
4114
4115         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4116                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4117                 /* the chip adds 2 halflines automatically */
4118                 adjusted_mode->crtc_vdisplay -= 1;
4119                 adjusted_mode->crtc_vtotal -= 1;
4120                 adjusted_mode->crtc_vblank_start -= 1;
4121                 adjusted_mode->crtc_vblank_end -= 1;
4122                 adjusted_mode->crtc_vsync_end -= 1;
4123                 adjusted_mode->crtc_vsync_start -= 1;
4124         } else
4125                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4126
4127         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4128                    ((adjusted_mode->crtc_htotal - 1) << 16));
4129         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4130                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4131         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4132                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4133         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4134                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4135         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4136                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4137         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4138                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4139         /* pipesrc and dspsize control the size that is scaled from, which should
4140          * always be the user's requested size.
4141          */
4142         if (!HAS_PCH_SPLIT(dev)) {
4143                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4144                                 (mode->hdisplay - 1));
4145                 I915_WRITE(dsppos_reg, 0);
4146         }
4147         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4148
4149         if (HAS_PCH_SPLIT(dev)) {
4150                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4151                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4152                 I915_WRITE(link_m1_reg, m_n.link_m);
4153                 I915_WRITE(link_n1_reg, m_n.link_n);
4154
4155                 if (is_edp) {
4156                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4157                 } else {
4158                         /* enable FDI RX PLL too */
4159                         temp = I915_READ(fdi_rx_reg);
4160                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4161                         I915_READ(fdi_rx_reg);
4162                         udelay(200);
4163
4164                         /* enable FDI TX PLL too */
4165                         temp = I915_READ(fdi_tx_reg);
4166                         I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4167                         I915_READ(fdi_tx_reg);
4168
4169                         /* enable FDI RX PCDCLK */
4170                         temp = I915_READ(fdi_rx_reg);
4171                         I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4172                         I915_READ(fdi_rx_reg);
4173                         udelay(200);
4174                 }
4175         }
4176
4177         I915_WRITE(pipeconf_reg, pipeconf);
4178         I915_READ(pipeconf_reg);
4179
4180         intel_wait_for_vblank(dev);
4181
4182         if (IS_IRONLAKE(dev)) {
4183                 /* enable address swizzle for tiling buffer */
4184                 temp = I915_READ(DISP_ARB_CTL);
4185                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4186         }
4187
4188         I915_WRITE(dspcntr_reg, dspcntr);
4189
4190         /* Flush the plane changes */
4191         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4192
4193         if ((IS_I965G(dev) || plane == 0))
4194                 intel_update_fbc(crtc, &crtc->mode);
4195
4196         intel_update_watermarks(dev);
4197
4198         drm_vblank_post_modeset(dev, pipe);
4199
4200         return ret;
4201 }
4202
4203 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4204 void intel_crtc_load_lut(struct drm_crtc *crtc)
4205 {
4206         struct drm_device *dev = crtc->dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4210         int i;
4211
4212         /* The clocks have to be on to load the palette. */
4213         if (!crtc->enabled)
4214                 return;
4215
4216         /* use legacy palette for Ironlake */
4217         if (HAS_PCH_SPLIT(dev))
4218                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4219                                                    LGC_PALETTE_B;
4220
4221         for (i = 0; i < 256; i++) {
4222                 I915_WRITE(palreg + 4 * i,
4223                            (intel_crtc->lut_r[i] << 16) |
4224                            (intel_crtc->lut_g[i] << 8) |
4225                            intel_crtc->lut_b[i]);
4226         }
4227 }
4228
4229 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4230 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4231 {
4232         struct drm_device *dev = crtc->dev;
4233         struct drm_i915_private *dev_priv = dev->dev_private;
4234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4235         int pipe = intel_crtc->pipe;
4236         int x = intel_crtc->cursor_x;
4237         int y = intel_crtc->cursor_y;
4238         uint32_t base, pos;
4239         bool visible;
4240
4241         pos = 0;
4242
4243         if (intel_crtc->cursor_on && crtc->fb) {
4244                 base = intel_crtc->cursor_addr;
4245                 if (x > (int) crtc->fb->width)
4246                         base = 0;
4247
4248                 if (y > (int) crtc->fb->height)
4249                         base = 0;
4250         } else
4251                 base = 0;
4252
4253         if (x < 0) {
4254                 if (x + intel_crtc->cursor_width < 0)
4255                         base = 0;
4256
4257                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4258                 x = -x;
4259         }
4260         pos |= x << CURSOR_X_SHIFT;
4261
4262         if (y < 0) {
4263                 if (y + intel_crtc->cursor_height < 0)
4264                         base = 0;
4265
4266                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4267                 y = -y;
4268         }
4269         pos |= y << CURSOR_Y_SHIFT;
4270
4271         visible = base != 0;
4272         if (!visible && !intel_crtc->cursor_visble)
4273                 return;
4274
4275         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4276         if (intel_crtc->cursor_visble != visible) {
4277                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4278                 if (base) {
4279                         /* Hooray for CUR*CNTR differences */
4280                         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4281                                 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4282                                 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4283                                 cntl |= pipe << 28; /* Connect to correct pipe */
4284                         } else {
4285                                 cntl &= ~(CURSOR_FORMAT_MASK);
4286                                 cntl |= CURSOR_ENABLE;
4287                                 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4288                         }
4289                 } else {
4290                         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4291                                 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4292                                 cntl |= CURSOR_MODE_DISABLE;
4293                         } else {
4294                                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4295                         }
4296                 }
4297                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4298
4299                 intel_crtc->cursor_visble = visible;
4300         }
4301         /* and commit changes on next vblank */
4302         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4303
4304         if (visible)
4305                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4306 }
4307
4308 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4309                                  struct drm_file *file_priv,
4310                                  uint32_t handle,
4311                                  uint32_t width, uint32_t height)
4312 {
4313         struct drm_device *dev = crtc->dev;
4314         struct drm_i915_private *dev_priv = dev->dev_private;
4315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4316         struct drm_gem_object *bo;
4317         struct drm_i915_gem_object *obj_priv;
4318         uint32_t addr;
4319         int ret;
4320
4321         DRM_DEBUG_KMS("\n");
4322
4323         /* if we want to turn off the cursor ignore width and height */
4324         if (!handle) {
4325                 DRM_DEBUG_KMS("cursor off\n");
4326                 addr = 0;
4327                 bo = NULL;
4328                 mutex_lock(&dev->struct_mutex);
4329                 goto finish;
4330         }
4331
4332         /* Currently we only support 64x64 cursors */
4333         if (width != 64 || height != 64) {
4334                 DRM_ERROR("we currently only support 64x64 cursors\n");
4335                 return -EINVAL;
4336         }
4337
4338         bo = drm_gem_object_lookup(dev, file_priv, handle);
4339         if (!bo)
4340                 return -ENOENT;
4341
4342         obj_priv = to_intel_bo(bo);
4343
4344         if (bo->size < width * height * 4) {
4345                 DRM_ERROR("buffer is to small\n");
4346                 ret = -ENOMEM;
4347                 goto fail;
4348         }
4349
4350         /* we only need to pin inside GTT if cursor is non-phy */
4351         mutex_lock(&dev->struct_mutex);
4352         if (!dev_priv->info->cursor_needs_physical) {
4353                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4354                 if (ret) {
4355                         DRM_ERROR("failed to pin cursor bo\n");
4356                         goto fail_locked;
4357                 }
4358
4359                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4360                 if (ret) {
4361                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4362                         goto fail_unpin;
4363                 }
4364
4365                 addr = obj_priv->gtt_offset;
4366         } else {
4367                 ret = i915_gem_attach_phys_object(dev, bo,
4368                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4369                 if (ret) {
4370                         DRM_ERROR("failed to attach phys object\n");
4371                         goto fail_locked;
4372                 }
4373                 addr = obj_priv->phys_obj->handle->busaddr;
4374         }
4375
4376         if (!IS_I9XX(dev))
4377                 I915_WRITE(CURSIZE, (height << 12) | width);
4378
4379  finish:
4380         if (intel_crtc->cursor_bo) {
4381                 if (dev_priv->info->cursor_needs_physical) {
4382                         if (intel_crtc->cursor_bo != bo)
4383                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4384                 } else
4385                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4386                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4387         }
4388
4389         mutex_unlock(&dev->struct_mutex);
4390
4391         intel_crtc->cursor_addr = addr;
4392         intel_crtc->cursor_bo = bo;
4393         intel_crtc->cursor_width = width;
4394         intel_crtc->cursor_height = height;
4395
4396         intel_crtc_update_cursor(crtc);
4397
4398         return 0;
4399 fail_unpin:
4400         i915_gem_object_unpin(bo);
4401 fail_locked:
4402         mutex_unlock(&dev->struct_mutex);
4403 fail:
4404         drm_gem_object_unreference_unlocked(bo);
4405         return ret;
4406 }
4407
4408 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4409 {
4410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411
4412         intel_crtc->cursor_x = x;
4413         intel_crtc->cursor_y = y;
4414
4415         intel_crtc_update_cursor(crtc);
4416
4417         return 0;
4418 }
4419
4420 /** Sets the color ramps on behalf of RandR */
4421 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4422                                  u16 blue, int regno)
4423 {
4424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4425
4426         intel_crtc->lut_r[regno] = red >> 8;
4427         intel_crtc->lut_g[regno] = green >> 8;
4428         intel_crtc->lut_b[regno] = blue >> 8;
4429 }
4430
4431 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4432                              u16 *blue, int regno)
4433 {
4434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435
4436         *red = intel_crtc->lut_r[regno] << 8;
4437         *green = intel_crtc->lut_g[regno] << 8;
4438         *blue = intel_crtc->lut_b[regno] << 8;
4439 }
4440
4441 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4442                                  u16 *blue, uint32_t size)
4443 {
4444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4445         int i;
4446
4447         if (size != 256)
4448                 return;
4449
4450         for (i = 0; i < 256; i++) {
4451                 intel_crtc->lut_r[i] = red[i] >> 8;
4452                 intel_crtc->lut_g[i] = green[i] >> 8;
4453                 intel_crtc->lut_b[i] = blue[i] >> 8;
4454         }
4455
4456         intel_crtc_load_lut(crtc);
4457 }
4458
4459 /**
4460  * Get a pipe with a simple mode set on it for doing load-based monitor
4461  * detection.
4462  *
4463  * It will be up to the load-detect code to adjust the pipe as appropriate for
4464  * its requirements.  The pipe will be connected to no other encoders.
4465  *
4466  * Currently this code will only succeed if there is a pipe with no encoders
4467  * configured for it.  In the future, it could choose to temporarily disable
4468  * some outputs to free up a pipe for its use.
4469  *
4470  * \return crtc, or NULL if no pipes are available.
4471  */
4472
4473 /* VESA 640x480x72Hz mode to set on the pipe */
4474 static struct drm_display_mode load_detect_mode = {
4475         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4476                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4477 };
4478
4479 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4480                                             struct drm_connector *connector,
4481                                             struct drm_display_mode *mode,
4482                                             int *dpms_mode)
4483 {
4484         struct intel_crtc *intel_crtc;
4485         struct drm_crtc *possible_crtc;
4486         struct drm_crtc *supported_crtc =NULL;
4487         struct drm_encoder *encoder = &intel_encoder->enc;
4488         struct drm_crtc *crtc = NULL;
4489         struct drm_device *dev = encoder->dev;
4490         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4491         struct drm_crtc_helper_funcs *crtc_funcs;
4492         int i = -1;
4493
4494         /*
4495          * Algorithm gets a little messy:
4496          *   - if the connector already has an assigned crtc, use it (but make
4497          *     sure it's on first)
4498          *   - try to find the first unused crtc that can drive this connector,
4499          *     and use that if we find one
4500          *   - if there are no unused crtcs available, try to use the first
4501          *     one we found that supports the connector
4502          */
4503
4504         /* See if we already have a CRTC for this connector */
4505         if (encoder->crtc) {
4506                 crtc = encoder->crtc;
4507                 /* Make sure the crtc and connector are running */
4508                 intel_crtc = to_intel_crtc(crtc);
4509                 *dpms_mode = intel_crtc->dpms_mode;
4510                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4511                         crtc_funcs = crtc->helper_private;
4512                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4513                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4514                 }
4515                 return crtc;
4516         }
4517
4518         /* Find an unused one (if possible) */
4519         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4520                 i++;
4521                 if (!(encoder->possible_crtcs & (1 << i)))
4522                         continue;
4523                 if (!possible_crtc->enabled) {
4524                         crtc = possible_crtc;
4525                         break;
4526                 }
4527                 if (!supported_crtc)
4528                         supported_crtc = possible_crtc;
4529         }
4530
4531         /*
4532          * If we didn't find an unused CRTC, don't use any.
4533          */
4534         if (!crtc) {
4535                 return NULL;
4536         }
4537
4538         encoder->crtc = crtc;
4539         connector->encoder = encoder;
4540         intel_encoder->load_detect_temp = true;
4541
4542         intel_crtc = to_intel_crtc(crtc);
4543         *dpms_mode = intel_crtc->dpms_mode;
4544
4545         if (!crtc->enabled) {
4546                 if (!mode)
4547                         mode = &load_detect_mode;
4548                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4549         } else {
4550                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4551                         crtc_funcs = crtc->helper_private;
4552                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4553                 }
4554
4555                 /* Add this connector to the crtc */
4556                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4557                 encoder_funcs->commit(encoder);
4558         }
4559         /* let the connector get through one full cycle before testing */
4560         intel_wait_for_vblank(dev);
4561
4562         return crtc;
4563 }
4564
4565 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4566                                     struct drm_connector *connector, int dpms_mode)
4567 {
4568         struct drm_encoder *encoder = &intel_encoder->enc;
4569         struct drm_device *dev = encoder->dev;
4570         struct drm_crtc *crtc = encoder->crtc;
4571         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4572         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4573
4574         if (intel_encoder->load_detect_temp) {
4575                 encoder->crtc = NULL;
4576                 connector->encoder = NULL;
4577                 intel_encoder->load_detect_temp = false;
4578                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4579                 drm_helper_disable_unused_functions(dev);
4580         }
4581
4582         /* Switch crtc and encoder back off if necessary */
4583         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4584                 if (encoder->crtc == crtc)
4585                         encoder_funcs->dpms(encoder, dpms_mode);
4586                 crtc_funcs->dpms(crtc, dpms_mode);
4587         }
4588 }
4589
4590 /* Returns the clock of the currently programmed mode of the given pipe. */
4591 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4592 {
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595         int pipe = intel_crtc->pipe;
4596         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4597         u32 fp;
4598         intel_clock_t clock;
4599
4600         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4601                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4602         else
4603                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4604
4605         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4606         if (IS_PINEVIEW(dev)) {
4607                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4608                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4609         } else {
4610                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4611                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4612         }
4613
4614         if (IS_I9XX(dev)) {
4615                 if (IS_PINEVIEW(dev))
4616                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4617                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4618                 else
4619                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4620                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4621
4622                 switch (dpll & DPLL_MODE_MASK) {
4623                 case DPLLB_MODE_DAC_SERIAL:
4624                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4625                                 5 : 10;
4626                         break;
4627                 case DPLLB_MODE_LVDS:
4628                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4629                                 7 : 14;
4630                         break;
4631                 default:
4632                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4633                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4634                         return 0;
4635                 }
4636
4637                 /* XXX: Handle the 100Mhz refclk */
4638                 intel_clock(dev, 96000, &clock);
4639         } else {
4640                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4641
4642                 if (is_lvds) {
4643                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4644                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4645                         clock.p2 = 14;
4646
4647                         if ((dpll & PLL_REF_INPUT_MASK) ==
4648                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4649                                 /* XXX: might not be 66MHz */
4650                                 intel_clock(dev, 66000, &clock);
4651                         } else
4652                                 intel_clock(dev, 48000, &clock);
4653                 } else {
4654                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4655                                 clock.p1 = 2;
4656                         else {
4657                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4658                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4659                         }
4660                         if (dpll & PLL_P2_DIVIDE_BY_4)
4661                                 clock.p2 = 4;
4662                         else
4663                                 clock.p2 = 2;
4664
4665                         intel_clock(dev, 48000, &clock);
4666                 }
4667         }
4668
4669         /* XXX: It would be nice to validate the clocks, but we can't reuse
4670          * i830PllIsValid() because it relies on the xf86_config connector
4671          * configuration being accurate, which it isn't necessarily.
4672          */
4673
4674         return clock.dot;
4675 }
4676
4677 /** Returns the currently programmed mode of the given pipe. */
4678 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4679                                              struct drm_crtc *crtc)
4680 {
4681         struct drm_i915_private *dev_priv = dev->dev_private;
4682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4683         int pipe = intel_crtc->pipe;
4684         struct drm_display_mode *mode;
4685         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4686         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4687         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4688         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4689
4690         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4691         if (!mode)
4692                 return NULL;
4693
4694         mode->clock = intel_crtc_clock_get(dev, crtc);
4695         mode->hdisplay = (htot & 0xffff) + 1;
4696         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4697         mode->hsync_start = (hsync & 0xffff) + 1;
4698         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4699         mode->vdisplay = (vtot & 0xffff) + 1;
4700         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4701         mode->vsync_start = (vsync & 0xffff) + 1;
4702         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4703
4704         drm_mode_set_name(mode);
4705         drm_mode_set_crtcinfo(mode, 0);
4706
4707         return mode;
4708 }
4709
4710 #define GPU_IDLE_TIMEOUT 500 /* ms */
4711
4712 /* When this timer fires, we've been idle for awhile */
4713 static void intel_gpu_idle_timer(unsigned long arg)
4714 {
4715         struct drm_device *dev = (struct drm_device *)arg;
4716         drm_i915_private_t *dev_priv = dev->dev_private;
4717
4718         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4719
4720         dev_priv->busy = false;
4721
4722         queue_work(dev_priv->wq, &dev_priv->idle_work);
4723 }
4724
4725 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4726
4727 static void intel_crtc_idle_timer(unsigned long arg)
4728 {
4729         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4730         struct drm_crtc *crtc = &intel_crtc->base;
4731         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4732
4733         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4734
4735         intel_crtc->busy = false;
4736
4737         queue_work(dev_priv->wq, &dev_priv->idle_work);
4738 }
4739
4740 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4741 {
4742         struct drm_device *dev = crtc->dev;
4743         drm_i915_private_t *dev_priv = dev->dev_private;
4744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4745         int pipe = intel_crtc->pipe;
4746         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4747         int dpll = I915_READ(dpll_reg);
4748
4749         if (HAS_PCH_SPLIT(dev))
4750                 return;
4751
4752         if (!dev_priv->lvds_downclock_avail)
4753                 return;
4754
4755         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4756                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4757
4758                 /* Unlock panel regs */
4759                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4760                            PANEL_UNLOCK_REGS);
4761
4762                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4763                 I915_WRITE(dpll_reg, dpll);
4764                 dpll = I915_READ(dpll_reg);
4765                 intel_wait_for_vblank(dev);
4766                 dpll = I915_READ(dpll_reg);
4767                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4768                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4769
4770                 /* ...and lock them again */
4771                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4772         }
4773
4774         /* Schedule downclock */
4775         if (schedule)
4776                 mod_timer(&intel_crtc->idle_timer, jiffies +
4777                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4778 }
4779
4780 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4781 {
4782         struct drm_device *dev = crtc->dev;
4783         drm_i915_private_t *dev_priv = dev->dev_private;
4784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4785         int pipe = intel_crtc->pipe;
4786         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4787         int dpll = I915_READ(dpll_reg);
4788
4789         if (HAS_PCH_SPLIT(dev))
4790                 return;
4791
4792         if (!dev_priv->lvds_downclock_avail)
4793                 return;
4794
4795         /*
4796          * Since this is called by a timer, we should never get here in
4797          * the manual case.
4798          */
4799         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4800                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4801
4802                 /* Unlock panel regs */
4803                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4804                            PANEL_UNLOCK_REGS);
4805
4806                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4807                 I915_WRITE(dpll_reg, dpll);
4808                 dpll = I915_READ(dpll_reg);
4809                 intel_wait_for_vblank(dev);
4810                 dpll = I915_READ(dpll_reg);
4811                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4812                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4813
4814                 /* ...and lock them again */
4815                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4816         }
4817
4818 }
4819
4820 /**
4821  * intel_idle_update - adjust clocks for idleness
4822  * @work: work struct
4823  *
4824  * Either the GPU or display (or both) went idle.  Check the busy status
4825  * here and adjust the CRTC and GPU clocks as necessary.
4826  */
4827 static void intel_idle_update(struct work_struct *work)
4828 {
4829         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4830                                                     idle_work);
4831         struct drm_device *dev = dev_priv->dev;
4832         struct drm_crtc *crtc;
4833         struct intel_crtc *intel_crtc;
4834         int enabled = 0;
4835
4836         if (!i915_powersave)
4837                 return;
4838
4839         mutex_lock(&dev->struct_mutex);
4840
4841         i915_update_gfx_val(dev_priv);
4842
4843         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4844                 /* Skip inactive CRTCs */
4845                 if (!crtc->fb)
4846                         continue;
4847
4848                 enabled++;
4849                 intel_crtc = to_intel_crtc(crtc);
4850                 if (!intel_crtc->busy)
4851                         intel_decrease_pllclock(crtc);
4852         }
4853
4854         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4855                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4856                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4857         }
4858
4859         mutex_unlock(&dev->struct_mutex);
4860 }
4861
4862 /**
4863  * intel_mark_busy - mark the GPU and possibly the display busy
4864  * @dev: drm device
4865  * @obj: object we're operating on
4866  *
4867  * Callers can use this function to indicate that the GPU is busy processing
4868  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4869  * buffer), we'll also mark the display as busy, so we know to increase its
4870  * clock frequency.
4871  */
4872 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4873 {
4874         drm_i915_private_t *dev_priv = dev->dev_private;
4875         struct drm_crtc *crtc = NULL;
4876         struct intel_framebuffer *intel_fb;
4877         struct intel_crtc *intel_crtc;
4878
4879         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4880                 return;
4881
4882         if (!dev_priv->busy) {
4883                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4884                         u32 fw_blc_self;
4885
4886                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4887                         fw_blc_self = I915_READ(FW_BLC_SELF);
4888                         fw_blc_self &= ~FW_BLC_SELF_EN;
4889                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4890                 }
4891                 dev_priv->busy = true;
4892         } else
4893                 mod_timer(&dev_priv->idle_timer, jiffies +
4894                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4895
4896         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4897                 if (!crtc->fb)
4898                         continue;
4899
4900                 intel_crtc = to_intel_crtc(crtc);
4901                 intel_fb = to_intel_framebuffer(crtc->fb);
4902                 if (intel_fb->obj == obj) {
4903                         if (!intel_crtc->busy) {
4904                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4905                                         u32 fw_blc_self;
4906
4907                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4908                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4909                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4910                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4911                                 }
4912                                 /* Non-busy -> busy, upclock */
4913                                 intel_increase_pllclock(crtc, true);
4914                                 intel_crtc->busy = true;
4915                         } else {
4916                                 /* Busy -> busy, put off timer */
4917                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4918                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4919                         }
4920                 }
4921         }
4922 }
4923
4924 static void intel_crtc_destroy(struct drm_crtc *crtc)
4925 {
4926         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4927
4928         drm_crtc_cleanup(crtc);
4929         kfree(intel_crtc);
4930 }
4931
4932 struct intel_unpin_work {
4933         struct work_struct work;
4934         struct drm_device *dev;
4935         struct drm_gem_object *old_fb_obj;
4936         struct drm_gem_object *pending_flip_obj;
4937         struct drm_pending_vblank_event *event;
4938         int pending;
4939 };
4940
4941 static void intel_unpin_work_fn(struct work_struct *__work)
4942 {
4943         struct intel_unpin_work *work =
4944                 container_of(__work, struct intel_unpin_work, work);
4945
4946         mutex_lock(&work->dev->struct_mutex);
4947         i915_gem_object_unpin(work->old_fb_obj);
4948         drm_gem_object_unreference(work->pending_flip_obj);
4949         drm_gem_object_unreference(work->old_fb_obj);
4950         mutex_unlock(&work->dev->struct_mutex);
4951         kfree(work);
4952 }
4953
4954 static void do_intel_finish_page_flip(struct drm_device *dev,
4955                                       struct drm_crtc *crtc)
4956 {
4957         drm_i915_private_t *dev_priv = dev->dev_private;
4958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4959         struct intel_unpin_work *work;
4960         struct drm_i915_gem_object *obj_priv;
4961         struct drm_pending_vblank_event *e;
4962         struct timeval now;
4963         unsigned long flags;
4964
4965         /* Ignore early vblank irqs */
4966         if (intel_crtc == NULL)
4967                 return;
4968
4969         spin_lock_irqsave(&dev->event_lock, flags);
4970         work = intel_crtc->unpin_work;
4971         if (work == NULL || !work->pending) {
4972                 spin_unlock_irqrestore(&dev->event_lock, flags);
4973                 return;
4974         }
4975
4976         intel_crtc->unpin_work = NULL;
4977         drm_vblank_put(dev, intel_crtc->pipe);
4978
4979         if (work->event) {
4980                 e = work->event;
4981                 do_gettimeofday(&now);
4982                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4983                 e->event.tv_sec = now.tv_sec;
4984                 e->event.tv_usec = now.tv_usec;
4985                 list_add_tail(&e->base.link,
4986                               &e->base.file_priv->event_list);
4987                 wake_up_interruptible(&e->base.file_priv->event_wait);
4988         }
4989
4990         spin_unlock_irqrestore(&dev->event_lock, flags);
4991
4992         obj_priv = to_intel_bo(work->pending_flip_obj);
4993
4994         /* Initial scanout buffer will have a 0 pending flip count */
4995         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4996             atomic_dec_and_test(&obj_priv->pending_flip))
4997                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4998         schedule_work(&work->work);
4999
5000         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5001 }
5002
5003 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5004 {
5005         drm_i915_private_t *dev_priv = dev->dev_private;
5006         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5007
5008         do_intel_finish_page_flip(dev, crtc);
5009 }
5010
5011 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5012 {
5013         drm_i915_private_t *dev_priv = dev->dev_private;
5014         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5015
5016         do_intel_finish_page_flip(dev, crtc);
5017 }
5018
5019 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5020 {
5021         drm_i915_private_t *dev_priv = dev->dev_private;
5022         struct intel_crtc *intel_crtc =
5023                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5024         unsigned long flags;
5025
5026         spin_lock_irqsave(&dev->event_lock, flags);
5027         if (intel_crtc->unpin_work) {
5028                 intel_crtc->unpin_work->pending = 1;
5029         } else {
5030                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5031         }
5032         spin_unlock_irqrestore(&dev->event_lock, flags);
5033 }
5034
5035 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5036                                 struct drm_framebuffer *fb,
5037                                 struct drm_pending_vblank_event *event)
5038 {
5039         struct drm_device *dev = crtc->dev;
5040         struct drm_i915_private *dev_priv = dev->dev_private;
5041         struct intel_framebuffer *intel_fb;
5042         struct drm_i915_gem_object *obj_priv;
5043         struct drm_gem_object *obj;
5044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5045         struct intel_unpin_work *work;
5046         unsigned long flags, offset;
5047         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5048         int ret, pipesrc;
5049         u32 flip_mask;
5050
5051         work = kzalloc(sizeof *work, GFP_KERNEL);
5052         if (work == NULL)
5053                 return -ENOMEM;
5054
5055         work->event = event;
5056         work->dev = crtc->dev;
5057         intel_fb = to_intel_framebuffer(crtc->fb);
5058         work->old_fb_obj = intel_fb->obj;
5059         INIT_WORK(&work->work, intel_unpin_work_fn);
5060
5061         /* We borrow the event spin lock for protecting unpin_work */
5062         spin_lock_irqsave(&dev->event_lock, flags);
5063         if (intel_crtc->unpin_work) {
5064                 spin_unlock_irqrestore(&dev->event_lock, flags);
5065                 kfree(work);
5066
5067                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5068                 return -EBUSY;
5069         }
5070         intel_crtc->unpin_work = work;
5071         spin_unlock_irqrestore(&dev->event_lock, flags);
5072
5073         intel_fb = to_intel_framebuffer(fb);
5074         obj = intel_fb->obj;
5075
5076         mutex_lock(&dev->struct_mutex);
5077         ret = intel_pin_and_fence_fb_obj(dev, obj);
5078         if (ret)
5079                 goto cleanup_work;
5080
5081         /* Reference the objects for the scheduled work. */
5082         drm_gem_object_reference(work->old_fb_obj);
5083         drm_gem_object_reference(obj);
5084
5085         crtc->fb = fb;
5086         ret = i915_gem_object_flush_write_domain(obj);
5087         if (ret)
5088                 goto cleanup_objs;
5089
5090         ret = drm_vblank_get(dev, intel_crtc->pipe);
5091         if (ret)
5092                 goto cleanup_objs;
5093
5094         obj_priv = to_intel_bo(obj);
5095         atomic_inc(&obj_priv->pending_flip);
5096         work->pending_flip_obj = obj;
5097
5098         if (intel_crtc->plane)
5099                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5100         else
5101                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5102
5103         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5104                 BEGIN_LP_RING(2);
5105                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5106                 OUT_RING(0);
5107                 ADVANCE_LP_RING();
5108         }
5109
5110         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5111         offset = obj_priv->gtt_offset;
5112         offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5113
5114         BEGIN_LP_RING(4);
5115         if (IS_I965G(dev)) {
5116                 OUT_RING(MI_DISPLAY_FLIP |
5117                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5118                 OUT_RING(fb->pitch);
5119                 OUT_RING(offset | obj_priv->tiling_mode);
5120                 pipesrc = I915_READ(pipesrc_reg);
5121                 OUT_RING(pipesrc & 0x0fff0fff);
5122         } else if (IS_GEN3(dev)) {
5123                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5124                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5125                 OUT_RING(fb->pitch);
5126                 OUT_RING(offset);
5127                 OUT_RING(MI_NOOP);
5128         } else {
5129                 OUT_RING(MI_DISPLAY_FLIP |
5130                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5131                 OUT_RING(fb->pitch);
5132                 OUT_RING(offset);
5133                 OUT_RING(MI_NOOP);
5134         }
5135         ADVANCE_LP_RING();
5136
5137         mutex_unlock(&dev->struct_mutex);
5138
5139         trace_i915_flip_request(intel_crtc->plane, obj);
5140
5141         return 0;
5142
5143 cleanup_objs:
5144         drm_gem_object_unreference(work->old_fb_obj);
5145         drm_gem_object_unreference(obj);
5146 cleanup_work:
5147         mutex_unlock(&dev->struct_mutex);
5148
5149         spin_lock_irqsave(&dev->event_lock, flags);
5150         intel_crtc->unpin_work = NULL;
5151         spin_unlock_irqrestore(&dev->event_lock, flags);
5152
5153         kfree(work);
5154
5155         return ret;
5156 }
5157
5158 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5159         .dpms = intel_crtc_dpms,
5160         .mode_fixup = intel_crtc_mode_fixup,
5161         .mode_set = intel_crtc_mode_set,
5162         .mode_set_base = intel_pipe_set_base,
5163         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5164         .prepare = intel_crtc_prepare,
5165         .commit = intel_crtc_commit,
5166         .load_lut = intel_crtc_load_lut,
5167 };
5168
5169 static const struct drm_crtc_funcs intel_crtc_funcs = {
5170         .cursor_set = intel_crtc_cursor_set,
5171         .cursor_move = intel_crtc_cursor_move,
5172         .gamma_set = intel_crtc_gamma_set,
5173         .set_config = drm_crtc_helper_set_config,
5174         .destroy = intel_crtc_destroy,
5175         .page_flip = intel_crtc_page_flip,
5176 };
5177
5178
5179 static void intel_crtc_init(struct drm_device *dev, int pipe)
5180 {
5181         drm_i915_private_t *dev_priv = dev->dev_private;
5182         struct intel_crtc *intel_crtc;
5183         int i;
5184
5185         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5186         if (intel_crtc == NULL)
5187                 return;
5188
5189         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5190
5191         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5192         intel_crtc->pipe = pipe;
5193         intel_crtc->plane = pipe;
5194         for (i = 0; i < 256; i++) {
5195                 intel_crtc->lut_r[i] = i;
5196                 intel_crtc->lut_g[i] = i;
5197                 intel_crtc->lut_b[i] = i;
5198         }
5199
5200         /* Swap pipes & planes for FBC on pre-965 */
5201         intel_crtc->pipe = pipe;
5202         intel_crtc->plane = pipe;
5203         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5204                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5205                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5206         }
5207
5208         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5209                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5210         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5211         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5212
5213         intel_crtc->cursor_addr = 0;
5214         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5215         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5216
5217         intel_crtc->busy = false;
5218
5219         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5220                     (unsigned long)intel_crtc);
5221 }
5222
5223 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5224                                 struct drm_file *file_priv)
5225 {
5226         drm_i915_private_t *dev_priv = dev->dev_private;
5227         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5228         struct drm_mode_object *drmmode_obj;
5229         struct intel_crtc *crtc;
5230
5231         if (!dev_priv) {
5232                 DRM_ERROR("called with no initialization\n");
5233                 return -EINVAL;
5234         }
5235
5236         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5237                         DRM_MODE_OBJECT_CRTC);
5238
5239         if (!drmmode_obj) {
5240                 DRM_ERROR("no such CRTC id\n");
5241                 return -EINVAL;
5242         }
5243
5244         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5245         pipe_from_crtc_id->pipe = crtc->pipe;
5246
5247         return 0;
5248 }
5249
5250 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5251 {
5252         struct drm_crtc *crtc = NULL;
5253
5254         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5255                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5256                 if (intel_crtc->pipe == pipe)
5257                         break;
5258         }
5259         return crtc;
5260 }
5261
5262 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5263 {
5264         int index_mask = 0;
5265         struct drm_encoder *encoder;
5266         int entry = 0;
5267
5268         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5269                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5270                 if (type_mask & intel_encoder->clone_mask)
5271                         index_mask |= (1 << entry);
5272                 entry++;
5273         }
5274         return index_mask;
5275 }
5276
5277
5278 static void intel_setup_outputs(struct drm_device *dev)
5279 {
5280         struct drm_i915_private *dev_priv = dev->dev_private;
5281         struct drm_encoder *encoder;
5282         bool dpd_is_edp = false;
5283
5284         if (IS_MOBILE(dev) && !IS_I830(dev))
5285                 intel_lvds_init(dev);
5286
5287         if (HAS_PCH_SPLIT(dev)) {
5288                 dpd_is_edp = intel_dpd_is_edp(dev);
5289
5290                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5291                         intel_dp_init(dev, DP_A);
5292
5293                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5294                         intel_dp_init(dev, PCH_DP_D);
5295         }
5296
5297         intel_crt_init(dev);
5298
5299         if (HAS_PCH_SPLIT(dev)) {
5300                 int found;
5301
5302                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5303                         /* PCH SDVOB multiplex with HDMIB */
5304                         found = intel_sdvo_init(dev, PCH_SDVOB);
5305                         if (!found)
5306                                 intel_hdmi_init(dev, HDMIB);
5307                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5308                                 intel_dp_init(dev, PCH_DP_B);
5309                 }
5310
5311                 if (I915_READ(HDMIC) & PORT_DETECTED)
5312                         intel_hdmi_init(dev, HDMIC);
5313
5314                 if (I915_READ(HDMID) & PORT_DETECTED)
5315                         intel_hdmi_init(dev, HDMID);
5316
5317                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5318                         intel_dp_init(dev, PCH_DP_C);
5319
5320                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5321                         intel_dp_init(dev, PCH_DP_D);
5322
5323         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5324                 bool found = false;
5325
5326                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5327                         DRM_DEBUG_KMS("probing SDVOB\n");
5328                         found = intel_sdvo_init(dev, SDVOB);
5329                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5330                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5331                                 intel_hdmi_init(dev, SDVOB);
5332                         }
5333
5334                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5335                                 DRM_DEBUG_KMS("probing DP_B\n");
5336                                 intel_dp_init(dev, DP_B);
5337                         }
5338                 }
5339
5340                 /* Before G4X SDVOC doesn't have its own detect register */
5341
5342                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5343                         DRM_DEBUG_KMS("probing SDVOC\n");
5344                         found = intel_sdvo_init(dev, SDVOC);
5345                 }
5346
5347                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5348
5349                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5350                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5351                                 intel_hdmi_init(dev, SDVOC);
5352                         }
5353                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5354                                 DRM_DEBUG_KMS("probing DP_C\n");
5355                                 intel_dp_init(dev, DP_C);
5356                         }
5357                 }
5358
5359                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5360                     (I915_READ(DP_D) & DP_DETECTED)) {
5361                         DRM_DEBUG_KMS("probing DP_D\n");
5362                         intel_dp_init(dev, DP_D);
5363                 }
5364         } else if (IS_GEN2(dev))
5365                 intel_dvo_init(dev);
5366
5367         if (SUPPORTS_TV(dev))
5368                 intel_tv_init(dev);
5369
5370         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5371                 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5372
5373                 encoder->possible_crtcs = intel_encoder->crtc_mask;
5374                 encoder->possible_clones = intel_encoder_clones(dev,
5375                                                 intel_encoder->clone_mask);
5376         }
5377 }
5378
5379 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5380 {
5381         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5382
5383         drm_framebuffer_cleanup(fb);
5384         drm_gem_object_unreference_unlocked(intel_fb->obj);
5385
5386         kfree(intel_fb);
5387 }
5388
5389 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5390                                                 struct drm_file *file_priv,
5391                                                 unsigned int *handle)
5392 {
5393         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5394         struct drm_gem_object *object = intel_fb->obj;
5395
5396         return drm_gem_handle_create(file_priv, object, handle);
5397 }
5398
5399 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5400         .destroy = intel_user_framebuffer_destroy,
5401         .create_handle = intel_user_framebuffer_create_handle,
5402 };
5403
5404 int intel_framebuffer_init(struct drm_device *dev,
5405                            struct intel_framebuffer *intel_fb,
5406                            struct drm_mode_fb_cmd *mode_cmd,
5407                            struct drm_gem_object *obj)
5408 {
5409         int ret;
5410
5411         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5412         if (ret) {
5413                 DRM_ERROR("framebuffer init failed %d\n", ret);
5414                 return ret;
5415         }
5416
5417         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5418         intel_fb->obj = obj;
5419         return 0;
5420 }
5421
5422 static struct drm_framebuffer *
5423 intel_user_framebuffer_create(struct drm_device *dev,
5424                               struct drm_file *filp,
5425                               struct drm_mode_fb_cmd *mode_cmd)
5426 {
5427         struct drm_gem_object *obj;
5428         struct intel_framebuffer *intel_fb;
5429         int ret;
5430
5431         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5432         if (!obj)
5433                 return NULL;
5434
5435         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5436         if (!intel_fb)
5437                 return NULL;
5438
5439         ret = intel_framebuffer_init(dev, intel_fb,
5440                                      mode_cmd, obj);
5441         if (ret) {
5442                 drm_gem_object_unreference_unlocked(obj);
5443                 kfree(intel_fb);
5444                 return NULL;
5445         }
5446
5447         return &intel_fb->base;
5448 }
5449
5450 static const struct drm_mode_config_funcs intel_mode_funcs = {
5451         .fb_create = intel_user_framebuffer_create,
5452         .output_poll_changed = intel_fb_output_poll_changed,
5453 };
5454
5455 static struct drm_gem_object *
5456 intel_alloc_power_context(struct drm_device *dev)
5457 {
5458         struct drm_gem_object *pwrctx;
5459         int ret;
5460
5461         pwrctx = i915_gem_alloc_object(dev, 4096);
5462         if (!pwrctx) {
5463                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5464                 return NULL;
5465         }
5466
5467         mutex_lock(&dev->struct_mutex);
5468         ret = i915_gem_object_pin(pwrctx, 4096);
5469         if (ret) {
5470                 DRM_ERROR("failed to pin power context: %d\n", ret);
5471                 goto err_unref;
5472         }
5473
5474         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5475         if (ret) {
5476                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5477                 goto err_unpin;
5478         }
5479         mutex_unlock(&dev->struct_mutex);
5480
5481         return pwrctx;
5482
5483 err_unpin:
5484         i915_gem_object_unpin(pwrctx);
5485 err_unref:
5486         drm_gem_object_unreference(pwrctx);
5487         mutex_unlock(&dev->struct_mutex);
5488         return NULL;
5489 }
5490
5491 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5492 {
5493         struct drm_i915_private *dev_priv = dev->dev_private;
5494         u16 rgvswctl;
5495
5496         rgvswctl = I915_READ16(MEMSWCTL);
5497         if (rgvswctl & MEMCTL_CMD_STS) {
5498                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5499                 return false; /* still busy with another command */
5500         }
5501
5502         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5503                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5504         I915_WRITE16(MEMSWCTL, rgvswctl);
5505         POSTING_READ16(MEMSWCTL);
5506
5507         rgvswctl |= MEMCTL_CMD_STS;
5508         I915_WRITE16(MEMSWCTL, rgvswctl);
5509
5510         return true;
5511 }
5512
5513 void ironlake_enable_drps(struct drm_device *dev)
5514 {
5515         struct drm_i915_private *dev_priv = dev->dev_private;
5516         u32 rgvmodectl = I915_READ(MEMMODECTL);
5517         u8 fmax, fmin, fstart, vstart;
5518         int i = 0;
5519
5520         /* 100ms RC evaluation intervals */
5521         I915_WRITE(RCUPEI, 100000);
5522         I915_WRITE(RCDNEI, 100000);
5523
5524         /* Set max/min thresholds to 90ms and 80ms respectively */
5525         I915_WRITE(RCBMAXAVG, 90000);
5526         I915_WRITE(RCBMINAVG, 80000);
5527
5528         I915_WRITE(MEMIHYST, 1);
5529
5530         /* Set up min, max, and cur for interrupt handling */
5531         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5532         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5533         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5534                 MEMMODE_FSTART_SHIFT;
5535         fstart = fmax;
5536
5537         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5538                 PXVFREQ_PX_SHIFT;
5539
5540         dev_priv->fmax = fstart; /* IPS callback will increase this */
5541         dev_priv->fstart = fstart;
5542
5543         dev_priv->max_delay = fmax;
5544         dev_priv->min_delay = fmin;
5545         dev_priv->cur_delay = fstart;
5546
5547         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5548                          fstart);
5549
5550         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5551
5552         /*
5553          * Interrupts will be enabled in ironlake_irq_postinstall
5554          */
5555
5556         I915_WRITE(VIDSTART, vstart);
5557         POSTING_READ(VIDSTART);
5558
5559         rgvmodectl |= MEMMODE_SWMODE_EN;
5560         I915_WRITE(MEMMODECTL, rgvmodectl);
5561
5562         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5563                 if (i++ > 100) {
5564                         DRM_ERROR("stuck trying to change perf mode\n");
5565                         break;
5566                 }
5567                 msleep(1);
5568         }
5569         msleep(1);
5570
5571         ironlake_set_drps(dev, fstart);
5572
5573         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5574                 I915_READ(0x112e0);
5575         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5576         dev_priv->last_count2 = I915_READ(0x112f4);
5577         getrawmonotonic(&dev_priv->last_time2);
5578 }
5579
5580 void ironlake_disable_drps(struct drm_device *dev)
5581 {
5582         struct drm_i915_private *dev_priv = dev->dev_private;
5583         u16 rgvswctl = I915_READ16(MEMSWCTL);
5584
5585         /* Ack interrupts, disable EFC interrupt */
5586         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5587         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5588         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5589         I915_WRITE(DEIIR, DE_PCU_EVENT);
5590         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5591
5592         /* Go back to the starting frequency */
5593         ironlake_set_drps(dev, dev_priv->fstart);
5594         msleep(1);
5595         rgvswctl |= MEMCTL_CMD_STS;
5596         I915_WRITE(MEMSWCTL, rgvswctl);
5597         msleep(1);
5598
5599 }
5600
5601 static unsigned long intel_pxfreq(u32 vidfreq)
5602 {
5603         unsigned long freq;
5604         int div = (vidfreq & 0x3f0000) >> 16;
5605         int post = (vidfreq & 0x3000) >> 12;
5606         int pre = (vidfreq & 0x7);
5607
5608         if (!pre)
5609                 return 0;
5610
5611         freq = ((div * 133333) / ((1<<post) * pre));
5612
5613         return freq;
5614 }
5615
5616 void intel_init_emon(struct drm_device *dev)
5617 {
5618         struct drm_i915_private *dev_priv = dev->dev_private;
5619         u32 lcfuse;
5620         u8 pxw[16];
5621         int i;
5622
5623         /* Disable to program */
5624         I915_WRITE(ECR, 0);
5625         POSTING_READ(ECR);
5626
5627         /* Program energy weights for various events */
5628         I915_WRITE(SDEW, 0x15040d00);
5629         I915_WRITE(CSIEW0, 0x007f0000);
5630         I915_WRITE(CSIEW1, 0x1e220004);
5631         I915_WRITE(CSIEW2, 0x04000004);
5632
5633         for (i = 0; i < 5; i++)
5634                 I915_WRITE(PEW + (i * 4), 0);
5635         for (i = 0; i < 3; i++)
5636                 I915_WRITE(DEW + (i * 4), 0);
5637
5638         /* Program P-state weights to account for frequency power adjustment */
5639         for (i = 0; i < 16; i++) {
5640                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5641                 unsigned long freq = intel_pxfreq(pxvidfreq);
5642                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5643                         PXVFREQ_PX_SHIFT;
5644                 unsigned long val;
5645
5646                 val = vid * vid;
5647                 val *= (freq / 1000);
5648                 val *= 255;
5649                 val /= (127*127*900);
5650                 if (val > 0xff)
5651                         DRM_ERROR("bad pxval: %ld\n", val);
5652                 pxw[i] = val;
5653         }
5654         /* Render standby states get 0 weight */
5655         pxw[14] = 0;
5656         pxw[15] = 0;
5657
5658         for (i = 0; i < 4; i++) {
5659                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5660                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5661                 I915_WRITE(PXW + (i * 4), val);
5662         }
5663
5664         /* Adjust magic regs to magic values (more experimental results) */
5665         I915_WRITE(OGW0, 0);
5666         I915_WRITE(OGW1, 0);
5667         I915_WRITE(EG0, 0x00007f00);
5668         I915_WRITE(EG1, 0x0000000e);
5669         I915_WRITE(EG2, 0x000e0000);
5670         I915_WRITE(EG3, 0x68000300);
5671         I915_WRITE(EG4, 0x42000000);
5672         I915_WRITE(EG5, 0x00140031);
5673         I915_WRITE(EG6, 0);
5674         I915_WRITE(EG7, 0);
5675
5676         for (i = 0; i < 8; i++)
5677                 I915_WRITE(PXWL + (i * 4), 0);
5678
5679         /* Enable PMON + select events */
5680         I915_WRITE(ECR, 0x80000019);
5681
5682         lcfuse = I915_READ(LCFUSE02);
5683
5684         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5685 }
5686
5687 void intel_init_clock_gating(struct drm_device *dev)
5688 {
5689         struct drm_i915_private *dev_priv = dev->dev_private;
5690
5691         /*
5692          * Disable clock gating reported to work incorrectly according to the
5693          * specs, but enable as much else as we can.
5694          */
5695         if (HAS_PCH_SPLIT(dev)) {
5696                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5697
5698                 if (IS_IRONLAKE(dev)) {
5699                         /* Required for FBC */
5700                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5701                         /* Required for CxSR */
5702                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5703
5704                         I915_WRITE(PCH_3DCGDIS0,
5705                                    MARIUNIT_CLOCK_GATE_DISABLE |
5706                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5707                 }
5708
5709                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5710
5711                 /*
5712                  * According to the spec the following bits should be set in
5713                  * order to enable memory self-refresh
5714                  * The bit 22/21 of 0x42004
5715                  * The bit 5 of 0x42020
5716                  * The bit 15 of 0x45000
5717                  */
5718                 if (IS_IRONLAKE(dev)) {
5719                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5720                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5721                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5722                         I915_WRITE(ILK_DSPCLK_GATE,
5723                                         (I915_READ(ILK_DSPCLK_GATE) |
5724                                                 ILK_DPARB_CLK_GATE));
5725                         I915_WRITE(DISP_ARB_CTL,
5726                                         (I915_READ(DISP_ARB_CTL) |
5727                                                 DISP_FBC_WM_DIS));
5728                 }
5729                 /*
5730                  * Based on the document from hardware guys the following bits
5731                  * should be set unconditionally in order to enable FBC.
5732                  * The bit 22 of 0x42000
5733                  * The bit 22 of 0x42004
5734                  * The bit 7,8,9 of 0x42020.
5735                  */
5736                 if (IS_IRONLAKE_M(dev)) {
5737                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5738                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5739                                    ILK_FBCQ_DIS);
5740                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5741                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5742                                    ILK_DPARB_GATE);
5743                         I915_WRITE(ILK_DSPCLK_GATE,
5744                                    I915_READ(ILK_DSPCLK_GATE) |
5745                                    ILK_DPFC_DIS1 |
5746                                    ILK_DPFC_DIS2 |
5747                                    ILK_CLK_FBC);
5748                 }
5749                 return;
5750         } else if (IS_G4X(dev)) {
5751                 uint32_t dspclk_gate;
5752                 I915_WRITE(RENCLK_GATE_D1, 0);
5753                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5754                        GS_UNIT_CLOCK_GATE_DISABLE |
5755                        CL_UNIT_CLOCK_GATE_DISABLE);
5756                 I915_WRITE(RAMCLK_GATE_D, 0);
5757                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5758                         OVRUNIT_CLOCK_GATE_DISABLE |
5759                         OVCUNIT_CLOCK_GATE_DISABLE;
5760                 if (IS_GM45(dev))
5761                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5762                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5763         } else if (IS_I965GM(dev)) {
5764                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5765                 I915_WRITE(RENCLK_GATE_D2, 0);
5766                 I915_WRITE(DSPCLK_GATE_D, 0);
5767                 I915_WRITE(RAMCLK_GATE_D, 0);
5768                 I915_WRITE16(DEUC, 0);
5769         } else if (IS_I965G(dev)) {
5770                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5771                        I965_RCC_CLOCK_GATE_DISABLE |
5772                        I965_RCPB_CLOCK_GATE_DISABLE |
5773                        I965_ISC_CLOCK_GATE_DISABLE |
5774                        I965_FBC_CLOCK_GATE_DISABLE);
5775                 I915_WRITE(RENCLK_GATE_D2, 0);
5776         } else if (IS_I9XX(dev)) {
5777                 u32 dstate = I915_READ(D_STATE);
5778
5779                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5780                         DSTATE_DOT_CLOCK_GATING;
5781                 I915_WRITE(D_STATE, dstate);
5782         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5783                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5784         } else if (IS_I830(dev)) {
5785                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5786         }
5787
5788         /*
5789          * GPU can automatically power down the render unit if given a page
5790          * to save state.
5791          */
5792         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5793                 struct drm_i915_gem_object *obj_priv = NULL;
5794
5795                 if (dev_priv->pwrctx) {
5796                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5797                 } else {
5798                         struct drm_gem_object *pwrctx;
5799
5800                         pwrctx = intel_alloc_power_context(dev);
5801                         if (pwrctx) {
5802                                 dev_priv->pwrctx = pwrctx;
5803                                 obj_priv = to_intel_bo(pwrctx);
5804                         }
5805                 }
5806
5807                 if (obj_priv) {
5808                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5809                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5810                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5811                 }
5812         }
5813 }
5814
5815 /* Set up chip specific display functions */
5816 static void intel_init_display(struct drm_device *dev)
5817 {
5818         struct drm_i915_private *dev_priv = dev->dev_private;
5819
5820         /* We always want a DPMS function */
5821         if (HAS_PCH_SPLIT(dev))
5822                 dev_priv->display.dpms = ironlake_crtc_dpms;
5823         else
5824                 dev_priv->display.dpms = i9xx_crtc_dpms;
5825
5826         if (I915_HAS_FBC(dev)) {
5827                 if (IS_IRONLAKE_M(dev)) {
5828                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5829                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5830                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5831                 } else if (IS_GM45(dev)) {
5832                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5833                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5834                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5835                 } else if (IS_I965GM(dev)) {
5836                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5837                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5838                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5839                 }
5840                 /* 855GM needs testing */
5841         }
5842
5843         /* Returns the core display clock speed */
5844         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5845                 dev_priv->display.get_display_clock_speed =
5846                         i945_get_display_clock_speed;
5847         else if (IS_I915G(dev))
5848                 dev_priv->display.get_display_clock_speed =
5849                         i915_get_display_clock_speed;
5850         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5851                 dev_priv->display.get_display_clock_speed =
5852                         i9xx_misc_get_display_clock_speed;
5853         else if (IS_I915GM(dev))
5854                 dev_priv->display.get_display_clock_speed =
5855                         i915gm_get_display_clock_speed;
5856         else if (IS_I865G(dev))
5857                 dev_priv->display.get_display_clock_speed =
5858                         i865_get_display_clock_speed;
5859         else if (IS_I85X(dev))
5860                 dev_priv->display.get_display_clock_speed =
5861                         i855_get_display_clock_speed;
5862         else /* 852, 830 */
5863                 dev_priv->display.get_display_clock_speed =
5864                         i830_get_display_clock_speed;
5865
5866         /* For FIFO watermark updates */
5867         if (HAS_PCH_SPLIT(dev)) {
5868                 if (IS_IRONLAKE(dev)) {
5869                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5870                                 dev_priv->display.update_wm = ironlake_update_wm;
5871                         else {
5872                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5873                                               "Disable CxSR\n");
5874                                 dev_priv->display.update_wm = NULL;
5875                         }
5876                 } else
5877                         dev_priv->display.update_wm = NULL;
5878         } else if (IS_PINEVIEW(dev)) {
5879                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5880                                             dev_priv->is_ddr3,
5881                                             dev_priv->fsb_freq,
5882                                             dev_priv->mem_freq)) {
5883                         DRM_INFO("failed to find known CxSR latency "
5884                                  "(found ddr%s fsb freq %d, mem freq %d), "
5885                                  "disabling CxSR\n",
5886                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5887                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5888                         /* Disable CxSR and never update its watermark again */
5889                         pineview_disable_cxsr(dev);
5890                         dev_priv->display.update_wm = NULL;
5891                 } else
5892                         dev_priv->display.update_wm = pineview_update_wm;
5893         } else if (IS_G4X(dev))
5894                 dev_priv->display.update_wm = g4x_update_wm;
5895         else if (IS_I965G(dev))
5896                 dev_priv->display.update_wm = i965_update_wm;
5897         else if (IS_I9XX(dev)) {
5898                 dev_priv->display.update_wm = i9xx_update_wm;
5899                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5900         } else if (IS_I85X(dev)) {
5901                 dev_priv->display.update_wm = i9xx_update_wm;
5902                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5903         } else {
5904                 dev_priv->display.update_wm = i830_update_wm;
5905                 if (IS_845G(dev))
5906                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5907                 else
5908                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5909         }
5910 }
5911
5912 /*
5913  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5914  * resume, or other times.  This quirk makes sure that's the case for
5915  * affected systems.
5916  */
5917 static void quirk_pipea_force (struct drm_device *dev)
5918 {
5919         struct drm_i915_private *dev_priv = dev->dev_private;
5920
5921         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5922         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5923 }
5924
5925 struct intel_quirk {
5926         int device;
5927         int subsystem_vendor;
5928         int subsystem_device;
5929         void (*hook)(struct drm_device *dev);
5930 };
5931
5932 struct intel_quirk intel_quirks[] = {
5933         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5934         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5935         /* HP Mini needs pipe A force quirk (LP: #322104) */
5936         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5937
5938         /* Thinkpad R31 needs pipe A force quirk */
5939         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5940         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5941         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5942
5943         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5944         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5945         /* ThinkPad X40 needs pipe A force quirk */
5946
5947         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5948         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5949
5950         /* 855 & before need to leave pipe A & dpll A up */
5951         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5952         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5953 };
5954
5955 static void intel_init_quirks(struct drm_device *dev)
5956 {
5957         struct pci_dev *d = dev->pdev;
5958         int i;
5959
5960         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5961                 struct intel_quirk *q = &intel_quirks[i];
5962
5963                 if (d->device == q->device &&
5964                     (d->subsystem_vendor == q->subsystem_vendor ||
5965                      q->subsystem_vendor == PCI_ANY_ID) &&
5966                     (d->subsystem_device == q->subsystem_device ||
5967                      q->subsystem_device == PCI_ANY_ID))
5968                         q->hook(dev);
5969         }
5970 }
5971
5972 void intel_modeset_init(struct drm_device *dev)
5973 {
5974         struct drm_i915_private *dev_priv = dev->dev_private;
5975         int i;
5976
5977         drm_mode_config_init(dev);
5978
5979         dev->mode_config.min_width = 0;
5980         dev->mode_config.min_height = 0;
5981
5982         dev->mode_config.funcs = (void *)&intel_mode_funcs;
5983
5984         intel_init_quirks(dev);
5985
5986         intel_init_display(dev);
5987
5988         if (IS_I965G(dev)) {
5989                 dev->mode_config.max_width = 8192;
5990                 dev->mode_config.max_height = 8192;
5991         } else if (IS_I9XX(dev)) {
5992                 dev->mode_config.max_width = 4096;
5993                 dev->mode_config.max_height = 4096;
5994         } else {
5995                 dev->mode_config.max_width = 2048;
5996                 dev->mode_config.max_height = 2048;
5997         }
5998
5999         /* set memory base */
6000         if (IS_I9XX(dev))
6001                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6002         else
6003                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6004
6005         if (IS_MOBILE(dev) || IS_I9XX(dev))
6006                 dev_priv->num_pipe = 2;
6007         else
6008                 dev_priv->num_pipe = 1;
6009         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6010                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6011
6012         for (i = 0; i < dev_priv->num_pipe; i++) {
6013                 intel_crtc_init(dev, i);
6014         }
6015
6016         intel_setup_outputs(dev);
6017
6018         intel_init_clock_gating(dev);
6019
6020         if (IS_IRONLAKE_M(dev)) {
6021                 ironlake_enable_drps(dev);
6022                 intel_init_emon(dev);
6023         }
6024
6025         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6026         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6027                     (unsigned long)dev);
6028
6029         intel_setup_overlay(dev);
6030 }
6031
6032 void intel_modeset_cleanup(struct drm_device *dev)
6033 {
6034         struct drm_i915_private *dev_priv = dev->dev_private;
6035         struct drm_crtc *crtc;
6036         struct intel_crtc *intel_crtc;
6037
6038         mutex_lock(&dev->struct_mutex);
6039
6040         drm_kms_helper_poll_fini(dev);
6041         intel_fbdev_fini(dev);
6042
6043         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6044                 /* Skip inactive CRTCs */
6045                 if (!crtc->fb)
6046                         continue;
6047
6048                 intel_crtc = to_intel_crtc(crtc);
6049                 intel_increase_pllclock(crtc, false);
6050                 del_timer_sync(&intel_crtc->idle_timer);
6051         }
6052
6053         del_timer_sync(&dev_priv->idle_timer);
6054
6055         if (dev_priv->display.disable_fbc)
6056                 dev_priv->display.disable_fbc(dev);
6057
6058         if (dev_priv->pwrctx) {
6059                 struct drm_i915_gem_object *obj_priv;
6060
6061                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6062                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6063                 I915_READ(PWRCTXA);
6064                 i915_gem_object_unpin(dev_priv->pwrctx);
6065                 drm_gem_object_unreference(dev_priv->pwrctx);
6066         }
6067
6068         if (IS_IRONLAKE_M(dev))
6069                 ironlake_disable_drps(dev);
6070
6071         mutex_unlock(&dev->struct_mutex);
6072
6073         drm_mode_config_cleanup(dev);
6074 }
6075
6076
6077 /*
6078  * Return which encoder is currently attached for connector.
6079  */
6080 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6081 {
6082         struct drm_mode_object *obj;
6083         struct drm_encoder *encoder;
6084         int i;
6085
6086         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6087                 if (connector->encoder_ids[i] == 0)
6088                         break;
6089
6090                 obj = drm_mode_object_find(connector->dev,
6091                                            connector->encoder_ids[i],
6092                                            DRM_MODE_OBJECT_ENCODER);
6093                 if (!obj)
6094                         continue;
6095
6096                 encoder = obj_to_encoder(obj);
6097                 return encoder;
6098         }
6099         return NULL;
6100 }
6101
6102 /*
6103  * set vga decode state - true == enable VGA decode
6104  */
6105 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6106 {
6107         struct drm_i915_private *dev_priv = dev->dev_private;
6108         u16 gmch_ctrl;
6109
6110         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6111         if (state)
6112                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6113         else
6114                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6115         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6116         return 0;
6117 }