drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 297 {
 298         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 299         int ret = IRQ_NONE;
 300         u32 de_iir, gt_iir, de_ier, pch_iir;
 301         struct drm_i915_master_private *master_priv;
 302         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 303         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 304
 305         if (IS_GEN6(dev))
 306                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 307
 308         /* disable master interrupt before clearing iir  */
 309         de_ier = I915_READ(DEIER);
 310         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 311         (void)I915_READ(DEIER);
 312
 313         de_iir = I915_READ(DEIIR);
 314         gt_iir = I915_READ(GTIIR);
 315         pch_iir = I915_READ(SDEIIR);
 316
 317         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 318                 goto done;
 319
 320         ret = IRQ_HANDLED;
 321
 322         if (dev->primary->master) {
 323                 master_priv = dev->primary->master->driver_priv;
 324                 if (master_priv->sarea_priv)
 325                         master_priv->sarea_priv->last_dispatch =
 326                                 READ_BREADCRUMB(dev_priv);
 327         }
 328
 329         if (gt_iir & GT_PIPE_NOTIFY) {
 330                 u32 seqno = render_ring->get_seqno(dev, render_ring);
 331                 render_ring->irq_gem_seqno = seqno;
 332                 trace_i915_gem_request_complete(dev, seqno);
 333                 wake_up_all(&dev_priv->render_ring.irq_queue);
 334                 dev_priv->hangcheck_count = 0;
 335                 mod_timer(&dev_priv->hangcheck_timer,
 336                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 337         }
 338         if (gt_iir & bsd_usr_interrupt)
 339                 wake_up_all(&dev_priv->bsd_ring.irq_queue);
 340
 341         if (de_iir & DE_GSE)
 342                 intel_opregion_gse_intr(dev);
 343
 344         if (de_iir & DE_PLANEA_FLIP_DONE) {
 345                 intel_prepare_page_flip(dev, 0);
 346                 intel_finish_page_flip_plane(dev, 0);
 347         }
 348
 349         if (de_iir & DE_PLANEB_FLIP_DONE) {
 350                 intel_prepare_page_flip(dev, 1);
 351                 intel_finish_page_flip_plane(dev, 1);
 352         }
 353
 354         if (de_iir & DE_PIPEA_VBLANK)
 355                 drm_handle_vblank(dev, 0);
 356
 357         if (de_iir & DE_PIPEB_VBLANK)
 358                 drm_handle_vblank(dev, 1);
 359
 360         /* check event from PCH */
 361         if ((de_iir & DE_PCH_EVENT) &&
 362             (pch_iir & SDE_HOTPLUG_MASK)) {
 363                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 364         }
 365
 366         if (de_iir & DE_PCU_EVENT) {
 367                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 368                 i915_handle_rps_change(dev);
 369         }
 370
 371         /* should clear PCH hotplug event before clear CPU irq */
 372         I915_WRITE(SDEIIR, pch_iir);
 373         I915_WRITE(GTIIR, gt_iir);
 374         I915_WRITE(DEIIR, de_iir);
 375
 376 done:
 377         I915_WRITE(DEIER, de_ier);
 378         (void)I915_READ(DEIER);
 379
 380         return ret;
 381 }
 382
 383 /**
 384  * i915_error_work_func - do process context error handling work
 385  * @work: work struct
 386  *
 387  * Fire an error uevent so userspace can see that a hang or error
 388  * was detected.
 389  */
 390 static void i915_error_work_func(struct work_struct *work)
 391 {
 392         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 393                                                     error_work);
 394         struct drm_device *dev = dev_priv->dev;
 395         char *error_event[] = { "ERROR=1", NULL };
 396         char *reset_event[] = { "RESET=1", NULL };
 397         char *reset_done_event[] = { "ERROR=0", NULL };
 398
 399         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 400
 401         if (atomic_read(&dev_priv->mm.wedged)) {
 402                 DRM_DEBUG_DRIVER("resetting chip\n");
 403                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 404                 if (!i915_reset(dev, GRDOM_RENDER)) {
 405                         atomic_set(&dev_priv->mm.wedged, 0);
 406                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 407                 }
 408                 complete_all(&dev_priv->error_completion);
 409         }
 410 }
 411
 412 #ifdef CONFIG_DEBUG_FS
 413 static struct drm_i915_error_object *
 414 i915_error_object_create(struct drm_device *dev,
 415                          struct drm_gem_object *src)
 416 {
 417         drm_i915_private_t *dev_priv = dev->dev_private;
 418         struct drm_i915_error_object *dst;
 419         struct drm_i915_gem_object *src_priv;
 420         int page, page_count;
 421         u32 reloc_offset;
 422
 423         if (src == NULL)
 424                 return NULL;
 425
 426         src_priv = to_intel_bo(src);
 427         if (src_priv->pages == NULL)
 428                 return NULL;
 429
 430         page_count = src->size / PAGE_SIZE;
 431
 432         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 433         if (dst == NULL)
 434                 return NULL;
 435
 436         reloc_offset = src_priv->gtt_offset;
 437         for (page = 0; page < page_count; page++) {
 438                 unsigned long flags;
 439                 void __iomem *s;
 440                 void *d;
 441
 442                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 443                 if (d == NULL)
 444                         goto unwind;
 445
 446                 local_irq_save(flags);
 447                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 448                                              reloc_offset,
 449                                              KM_IRQ0);
 450                 memcpy_fromio(d, s, PAGE_SIZE);
 451                 io_mapping_unmap_atomic(s, KM_IRQ0);
 452                 local_irq_restore(flags);
 453
 454                 dst->pages[page] = d;
 455
 456                 reloc_offset += PAGE_SIZE;
 457         }
 458         dst->page_count = page_count;
 459         dst->gtt_offset = src_priv->gtt_offset;
 460
 461         return dst;
 462
 463 unwind:
 464         while (page--)
 465                 kfree(dst->pages[page]);
 466         kfree(dst);
 467         return NULL;
 468 }
 469
 470 static void
 471 i915_error_object_free(struct drm_i915_error_object *obj)
 472 {
 473         int page;
 474
 475         if (obj == NULL)
 476                 return;
 477
 478         for (page = 0; page < obj->page_count; page++)
 479                 kfree(obj->pages[page]);
 480
 481         kfree(obj);
 482 }
 483
 484 static void
 485 i915_error_state_free(struct drm_device *dev,
 486                       struct drm_i915_error_state *error)
 487 {
 488         i915_error_object_free(error->batchbuffer[0]);
 489         i915_error_object_free(error->batchbuffer[1]);
 490         i915_error_object_free(error->ringbuffer);
 491         kfree(error->active_bo);
 492         kfree(error->overlay);
 493         kfree(error);
 494 }
 495
 496 static u32
 497 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 498 {
 499         u32 cmd;
 500
 501         if (IS_I830(dev) || IS_845G(dev))
 502                 cmd = MI_BATCH_BUFFER;
 503         else if (INTEL_INFO(dev)->gen >= 4)
 504                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 505                        MI_BATCH_NON_SECURE_I965);
 506         else
 507                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 508
 509         return ring[0] == cmd ? ring[1] : 0;
 510 }
 511
 512 static u32
 513 i915_ringbuffer_last_batch(struct drm_device *dev)
 514 {
 515         struct drm_i915_private *dev_priv = dev->dev_private;
 516         u32 head, bbaddr;
 517         u32 *ring;
 518
 519         /* Locate the current position in the ringbuffer and walk back
 520          * to find the most recently dispatched batch buffer.
 521          */
 522         bbaddr = 0;
 523         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 524         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 525
 526         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 527                 bbaddr = i915_get_bbaddr(dev, ring);
 528                 if (bbaddr)
 529                         break;
 530         }
 531
 532         if (bbaddr == 0) {
 533                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 534                                 + dev_priv->render_ring.size);
 535                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 536                         bbaddr = i915_get_bbaddr(dev, ring);
 537                         if (bbaddr)
 538                                 break;
 539                 }
 540         }
 541
 542         return bbaddr;
 543 }
 544
 545 /**
 546  * i915_capture_error_state - capture an error record for later analysis
 547  * @dev: drm device
 548  *
 549  * Should be called when an error is detected (either a hang or an error
 550  * interrupt) to capture error state from the time of the error.  Fills
 551  * out a structure which becomes available in debugfs for user level tools
 552  * to pick up.
 553  */
 554 static void i915_capture_error_state(struct drm_device *dev)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         struct drm_i915_gem_object *obj_priv;
 558         struct drm_i915_error_state *error;
 559         struct drm_gem_object *batchbuffer[2];
 560         unsigned long flags;
 561         u32 bbaddr;
 562         int count;
 563
 564         spin_lock_irqsave(&dev_priv->error_lock, flags);
 565         error = dev_priv->first_error;
 566         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 567         if (error)
 568                 return;
 569
 570         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 571         if (!error) {
 572                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 573                 return;
 574         }
 575
 576         DRM_DEBUG_DRIVER("generating error event\n");
 577
 578         error->seqno =
 579                 dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring);
 580         error->eir = I915_READ(EIR);
 581         error->pgtbl_er = I915_READ(PGTBL_ER);
 582         error->pipeastat = I915_READ(PIPEASTAT);
 583         error->pipebstat = I915_READ(PIPEBSTAT);
 584         error->instpm = I915_READ(INSTPM);
 585         if (INTEL_INFO(dev)->gen < 4) {
 586                 error->ipeir = I915_READ(IPEIR);
 587                 error->ipehr = I915_READ(IPEHR);
 588                 error->instdone = I915_READ(INSTDONE);
 589                 error->acthd = I915_READ(ACTHD);
 590                 error->bbaddr = 0;
 591         } else {
 592                 error->ipeir = I915_READ(IPEIR_I965);
 593                 error->ipehr = I915_READ(IPEHR_I965);
 594                 error->instdone = I915_READ(INSTDONE_I965);
 595                 error->instps = I915_READ(INSTPS);
 596                 error->instdone1 = I915_READ(INSTDONE1);
 597                 error->acthd = I915_READ(ACTHD_I965);
 598                 error->bbaddr = I915_READ64(BB_ADDR);
 599         }
 600
 601         bbaddr = i915_ringbuffer_last_batch(dev);
 602
 603         /* Grab the current batchbuffer, most likely to have crashed. */
 604         batchbuffer[0] = NULL;
 605         batchbuffer[1] = NULL;
 606         count = 0;
 607         list_for_each_entry(obj_priv,
 608                         &dev_priv->render_ring.active_list, list) {
 609
 610                 struct drm_gem_object *obj = &obj_priv->base;
 611
 612                 if (batchbuffer[0] == NULL &&
 613                     bbaddr >= obj_priv->gtt_offset &&
 614                     bbaddr < obj_priv->gtt_offset + obj->size)
 615                         batchbuffer[0] = obj;
 616
 617                 if (batchbuffer[1] == NULL &&
 618                     error->acthd >= obj_priv->gtt_offset &&
 619                     error->acthd < obj_priv->gtt_offset + obj->size)
 620                         batchbuffer[1] = obj;
 621
 622                 count++;
 623         }
 624         /* Scan the other lists for completeness for those bizarre errors. */
 625         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 626                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
 627                         struct drm_gem_object *obj = &obj_priv->base;
 628
 629                         if (batchbuffer[0] == NULL &&
 630                             bbaddr >= obj_priv->gtt_offset &&
 631                             bbaddr < obj_priv->gtt_offset + obj->size)
 632                                 batchbuffer[0] = obj;
 633
 634                         if (batchbuffer[1] == NULL &&
 635                             error->acthd >= obj_priv->gtt_offset &&
 636                             error->acthd < obj_priv->gtt_offset + obj->size)
 637                                 batchbuffer[1] = obj;
 638
 639                         if (batchbuffer[0] && batchbuffer[1])
 640                                 break;
 641                 }
 642         }
 643         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 644                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 645                         struct drm_gem_object *obj = &obj_priv->base;
 646
 647                         if (batchbuffer[0] == NULL &&
 648                             bbaddr >= obj_priv->gtt_offset &&
 649                             bbaddr < obj_priv->gtt_offset + obj->size)
 650                                 batchbuffer[0] = obj;
 651
 652                         if (batchbuffer[1] == NULL &&
 653                             error->acthd >= obj_priv->gtt_offset &&
 654                             error->acthd < obj_priv->gtt_offset + obj->size)
 655                                 batchbuffer[1] = obj;
 656
 657                         if (batchbuffer[0] && batchbuffer[1])
 658                                 break;
 659                 }
 660         }
 661
 662         /* We need to copy these to an anonymous buffer as the simplest
 663          * method to avoid being overwritten by userpace.
 664          */
 665         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 666         if (batchbuffer[1] != batchbuffer[0])
 667                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 668         else
 669                 error->batchbuffer[1] = NULL;
 670
 671         /* Record the ringbuffer */
 672         error->ringbuffer = i915_error_object_create(dev,
 673                         dev_priv->render_ring.gem_object);
 674
 675         /* Record buffers on the active list. */
 676         error->active_bo = NULL;
 677         error->active_bo_count = 0;
 678
 679         if (count)
 680                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 681                                            GFP_ATOMIC);
 682
 683         if (error->active_bo) {
 684                 int i = 0;
 685                 list_for_each_entry(obj_priv,
 686                                 &dev_priv->render_ring.active_list, list) {
 687                         struct drm_gem_object *obj = &obj_priv->base;
 688
 689                         error->active_bo[i].size = obj->size;
 690                         error->active_bo[i].name = obj->name;
 691                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 692                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 693                         error->active_bo[i].read_domains = obj->read_domains;
 694                         error->active_bo[i].write_domain = obj->write_domain;
 695                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 696                         error->active_bo[i].pinned = 0;
 697                         if (obj_priv->pin_count > 0)
 698                                 error->active_bo[i].pinned = 1;
 699                         if (obj_priv->user_pin_count > 0)
 700                                 error->active_bo[i].pinned = -1;
 701                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 702                         error->active_bo[i].dirty = obj_priv->dirty;
 703                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 704
 705                         if (++i == count)
 706                                 break;
 707                 }
 708                 error->active_bo_count = i;
 709         }
 710
 711         do_gettimeofday(&error->time);
 712
 713         error->overlay = intel_overlay_capture_error_state(dev);
 714
 715         spin_lock_irqsave(&dev_priv->error_lock, flags);
 716         if (dev_priv->first_error == NULL) {
 717                 dev_priv->first_error = error;
 718                 error = NULL;
 719         }
 720         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 721
 722         if (error)
 723                 i915_error_state_free(dev, error);
 724 }
 725
 726 void i915_destroy_error_state(struct drm_device *dev)
 727 {
 728         struct drm_i915_private *dev_priv = dev->dev_private;
 729         struct drm_i915_error_state *error;
 730
 731         spin_lock(&dev_priv->error_lock);
 732         error = dev_priv->first_error;
 733         dev_priv->first_error = NULL;
 734         spin_unlock(&dev_priv->error_lock);
 735
 736         if (error)
 737                 i915_error_state_free(dev, error);
 738 }
 739 #else
 740 #define i915_capture_error_state(x)
 741 #endif
 742
 743 static void i915_report_and_clear_eir(struct drm_device *dev)
 744 {
 745         struct drm_i915_private *dev_priv = dev->dev_private;
 746         u32 eir = I915_READ(EIR);
 747
 748         if (!eir)
 749                 return;
 750
 751         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 752                eir);
 753
 754         if (IS_G4X(dev)) {
 755                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 756                         u32 ipeir = I915_READ(IPEIR_I965);
 757
 758                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 759                                I915_READ(IPEIR_I965));
 760                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 761                                I915_READ(IPEHR_I965));
 762                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 763                                I915_READ(INSTDONE_I965));
 764                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 765                                I915_READ(INSTPS));
 766                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 767                                I915_READ(INSTDONE1));
 768                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 769                                I915_READ(ACTHD_I965));
 770                         I915_WRITE(IPEIR_I965, ipeir);
 771                         (void)I915_READ(IPEIR_I965);
 772                 }
 773                 if (eir & GM45_ERROR_PAGE_TABLE) {
 774                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 775                         printk(KERN_ERR "page table error\n");
 776                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 777                                pgtbl_err);
 778                         I915_WRITE(PGTBL_ER, pgtbl_err);
 779                         (void)I915_READ(PGTBL_ER);
 780                 }
 781         }
 782
 783         if (!IS_GEN2(dev)) {
 784                 if (eir & I915_ERROR_PAGE_TABLE) {
 785                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 786                         printk(KERN_ERR "page table error\n");
 787                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 788                                pgtbl_err);
 789                         I915_WRITE(PGTBL_ER, pgtbl_err);
 790                         (void)I915_READ(PGTBL_ER);
 791                 }
 792         }
 793
 794         if (eir & I915_ERROR_MEMORY_REFRESH) {
 795                 u32 pipea_stats = I915_READ(PIPEASTAT);
 796                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 797
 798                 printk(KERN_ERR "memory refresh error\n");
 799                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 800                        pipea_stats);
 801                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 802                        pipeb_stats);
 803                 /* pipestat has already been acked */
 804         }
 805         if (eir & I915_ERROR_INSTRUCTION) {
 806                 printk(KERN_ERR "instruction error\n");
 807                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 808                        I915_READ(INSTPM));
 809                 if (INTEL_INFO(dev)->gen < 4) {
 810                         u32 ipeir = I915_READ(IPEIR);
 811
 812                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 813                                I915_READ(IPEIR));
 814                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 815                                I915_READ(IPEHR));
 816                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 817                                I915_READ(INSTDONE));
 818                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 819                                I915_READ(ACTHD));
 820                         I915_WRITE(IPEIR, ipeir);
 821                         (void)I915_READ(IPEIR);
 822                 } else {
 823                         u32 ipeir = I915_READ(IPEIR_I965);
 824
 825                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 826                                I915_READ(IPEIR_I965));
 827                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 828                                I915_READ(IPEHR_I965));
 829                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 830                                I915_READ(INSTDONE_I965));
 831                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 832                                I915_READ(INSTPS));
 833                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 834                                I915_READ(INSTDONE1));
 835                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 836                                I915_READ(ACTHD_I965));
 837                         I915_WRITE(IPEIR_I965, ipeir);
 838                         (void)I915_READ(IPEIR_I965);
 839                 }
 840         }
 841
 842         I915_WRITE(EIR, eir);
 843         (void)I915_READ(EIR);
 844         eir = I915_READ(EIR);
 845         if (eir) {
 846                 /*
 847                  * some errors might have become stuck,
 848                  * mask them.
 849                  */
 850                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 851                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 852                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 853         }
 854 }
 855
 856 /**
 857  * i915_handle_error - handle an error interrupt
 858  * @dev: drm device
 859  *
 860  * Do some basic checking of regsiter state at error interrupt time and
 861  * dump it to the syslog.  Also call i915_capture_error_state() to make
 862  * sure we get a record and make it available in debugfs.  Fire a uevent
 863  * so userspace knows something bad happened (should trigger collection
 864  * of a ring dump etc.).
 865  */
 866 static void i915_handle_error(struct drm_device *dev, bool wedged)
 867 {
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869
 870         i915_capture_error_state(dev);
 871         i915_report_and_clear_eir(dev);
 872
 873         if (wedged) {
 874                 INIT_COMPLETION(dev_priv->error_completion);
 875                 atomic_set(&dev_priv->mm.wedged, 1);
 876
 877                 /*
 878                  * Wakeup waiting processes so they don't hang
 879                  */
 880                 wake_up_all(&dev_priv->render_ring.irq_queue);
 881                 if (HAS_BSD(dev))
 882                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 883         }
 884
 885         queue_work(dev_priv->wq, &dev_priv->error_work);
 886 }
 887
 888 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 889 {
 890         drm_i915_private_t *dev_priv = dev->dev_private;
 891         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 893         struct drm_i915_gem_object *obj_priv;
 894         struct intel_unpin_work *work;
 895         unsigned long flags;
 896         bool stall_detected;
 897
 898         /* Ignore early vblank irqs */
 899         if (intel_crtc == NULL)
 900                 return;
 901
 902         spin_lock_irqsave(&dev->event_lock, flags);
 903         work = intel_crtc->unpin_work;
 904
 905         if (work == NULL || work->pending || !work->enable_stall_check) {
 906                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 907                 spin_unlock_irqrestore(&dev->event_lock, flags);
 908                 return;
 909         }
 910
 911         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 912         obj_priv = to_intel_bo(work->pending_flip_obj);
 913         if (INTEL_INFO(dev)->gen >= 4) {
 914                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 915                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 916         } else {
 917                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 918                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 919                                                         crtc->y * crtc->fb->pitch +
 920                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 921         }
 922
 923         spin_unlock_irqrestore(&dev->event_lock, flags);
 924
 925         if (stall_detected) {
 926                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 927                 intel_prepare_page_flip(dev, intel_crtc->plane);
 928         }
 929 }
 930
 931 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 932 {
 933         struct drm_device *dev = (struct drm_device *) arg;
 934         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 935         struct drm_i915_master_private *master_priv;
 936         u32 iir, new_iir;
 937         u32 pipea_stats, pipeb_stats;
 938         u32 vblank_status;
 939         int vblank = 0;
 940         unsigned long irqflags;
 941         int irq_received;
 942         int ret = IRQ_NONE;
 943         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 944
 945         atomic_inc(&dev_priv->irq_received);
 946
 947         if (HAS_PCH_SPLIT(dev))
 948                 return ironlake_irq_handler(dev);
 949
 950         iir = I915_READ(IIR);
 951
 952         if (INTEL_INFO(dev)->gen >= 4)
 953                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 954         else
 955                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 956
 957         for (;;) {
 958                 irq_received = iir != 0;
 959
 960                 /* Can't rely on pipestat interrupt bit in iir as it might
 961                  * have been cleared after the pipestat interrupt was received.
 962                  * It doesn't set the bit in iir again, but it still produces
 963                  * interrupts (for non-MSI).
 964                  */
 965                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 966                 pipea_stats = I915_READ(PIPEASTAT);
 967                 pipeb_stats = I915_READ(PIPEBSTAT);
 968
 969                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 970                         i915_handle_error(dev, false);
 971
 972                 /*
 973                  * Clear the PIPE(A|B)STAT regs before the IIR
 974                  */
 975                 if (pipea_stats & 0x8000ffff) {
 976                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 977                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 978                         I915_WRITE(PIPEASTAT, pipea_stats);
 979                         irq_received = 1;
 980                 }
 981
 982                 if (pipeb_stats & 0x8000ffff) {
 983                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 984                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 985                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 986                         irq_received = 1;
 987                 }
 988                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 989
 990                 if (!irq_received)
 991                         break;
 992
 993                 ret = IRQ_HANDLED;
 994
 995                 /* Consume port.  Then clear IIR or we'll miss events */
 996                 if ((I915_HAS_HOTPLUG(dev)) &&
 997                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 998                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 999
1000                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1001                                   hotplug_status);
1002                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1003                                 queue_work(dev_priv->wq,
1004                                            &dev_priv->hotplug_work);
1005
1006                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1007                         I915_READ(PORT_HOTPLUG_STAT);
1008                 }
1009
1010                 I915_WRITE(IIR, iir);
1011                 new_iir = I915_READ(IIR); /* Flush posted writes */
1012
1013                 if (dev->primary->master) {
1014                         master_priv = dev->primary->master->driver_priv;
1015                         if (master_priv->sarea_priv)
1016                                 master_priv->sarea_priv->last_dispatch =
1017                                         READ_BREADCRUMB(dev_priv);
1018                 }
1019
1020                 if (iir & I915_USER_INTERRUPT) {
1021                         u32 seqno = render_ring->get_seqno(dev, render_ring);
1022                         render_ring->irq_gem_seqno = seqno;
1023                         trace_i915_gem_request_complete(dev, seqno);
1024                         wake_up_all(&dev_priv->render_ring.irq_queue);
1025                         dev_priv->hangcheck_count = 0;
1026                         mod_timer(&dev_priv->hangcheck_timer,
1027                                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1028                 }
1029
1030                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1031                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
1032
1033                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1034                         intel_prepare_page_flip(dev, 0);
1035                         if (dev_priv->flip_pending_is_done)
1036                                 intel_finish_page_flip_plane(dev, 0);
1037                 }
1038
1039                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1040                         intel_prepare_page_flip(dev, 1);
1041                         if (dev_priv->flip_pending_is_done)
1042                                 intel_finish_page_flip_plane(dev, 1);
1043                 }
1044
1045                 if (pipea_stats & vblank_status) {
1046                         vblank++;
1047                         drm_handle_vblank(dev, 0);
1048                         if (!dev_priv->flip_pending_is_done) {
1049                                 i915_pageflip_stall_check(dev, 0);
1050                                 intel_finish_page_flip(dev, 0);
1051                         }
1052                 }
1053
1054                 if (pipeb_stats & vblank_status) {
1055                         vblank++;
1056                         drm_handle_vblank(dev, 1);
1057                         if (!dev_priv->flip_pending_is_done) {
1058                                 i915_pageflip_stall_check(dev, 1);
1059                                 intel_finish_page_flip(dev, 1);
1060                         }
1061                 }
1062
1063                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1064                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1065                     (iir & I915_ASLE_INTERRUPT))
1066                         intel_opregion_asle_intr(dev);
1067
1068                 /* With MSI, interrupts are only generated when iir
1069                  * transitions from zero to nonzero.  If another bit got
1070                  * set while we were handling the existing iir bits, then
1071                  * we would never get another interrupt.
1072                  *
1073                  * This is fine on non-MSI as well, as if we hit this path
1074                  * we avoid exiting the interrupt handler only to generate
1075                  * another one.
1076                  *
1077                  * Note that for MSI this could cause a stray interrupt report
1078                  * if an interrupt landed in the time between writing IIR and
1079                  * the posting read.  This should be rare enough to never
1080                  * trigger the 99% of 100,000 interrupts test for disabling
1081                  * stray interrupts.
1082                  */
1083                 iir = new_iir;
1084         }
1085
1086         return ret;
1087 }
1088
1089 static int i915_emit_irq(struct drm_device * dev)
1090 {
1091         drm_i915_private_t *dev_priv = dev->dev_private;
1092         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1093
1094         i915_kernel_lost_context(dev);
1095
1096         DRM_DEBUG_DRIVER("\n");
1097
1098         dev_priv->counter++;
1099         if (dev_priv->counter > 0x7FFFFFFFUL)
1100                 dev_priv->counter = 1;
1101         if (master_priv->sarea_priv)
1102                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1103
1104         BEGIN_LP_RING(4);
1105         OUT_RING(MI_STORE_DWORD_INDEX);
1106         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1107         OUT_RING(dev_priv->counter);
1108         OUT_RING(MI_USER_INTERRUPT);
1109         ADVANCE_LP_RING();
1110
1111         return dev_priv->counter;
1112 }
1113
1114 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1115 {
1116         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1117         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1118
1119         if (dev_priv->trace_irq_seqno == 0)
1120                 render_ring->user_irq_get(dev, render_ring);
1121
1122         dev_priv->trace_irq_seqno = seqno;
1123 }
1124
1125 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1126 {
1127         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1128         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1129         int ret = 0;
1130         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1131
1132         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1133                   READ_BREADCRUMB(dev_priv));
1134
1135         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1136                 if (master_priv->sarea_priv)
1137                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1138                 return 0;
1139         }
1140
1141         if (master_priv->sarea_priv)
1142                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1143
1144         render_ring->user_irq_get(dev, render_ring);
1145         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1146                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1147         render_ring->user_irq_put(dev, render_ring);
1148
1149         if (ret == -EBUSY) {
1150                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1151                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1152         }
1153
1154         return ret;
1155 }
1156
1157 /* Needs the lock as it touches the ring.
1158  */
1159 int i915_irq_emit(struct drm_device *dev, void *data,
1160                          struct drm_file *file_priv)
1161 {
1162         drm_i915_private_t *dev_priv = dev->dev_private;
1163         drm_i915_irq_emit_t *emit = data;
1164         int result;
1165
1166         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1167                 DRM_ERROR("called with no initialization\n");
1168                 return -EINVAL;
1169         }
1170
1171         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1172
1173         mutex_lock(&dev->struct_mutex);
1174         result = i915_emit_irq(dev);
1175         mutex_unlock(&dev->struct_mutex);
1176
1177         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1178                 DRM_ERROR("copy_to_user\n");
1179                 return -EFAULT;
1180         }
1181
1182         return 0;
1183 }
1184
1185 /* Doesn't need the hardware lock.
1186  */
1187 int i915_irq_wait(struct drm_device *dev, void *data,
1188                          struct drm_file *file_priv)
1189 {
1190         drm_i915_private_t *dev_priv = dev->dev_private;
1191         drm_i915_irq_wait_t *irqwait = data;
1192
1193         if (!dev_priv) {
1194                 DRM_ERROR("called with no initialization\n");
1195                 return -EINVAL;
1196         }
1197
1198         return i915_wait_irq(dev, irqwait->irq_seq);
1199 }
1200
1201 /* Called from drm generic code, passed 'crtc' which
1202  * we use as a pipe index
1203  */
1204 int i915_enable_vblank(struct drm_device *dev, int pipe)
1205 {
1206         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1207         unsigned long irqflags;
1208
1209         if (!i915_pipe_enabled(dev, pipe))
1210                 return -EINVAL;
1211
1212         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1213         if (HAS_PCH_SPLIT(dev))
1214                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1215                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1216         else if (INTEL_INFO(dev)->gen >= 4)
1217                 i915_enable_pipestat(dev_priv, pipe,
1218                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1219         else
1220                 i915_enable_pipestat(dev_priv, pipe,
1221                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1222         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1223         return 0;
1224 }
1225
1226 /* Called from drm generic code, passed 'crtc' which
1227  * we use as a pipe index
1228  */
1229 void i915_disable_vblank(struct drm_device *dev, int pipe)
1230 {
1231         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1232         unsigned long irqflags;
1233
1234         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1235         if (HAS_PCH_SPLIT(dev))
1236                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1237                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1238         else
1239                 i915_disable_pipestat(dev_priv, pipe,
1240                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1241                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1242         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1243 }
1244
1245 void i915_enable_interrupt (struct drm_device *dev)
1246 {
1247         struct drm_i915_private *dev_priv = dev->dev_private;
1248
1249         if (!HAS_PCH_SPLIT(dev))
1250                 intel_opregion_enable_asle(dev);
1251         dev_priv->irq_enabled = 1;
1252 }
1253
1254
1255 /* Set the vblank monitor pipe
1256  */
1257 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1258                          struct drm_file *file_priv)
1259 {
1260         drm_i915_private_t *dev_priv = dev->dev_private;
1261
1262         if (!dev_priv) {
1263                 DRM_ERROR("called with no initialization\n");
1264                 return -EINVAL;
1265         }
1266
1267         return 0;
1268 }
1269
1270 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1271                          struct drm_file *file_priv)
1272 {
1273         drm_i915_private_t *dev_priv = dev->dev_private;
1274         drm_i915_vblank_pipe_t *pipe = data;
1275
1276         if (!dev_priv) {
1277                 DRM_ERROR("called with no initialization\n");
1278                 return -EINVAL;
1279         }
1280
1281         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1282
1283         return 0;
1284 }
1285
1286 /**
1287  * Schedule buffer swap at given vertical blank.
1288  */
1289 int i915_vblank_swap(struct drm_device *dev, void *data,
1290                      struct drm_file *file_priv)
1291 {
1292         /* The delayed swap mechanism was fundamentally racy, and has been
1293          * removed.  The model was that the client requested a delayed flip/swap
1294          * from the kernel, then waited for vblank before continuing to perform
1295          * rendering.  The problem was that the kernel might wake the client
1296          * up before it dispatched the vblank swap (since the lock has to be
1297          * held while touching the ringbuffer), in which case the client would
1298          * clear and start the next frame before the swap occurred, and
1299          * flicker would occur in addition to likely missing the vblank.
1300          *
1301          * In the absence of this ioctl, userland falls back to a correct path
1302          * of waiting for a vblank, then dispatching the swap on its own.
1303          * Context switching to userland and back is plenty fast enough for
1304          * meeting the requirements of vblank swapping.
1305          */
1306         return -EINVAL;
1307 }
1308
1309 static struct drm_i915_gem_request *
1310 i915_get_tail_request(struct drm_device *dev)
1311 {
1312         drm_i915_private_t *dev_priv = dev->dev_private;
1313         return list_entry(dev_priv->render_ring.request_list.prev,
1314                         struct drm_i915_gem_request, list);
1315 }
1316
1317 /**
1318  * This is called when the chip hasn't reported back with completed
1319  * batchbuffers in a long time. The first time this is called we simply record
1320  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1321  * again, we assume the chip is wedged and try to fix it.
1322  */
1323 void i915_hangcheck_elapsed(unsigned long data)
1324 {
1325         struct drm_device *dev = (struct drm_device *)data;
1326         drm_i915_private_t *dev_priv = dev->dev_private;
1327         uint32_t acthd, instdone, instdone1;
1328
1329         if (INTEL_INFO(dev)->gen < 4) {
1330                 acthd = I915_READ(ACTHD);
1331                 instdone = I915_READ(INSTDONE);
1332                 instdone1 = 0;
1333         } else {
1334                 acthd = I915_READ(ACTHD_I965);
1335                 instdone = I915_READ(INSTDONE_I965);
1336                 instdone1 = I915_READ(INSTDONE1);
1337         }
1338
1339         /* If all work is done then ACTHD clearly hasn't advanced. */
1340         if (list_empty(&dev_priv->render_ring.request_list) ||
1341                 i915_seqno_passed(dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring),
1342                                   i915_get_tail_request(dev)->seqno)) {
1343                 bool missed_wakeup = false;
1344
1345                 dev_priv->hangcheck_count = 0;
1346
1347                 /* Issue a wake-up to catch stuck h/w. */
1348                 if (dev_priv->render_ring.waiting_gem_seqno &&
1349                     waitqueue_active(&dev_priv->render_ring.irq_queue)) {
1350                         wake_up_all(&dev_priv->render_ring.irq_queue);
1351                         missed_wakeup = true;
1352                 }
1353
1354                 if (dev_priv->bsd_ring.waiting_gem_seqno &&
1355                     waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
1356                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
1357                         missed_wakeup = true;
1358                 }
1359
1360                 if (missed_wakeup)
1361                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1362                 return;
1363         }
1364
1365         if (dev_priv->last_acthd == acthd &&
1366             dev_priv->last_instdone == instdone &&
1367             dev_priv->last_instdone1 == instdone1) {
1368                 if (dev_priv->hangcheck_count++ > 1) {
1369                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1370
1371                         if (!IS_GEN2(dev)) {
1372                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1373                                  * If so we can simply poke the RB_WAIT bit
1374                                  * and break the hang. This should work on
1375                                  * all but the second generation chipsets.
1376                                  */
1377                                 u32 tmp = I915_READ(PRB0_CTL);
1378                                 if (tmp & RING_WAIT) {
1379                                         I915_WRITE(PRB0_CTL, tmp);
1380                                         POSTING_READ(PRB0_CTL);
1381                                         goto out;
1382                                 }
1383                         }
1384
1385                         i915_handle_error(dev, true);
1386                         return;
1387                 }
1388         } else {
1389                 dev_priv->hangcheck_count = 0;
1390
1391                 dev_priv->last_acthd = acthd;
1392                 dev_priv->last_instdone = instdone;
1393                 dev_priv->last_instdone1 = instdone1;
1394         }
1395
1396 out:
1397         /* Reset timer case chip hangs without another request being added */
1398         mod_timer(&dev_priv->hangcheck_timer,
1399                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1400 }
1401
1402 /* drm_dma.h hooks
1403 */
1404 static void ironlake_irq_preinstall(struct drm_device *dev)
1405 {
1406         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1407
1408         I915_WRITE(HWSTAM, 0xeffe);
1409
1410         /* XXX hotplug from PCH */
1411
1412         I915_WRITE(DEIMR, 0xffffffff);
1413         I915_WRITE(DEIER, 0x0);
1414         (void) I915_READ(DEIER);
1415
1416         /* and GT */
1417         I915_WRITE(GTIMR, 0xffffffff);
1418         I915_WRITE(GTIER, 0x0);
1419         (void) I915_READ(GTIER);
1420
1421         /* south display irq */
1422         I915_WRITE(SDEIMR, 0xffffffff);
1423         I915_WRITE(SDEIER, 0x0);
1424         (void) I915_READ(SDEIER);
1425 }
1426
1427 static int ironlake_irq_postinstall(struct drm_device *dev)
1428 {
1429         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1430         /* enable kind of interrupts always enabled */
1431         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1432                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1433         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1434         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1435                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1436
1437         dev_priv->irq_mask_reg = ~display_mask;
1438         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1439
1440         /* should always can generate irq */
1441         I915_WRITE(DEIIR, I915_READ(DEIIR));
1442         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1443         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1444         (void) I915_READ(DEIER);
1445
1446         if (IS_GEN6(dev))
1447                 render_mask = GT_PIPE_NOTIFY | GT_GEN6_BSD_USER_INTERRUPT;
1448
1449         dev_priv->gt_irq_mask_reg = ~render_mask;
1450         dev_priv->gt_irq_enable_reg = render_mask;
1451
1452         I915_WRITE(GTIIR, I915_READ(GTIIR));
1453         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1454         if (IS_GEN6(dev)) {
1455                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1456                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1457         }
1458
1459         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1460         (void) I915_READ(GTIER);
1461
1462         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1463         dev_priv->pch_irq_enable_reg = hotplug_mask;
1464
1465         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1466         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1467         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1468         (void) I915_READ(SDEIER);
1469
1470         if (IS_IRONLAKE_M(dev)) {
1471                 /* Clear & enable PCU event interrupts */
1472                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1473                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1474                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1475         }
1476
1477         return 0;
1478 }
1479
1480 void i915_driver_irq_preinstall(struct drm_device * dev)
1481 {
1482         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1483
1484         atomic_set(&dev_priv->irq_received, 0);
1485
1486         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1487         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1488
1489         if (HAS_PCH_SPLIT(dev)) {
1490                 ironlake_irq_preinstall(dev);
1491                 return;
1492         }
1493
1494         if (I915_HAS_HOTPLUG(dev)) {
1495                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1496                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1497         }
1498
1499         I915_WRITE(HWSTAM, 0xeffe);
1500         I915_WRITE(PIPEASTAT, 0);
1501         I915_WRITE(PIPEBSTAT, 0);
1502         I915_WRITE(IMR, 0xffffffff);
1503         I915_WRITE(IER, 0x0);
1504         (void) I915_READ(IER);
1505 }
1506
1507 /*
1508  * Must be called after intel_modeset_init or hotplug interrupts won't be
1509  * enabled correctly.
1510  */
1511 int i915_driver_irq_postinstall(struct drm_device *dev)
1512 {
1513         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1514         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1515         u32 error_mask;
1516
1517         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1518
1519         if (HAS_BSD(dev))
1520                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1521
1522         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1523
1524         if (HAS_PCH_SPLIT(dev))
1525                 return ironlake_irq_postinstall(dev);
1526
1527         /* Unmask the interrupts that we always want on. */
1528         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1529
1530         dev_priv->pipestat[0] = 0;
1531         dev_priv->pipestat[1] = 0;
1532
1533         if (I915_HAS_HOTPLUG(dev)) {
1534                 /* Enable in IER... */
1535                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1536                 /* and unmask in IMR */
1537                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1538         }
1539
1540         /*
1541          * Enable some error detection, note the instruction error mask
1542          * bit is reserved, so we leave it masked.
1543          */
1544         if (IS_G4X(dev)) {
1545                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1546                                GM45_ERROR_MEM_PRIV |
1547                                GM45_ERROR_CP_PRIV |
1548                                I915_ERROR_MEMORY_REFRESH);
1549         } else {
1550                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1551                                I915_ERROR_MEMORY_REFRESH);
1552         }
1553         I915_WRITE(EMR, error_mask);
1554
1555         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1556         I915_WRITE(IER, enable_mask);
1557         (void) I915_READ(IER);
1558
1559         if (I915_HAS_HOTPLUG(dev)) {
1560                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1561
1562                 /* Note HDMI and DP share bits */
1563                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1564                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1565                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1566                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1567                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1568                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1569                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1570                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1571                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1572                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1573                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1574                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1575
1576                         /* Programming the CRT detection parameters tends
1577                            to generate a spurious hotplug event about three
1578                            seconds later.  So just do it once.
1579                         */
1580                         if (IS_G4X(dev))
1581                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1582                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1583                 }
1584
1585                 /* Ignore TV since it's buggy */
1586
1587                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1588         }
1589
1590         intel_opregion_enable_asle(dev);
1591
1592         return 0;
1593 }
1594
1595 static void ironlake_irq_uninstall(struct drm_device *dev)
1596 {
1597         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1598         I915_WRITE(HWSTAM, 0xffffffff);
1599
1600         I915_WRITE(DEIMR, 0xffffffff);
1601         I915_WRITE(DEIER, 0x0);
1602         I915_WRITE(DEIIR, I915_READ(DEIIR));
1603
1604         I915_WRITE(GTIMR, 0xffffffff);
1605         I915_WRITE(GTIER, 0x0);
1606         I915_WRITE(GTIIR, I915_READ(GTIIR));
1607 }
1608
1609 void i915_driver_irq_uninstall(struct drm_device * dev)
1610 {
1611         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1612
1613         if (!dev_priv)
1614                 return;
1615
1616         dev_priv->vblank_pipe = 0;
1617
1618         if (HAS_PCH_SPLIT(dev)) {
1619                 ironlake_irq_uninstall(dev);
1620                 return;
1621         }
1622
1623         if (I915_HAS_HOTPLUG(dev)) {
1624                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1625                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1626         }
1627
1628         I915_WRITE(HWSTAM, 0xffffffff);
1629         I915_WRITE(PIPEASTAT, 0);
1630         I915_WRITE(PIPEBSTAT, 0);
1631         I915_WRITE(IMR, 0xffffffff);
1632         I915_WRITE(IER, 0x0);
1633
1634         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1635         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1636         I915_WRITE(IIR, I915_READ(IIR));
1637 }