2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "linux/string.h"
29 #include "linux/bitops.h"
35 /** @file i915_gem_tiling.c
37 * Support for managing tiling state of buffer objects.
39 * The idea behind tiling is to increase cache hit rates by rearranging
40 * pixel data so that a group of pixel accesses are in the same cacheline.
41 * Performance improvement from doing this on the back/depth buffer are on
44 * Intel architectures make this somewhat more complicated, though, by
45 * adjustments made to addressing of data when the memory is in interleaved
46 * mode (matched pairs of DIMMS) to improve memory bandwidth.
47 * For interleaved memory, the CPU sends every sequential 64 bytes
48 * to an alternate memory channel so it can get the bandwidth from both.
50 * The GPU also rearranges its accesses for increased bandwidth to interleaved
51 * memory, and it matches what the CPU does for non-tiled. However, when tiled
52 * it does it a little differently, since one walks addresses not just in the
53 * X direction but also Y. So, along with alternating channels when bit
54 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
55 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
56 * are common to both the 915 and 965-class hardware.
58 * The CPU also sometimes XORs in higher bits as well, to improve
59 * bandwidth doing strided access like we do so frequently in graphics. This
60 * is called "Channel XOR Randomization" in the MCH documentation. The result
61 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
64 * All of this bit 6 XORing has an effect on our memory management,
65 * as we need to make sure that the 3d driver can correctly address object
68 * If we don't have interleaved memory, all tiling is safe and no swizzling is
71 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
72 * 17 is not just a page offset, so as we page an objet out and back in,
73 * individual pages in it will have different bit 17 addresses, resulting in
74 * each 64 bytes being swapped with its neighbor!
76 * Otherwise, if interleaved, we have to tell the 3d driver what the address
77 * swizzling it needs to do is, since it's writing with the CPU to the pages
78 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
79 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
80 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
81 * to match what the GPU expects.
85 * Detects bit 6 swizzling of address lookup between IGD access and CPU
86 * access through main memory.
89 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
91 drm_i915_private_t *dev_priv = dev->dev_private;
92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
95 if (IS_IRONLAKE(dev)) {
96 /* On Ironlake whatever DRAM config, GPU always do
97 * same swizzling setup.
99 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
100 swizzle_y = I915_BIT_6_SWIZZLE_9;
101 } else if (!IS_I9XX(dev)) {
102 /* As far as we know, the 865 doesn't have these bit 6
105 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
106 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
107 } else if (IS_MOBILE(dev)) {
110 /* On mobile 9xx chipsets, channel interleave by the CPU is
111 * determined by DCC. For single-channel, neither the CPU
112 * nor the GPU do swizzling. For dual channel interleaved,
113 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
114 * 9 for Y tiled. The CPU's interleave is independent, and
115 * can be based on either bit 11 (haven't seen this yet) or
118 dcc = I915_READ(DCC);
119 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
120 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
121 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
122 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
123 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
125 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
126 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
127 /* This is the base swizzling by the GPU for
130 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
131 swizzle_y = I915_BIT_6_SWIZZLE_9;
132 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
133 /* Bit 11 swizzling by the CPU in addition. */
134 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
135 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
137 /* Bit 17 swizzling by the CPU in addition. */
138 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
139 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
143 if (dcc == 0xffffffff) {
144 DRM_ERROR("Couldn't read from MCHBAR. "
145 "Disabling tiling.\n");
146 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
147 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
150 /* The 965, G33, and newer, have a very flexible memory
151 * configuration. It will enable dual-channel mode
152 * (interleaving) on as much memory as it can, and the GPU
153 * will additionally sometimes enable different bit 6
154 * swizzling for tiled objects from the CPU.
156 * Here's what I found on the G965:
157 * slot fill memory size swizzling
158 * 0A 0B 1A 1B 1-ch 2-ch
160 * 512 0 512 0 16 1008 X
161 * 512 0 0 512 16 1008 X
162 * 0 512 0 512 16 1008 X
163 * 1024 1024 1024 0 2048 1024 O
165 * We could probably detect this based on either the DRB
166 * matching, which was the case for the swizzling required in
167 * the table above, or from the 1-ch value being less than
168 * the minimum size of a rank.
170 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
171 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
172 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
174 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
175 swizzle_y = I915_BIT_6_SWIZZLE_9;
179 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
180 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
185 * Returns whether an object is currently fenceable. If not, it may need
186 * to be unbound and have its pitch adjusted.
189 i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj)
191 struct drm_i915_gem_object *obj_priv = obj->driver_private;
194 /* The 965 can have fences at any page boundary. */
195 if (obj->size & 4095)
198 } else if (IS_I9XX(dev)) {
199 if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
202 if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
206 /* Power of two sized... */
207 if (obj->size & (obj->size - 1))
210 /* Objects must be size aligned as well */
211 if (obj_priv->gtt_offset & (obj->size - 1))
216 /* Check pitch constriants for all chips & tiling formats */
218 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
222 /* Linear is always fine */
223 if (tiling_mode == I915_TILING_NONE)
227 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
232 /* check maximum stride & object size */
234 /* i965 stores the end address of the gtt mapping in the fence
235 * reg, so dont bother to check the size */
236 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
238 } else if (IS_I9XX(dev)) {
239 uint32_t pitch_val = ffs(stride / tile_width) - 1;
241 /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB)
242 * instead of 4 (2KB) on 945s.
244 if (pitch_val > I915_FENCE_MAX_PITCH_VAL ||
245 size > (I830_FENCE_MAX_SIZE_VAL << 20))
248 uint32_t pitch_val = ffs(stride / tile_width) - 1;
250 if (pitch_val > I830_FENCE_MAX_PITCH_VAL ||
251 size > (I830_FENCE_MAX_SIZE_VAL << 19))
255 /* 965+ just needs multiples of tile width */
257 if (stride & (tile_width - 1))
262 /* Pre-965 needs power of two tile widths */
263 if (stride < tile_width)
266 if (stride & (stride - 1))
273 i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode)
275 struct drm_device *dev = obj->dev;
276 struct drm_i915_gem_object *obj_priv = obj->driver_private;
278 if (obj_priv->gtt_space == NULL)
281 if (tiling_mode == I915_TILING_NONE)
284 if (!IS_I965G(dev)) {
285 if (obj_priv->gtt_offset & (obj->size - 1))
288 if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
291 if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
300 * Sets the tiling mode of an object, returning the required swizzling of
301 * bit 6 of addresses in the object.
304 i915_gem_set_tiling(struct drm_device *dev, void *data,
305 struct drm_file *file_priv)
307 struct drm_i915_gem_set_tiling *args = data;
308 drm_i915_private_t *dev_priv = dev->dev_private;
309 struct drm_gem_object *obj;
310 struct drm_i915_gem_object *obj_priv;
313 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
316 obj_priv = obj->driver_private;
318 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
319 mutex_lock(&dev->struct_mutex);
320 drm_gem_object_unreference(obj);
321 mutex_unlock(&dev->struct_mutex);
325 if (args->tiling_mode == I915_TILING_NONE) {
326 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
329 if (args->tiling_mode == I915_TILING_X)
330 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
332 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
334 /* Hide bit 17 swizzling from the user. This prevents old Mesa
335 * from aborting the application on sw fallbacks to bit 17,
336 * and we use the pread/pwrite bit17 paths to swizzle for it.
337 * If there was a user that was relying on the swizzle
338 * information for drm_intel_bo_map()ed reads/writes this would
339 * break it, but we don't have any of those.
341 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
342 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
343 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
344 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
346 /* If we can't handle the swizzling, make it untiled. */
347 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
348 args->tiling_mode = I915_TILING_NONE;
349 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
354 mutex_lock(&dev->struct_mutex);
355 if (args->tiling_mode != obj_priv->tiling_mode ||
356 args->stride != obj_priv->stride) {
357 /* We need to rebind the object if its current allocation
358 * no longer meets the alignment restrictions for its new
359 * tiling mode. Otherwise we can just leave it alone, but
360 * need to ensure that any fence register is cleared.
362 if (!i915_gem_object_fence_offset_ok(obj, args->tiling_mode))
363 ret = i915_gem_object_unbind(obj);
365 ret = i915_gem_object_put_fence_reg(obj);
367 WARN(ret != -ERESTARTSYS,
368 "failed to reset object for tiling switch");
369 args->tiling_mode = obj_priv->tiling_mode;
370 args->stride = obj_priv->stride;
374 obj_priv->tiling_mode = args->tiling_mode;
375 obj_priv->stride = args->stride;
378 drm_gem_object_unreference(obj);
379 mutex_unlock(&dev->struct_mutex);
385 * Returns the current tiling mode and required bit 6 swizzling for the object.
388 i915_gem_get_tiling(struct drm_device *dev, void *data,
389 struct drm_file *file_priv)
391 struct drm_i915_gem_get_tiling *args = data;
392 drm_i915_private_t *dev_priv = dev->dev_private;
393 struct drm_gem_object *obj;
394 struct drm_i915_gem_object *obj_priv;
396 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
399 obj_priv = obj->driver_private;
401 mutex_lock(&dev->struct_mutex);
403 args->tiling_mode = obj_priv->tiling_mode;
404 switch (obj_priv->tiling_mode) {
406 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
409 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
411 case I915_TILING_NONE:
412 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
415 DRM_ERROR("unknown tiling mode\n");
418 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
419 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
420 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
421 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
422 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
424 drm_gem_object_unreference(obj);
425 mutex_unlock(&dev->struct_mutex);
431 * Swap every 64 bytes of this page around, to account for it having a new
432 * bit 17 of its physical address and therefore being interpreted differently
436 i915_gem_swizzle_page(struct page *page)
446 for (i = 0; i < PAGE_SIZE; i += 128) {
447 memcpy(temp, &vaddr[i], 64);
448 memcpy(&vaddr[i], &vaddr[i + 64], 64);
449 memcpy(&vaddr[i + 64], temp, 64);
458 i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj)
460 struct drm_device *dev = obj->dev;
461 drm_i915_private_t *dev_priv = dev->dev_private;
462 struct drm_i915_gem_object *obj_priv = obj->driver_private;
463 int page_count = obj->size >> PAGE_SHIFT;
466 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
469 if (obj_priv->bit_17 == NULL)
472 for (i = 0; i < page_count; i++) {
473 char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17;
474 if ((new_bit_17 & 0x1) !=
475 (test_bit(i, obj_priv->bit_17) != 0)) {
476 int ret = i915_gem_swizzle_page(obj_priv->pages[i]);
478 DRM_ERROR("Failed to swizzle page\n");
481 set_page_dirty(obj_priv->pages[i]);
487 i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj)
489 struct drm_device *dev = obj->dev;
490 drm_i915_private_t *dev_priv = dev->dev_private;
491 struct drm_i915_gem_object *obj_priv = obj->driver_private;
492 int page_count = obj->size >> PAGE_SHIFT;
495 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
498 if (obj_priv->bit_17 == NULL) {
499 obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
500 sizeof(long), GFP_KERNEL);
501 if (obj_priv->bit_17 == NULL) {
502 DRM_ERROR("Failed to allocate memory for bit 17 "
508 for (i = 0; i < page_count; i++) {
509 if (page_to_phys(obj_priv->pages[i]) & (1 << 17))
510 __set_bit(i, obj_priv->bit_17);
512 __clear_bit(i, obj_priv->bit_17);