drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  42                                              int write);
  43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  44                                                      uint64_t offset,
  45                                                      uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  49                                            unsigned alignment);
  50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  51 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
  52 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
  53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file_priv);
  56 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  57
  58 static LIST_HEAD(shrink_list);
  59 static DEFINE_SPINLOCK(shrink_list_lock);
  60
  61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  62                      unsigned long end)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65
  66         if (start >= end ||
  67             (start & (PAGE_SIZE - 1)) != 0 ||
  68             (end & (PAGE_SIZE - 1)) != 0) {
  69                 return -EINVAL;
  70         }
  71
  72         drm_mm_init(&dev_priv->mm.gtt_space, start,
  73                     end - start);
  74
  75         dev->gtt_total = (uint32_t) (end - start);
  76
  77         return 0;
  78 }
  79
  80 int
  81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  82                     struct drm_file *file_priv)
  83 {
  84         struct drm_i915_gem_init *args = data;
  85         int ret;
  86
  87         mutex_lock(&dev->struct_mutex);
  88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  89         mutex_unlock(&dev->struct_mutex);
  90
  91         return ret;
  92 }
  93
  94 int
  95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  96                             struct drm_file *file_priv)
  97 {
  98         struct drm_i915_gem_get_aperture *args = data;
  99
 100         if (!(dev->driver->driver_features & DRIVER_GEM))
 101                 return -ENODEV;
 102
 103         args->aper_size = dev->gtt_total;
 104         args->aper_available_size = (args->aper_size -
 105                                      atomic_read(&dev->pin_memory));
 106
 107         return 0;
 108 }
 109
 110
 111 /**
 112  * Creates a new mm object and returns a handle to it.
 113  */
 114 int
 115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 116                       struct drm_file *file_priv)
 117 {
 118         struct drm_i915_gem_create *args = data;
 119         struct drm_gem_object *obj;
 120         int ret;
 121         u32 handle;
 122
 123         args->size = roundup(args->size, PAGE_SIZE);
 124
 125         /* Allocate the new object */
 126         obj = i915_gem_alloc_object(dev, args->size);
 127         if (obj == NULL)
 128                 return -ENOMEM;
 129
 130         ret = drm_gem_handle_create(file_priv, obj, &handle);
 131         drm_gem_object_unreference_unlocked(obj);
 132         if (ret)
 133                 return ret;
 134
 135         args->handle = handle;
 136
 137         return 0;
 138 }
 139
 140 static inline int
 141 fast_shmem_read(struct page **pages,
 142                 loff_t page_base, int page_offset,
 143                 char __user *data,
 144                 int length)
 145 {
 146         char __iomem *vaddr;
 147         int unwritten;
 148
 149         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 150         if (vaddr == NULL)
 151                 return -ENOMEM;
 152         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 153         kunmap_atomic(vaddr, KM_USER0);
 154
 155         if (unwritten)
 156                 return -EFAULT;
 157
 158         return 0;
 159 }
 160
 161 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 162 {
 163         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 164         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 165
 166         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 167                 obj_priv->tiling_mode != I915_TILING_NONE;
 168 }
 169
 170 static inline void
 171 slow_shmem_copy(struct page *dst_page,
 172                 int dst_offset,
 173                 struct page *src_page,
 174                 int src_offset,
 175                 int length)
 176 {
 177         char *dst_vaddr, *src_vaddr;
 178
 179         dst_vaddr = kmap(dst_page);
 180         src_vaddr = kmap(src_page);
 181
 182         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 183
 184         kunmap(src_page);
 185         kunmap(dst_page);
 186 }
 187
 188 static inline void
 189 slow_shmem_bit17_copy(struct page *gpu_page,
 190                       int gpu_offset,
 191                       struct page *cpu_page,
 192                       int cpu_offset,
 193                       int length,
 194                       int is_read)
 195 {
 196         char *gpu_vaddr, *cpu_vaddr;
 197
 198         /* Use the unswizzled path if this page isn't affected. */
 199         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 200                 if (is_read)
 201                         return slow_shmem_copy(cpu_page, cpu_offset,
 202                                                gpu_page, gpu_offset, length);
 203                 else
 204                         return slow_shmem_copy(gpu_page, gpu_offset,
 205                                                cpu_page, cpu_offset, length);
 206         }
 207
 208         gpu_vaddr = kmap(gpu_page);
 209         cpu_vaddr = kmap(cpu_page);
 210
 211         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 212          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 213          */
 214         while (length > 0) {
 215                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 216                 int this_length = min(cacheline_end - gpu_offset, length);
 217                 int swizzled_gpu_offset = gpu_offset ^ 64;
 218
 219                 if (is_read) {
 220                         memcpy(cpu_vaddr + cpu_offset,
 221                                gpu_vaddr + swizzled_gpu_offset,
 222                                this_length);
 223                 } else {
 224                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 225                                cpu_vaddr + cpu_offset,
 226                                this_length);
 227                 }
 228                 cpu_offset += this_length;
 229                 gpu_offset += this_length;
 230                 length -= this_length;
 231         }
 232
 233         kunmap(cpu_page);
 234         kunmap(gpu_page);
 235 }
 236
 237 /**
 238  * This is the fast shmem pread path, which attempts to copy_from_user directly
 239  * from the backing pages of the object to the user's address space.  On a
 240  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 241  */
 242 static int
 243 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 244                           struct drm_i915_gem_pread *args,
 245                           struct drm_file *file_priv)
 246 {
 247         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 248         ssize_t remain;
 249         loff_t offset, page_base;
 250         char __user *user_data;
 251         int page_offset, page_length;
 252         int ret;
 253
 254         user_data = (char __user *) (uintptr_t) args->data_ptr;
 255         remain = args->size;
 256
 257         mutex_lock(&dev->struct_mutex);
 258
 259         ret = i915_gem_object_get_pages(obj, 0);
 260         if (ret != 0)
 261                 goto fail_unlock;
 262
 263         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 264                                                         args->size);
 265         if (ret != 0)
 266                 goto fail_put_pages;
 267
 268         obj_priv = to_intel_bo(obj);
 269         offset = args->offset;
 270
 271         while (remain > 0) {
 272                 /* Operation in this page
 273                  *
 274                  * page_base = page offset within aperture
 275                  * page_offset = offset within page
 276                  * page_length = bytes to copy for this page
 277                  */
 278                 page_base = (offset & ~(PAGE_SIZE-1));
 279                 page_offset = offset & (PAGE_SIZE-1);
 280                 page_length = remain;
 281                 if ((page_offset + remain) > PAGE_SIZE)
 282                         page_length = PAGE_SIZE - page_offset;
 283
 284                 ret = fast_shmem_read(obj_priv->pages,
 285                                       page_base, page_offset,
 286                                       user_data, page_length);
 287                 if (ret)
 288                         goto fail_put_pages;
 289
 290                 remain -= page_length;
 291                 user_data += page_length;
 292                 offset += page_length;
 293         }
 294
 295 fail_put_pages:
 296         i915_gem_object_put_pages(obj);
 297 fail_unlock:
 298         mutex_unlock(&dev->struct_mutex);
 299
 300         return ret;
 301 }
 302
 303 static int
 304 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 305 {
 306         int ret;
 307
 308         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 309
 310         /* If we've insufficient memory to map in the pages, attempt
 311          * to make some space by throwing out some old buffers.
 312          */
 313         if (ret == -ENOMEM) {
 314                 struct drm_device *dev = obj->dev;
 315
 316                 ret = i915_gem_evict_something(dev, obj->size);
 317                 if (ret)
 318                         return ret;
 319
 320                 ret = i915_gem_object_get_pages(obj, 0);
 321         }
 322
 323         return ret;
 324 }
 325
 326 /**
 327  * This is the fallback shmem pread path, which allocates temporary storage
 328  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 329  * can copy out of the object's backing pages while holding the struct mutex
 330  * and not take page faults.
 331  */
 332 static int
 333 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 334                           struct drm_i915_gem_pread *args,
 335                           struct drm_file *file_priv)
 336 {
 337         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 338         struct mm_struct *mm = current->mm;
 339         struct page **user_pages;
 340         ssize_t remain;
 341         loff_t offset, pinned_pages, i;
 342         loff_t first_data_page, last_data_page, num_pages;
 343         int shmem_page_index, shmem_page_offset;
 344         int data_page_index,  data_page_offset;
 345         int page_length;
 346         int ret;
 347         uint64_t data_ptr = args->data_ptr;
 348         int do_bit17_swizzling;
 349
 350         remain = args->size;
 351
 352         /* Pin the user pages containing the data.  We can't fault while
 353          * holding the struct mutex, yet we want to hold it while
 354          * dereferencing the user data.
 355          */
 356         first_data_page = data_ptr / PAGE_SIZE;
 357         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 358         num_pages = last_data_page - first_data_page + 1;
 359
 360         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 361         if (user_pages == NULL)
 362                 return -ENOMEM;
 363
 364         down_read(&mm->mmap_sem);
 365         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 366                                       num_pages, 1, 0, user_pages, NULL);
 367         up_read(&mm->mmap_sem);
 368         if (pinned_pages < num_pages) {
 369                 ret = -EFAULT;
 370                 goto fail_put_user_pages;
 371         }
 372
 373         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 374
 375         mutex_lock(&dev->struct_mutex);
 376
 377         ret = i915_gem_object_get_pages_or_evict(obj);
 378         if (ret)
 379                 goto fail_unlock;
 380
 381         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 382                                                         args->size);
 383         if (ret != 0)
 384                 goto fail_put_pages;
 385
 386         obj_priv = to_intel_bo(obj);
 387         offset = args->offset;
 388
 389         while (remain > 0) {
 390                 /* Operation in this page
 391                  *
 392                  * shmem_page_index = page number within shmem file
 393                  * shmem_page_offset = offset within page in shmem file
 394                  * data_page_index = page number in get_user_pages return
 395                  * data_page_offset = offset with data_page_index page.
 396                  * page_length = bytes to copy for this page
 397                  */
 398                 shmem_page_index = offset / PAGE_SIZE;
 399                 shmem_page_offset = offset & ~PAGE_MASK;
 400                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 401                 data_page_offset = data_ptr & ~PAGE_MASK;
 402
 403                 page_length = remain;
 404                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 405                         page_length = PAGE_SIZE - shmem_page_offset;
 406                 if ((data_page_offset + page_length) > PAGE_SIZE)
 407                         page_length = PAGE_SIZE - data_page_offset;
 408
 409                 if (do_bit17_swizzling) {
 410                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 411                                               shmem_page_offset,
 412                                               user_pages[data_page_index],
 413                                               data_page_offset,
 414                                               page_length,
 415                                               1);
 416                 } else {
 417                         slow_shmem_copy(user_pages[data_page_index],
 418                                         data_page_offset,
 419                                         obj_priv->pages[shmem_page_index],
 420                                         shmem_page_offset,
 421                                         page_length);
 422                 }
 423
 424                 remain -= page_length;
 425                 data_ptr += page_length;
 426                 offset += page_length;
 427         }
 428
 429 fail_put_pages:
 430         i915_gem_object_put_pages(obj);
 431 fail_unlock:
 432         mutex_unlock(&dev->struct_mutex);
 433 fail_put_user_pages:
 434         for (i = 0; i < pinned_pages; i++) {
 435                 SetPageDirty(user_pages[i]);
 436                 page_cache_release(user_pages[i]);
 437         }
 438         drm_free_large(user_pages);
 439
 440         return ret;
 441 }
 442
 443 /**
 444  * Reads data from the object referenced by handle.
 445  *
 446  * On error, the contents of *data are undefined.
 447  */
 448 int
 449 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 450                      struct drm_file *file_priv)
 451 {
 452         struct drm_i915_gem_pread *args = data;
 453         struct drm_gem_object *obj;
 454         struct drm_i915_gem_object *obj_priv;
 455         int ret;
 456
 457         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 458         if (obj == NULL)
 459                 return -EBADF;
 460         obj_priv = to_intel_bo(obj);
 461
 462         /* Bounds check source.
 463          *
 464          * XXX: This could use review for overflow issues...
 465          */
 466         if (args->offset > obj->size || args->size > obj->size ||
 467             args->offset + args->size > obj->size) {
 468                 drm_gem_object_unreference_unlocked(obj);
 469                 return -EINVAL;
 470         }
 471
 472         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 473                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 474         } else {
 475                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 476                 if (ret != 0)
 477                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 478                                                         file_priv);
 479         }
 480
 481         drm_gem_object_unreference_unlocked(obj);
 482
 483         return ret;
 484 }
 485
 486 /* This is the fast write path which cannot handle
 487  * page faults in the source data
 488  */
 489
 490 static inline int
 491 fast_user_write(struct io_mapping *mapping,
 492                 loff_t page_base, int page_offset,
 493                 char __user *user_data,
 494                 int length)
 495 {
 496         char *vaddr_atomic;
 497         unsigned long unwritten;
 498
 499         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
 500         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 501                                                       user_data, length);
 502         io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
 503         if (unwritten)
 504                 return -EFAULT;
 505         return 0;
 506 }
 507
 508 /* Here's the write path which can sleep for
 509  * page faults
 510  */
 511
 512 static inline void
 513 slow_kernel_write(struct io_mapping *mapping,
 514                   loff_t gtt_base, int gtt_offset,
 515                   struct page *user_page, int user_offset,
 516                   int length)
 517 {
 518         char __iomem *dst_vaddr;
 519         char *src_vaddr;
 520
 521         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 522         src_vaddr = kmap(user_page);
 523
 524         memcpy_toio(dst_vaddr + gtt_offset,
 525                     src_vaddr + user_offset,
 526                     length);
 527
 528         kunmap(user_page);
 529         io_mapping_unmap(dst_vaddr);
 530 }
 531
 532 static inline int
 533 fast_shmem_write(struct page **pages,
 534                  loff_t page_base, int page_offset,
 535                  char __user *data,
 536                  int length)
 537 {
 538         char __iomem *vaddr;
 539         unsigned long unwritten;
 540
 541         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 542         if (vaddr == NULL)
 543                 return -ENOMEM;
 544         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 545         kunmap_atomic(vaddr, KM_USER0);
 546
 547         if (unwritten)
 548                 return -EFAULT;
 549         return 0;
 550 }
 551
 552 /**
 553  * This is the fast pwrite path, where we copy the data directly from the
 554  * user into the GTT, uncached.
 555  */
 556 static int
 557 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 558                          struct drm_i915_gem_pwrite *args,
 559                          struct drm_file *file_priv)
 560 {
 561         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 562         drm_i915_private_t *dev_priv = dev->dev_private;
 563         ssize_t remain;
 564         loff_t offset, page_base;
 565         char __user *user_data;
 566         int page_offset, page_length;
 567         int ret;
 568
 569         user_data = (char __user *) (uintptr_t) args->data_ptr;
 570         remain = args->size;
 571         if (!access_ok(VERIFY_READ, user_data, remain))
 572                 return -EFAULT;
 573
 574
 575         mutex_lock(&dev->struct_mutex);
 576         ret = i915_gem_object_pin(obj, 0);
 577         if (ret) {
 578                 mutex_unlock(&dev->struct_mutex);
 579                 return ret;
 580         }
 581         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 582         if (ret)
 583                 goto fail;
 584
 585         obj_priv = to_intel_bo(obj);
 586         offset = obj_priv->gtt_offset + args->offset;
 587
 588         while (remain > 0) {
 589                 /* Operation in this page
 590                  *
 591                  * page_base = page offset within aperture
 592                  * page_offset = offset within page
 593                  * page_length = bytes to copy for this page
 594                  */
 595                 page_base = (offset & ~(PAGE_SIZE-1));
 596                 page_offset = offset & (PAGE_SIZE-1);
 597                 page_length = remain;
 598                 if ((page_offset + remain) > PAGE_SIZE)
 599                         page_length = PAGE_SIZE - page_offset;
 600
 601                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 602                                        page_offset, user_data, page_length);
 603
 604                 /* If we get a fault while copying data, then (presumably) our
 605                  * source page isn't available.  Return the error and we'll
 606                  * retry in the slow path.
 607                  */
 608                 if (ret)
 609                         goto fail;
 610
 611                 remain -= page_length;
 612                 user_data += page_length;
 613                 offset += page_length;
 614         }
 615
 616 fail:
 617         i915_gem_object_unpin(obj);
 618         mutex_unlock(&dev->struct_mutex);
 619
 620         return ret;
 621 }
 622
 623 /**
 624  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 625  * the memory and maps it using kmap_atomic for copying.
 626  *
 627  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 628  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 629  */
 630 static int
 631 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 632                          struct drm_i915_gem_pwrite *args,
 633                          struct drm_file *file_priv)
 634 {
 635         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 636         drm_i915_private_t *dev_priv = dev->dev_private;
 637         ssize_t remain;
 638         loff_t gtt_page_base, offset;
 639         loff_t first_data_page, last_data_page, num_pages;
 640         loff_t pinned_pages, i;
 641         struct page **user_pages;
 642         struct mm_struct *mm = current->mm;
 643         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 644         int ret;
 645         uint64_t data_ptr = args->data_ptr;
 646
 647         remain = args->size;
 648
 649         /* Pin the user pages containing the data.  We can't fault while
 650          * holding the struct mutex, and all of the pwrite implementations
 651          * want to hold it while dereferencing the user data.
 652          */
 653         first_data_page = data_ptr / PAGE_SIZE;
 654         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 655         num_pages = last_data_page - first_data_page + 1;
 656
 657         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 658         if (user_pages == NULL)
 659                 return -ENOMEM;
 660
 661         down_read(&mm->mmap_sem);
 662         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 663                                       num_pages, 0, 0, user_pages, NULL);
 664         up_read(&mm->mmap_sem);
 665         if (pinned_pages < num_pages) {
 666                 ret = -EFAULT;
 667                 goto out_unpin_pages;
 668         }
 669
 670         mutex_lock(&dev->struct_mutex);
 671         ret = i915_gem_object_pin(obj, 0);
 672         if (ret)
 673                 goto out_unlock;
 674
 675         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 676         if (ret)
 677                 goto out_unpin_object;
 678
 679         obj_priv = to_intel_bo(obj);
 680         offset = obj_priv->gtt_offset + args->offset;
 681
 682         while (remain > 0) {
 683                 /* Operation in this page
 684                  *
 685                  * gtt_page_base = page offset within aperture
 686                  * gtt_page_offset = offset within page in aperture
 687                  * data_page_index = page number in get_user_pages return
 688                  * data_page_offset = offset with data_page_index page.
 689                  * page_length = bytes to copy for this page
 690                  */
 691                 gtt_page_base = offset & PAGE_MASK;
 692                 gtt_page_offset = offset & ~PAGE_MASK;
 693                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 694                 data_page_offset = data_ptr & ~PAGE_MASK;
 695
 696                 page_length = remain;
 697                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 698                         page_length = PAGE_SIZE - gtt_page_offset;
 699                 if ((data_page_offset + page_length) > PAGE_SIZE)
 700                         page_length = PAGE_SIZE - data_page_offset;
 701
 702                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 703                                   gtt_page_base, gtt_page_offset,
 704                                   user_pages[data_page_index],
 705                                   data_page_offset,
 706                                   page_length);
 707
 708                 remain -= page_length;
 709                 offset += page_length;
 710                 data_ptr += page_length;
 711         }
 712
 713 out_unpin_object:
 714         i915_gem_object_unpin(obj);
 715 out_unlock:
 716         mutex_unlock(&dev->struct_mutex);
 717 out_unpin_pages:
 718         for (i = 0; i < pinned_pages; i++)
 719                 page_cache_release(user_pages[i]);
 720         drm_free_large(user_pages);
 721
 722         return ret;
 723 }
 724
 725 /**
 726  * This is the fast shmem pwrite path, which attempts to directly
 727  * copy_from_user into the kmapped pages backing the object.
 728  */
 729 static int
 730 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 731                            struct drm_i915_gem_pwrite *args,
 732                            struct drm_file *file_priv)
 733 {
 734         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 735         ssize_t remain;
 736         loff_t offset, page_base;
 737         char __user *user_data;
 738         int page_offset, page_length;
 739         int ret;
 740
 741         user_data = (char __user *) (uintptr_t) args->data_ptr;
 742         remain = args->size;
 743
 744         mutex_lock(&dev->struct_mutex);
 745
 746         ret = i915_gem_object_get_pages(obj, 0);
 747         if (ret != 0)
 748                 goto fail_unlock;
 749
 750         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 751         if (ret != 0)
 752                 goto fail_put_pages;
 753
 754         obj_priv = to_intel_bo(obj);
 755         offset = args->offset;
 756         obj_priv->dirty = 1;
 757
 758         while (remain > 0) {
 759                 /* Operation in this page
 760                  *
 761                  * page_base = page offset within aperture
 762                  * page_offset = offset within page
 763                  * page_length = bytes to copy for this page
 764                  */
 765                 page_base = (offset & ~(PAGE_SIZE-1));
 766                 page_offset = offset & (PAGE_SIZE-1);
 767                 page_length = remain;
 768                 if ((page_offset + remain) > PAGE_SIZE)
 769                         page_length = PAGE_SIZE - page_offset;
 770
 771                 ret = fast_shmem_write(obj_priv->pages,
 772                                        page_base, page_offset,
 773                                        user_data, page_length);
 774                 if (ret)
 775                         goto fail_put_pages;
 776
 777                 remain -= page_length;
 778                 user_data += page_length;
 779                 offset += page_length;
 780         }
 781
 782 fail_put_pages:
 783         i915_gem_object_put_pages(obj);
 784 fail_unlock:
 785         mutex_unlock(&dev->struct_mutex);
 786
 787         return ret;
 788 }
 789
 790 /**
 791  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 792  * the memory and maps it using kmap_atomic for copying.
 793  *
 794  * This avoids taking mmap_sem for faulting on the user's address while the
 795  * struct_mutex is held.
 796  */
 797 static int
 798 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 799                            struct drm_i915_gem_pwrite *args,
 800                            struct drm_file *file_priv)
 801 {
 802         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 803         struct mm_struct *mm = current->mm;
 804         struct page **user_pages;
 805         ssize_t remain;
 806         loff_t offset, pinned_pages, i;
 807         loff_t first_data_page, last_data_page, num_pages;
 808         int shmem_page_index, shmem_page_offset;
 809         int data_page_index,  data_page_offset;
 810         int page_length;
 811         int ret;
 812         uint64_t data_ptr = args->data_ptr;
 813         int do_bit17_swizzling;
 814
 815         remain = args->size;
 816
 817         /* Pin the user pages containing the data.  We can't fault while
 818          * holding the struct mutex, and all of the pwrite implementations
 819          * want to hold it while dereferencing the user data.
 820          */
 821         first_data_page = data_ptr / PAGE_SIZE;
 822         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 823         num_pages = last_data_page - first_data_page + 1;
 824
 825         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 826         if (user_pages == NULL)
 827                 return -ENOMEM;
 828
 829         down_read(&mm->mmap_sem);
 830         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 831                                       num_pages, 0, 0, user_pages, NULL);
 832         up_read(&mm->mmap_sem);
 833         if (pinned_pages < num_pages) {
 834                 ret = -EFAULT;
 835                 goto fail_put_user_pages;
 836         }
 837
 838         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 839
 840         mutex_lock(&dev->struct_mutex);
 841
 842         ret = i915_gem_object_get_pages_or_evict(obj);
 843         if (ret)
 844                 goto fail_unlock;
 845
 846         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 847         if (ret != 0)
 848                 goto fail_put_pages;
 849
 850         obj_priv = to_intel_bo(obj);
 851         offset = args->offset;
 852         obj_priv->dirty = 1;
 853
 854         while (remain > 0) {
 855                 /* Operation in this page
 856                  *
 857                  * shmem_page_index = page number within shmem file
 858                  * shmem_page_offset = offset within page in shmem file
 859                  * data_page_index = page number in get_user_pages return
 860                  * data_page_offset = offset with data_page_index page.
 861                  * page_length = bytes to copy for this page
 862                  */
 863                 shmem_page_index = offset / PAGE_SIZE;
 864                 shmem_page_offset = offset & ~PAGE_MASK;
 865                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 866                 data_page_offset = data_ptr & ~PAGE_MASK;
 867
 868                 page_length = remain;
 869                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 870                         page_length = PAGE_SIZE - shmem_page_offset;
 871                 if ((data_page_offset + page_length) > PAGE_SIZE)
 872                         page_length = PAGE_SIZE - data_page_offset;
 873
 874                 if (do_bit17_swizzling) {
 875                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 876                                               shmem_page_offset,
 877                                               user_pages[data_page_index],
 878                                               data_page_offset,
 879                                               page_length,
 880                                               0);
 881                 } else {
 882                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 883                                         shmem_page_offset,
 884                                         user_pages[data_page_index],
 885                                         data_page_offset,
 886                                         page_length);
 887                 }
 888
 889                 remain -= page_length;
 890                 data_ptr += page_length;
 891                 offset += page_length;
 892         }
 893
 894 fail_put_pages:
 895         i915_gem_object_put_pages(obj);
 896 fail_unlock:
 897         mutex_unlock(&dev->struct_mutex);
 898 fail_put_user_pages:
 899         for (i = 0; i < pinned_pages; i++)
 900                 page_cache_release(user_pages[i]);
 901         drm_free_large(user_pages);
 902
 903         return ret;
 904 }
 905
 906 /**
 907  * Writes data to the object referenced by handle.
 908  *
 909  * On error, the contents of the buffer that were to be modified are undefined.
 910  */
 911 int
 912 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 913                       struct drm_file *file_priv)
 914 {
 915         struct drm_i915_gem_pwrite *args = data;
 916         struct drm_gem_object *obj;
 917         struct drm_i915_gem_object *obj_priv;
 918         int ret = 0;
 919
 920         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 921         if (obj == NULL)
 922                 return -EBADF;
 923         obj_priv = to_intel_bo(obj);
 924
 925         /* Bounds check destination.
 926          *
 927          * XXX: This could use review for overflow issues...
 928          */
 929         if (args->offset > obj->size || args->size > obj->size ||
 930             args->offset + args->size > obj->size) {
 931                 drm_gem_object_unreference_unlocked(obj);
 932                 return -EINVAL;
 933         }
 934
 935         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 936          * it would end up going through the fenced access, and we'll get
 937          * different detiling behavior between reading and writing.
 938          * pread/pwrite currently are reading and writing from the CPU
 939          * perspective, requiring manual detiling by the client.
 940          */
 941         if (obj_priv->phys_obj)
 942                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 943         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 944                  dev->gtt_total != 0 &&
 945                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
 946                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 947                 if (ret == -EFAULT) {
 948                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 949                                                        file_priv);
 950                 }
 951         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 952                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 953         } else {
 954                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 955                 if (ret == -EFAULT) {
 956                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 957                                                          file_priv);
 958                 }
 959         }
 960
 961 #if WATCH_PWRITE
 962         if (ret)
 963                 DRM_INFO("pwrite failed %d\n", ret);
 964 #endif
 965
 966         drm_gem_object_unreference_unlocked(obj);
 967
 968         return ret;
 969 }
 970
 971 /**
 972  * Called when user space prepares to use an object with the CPU, either
 973  * through the mmap ioctl's mapping or a GTT mapping.
 974  */
 975 int
 976 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 977                           struct drm_file *file_priv)
 978 {
 979         struct drm_i915_private *dev_priv = dev->dev_private;
 980         struct drm_i915_gem_set_domain *args = data;
 981         struct drm_gem_object *obj;
 982         struct drm_i915_gem_object *obj_priv;
 983         uint32_t read_domains = args->read_domains;
 984         uint32_t write_domain = args->write_domain;
 985         int ret;
 986
 987         if (!(dev->driver->driver_features & DRIVER_GEM))
 988                 return -ENODEV;
 989
 990         /* Only handle setting domains to types used by the CPU. */
 991         if (write_domain & I915_GEM_GPU_DOMAINS)
 992                 return -EINVAL;
 993
 994         if (read_domains & I915_GEM_GPU_DOMAINS)
 995                 return -EINVAL;
 996
 997         /* Having something in the write domain implies it's in the read
 998          * domain, and only that read domain.  Enforce that in the request.
 999          */
1000         if (write_domain != 0 && read_domains != write_domain)
1001                 return -EINVAL;
1002
1003         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1004         if (obj == NULL)
1005                 return -EBADF;
1006         obj_priv = to_intel_bo(obj);
1007
1008         mutex_lock(&dev->struct_mutex);
1009
1010         intel_mark_busy(dev, obj);
1011
1012 #if WATCH_BUF
1013         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1014                  obj, obj->size, read_domains, write_domain);
1015 #endif
1016         if (read_domains & I915_GEM_DOMAIN_GTT) {
1017                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1018
1019                 /* Update the LRU on the fence for the CPU access that's
1020                  * about to occur.
1021                  */
1022                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1023                         struct drm_i915_fence_reg *reg =
1024                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1025                         list_move_tail(&reg->lru_list,
1026                                        &dev_priv->mm.fence_list);
1027                 }
1028
1029                 /* Silently promote "you're not bound, there was nothing to do"
1030                  * to success, since the client was just asking us to
1031                  * make sure everything was done.
1032                  */
1033                 if (ret == -EINVAL)
1034                         ret = 0;
1035         } else {
1036                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1037         }
1038
1039         drm_gem_object_unreference(obj);
1040         mutex_unlock(&dev->struct_mutex);
1041         return ret;
1042 }
1043
1044 /**
1045  * Called when user space has done writes to this buffer
1046  */
1047 int
1048 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1049                       struct drm_file *file_priv)
1050 {
1051         struct drm_i915_gem_sw_finish *args = data;
1052         struct drm_gem_object *obj;
1053         struct drm_i915_gem_object *obj_priv;
1054         int ret = 0;
1055
1056         if (!(dev->driver->driver_features & DRIVER_GEM))
1057                 return -ENODEV;
1058
1059         mutex_lock(&dev->struct_mutex);
1060         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1061         if (obj == NULL) {
1062                 mutex_unlock(&dev->struct_mutex);
1063                 return -EBADF;
1064         }
1065
1066 #if WATCH_BUF
1067         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1068                  __func__, args->handle, obj, obj->size);
1069 #endif
1070         obj_priv = to_intel_bo(obj);
1071
1072         /* Pinned buffers may be scanout, so flush the cache */
1073         if (obj_priv->pin_count)
1074                 i915_gem_object_flush_cpu_write_domain(obj);
1075
1076         drm_gem_object_unreference(obj);
1077         mutex_unlock(&dev->struct_mutex);
1078         return ret;
1079 }
1080
1081 /**
1082  * Maps the contents of an object, returning the address it is mapped
1083  * into.
1084  *
1085  * While the mapping holds a reference on the contents of the object, it doesn't
1086  * imply a ref on the object itself.
1087  */
1088 int
1089 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1090                    struct drm_file *file_priv)
1091 {
1092         struct drm_i915_gem_mmap *args = data;
1093         struct drm_gem_object *obj;
1094         loff_t offset;
1095         unsigned long addr;
1096
1097         if (!(dev->driver->driver_features & DRIVER_GEM))
1098                 return -ENODEV;
1099
1100         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1101         if (obj == NULL)
1102                 return -EBADF;
1103
1104         offset = args->offset;
1105
1106         down_write(&current->mm->mmap_sem);
1107         addr = do_mmap(obj->filp, 0, args->size,
1108                        PROT_READ | PROT_WRITE, MAP_SHARED,
1109                        args->offset);
1110         up_write(&current->mm->mmap_sem);
1111         drm_gem_object_unreference_unlocked(obj);
1112         if (IS_ERR((void *)addr))
1113                 return addr;
1114
1115         args->addr_ptr = (uint64_t) addr;
1116
1117         return 0;
1118 }
1119
1120 /**
1121  * i915_gem_fault - fault a page into the GTT
1122  * vma: VMA in question
1123  * vmf: fault info
1124  *
1125  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1126  * from userspace.  The fault handler takes care of binding the object to
1127  * the GTT (if needed), allocating and programming a fence register (again,
1128  * only if needed based on whether the old reg is still valid or the object
1129  * is tiled) and inserting a new PTE into the faulting process.
1130  *
1131  * Note that the faulting process may involve evicting existing objects
1132  * from the GTT and/or fence registers to make room.  So performance may
1133  * suffer if the GTT working set is large or there are few fence registers
1134  * left.
1135  */
1136 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1137 {
1138         struct drm_gem_object *obj = vma->vm_private_data;
1139         struct drm_device *dev = obj->dev;
1140         struct drm_i915_private *dev_priv = dev->dev_private;
1141         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1142         pgoff_t page_offset;
1143         unsigned long pfn;
1144         int ret = 0;
1145         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1146
1147         /* We don't use vmf->pgoff since that has the fake offset */
1148         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1149                 PAGE_SHIFT;
1150
1151         /* Now bind it into the GTT if needed */
1152         mutex_lock(&dev->struct_mutex);
1153         if (!obj_priv->gtt_space) {
1154                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1155                 if (ret)
1156                         goto unlock;
1157
1158                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1159
1160                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1161                 if (ret)
1162                         goto unlock;
1163         }
1164
1165         /* Need a new fence register? */
1166         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1167                 ret = i915_gem_object_get_fence_reg(obj);
1168                 if (ret)
1169                         goto unlock;
1170         }
1171
1172         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1173                 page_offset;
1174
1175         /* Finally, remap it using the new GTT offset */
1176         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1177 unlock:
1178         mutex_unlock(&dev->struct_mutex);
1179
1180         switch (ret) {
1181         case 0:
1182         case -ERESTARTSYS:
1183                 return VM_FAULT_NOPAGE;
1184         case -ENOMEM:
1185         case -EAGAIN:
1186                 return VM_FAULT_OOM;
1187         default:
1188                 return VM_FAULT_SIGBUS;
1189         }
1190 }
1191
1192 /**
1193  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1194  * @obj: obj in question
1195  *
1196  * GEM memory mapping works by handing back to userspace a fake mmap offset
1197  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1198  * up the object based on the offset and sets up the various memory mapping
1199  * structures.
1200  *
1201  * This routine allocates and attaches a fake offset for @obj.
1202  */
1203 static int
1204 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1205 {
1206         struct drm_device *dev = obj->dev;
1207         struct drm_gem_mm *mm = dev->mm_private;
1208         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1209         struct drm_map_list *list;
1210         struct drm_local_map *map;
1211         int ret = 0;
1212
1213         /* Set the object up for mmap'ing */
1214         list = &obj->map_list;
1215         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1216         if (!list->map)
1217                 return -ENOMEM;
1218
1219         map = list->map;
1220         map->type = _DRM_GEM;
1221         map->size = obj->size;
1222         map->handle = obj;
1223
1224         /* Get a DRM GEM mmap offset allocated... */
1225         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1226                                                     obj->size / PAGE_SIZE, 0, 0);
1227         if (!list->file_offset_node) {
1228                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1229                 ret = -ENOMEM;
1230                 goto out_free_list;
1231         }
1232
1233         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1234                                                   obj->size / PAGE_SIZE, 0);
1235         if (!list->file_offset_node) {
1236                 ret = -ENOMEM;
1237                 goto out_free_list;
1238         }
1239
1240         list->hash.key = list->file_offset_node->start;
1241         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1242                 DRM_ERROR("failed to add to map hash\n");
1243                 ret = -ENOMEM;
1244                 goto out_free_mm;
1245         }
1246
1247         /* By now we should be all set, any drm_mmap request on the offset
1248          * below will get to our mmap & fault handler */
1249         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1250
1251         return 0;
1252
1253 out_free_mm:
1254         drm_mm_put_block(list->file_offset_node);
1255 out_free_list:
1256         kfree(list->map);
1257
1258         return ret;
1259 }
1260
1261 /**
1262  * i915_gem_release_mmap - remove physical page mappings
1263  * @obj: obj in question
1264  *
1265  * Preserve the reservation of the mmapping with the DRM core code, but
1266  * relinquish ownership of the pages back to the system.
1267  *
1268  * It is vital that we remove the page mapping if we have mapped a tiled
1269  * object through the GTT and then lose the fence register due to
1270  * resource pressure. Similarly if the object has been moved out of the
1271  * aperture, than pages mapped into userspace must be revoked. Removing the
1272  * mapping will then trigger a page fault on the next user access, allowing
1273  * fixup by i915_gem_fault().
1274  */
1275 void
1276 i915_gem_release_mmap(struct drm_gem_object *obj)
1277 {
1278         struct drm_device *dev = obj->dev;
1279         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1280
1281         if (dev->dev_mapping)
1282                 unmap_mapping_range(dev->dev_mapping,
1283                                     obj_priv->mmap_offset, obj->size, 1);
1284 }
1285
1286 static void
1287 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1288 {
1289         struct drm_device *dev = obj->dev;
1290         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1291         struct drm_gem_mm *mm = dev->mm_private;
1292         struct drm_map_list *list;
1293
1294         list = &obj->map_list;
1295         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1296
1297         if (list->file_offset_node) {
1298                 drm_mm_put_block(list->file_offset_node);
1299                 list->file_offset_node = NULL;
1300         }
1301
1302         if (list->map) {
1303                 kfree(list->map);
1304                 list->map = NULL;
1305         }
1306
1307         obj_priv->mmap_offset = 0;
1308 }
1309
1310 /**
1311  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1312  * @obj: object to check
1313  *
1314  * Return the required GTT alignment for an object, taking into account
1315  * potential fence register mapping if needed.
1316  */
1317 static uint32_t
1318 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1319 {
1320         struct drm_device *dev = obj->dev;
1321         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1322         int start, i;
1323
1324         /*
1325          * Minimum alignment is 4k (GTT page size), but might be greater
1326          * if a fence register is needed for the object.
1327          */
1328         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1329                 return 4096;
1330
1331         /*
1332          * Previous chips need to be aligned to the size of the smallest
1333          * fence register that can contain the object.
1334          */
1335         if (IS_I9XX(dev))
1336                 start = 1024*1024;
1337         else
1338                 start = 512*1024;
1339
1340         for (i = start; i < obj->size; i <<= 1)
1341                 ;
1342
1343         return i;
1344 }
1345
1346 /**
1347  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1348  * @dev: DRM device
1349  * @data: GTT mapping ioctl data
1350  * @file_priv: GEM object info
1351  *
1352  * Simply returns the fake offset to userspace so it can mmap it.
1353  * The mmap call will end up in drm_gem_mmap(), which will set things
1354  * up so we can get faults in the handler above.
1355  *
1356  * The fault handler will take care of binding the object into the GTT
1357  * (since it may have been evicted to make room for something), allocating
1358  * a fence register, and mapping the appropriate aperture address into
1359  * userspace.
1360  */
1361 int
1362 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1363                         struct drm_file *file_priv)
1364 {
1365         struct drm_i915_gem_mmap_gtt *args = data;
1366         struct drm_i915_private *dev_priv = dev->dev_private;
1367         struct drm_gem_object *obj;
1368         struct drm_i915_gem_object *obj_priv;
1369         int ret;
1370
1371         if (!(dev->driver->driver_features & DRIVER_GEM))
1372                 return -ENODEV;
1373
1374         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1375         if (obj == NULL)
1376                 return -EBADF;
1377
1378         mutex_lock(&dev->struct_mutex);
1379
1380         obj_priv = to_intel_bo(obj);
1381
1382         if (obj_priv->madv != I915_MADV_WILLNEED) {
1383                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1384                 drm_gem_object_unreference(obj);
1385                 mutex_unlock(&dev->struct_mutex);
1386                 return -EINVAL;
1387         }
1388
1389
1390         if (!obj_priv->mmap_offset) {
1391                 ret = i915_gem_create_mmap_offset(obj);
1392                 if (ret) {
1393                         drm_gem_object_unreference(obj);
1394                         mutex_unlock(&dev->struct_mutex);
1395                         return ret;
1396                 }
1397         }
1398
1399         args->offset = obj_priv->mmap_offset;
1400
1401         /*
1402          * Pull it into the GTT so that we have a page list (makes the
1403          * initial fault faster and any subsequent flushing possible).
1404          */
1405         if (!obj_priv->agp_mem) {
1406                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1407                 if (ret) {
1408                         drm_gem_object_unreference(obj);
1409                         mutex_unlock(&dev->struct_mutex);
1410                         return ret;
1411                 }
1412                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1413         }
1414
1415         drm_gem_object_unreference(obj);
1416         mutex_unlock(&dev->struct_mutex);
1417
1418         return 0;
1419 }
1420
1421 void
1422 i915_gem_object_put_pages(struct drm_gem_object *obj)
1423 {
1424         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1425         int page_count = obj->size / PAGE_SIZE;
1426         int i;
1427
1428         BUG_ON(obj_priv->pages_refcount == 0);
1429         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1430
1431         if (--obj_priv->pages_refcount != 0)
1432                 return;
1433
1434         if (obj_priv->tiling_mode != I915_TILING_NONE)
1435                 i915_gem_object_save_bit_17_swizzle(obj);
1436
1437         if (obj_priv->madv == I915_MADV_DONTNEED)
1438                 obj_priv->dirty = 0;
1439
1440         for (i = 0; i < page_count; i++) {
1441                 if (obj_priv->dirty)
1442                         set_page_dirty(obj_priv->pages[i]);
1443
1444                 if (obj_priv->madv == I915_MADV_WILLNEED)
1445                         mark_page_accessed(obj_priv->pages[i]);
1446
1447                 page_cache_release(obj_priv->pages[i]);
1448         }
1449         obj_priv->dirty = 0;
1450
1451         drm_free_large(obj_priv->pages);
1452         obj_priv->pages = NULL;
1453 }
1454
1455 static void
1456 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1457                                struct intel_ring_buffer *ring)
1458 {
1459         struct drm_device *dev = obj->dev;
1460         drm_i915_private_t *dev_priv = dev->dev_private;
1461         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1462         BUG_ON(ring == NULL);
1463         obj_priv->ring = ring;
1464
1465         /* Add a reference if we're newly entering the active list. */
1466         if (!obj_priv->active) {
1467                 drm_gem_object_reference(obj);
1468                 obj_priv->active = 1;
1469         }
1470         /* Move from whatever list we were on to the tail of execution. */
1471         spin_lock(&dev_priv->mm.active_list_lock);
1472         list_move_tail(&obj_priv->list, &ring->active_list);
1473         spin_unlock(&dev_priv->mm.active_list_lock);
1474         obj_priv->last_rendering_seqno = seqno;
1475 }
1476
1477 static void
1478 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1479 {
1480         struct drm_device *dev = obj->dev;
1481         drm_i915_private_t *dev_priv = dev->dev_private;
1482         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1483
1484         BUG_ON(!obj_priv->active);
1485         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1486         obj_priv->last_rendering_seqno = 0;
1487 }
1488
1489 /* Immediately discard the backing storage */
1490 static void
1491 i915_gem_object_truncate(struct drm_gem_object *obj)
1492 {
1493         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1494         struct inode *inode;
1495
1496         inode = obj->filp->f_path.dentry->d_inode;
1497         if (inode->i_op->truncate)
1498                 inode->i_op->truncate (inode);
1499
1500         obj_priv->madv = __I915_MADV_PURGED;
1501 }
1502
1503 static inline int
1504 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1505 {
1506         return obj_priv->madv == I915_MADV_DONTNEED;
1507 }
1508
1509 static void
1510 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1511 {
1512         struct drm_device *dev = obj->dev;
1513         drm_i915_private_t *dev_priv = dev->dev_private;
1514         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1515
1516         i915_verify_inactive(dev, __FILE__, __LINE__);
1517         if (obj_priv->pin_count != 0)
1518                 list_del_init(&obj_priv->list);
1519         else
1520                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1521
1522         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1523
1524         obj_priv->last_rendering_seqno = 0;
1525         obj_priv->ring = NULL;
1526         if (obj_priv->active) {
1527                 obj_priv->active = 0;
1528                 drm_gem_object_unreference(obj);
1529         }
1530         i915_verify_inactive(dev, __FILE__, __LINE__);
1531 }
1532
1533 static void
1534 i915_gem_process_flushing_list(struct drm_device *dev,
1535                                uint32_t flush_domains, uint32_t seqno,
1536                                struct intel_ring_buffer *ring)
1537 {
1538         drm_i915_private_t *dev_priv = dev->dev_private;
1539         struct drm_i915_gem_object *obj_priv, *next;
1540
1541         list_for_each_entry_safe(obj_priv, next,
1542                                  &dev_priv->mm.gpu_write_list,
1543                                  gpu_write_list) {
1544                 struct drm_gem_object *obj = &obj_priv->base;
1545
1546                 if ((obj->write_domain & flush_domains) ==
1547                     obj->write_domain &&
1548                     obj_priv->ring->ring_flag == ring->ring_flag) {
1549                         uint32_t old_write_domain = obj->write_domain;
1550
1551                         obj->write_domain = 0;
1552                         list_del_init(&obj_priv->gpu_write_list);
1553                         i915_gem_object_move_to_active(obj, seqno, ring);
1554
1555                         /* update the fence lru list */
1556                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1557                                 struct drm_i915_fence_reg *reg =
1558                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1559                                 list_move_tail(&reg->lru_list,
1560                                                 &dev_priv->mm.fence_list);
1561                         }
1562
1563                         trace_i915_gem_object_change_domain(obj,
1564                                                             obj->read_domains,
1565                                                             old_write_domain);
1566                 }
1567         }
1568 }
1569
1570 uint32_t
1571 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1572                  uint32_t flush_domains, struct intel_ring_buffer *ring)
1573 {
1574         drm_i915_private_t *dev_priv = dev->dev_private;
1575         struct drm_i915_file_private *i915_file_priv = NULL;
1576         struct drm_i915_gem_request *request;
1577         uint32_t seqno;
1578         int was_empty;
1579
1580         if (file_priv != NULL)
1581                 i915_file_priv = file_priv->driver_priv;
1582
1583         request = kzalloc(sizeof(*request), GFP_KERNEL);
1584         if (request == NULL)
1585                 return 0;
1586
1587         seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1588
1589         request->seqno = seqno;
1590         request->ring = ring;
1591         request->emitted_jiffies = jiffies;
1592         was_empty = list_empty(&ring->request_list);
1593         list_add_tail(&request->list, &ring->request_list);
1594
1595         if (i915_file_priv) {
1596                 list_add_tail(&request->client_list,
1597                               &i915_file_priv->mm.request_list);
1598         } else {
1599                 INIT_LIST_HEAD(&request->client_list);
1600         }
1601
1602         /* Associate any objects on the flushing list matching the write
1603          * domain we're flushing with our flush.
1604          */
1605         if (flush_domains != 0)
1606                 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1607
1608         if (!dev_priv->mm.suspended) {
1609                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1610                 if (was_empty)
1611                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1612         }
1613         return seqno;
1614 }
1615
1616 /**
1617  * Command execution barrier
1618  *
1619  * Ensures that all commands in the ring are finished
1620  * before signalling the CPU
1621  */
1622 static uint32_t
1623 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1624 {
1625         uint32_t flush_domains = 0;
1626
1627         /* The sampler always gets flushed on i965 (sigh) */
1628         if (IS_I965G(dev))
1629                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1630
1631         ring->flush(dev, ring,
1632                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1633         return flush_domains;
1634 }
1635
1636 /**
1637  * Moves buffers associated only with the given active seqno from the active
1638  * to inactive list, potentially freeing them.
1639  */
1640 static void
1641 i915_gem_retire_request(struct drm_device *dev,
1642                         struct drm_i915_gem_request *request)
1643 {
1644         drm_i915_private_t *dev_priv = dev->dev_private;
1645
1646         trace_i915_gem_request_retire(dev, request->seqno);
1647
1648         /* Move any buffers on the active list that are no longer referenced
1649          * by the ringbuffer to the flushing/inactive lists as appropriate.
1650          */
1651         spin_lock(&dev_priv->mm.active_list_lock);
1652         while (!list_empty(&request->ring->active_list)) {
1653                 struct drm_gem_object *obj;
1654                 struct drm_i915_gem_object *obj_priv;
1655
1656                 obj_priv = list_first_entry(&request->ring->active_list,
1657                                             struct drm_i915_gem_object,
1658                                             list);
1659                 obj = &obj_priv->base;
1660
1661                 /* If the seqno being retired doesn't match the oldest in the
1662                  * list, then the oldest in the list must still be newer than
1663                  * this seqno.
1664                  */
1665                 if (obj_priv->last_rendering_seqno != request->seqno)
1666                         goto out;
1667
1668 #if WATCH_LRU
1669                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1670                          __func__, request->seqno, obj);
1671 #endif
1672
1673                 if (obj->write_domain != 0)
1674                         i915_gem_object_move_to_flushing(obj);
1675                 else {
1676                         /* Take a reference on the object so it won't be
1677                          * freed while the spinlock is held.  The list
1678                          * protection for this spinlock is safe when breaking
1679                          * the lock like this since the next thing we do
1680                          * is just get the head of the list again.
1681                          */
1682                         drm_gem_object_reference(obj);
1683                         i915_gem_object_move_to_inactive(obj);
1684                         spin_unlock(&dev_priv->mm.active_list_lock);
1685                         drm_gem_object_unreference(obj);
1686                         spin_lock(&dev_priv->mm.active_list_lock);
1687                 }
1688         }
1689 out:
1690         spin_unlock(&dev_priv->mm.active_list_lock);
1691 }
1692
1693 /**
1694  * Returns true if seq1 is later than seq2.
1695  */
1696 bool
1697 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1698 {
1699         return (int32_t)(seq1 - seq2) >= 0;
1700 }
1701
1702 uint32_t
1703 i915_get_gem_seqno(struct drm_device *dev,
1704                    struct intel_ring_buffer *ring)
1705 {
1706         return ring->get_gem_seqno(dev, ring);
1707 }
1708
1709 /**
1710  * This function clears the request list as sequence numbers are passed.
1711  */
1712 static void
1713 i915_gem_retire_requests_ring(struct drm_device *dev,
1714                               struct intel_ring_buffer *ring)
1715 {
1716         drm_i915_private_t *dev_priv = dev->dev_private;
1717         uint32_t seqno;
1718
1719         if (!ring->status_page.page_addr
1720                         || list_empty(&ring->request_list))
1721                 return;
1722
1723         seqno = i915_get_gem_seqno(dev, ring);
1724
1725         while (!list_empty(&ring->request_list)) {
1726                 struct drm_i915_gem_request *request;
1727                 uint32_t retiring_seqno;
1728
1729                 request = list_first_entry(&ring->request_list,
1730                                            struct drm_i915_gem_request,
1731                                            list);
1732                 retiring_seqno = request->seqno;
1733
1734                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1735                     atomic_read(&dev_priv->mm.wedged)) {
1736                         i915_gem_retire_request(dev, request);
1737
1738                         list_del(&request->list);
1739                         list_del(&request->client_list);
1740                         kfree(request);
1741                 } else
1742                         break;
1743         }
1744
1745         if (unlikely (dev_priv->trace_irq_seqno &&
1746                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1747
1748                 ring->user_irq_put(dev, ring);
1749                 dev_priv->trace_irq_seqno = 0;
1750         }
1751 }
1752
1753 void
1754 i915_gem_retire_requests(struct drm_device *dev)
1755 {
1756         drm_i915_private_t *dev_priv = dev->dev_private;
1757
1758         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1759             struct drm_i915_gem_object *obj_priv, *tmp;
1760
1761             /* We must be careful that during unbind() we do not
1762              * accidentally infinitely recurse into retire requests.
1763              * Currently:
1764              *   retire -> free -> unbind -> wait -> retire_ring
1765              */
1766             list_for_each_entry_safe(obj_priv, tmp,
1767                                      &dev_priv->mm.deferred_free_list,
1768                                      list)
1769                     i915_gem_free_object_tail(&obj_priv->base);
1770         }
1771
1772         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1773         if (HAS_BSD(dev))
1774                 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1775 }
1776
1777 void
1778 i915_gem_retire_work_handler(struct work_struct *work)
1779 {
1780         drm_i915_private_t *dev_priv;
1781         struct drm_device *dev;
1782
1783         dev_priv = container_of(work, drm_i915_private_t,
1784                                 mm.retire_work.work);
1785         dev = dev_priv->dev;
1786
1787         mutex_lock(&dev->struct_mutex);
1788         i915_gem_retire_requests(dev);
1789
1790         if (!dev_priv->mm.suspended &&
1791                 (!list_empty(&dev_priv->render_ring.request_list) ||
1792                         (HAS_BSD(dev) &&
1793                          !list_empty(&dev_priv->bsd_ring.request_list))))
1794                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1795         mutex_unlock(&dev->struct_mutex);
1796 }
1797
1798 int
1799 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1800                 int interruptible, struct intel_ring_buffer *ring)
1801 {
1802         drm_i915_private_t *dev_priv = dev->dev_private;
1803         u32 ier;
1804         int ret = 0;
1805
1806         BUG_ON(seqno == 0);
1807
1808         if (atomic_read(&dev_priv->mm.wedged))
1809                 return -EIO;
1810
1811         if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1812                 if (HAS_PCH_SPLIT(dev))
1813                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1814                 else
1815                         ier = I915_READ(IER);
1816                 if (!ier) {
1817                         DRM_ERROR("something (likely vbetool) disabled "
1818                                   "interrupts, re-enabling\n");
1819                         i915_driver_irq_preinstall(dev);
1820                         i915_driver_irq_postinstall(dev);
1821                 }
1822
1823                 trace_i915_gem_request_wait_begin(dev, seqno);
1824
1825                 ring->waiting_gem_seqno = seqno;
1826                 ring->user_irq_get(dev, ring);
1827                 if (interruptible)
1828                         ret = wait_event_interruptible(ring->irq_queue,
1829                                 i915_seqno_passed(
1830                                         ring->get_gem_seqno(dev, ring), seqno)
1831                                 || atomic_read(&dev_priv->mm.wedged));
1832                 else
1833                         wait_event(ring->irq_queue,
1834                                 i915_seqno_passed(
1835                                         ring->get_gem_seqno(dev, ring), seqno)
1836                                 || atomic_read(&dev_priv->mm.wedged));
1837
1838                 ring->user_irq_put(dev, ring);
1839                 ring->waiting_gem_seqno = 0;
1840
1841                 trace_i915_gem_request_wait_end(dev, seqno);
1842         }
1843         if (atomic_read(&dev_priv->mm.wedged))
1844                 ret = -EIO;
1845
1846         if (ret && ret != -ERESTARTSYS)
1847                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1848                           __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1849
1850         /* Directly dispatch request retiring.  While we have the work queue
1851          * to handle this, the waiter on a request often wants an associated
1852          * buffer to have made it to the inactive list, and we would need
1853          * a separate wait queue to handle that.
1854          */
1855         if (ret == 0)
1856                 i915_gem_retire_requests_ring(dev, ring);
1857
1858         return ret;
1859 }
1860
1861 /**
1862  * Waits for a sequence number to be signaled, and cleans up the
1863  * request and object lists appropriately for that event.
1864  */
1865 static int
1866 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1867                 struct intel_ring_buffer *ring)
1868 {
1869         return i915_do_wait_request(dev, seqno, 1, ring);
1870 }
1871
1872 static void
1873 i915_gem_flush(struct drm_device *dev,
1874                uint32_t invalidate_domains,
1875                uint32_t flush_domains)
1876 {
1877         drm_i915_private_t *dev_priv = dev->dev_private;
1878         if (flush_domains & I915_GEM_DOMAIN_CPU)
1879                 drm_agp_chipset_flush(dev);
1880         dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1881                         invalidate_domains,
1882                         flush_domains);
1883
1884         if (HAS_BSD(dev))
1885                 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1886                                 invalidate_domains,
1887                                 flush_domains);
1888 }
1889
1890 static void
1891 i915_gem_flush_ring(struct drm_device *dev,
1892                uint32_t invalidate_domains,
1893                uint32_t flush_domains,
1894                struct intel_ring_buffer *ring)
1895 {
1896         if (flush_domains & I915_GEM_DOMAIN_CPU)
1897                 drm_agp_chipset_flush(dev);
1898         ring->flush(dev, ring,
1899                         invalidate_domains,
1900                         flush_domains);
1901 }
1902
1903 /**
1904  * Ensures that all rendering to the object has completed and the object is
1905  * safe to unbind from the GTT or access from the CPU.
1906  */
1907 static int
1908 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1909 {
1910         struct drm_device *dev = obj->dev;
1911         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1912         int ret;
1913
1914         /* This function only exists to support waiting for existing rendering,
1915          * not for emitting required flushes.
1916          */
1917         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1918
1919         /* If there is rendering queued on the buffer being evicted, wait for
1920          * it.
1921          */
1922         if (obj_priv->active) {
1923 #if WATCH_BUF
1924                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1925                           __func__, obj, obj_priv->last_rendering_seqno);
1926 #endif
1927                 ret = i915_wait_request(dev,
1928                                 obj_priv->last_rendering_seqno, obj_priv->ring);
1929                 if (ret != 0)
1930                         return ret;
1931         }
1932
1933         return 0;
1934 }
1935
1936 /**
1937  * Unbinds an object from the GTT aperture.
1938  */
1939 int
1940 i915_gem_object_unbind(struct drm_gem_object *obj)
1941 {
1942         struct drm_device *dev = obj->dev;
1943         drm_i915_private_t *dev_priv = dev->dev_private;
1944         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1945         int ret = 0;
1946
1947 #if WATCH_BUF
1948         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1949         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1950 #endif
1951         if (obj_priv->gtt_space == NULL)
1952                 return 0;
1953
1954         if (obj_priv->pin_count != 0) {
1955                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1956                 return -EINVAL;
1957         }
1958
1959         /* blow away mappings if mapped through GTT */
1960         i915_gem_release_mmap(obj);
1961
1962         /* Move the object to the CPU domain to ensure that
1963          * any possible CPU writes while it's not in the GTT
1964          * are flushed when we go to remap it. This will
1965          * also ensure that all pending GPU writes are finished
1966          * before we unbind.
1967          */
1968         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1969         if (ret == -ERESTARTSYS)
1970                 return ret;
1971         /* Continue on if we fail due to EIO, the GPU is hung so we
1972          * should be safe and we need to cleanup or else we might
1973          * cause memory corruption through use-after-free.
1974          */
1975
1976         BUG_ON(obj_priv->active);
1977
1978         /* release the fence reg _after_ flushing */
1979         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1980                 i915_gem_clear_fence_reg(obj);
1981
1982         if (obj_priv->agp_mem != NULL) {
1983                 drm_unbind_agp(obj_priv->agp_mem);
1984                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1985                 obj_priv->agp_mem = NULL;
1986         }
1987
1988         i915_gem_object_put_pages(obj);
1989         BUG_ON(obj_priv->pages_refcount);
1990
1991         if (obj_priv->gtt_space) {
1992                 atomic_dec(&dev->gtt_count);
1993                 atomic_sub(obj->size, &dev->gtt_memory);
1994
1995                 drm_mm_put_block(obj_priv->gtt_space);
1996                 obj_priv->gtt_space = NULL;
1997         }
1998
1999         /* Remove ourselves from the LRU list if present. */
2000         spin_lock(&dev_priv->mm.active_list_lock);
2001         if (!list_empty(&obj_priv->list))
2002                 list_del_init(&obj_priv->list);
2003         spin_unlock(&dev_priv->mm.active_list_lock);
2004
2005         if (i915_gem_object_is_purgeable(obj_priv))
2006                 i915_gem_object_truncate(obj);
2007
2008         trace_i915_gem_object_unbind(obj);
2009
2010         return ret;
2011 }
2012
2013 static struct drm_gem_object *
2014 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2015 {
2016         drm_i915_private_t *dev_priv = dev->dev_private;
2017         struct drm_i915_gem_object *obj_priv;
2018         struct drm_gem_object *best = NULL;
2019         struct drm_gem_object *first = NULL;
2020
2021         /* Try to find the smallest clean object */
2022         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2023                 struct drm_gem_object *obj = &obj_priv->base;
2024                 if (obj->size >= min_size) {
2025                         if ((!obj_priv->dirty ||
2026                              i915_gem_object_is_purgeable(obj_priv)) &&
2027                             (!best || obj->size < best->size)) {
2028                                 best = obj;
2029                                 if (best->size == min_size)
2030                                         return best;
2031                         }
2032                         if (!first)
2033                             first = obj;
2034                 }
2035         }
2036
2037         return best ? best : first;
2038 }
2039
2040 static int
2041 i915_gpu_idle(struct drm_device *dev)
2042 {
2043         drm_i915_private_t *dev_priv = dev->dev_private;
2044         bool lists_empty;
2045         uint32_t seqno1, seqno2;
2046         int ret;
2047
2048         spin_lock(&dev_priv->mm.active_list_lock);
2049         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2050                        list_empty(&dev_priv->render_ring.active_list) &&
2051                        (!HAS_BSD(dev) ||
2052                         list_empty(&dev_priv->bsd_ring.active_list)));
2053         spin_unlock(&dev_priv->mm.active_list_lock);
2054
2055         if (lists_empty)
2056                 return 0;
2057
2058         /* Flush everything onto the inactive list. */
2059         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2060         seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2061                         &dev_priv->render_ring);
2062         if (seqno1 == 0)
2063                 return -ENOMEM;
2064         ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2065
2066         if (HAS_BSD(dev)) {
2067                 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2068                                 &dev_priv->bsd_ring);
2069                 if (seqno2 == 0)
2070                         return -ENOMEM;
2071
2072                 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2073                 if (ret)
2074                         return ret;
2075         }
2076
2077
2078         return ret;
2079 }
2080
2081 static int
2082 i915_gem_evict_everything(struct drm_device *dev)
2083 {
2084         drm_i915_private_t *dev_priv = dev->dev_private;
2085         int ret;
2086         bool lists_empty;
2087
2088         spin_lock(&dev_priv->mm.active_list_lock);
2089         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090                        list_empty(&dev_priv->mm.flushing_list) &&
2091                        list_empty(&dev_priv->render_ring.active_list) &&
2092                        (!HAS_BSD(dev)
2093                         || list_empty(&dev_priv->bsd_ring.active_list)));
2094         spin_unlock(&dev_priv->mm.active_list_lock);
2095
2096         if (lists_empty)
2097                 return -ENOSPC;
2098
2099         /* Flush everything (on to the inactive lists) and evict */
2100         ret = i915_gpu_idle(dev);
2101         if (ret)
2102                 return ret;
2103
2104         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2105
2106         ret = i915_gem_evict_from_inactive_list(dev);
2107         if (ret)
2108                 return ret;
2109
2110         spin_lock(&dev_priv->mm.active_list_lock);
2111         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2112                        list_empty(&dev_priv->mm.flushing_list) &&
2113                        list_empty(&dev_priv->render_ring.active_list) &&
2114                        (!HAS_BSD(dev)
2115                         || list_empty(&dev_priv->bsd_ring.active_list)));
2116         spin_unlock(&dev_priv->mm.active_list_lock);
2117         BUG_ON(!lists_empty);
2118
2119         return 0;
2120 }
2121
2122 static int
2123 i915_gem_evict_something(struct drm_device *dev, int min_size)
2124 {
2125         drm_i915_private_t *dev_priv = dev->dev_private;
2126         struct drm_gem_object *obj;
2127         int ret;
2128
2129         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
2130         struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
2131         for (;;) {
2132                 i915_gem_retire_requests(dev);
2133
2134                 /* If there's an inactive buffer available now, grab it
2135                  * and be done.
2136                  */
2137                 obj = i915_gem_find_inactive_object(dev, min_size);
2138                 if (obj) {
2139                         struct drm_i915_gem_object *obj_priv;
2140
2141 #if WATCH_LRU
2142                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2143 #endif
2144                         obj_priv = to_intel_bo(obj);
2145                         BUG_ON(obj_priv->pin_count != 0);
2146                         BUG_ON(obj_priv->active);
2147
2148                         /* Wait on the rendering and unbind the buffer. */
2149                         return i915_gem_object_unbind(obj);
2150                 }
2151
2152                 /* If we didn't get anything, but the ring is still processing
2153                  * things, wait for the next to finish and hopefully leave us
2154                  * a buffer to evict.
2155                  */
2156                 if (!list_empty(&render_ring->request_list)) {
2157                         struct drm_i915_gem_request *request;
2158
2159                         request = list_first_entry(&render_ring->request_list,
2160                                                    struct drm_i915_gem_request,
2161                                                    list);
2162
2163                         ret = i915_wait_request(dev,
2164                                         request->seqno, request->ring);
2165                         if (ret)
2166                                 return ret;
2167
2168                         continue;
2169                 }
2170
2171                 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2172                         struct drm_i915_gem_request *request;
2173
2174                         request = list_first_entry(&bsd_ring->request_list,
2175                                                    struct drm_i915_gem_request,
2176                                                    list);
2177
2178                         ret = i915_wait_request(dev,
2179                                         request->seqno, request->ring);
2180                         if (ret)
2181                                 return ret;
2182
2183                         continue;
2184                 }
2185
2186                 /* If we didn't have anything on the request list but there
2187                  * are buffers awaiting a flush, emit one and try again.
2188                  * When we wait on it, those buffers waiting for that flush
2189                  * will get moved to inactive.
2190                  */
2191                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2192                         struct drm_i915_gem_object *obj_priv;
2193
2194                         /* Find an object that we can immediately reuse */
2195                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2196                                 obj = &obj_priv->base;
2197                                 if (obj->size >= min_size)
2198                                         break;
2199
2200                                 obj = NULL;
2201                         }
2202
2203                         if (obj != NULL) {
2204                                 uint32_t seqno;
2205
2206                                 i915_gem_flush_ring(dev,
2207                                                obj->write_domain,
2208                                                obj->write_domain,
2209                                                obj_priv->ring);
2210                                 seqno = i915_add_request(dev, NULL,
2211                                                 obj->write_domain,
2212                                                 obj_priv->ring);
2213                                 if (seqno == 0)
2214                                         return -ENOMEM;
2215                                 continue;
2216                         }
2217                 }
2218
2219                 /* If we didn't do any of the above, there's no single buffer
2220                  * large enough to swap out for the new one, so just evict
2221                  * everything and start again. (This should be rare.)
2222                  */
2223                 if (!list_empty (&dev_priv->mm.inactive_list))
2224                         return i915_gem_evict_from_inactive_list(dev);
2225                 else
2226                         return i915_gem_evict_everything(dev);
2227         }
2228 }
2229
2230 int
2231 i915_gem_object_get_pages(struct drm_gem_object *obj,
2232                           gfp_t gfpmask)
2233 {
2234         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2235         int page_count, i;
2236         struct address_space *mapping;
2237         struct inode *inode;
2238         struct page *page;
2239
2240         BUG_ON(obj_priv->pages_refcount
2241                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2242
2243         if (obj_priv->pages_refcount++ != 0)
2244                 return 0;
2245
2246         /* Get the list of pages out of our struct file.  They'll be pinned
2247          * at this point until we release them.
2248          */
2249         page_count = obj->size / PAGE_SIZE;
2250         BUG_ON(obj_priv->pages != NULL);
2251         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2252         if (obj_priv->pages == NULL) {
2253                 obj_priv->pages_refcount--;
2254                 return -ENOMEM;
2255         }
2256
2257         inode = obj->filp->f_path.dentry->d_inode;
2258         mapping = inode->i_mapping;
2259         for (i = 0; i < page_count; i++) {
2260                 page = read_cache_page_gfp(mapping, i,
2261                                            GFP_HIGHUSER |
2262                                            __GFP_COLD |
2263                                            __GFP_RECLAIMABLE |
2264                                            gfpmask);
2265                 if (IS_ERR(page))
2266                         goto err_pages;
2267
2268                 obj_priv->pages[i] = page;
2269         }
2270
2271         if (obj_priv->tiling_mode != I915_TILING_NONE)
2272                 i915_gem_object_do_bit_17_swizzle(obj);
2273
2274         return 0;
2275
2276 err_pages:
2277         while (i--)
2278                 page_cache_release(obj_priv->pages[i]);
2279
2280         drm_free_large(obj_priv->pages);
2281         obj_priv->pages = NULL;
2282         obj_priv->pages_refcount--;
2283         return PTR_ERR(page);
2284 }
2285
2286 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2287 {
2288         struct drm_gem_object *obj = reg->obj;
2289         struct drm_device *dev = obj->dev;
2290         drm_i915_private_t *dev_priv = dev->dev_private;
2291         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2292         int regnum = obj_priv->fence_reg;
2293         uint64_t val;
2294
2295         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2296                     0xfffff000) << 32;
2297         val |= obj_priv->gtt_offset & 0xfffff000;
2298         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2299                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2300
2301         if (obj_priv->tiling_mode == I915_TILING_Y)
2302                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2303         val |= I965_FENCE_REG_VALID;
2304
2305         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2306 }
2307
2308 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2309 {
2310         struct drm_gem_object *obj = reg->obj;
2311         struct drm_device *dev = obj->dev;
2312         drm_i915_private_t *dev_priv = dev->dev_private;
2313         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2314         int regnum = obj_priv->fence_reg;
2315         uint64_t val;
2316
2317         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2318                     0xfffff000) << 32;
2319         val |= obj_priv->gtt_offset & 0xfffff000;
2320         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2321         if (obj_priv->tiling_mode == I915_TILING_Y)
2322                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2323         val |= I965_FENCE_REG_VALID;
2324
2325         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2326 }
2327
2328 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2329 {
2330         struct drm_gem_object *obj = reg->obj;
2331         struct drm_device *dev = obj->dev;
2332         drm_i915_private_t *dev_priv = dev->dev_private;
2333         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2334         int regnum = obj_priv->fence_reg;
2335         int tile_width;
2336         uint32_t fence_reg, val;
2337         uint32_t pitch_val;
2338
2339         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2340             (obj_priv->gtt_offset & (obj->size - 1))) {
2341                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2342                      __func__, obj_priv->gtt_offset, obj->size);
2343                 return;
2344         }
2345
2346         if (obj_priv->tiling_mode == I915_TILING_Y &&
2347             HAS_128_BYTE_Y_TILING(dev))
2348                 tile_width = 128;
2349         else
2350                 tile_width = 512;
2351
2352         /* Note: pitch better be a power of two tile widths */
2353         pitch_val = obj_priv->stride / tile_width;
2354         pitch_val = ffs(pitch_val) - 1;
2355
2356         if (obj_priv->tiling_mode == I915_TILING_Y &&
2357             HAS_128_BYTE_Y_TILING(dev))
2358                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2359         else
2360                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2361
2362         val = obj_priv->gtt_offset;
2363         if (obj_priv->tiling_mode == I915_TILING_Y)
2364                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2365         val |= I915_FENCE_SIZE_BITS(obj->size);
2366         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2367         val |= I830_FENCE_REG_VALID;
2368
2369         if (regnum < 8)
2370                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2371         else
2372                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2373         I915_WRITE(fence_reg, val);
2374 }
2375
2376 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2377 {
2378         struct drm_gem_object *obj = reg->obj;
2379         struct drm_device *dev = obj->dev;
2380         drm_i915_private_t *dev_priv = dev->dev_private;
2381         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2382         int regnum = obj_priv->fence_reg;
2383         uint32_t val;
2384         uint32_t pitch_val;
2385         uint32_t fence_size_bits;
2386
2387         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2388             (obj_priv->gtt_offset & (obj->size - 1))) {
2389                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2390                      __func__, obj_priv->gtt_offset);
2391                 return;
2392         }
2393
2394         pitch_val = obj_priv->stride / 128;
2395         pitch_val = ffs(pitch_val) - 1;
2396         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2397
2398         val = obj_priv->gtt_offset;
2399         if (obj_priv->tiling_mode == I915_TILING_Y)
2400                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2401         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2402         WARN_ON(fence_size_bits & ~0x00000f00);
2403         val |= fence_size_bits;
2404         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2405         val |= I830_FENCE_REG_VALID;
2406
2407         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2408 }
2409
2410 static int i915_find_fence_reg(struct drm_device *dev)
2411 {
2412         struct drm_i915_fence_reg *reg = NULL;
2413         struct drm_i915_gem_object *obj_priv = NULL;
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         struct drm_gem_object *obj = NULL;
2416         int i, avail, ret;
2417
2418         /* First try to find a free reg */
2419         avail = 0;
2420         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2421                 reg = &dev_priv->fence_regs[i];
2422                 if (!reg->obj)
2423                         return i;
2424
2425                 obj_priv = to_intel_bo(reg->obj);
2426                 if (!obj_priv->pin_count)
2427                     avail++;
2428         }
2429
2430         if (avail == 0)
2431                 return -ENOSPC;
2432
2433         /* None available, try to steal one or wait for a user to finish */
2434         i = I915_FENCE_REG_NONE;
2435         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2436                             lru_list) {
2437                 obj = reg->obj;
2438                 obj_priv = to_intel_bo(obj);
2439
2440                 if (obj_priv->pin_count)
2441                         continue;
2442
2443                 /* found one! */
2444                 i = obj_priv->fence_reg;
2445                 break;
2446         }
2447
2448         BUG_ON(i == I915_FENCE_REG_NONE);
2449
2450         /* We only have a reference on obj from the active list. put_fence_reg
2451          * might drop that one, causing a use-after-free in it. So hold a
2452          * private reference to obj like the other callers of put_fence_reg
2453          * (set_tiling ioctl) do. */
2454         drm_gem_object_reference(obj);
2455         ret = i915_gem_object_put_fence_reg(obj);
2456         drm_gem_object_unreference(obj);
2457         if (ret != 0)
2458                 return ret;
2459
2460         return i;
2461 }
2462
2463 /**
2464  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2465  * @obj: object to map through a fence reg
2466  *
2467  * When mapping objects through the GTT, userspace wants to be able to write
2468  * to them without having to worry about swizzling if the object is tiled.
2469  *
2470  * This function walks the fence regs looking for a free one for @obj,
2471  * stealing one if it can't find any.
2472  *
2473  * It then sets up the reg based on the object's properties: address, pitch
2474  * and tiling format.
2475  */
2476 int
2477 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2478 {
2479         struct drm_device *dev = obj->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2482         struct drm_i915_fence_reg *reg = NULL;
2483         int ret;
2484
2485         /* Just update our place in the LRU if our fence is getting used. */
2486         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2487                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2488                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2489                 return 0;
2490         }
2491
2492         switch (obj_priv->tiling_mode) {
2493         case I915_TILING_NONE:
2494                 WARN(1, "allocating a fence for non-tiled object?\n");
2495                 break;
2496         case I915_TILING_X:
2497                 if (!obj_priv->stride)
2498                         return -EINVAL;
2499                 WARN((obj_priv->stride & (512 - 1)),
2500                      "object 0x%08x is X tiled but has non-512B pitch\n",
2501                      obj_priv->gtt_offset);
2502                 break;
2503         case I915_TILING_Y:
2504                 if (!obj_priv->stride)
2505                         return -EINVAL;
2506                 WARN((obj_priv->stride & (128 - 1)),
2507                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2508                      obj_priv->gtt_offset);
2509                 break;
2510         }
2511
2512         ret = i915_find_fence_reg(dev);
2513         if (ret < 0)
2514                 return ret;
2515
2516         obj_priv->fence_reg = ret;
2517         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2518         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2519
2520         reg->obj = obj;
2521
2522         if (IS_GEN6(dev))
2523                 sandybridge_write_fence_reg(reg);
2524         else if (IS_I965G(dev))
2525                 i965_write_fence_reg(reg);
2526         else if (IS_I9XX(dev))
2527                 i915_write_fence_reg(reg);
2528         else
2529                 i830_write_fence_reg(reg);
2530
2531         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2532                         obj_priv->tiling_mode);
2533
2534         return 0;
2535 }
2536
2537 /**
2538  * i915_gem_clear_fence_reg - clear out fence register info
2539  * @obj: object to clear
2540  *
2541  * Zeroes out the fence register itself and clears out the associated
2542  * data structures in dev_priv and obj_priv.
2543  */
2544 static void
2545 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2546 {
2547         struct drm_device *dev = obj->dev;
2548         drm_i915_private_t *dev_priv = dev->dev_private;
2549         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2550         struct drm_i915_fence_reg *reg =
2551                 &dev_priv->fence_regs[obj_priv->fence_reg];
2552
2553         if (IS_GEN6(dev)) {
2554                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2555                              (obj_priv->fence_reg * 8), 0);
2556         } else if (IS_I965G(dev)) {
2557                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2558         } else {
2559                 uint32_t fence_reg;
2560
2561                 if (obj_priv->fence_reg < 8)
2562                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2563                 else
2564                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2565                                                        8) * 4;
2566
2567                 I915_WRITE(fence_reg, 0);
2568         }
2569
2570         reg->obj = NULL;
2571         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2572         list_del_init(&reg->lru_list);
2573 }
2574
2575 /**
2576  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2577  * to the buffer to finish, and then resets the fence register.
2578  * @obj: tiled object holding a fence register.
2579  *
2580  * Zeroes out the fence register itself and clears out the associated
2581  * data structures in dev_priv and obj_priv.
2582  */
2583 int
2584 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2585 {
2586         struct drm_device *dev = obj->dev;
2587         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2588
2589         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2590                 return 0;
2591
2592         /* If we've changed tiling, GTT-mappings of the object
2593          * need to re-fault to ensure that the correct fence register
2594          * setup is in place.
2595          */
2596         i915_gem_release_mmap(obj);
2597
2598         /* On the i915, GPU access to tiled buffers is via a fence,
2599          * therefore we must wait for any outstanding access to complete
2600          * before clearing the fence.
2601          */
2602         if (!IS_I965G(dev)) {
2603                 int ret;
2604
2605                 ret = i915_gem_object_flush_gpu_write_domain(obj);
2606                 if (ret != 0)
2607                         return ret;
2608
2609                 ret = i915_gem_object_wait_rendering(obj);
2610                 if (ret != 0)
2611                         return ret;
2612         }
2613
2614         i915_gem_object_flush_gtt_write_domain(obj);
2615         i915_gem_clear_fence_reg (obj);
2616
2617         return 0;
2618 }
2619
2620 /**
2621  * Finds free space in the GTT aperture and binds the object there.
2622  */
2623 static int
2624 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2625 {
2626         struct drm_device *dev = obj->dev;
2627         drm_i915_private_t *dev_priv = dev->dev_private;
2628         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2629         struct drm_mm_node *free_space;
2630         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2631         int ret;
2632
2633         if (obj_priv->madv != I915_MADV_WILLNEED) {
2634                 DRM_ERROR("Attempting to bind a purgeable object\n");
2635                 return -EINVAL;
2636         }
2637
2638         if (alignment == 0)
2639                 alignment = i915_gem_get_gtt_alignment(obj);
2640         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2641                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2642                 return -EINVAL;
2643         }
2644
2645         /* If the object is bigger than the entire aperture, reject it early
2646          * before evicting everything in a vain attempt to find space.
2647          */
2648         if (obj->size > dev->gtt_total) {
2649                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2650                 return -E2BIG;
2651         }
2652
2653  search_free:
2654         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2655                                         obj->size, alignment, 0);
2656         if (free_space != NULL) {
2657                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2658                                                        alignment);
2659                 if (obj_priv->gtt_space != NULL)
2660                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2661         }
2662         if (obj_priv->gtt_space == NULL) {
2663                 /* If the gtt is empty and we're still having trouble
2664                  * fitting our object in, we're out of memory.
2665                  */
2666 #if WATCH_LRU
2667                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2668 #endif
2669                 ret = i915_gem_evict_something(dev, obj->size);
2670                 if (ret)
2671                         return ret;
2672
2673                 goto search_free;
2674         }
2675
2676 #if WATCH_BUF
2677         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2678                  obj->size, obj_priv->gtt_offset);
2679 #endif
2680         ret = i915_gem_object_get_pages(obj, gfpmask);
2681         if (ret) {
2682                 drm_mm_put_block(obj_priv->gtt_space);
2683                 obj_priv->gtt_space = NULL;
2684
2685                 if (ret == -ENOMEM) {
2686                         /* first try to clear up some space from the GTT */
2687                         ret = i915_gem_evict_something(dev, obj->size);
2688                         if (ret) {
2689                                 /* now try to shrink everyone else */
2690                                 if (gfpmask) {
2691                                         gfpmask = 0;
2692                                         goto search_free;
2693                                 }
2694
2695                                 return ret;
2696                         }
2697
2698                         goto search_free;
2699                 }
2700
2701                 return ret;
2702         }
2703
2704         /* Create an AGP memory structure pointing at our pages, and bind it
2705          * into the GTT.
2706          */
2707         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2708                                                obj_priv->pages,
2709                                                obj->size >> PAGE_SHIFT,
2710                                                obj_priv->gtt_offset,
2711                                                obj_priv->agp_type);
2712         if (obj_priv->agp_mem == NULL) {
2713                 i915_gem_object_put_pages(obj);
2714                 drm_mm_put_block(obj_priv->gtt_space);
2715                 obj_priv->gtt_space = NULL;
2716
2717                 ret = i915_gem_evict_something(dev, obj->size);
2718                 if (ret)
2719                         return ret;
2720
2721                 goto search_free;
2722         }
2723         atomic_inc(&dev->gtt_count);
2724         atomic_add(obj->size, &dev->gtt_memory);
2725
2726         /* Assert that the object is not currently in any GPU domain. As it
2727          * wasn't in the GTT, there shouldn't be any way it could have been in
2728          * a GPU cache
2729          */
2730         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2731         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2732
2733         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2734
2735         return 0;
2736 }
2737
2738 void
2739 i915_gem_clflush_object(struct drm_gem_object *obj)
2740 {
2741         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2742
2743         /* If we don't have a page list set up, then we're not pinned
2744          * to GPU, and we can ignore the cache flush because it'll happen
2745          * again at bind time.
2746          */
2747         if (obj_priv->pages == NULL)
2748                 return;
2749
2750         trace_i915_gem_object_clflush(obj);
2751
2752         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2753 }
2754
2755 /** Flushes any GPU write domain for the object if it's dirty. */
2756 static int
2757 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2758 {
2759         struct drm_device *dev = obj->dev;
2760         uint32_t old_write_domain;
2761         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2762
2763         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2764                 return 0;
2765
2766         /* Queue the GPU write cache flushing we need. */
2767         old_write_domain = obj->write_domain;
2768         i915_gem_flush(dev, 0, obj->write_domain);
2769         if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2770                 return -ENOMEM;
2771
2772         trace_i915_gem_object_change_domain(obj,
2773                                             obj->read_domains,
2774                                             old_write_domain);
2775         return 0;
2776 }
2777
2778 /** Flushes the GTT write domain for the object if it's dirty. */
2779 static void
2780 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2781 {
2782         uint32_t old_write_domain;
2783
2784         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2785                 return;
2786
2787         /* No actual flushing is required for the GTT write domain.   Writes
2788          * to it immediately go to main memory as far as we know, so there's
2789          * no chipset flush.  It also doesn't land in render cache.
2790          */
2791         old_write_domain = obj->write_domain;
2792         obj->write_domain = 0;
2793
2794         trace_i915_gem_object_change_domain(obj,
2795                                             obj->read_domains,
2796                                             old_write_domain);
2797 }
2798
2799 /** Flushes the CPU write domain for the object if it's dirty. */
2800 static void
2801 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2802 {
2803         struct drm_device *dev = obj->dev;
2804         uint32_t old_write_domain;
2805
2806         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2807                 return;
2808
2809         i915_gem_clflush_object(obj);
2810         drm_agp_chipset_flush(dev);
2811         old_write_domain = obj->write_domain;
2812         obj->write_domain = 0;
2813
2814         trace_i915_gem_object_change_domain(obj,
2815                                             obj->read_domains,
2816                                             old_write_domain);
2817 }
2818
2819 int
2820 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2821 {
2822         int ret = 0;
2823
2824         switch (obj->write_domain) {
2825         case I915_GEM_DOMAIN_GTT:
2826                 i915_gem_object_flush_gtt_write_domain(obj);
2827                 break;
2828         case I915_GEM_DOMAIN_CPU:
2829                 i915_gem_object_flush_cpu_write_domain(obj);
2830                 break;
2831         default:
2832                 ret = i915_gem_object_flush_gpu_write_domain(obj);
2833                 break;
2834         }
2835
2836         return ret;
2837 }
2838
2839 /**
2840  * Moves a single object to the GTT read, and possibly write domain.
2841  *
2842  * This function returns when the move is complete, including waiting on
2843  * flushes to occur.
2844  */
2845 int
2846 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2847 {
2848         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2849         uint32_t old_write_domain, old_read_domains;
2850         int ret;
2851
2852         /* Not valid to be called on unbound objects. */
2853         if (obj_priv->gtt_space == NULL)
2854                 return -EINVAL;
2855
2856         ret = i915_gem_object_flush_gpu_write_domain(obj);
2857         if (ret != 0)
2858                 return ret;
2859
2860         /* Wait on any GPU rendering and flushing to occur. */
2861         ret = i915_gem_object_wait_rendering(obj);
2862         if (ret != 0)
2863                 return ret;
2864
2865         old_write_domain = obj->write_domain;
2866         old_read_domains = obj->read_domains;
2867
2868         /* If we're writing through the GTT domain, then CPU and GPU caches
2869          * will need to be invalidated at next use.
2870          */
2871         if (write)
2872                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2873
2874         i915_gem_object_flush_cpu_write_domain(obj);
2875
2876         /* It should now be out of any other write domains, and we can update
2877          * the domain values for our changes.
2878          */
2879         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2880         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2881         if (write) {
2882                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2883                 obj_priv->dirty = 1;
2884         }
2885
2886         trace_i915_gem_object_change_domain(obj,
2887                                             old_read_domains,
2888                                             old_write_domain);
2889
2890         return 0;
2891 }
2892
2893 /*
2894  * Prepare buffer for display plane. Use uninterruptible for possible flush
2895  * wait, as in modesetting process we're not supposed to be interrupted.
2896  */
2897 int
2898 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2899 {
2900         struct drm_device *dev = obj->dev;
2901         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2902         uint32_t old_write_domain, old_read_domains;
2903         int ret;
2904
2905         /* Not valid to be called on unbound objects. */
2906         if (obj_priv->gtt_space == NULL)
2907                 return -EINVAL;
2908
2909         ret = i915_gem_object_flush_gpu_write_domain(obj);
2910         if (ret)
2911                 return ret;
2912
2913         /* Wait on any GPU rendering and flushing to occur. */
2914         if (obj_priv->active) {
2915 #if WATCH_BUF
2916                 DRM_INFO("%s: object %p wait for seqno %08x\n",
2917                           __func__, obj, obj_priv->last_rendering_seqno);
2918 #endif
2919                 ret = i915_do_wait_request(dev,
2920                                 obj_priv->last_rendering_seqno,
2921                                 0,
2922                                 obj_priv->ring);
2923                 if (ret != 0)
2924                         return ret;
2925         }
2926
2927         i915_gem_object_flush_cpu_write_domain(obj);
2928
2929         old_write_domain = obj->write_domain;
2930         old_read_domains = obj->read_domains;
2931
2932         /* It should now be out of any other write domains, and we can update
2933          * the domain values for our changes.
2934          */
2935         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2936         obj->read_domains = I915_GEM_DOMAIN_GTT;
2937         obj->write_domain = I915_GEM_DOMAIN_GTT;
2938         obj_priv->dirty = 1;
2939
2940         trace_i915_gem_object_change_domain(obj,
2941                                             old_read_domains,
2942                                             old_write_domain);
2943
2944         return 0;
2945 }
2946
2947 /**
2948  * Moves a single object to the CPU read, and possibly write domain.
2949  *
2950  * This function returns when the move is complete, including waiting on
2951  * flushes to occur.
2952  */
2953 static int
2954 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2955 {
2956         uint32_t old_write_domain, old_read_domains;
2957         int ret;
2958
2959         ret = i915_gem_object_flush_gpu_write_domain(obj);
2960         if (ret)
2961                 return ret;
2962
2963         /* Wait on any GPU rendering and flushing to occur. */
2964         ret = i915_gem_object_wait_rendering(obj);
2965         if (ret != 0)
2966                 return ret;
2967
2968         i915_gem_object_flush_gtt_write_domain(obj);
2969
2970         /* If we have a partially-valid cache of the object in the CPU,
2971          * finish invalidating it and free the per-page flags.
2972          */
2973         i915_gem_object_set_to_full_cpu_read_domain(obj);
2974
2975         old_write_domain = obj->write_domain;
2976         old_read_domains = obj->read_domains;
2977
2978         /* Flush the CPU cache if it's still invalid. */
2979         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2980                 i915_gem_clflush_object(obj);
2981
2982                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2983         }
2984
2985         /* It should now be out of any other write domains, and we can update
2986          * the domain values for our changes.
2987          */
2988         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2989
2990         /* If we're writing through the CPU, then the GPU read domains will
2991          * need to be invalidated at next use.
2992          */
2993         if (write) {
2994                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2995                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2996         }
2997
2998         trace_i915_gem_object_change_domain(obj,
2999                                             old_read_domains,
3000                                             old_write_domain);
3001
3002         return 0;
3003 }
3004
3005 /*
3006  * Set the next domain for the specified object. This
3007  * may not actually perform the necessary flushing/invaliding though,
3008  * as that may want to be batched with other set_domain operations
3009  *
3010  * This is (we hope) the only really tricky part of gem. The goal
3011  * is fairly simple -- track which caches hold bits of the object
3012  * and make sure they remain coherent. A few concrete examples may
3013  * help to explain how it works. For shorthand, we use the notation
3014  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3015  * a pair of read and write domain masks.
3016  *
3017  * Case 1: the batch buffer
3018  *
3019  *      1. Allocated
3020  *      2. Written by CPU
3021  *      3. Mapped to GTT
3022  *      4. Read by GPU
3023  *      5. Unmapped from GTT
3024  *      6. Freed
3025  *
3026  *      Let's take these a step at a time
3027  *
3028  *      1. Allocated
3029  *              Pages allocated from the kernel may still have
3030  *              cache contents, so we set them to (CPU, CPU) always.
3031  *      2. Written by CPU (using pwrite)
3032  *              The pwrite function calls set_domain (CPU, CPU) and
3033  *              this function does nothing (as nothing changes)
3034  *      3. Mapped by GTT
3035  *              This function asserts that the object is not
3036  *              currently in any GPU-based read or write domains
3037  *      4. Read by GPU
3038  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
3039  *              As write_domain is zero, this function adds in the
3040  *              current read domains (CPU+COMMAND, 0).
3041  *              flush_domains is set to CPU.
3042  *              invalidate_domains is set to COMMAND
3043  *              clflush is run to get data out of the CPU caches
3044  *              then i915_dev_set_domain calls i915_gem_flush to
3045  *              emit an MI_FLUSH and drm_agp_chipset_flush
3046  *      5. Unmapped from GTT
3047  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3048  *              flush_domains and invalidate_domains end up both zero
3049  *              so no flushing/invalidating happens
3050  *      6. Freed
3051  *              yay, done
3052  *
3053  * Case 2: The shared render buffer
3054  *
3055  *      1. Allocated
3056  *      2. Mapped to GTT
3057  *      3. Read/written by GPU
3058  *      4. set_domain to (CPU,CPU)
3059  *      5. Read/written by CPU
3060  *      6. Read/written by GPU
3061  *
3062  *      1. Allocated
3063  *              Same as last example, (CPU, CPU)
3064  *      2. Mapped to GTT
3065  *              Nothing changes (assertions find that it is not in the GPU)
3066  *      3. Read/written by GPU
3067  *              execbuffer calls set_domain (RENDER, RENDER)
3068  *              flush_domains gets CPU
3069  *              invalidate_domains gets GPU
3070  *              clflush (obj)
3071  *              MI_FLUSH and drm_agp_chipset_flush
3072  *      4. set_domain (CPU, CPU)
3073  *              flush_domains gets GPU
3074  *              invalidate_domains gets CPU
3075  *              wait_rendering (obj) to make sure all drawing is complete.
3076  *              This will include an MI_FLUSH to get the data from GPU
3077  *              to memory
3078  *              clflush (obj) to invalidate the CPU cache
3079  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3080  *      5. Read/written by CPU
3081  *              cache lines are loaded and dirtied
3082  *      6. Read written by GPU
3083  *              Same as last GPU access
3084  *
3085  * Case 3: The constant buffer
3086  *
3087  *      1. Allocated
3088  *      2. Written by CPU
3089  *      3. Read by GPU
3090  *      4. Updated (written) by CPU again
3091  *      5. Read by GPU
3092  *
3093  *      1. Allocated
3094  *              (CPU, CPU)
3095  *      2. Written by CPU
3096  *              (CPU, CPU)
3097  *      3. Read by GPU
3098  *              (CPU+RENDER, 0)
3099  *              flush_domains = CPU
3100  *              invalidate_domains = RENDER
3101  *              clflush (obj)
3102  *              MI_FLUSH
3103  *              drm_agp_chipset_flush
3104  *      4. Updated (written) by CPU again
3105  *              (CPU, CPU)
3106  *              flush_domains = 0 (no previous write domain)
3107  *              invalidate_domains = 0 (no new read domains)
3108  *      5. Read by GPU
3109  *              (CPU+RENDER, 0)
3110  *              flush_domains = CPU
3111  *              invalidate_domains = RENDER
3112  *              clflush (obj)
3113  *              MI_FLUSH
3114  *              drm_agp_chipset_flush
3115  */
3116 static void
3117 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3118 {
3119         struct drm_device               *dev = obj->dev;
3120         drm_i915_private_t              *dev_priv = dev->dev_private;
3121         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3122         uint32_t                        invalidate_domains = 0;
3123         uint32_t                        flush_domains = 0;
3124         uint32_t                        old_read_domains;
3125
3126         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3127         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3128
3129         intel_mark_busy(dev, obj);
3130
3131 #if WATCH_BUF
3132         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3133                  __func__, obj,
3134                  obj->read_domains, obj->pending_read_domains,
3135                  obj->write_domain, obj->pending_write_domain);
3136 #endif
3137         /*
3138          * If the object isn't moving to a new write domain,
3139          * let the object stay in multiple read domains
3140          */
3141         if (obj->pending_write_domain == 0)
3142                 obj->pending_read_domains |= obj->read_domains;
3143         else
3144                 obj_priv->dirty = 1;
3145
3146         /*
3147          * Flush the current write domain if
3148          * the new read domains don't match. Invalidate
3149          * any read domains which differ from the old
3150          * write domain
3151          */
3152         if (obj->write_domain &&
3153             obj->write_domain != obj->pending_read_domains) {
3154                 flush_domains |= obj->write_domain;
3155                 invalidate_domains |=
3156                         obj->pending_read_domains & ~obj->write_domain;
3157         }
3158         /*
3159          * Invalidate any read caches which may have
3160          * stale data. That is, any new read domains.
3161          */
3162         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3163         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3164 #if WATCH_BUF
3165                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3166                          __func__, flush_domains, invalidate_domains);
3167 #endif
3168                 i915_gem_clflush_object(obj);
3169         }
3170
3171         old_read_domains = obj->read_domains;
3172
3173         /* The actual obj->write_domain will be updated with
3174          * pending_write_domain after we emit the accumulated flush for all
3175          * of our domain changes in execbuffers (which clears objects'
3176          * write_domains).  So if we have a current write domain that we
3177          * aren't changing, set pending_write_domain to that.
3178          */
3179         if (flush_domains == 0 && obj->pending_write_domain == 0)
3180                 obj->pending_write_domain = obj->write_domain;
3181         obj->read_domains = obj->pending_read_domains;
3182
3183         if (flush_domains & I915_GEM_GPU_DOMAINS) {
3184                 if (obj_priv->ring == &dev_priv->render_ring)
3185                         dev_priv->flush_rings |= FLUSH_RENDER_RING;
3186                 else if (obj_priv->ring == &dev_priv->bsd_ring)
3187                         dev_priv->flush_rings |= FLUSH_BSD_RING;
3188         }
3189
3190         dev->invalidate_domains |= invalidate_domains;
3191         dev->flush_domains |= flush_domains;
3192 #if WATCH_BUF
3193         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3194                  __func__,
3195                  obj->read_domains, obj->write_domain,
3196                  dev->invalidate_domains, dev->flush_domains);
3197 #endif
3198
3199         trace_i915_gem_object_change_domain(obj,
3200                                             old_read_domains,
3201                                             obj->write_domain);
3202 }
3203
3204 /**
3205  * Moves the object from a partially CPU read to a full one.
3206  *
3207  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3208  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3209  */
3210 static void
3211 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3212 {
3213         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3214
3215         if (!obj_priv->page_cpu_valid)
3216                 return;
3217
3218         /* If we're partially in the CPU read domain, finish moving it in.
3219          */
3220         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3221                 int i;
3222
3223                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3224                         if (obj_priv->page_cpu_valid[i])
3225                                 continue;
3226                         drm_clflush_pages(obj_priv->pages + i, 1);
3227                 }
3228         }
3229
3230         /* Free the page_cpu_valid mappings which are now stale, whether
3231          * or not we've got I915_GEM_DOMAIN_CPU.
3232          */
3233         kfree(obj_priv->page_cpu_valid);
3234         obj_priv->page_cpu_valid = NULL;
3235 }
3236
3237 /**
3238  * Set the CPU read domain on a range of the object.
3239  *
3240  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3241  * not entirely valid.  The page_cpu_valid member of the object flags which
3242  * pages have been flushed, and will be respected by
3243  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3244  * of the whole object.
3245  *
3246  * This function returns when the move is complete, including waiting on
3247  * flushes to occur.
3248  */
3249 static int
3250 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3251                                           uint64_t offset, uint64_t size)
3252 {
3253         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3254         uint32_t old_read_domains;
3255         int i, ret;
3256
3257         if (offset == 0 && size == obj->size)
3258                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3259
3260         ret = i915_gem_object_flush_gpu_write_domain(obj);
3261         if (ret)
3262                 return ret;
3263
3264         /* Wait on any GPU rendering and flushing to occur. */
3265         ret = i915_gem_object_wait_rendering(obj);
3266         if (ret != 0)
3267                 return ret;
3268         i915_gem_object_flush_gtt_write_domain(obj);
3269
3270         /* If we're already fully in the CPU read domain, we're done. */
3271         if (obj_priv->page_cpu_valid == NULL &&
3272             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3273                 return 0;
3274
3275         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3276          * newly adding I915_GEM_DOMAIN_CPU
3277          */
3278         if (obj_priv->page_cpu_valid == NULL) {
3279                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3280                                                    GFP_KERNEL);
3281                 if (obj_priv->page_cpu_valid == NULL)
3282                         return -ENOMEM;
3283         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3284                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3285
3286         /* Flush the cache on any pages that are still invalid from the CPU's
3287          * perspective.
3288          */
3289         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3290              i++) {
3291                 if (obj_priv->page_cpu_valid[i])
3292                         continue;
3293
3294                 drm_clflush_pages(obj_priv->pages + i, 1);
3295
3296                 obj_priv->page_cpu_valid[i] = 1;
3297         }
3298
3299         /* It should now be out of any other write domains, and we can update
3300          * the domain values for our changes.
3301          */
3302         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3303
3304         old_read_domains = obj->read_domains;
3305         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3306
3307         trace_i915_gem_object_change_domain(obj,
3308                                             old_read_domains,
3309                                             obj->write_domain);
3310
3311         return 0;
3312 }
3313
3314 /**
3315  * Pin an object to the GTT and evaluate the relocations landing in it.
3316  */
3317 static int
3318 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3319                                  struct drm_file *file_priv,
3320                                  struct drm_i915_gem_exec_object2 *entry,
3321                                  struct drm_i915_gem_relocation_entry *relocs)
3322 {
3323         struct drm_device *dev = obj->dev;
3324         drm_i915_private_t *dev_priv = dev->dev_private;
3325         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3326         int i, ret;
3327         void __iomem *reloc_page;
3328         bool need_fence;
3329
3330         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3331                      obj_priv->tiling_mode != I915_TILING_NONE;
3332
3333         /* Check fence reg constraints and rebind if necessary */
3334         if (need_fence &&
3335             !i915_gem_object_fence_offset_ok(obj,
3336                                              obj_priv->tiling_mode)) {
3337                 ret = i915_gem_object_unbind(obj);
3338                 if (ret)
3339                         return ret;
3340         }
3341
3342         /* Choose the GTT offset for our buffer and put it there. */
3343         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3344         if (ret)
3345                 return ret;
3346
3347         /*
3348          * Pre-965 chips need a fence register set up in order to
3349          * properly handle blits to/from tiled surfaces.
3350          */
3351         if (need_fence) {
3352                 ret = i915_gem_object_get_fence_reg(obj);
3353                 if (ret != 0) {
3354                         i915_gem_object_unpin(obj);
3355                         return ret;
3356                 }
3357         }
3358
3359         entry->offset = obj_priv->gtt_offset;
3360
3361         /* Apply the relocations, using the GTT aperture to avoid cache
3362          * flushing requirements.
3363          */
3364         for (i = 0; i < entry->relocation_count; i++) {
3365                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3366                 struct drm_gem_object *target_obj;
3367                 struct drm_i915_gem_object *target_obj_priv;
3368                 uint32_t reloc_val, reloc_offset;
3369                 uint32_t __iomem *reloc_entry;
3370
3371                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3372                                                    reloc->target_handle);
3373                 if (target_obj == NULL) {
3374                         i915_gem_object_unpin(obj);
3375                         return -EBADF;
3376                 }
3377                 target_obj_priv = to_intel_bo(target_obj);
3378
3379 #if WATCH_RELOC
3380                 DRM_INFO("%s: obj %p offset %08x target %d "
3381                          "read %08x write %08x gtt %08x "
3382                          "presumed %08x delta %08x\n",
3383                          __func__,
3384                          obj,
3385                          (int) reloc->offset,
3386                          (int) reloc->target_handle,
3387                          (int) reloc->read_domains,
3388                          (int) reloc->write_domain,
3389                          (int) target_obj_priv->gtt_offset,
3390                          (int) reloc->presumed_offset,
3391                          reloc->delta);
3392 #endif
3393
3394                 /* The target buffer should have appeared before us in the
3395                  * exec_object list, so it should have a GTT space bound by now.
3396                  */
3397                 if (target_obj_priv->gtt_space == NULL) {
3398                         DRM_ERROR("No GTT space found for object %d\n",
3399                                   reloc->target_handle);
3400                         drm_gem_object_unreference(target_obj);
3401                         i915_gem_object_unpin(obj);
3402                         return -EINVAL;
3403                 }
3404
3405                 /* Validate that the target is in a valid r/w GPU domain */
3406                 if (reloc->write_domain & (reloc->write_domain - 1)) {
3407                         DRM_ERROR("reloc with multiple write domains: "
3408                                   "obj %p target %d offset %d "
3409                                   "read %08x write %08x",
3410                                   obj, reloc->target_handle,
3411                                   (int) reloc->offset,
3412                                   reloc->read_domains,
3413                                   reloc->write_domain);
3414                         return -EINVAL;
3415                 }
3416                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3417                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3418                         DRM_ERROR("reloc with read/write CPU domains: "
3419                                   "obj %p target %d offset %d "
3420                                   "read %08x write %08x",
3421                                   obj, reloc->target_handle,
3422                                   (int) reloc->offset,
3423                                   reloc->read_domains,
3424                                   reloc->write_domain);
3425                         drm_gem_object_unreference(target_obj);
3426                         i915_gem_object_unpin(obj);
3427                         return -EINVAL;
3428                 }
3429                 if (reloc->write_domain && target_obj->pending_write_domain &&
3430                     reloc->write_domain != target_obj->pending_write_domain) {
3431                         DRM_ERROR("Write domain conflict: "
3432                                   "obj %p target %d offset %d "
3433                                   "new %08x old %08x\n",
3434                                   obj, reloc->target_handle,
3435                                   (int) reloc->offset,
3436                                   reloc->write_domain,
3437                                   target_obj->pending_write_domain);
3438                         drm_gem_object_unreference(target_obj);
3439                         i915_gem_object_unpin(obj);
3440                         return -EINVAL;
3441                 }
3442
3443                 target_obj->pending_read_domains |= reloc->read_domains;
3444                 target_obj->pending_write_domain |= reloc->write_domain;
3445
3446                 /* If the relocation already has the right value in it, no
3447                  * more work needs to be done.
3448                  */
3449                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3450                         drm_gem_object_unreference(target_obj);
3451                         continue;
3452                 }
3453
3454                 /* Check that the relocation address is valid... */
3455                 if (reloc->offset > obj->size - 4) {
3456                         DRM_ERROR("Relocation beyond object bounds: "
3457                                   "obj %p target %d offset %d size %d.\n",
3458                                   obj, reloc->target_handle,
3459                                   (int) reloc->offset, (int) obj->size);
3460                         drm_gem_object_unreference(target_obj);
3461                         i915_gem_object_unpin(obj);
3462                         return -EINVAL;
3463                 }
3464                 if (reloc->offset & 3) {
3465                         DRM_ERROR("Relocation not 4-byte aligned: "
3466                                   "obj %p target %d offset %d.\n",
3467                                   obj, reloc->target_handle,
3468                                   (int) reloc->offset);
3469                         drm_gem_object_unreference(target_obj);
3470                         i915_gem_object_unpin(obj);
3471                         return -EINVAL;
3472                 }
3473
3474                 /* and points to somewhere within the target object. */
3475                 if (reloc->delta >= target_obj->size) {
3476                         DRM_ERROR("Relocation beyond target object bounds: "
3477                                   "obj %p target %d delta %d size %d.\n",
3478                                   obj, reloc->target_handle,
3479                                   (int) reloc->delta, (int) target_obj->size);
3480                         drm_gem_object_unreference(target_obj);
3481                         i915_gem_object_unpin(obj);
3482                         return -EINVAL;
3483                 }
3484
3485                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3486                 if (ret != 0) {
3487                         drm_gem_object_unreference(target_obj);
3488                         i915_gem_object_unpin(obj);
3489                         return -EINVAL;
3490                 }
3491
3492                 /* Map the page containing the relocation we're going to
3493                  * perform.
3494                  */
3495                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3496                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3497                                                       (reloc_offset &
3498                                                        ~(PAGE_SIZE - 1)),
3499                                                       KM_USER0);
3500                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3501                                                    (reloc_offset & (PAGE_SIZE - 1)));
3502                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3503
3504 #if WATCH_BUF
3505                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3506                           obj, (unsigned int) reloc->offset,
3507                           readl(reloc_entry), reloc_val);
3508 #endif
3509                 writel(reloc_val, reloc_entry);
3510                 io_mapping_unmap_atomic(reloc_page, KM_USER0);
3511
3512                 /* The updated presumed offset for this entry will be
3513                  * copied back out to the user.
3514                  */
3515                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3516
3517                 drm_gem_object_unreference(target_obj);
3518         }
3519
3520 #if WATCH_BUF
3521         if (0)
3522                 i915_gem_dump_object(obj, 128, __func__, ~0);
3523 #endif
3524         return 0;
3525 }
3526
3527 /* Throttle our rendering by waiting until the ring has completed our requests
3528  * emitted over 20 msec ago.
3529  *
3530  * Note that if we were to use the current jiffies each time around the loop,
3531  * we wouldn't escape the function with any frames outstanding if the time to
3532  * render a frame was over 20ms.
3533  *
3534  * This should get us reasonable parallelism between CPU and GPU but also
3535  * relatively low latency when blocking on a particular request to finish.
3536  */
3537 static int
3538 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3539 {
3540         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3541         int ret = 0;
3542         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3543
3544         mutex_lock(&dev->struct_mutex);
3545         while (!list_empty(&i915_file_priv->mm.request_list)) {
3546                 struct drm_i915_gem_request *request;
3547
3548                 request = list_first_entry(&i915_file_priv->mm.request_list,
3549                                            struct drm_i915_gem_request,
3550                                            client_list);
3551
3552                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3553                         break;
3554
3555                 ret = i915_wait_request(dev, request->seqno, request->ring);
3556                 if (ret != 0)
3557                         break;
3558         }
3559         mutex_unlock(&dev->struct_mutex);
3560
3561         return ret;
3562 }
3563
3564 static int
3565 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3566                               uint32_t buffer_count,
3567                               struct drm_i915_gem_relocation_entry **relocs)
3568 {
3569         uint32_t reloc_count = 0, reloc_index = 0, i;
3570         int ret;
3571
3572         *relocs = NULL;
3573         for (i = 0; i < buffer_count; i++) {
3574                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3575                         return -EINVAL;
3576                 reloc_count += exec_list[i].relocation_count;
3577         }
3578
3579         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3580         if (*relocs == NULL) {
3581                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3582                 return -ENOMEM;
3583         }
3584
3585         for (i = 0; i < buffer_count; i++) {
3586                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3587
3588                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3589
3590                 ret = copy_from_user(&(*relocs)[reloc_index],
3591                                      user_relocs,
3592                                      exec_list[i].relocation_count *
3593                                      sizeof(**relocs));
3594                 if (ret != 0) {
3595                         drm_free_large(*relocs);
3596                         *relocs = NULL;
3597                         return -EFAULT;
3598                 }
3599
3600                 reloc_index += exec_list[i].relocation_count;
3601         }
3602
3603         return 0;
3604 }
3605
3606 static int
3607 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3608                             uint32_t buffer_count,
3609                             struct drm_i915_gem_relocation_entry *relocs)
3610 {
3611         uint32_t reloc_count = 0, i;
3612         int ret = 0;
3613
3614         if (relocs == NULL)
3615             return 0;
3616
3617         for (i = 0; i < buffer_count; i++) {
3618                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3619                 int unwritten;
3620
3621                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3622
3623                 unwritten = copy_to_user(user_relocs,
3624                                          &relocs[reloc_count],
3625                                          exec_list[i].relocation_count *
3626                                          sizeof(*relocs));
3627
3628                 if (unwritten) {
3629                         ret = -EFAULT;
3630                         goto err;
3631                 }
3632
3633                 reloc_count += exec_list[i].relocation_count;
3634         }
3635
3636 err:
3637         drm_free_large(relocs);
3638
3639         return ret;
3640 }
3641
3642 static int
3643 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3644                            uint64_t exec_offset)
3645 {
3646         uint32_t exec_start, exec_len;
3647
3648         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3649         exec_len = (uint32_t) exec->batch_len;
3650
3651         if ((exec_start | exec_len) & 0x7)
3652                 return -EINVAL;
3653
3654         if (!exec_start)
3655                 return -EINVAL;
3656
3657         return 0;
3658 }
3659
3660 static int
3661 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3662                                struct drm_gem_object **object_list,
3663                                int count)
3664 {
3665         drm_i915_private_t *dev_priv = dev->dev_private;
3666         struct drm_i915_gem_object *obj_priv;
3667         DEFINE_WAIT(wait);
3668         int i, ret = 0;
3669
3670         for (;;) {
3671                 prepare_to_wait(&dev_priv->pending_flip_queue,
3672                                 &wait, TASK_INTERRUPTIBLE);
3673                 for (i = 0; i < count; i++) {
3674                         obj_priv = to_intel_bo(object_list[i]);
3675                         if (atomic_read(&obj_priv->pending_flip) > 0)
3676                                 break;
3677                 }
3678                 if (i == count)
3679                         break;
3680
3681                 if (!signal_pending(current)) {
3682                         mutex_unlock(&dev->struct_mutex);
3683                         schedule();
3684                         mutex_lock(&dev->struct_mutex);
3685                         continue;
3686                 }
3687                 ret = -ERESTARTSYS;
3688                 break;
3689         }
3690         finish_wait(&dev_priv->pending_flip_queue, &wait);
3691
3692         return ret;
3693 }
3694
3695
3696 int
3697 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3698                        struct drm_file *file_priv,
3699                        struct drm_i915_gem_execbuffer2 *args,
3700                        struct drm_i915_gem_exec_object2 *exec_list)
3701 {
3702         drm_i915_private_t *dev_priv = dev->dev_private;
3703         struct drm_gem_object **object_list = NULL;
3704         struct drm_gem_object *batch_obj;
3705         struct drm_i915_gem_object *obj_priv;
3706         struct drm_clip_rect *cliprects = NULL;
3707         struct drm_i915_gem_relocation_entry *relocs = NULL;
3708         int ret = 0, ret2, i, pinned = 0;
3709         uint64_t exec_offset;
3710         uint32_t seqno, flush_domains, reloc_index;
3711         int pin_tries, flips;
3712
3713         struct intel_ring_buffer *ring = NULL;
3714
3715 #if WATCH_EXEC
3716         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3717                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3718 #endif
3719         if (args->flags & I915_EXEC_BSD) {
3720                 if (!HAS_BSD(dev)) {
3721                         DRM_ERROR("execbuf with wrong flag\n");
3722                         return -EINVAL;
3723                 }
3724                 ring = &dev_priv->bsd_ring;
3725         } else {
3726                 ring = &dev_priv->render_ring;
3727         }
3728
3729         if (args->buffer_count < 1) {
3730                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3731                 return -EINVAL;
3732         }
3733         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3734         if (object_list == NULL) {
3735                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3736                           args->buffer_count);
3737                 ret = -ENOMEM;
3738                 goto pre_mutex_err;
3739         }
3740
3741         if (args->num_cliprects != 0) {
3742                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3743                                     GFP_KERNEL);
3744                 if (cliprects == NULL) {
3745                         ret = -ENOMEM;
3746                         goto pre_mutex_err;
3747                 }
3748
3749                 ret = copy_from_user(cliprects,
3750                                      (struct drm_clip_rect __user *)
3751                                      (uintptr_t) args->cliprects_ptr,
3752                                      sizeof(*cliprects) * args->num_cliprects);
3753                 if (ret != 0) {
3754                         DRM_ERROR("copy %d cliprects failed: %d\n",
3755                                   args->num_cliprects, ret);
3756                         goto pre_mutex_err;
3757                 }
3758         }
3759
3760         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3761                                             &relocs);
3762         if (ret != 0)
3763                 goto pre_mutex_err;
3764
3765         mutex_lock(&dev->struct_mutex);
3766
3767         i915_verify_inactive(dev, __FILE__, __LINE__);
3768
3769         if (atomic_read(&dev_priv->mm.wedged)) {
3770                 mutex_unlock(&dev->struct_mutex);
3771                 ret = -EIO;
3772                 goto pre_mutex_err;
3773         }
3774
3775         if (dev_priv->mm.suspended) {
3776                 mutex_unlock(&dev->struct_mutex);
3777                 ret = -EBUSY;
3778                 goto pre_mutex_err;
3779         }
3780
3781         /* Look up object handles */
3782         flips = 0;
3783         for (i = 0; i < args->buffer_count; i++) {
3784                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3785                                                        exec_list[i].handle);
3786                 if (object_list[i] == NULL) {
3787                         DRM_ERROR("Invalid object handle %d at index %d\n",
3788                                    exec_list[i].handle, i);
3789                         /* prevent error path from reading uninitialized data */
3790                         args->buffer_count = i + 1;
3791                         ret = -EBADF;
3792                         goto err;
3793                 }
3794
3795                 obj_priv = to_intel_bo(object_list[i]);
3796                 if (obj_priv->in_execbuffer) {
3797                         DRM_ERROR("Object %p appears more than once in object list\n",
3798                                    object_list[i]);
3799                         /* prevent error path from reading uninitialized data */
3800                         args->buffer_count = i + 1;
3801                         ret = -EBADF;
3802                         goto err;
3803                 }
3804                 obj_priv->in_execbuffer = true;
3805                 flips += atomic_read(&obj_priv->pending_flip);
3806         }
3807
3808         if (flips > 0) {
3809                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3810                                                      args->buffer_count);
3811                 if (ret)
3812                         goto err;
3813         }
3814
3815         /* Pin and relocate */
3816         for (pin_tries = 0; ; pin_tries++) {
3817                 ret = 0;
3818                 reloc_index = 0;
3819
3820                 for (i = 0; i < args->buffer_count; i++) {
3821                         object_list[i]->pending_read_domains = 0;
3822                         object_list[i]->pending_write_domain = 0;
3823                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3824                                                                file_priv,
3825                                                                &exec_list[i],
3826                                                                &relocs[reloc_index]);
3827                         if (ret)
3828                                 break;
3829                         pinned = i + 1;
3830                         reloc_index += exec_list[i].relocation_count;
3831                 }
3832                 /* success */
3833                 if (ret == 0)
3834                         break;
3835
3836                 /* error other than GTT full, or we've already tried again */
3837                 if (ret != -ENOSPC || pin_tries >= 1) {
3838                         if (ret != -ERESTARTSYS) {
3839                                 unsigned long long total_size = 0;
3840                                 int num_fences = 0;
3841                                 for (i = 0; i < args->buffer_count; i++) {
3842                                         obj_priv = to_intel_bo(object_list[i]);
3843
3844                                         total_size += object_list[i]->size;
3845                                         num_fences +=
3846                                                 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3847                                                 obj_priv->tiling_mode != I915_TILING_NONE;
3848                                 }
3849                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3850                                           pinned+1, args->buffer_count,
3851                                           total_size, num_fences,
3852                                           ret);
3853                                 DRM_ERROR("%d objects [%d pinned], "
3854                                           "%d object bytes [%d pinned], "
3855                                           "%d/%d gtt bytes\n",
3856                                           atomic_read(&dev->object_count),
3857                                           atomic_read(&dev->pin_count),
3858                                           atomic_read(&dev->object_memory),
3859                                           atomic_read(&dev->pin_memory),
3860                                           atomic_read(&dev->gtt_memory),
3861                                           dev->gtt_total);
3862                         }
3863                         goto err;
3864                 }
3865
3866                 /* unpin all of our buffers */
3867                 for (i = 0; i < pinned; i++)
3868                         i915_gem_object_unpin(object_list[i]);
3869                 pinned = 0;
3870
3871                 /* evict everyone we can from the aperture */
3872                 ret = i915_gem_evict_everything(dev);
3873                 if (ret && ret != -ENOSPC)
3874                         goto err;
3875         }
3876
3877         /* Set the pending read domains for the batch buffer to COMMAND */
3878         batch_obj = object_list[args->buffer_count-1];
3879         if (batch_obj->pending_write_domain) {
3880                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3881                 ret = -EINVAL;
3882                 goto err;
3883         }
3884         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3885
3886         /* Sanity check the batch buffer, prior to moving objects */
3887         exec_offset = exec_list[args->buffer_count - 1].offset;
3888         ret = i915_gem_check_execbuffer (args, exec_offset);
3889         if (ret != 0) {
3890                 DRM_ERROR("execbuf with invalid offset/length\n");
3891                 goto err;
3892         }
3893
3894         i915_verify_inactive(dev, __FILE__, __LINE__);
3895
3896         /* Zero the global flush/invalidate flags. These
3897          * will be modified as new domains are computed
3898          * for each object
3899          */
3900         dev->invalidate_domains = 0;
3901         dev->flush_domains = 0;
3902         dev_priv->flush_rings = 0;
3903
3904         for (i = 0; i < args->buffer_count; i++) {
3905                 struct drm_gem_object *obj = object_list[i];
3906
3907                 /* Compute new gpu domains and update invalidate/flush */
3908                 i915_gem_object_set_to_gpu_domain(obj);
3909         }
3910
3911         i915_verify_inactive(dev, __FILE__, __LINE__);
3912
3913         if (dev->invalidate_domains | dev->flush_domains) {
3914 #if WATCH_EXEC
3915                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3916                           __func__,
3917                          dev->invalidate_domains,
3918                          dev->flush_domains);
3919 #endif
3920                 i915_gem_flush(dev,
3921                                dev->invalidate_domains,
3922                                dev->flush_domains);
3923                 if (dev_priv->flush_rings & FLUSH_RENDER_RING)
3924                         (void)i915_add_request(dev, file_priv,
3925                                                dev->flush_domains,
3926                                                &dev_priv->render_ring);
3927                 if (dev_priv->flush_rings & FLUSH_BSD_RING)
3928                         (void)i915_add_request(dev, file_priv,
3929                                                dev->flush_domains,
3930                                                &dev_priv->bsd_ring);
3931         }
3932
3933         for (i = 0; i < args->buffer_count; i++) {
3934                 struct drm_gem_object *obj = object_list[i];
3935                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3936                 uint32_t old_write_domain = obj->write_domain;
3937
3938                 obj->write_domain = obj->pending_write_domain;
3939                 if (obj->write_domain)
3940                         list_move_tail(&obj_priv->gpu_write_list,
3941                                        &dev_priv->mm.gpu_write_list);
3942                 else
3943                         list_del_init(&obj_priv->gpu_write_list);
3944
3945                 trace_i915_gem_object_change_domain(obj,
3946                                                     obj->read_domains,
3947                                                     old_write_domain);
3948         }
3949
3950         i915_verify_inactive(dev, __FILE__, __LINE__);
3951
3952 #if WATCH_COHERENCY
3953         for (i = 0; i < args->buffer_count; i++) {
3954                 i915_gem_object_check_coherency(object_list[i],
3955                                                 exec_list[i].handle);
3956         }
3957 #endif
3958
3959 #if WATCH_EXEC
3960         i915_gem_dump_object(batch_obj,
3961                               args->batch_len,
3962                               __func__,
3963                               ~0);
3964 #endif
3965
3966         /* Exec the batchbuffer */
3967         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3968                         cliprects, exec_offset);
3969         if (ret) {
3970                 DRM_ERROR("dispatch failed %d\n", ret);
3971                 goto err;
3972         }
3973
3974         /*
3975          * Ensure that the commands in the batch buffer are
3976          * finished before the interrupt fires
3977          */
3978         flush_domains = i915_retire_commands(dev, ring);
3979
3980         i915_verify_inactive(dev, __FILE__, __LINE__);
3981
3982         /*
3983          * Get a seqno representing the execution of the current buffer,
3984          * which we can wait on.  We would like to mitigate these interrupts,
3985          * likely by only creating seqnos occasionally (so that we have
3986          * *some* interrupts representing completion of buffers that we can
3987          * wait on when trying to clear up gtt space).
3988          */
3989         seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3990         BUG_ON(seqno == 0);
3991         for (i = 0; i < args->buffer_count; i++) {
3992                 struct drm_gem_object *obj = object_list[i];
3993                 obj_priv = to_intel_bo(obj);
3994
3995                 i915_gem_object_move_to_active(obj, seqno, ring);
3996 #if WATCH_LRU
3997                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3998 #endif
3999         }
4000 #if WATCH_LRU
4001         i915_dump_lru(dev, __func__);
4002 #endif
4003
4004         i915_verify_inactive(dev, __FILE__, __LINE__);
4005
4006 err:
4007         for (i = 0; i < pinned; i++)
4008                 i915_gem_object_unpin(object_list[i]);
4009
4010         for (i = 0; i < args->buffer_count; i++) {
4011                 if (object_list[i]) {
4012                         obj_priv = to_intel_bo(object_list[i]);
4013                         obj_priv->in_execbuffer = false;
4014                 }
4015                 drm_gem_object_unreference(object_list[i]);
4016         }
4017
4018         mutex_unlock(&dev->struct_mutex);
4019
4020 pre_mutex_err:
4021         /* Copy the updated relocations out regardless of current error
4022          * state.  Failure to update the relocs would mean that the next
4023          * time userland calls execbuf, it would do so with presumed offset
4024          * state that didn't match the actual object state.
4025          */
4026         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4027                                            relocs);
4028         if (ret2 != 0) {
4029                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4030
4031                 if (ret == 0)
4032                         ret = ret2;
4033         }
4034
4035         drm_free_large(object_list);
4036         kfree(cliprects);
4037
4038         return ret;
4039 }
4040
4041 /*
4042  * Legacy execbuffer just creates an exec2 list from the original exec object
4043  * list array and passes it to the real function.
4044  */
4045 int
4046 i915_gem_execbuffer(struct drm_device *dev, void *data,
4047                     struct drm_file *file_priv)
4048 {
4049         struct drm_i915_gem_execbuffer *args = data;
4050         struct drm_i915_gem_execbuffer2 exec2;
4051         struct drm_i915_gem_exec_object *exec_list = NULL;
4052         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4053         int ret, i;
4054
4055 #if WATCH_EXEC
4056         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4057                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4058 #endif
4059
4060         if (args->buffer_count < 1) {
4061                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4062                 return -EINVAL;
4063         }
4064
4065         /* Copy in the exec list from userland */
4066         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4067         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4068         if (exec_list == NULL || exec2_list == NULL) {
4069                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4070                           args->buffer_count);
4071                 drm_free_large(exec_list);
4072                 drm_free_large(exec2_list);
4073                 return -ENOMEM;
4074         }
4075         ret = copy_from_user(exec_list,
4076                              (struct drm_i915_relocation_entry __user *)
4077                              (uintptr_t) args->buffers_ptr,
4078                              sizeof(*exec_list) * args->buffer_count);
4079         if (ret != 0) {
4080                 DRM_ERROR("copy %d exec entries failed %d\n",
4081                           args->buffer_count, ret);
4082                 drm_free_large(exec_list);
4083                 drm_free_large(exec2_list);
4084                 return -EFAULT;
4085         }
4086
4087         for (i = 0; i < args->buffer_count; i++) {
4088                 exec2_list[i].handle = exec_list[i].handle;
4089                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4090                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4091                 exec2_list[i].alignment = exec_list[i].alignment;
4092                 exec2_list[i].offset = exec_list[i].offset;
4093                 if (!IS_I965G(dev))
4094                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4095                 else
4096                         exec2_list[i].flags = 0;
4097         }
4098
4099         exec2.buffers_ptr = args->buffers_ptr;
4100         exec2.buffer_count = args->buffer_count;
4101         exec2.batch_start_offset = args->batch_start_offset;
4102         exec2.batch_len = args->batch_len;
4103         exec2.DR1 = args->DR1;
4104         exec2.DR4 = args->DR4;
4105         exec2.num_cliprects = args->num_cliprects;
4106         exec2.cliprects_ptr = args->cliprects_ptr;
4107         exec2.flags = I915_EXEC_RENDER;
4108
4109         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4110         if (!ret) {
4111                 /* Copy the new buffer offsets back to the user's exec list. */
4112                 for (i = 0; i < args->buffer_count; i++)
4113                         exec_list[i].offset = exec2_list[i].offset;
4114                 /* ... and back out to userspace */
4115                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4116                                    (uintptr_t) args->buffers_ptr,
4117                                    exec_list,
4118                                    sizeof(*exec_list) * args->buffer_count);
4119                 if (ret) {
4120                         ret = -EFAULT;
4121                         DRM_ERROR("failed to copy %d exec entries "
4122                                   "back to user (%d)\n",
4123                                   args->buffer_count, ret);
4124                 }
4125         }
4126
4127         drm_free_large(exec_list);
4128         drm_free_large(exec2_list);
4129         return ret;
4130 }
4131
4132 int
4133 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4134                      struct drm_file *file_priv)
4135 {
4136         struct drm_i915_gem_execbuffer2 *args = data;
4137         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4138         int ret;
4139
4140 #if WATCH_EXEC
4141         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4142                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4143 #endif
4144
4145         if (args->buffer_count < 1) {
4146                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4147                 return -EINVAL;
4148         }
4149
4150         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4151         if (exec2_list == NULL) {
4152                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4153                           args->buffer_count);
4154                 return -ENOMEM;
4155         }
4156         ret = copy_from_user(exec2_list,
4157                              (struct drm_i915_relocation_entry __user *)
4158                              (uintptr_t) args->buffers_ptr,
4159                              sizeof(*exec2_list) * args->buffer_count);
4160         if (ret != 0) {
4161                 DRM_ERROR("copy %d exec entries failed %d\n",
4162                           args->buffer_count, ret);
4163                 drm_free_large(exec2_list);
4164                 return -EFAULT;
4165         }
4166
4167         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4168         if (!ret) {
4169                 /* Copy the new buffer offsets back to the user's exec list. */
4170                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4171                                    (uintptr_t) args->buffers_ptr,
4172                                    exec2_list,
4173                                    sizeof(*exec2_list) * args->buffer_count);
4174                 if (ret) {
4175                         ret = -EFAULT;
4176                         DRM_ERROR("failed to copy %d exec entries "
4177                                   "back to user (%d)\n",
4178                                   args->buffer_count, ret);
4179                 }
4180         }
4181
4182         drm_free_large(exec2_list);
4183         return ret;
4184 }
4185
4186 int
4187 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4188 {
4189         struct drm_device *dev = obj->dev;
4190         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4191         int ret;
4192
4193         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4194
4195         i915_verify_inactive(dev, __FILE__, __LINE__);
4196
4197         if (obj_priv->gtt_space != NULL) {
4198                 if (alignment == 0)
4199                         alignment = i915_gem_get_gtt_alignment(obj);
4200                 if (obj_priv->gtt_offset & (alignment - 1)) {
4201                         WARN(obj_priv->pin_count,
4202                              "bo is already pinned with incorrect alignment:"
4203                              " offset=%x, req.alignment=%x\n",
4204                              obj_priv->gtt_offset, alignment);
4205                         ret = i915_gem_object_unbind(obj);
4206                         if (ret)
4207                                 return ret;
4208                 }
4209         }
4210
4211         if (obj_priv->gtt_space == NULL) {
4212                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4213                 if (ret)
4214                         return ret;
4215         }
4216
4217         obj_priv->pin_count++;
4218
4219         /* If the object is not active and not pending a flush,
4220          * remove it from the inactive list
4221          */
4222         if (obj_priv->pin_count == 1) {
4223                 atomic_inc(&dev->pin_count);
4224                 atomic_add(obj->size, &dev->pin_memory);
4225                 if (!obj_priv->active &&
4226                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4227                     !list_empty(&obj_priv->list))
4228                         list_del_init(&obj_priv->list);
4229         }
4230         i915_verify_inactive(dev, __FILE__, __LINE__);
4231
4232         return 0;
4233 }
4234
4235 void
4236 i915_gem_object_unpin(struct drm_gem_object *obj)
4237 {
4238         struct drm_device *dev = obj->dev;
4239         drm_i915_private_t *dev_priv = dev->dev_private;
4240         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4241
4242         i915_verify_inactive(dev, __FILE__, __LINE__);
4243         obj_priv->pin_count--;
4244         BUG_ON(obj_priv->pin_count < 0);
4245         BUG_ON(obj_priv->gtt_space == NULL);
4246
4247         /* If the object is no longer pinned, and is
4248          * neither active nor being flushed, then stick it on
4249          * the inactive list
4250          */
4251         if (obj_priv->pin_count == 0) {
4252                 if (!obj_priv->active &&
4253                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4254                         list_move_tail(&obj_priv->list,
4255                                        &dev_priv->mm.inactive_list);
4256                 atomic_dec(&dev->pin_count);
4257                 atomic_sub(obj->size, &dev->pin_memory);
4258         }
4259         i915_verify_inactive(dev, __FILE__, __LINE__);
4260 }
4261
4262 int
4263 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4264                    struct drm_file *file_priv)
4265 {
4266         struct drm_i915_gem_pin *args = data;
4267         struct drm_gem_object *obj;
4268         struct drm_i915_gem_object *obj_priv;
4269         int ret;
4270
4271         mutex_lock(&dev->struct_mutex);
4272
4273         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4274         if (obj == NULL) {
4275                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4276                           args->handle);
4277                 mutex_unlock(&dev->struct_mutex);
4278                 return -EBADF;
4279         }
4280         obj_priv = to_intel_bo(obj);
4281
4282         if (obj_priv->madv != I915_MADV_WILLNEED) {
4283                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4284                 drm_gem_object_unreference(obj);
4285                 mutex_unlock(&dev->struct_mutex);
4286                 return -EINVAL;
4287         }
4288
4289         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4290                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4291                           args->handle);
4292                 drm_gem_object_unreference(obj);
4293                 mutex_unlock(&dev->struct_mutex);
4294                 return -EINVAL;
4295         }
4296
4297         obj_priv->user_pin_count++;
4298         obj_priv->pin_filp = file_priv;
4299         if (obj_priv->user_pin_count == 1) {
4300                 ret = i915_gem_object_pin(obj, args->alignment);
4301                 if (ret != 0) {
4302                         drm_gem_object_unreference(obj);
4303                         mutex_unlock(&dev->struct_mutex);
4304                         return ret;
4305                 }
4306         }
4307
4308         /* XXX - flush the CPU caches for pinned objects
4309          * as the X server doesn't manage domains yet
4310          */
4311         i915_gem_object_flush_cpu_write_domain(obj);
4312         args->offset = obj_priv->gtt_offset;
4313         drm_gem_object_unreference(obj);
4314         mutex_unlock(&dev->struct_mutex);
4315
4316         return 0;
4317 }
4318
4319 int
4320 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4321                      struct drm_file *file_priv)
4322 {
4323         struct drm_i915_gem_pin *args = data;
4324         struct drm_gem_object *obj;
4325         struct drm_i915_gem_object *obj_priv;
4326
4327         mutex_lock(&dev->struct_mutex);
4328
4329         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4330         if (obj == NULL) {
4331                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4332                           args->handle);
4333                 mutex_unlock(&dev->struct_mutex);
4334                 return -EBADF;
4335         }
4336
4337         obj_priv = to_intel_bo(obj);
4338         if (obj_priv->pin_filp != file_priv) {
4339                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4340                           args->handle);
4341                 drm_gem_object_unreference(obj);
4342                 mutex_unlock(&dev->struct_mutex);
4343                 return -EINVAL;
4344         }
4345         obj_priv->user_pin_count--;
4346         if (obj_priv->user_pin_count == 0) {
4347                 obj_priv->pin_filp = NULL;
4348                 i915_gem_object_unpin(obj);
4349         }
4350
4351         drm_gem_object_unreference(obj);
4352         mutex_unlock(&dev->struct_mutex);
4353         return 0;
4354 }
4355
4356 int
4357 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4358                     struct drm_file *file_priv)
4359 {
4360         struct drm_i915_gem_busy *args = data;
4361         struct drm_gem_object *obj;
4362         struct drm_i915_gem_object *obj_priv;
4363
4364         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4365         if (obj == NULL) {
4366                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4367                           args->handle);
4368                 return -EBADF;
4369         }
4370
4371         mutex_lock(&dev->struct_mutex);
4372
4373         /* Count all active objects as busy, even if they are currently not used
4374          * by the gpu. Users of this interface expect objects to eventually
4375          * become non-busy without any further actions, therefore emit any
4376          * necessary flushes here.
4377          */
4378         obj_priv = to_intel_bo(obj);
4379         args->busy = obj_priv->active;
4380         if (args->busy) {
4381                 /* Unconditionally flush objects, even when the gpu still uses this
4382                  * object. Userspace calling this function indicates that it wants to
4383                  * use this buffer rather sooner than later, so issuing the required
4384                  * flush earlier is beneficial.
4385                  */
4386                 if (obj->write_domain) {
4387                         i915_gem_flush(dev, 0, obj->write_domain);
4388                         (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring);
4389                 }
4390
4391                 /* Update the active list for the hardware's current position.
4392                  * Otherwise this only updates on a delayed timer or when irqs
4393                  * are actually unmasked, and our working set ends up being
4394                  * larger than required.
4395                  */
4396                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4397
4398                 args->busy = obj_priv->active;
4399         }
4400
4401         drm_gem_object_unreference(obj);
4402         mutex_unlock(&dev->struct_mutex);
4403         return 0;
4404 }
4405
4406 int
4407 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4408                         struct drm_file *file_priv)
4409 {
4410     return i915_gem_ring_throttle(dev, file_priv);
4411 }
4412
4413 int
4414 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4415                        struct drm_file *file_priv)
4416 {
4417         struct drm_i915_gem_madvise *args = data;
4418         struct drm_gem_object *obj;
4419         struct drm_i915_gem_object *obj_priv;
4420
4421         switch (args->madv) {
4422         case I915_MADV_DONTNEED:
4423         case I915_MADV_WILLNEED:
4424             break;
4425         default:
4426             return -EINVAL;
4427         }
4428
4429         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4430         if (obj == NULL) {
4431                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4432                           args->handle);
4433                 return -EBADF;
4434         }
4435
4436         mutex_lock(&dev->struct_mutex);
4437         obj_priv = to_intel_bo(obj);
4438
4439         if (obj_priv->pin_count) {
4440                 drm_gem_object_unreference(obj);
4441                 mutex_unlock(&dev->struct_mutex);
4442
4443                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4444                 return -EINVAL;
4445         }
4446
4447         if (obj_priv->madv != __I915_MADV_PURGED)
4448                 obj_priv->madv = args->madv;
4449
4450         /* if the object is no longer bound, discard its backing storage */
4451         if (i915_gem_object_is_purgeable(obj_priv) &&
4452             obj_priv->gtt_space == NULL)
4453                 i915_gem_object_truncate(obj);
4454
4455         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4456
4457         drm_gem_object_unreference(obj);
4458         mutex_unlock(&dev->struct_mutex);
4459
4460         return 0;
4461 }
4462
4463 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4464                                               size_t size)
4465 {
4466         struct drm_i915_gem_object *obj;
4467
4468         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4469         if (obj == NULL)
4470                 return NULL;
4471
4472         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4473                 kfree(obj);
4474                 return NULL;
4475         }
4476
4477         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4478         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4479
4480         obj->agp_type = AGP_USER_MEMORY;
4481         obj->base.driver_private = NULL;
4482         obj->fence_reg = I915_FENCE_REG_NONE;
4483         INIT_LIST_HEAD(&obj->list);
4484         INIT_LIST_HEAD(&obj->gpu_write_list);
4485         obj->madv = I915_MADV_WILLNEED;
4486
4487         trace_i915_gem_object_create(&obj->base);
4488
4489         return &obj->base;
4490 }
4491
4492 int i915_gem_init_object(struct drm_gem_object *obj)
4493 {
4494         BUG();
4495
4496         return 0;
4497 }
4498
4499 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4500 {
4501         struct drm_device *dev = obj->dev;
4502         drm_i915_private_t *dev_priv = dev->dev_private;
4503         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4504         int ret;
4505
4506         ret = i915_gem_object_unbind(obj);
4507         if (ret == -ERESTARTSYS) {
4508                 list_move(&obj_priv->list,
4509                           &dev_priv->mm.deferred_free_list);
4510                 return;
4511         }
4512
4513         if (obj_priv->mmap_offset)
4514                 i915_gem_free_mmap_offset(obj);
4515
4516         drm_gem_object_release(obj);
4517
4518         kfree(obj_priv->page_cpu_valid);
4519         kfree(obj_priv->bit_17);
4520         kfree(obj_priv);
4521 }
4522
4523 void i915_gem_free_object(struct drm_gem_object *obj)
4524 {
4525         struct drm_device *dev = obj->dev;
4526         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4527
4528         trace_i915_gem_object_destroy(obj);
4529
4530         while (obj_priv->pin_count > 0)
4531                 i915_gem_object_unpin(obj);
4532
4533         if (obj_priv->phys_obj)
4534                 i915_gem_detach_phys_object(dev, obj);
4535
4536         i915_gem_free_object_tail(obj);
4537 }
4538
4539 /** Unbinds all inactive objects. */
4540 static int
4541 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4542 {
4543         drm_i915_private_t *dev_priv = dev->dev_private;
4544
4545         while (!list_empty(&dev_priv->mm.inactive_list)) {
4546                 struct drm_gem_object *obj;
4547                 int ret;
4548
4549                 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4550                                         struct drm_i915_gem_object,
4551                                         list)->base;
4552
4553                 ret = i915_gem_object_unbind(obj);
4554                 if (ret != 0) {
4555                         DRM_ERROR("Error unbinding object: %d\n", ret);
4556                         return ret;
4557                 }
4558         }
4559
4560         return 0;
4561 }
4562
4563 int
4564 i915_gem_idle(struct drm_device *dev)
4565 {
4566         drm_i915_private_t *dev_priv = dev->dev_private;
4567         int ret;
4568
4569         mutex_lock(&dev->struct_mutex);
4570
4571         if (dev_priv->mm.suspended ||
4572                         (dev_priv->render_ring.gem_object == NULL) ||
4573                         (HAS_BSD(dev) &&
4574                          dev_priv->bsd_ring.gem_object == NULL)) {
4575                 mutex_unlock(&dev->struct_mutex);
4576                 return 0;
4577         }
4578
4579         ret = i915_gpu_idle(dev);
4580         if (ret) {
4581                 mutex_unlock(&dev->struct_mutex);
4582                 return ret;
4583         }
4584
4585         /* Under UMS, be paranoid and evict. */
4586         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4587                 ret = i915_gem_evict_from_inactive_list(dev);
4588                 if (ret) {
4589                         mutex_unlock(&dev->struct_mutex);
4590                         return ret;
4591                 }
4592         }
4593
4594         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4595          * We need to replace this with a semaphore, or something.
4596          * And not confound mm.suspended!
4597          */
4598         dev_priv->mm.suspended = 1;
4599         del_timer(&dev_priv->hangcheck_timer);
4600
4601         i915_kernel_lost_context(dev);
4602         i915_gem_cleanup_ringbuffer(dev);
4603
4604         mutex_unlock(&dev->struct_mutex);
4605
4606         /* Cancel the retire work handler, which should be idle now. */
4607         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4608
4609         return 0;
4610 }
4611
4612 /*
4613  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4614  * over cache flushing.
4615  */
4616 static int
4617 i915_gem_init_pipe_control(struct drm_device *dev)
4618 {
4619         drm_i915_private_t *dev_priv = dev->dev_private;
4620         struct drm_gem_object *obj;
4621         struct drm_i915_gem_object *obj_priv;
4622         int ret;
4623
4624         obj = i915_gem_alloc_object(dev, 4096);
4625         if (obj == NULL) {
4626                 DRM_ERROR("Failed to allocate seqno page\n");
4627                 ret = -ENOMEM;
4628                 goto err;
4629         }
4630         obj_priv = to_intel_bo(obj);
4631         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4632
4633         ret = i915_gem_object_pin(obj, 4096);
4634         if (ret)
4635                 goto err_unref;
4636
4637         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4638         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4639         if (dev_priv->seqno_page == NULL)
4640                 goto err_unpin;
4641
4642         dev_priv->seqno_obj = obj;
4643         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4644
4645         return 0;
4646
4647 err_unpin:
4648         i915_gem_object_unpin(obj);
4649 err_unref:
4650         drm_gem_object_unreference(obj);
4651 err:
4652         return ret;
4653 }
4654
4655
4656 static void
4657 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4658 {
4659         drm_i915_private_t *dev_priv = dev->dev_private;
4660         struct drm_gem_object *obj;
4661         struct drm_i915_gem_object *obj_priv;
4662
4663         obj = dev_priv->seqno_obj;
4664         obj_priv = to_intel_bo(obj);
4665         kunmap(obj_priv->pages[0]);
4666         i915_gem_object_unpin(obj);
4667         drm_gem_object_unreference(obj);
4668         dev_priv->seqno_obj = NULL;
4669
4670         dev_priv->seqno_page = NULL;
4671 }
4672
4673 int
4674 i915_gem_init_ringbuffer(struct drm_device *dev)
4675 {
4676         drm_i915_private_t *dev_priv = dev->dev_private;
4677         int ret;
4678
4679         dev_priv->render_ring = render_ring;
4680
4681         if (!I915_NEED_GFX_HWS(dev)) {
4682                 dev_priv->render_ring.status_page.page_addr
4683                         = dev_priv->status_page_dmah->vaddr;
4684                 memset(dev_priv->render_ring.status_page.page_addr,
4685                                 0, PAGE_SIZE);
4686         }
4687
4688         if (HAS_PIPE_CONTROL(dev)) {
4689                 ret = i915_gem_init_pipe_control(dev);
4690                 if (ret)
4691                         return ret;
4692         }
4693
4694         ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4695         if (ret)
4696                 goto cleanup_pipe_control;
4697
4698         if (HAS_BSD(dev)) {
4699                 dev_priv->bsd_ring = bsd_ring;
4700                 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4701                 if (ret)
4702                         goto cleanup_render_ring;
4703         }
4704
4705         return 0;
4706
4707 cleanup_render_ring:
4708         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4709 cleanup_pipe_control:
4710         if (HAS_PIPE_CONTROL(dev))
4711                 i915_gem_cleanup_pipe_control(dev);
4712         return ret;
4713 }
4714
4715 void
4716 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4717 {
4718         drm_i915_private_t *dev_priv = dev->dev_private;
4719
4720         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4721         if (HAS_BSD(dev))
4722                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4723         if (HAS_PIPE_CONTROL(dev))
4724                 i915_gem_cleanup_pipe_control(dev);
4725 }
4726
4727 int
4728 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4729                        struct drm_file *file_priv)
4730 {
4731         drm_i915_private_t *dev_priv = dev->dev_private;
4732         int ret;
4733
4734         if (drm_core_check_feature(dev, DRIVER_MODESET))
4735                 return 0;
4736
4737         if (atomic_read(&dev_priv->mm.wedged)) {
4738                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4739                 atomic_set(&dev_priv->mm.wedged, 0);
4740         }
4741
4742         mutex_lock(&dev->struct_mutex);
4743         dev_priv->mm.suspended = 0;
4744
4745         ret = i915_gem_init_ringbuffer(dev);
4746         if (ret != 0) {
4747                 mutex_unlock(&dev->struct_mutex);
4748                 return ret;
4749         }
4750
4751         spin_lock(&dev_priv->mm.active_list_lock);
4752         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4753         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4754         spin_unlock(&dev_priv->mm.active_list_lock);
4755
4756         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4757         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4758         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4759         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4760         mutex_unlock(&dev->struct_mutex);
4761
4762         ret = drm_irq_install(dev);
4763         if (ret)
4764                 goto cleanup_ringbuffer;
4765
4766         return 0;
4767
4768 cleanup_ringbuffer:
4769         mutex_lock(&dev->struct_mutex);
4770         i915_gem_cleanup_ringbuffer(dev);
4771         dev_priv->mm.suspended = 1;
4772         mutex_unlock(&dev->struct_mutex);
4773
4774         return ret;
4775 }
4776
4777 int
4778 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4779                        struct drm_file *file_priv)
4780 {
4781         if (drm_core_check_feature(dev, DRIVER_MODESET))
4782                 return 0;
4783
4784         drm_irq_uninstall(dev);
4785         return i915_gem_idle(dev);
4786 }
4787
4788 void
4789 i915_gem_lastclose(struct drm_device *dev)
4790 {
4791         int ret;
4792
4793         if (drm_core_check_feature(dev, DRIVER_MODESET))
4794                 return;
4795
4796         ret = i915_gem_idle(dev);
4797         if (ret)
4798                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4799 }
4800
4801 void
4802 i915_gem_load(struct drm_device *dev)
4803 {
4804         int i;
4805         drm_i915_private_t *dev_priv = dev->dev_private;
4806
4807         spin_lock_init(&dev_priv->mm.active_list_lock);
4808         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4809         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4810         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4811         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4812         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4813         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4814         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4815         if (HAS_BSD(dev)) {
4816                 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4817                 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4818         }
4819         for (i = 0; i < 16; i++)
4820                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4821         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4822                           i915_gem_retire_work_handler);
4823         spin_lock(&shrink_list_lock);
4824         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4825         spin_unlock(&shrink_list_lock);
4826
4827         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4828         if (IS_GEN3(dev)) {
4829                 u32 tmp = I915_READ(MI_ARB_STATE);
4830                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4831                         /* arb state is a masked write, so set bit + bit in mask */
4832                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4833                         I915_WRITE(MI_ARB_STATE, tmp);
4834                 }
4835         }
4836
4837         /* Old X drivers will take 0-2 for front, back, depth buffers */
4838         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4839                 dev_priv->fence_reg_start = 3;
4840
4841         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4842                 dev_priv->num_fence_regs = 16;
4843         else
4844                 dev_priv->num_fence_regs = 8;
4845
4846         /* Initialize fence registers to zero */
4847         if (IS_I965G(dev)) {
4848                 for (i = 0; i < 16; i++)
4849                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4850         } else {
4851                 for (i = 0; i < 8; i++)
4852                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4853                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4854                         for (i = 0; i < 8; i++)
4855                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4856         }
4857         i915_gem_detect_bit_6_swizzle(dev);
4858         init_waitqueue_head(&dev_priv->pending_flip_queue);
4859 }
4860
4861 /*
4862  * Create a physically contiguous memory object for this object
4863  * e.g. for cursor + overlay regs
4864  */
4865 int i915_gem_init_phys_object(struct drm_device *dev,
4866                               int id, int size)
4867 {
4868         drm_i915_private_t *dev_priv = dev->dev_private;
4869         struct drm_i915_gem_phys_object *phys_obj;
4870         int ret;
4871
4872         if (dev_priv->mm.phys_objs[id - 1] || !size)
4873                 return 0;
4874
4875         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4876         if (!phys_obj)
4877                 return -ENOMEM;
4878
4879         phys_obj->id = id;
4880
4881         phys_obj->handle = drm_pci_alloc(dev, size, 0);
4882         if (!phys_obj->handle) {
4883                 ret = -ENOMEM;
4884                 goto kfree_obj;
4885         }
4886 #ifdef CONFIG_X86
4887         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4888 #endif
4889
4890         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4891
4892         return 0;
4893 kfree_obj:
4894         kfree(phys_obj);
4895         return ret;
4896 }
4897
4898 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4899 {
4900         drm_i915_private_t *dev_priv = dev->dev_private;
4901         struct drm_i915_gem_phys_object *phys_obj;
4902
4903         if (!dev_priv->mm.phys_objs[id - 1])
4904                 return;
4905
4906         phys_obj = dev_priv->mm.phys_objs[id - 1];
4907         if (phys_obj->cur_obj) {
4908                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4909         }
4910
4911 #ifdef CONFIG_X86
4912         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4913 #endif
4914         drm_pci_free(dev, phys_obj->handle);
4915         kfree(phys_obj);
4916         dev_priv->mm.phys_objs[id - 1] = NULL;
4917 }
4918
4919 void i915_gem_free_all_phys_object(struct drm_device *dev)
4920 {
4921         int i;
4922
4923         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4924                 i915_gem_free_phys_object(dev, i);
4925 }
4926
4927 void i915_gem_detach_phys_object(struct drm_device *dev,
4928                                  struct drm_gem_object *obj)
4929 {
4930         struct drm_i915_gem_object *obj_priv;
4931         int i;
4932         int ret;
4933         int page_count;
4934
4935         obj_priv = to_intel_bo(obj);
4936         if (!obj_priv->phys_obj)
4937                 return;
4938
4939         ret = i915_gem_object_get_pages(obj, 0);
4940         if (ret)
4941                 goto out;
4942
4943         page_count = obj->size / PAGE_SIZE;
4944
4945         for (i = 0; i < page_count; i++) {
4946                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4947                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4948
4949                 memcpy(dst, src, PAGE_SIZE);
4950                 kunmap_atomic(dst, KM_USER0);
4951         }
4952         drm_clflush_pages(obj_priv->pages, page_count);
4953         drm_agp_chipset_flush(dev);
4954
4955         i915_gem_object_put_pages(obj);
4956 out:
4957         obj_priv->phys_obj->cur_obj = NULL;
4958         obj_priv->phys_obj = NULL;
4959 }
4960
4961 int
4962 i915_gem_attach_phys_object(struct drm_device *dev,
4963                             struct drm_gem_object *obj, int id)
4964 {
4965         drm_i915_private_t *dev_priv = dev->dev_private;
4966         struct drm_i915_gem_object *obj_priv;
4967         int ret = 0;
4968         int page_count;
4969         int i;
4970
4971         if (id > I915_MAX_PHYS_OBJECT)
4972                 return -EINVAL;
4973
4974         obj_priv = to_intel_bo(obj);
4975
4976         if (obj_priv->phys_obj) {
4977                 if (obj_priv->phys_obj->id == id)
4978                         return 0;
4979                 i915_gem_detach_phys_object(dev, obj);
4980         }
4981
4982
4983         /* create a new object */
4984         if (!dev_priv->mm.phys_objs[id - 1]) {
4985                 ret = i915_gem_init_phys_object(dev, id,
4986                                                 obj->size);
4987                 if (ret) {
4988                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4989                         goto out;
4990                 }
4991         }
4992
4993         /* bind to the object */
4994         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4995         obj_priv->phys_obj->cur_obj = obj;
4996
4997         ret = i915_gem_object_get_pages(obj, 0);
4998         if (ret) {
4999                 DRM_ERROR("failed to get page list\n");
5000                 goto out;
5001         }
5002
5003         page_count = obj->size / PAGE_SIZE;
5004
5005         for (i = 0; i < page_count; i++) {
5006                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
5007                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5008
5009                 memcpy(dst, src, PAGE_SIZE);
5010                 kunmap_atomic(src, KM_USER0);
5011         }
5012
5013         i915_gem_object_put_pages(obj);
5014
5015         return 0;
5016 out:
5017         return ret;
5018 }
5019
5020 static int
5021 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5022                      struct drm_i915_gem_pwrite *args,
5023                      struct drm_file *file_priv)
5024 {
5025         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5026         void *obj_addr;
5027         int ret;
5028         char __user *user_data;
5029
5030         user_data = (char __user *) (uintptr_t) args->data_ptr;
5031         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5032
5033         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5034         ret = copy_from_user(obj_addr, user_data, args->size);
5035         if (ret)
5036                 return -EFAULT;
5037
5038         drm_agp_chipset_flush(dev);
5039         return 0;
5040 }
5041
5042 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5043 {
5044         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5045
5046         /* Clean up our request list when the client is going away, so that
5047          * later retire_requests won't dereference our soon-to-be-gone
5048          * file_priv.
5049          */
5050         mutex_lock(&dev->struct_mutex);
5051         while (!list_empty(&i915_file_priv->mm.request_list))
5052                 list_del_init(i915_file_priv->mm.request_list.next);
5053         mutex_unlock(&dev->struct_mutex);
5054 }
5055
5056 static int
5057 i915_gpu_is_active(struct drm_device *dev)
5058 {
5059         drm_i915_private_t *dev_priv = dev->dev_private;
5060         int lists_empty;
5061
5062         spin_lock(&dev_priv->mm.active_list_lock);
5063         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
5064                       list_empty(&dev_priv->render_ring.active_list);
5065         if (HAS_BSD(dev))
5066                 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
5067         spin_unlock(&dev_priv->mm.active_list_lock);
5068
5069         return !lists_empty;
5070 }
5071
5072 static int
5073 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
5074 {
5075         drm_i915_private_t *dev_priv, *next_dev;
5076         struct drm_i915_gem_object *obj_priv, *next_obj;
5077         int cnt = 0;
5078         int would_deadlock = 1;
5079
5080         /* "fast-path" to count number of available objects */
5081         if (nr_to_scan == 0) {
5082                 spin_lock(&shrink_list_lock);
5083                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5084                         struct drm_device *dev = dev_priv->dev;
5085
5086                         if (mutex_trylock(&dev->struct_mutex)) {
5087                                 list_for_each_entry(obj_priv,
5088                                                     &dev_priv->mm.inactive_list,
5089                                                     list)
5090                                         cnt++;
5091                                 mutex_unlock(&dev->struct_mutex);
5092                         }
5093                 }
5094                 spin_unlock(&shrink_list_lock);
5095
5096                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5097         }
5098
5099         spin_lock(&shrink_list_lock);
5100
5101 rescan:
5102         /* first scan for clean buffers */
5103         list_for_each_entry_safe(dev_priv, next_dev,
5104                                  &shrink_list, mm.shrink_list) {
5105                 struct drm_device *dev = dev_priv->dev;
5106
5107                 if (! mutex_trylock(&dev->struct_mutex))
5108                         continue;
5109
5110                 spin_unlock(&shrink_list_lock);
5111                 i915_gem_retire_requests(dev);
5112
5113                 list_for_each_entry_safe(obj_priv, next_obj,
5114                                          &dev_priv->mm.inactive_list,
5115                                          list) {
5116                         if (i915_gem_object_is_purgeable(obj_priv)) {
5117                                 i915_gem_object_unbind(&obj_priv->base);
5118                                 if (--nr_to_scan <= 0)
5119                                         break;
5120                         }
5121                 }
5122
5123                 spin_lock(&shrink_list_lock);
5124                 mutex_unlock(&dev->struct_mutex);
5125
5126                 would_deadlock = 0;
5127
5128                 if (nr_to_scan <= 0)
5129                         break;
5130         }
5131
5132         /* second pass, evict/count anything still on the inactive list */
5133         list_for_each_entry_safe(dev_priv, next_dev,
5134                                  &shrink_list, mm.shrink_list) {
5135                 struct drm_device *dev = dev_priv->dev;
5136
5137                 if (! mutex_trylock(&dev->struct_mutex))
5138                         continue;
5139
5140                 spin_unlock(&shrink_list_lock);
5141
5142                 list_for_each_entry_safe(obj_priv, next_obj,
5143                                          &dev_priv->mm.inactive_list,
5144                                          list) {
5145                         if (nr_to_scan > 0) {
5146                                 i915_gem_object_unbind(&obj_priv->base);
5147                                 nr_to_scan--;
5148                         } else
5149                                 cnt++;
5150                 }
5151
5152                 spin_lock(&shrink_list_lock);
5153                 mutex_unlock(&dev->struct_mutex);
5154
5155                 would_deadlock = 0;
5156         }
5157
5158         if (nr_to_scan) {
5159                 int active = 0;
5160
5161                 /*
5162                  * We are desperate for pages, so as a last resort, wait
5163                  * for the GPU to finish and discard whatever we can.
5164                  * This has a dramatic impact to reduce the number of
5165                  * OOM-killer events whilst running the GPU aggressively.
5166                  */
5167                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5168                         struct drm_device *dev = dev_priv->dev;
5169
5170                         if (!mutex_trylock(&dev->struct_mutex))
5171                                 continue;
5172
5173                         spin_unlock(&shrink_list_lock);
5174
5175                         if (i915_gpu_is_active(dev)) {
5176                                 i915_gpu_idle(dev);
5177                                 active++;
5178                         }
5179
5180                         spin_lock(&shrink_list_lock);
5181                         mutex_unlock(&dev->struct_mutex);
5182                 }
5183
5184                 if (active)
5185                         goto rescan;
5186         }
5187
5188         spin_unlock(&shrink_list_lock);
5189
5190         if (would_deadlock)
5191                 return -1;
5192         else if (cnt > 0)
5193                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5194         else
5195                 return 0;
5196 }
5197
5198 static struct shrinker shrinker = {
5199         .shrink = i915_gem_shrink,
5200         .seeks = DEFAULT_SEEKS,
5201 };
5202
5203 __init void
5204 i915_gem_shrinker_init(void)
5205 {
5206     register_shrinker(&shrinker);
5207 }
5208
5209 __exit void
5210 i915_gem_shrinker_exit(void)
5211 {
5212     unregister_shrinker(&shrinker);
5213 }