2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
40 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
43 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
49 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
50 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
53 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
54 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
55 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
56 struct drm_i915_gem_pwrite *args,
57 struct drm_file *file_priv);
59 static LIST_HEAD(shrink_list);
60 static DEFINE_SPINLOCK(shrink_list_lock);
62 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
65 drm_i915_private_t *dev_priv = dev->dev_private;
68 (start & (PAGE_SIZE - 1)) != 0 ||
69 (end & (PAGE_SIZE - 1)) != 0) {
73 drm_mm_init(&dev_priv->mm.gtt_space, start,
76 dev->gtt_total = (uint32_t) (end - start);
82 i915_gem_init_ioctl(struct drm_device *dev, void *data,
83 struct drm_file *file_priv)
85 struct drm_i915_gem_init *args = data;
88 mutex_lock(&dev->struct_mutex);
89 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
90 mutex_unlock(&dev->struct_mutex);
96 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
97 struct drm_file *file_priv)
99 struct drm_i915_gem_get_aperture *args = data;
101 if (!(dev->driver->driver_features & DRIVER_GEM))
104 args->aper_size = dev->gtt_total;
105 args->aper_available_size = (args->aper_size -
106 atomic_read(&dev->pin_memory));
113 * Creates a new mm object and returns a handle to it.
116 i915_gem_create_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv)
119 struct drm_i915_gem_create *args = data;
120 struct drm_gem_object *obj;
124 args->size = roundup(args->size, PAGE_SIZE);
126 /* Allocate the new object */
127 obj = drm_gem_object_alloc(dev, args->size);
131 ret = drm_gem_handle_create(file_priv, obj, &handle);
132 drm_gem_object_handle_unreference_unlocked(obj);
137 args->handle = handle;
143 fast_shmem_read(struct page **pages,
144 loff_t page_base, int page_offset,
151 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
154 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
155 kunmap_atomic(vaddr, KM_USER0);
163 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165 drm_i915_private_t *dev_priv = obj->dev->dev_private;
166 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
168 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
169 obj_priv->tiling_mode != I915_TILING_NONE;
173 slow_shmem_copy(struct page *dst_page,
175 struct page *src_page,
179 char *dst_vaddr, *src_vaddr;
181 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
182 if (dst_vaddr == NULL)
185 src_vaddr = kmap_atomic(src_page, KM_USER1);
186 if (src_vaddr == NULL) {
187 kunmap_atomic(dst_vaddr, KM_USER0);
191 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193 kunmap_atomic(src_vaddr, KM_USER1);
194 kunmap_atomic(dst_vaddr, KM_USER0);
200 slow_shmem_bit17_copy(struct page *gpu_page,
202 struct page *cpu_page,
207 char *gpu_vaddr, *cpu_vaddr;
209 /* Use the unswizzled path if this page isn't affected. */
210 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 return slow_shmem_copy(cpu_page, cpu_offset,
213 gpu_page, gpu_offset, length);
215 return slow_shmem_copy(gpu_page, gpu_offset,
216 cpu_page, cpu_offset, length);
219 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
220 if (gpu_vaddr == NULL)
223 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
224 if (cpu_vaddr == NULL) {
225 kunmap_atomic(gpu_vaddr, KM_USER0);
229 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
230 * XORing with the other bits (A9 for Y, A9 and A10 for X)
233 int cacheline_end = ALIGN(gpu_offset + 1, 64);
234 int this_length = min(cacheline_end - gpu_offset, length);
235 int swizzled_gpu_offset = gpu_offset ^ 64;
238 memcpy(cpu_vaddr + cpu_offset,
239 gpu_vaddr + swizzled_gpu_offset,
242 memcpy(gpu_vaddr + swizzled_gpu_offset,
243 cpu_vaddr + cpu_offset,
246 cpu_offset += this_length;
247 gpu_offset += this_length;
248 length -= this_length;
251 kunmap_atomic(cpu_vaddr, KM_USER1);
252 kunmap_atomic(gpu_vaddr, KM_USER0);
258 * This is the fast shmem pread path, which attempts to copy_from_user directly
259 * from the backing pages of the object to the user's address space. On a
260 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
263 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
264 struct drm_i915_gem_pread *args,
265 struct drm_file *file_priv)
267 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
269 loff_t offset, page_base;
270 char __user *user_data;
271 int page_offset, page_length;
274 user_data = (char __user *) (uintptr_t) args->data_ptr;
277 mutex_lock(&dev->struct_mutex);
279 ret = i915_gem_object_get_pages(obj, 0);
283 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
288 obj_priv = to_intel_bo(obj);
289 offset = args->offset;
292 /* Operation in this page
294 * page_base = page offset within aperture
295 * page_offset = offset within page
296 * page_length = bytes to copy for this page
298 page_base = (offset & ~(PAGE_SIZE-1));
299 page_offset = offset & (PAGE_SIZE-1);
300 page_length = remain;
301 if ((page_offset + remain) > PAGE_SIZE)
302 page_length = PAGE_SIZE - page_offset;
304 ret = fast_shmem_read(obj_priv->pages,
305 page_base, page_offset,
306 user_data, page_length);
310 remain -= page_length;
311 user_data += page_length;
312 offset += page_length;
316 i915_gem_object_put_pages(obj);
318 mutex_unlock(&dev->struct_mutex);
324 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
328 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
330 /* If we've insufficient memory to map in the pages, attempt
331 * to make some space by throwing out some old buffers.
333 if (ret == -ENOMEM) {
334 struct drm_device *dev = obj->dev;
336 ret = i915_gem_evict_something(dev, obj->size);
340 ret = i915_gem_object_get_pages(obj, 0);
347 * This is the fallback shmem pread path, which allocates temporary storage
348 * in kernel space to copy_to_user into outside of the struct_mutex, so we
349 * can copy out of the object's backing pages while holding the struct mutex
350 * and not take page faults.
353 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
354 struct drm_i915_gem_pread *args,
355 struct drm_file *file_priv)
357 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
358 struct mm_struct *mm = current->mm;
359 struct page **user_pages;
361 loff_t offset, pinned_pages, i;
362 loff_t first_data_page, last_data_page, num_pages;
363 int shmem_page_index, shmem_page_offset;
364 int data_page_index, data_page_offset;
367 uint64_t data_ptr = args->data_ptr;
368 int do_bit17_swizzling;
372 /* Pin the user pages containing the data. We can't fault while
373 * holding the struct mutex, yet we want to hold it while
374 * dereferencing the user data.
376 first_data_page = data_ptr / PAGE_SIZE;
377 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
378 num_pages = last_data_page - first_data_page + 1;
380 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
381 if (user_pages == NULL)
384 down_read(&mm->mmap_sem);
385 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
386 num_pages, 1, 0, user_pages, NULL);
387 up_read(&mm->mmap_sem);
388 if (pinned_pages < num_pages) {
390 goto fail_put_user_pages;
393 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
395 mutex_lock(&dev->struct_mutex);
397 ret = i915_gem_object_get_pages_or_evict(obj);
401 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
406 obj_priv = to_intel_bo(obj);
407 offset = args->offset;
410 /* Operation in this page
412 * shmem_page_index = page number within shmem file
413 * shmem_page_offset = offset within page in shmem file
414 * data_page_index = page number in get_user_pages return
415 * data_page_offset = offset with data_page_index page.
416 * page_length = bytes to copy for this page
418 shmem_page_index = offset / PAGE_SIZE;
419 shmem_page_offset = offset & ~PAGE_MASK;
420 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
421 data_page_offset = data_ptr & ~PAGE_MASK;
423 page_length = remain;
424 if ((shmem_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - shmem_page_offset;
426 if ((data_page_offset + page_length) > PAGE_SIZE)
427 page_length = PAGE_SIZE - data_page_offset;
429 if (do_bit17_swizzling) {
430 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
432 user_pages[data_page_index],
437 ret = slow_shmem_copy(user_pages[data_page_index],
439 obj_priv->pages[shmem_page_index],
446 remain -= page_length;
447 data_ptr += page_length;
448 offset += page_length;
452 i915_gem_object_put_pages(obj);
454 mutex_unlock(&dev->struct_mutex);
456 for (i = 0; i < pinned_pages; i++) {
457 SetPageDirty(user_pages[i]);
458 page_cache_release(user_pages[i]);
460 drm_free_large(user_pages);
466 * Reads data from the object referenced by handle.
468 * On error, the contents of *data are undefined.
471 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv)
474 struct drm_i915_gem_pread *args = data;
475 struct drm_gem_object *obj;
476 struct drm_i915_gem_object *obj_priv;
479 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
482 obj_priv = to_intel_bo(obj);
484 /* Bounds check source.
486 * XXX: This could use review for overflow issues...
488 if (args->offset > obj->size || args->size > obj->size ||
489 args->offset + args->size > obj->size) {
490 drm_gem_object_unreference_unlocked(obj);
494 if (i915_gem_object_needs_bit17_swizzle(obj)) {
495 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
497 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
499 ret = i915_gem_shmem_pread_slow(dev, obj, args,
503 drm_gem_object_unreference_unlocked(obj);
508 /* This is the fast write path which cannot handle
509 * page faults in the source data
513 fast_user_write(struct io_mapping *mapping,
514 loff_t page_base, int page_offset,
515 char __user *user_data,
519 unsigned long unwritten;
521 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
522 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
524 io_mapping_unmap_atomic(vaddr_atomic);
530 /* Here's the write path which can sleep for
535 slow_kernel_write(struct io_mapping *mapping,
536 loff_t gtt_base, int gtt_offset,
537 struct page *user_page, int user_offset,
540 char *src_vaddr, *dst_vaddr;
541 unsigned long unwritten;
543 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
544 src_vaddr = kmap_atomic(user_page, KM_USER1);
545 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
546 src_vaddr + user_offset,
548 kunmap_atomic(src_vaddr, KM_USER1);
549 io_mapping_unmap_atomic(dst_vaddr);
556 fast_shmem_write(struct page **pages,
557 loff_t page_base, int page_offset,
562 unsigned long unwritten;
564 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
567 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
568 kunmap_atomic(vaddr, KM_USER0);
576 * This is the fast pwrite path, where we copy the data directly from the
577 * user into the GTT, uncached.
580 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
581 struct drm_i915_gem_pwrite *args,
582 struct drm_file *file_priv)
584 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
585 drm_i915_private_t *dev_priv = dev->dev_private;
587 loff_t offset, page_base;
588 char __user *user_data;
589 int page_offset, page_length;
592 user_data = (char __user *) (uintptr_t) args->data_ptr;
594 if (!access_ok(VERIFY_READ, user_data, remain))
598 mutex_lock(&dev->struct_mutex);
599 ret = i915_gem_object_pin(obj, 0);
601 mutex_unlock(&dev->struct_mutex);
604 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
608 obj_priv = to_intel_bo(obj);
609 offset = obj_priv->gtt_offset + args->offset;
612 /* Operation in this page
614 * page_base = page offset within aperture
615 * page_offset = offset within page
616 * page_length = bytes to copy for this page
618 page_base = (offset & ~(PAGE_SIZE-1));
619 page_offset = offset & (PAGE_SIZE-1);
620 page_length = remain;
621 if ((page_offset + remain) > PAGE_SIZE)
622 page_length = PAGE_SIZE - page_offset;
624 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
625 page_offset, user_data, page_length);
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
634 remain -= page_length;
635 user_data += page_length;
636 offset += page_length;
640 i915_gem_object_unpin(obj);
641 mutex_unlock(&dev->struct_mutex);
647 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
648 * the memory and maps it using kmap_atomic for copying.
650 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
651 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
654 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
655 struct drm_i915_gem_pwrite *args,
656 struct drm_file *file_priv)
658 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
659 drm_i915_private_t *dev_priv = dev->dev_private;
661 loff_t gtt_page_base, offset;
662 loff_t first_data_page, last_data_page, num_pages;
663 loff_t pinned_pages, i;
664 struct page **user_pages;
665 struct mm_struct *mm = current->mm;
666 int gtt_page_offset, data_page_offset, data_page_index, page_length;
668 uint64_t data_ptr = args->data_ptr;
672 /* Pin the user pages containing the data. We can't fault while
673 * holding the struct mutex, and all of the pwrite implementations
674 * want to hold it while dereferencing the user data.
676 first_data_page = data_ptr / PAGE_SIZE;
677 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
678 num_pages = last_data_page - first_data_page + 1;
680 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
681 if (user_pages == NULL)
684 down_read(&mm->mmap_sem);
685 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
686 num_pages, 0, 0, user_pages, NULL);
687 up_read(&mm->mmap_sem);
688 if (pinned_pages < num_pages) {
690 goto out_unpin_pages;
693 mutex_lock(&dev->struct_mutex);
694 ret = i915_gem_object_pin(obj, 0);
698 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
700 goto out_unpin_object;
702 obj_priv = to_intel_bo(obj);
703 offset = obj_priv->gtt_offset + args->offset;
706 /* Operation in this page
708 * gtt_page_base = page offset within aperture
709 * gtt_page_offset = offset within page in aperture
710 * data_page_index = page number in get_user_pages return
711 * data_page_offset = offset with data_page_index page.
712 * page_length = bytes to copy for this page
714 gtt_page_base = offset & PAGE_MASK;
715 gtt_page_offset = offset & ~PAGE_MASK;
716 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
717 data_page_offset = data_ptr & ~PAGE_MASK;
719 page_length = remain;
720 if ((gtt_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - gtt_page_offset;
722 if ((data_page_offset + page_length) > PAGE_SIZE)
723 page_length = PAGE_SIZE - data_page_offset;
725 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
726 gtt_page_base, gtt_page_offset,
727 user_pages[data_page_index],
731 /* If we get a fault while copying data, then (presumably) our
732 * source page isn't available. Return the error and we'll
733 * retry in the slow path.
736 goto out_unpin_object;
738 remain -= page_length;
739 offset += page_length;
740 data_ptr += page_length;
744 i915_gem_object_unpin(obj);
746 mutex_unlock(&dev->struct_mutex);
748 for (i = 0; i < pinned_pages; i++)
749 page_cache_release(user_pages[i]);
750 drm_free_large(user_pages);
756 * This is the fast shmem pwrite path, which attempts to directly
757 * copy_from_user into the kmapped pages backing the object.
760 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
761 struct drm_i915_gem_pwrite *args,
762 struct drm_file *file_priv)
764 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
766 loff_t offset, page_base;
767 char __user *user_data;
768 int page_offset, page_length;
771 user_data = (char __user *) (uintptr_t) args->data_ptr;
774 mutex_lock(&dev->struct_mutex);
776 ret = i915_gem_object_get_pages(obj, 0);
780 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
784 obj_priv = to_intel_bo(obj);
785 offset = args->offset;
789 /* Operation in this page
791 * page_base = page offset within aperture
792 * page_offset = offset within page
793 * page_length = bytes to copy for this page
795 page_base = (offset & ~(PAGE_SIZE-1));
796 page_offset = offset & (PAGE_SIZE-1);
797 page_length = remain;
798 if ((page_offset + remain) > PAGE_SIZE)
799 page_length = PAGE_SIZE - page_offset;
801 ret = fast_shmem_write(obj_priv->pages,
802 page_base, page_offset,
803 user_data, page_length);
807 remain -= page_length;
808 user_data += page_length;
809 offset += page_length;
813 i915_gem_object_put_pages(obj);
815 mutex_unlock(&dev->struct_mutex);
821 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
822 * the memory and maps it using kmap_atomic for copying.
824 * This avoids taking mmap_sem for faulting on the user's address while the
825 * struct_mutex is held.
828 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
829 struct drm_i915_gem_pwrite *args,
830 struct drm_file *file_priv)
832 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
833 struct mm_struct *mm = current->mm;
834 struct page **user_pages;
836 loff_t offset, pinned_pages, i;
837 loff_t first_data_page, last_data_page, num_pages;
838 int shmem_page_index, shmem_page_offset;
839 int data_page_index, data_page_offset;
842 uint64_t data_ptr = args->data_ptr;
843 int do_bit17_swizzling;
847 /* Pin the user pages containing the data. We can't fault while
848 * holding the struct mutex, and all of the pwrite implementations
849 * want to hold it while dereferencing the user data.
851 first_data_page = data_ptr / PAGE_SIZE;
852 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
853 num_pages = last_data_page - first_data_page + 1;
855 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
856 if (user_pages == NULL)
859 down_read(&mm->mmap_sem);
860 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
861 num_pages, 0, 0, user_pages, NULL);
862 up_read(&mm->mmap_sem);
863 if (pinned_pages < num_pages) {
865 goto fail_put_user_pages;
868 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
870 mutex_lock(&dev->struct_mutex);
872 ret = i915_gem_object_get_pages_or_evict(obj);
876 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
880 obj_priv = to_intel_bo(obj);
881 offset = args->offset;
885 /* Operation in this page
887 * shmem_page_index = page number within shmem file
888 * shmem_page_offset = offset within page in shmem file
889 * data_page_index = page number in get_user_pages return
890 * data_page_offset = offset with data_page_index page.
891 * page_length = bytes to copy for this page
893 shmem_page_index = offset / PAGE_SIZE;
894 shmem_page_offset = offset & ~PAGE_MASK;
895 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
896 data_page_offset = data_ptr & ~PAGE_MASK;
898 page_length = remain;
899 if ((shmem_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - shmem_page_offset;
901 if ((data_page_offset + page_length) > PAGE_SIZE)
902 page_length = PAGE_SIZE - data_page_offset;
904 if (do_bit17_swizzling) {
905 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
907 user_pages[data_page_index],
912 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
914 user_pages[data_page_index],
921 remain -= page_length;
922 data_ptr += page_length;
923 offset += page_length;
927 i915_gem_object_put_pages(obj);
929 mutex_unlock(&dev->struct_mutex);
931 for (i = 0; i < pinned_pages; i++)
932 page_cache_release(user_pages[i]);
933 drm_free_large(user_pages);
939 * Writes data to the object referenced by handle.
941 * On error, the contents of the buffer that were to be modified are undefined.
944 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
945 struct drm_file *file_priv)
947 struct drm_i915_gem_pwrite *args = data;
948 struct drm_gem_object *obj;
949 struct drm_i915_gem_object *obj_priv;
952 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
955 obj_priv = to_intel_bo(obj);
957 /* Bounds check destination.
959 * XXX: This could use review for overflow issues...
961 if (args->offset > obj->size || args->size > obj->size ||
962 args->offset + args->size > obj->size) {
963 drm_gem_object_unreference_unlocked(obj);
967 /* We can only do the GTT pwrite on untiled buffers, as otherwise
968 * it would end up going through the fenced access, and we'll get
969 * different detiling behavior between reading and writing.
970 * pread/pwrite currently are reading and writing from the CPU
971 * perspective, requiring manual detiling by the client.
973 if (obj_priv->phys_obj)
974 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
975 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
976 dev->gtt_total != 0) {
977 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
978 if (ret == -EFAULT) {
979 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
982 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
983 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
985 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
986 if (ret == -EFAULT) {
987 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
994 DRM_INFO("pwrite failed %d\n", ret);
997 drm_gem_object_unreference_unlocked(obj);
1003 * Called when user space prepares to use an object with the CPU, either
1004 * through the mmap ioctl's mapping or a GTT mapping.
1007 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv)
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct drm_i915_gem_set_domain *args = data;
1012 struct drm_gem_object *obj;
1013 struct drm_i915_gem_object *obj_priv;
1014 uint32_t read_domains = args->read_domains;
1015 uint32_t write_domain = args->write_domain;
1018 if (!(dev->driver->driver_features & DRIVER_GEM))
1021 /* Only handle setting domains to types used by the CPU. */
1022 if (write_domain & I915_GEM_GPU_DOMAINS)
1025 if (read_domains & I915_GEM_GPU_DOMAINS)
1028 /* Having something in the write domain implies it's in the read
1029 * domain, and only that read domain. Enforce that in the request.
1031 if (write_domain != 0 && read_domains != write_domain)
1034 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1037 obj_priv = to_intel_bo(obj);
1039 mutex_lock(&dev->struct_mutex);
1041 intel_mark_busy(dev, obj);
1044 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1045 obj, obj->size, read_domains, write_domain);
1047 if (read_domains & I915_GEM_DOMAIN_GTT) {
1048 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1050 /* Update the LRU on the fence for the CPU access that's
1053 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1054 list_move_tail(&obj_priv->fence_list,
1055 &dev_priv->mm.fence_list);
1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1074 * Called when user space has done writes to this buffer
1077 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 mutex_unlock(&dev->struct_mutex);
1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1097 __func__, args->handle, obj, obj->size);
1099 obj_priv = to_intel_bo(obj);
1101 /* Pinned buffers may be scanout, so flush the cache */
1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1111 * Maps the contents of an object, returning the address it is mapped
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1118 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1133 offset = args->offset;
1135 down_write(¤t->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1139 up_write(¤t->mm->mmap_sem);
1140 drm_gem_object_unreference_unlocked(obj);
1141 if (IS_ERR((void *)addr))
1144 args->addr_ptr = (uint64_t) addr;
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1165 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1171 pgoff_t page_offset;
1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1194 /* Need a new fence register? */
1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1196 ret = i915_gem_object_get_fence_reg(obj);
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1207 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_NOPAGE;
1215 return VM_FAULT_OOM;
1217 return VM_FAULT_SIGBUS;
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1230 * This routine allocates and attaches a fake offset for @obj.
1233 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1238 struct drm_map_list *list;
1239 struct drm_local_map *map;
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1283 drm_mm_put_block(list->file_offset_node);
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1294 * Preserve the reservation of the mmapping with the DRM core code, but
1295 * relinquish ownership of the pages back to the system.
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1305 i915_gem_release_mmap(struct drm_gem_object *obj)
1307 struct drm_device *dev = obj->dev;
1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1316 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1318 struct drm_device *dev = obj->dev;
1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1336 obj_priv->mmap_offset = 0;
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1347 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1349 struct drm_device *dev = obj->dev;
1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1369 for (i = start; i < obj->size; i <<= 1)
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1391 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407 mutex_lock(&dev->struct_mutex);
1409 obj_priv = to_intel_bo(obj);
1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
1428 args->offset = obj_priv->mmap_offset;
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1434 if (!obj_priv->agp_mem) {
1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1451 i915_gem_object_put_pages(struct drm_gem_object *obj)
1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1454 int page_count = obj->size / PAGE_SIZE;
1457 BUG_ON(obj_priv->pages_refcount == 0);
1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1460 if (--obj_priv->pages_refcount != 0)
1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1466 if (obj_priv->madv == I915_MADV_DONTNEED)
1467 obj_priv->dirty = 0;
1469 for (i = 0; i < page_count; i++) {
1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
1474 mark_page_accessed(obj_priv->pages[i]);
1476 page_cache_release(obj_priv->pages[i]);
1478 obj_priv->dirty = 0;
1480 drm_free_large(obj_priv->pages);
1481 obj_priv->pages = NULL;
1485 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1491 /* Add a reference if we're newly entering the active list. */
1492 if (!obj_priv->active) {
1493 drm_gem_object_reference(obj);
1494 obj_priv->active = 1;
1496 /* Move from whatever list we were on to the tail of execution. */
1497 spin_lock(&dev_priv->mm.active_list_lock);
1498 list_move_tail(&obj_priv->list,
1499 &dev_priv->mm.active_list);
1500 spin_unlock(&dev_priv->mm.active_list_lock);
1501 obj_priv->last_rendering_seqno = seqno;
1505 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1507 struct drm_device *dev = obj->dev;
1508 drm_i915_private_t *dev_priv = dev->dev_private;
1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1511 BUG_ON(!obj_priv->active);
1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1513 obj_priv->last_rendering_seqno = 0;
1516 /* Immediately discard the backing storage */
1518 i915_gem_object_truncate(struct drm_gem_object *obj)
1520 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1521 struct inode *inode;
1523 inode = obj->filp->f_path.dentry->d_inode;
1524 if (inode->i_op->truncate)
1525 inode->i_op->truncate (inode);
1527 obj_priv->madv = __I915_MADV_PURGED;
1531 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1533 return obj_priv->madv == I915_MADV_DONTNEED;
1537 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1539 struct drm_device *dev = obj->dev;
1540 drm_i915_private_t *dev_priv = dev->dev_private;
1541 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1543 i915_verify_inactive(dev, __FILE__, __LINE__);
1544 if (obj_priv->pin_count != 0)
1545 list_del_init(&obj_priv->list);
1547 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1549 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1551 obj_priv->last_rendering_seqno = 0;
1552 if (obj_priv->active) {
1553 obj_priv->active = 0;
1554 drm_gem_object_unreference(obj);
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1560 i915_gem_process_flushing_list(struct drm_device *dev,
1561 uint32_t flush_domains, uint32_t seqno)
1563 drm_i915_private_t *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj_priv, *next;
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.gpu_write_list,
1569 struct drm_gem_object *obj = obj_priv->obj;
1571 if ((obj->write_domain & flush_domains) ==
1572 obj->write_domain) {
1573 uint32_t old_write_domain = obj->write_domain;
1575 obj->write_domain = 0;
1576 list_del_init(&obj_priv->gpu_write_list);
1577 i915_gem_object_move_to_active(obj, seqno);
1579 /* update the fence lru list */
1580 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1581 list_move_tail(&obj_priv->fence_list,
1582 &dev_priv->mm.fence_list);
1584 trace_i915_gem_object_change_domain(obj,
1591 #define PIPE_CONTROL_FLUSH(addr) \
1592 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
1593 PIPE_CONTROL_DEPTH_STALL); \
1594 OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
1599 * Creates a new sequence number, emitting a write of it to the status page
1600 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1602 * Must be called with struct_lock held.
1604 * Returned sequence numbers are nonzero on success.
1607 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1608 uint32_t flush_domains)
1610 drm_i915_private_t *dev_priv = dev->dev_private;
1611 struct drm_i915_file_private *i915_file_priv = NULL;
1612 struct drm_i915_gem_request *request;
1617 if (file_priv != NULL)
1618 i915_file_priv = file_priv->driver_priv;
1620 request = kzalloc(sizeof(*request), GFP_KERNEL);
1621 if (request == NULL)
1624 /* Grab the seqno we're going to make this request be, and bump the
1625 * next (skipping 0 so it can be the reserved no-seqno value).
1627 seqno = dev_priv->mm.next_gem_seqno;
1628 dev_priv->mm.next_gem_seqno++;
1629 if (dev_priv->mm.next_gem_seqno == 0)
1630 dev_priv->mm.next_gem_seqno++;
1632 if (HAS_PIPE_CONTROL(dev)) {
1633 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
1636 * Workaround qword write incoherence by flushing the
1637 * PIPE_NOTIFY buffers out to memory before requesting
1641 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
1642 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
1643 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
1646 PIPE_CONTROL_FLUSH(scratch_addr);
1647 scratch_addr += 128; /* write to separate cachelines */
1648 PIPE_CONTROL_FLUSH(scratch_addr);
1649 scratch_addr += 128;
1650 PIPE_CONTROL_FLUSH(scratch_addr);
1651 scratch_addr += 128;
1652 PIPE_CONTROL_FLUSH(scratch_addr);
1653 scratch_addr += 128;
1654 PIPE_CONTROL_FLUSH(scratch_addr);
1655 scratch_addr += 128;
1656 PIPE_CONTROL_FLUSH(scratch_addr);
1657 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
1658 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
1659 PIPE_CONTROL_NOTIFY);
1660 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
1666 OUT_RING(MI_STORE_DWORD_INDEX);
1667 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1670 OUT_RING(MI_USER_INTERRUPT);
1674 DRM_DEBUG_DRIVER("%d\n", seqno);
1676 request->seqno = seqno;
1677 request->emitted_jiffies = jiffies;
1678 was_empty = list_empty(&dev_priv->mm.request_list);
1679 list_add_tail(&request->list, &dev_priv->mm.request_list);
1680 if (i915_file_priv) {
1681 list_add_tail(&request->client_list,
1682 &i915_file_priv->mm.request_list);
1684 INIT_LIST_HEAD(&request->client_list);
1687 /* Associate any objects on the flushing list matching the write
1688 * domain we're flushing with our flush.
1690 if (flush_domains != 0)
1691 i915_gem_process_flushing_list(dev, flush_domains, seqno);
1693 if (!dev_priv->mm.suspended) {
1694 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1696 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1702 * Command execution barrier
1704 * Ensures that all commands in the ring are finished
1705 * before signalling the CPU
1708 i915_retire_commands(struct drm_device *dev)
1710 drm_i915_private_t *dev_priv = dev->dev_private;
1711 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1712 uint32_t flush_domains = 0;
1715 /* The sampler always gets flushed on i965 (sigh) */
1717 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1720 OUT_RING(0); /* noop */
1722 return flush_domains;
1726 * Moves buffers associated only with the given active seqno from the active
1727 * to inactive list, potentially freeing them.
1730 i915_gem_retire_request(struct drm_device *dev,
1731 struct drm_i915_gem_request *request)
1733 drm_i915_private_t *dev_priv = dev->dev_private;
1735 trace_i915_gem_request_retire(dev, request->seqno);
1737 /* Move any buffers on the active list that are no longer referenced
1738 * by the ringbuffer to the flushing/inactive lists as appropriate.
1740 spin_lock(&dev_priv->mm.active_list_lock);
1741 while (!list_empty(&dev_priv->mm.active_list)) {
1742 struct drm_gem_object *obj;
1743 struct drm_i915_gem_object *obj_priv;
1745 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1746 struct drm_i915_gem_object,
1748 obj = obj_priv->obj;
1750 /* If the seqno being retired doesn't match the oldest in the
1751 * list, then the oldest in the list must still be newer than
1754 if (obj_priv->last_rendering_seqno != request->seqno)
1758 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1759 __func__, request->seqno, obj);
1762 if (obj->write_domain != 0)
1763 i915_gem_object_move_to_flushing(obj);
1765 /* Take a reference on the object so it won't be
1766 * freed while the spinlock is held. The list
1767 * protection for this spinlock is safe when breaking
1768 * the lock like this since the next thing we do
1769 * is just get the head of the list again.
1771 drm_gem_object_reference(obj);
1772 i915_gem_object_move_to_inactive(obj);
1773 spin_unlock(&dev_priv->mm.active_list_lock);
1774 drm_gem_object_unreference(obj);
1775 spin_lock(&dev_priv->mm.active_list_lock);
1779 spin_unlock(&dev_priv->mm.active_list_lock);
1783 * Returns true if seq1 is later than seq2.
1786 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1788 return (int32_t)(seq1 - seq2) >= 0;
1792 i915_get_gem_seqno(struct drm_device *dev)
1794 drm_i915_private_t *dev_priv = dev->dev_private;
1796 if (HAS_PIPE_CONTROL(dev))
1797 return ((volatile u32 *)(dev_priv->seqno_page))[0];
1799 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1803 * This function clears the request list as sequence numbers are passed.
1806 i915_gem_retire_requests(struct drm_device *dev)
1808 drm_i915_private_t *dev_priv = dev->dev_private;
1811 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1814 seqno = i915_get_gem_seqno(dev);
1816 while (!list_empty(&dev_priv->mm.request_list)) {
1817 struct drm_i915_gem_request *request;
1818 uint32_t retiring_seqno;
1820 request = list_first_entry(&dev_priv->mm.request_list,
1821 struct drm_i915_gem_request,
1823 retiring_seqno = request->seqno;
1825 if (i915_seqno_passed(seqno, retiring_seqno) ||
1826 atomic_read(&dev_priv->mm.wedged)) {
1827 i915_gem_retire_request(dev, request);
1829 list_del(&request->list);
1830 list_del(&request->client_list);
1836 if (unlikely (dev_priv->trace_irq_seqno &&
1837 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1838 i915_user_irq_put(dev);
1839 dev_priv->trace_irq_seqno = 0;
1844 i915_gem_retire_work_handler(struct work_struct *work)
1846 drm_i915_private_t *dev_priv;
1847 struct drm_device *dev;
1849 dev_priv = container_of(work, drm_i915_private_t,
1850 mm.retire_work.work);
1851 dev = dev_priv->dev;
1853 mutex_lock(&dev->struct_mutex);
1854 i915_gem_retire_requests(dev);
1855 if (!dev_priv->mm.suspended &&
1856 !list_empty(&dev_priv->mm.request_list))
1857 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1858 mutex_unlock(&dev->struct_mutex);
1862 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1864 drm_i915_private_t *dev_priv = dev->dev_private;
1870 if (atomic_read(&dev_priv->mm.wedged))
1873 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1874 if (HAS_PCH_SPLIT(dev))
1875 ier = I915_READ(DEIER) | I915_READ(GTIER);
1877 ier = I915_READ(IER);
1879 DRM_ERROR("something (likely vbetool) disabled "
1880 "interrupts, re-enabling\n");
1881 i915_driver_irq_preinstall(dev);
1882 i915_driver_irq_postinstall(dev);
1885 trace_i915_gem_request_wait_begin(dev, seqno);
1887 dev_priv->mm.waiting_gem_seqno = seqno;
1888 i915_user_irq_get(dev);
1890 ret = wait_event_interruptible(dev_priv->irq_queue,
1891 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1892 atomic_read(&dev_priv->mm.wedged));
1894 wait_event(dev_priv->irq_queue,
1895 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1896 atomic_read(&dev_priv->mm.wedged));
1898 i915_user_irq_put(dev);
1899 dev_priv->mm.waiting_gem_seqno = 0;
1901 trace_i915_gem_request_wait_end(dev, seqno);
1903 if (atomic_read(&dev_priv->mm.wedged))
1906 if (ret && ret != -ERESTARTSYS)
1907 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1908 __func__, ret, seqno, i915_get_gem_seqno(dev));
1910 /* Directly dispatch request retiring. While we have the work queue
1911 * to handle this, the waiter on a request often wants an associated
1912 * buffer to have made it to the inactive list, and we would need
1913 * a separate wait queue to handle that.
1916 i915_gem_retire_requests(dev);
1922 * Waits for a sequence number to be signaled, and cleans up the
1923 * request and object lists appropriately for that event.
1926 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1928 return i915_do_wait_request(dev, seqno, 1);
1932 i915_gem_flush(struct drm_device *dev,
1933 uint32_t invalidate_domains,
1934 uint32_t flush_domains)
1936 drm_i915_private_t *dev_priv = dev->dev_private;
1941 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1942 invalidate_domains, flush_domains);
1944 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1945 invalidate_domains, flush_domains);
1947 if (flush_domains & I915_GEM_DOMAIN_CPU)
1948 drm_agp_chipset_flush(dev);
1950 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1952 * read/write caches:
1954 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1955 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1956 * also flushed at 2d versus 3d pipeline switches.
1960 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1961 * MI_READ_FLUSH is set, and is always flushed on 965.
1963 * I915_GEM_DOMAIN_COMMAND may not exist?
1965 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1966 * invalidated when MI_EXE_FLUSH is set.
1968 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1969 * invalidated with every MI_FLUSH.
1973 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1974 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1975 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1976 * are flushed at any MI_FLUSH.
1979 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1980 if ((invalidate_domains|flush_domains) &
1981 I915_GEM_DOMAIN_RENDER)
1982 cmd &= ~MI_NO_WRITE_FLUSH;
1983 if (!IS_I965G(dev)) {
1985 * On the 965, the sampler cache always gets flushed
1986 * and this bit is reserved.
1988 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1989 cmd |= MI_READ_FLUSH;
1991 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1992 cmd |= MI_EXE_FLUSH;
1995 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
2005 * Ensures that all rendering to the object has completed and the object is
2006 * safe to unbind from the GTT or access from the CPU.
2009 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
2011 struct drm_device *dev = obj->dev;
2012 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2015 /* This function only exists to support waiting for existing rendering,
2016 * not for emitting required flushes.
2018 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2020 /* If there is rendering queued on the buffer being evicted, wait for
2023 if (obj_priv->active) {
2025 DRM_INFO("%s: object %p wait for seqno %08x\n",
2026 __func__, obj, obj_priv->last_rendering_seqno);
2028 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
2037 * Unbinds an object from the GTT aperture.
2040 i915_gem_object_unbind(struct drm_gem_object *obj)
2042 struct drm_device *dev = obj->dev;
2043 drm_i915_private_t *dev_priv = dev->dev_private;
2044 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2048 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2049 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2051 if (obj_priv->gtt_space == NULL)
2054 if (obj_priv->pin_count != 0) {
2055 DRM_ERROR("Attempting to unbind pinned buffer\n");
2059 /* blow away mappings if mapped through GTT */
2060 i915_gem_release_mmap(obj);
2062 /* Move the object to the CPU domain to ensure that
2063 * any possible CPU writes while it's not in the GTT
2064 * are flushed when we go to remap it. This will
2065 * also ensure that all pending GPU writes are finished
2068 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2070 if (ret != -ERESTARTSYS)
2071 DRM_ERROR("set_domain failed: %d\n", ret);
2075 BUG_ON(obj_priv->active);
2077 /* release the fence reg _after_ flushing */
2078 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2079 i915_gem_clear_fence_reg(obj);
2081 if (obj_priv->agp_mem != NULL) {
2082 drm_unbind_agp(obj_priv->agp_mem);
2083 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2084 obj_priv->agp_mem = NULL;
2087 i915_gem_object_put_pages(obj);
2088 BUG_ON(obj_priv->pages_refcount);
2090 if (obj_priv->gtt_space) {
2091 atomic_dec(&dev->gtt_count);
2092 atomic_sub(obj->size, &dev->gtt_memory);
2094 drm_mm_put_block(obj_priv->gtt_space);
2095 obj_priv->gtt_space = NULL;
2098 /* Remove ourselves from the LRU list if present. */
2099 spin_lock(&dev_priv->mm.active_list_lock);
2100 if (!list_empty(&obj_priv->list))
2101 list_del_init(&obj_priv->list);
2102 spin_unlock(&dev_priv->mm.active_list_lock);
2104 if (i915_gem_object_is_purgeable(obj_priv))
2105 i915_gem_object_truncate(obj);
2107 trace_i915_gem_object_unbind(obj);
2112 static struct drm_gem_object *
2113 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2115 drm_i915_private_t *dev_priv = dev->dev_private;
2116 struct drm_i915_gem_object *obj_priv;
2117 struct drm_gem_object *best = NULL;
2118 struct drm_gem_object *first = NULL;
2120 /* Try to find the smallest clean object */
2121 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2122 struct drm_gem_object *obj = obj_priv->obj;
2123 if (obj->size >= min_size) {
2124 if ((!obj_priv->dirty ||
2125 i915_gem_object_is_purgeable(obj_priv)) &&
2126 (!best || obj->size < best->size)) {
2128 if (best->size == min_size)
2136 return best ? best : first;
2140 i915_gpu_idle(struct drm_device *dev)
2142 drm_i915_private_t *dev_priv = dev->dev_private;
2146 spin_lock(&dev_priv->mm.active_list_lock);
2147 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2148 list_empty(&dev_priv->mm.active_list);
2149 spin_unlock(&dev_priv->mm.active_list_lock);
2154 /* Flush everything onto the inactive list. */
2155 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2156 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2160 return i915_wait_request(dev, seqno);
2164 i915_gem_evict_everything(struct drm_device *dev)
2166 drm_i915_private_t *dev_priv = dev->dev_private;
2170 spin_lock(&dev_priv->mm.active_list_lock);
2171 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2172 list_empty(&dev_priv->mm.flushing_list) &&
2173 list_empty(&dev_priv->mm.active_list));
2174 spin_unlock(&dev_priv->mm.active_list_lock);
2179 /* Flush everything (on to the inactive lists) and evict */
2180 ret = i915_gpu_idle(dev);
2184 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2186 ret = i915_gem_evict_from_inactive_list(dev);
2190 spin_lock(&dev_priv->mm.active_list_lock);
2191 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2192 list_empty(&dev_priv->mm.flushing_list) &&
2193 list_empty(&dev_priv->mm.active_list));
2194 spin_unlock(&dev_priv->mm.active_list_lock);
2195 BUG_ON(!lists_empty);
2201 i915_gem_evict_something(struct drm_device *dev, int min_size)
2203 drm_i915_private_t *dev_priv = dev->dev_private;
2204 struct drm_gem_object *obj;
2208 i915_gem_retire_requests(dev);
2210 /* If there's an inactive buffer available now, grab it
2213 obj = i915_gem_find_inactive_object(dev, min_size);
2215 struct drm_i915_gem_object *obj_priv;
2218 DRM_INFO("%s: evicting %p\n", __func__, obj);
2220 obj_priv = to_intel_bo(obj);
2221 BUG_ON(obj_priv->pin_count != 0);
2222 BUG_ON(obj_priv->active);
2224 /* Wait on the rendering and unbind the buffer. */
2225 return i915_gem_object_unbind(obj);
2228 /* If we didn't get anything, but the ring is still processing
2229 * things, wait for the next to finish and hopefully leave us
2230 * a buffer to evict.
2232 if (!list_empty(&dev_priv->mm.request_list)) {
2233 struct drm_i915_gem_request *request;
2235 request = list_first_entry(&dev_priv->mm.request_list,
2236 struct drm_i915_gem_request,
2239 ret = i915_wait_request(dev, request->seqno);
2246 /* If we didn't have anything on the request list but there
2247 * are buffers awaiting a flush, emit one and try again.
2248 * When we wait on it, those buffers waiting for that flush
2249 * will get moved to inactive.
2251 if (!list_empty(&dev_priv->mm.flushing_list)) {
2252 struct drm_i915_gem_object *obj_priv;
2254 /* Find an object that we can immediately reuse */
2255 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2256 obj = obj_priv->obj;
2257 if (obj->size >= min_size)
2269 seqno = i915_add_request(dev, NULL, obj->write_domain);
2276 /* If we didn't do any of the above, there's no single buffer
2277 * large enough to swap out for the new one, so just evict
2278 * everything and start again. (This should be rare.)
2280 if (!list_empty (&dev_priv->mm.inactive_list))
2281 return i915_gem_evict_from_inactive_list(dev);
2283 return i915_gem_evict_everything(dev);
2288 i915_gem_object_get_pages(struct drm_gem_object *obj,
2291 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2293 struct address_space *mapping;
2294 struct inode *inode;
2297 if (obj_priv->pages_refcount++ != 0)
2300 /* Get the list of pages out of our struct file. They'll be pinned
2301 * at this point until we release them.
2303 page_count = obj->size / PAGE_SIZE;
2304 BUG_ON(obj_priv->pages != NULL);
2305 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2306 if (obj_priv->pages == NULL) {
2307 obj_priv->pages_refcount--;
2311 inode = obj->filp->f_path.dentry->d_inode;
2312 mapping = inode->i_mapping;
2313 for (i = 0; i < page_count; i++) {
2314 page = read_cache_page_gfp(mapping, i,
2315 mapping_gfp_mask (mapping) |
2321 obj_priv->pages[i] = page;
2324 if (obj_priv->tiling_mode != I915_TILING_NONE)
2325 i915_gem_object_do_bit_17_swizzle(obj);
2331 page_cache_release(obj_priv->pages[i]);
2333 drm_free_large(obj_priv->pages);
2334 obj_priv->pages = NULL;
2335 obj_priv->pages_refcount--;
2336 return PTR_ERR(page);
2339 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2341 struct drm_gem_object *obj = reg->obj;
2342 struct drm_device *dev = obj->dev;
2343 drm_i915_private_t *dev_priv = dev->dev_private;
2344 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2345 int regnum = obj_priv->fence_reg;
2348 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2350 val |= obj_priv->gtt_offset & 0xfffff000;
2351 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2352 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2354 if (obj_priv->tiling_mode == I915_TILING_Y)
2355 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2356 val |= I965_FENCE_REG_VALID;
2358 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2361 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2363 struct drm_gem_object *obj = reg->obj;
2364 struct drm_device *dev = obj->dev;
2365 drm_i915_private_t *dev_priv = dev->dev_private;
2366 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2367 int regnum = obj_priv->fence_reg;
2370 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2372 val |= obj_priv->gtt_offset & 0xfffff000;
2373 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2374 if (obj_priv->tiling_mode == I915_TILING_Y)
2375 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2376 val |= I965_FENCE_REG_VALID;
2378 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2381 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2383 struct drm_gem_object *obj = reg->obj;
2384 struct drm_device *dev = obj->dev;
2385 drm_i915_private_t *dev_priv = dev->dev_private;
2386 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2387 int regnum = obj_priv->fence_reg;
2389 uint32_t fence_reg, val;
2392 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2393 (obj_priv->gtt_offset & (obj->size - 1))) {
2394 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2395 __func__, obj_priv->gtt_offset, obj->size);
2399 if (obj_priv->tiling_mode == I915_TILING_Y &&
2400 HAS_128_BYTE_Y_TILING(dev))
2405 /* Note: pitch better be a power of two tile widths */
2406 pitch_val = obj_priv->stride / tile_width;
2407 pitch_val = ffs(pitch_val) - 1;
2409 if (obj_priv->tiling_mode == I915_TILING_Y &&
2410 HAS_128_BYTE_Y_TILING(dev))
2411 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2413 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2415 val = obj_priv->gtt_offset;
2416 if (obj_priv->tiling_mode == I915_TILING_Y)
2417 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2418 val |= I915_FENCE_SIZE_BITS(obj->size);
2419 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2420 val |= I830_FENCE_REG_VALID;
2423 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2425 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2426 I915_WRITE(fence_reg, val);
2429 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2431 struct drm_gem_object *obj = reg->obj;
2432 struct drm_device *dev = obj->dev;
2433 drm_i915_private_t *dev_priv = dev->dev_private;
2434 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2435 int regnum = obj_priv->fence_reg;
2438 uint32_t fence_size_bits;
2440 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2441 (obj_priv->gtt_offset & (obj->size - 1))) {
2442 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2443 __func__, obj_priv->gtt_offset);
2447 pitch_val = obj_priv->stride / 128;
2448 pitch_val = ffs(pitch_val) - 1;
2449 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2451 val = obj_priv->gtt_offset;
2452 if (obj_priv->tiling_mode == I915_TILING_Y)
2453 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2454 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2455 WARN_ON(fence_size_bits & ~0x00000f00);
2456 val |= fence_size_bits;
2457 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2458 val |= I830_FENCE_REG_VALID;
2460 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2463 static int i915_find_fence_reg(struct drm_device *dev)
2465 struct drm_i915_fence_reg *reg = NULL;
2466 struct drm_i915_gem_object *obj_priv = NULL;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct drm_gem_object *obj = NULL;
2471 /* First try to find a free reg */
2473 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2474 reg = &dev_priv->fence_regs[i];
2478 obj_priv = to_intel_bo(reg->obj);
2479 if (!obj_priv->pin_count)
2486 /* None available, try to steal one or wait for a user to finish */
2487 i = I915_FENCE_REG_NONE;
2488 list_for_each_entry(obj_priv, &dev_priv->mm.fence_list,
2490 obj = obj_priv->obj;
2492 if (obj_priv->pin_count)
2496 i = obj_priv->fence_reg;
2500 BUG_ON(i == I915_FENCE_REG_NONE);
2502 /* We only have a reference on obj from the active list. put_fence_reg
2503 * might drop that one, causing a use-after-free in it. So hold a
2504 * private reference to obj like the other callers of put_fence_reg
2505 * (set_tiling ioctl) do. */
2506 drm_gem_object_reference(obj);
2507 ret = i915_gem_object_put_fence_reg(obj);
2508 drm_gem_object_unreference(obj);
2516 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2517 * @obj: object to map through a fence reg
2519 * When mapping objects through the GTT, userspace wants to be able to write
2520 * to them without having to worry about swizzling if the object is tiled.
2522 * This function walks the fence regs looking for a free one for @obj,
2523 * stealing one if it can't find any.
2525 * It then sets up the reg based on the object's properties: address, pitch
2526 * and tiling format.
2529 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2531 struct drm_device *dev = obj->dev;
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2534 struct drm_i915_fence_reg *reg = NULL;
2537 /* Just update our place in the LRU if our fence is getting used. */
2538 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2539 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2543 switch (obj_priv->tiling_mode) {
2544 case I915_TILING_NONE:
2545 WARN(1, "allocating a fence for non-tiled object?\n");
2548 if (!obj_priv->stride)
2550 WARN((obj_priv->stride & (512 - 1)),
2551 "object 0x%08x is X tiled but has non-512B pitch\n",
2552 obj_priv->gtt_offset);
2555 if (!obj_priv->stride)
2557 WARN((obj_priv->stride & (128 - 1)),
2558 "object 0x%08x is Y tiled but has non-128B pitch\n",
2559 obj_priv->gtt_offset);
2563 ret = i915_find_fence_reg(dev);
2567 obj_priv->fence_reg = ret;
2568 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2569 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2574 sandybridge_write_fence_reg(reg);
2575 else if (IS_I965G(dev))
2576 i965_write_fence_reg(reg);
2577 else if (IS_I9XX(dev))
2578 i915_write_fence_reg(reg);
2580 i830_write_fence_reg(reg);
2582 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2583 obj_priv->tiling_mode);
2589 * i915_gem_clear_fence_reg - clear out fence register info
2590 * @obj: object to clear
2592 * Zeroes out the fence register itself and clears out the associated
2593 * data structures in dev_priv and obj_priv.
2596 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2598 struct drm_device *dev = obj->dev;
2599 drm_i915_private_t *dev_priv = dev->dev_private;
2600 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2603 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2604 (obj_priv->fence_reg * 8), 0);
2605 } else if (IS_I965G(dev)) {
2606 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2610 if (obj_priv->fence_reg < 8)
2611 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2613 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2616 I915_WRITE(fence_reg, 0);
2619 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2620 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2621 list_del_init(&obj_priv->fence_list);
2625 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2626 * to the buffer to finish, and then resets the fence register.
2627 * @obj: tiled object holding a fence register.
2629 * Zeroes out the fence register itself and clears out the associated
2630 * data structures in dev_priv and obj_priv.
2633 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2635 struct drm_device *dev = obj->dev;
2636 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2638 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2641 /* If we've changed tiling, GTT-mappings of the object
2642 * need to re-fault to ensure that the correct fence register
2643 * setup is in place.
2645 i915_gem_release_mmap(obj);
2647 /* On the i915, GPU access to tiled buffers is via a fence,
2648 * therefore we must wait for any outstanding access to complete
2649 * before clearing the fence.
2651 if (!IS_I965G(dev)) {
2654 i915_gem_object_flush_gpu_write_domain(obj);
2655 ret = i915_gem_object_wait_rendering(obj);
2660 i915_gem_object_flush_gtt_write_domain(obj);
2661 i915_gem_clear_fence_reg (obj);
2667 * Finds free space in the GTT aperture and binds the object there.
2670 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2672 struct drm_device *dev = obj->dev;
2673 drm_i915_private_t *dev_priv = dev->dev_private;
2674 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2675 struct drm_mm_node *free_space;
2676 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2679 if (obj_priv->madv != I915_MADV_WILLNEED) {
2680 DRM_ERROR("Attempting to bind a purgeable object\n");
2685 alignment = i915_gem_get_gtt_alignment(obj);
2686 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2687 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2692 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2693 obj->size, alignment, 0);
2694 if (free_space != NULL) {
2695 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2697 if (obj_priv->gtt_space != NULL) {
2698 obj_priv->gtt_space->private = obj;
2699 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2702 if (obj_priv->gtt_space == NULL) {
2703 /* If the gtt is empty and we're still having trouble
2704 * fitting our object in, we're out of memory.
2707 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2709 ret = i915_gem_evict_something(dev, obj->size);
2717 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2718 obj->size, obj_priv->gtt_offset);
2720 ret = i915_gem_object_get_pages(obj, gfpmask);
2722 drm_mm_put_block(obj_priv->gtt_space);
2723 obj_priv->gtt_space = NULL;
2725 if (ret == -ENOMEM) {
2726 /* first try to clear up some space from the GTT */
2727 ret = i915_gem_evict_something(dev, obj->size);
2729 /* now try to shrink everyone else */
2744 /* Create an AGP memory structure pointing at our pages, and bind it
2747 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2749 obj->size >> PAGE_SHIFT,
2750 obj_priv->gtt_offset,
2751 obj_priv->agp_type);
2752 if (obj_priv->agp_mem == NULL) {
2753 i915_gem_object_put_pages(obj);
2754 drm_mm_put_block(obj_priv->gtt_space);
2755 obj_priv->gtt_space = NULL;
2757 ret = i915_gem_evict_something(dev, obj->size);
2763 atomic_inc(&dev->gtt_count);
2764 atomic_add(obj->size, &dev->gtt_memory);
2766 /* Assert that the object is not currently in any GPU domain. As it
2767 * wasn't in the GTT, there shouldn't be any way it could have been in
2770 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2771 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2773 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2779 i915_gem_clflush_object(struct drm_gem_object *obj)
2781 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2783 /* If we don't have a page list set up, then we're not pinned
2784 * to GPU, and we can ignore the cache flush because it'll happen
2785 * again at bind time.
2787 if (obj_priv->pages == NULL)
2790 trace_i915_gem_object_clflush(obj);
2792 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2795 /** Flushes any GPU write domain for the object if it's dirty. */
2797 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2799 struct drm_device *dev = obj->dev;
2800 uint32_t old_write_domain;
2802 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2805 /* Queue the GPU write cache flushing we need. */
2806 old_write_domain = obj->write_domain;
2807 i915_gem_flush(dev, 0, obj->write_domain);
2808 (void) i915_add_request(dev, NULL, obj->write_domain);
2809 BUG_ON(obj->write_domain);
2811 trace_i915_gem_object_change_domain(obj,
2816 /** Flushes the GTT write domain for the object if it's dirty. */
2818 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2820 uint32_t old_write_domain;
2822 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2825 /* No actual flushing is required for the GTT write domain. Writes
2826 * to it immediately go to main memory as far as we know, so there's
2827 * no chipset flush. It also doesn't land in render cache.
2829 old_write_domain = obj->write_domain;
2830 obj->write_domain = 0;
2832 trace_i915_gem_object_change_domain(obj,
2837 /** Flushes the CPU write domain for the object if it's dirty. */
2839 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2841 struct drm_device *dev = obj->dev;
2842 uint32_t old_write_domain;
2844 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2847 i915_gem_clflush_object(obj);
2848 drm_agp_chipset_flush(dev);
2849 old_write_domain = obj->write_domain;
2850 obj->write_domain = 0;
2852 trace_i915_gem_object_change_domain(obj,
2858 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2860 switch (obj->write_domain) {
2861 case I915_GEM_DOMAIN_GTT:
2862 i915_gem_object_flush_gtt_write_domain(obj);
2864 case I915_GEM_DOMAIN_CPU:
2865 i915_gem_object_flush_cpu_write_domain(obj);
2868 i915_gem_object_flush_gpu_write_domain(obj);
2874 * Moves a single object to the GTT read, and possibly write domain.
2876 * This function returns when the move is complete, including waiting on
2880 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2882 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2883 uint32_t old_write_domain, old_read_domains;
2886 /* Not valid to be called on unbound objects. */
2887 if (obj_priv->gtt_space == NULL)
2890 i915_gem_object_flush_gpu_write_domain(obj);
2891 /* Wait on any GPU rendering and flushing to occur. */
2892 ret = i915_gem_object_wait_rendering(obj);
2896 old_write_domain = obj->write_domain;
2897 old_read_domains = obj->read_domains;
2899 /* If we're writing through the GTT domain, then CPU and GPU caches
2900 * will need to be invalidated at next use.
2903 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2905 i915_gem_object_flush_cpu_write_domain(obj);
2907 /* It should now be out of any other write domains, and we can update
2908 * the domain values for our changes.
2910 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2911 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2913 obj->write_domain = I915_GEM_DOMAIN_GTT;
2914 obj_priv->dirty = 1;
2917 trace_i915_gem_object_change_domain(obj,
2925 * Prepare buffer for display plane. Use uninterruptible for possible flush
2926 * wait, as in modesetting process we're not supposed to be interrupted.
2929 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2931 struct drm_device *dev = obj->dev;
2932 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2933 uint32_t old_write_domain, old_read_domains;
2936 /* Not valid to be called on unbound objects. */
2937 if (obj_priv->gtt_space == NULL)
2940 i915_gem_object_flush_gpu_write_domain(obj);
2942 /* Wait on any GPU rendering and flushing to occur. */
2943 if (obj_priv->active) {
2945 DRM_INFO("%s: object %p wait for seqno %08x\n",
2946 __func__, obj, obj_priv->last_rendering_seqno);
2948 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2953 old_write_domain = obj->write_domain;
2954 old_read_domains = obj->read_domains;
2956 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2958 i915_gem_object_flush_cpu_write_domain(obj);
2960 /* It should now be out of any other write domains, and we can update
2961 * the domain values for our changes.
2963 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2964 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2965 obj->write_domain = I915_GEM_DOMAIN_GTT;
2966 obj_priv->dirty = 1;
2968 trace_i915_gem_object_change_domain(obj,
2976 * Moves a single object to the CPU read, and possibly write domain.
2978 * This function returns when the move is complete, including waiting on
2982 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2984 uint32_t old_write_domain, old_read_domains;
2987 i915_gem_object_flush_gpu_write_domain(obj);
2988 /* Wait on any GPU rendering and flushing to occur. */
2989 ret = i915_gem_object_wait_rendering(obj);
2993 i915_gem_object_flush_gtt_write_domain(obj);
2995 /* If we have a partially-valid cache of the object in the CPU,
2996 * finish invalidating it and free the per-page flags.
2998 i915_gem_object_set_to_full_cpu_read_domain(obj);
3000 old_write_domain = obj->write_domain;
3001 old_read_domains = obj->read_domains;
3003 /* Flush the CPU cache if it's still invalid. */
3004 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3005 i915_gem_clflush_object(obj);
3007 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3010 /* It should now be out of any other write domains, and we can update
3011 * the domain values for our changes.
3013 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3015 /* If we're writing through the CPU, then the GPU read domains will
3016 * need to be invalidated at next use.
3019 obj->read_domains &= I915_GEM_DOMAIN_CPU;
3020 obj->write_domain = I915_GEM_DOMAIN_CPU;
3023 trace_i915_gem_object_change_domain(obj,
3031 * Set the next domain for the specified object. This
3032 * may not actually perform the necessary flushing/invaliding though,
3033 * as that may want to be batched with other set_domain operations
3035 * This is (we hope) the only really tricky part of gem. The goal
3036 * is fairly simple -- track which caches hold bits of the object
3037 * and make sure they remain coherent. A few concrete examples may
3038 * help to explain how it works. For shorthand, we use the notation
3039 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3040 * a pair of read and write domain masks.
3042 * Case 1: the batch buffer
3048 * 5. Unmapped from GTT
3051 * Let's take these a step at a time
3054 * Pages allocated from the kernel may still have
3055 * cache contents, so we set them to (CPU, CPU) always.
3056 * 2. Written by CPU (using pwrite)
3057 * The pwrite function calls set_domain (CPU, CPU) and
3058 * this function does nothing (as nothing changes)
3060 * This function asserts that the object is not
3061 * currently in any GPU-based read or write domains
3063 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3064 * As write_domain is zero, this function adds in the
3065 * current read domains (CPU+COMMAND, 0).
3066 * flush_domains is set to CPU.
3067 * invalidate_domains is set to COMMAND
3068 * clflush is run to get data out of the CPU caches
3069 * then i915_dev_set_domain calls i915_gem_flush to
3070 * emit an MI_FLUSH and drm_agp_chipset_flush
3071 * 5. Unmapped from GTT
3072 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3073 * flush_domains and invalidate_domains end up both zero
3074 * so no flushing/invalidating happens
3078 * Case 2: The shared render buffer
3082 * 3. Read/written by GPU
3083 * 4. set_domain to (CPU,CPU)
3084 * 5. Read/written by CPU
3085 * 6. Read/written by GPU
3088 * Same as last example, (CPU, CPU)
3090 * Nothing changes (assertions find that it is not in the GPU)
3091 * 3. Read/written by GPU
3092 * execbuffer calls set_domain (RENDER, RENDER)
3093 * flush_domains gets CPU
3094 * invalidate_domains gets GPU
3096 * MI_FLUSH and drm_agp_chipset_flush
3097 * 4. set_domain (CPU, CPU)
3098 * flush_domains gets GPU
3099 * invalidate_domains gets CPU
3100 * wait_rendering (obj) to make sure all drawing is complete.
3101 * This will include an MI_FLUSH to get the data from GPU
3103 * clflush (obj) to invalidate the CPU cache
3104 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3105 * 5. Read/written by CPU
3106 * cache lines are loaded and dirtied
3107 * 6. Read written by GPU
3108 * Same as last GPU access
3110 * Case 3: The constant buffer
3115 * 4. Updated (written) by CPU again
3124 * flush_domains = CPU
3125 * invalidate_domains = RENDER
3128 * drm_agp_chipset_flush
3129 * 4. Updated (written) by CPU again
3131 * flush_domains = 0 (no previous write domain)
3132 * invalidate_domains = 0 (no new read domains)
3135 * flush_domains = CPU
3136 * invalidate_domains = RENDER
3139 * drm_agp_chipset_flush
3142 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3144 struct drm_device *dev = obj->dev;
3145 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3146 uint32_t invalidate_domains = 0;
3147 uint32_t flush_domains = 0;
3148 uint32_t old_read_domains;
3150 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3151 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3153 intel_mark_busy(dev, obj);
3156 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3158 obj->read_domains, obj->pending_read_domains,
3159 obj->write_domain, obj->pending_write_domain);
3162 * If the object isn't moving to a new write domain,
3163 * let the object stay in multiple read domains
3165 if (obj->pending_write_domain == 0)
3166 obj->pending_read_domains |= obj->read_domains;
3168 obj_priv->dirty = 1;
3171 * Flush the current write domain if
3172 * the new read domains don't match. Invalidate
3173 * any read domains which differ from the old
3176 if (obj->write_domain &&
3177 obj->write_domain != obj->pending_read_domains) {
3178 flush_domains |= obj->write_domain;
3179 invalidate_domains |=
3180 obj->pending_read_domains & ~obj->write_domain;
3183 * Invalidate any read caches which may have
3184 * stale data. That is, any new read domains.
3186 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3187 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3189 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3190 __func__, flush_domains, invalidate_domains);
3192 i915_gem_clflush_object(obj);
3195 old_read_domains = obj->read_domains;
3197 /* The actual obj->write_domain will be updated with
3198 * pending_write_domain after we emit the accumulated flush for all
3199 * of our domain changes in execbuffers (which clears objects'
3200 * write_domains). So if we have a current write domain that we
3201 * aren't changing, set pending_write_domain to that.
3203 if (flush_domains == 0 && obj->pending_write_domain == 0)
3204 obj->pending_write_domain = obj->write_domain;
3205 obj->read_domains = obj->pending_read_domains;
3207 dev->invalidate_domains |= invalidate_domains;
3208 dev->flush_domains |= flush_domains;
3210 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3212 obj->read_domains, obj->write_domain,
3213 dev->invalidate_domains, dev->flush_domains);
3216 trace_i915_gem_object_change_domain(obj,
3222 * Moves the object from a partially CPU read to a full one.
3224 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3225 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3228 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3230 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3232 if (!obj_priv->page_cpu_valid)
3235 /* If we're partially in the CPU read domain, finish moving it in.
3237 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3240 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3241 if (obj_priv->page_cpu_valid[i])
3243 drm_clflush_pages(obj_priv->pages + i, 1);
3247 /* Free the page_cpu_valid mappings which are now stale, whether
3248 * or not we've got I915_GEM_DOMAIN_CPU.
3250 kfree(obj_priv->page_cpu_valid);
3251 obj_priv->page_cpu_valid = NULL;
3255 * Set the CPU read domain on a range of the object.
3257 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3258 * not entirely valid. The page_cpu_valid member of the object flags which
3259 * pages have been flushed, and will be respected by
3260 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3261 * of the whole object.
3263 * This function returns when the move is complete, including waiting on
3267 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3268 uint64_t offset, uint64_t size)
3270 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3271 uint32_t old_read_domains;
3274 if (offset == 0 && size == obj->size)
3275 return i915_gem_object_set_to_cpu_domain(obj, 0);
3277 i915_gem_object_flush_gpu_write_domain(obj);
3278 /* Wait on any GPU rendering and flushing to occur. */
3279 ret = i915_gem_object_wait_rendering(obj);
3282 i915_gem_object_flush_gtt_write_domain(obj);
3284 /* If we're already fully in the CPU read domain, we're done. */
3285 if (obj_priv->page_cpu_valid == NULL &&
3286 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3289 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3290 * newly adding I915_GEM_DOMAIN_CPU
3292 if (obj_priv->page_cpu_valid == NULL) {
3293 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3295 if (obj_priv->page_cpu_valid == NULL)
3297 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3298 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3300 /* Flush the cache on any pages that are still invalid from the CPU's
3303 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3305 if (obj_priv->page_cpu_valid[i])
3308 drm_clflush_pages(obj_priv->pages + i, 1);
3310 obj_priv->page_cpu_valid[i] = 1;
3313 /* It should now be out of any other write domains, and we can update
3314 * the domain values for our changes.
3316 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3318 old_read_domains = obj->read_domains;
3319 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3321 trace_i915_gem_object_change_domain(obj,
3329 * Pin an object to the GTT and evaluate the relocations landing in it.
3332 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3333 struct drm_file *file_priv,
3334 struct drm_i915_gem_exec_object2 *entry,
3335 struct drm_i915_gem_relocation_entry *relocs)
3337 struct drm_device *dev = obj->dev;
3338 drm_i915_private_t *dev_priv = dev->dev_private;
3339 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3341 void __iomem *reloc_page;
3344 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3345 obj_priv->tiling_mode != I915_TILING_NONE;
3347 /* Check fence reg constraints and rebind if necessary */
3348 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3349 obj_priv->tiling_mode))
3350 i915_gem_object_unbind(obj);
3352 /* Choose the GTT offset for our buffer and put it there. */
3353 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3358 * Pre-965 chips need a fence register set up in order to
3359 * properly handle blits to/from tiled surfaces.
3362 ret = i915_gem_object_get_fence_reg(obj);
3364 if (ret != -EBUSY && ret != -ERESTARTSYS)
3365 DRM_ERROR("Failure to install fence: %d\n",
3367 i915_gem_object_unpin(obj);
3372 entry->offset = obj_priv->gtt_offset;
3374 /* Apply the relocations, using the GTT aperture to avoid cache
3375 * flushing requirements.
3377 for (i = 0; i < entry->relocation_count; i++) {
3378 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3379 struct drm_gem_object *target_obj;
3380 struct drm_i915_gem_object *target_obj_priv;
3381 uint32_t reloc_val, reloc_offset;
3382 uint32_t __iomem *reloc_entry;
3384 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3385 reloc->target_handle);
3386 if (target_obj == NULL) {
3387 i915_gem_object_unpin(obj);
3390 target_obj_priv = to_intel_bo(target_obj);
3393 DRM_INFO("%s: obj %p offset %08x target %d "
3394 "read %08x write %08x gtt %08x "
3395 "presumed %08x delta %08x\n",
3398 (int) reloc->offset,
3399 (int) reloc->target_handle,
3400 (int) reloc->read_domains,
3401 (int) reloc->write_domain,
3402 (int) target_obj_priv->gtt_offset,
3403 (int) reloc->presumed_offset,
3407 /* The target buffer should have appeared before us in the
3408 * exec_object list, so it should have a GTT space bound by now.
3410 if (target_obj_priv->gtt_space == NULL) {
3411 DRM_ERROR("No GTT space found for object %d\n",
3412 reloc->target_handle);
3413 drm_gem_object_unreference(target_obj);
3414 i915_gem_object_unpin(obj);
3418 /* Validate that the target is in a valid r/w GPU domain */
3419 if (reloc->write_domain & (reloc->write_domain - 1)) {
3420 DRM_ERROR("reloc with multiple write domains: "
3421 "obj %p target %d offset %d "
3422 "read %08x write %08x",
3423 obj, reloc->target_handle,
3424 (int) reloc->offset,
3425 reloc->read_domains,
3426 reloc->write_domain);
3429 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3430 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3431 DRM_ERROR("reloc with read/write CPU domains: "
3432 "obj %p target %d offset %d "
3433 "read %08x write %08x",
3434 obj, reloc->target_handle,
3435 (int) reloc->offset,
3436 reloc->read_domains,
3437 reloc->write_domain);
3438 drm_gem_object_unreference(target_obj);
3439 i915_gem_object_unpin(obj);
3442 if (reloc->write_domain && target_obj->pending_write_domain &&
3443 reloc->write_domain != target_obj->pending_write_domain) {
3444 DRM_ERROR("Write domain conflict: "
3445 "obj %p target %d offset %d "
3446 "new %08x old %08x\n",
3447 obj, reloc->target_handle,
3448 (int) reloc->offset,
3449 reloc->write_domain,
3450 target_obj->pending_write_domain);
3451 drm_gem_object_unreference(target_obj);
3452 i915_gem_object_unpin(obj);
3456 target_obj->pending_read_domains |= reloc->read_domains;
3457 target_obj->pending_write_domain |= reloc->write_domain;
3459 /* If the relocation already has the right value in it, no
3460 * more work needs to be done.
3462 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3463 drm_gem_object_unreference(target_obj);
3467 /* Check that the relocation address is valid... */
3468 if (reloc->offset > obj->size - 4) {
3469 DRM_ERROR("Relocation beyond object bounds: "
3470 "obj %p target %d offset %d size %d.\n",
3471 obj, reloc->target_handle,
3472 (int) reloc->offset, (int) obj->size);
3473 drm_gem_object_unreference(target_obj);
3474 i915_gem_object_unpin(obj);
3477 if (reloc->offset & 3) {
3478 DRM_ERROR("Relocation not 4-byte aligned: "
3479 "obj %p target %d offset %d.\n",
3480 obj, reloc->target_handle,
3481 (int) reloc->offset);
3482 drm_gem_object_unreference(target_obj);
3483 i915_gem_object_unpin(obj);
3487 /* and points to somewhere within the target object. */
3488 if (reloc->delta >= target_obj->size) {
3489 DRM_ERROR("Relocation beyond target object bounds: "
3490 "obj %p target %d delta %d size %d.\n",
3491 obj, reloc->target_handle,
3492 (int) reloc->delta, (int) target_obj->size);
3493 drm_gem_object_unreference(target_obj);
3494 i915_gem_object_unpin(obj);
3498 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3500 drm_gem_object_unreference(target_obj);
3501 i915_gem_object_unpin(obj);
3505 /* Map the page containing the relocation we're going to
3508 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3509 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3512 reloc_entry = (uint32_t __iomem *)(reloc_page +
3513 (reloc_offset & (PAGE_SIZE - 1)));
3514 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3517 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3518 obj, (unsigned int) reloc->offset,
3519 readl(reloc_entry), reloc_val);
3521 writel(reloc_val, reloc_entry);
3522 io_mapping_unmap_atomic(reloc_page);
3524 /* The updated presumed offset for this entry will be
3525 * copied back out to the user.
3527 reloc->presumed_offset = target_obj_priv->gtt_offset;
3529 drm_gem_object_unreference(target_obj);
3534 i915_gem_dump_object(obj, 128, __func__, ~0);
3539 /** Dispatch a batchbuffer to the ring
3542 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3543 struct drm_i915_gem_execbuffer2 *exec,
3544 struct drm_clip_rect *cliprects,
3545 uint64_t exec_offset)
3547 drm_i915_private_t *dev_priv = dev->dev_private;
3548 int nbox = exec->num_cliprects;
3550 uint32_t exec_start, exec_len;
3553 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3554 exec_len = (uint32_t) exec->batch_len;
3556 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3558 count = nbox ? nbox : 1;
3560 for (i = 0; i < count; i++) {
3562 int ret = i915_emit_box(dev, cliprects, i,
3563 exec->DR1, exec->DR4);
3568 if (IS_I830(dev) || IS_845G(dev)) {
3570 OUT_RING(MI_BATCH_BUFFER);
3571 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3572 OUT_RING(exec_start + exec_len - 4);
3577 if (IS_I965G(dev)) {
3578 OUT_RING(MI_BATCH_BUFFER_START |
3580 MI_BATCH_NON_SECURE_I965);
3581 OUT_RING(exec_start);
3583 OUT_RING(MI_BATCH_BUFFER_START |
3585 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3591 /* XXX breadcrumb */
3595 /* Throttle our rendering by waiting until the ring has completed our requests
3596 * emitted over 20 msec ago.
3598 * Note that if we were to use the current jiffies each time around the loop,
3599 * we wouldn't escape the function with any frames outstanding if the time to
3600 * render a frame was over 20ms.
3602 * This should get us reasonable parallelism between CPU and GPU but also
3603 * relatively low latency when blocking on a particular request to finish.
3606 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3608 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3610 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3612 mutex_lock(&dev->struct_mutex);
3613 while (!list_empty(&i915_file_priv->mm.request_list)) {
3614 struct drm_i915_gem_request *request;
3616 request = list_first_entry(&i915_file_priv->mm.request_list,
3617 struct drm_i915_gem_request,
3620 if (time_after_eq(request->emitted_jiffies, recent_enough))
3623 ret = i915_wait_request(dev, request->seqno);
3627 mutex_unlock(&dev->struct_mutex);
3633 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3634 uint32_t buffer_count,
3635 struct drm_i915_gem_relocation_entry **relocs)
3637 uint32_t reloc_count = 0, reloc_index = 0, i;
3641 for (i = 0; i < buffer_count; i++) {
3642 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3644 reloc_count += exec_list[i].relocation_count;
3647 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3648 if (*relocs == NULL) {
3649 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3653 for (i = 0; i < buffer_count; i++) {
3654 struct drm_i915_gem_relocation_entry __user *user_relocs;
3656 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3658 ret = copy_from_user(&(*relocs)[reloc_index],
3660 exec_list[i].relocation_count *
3663 drm_free_large(*relocs);
3668 reloc_index += exec_list[i].relocation_count;
3675 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3676 uint32_t buffer_count,
3677 struct drm_i915_gem_relocation_entry *relocs)
3679 uint32_t reloc_count = 0, i;
3685 for (i = 0; i < buffer_count; i++) {
3686 struct drm_i915_gem_relocation_entry __user *user_relocs;
3689 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3691 unwritten = copy_to_user(user_relocs,
3692 &relocs[reloc_count],
3693 exec_list[i].relocation_count *
3701 reloc_count += exec_list[i].relocation_count;
3705 drm_free_large(relocs);
3711 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3712 uint64_t exec_offset)
3714 uint32_t exec_start, exec_len;
3716 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3717 exec_len = (uint32_t) exec->batch_len;
3719 if ((exec_start | exec_len) & 0x7)
3729 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3730 struct drm_gem_object **object_list,
3733 drm_i915_private_t *dev_priv = dev->dev_private;
3734 struct drm_i915_gem_object *obj_priv;
3739 prepare_to_wait(&dev_priv->pending_flip_queue,
3740 &wait, TASK_INTERRUPTIBLE);
3741 for (i = 0; i < count; i++) {
3742 obj_priv = to_intel_bo(object_list[i]);
3743 if (atomic_read(&obj_priv->pending_flip) > 0)
3749 if (!signal_pending(current)) {
3750 mutex_unlock(&dev->struct_mutex);
3752 mutex_lock(&dev->struct_mutex);
3758 finish_wait(&dev_priv->pending_flip_queue, &wait);
3764 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3765 struct drm_file *file_priv,
3766 struct drm_i915_gem_execbuffer2 *args,
3767 struct drm_i915_gem_exec_object2 *exec_list)
3769 drm_i915_private_t *dev_priv = dev->dev_private;
3770 struct drm_gem_object **object_list = NULL;
3771 struct drm_gem_object *batch_obj;
3772 struct drm_i915_gem_object *obj_priv;
3773 struct drm_clip_rect *cliprects = NULL;
3774 struct drm_i915_gem_relocation_entry *relocs = NULL;
3775 int ret = 0, ret2, i, pinned = 0;
3776 uint64_t exec_offset;
3777 uint32_t seqno, flush_domains, reloc_index;
3778 int pin_tries, flips;
3781 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3782 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3785 if (args->buffer_count < 1) {
3786 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3789 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3790 if (object_list == NULL) {
3791 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3792 args->buffer_count);
3797 if (args->num_cliprects != 0) {
3798 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3800 if (cliprects == NULL) {
3805 ret = copy_from_user(cliprects,
3806 (struct drm_clip_rect __user *)
3807 (uintptr_t) args->cliprects_ptr,
3808 sizeof(*cliprects) * args->num_cliprects);
3810 DRM_ERROR("copy %d cliprects failed: %d\n",
3811 args->num_cliprects, ret);
3816 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3821 mutex_lock(&dev->struct_mutex);
3823 i915_verify_inactive(dev, __FILE__, __LINE__);
3825 if (atomic_read(&dev_priv->mm.wedged)) {
3826 mutex_unlock(&dev->struct_mutex);
3831 if (dev_priv->mm.suspended) {
3832 mutex_unlock(&dev->struct_mutex);
3837 /* Look up object handles */
3839 for (i = 0; i < args->buffer_count; i++) {
3840 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3841 exec_list[i].handle);
3842 if (object_list[i] == NULL) {
3843 DRM_ERROR("Invalid object handle %d at index %d\n",
3844 exec_list[i].handle, i);
3845 /* prevent error path from reading uninitialized data */
3846 args->buffer_count = i + 1;
3851 obj_priv = to_intel_bo(object_list[i]);
3852 if (obj_priv->in_execbuffer) {
3853 DRM_ERROR("Object %p appears more than once in object list\n",
3855 /* prevent error path from reading uninitialized data */
3856 args->buffer_count = i + 1;
3860 obj_priv->in_execbuffer = true;
3861 flips += atomic_read(&obj_priv->pending_flip);
3865 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3866 args->buffer_count);
3871 /* Pin and relocate */
3872 for (pin_tries = 0; ; pin_tries++) {
3876 for (i = 0; i < args->buffer_count; i++) {
3877 object_list[i]->pending_read_domains = 0;
3878 object_list[i]->pending_write_domain = 0;
3879 ret = i915_gem_object_pin_and_relocate(object_list[i],
3882 &relocs[reloc_index]);
3886 reloc_index += exec_list[i].relocation_count;
3892 /* error other than GTT full, or we've already tried again */
3893 if (ret != -ENOSPC || pin_tries >= 1) {
3894 if (ret != -ERESTARTSYS) {
3895 unsigned long long total_size = 0;
3896 for (i = 0; i < args->buffer_count; i++)
3897 total_size += object_list[i]->size;
3898 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3899 pinned+1, args->buffer_count,
3901 DRM_ERROR("%d objects [%d pinned], "
3902 "%d object bytes [%d pinned], "
3903 "%d/%d gtt bytes\n",
3904 atomic_read(&dev->object_count),
3905 atomic_read(&dev->pin_count),
3906 atomic_read(&dev->object_memory),
3907 atomic_read(&dev->pin_memory),
3908 atomic_read(&dev->gtt_memory),
3914 /* unpin all of our buffers */
3915 for (i = 0; i < pinned; i++)
3916 i915_gem_object_unpin(object_list[i]);
3919 /* evict everyone we can from the aperture */
3920 ret = i915_gem_evict_everything(dev);
3921 if (ret && ret != -ENOSPC)
3925 /* Set the pending read domains for the batch buffer to COMMAND */
3926 batch_obj = object_list[args->buffer_count-1];
3927 if (batch_obj->pending_write_domain) {
3928 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3932 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3934 /* Sanity check the batch buffer, prior to moving objects */
3935 exec_offset = exec_list[args->buffer_count - 1].offset;
3936 ret = i915_gem_check_execbuffer (args, exec_offset);
3938 DRM_ERROR("execbuf with invalid offset/length\n");
3942 i915_verify_inactive(dev, __FILE__, __LINE__);
3944 /* Zero the global flush/invalidate flags. These
3945 * will be modified as new domains are computed
3948 dev->invalidate_domains = 0;
3949 dev->flush_domains = 0;
3951 for (i = 0; i < args->buffer_count; i++) {
3952 struct drm_gem_object *obj = object_list[i];
3954 /* Compute new gpu domains and update invalidate/flush */
3955 i915_gem_object_set_to_gpu_domain(obj);
3958 i915_verify_inactive(dev, __FILE__, __LINE__);
3960 if (dev->invalidate_domains | dev->flush_domains) {
3962 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3964 dev->invalidate_domains,
3965 dev->flush_domains);
3968 dev->invalidate_domains,
3969 dev->flush_domains);
3970 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3971 (void)i915_add_request(dev, file_priv,
3972 dev->flush_domains);
3975 for (i = 0; i < args->buffer_count; i++) {
3976 struct drm_gem_object *obj = object_list[i];
3977 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3978 uint32_t old_write_domain = obj->write_domain;
3980 obj->write_domain = obj->pending_write_domain;
3981 if (obj->write_domain)
3982 list_move_tail(&obj_priv->gpu_write_list,
3983 &dev_priv->mm.gpu_write_list);
3985 list_del_init(&obj_priv->gpu_write_list);
3987 trace_i915_gem_object_change_domain(obj,
3992 i915_verify_inactive(dev, __FILE__, __LINE__);
3995 for (i = 0; i < args->buffer_count; i++) {
3996 i915_gem_object_check_coherency(object_list[i],
3997 exec_list[i].handle);
4002 i915_gem_dump_object(batch_obj,
4008 /* Exec the batchbuffer */
4009 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
4011 DRM_ERROR("dispatch failed %d\n", ret);
4016 * Ensure that the commands in the batch buffer are
4017 * finished before the interrupt fires
4019 flush_domains = i915_retire_commands(dev);
4021 i915_verify_inactive(dev, __FILE__, __LINE__);
4024 * Get a seqno representing the execution of the current buffer,
4025 * which we can wait on. We would like to mitigate these interrupts,
4026 * likely by only creating seqnos occasionally (so that we have
4027 * *some* interrupts representing completion of buffers that we can
4028 * wait on when trying to clear up gtt space).
4030 seqno = i915_add_request(dev, file_priv, flush_domains);
4032 for (i = 0; i < args->buffer_count; i++) {
4033 struct drm_gem_object *obj = object_list[i];
4035 i915_gem_object_move_to_active(obj, seqno);
4037 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
4041 i915_dump_lru(dev, __func__);
4044 i915_verify_inactive(dev, __FILE__, __LINE__);
4047 for (i = 0; i < pinned; i++)
4048 i915_gem_object_unpin(object_list[i]);
4050 for (i = 0; i < args->buffer_count; i++) {
4051 if (object_list[i]) {
4052 obj_priv = to_intel_bo(object_list[i]);
4053 obj_priv->in_execbuffer = false;
4055 drm_gem_object_unreference(object_list[i]);
4058 mutex_unlock(&dev->struct_mutex);
4061 /* Copy the updated relocations out regardless of current error
4062 * state. Failure to update the relocs would mean that the next
4063 * time userland calls execbuf, it would do so with presumed offset
4064 * state that didn't match the actual object state.
4066 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4069 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4075 drm_free_large(object_list);
4082 * Legacy execbuffer just creates an exec2 list from the original exec object
4083 * list array and passes it to the real function.
4086 i915_gem_execbuffer(struct drm_device *dev, void *data,
4087 struct drm_file *file_priv)
4089 struct drm_i915_gem_execbuffer *args = data;
4090 struct drm_i915_gem_execbuffer2 exec2;
4091 struct drm_i915_gem_exec_object *exec_list = NULL;
4092 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4096 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4097 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4100 if (args->buffer_count < 1) {
4101 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4105 /* Copy in the exec list from userland */
4106 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4107 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4108 if (exec_list == NULL || exec2_list == NULL) {
4109 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4110 args->buffer_count);
4111 drm_free_large(exec_list);
4112 drm_free_large(exec2_list);
4115 ret = copy_from_user(exec_list,
4116 (struct drm_i915_relocation_entry __user *)
4117 (uintptr_t) args->buffers_ptr,
4118 sizeof(*exec_list) * args->buffer_count);
4120 DRM_ERROR("copy %d exec entries failed %d\n",
4121 args->buffer_count, ret);
4122 drm_free_large(exec_list);
4123 drm_free_large(exec2_list);
4127 for (i = 0; i < args->buffer_count; i++) {
4128 exec2_list[i].handle = exec_list[i].handle;
4129 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4130 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4131 exec2_list[i].alignment = exec_list[i].alignment;
4132 exec2_list[i].offset = exec_list[i].offset;
4134 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4136 exec2_list[i].flags = 0;
4139 exec2.buffers_ptr = args->buffers_ptr;
4140 exec2.buffer_count = args->buffer_count;
4141 exec2.batch_start_offset = args->batch_start_offset;
4142 exec2.batch_len = args->batch_len;
4143 exec2.DR1 = args->DR1;
4144 exec2.DR4 = args->DR4;
4145 exec2.num_cliprects = args->num_cliprects;
4146 exec2.cliprects_ptr = args->cliprects_ptr;
4149 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4151 /* Copy the new buffer offsets back to the user's exec list. */
4152 for (i = 0; i < args->buffer_count; i++)
4153 exec_list[i].offset = exec2_list[i].offset;
4154 /* ... and back out to userspace */
4155 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4156 (uintptr_t) args->buffers_ptr,
4158 sizeof(*exec_list) * args->buffer_count);
4161 DRM_ERROR("failed to copy %d exec entries "
4162 "back to user (%d)\n",
4163 args->buffer_count, ret);
4167 drm_free_large(exec_list);
4168 drm_free_large(exec2_list);
4173 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4174 struct drm_file *file_priv)
4176 struct drm_i915_gem_execbuffer2 *args = data;
4177 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4181 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4182 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4185 if (args->buffer_count < 1) {
4186 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4190 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4191 if (exec2_list == NULL) {
4192 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4193 args->buffer_count);
4196 ret = copy_from_user(exec2_list,
4197 (struct drm_i915_relocation_entry __user *)
4198 (uintptr_t) args->buffers_ptr,
4199 sizeof(*exec2_list) * args->buffer_count);
4201 DRM_ERROR("copy %d exec entries failed %d\n",
4202 args->buffer_count, ret);
4203 drm_free_large(exec2_list);
4207 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4209 /* Copy the new buffer offsets back to the user's exec list. */
4210 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4211 (uintptr_t) args->buffers_ptr,
4213 sizeof(*exec2_list) * args->buffer_count);
4216 DRM_ERROR("failed to copy %d exec entries "
4217 "back to user (%d)\n",
4218 args->buffer_count, ret);
4222 drm_free_large(exec2_list);
4227 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4229 struct drm_device *dev = obj->dev;
4230 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4233 i915_verify_inactive(dev, __FILE__, __LINE__);
4234 if (obj_priv->gtt_space == NULL) {
4235 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4240 obj_priv->pin_count++;
4242 /* If the object is not active and not pending a flush,
4243 * remove it from the inactive list
4245 if (obj_priv->pin_count == 1) {
4246 atomic_inc(&dev->pin_count);
4247 atomic_add(obj->size, &dev->pin_memory);
4248 if (!obj_priv->active &&
4249 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4250 !list_empty(&obj_priv->list))
4251 list_del_init(&obj_priv->list);
4253 i915_verify_inactive(dev, __FILE__, __LINE__);
4259 i915_gem_object_unpin(struct drm_gem_object *obj)
4261 struct drm_device *dev = obj->dev;
4262 drm_i915_private_t *dev_priv = dev->dev_private;
4263 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4265 i915_verify_inactive(dev, __FILE__, __LINE__);
4266 obj_priv->pin_count--;
4267 BUG_ON(obj_priv->pin_count < 0);
4268 BUG_ON(obj_priv->gtt_space == NULL);
4270 /* If the object is no longer pinned, and is
4271 * neither active nor being flushed, then stick it on
4274 if (obj_priv->pin_count == 0) {
4275 if (!obj_priv->active &&
4276 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4277 list_move_tail(&obj_priv->list,
4278 &dev_priv->mm.inactive_list);
4279 atomic_dec(&dev->pin_count);
4280 atomic_sub(obj->size, &dev->pin_memory);
4282 i915_verify_inactive(dev, __FILE__, __LINE__);
4286 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4287 struct drm_file *file_priv)
4289 struct drm_i915_gem_pin *args = data;
4290 struct drm_gem_object *obj;
4291 struct drm_i915_gem_object *obj_priv;
4294 mutex_lock(&dev->struct_mutex);
4296 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4298 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4300 mutex_unlock(&dev->struct_mutex);
4303 obj_priv = to_intel_bo(obj);
4305 if (obj_priv->madv != I915_MADV_WILLNEED) {
4306 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4307 drm_gem_object_unreference(obj);
4308 mutex_unlock(&dev->struct_mutex);
4312 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4313 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4315 drm_gem_object_unreference(obj);
4316 mutex_unlock(&dev->struct_mutex);
4320 obj_priv->user_pin_count++;
4321 obj_priv->pin_filp = file_priv;
4322 if (obj_priv->user_pin_count == 1) {
4323 ret = i915_gem_object_pin(obj, args->alignment);
4325 drm_gem_object_unreference(obj);
4326 mutex_unlock(&dev->struct_mutex);
4331 /* XXX - flush the CPU caches for pinned objects
4332 * as the X server doesn't manage domains yet
4334 i915_gem_object_flush_cpu_write_domain(obj);
4335 args->offset = obj_priv->gtt_offset;
4336 drm_gem_object_unreference(obj);
4337 mutex_unlock(&dev->struct_mutex);
4343 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4344 struct drm_file *file_priv)
4346 struct drm_i915_gem_pin *args = data;
4347 struct drm_gem_object *obj;
4348 struct drm_i915_gem_object *obj_priv;
4350 mutex_lock(&dev->struct_mutex);
4352 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4354 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4356 mutex_unlock(&dev->struct_mutex);
4360 obj_priv = to_intel_bo(obj);
4361 if (obj_priv->pin_filp != file_priv) {
4362 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4364 drm_gem_object_unreference(obj);
4365 mutex_unlock(&dev->struct_mutex);
4368 obj_priv->user_pin_count--;
4369 if (obj_priv->user_pin_count == 0) {
4370 obj_priv->pin_filp = NULL;
4371 i915_gem_object_unpin(obj);
4374 drm_gem_object_unreference(obj);
4375 mutex_unlock(&dev->struct_mutex);
4380 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4381 struct drm_file *file_priv)
4383 struct drm_i915_gem_busy *args = data;
4384 struct drm_gem_object *obj;
4385 struct drm_i915_gem_object *obj_priv;
4387 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4389 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4394 mutex_lock(&dev->struct_mutex);
4395 /* Update the active list for the hardware's current position.
4396 * Otherwise this only updates on a delayed timer or when irqs are
4397 * actually unmasked, and our working set ends up being larger than
4400 i915_gem_retire_requests(dev);
4402 obj_priv = to_intel_bo(obj);
4403 /* Don't count being on the flushing list against the object being
4404 * done. Otherwise, a buffer left on the flushing list but not getting
4405 * flushed (because nobody's flushing that domain) won't ever return
4406 * unbusy and get reused by libdrm's bo cache. The other expected
4407 * consumer of this interface, OpenGL's occlusion queries, also specs
4408 * that the objects get unbusy "eventually" without any interference.
4410 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4412 drm_gem_object_unreference(obj);
4413 mutex_unlock(&dev->struct_mutex);
4418 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4419 struct drm_file *file_priv)
4421 return i915_gem_ring_throttle(dev, file_priv);
4425 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4426 struct drm_file *file_priv)
4428 struct drm_i915_gem_madvise *args = data;
4429 struct drm_gem_object *obj;
4430 struct drm_i915_gem_object *obj_priv;
4432 switch (args->madv) {
4433 case I915_MADV_DONTNEED:
4434 case I915_MADV_WILLNEED:
4440 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4442 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4447 mutex_lock(&dev->struct_mutex);
4448 obj_priv = to_intel_bo(obj);
4450 if (obj_priv->pin_count) {
4451 drm_gem_object_unreference(obj);
4452 mutex_unlock(&dev->struct_mutex);
4454 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4458 if (obj_priv->madv != __I915_MADV_PURGED)
4459 obj_priv->madv = args->madv;
4461 /* if the object is no longer bound, discard its backing storage */
4462 if (i915_gem_object_is_purgeable(obj_priv) &&
4463 obj_priv->gtt_space == NULL)
4464 i915_gem_object_truncate(obj);
4466 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4468 drm_gem_object_unreference(obj);
4469 mutex_unlock(&dev->struct_mutex);
4474 int i915_gem_init_object(struct drm_gem_object *obj)
4476 struct drm_i915_gem_object *obj_priv;
4478 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4479 if (obj_priv == NULL)
4483 * We've just allocated pages from the kernel,
4484 * so they've just been written by the CPU with
4485 * zeros. They'll need to be clflushed before we
4486 * use them with the GPU.
4488 obj->write_domain = I915_GEM_DOMAIN_CPU;
4489 obj->read_domains = I915_GEM_DOMAIN_CPU;
4491 obj_priv->agp_type = AGP_USER_MEMORY;
4493 obj->driver_private = obj_priv;
4494 obj_priv->obj = obj;
4495 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4496 INIT_LIST_HEAD(&obj_priv->list);
4497 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4498 INIT_LIST_HEAD(&obj_priv->fence_list);
4499 obj_priv->madv = I915_MADV_WILLNEED;
4501 trace_i915_gem_object_create(obj);
4506 void i915_gem_free_object(struct drm_gem_object *obj)
4508 struct drm_device *dev = obj->dev;
4509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4511 trace_i915_gem_object_destroy(obj);
4513 while (obj_priv->pin_count > 0)
4514 i915_gem_object_unpin(obj);
4516 if (obj_priv->phys_obj)
4517 i915_gem_detach_phys_object(dev, obj);
4519 i915_gem_object_unbind(obj);
4521 if (obj_priv->mmap_offset)
4522 i915_gem_free_mmap_offset(obj);
4524 kfree(obj_priv->page_cpu_valid);
4525 kfree(obj_priv->bit_17);
4526 kfree(obj->driver_private);
4529 /** Unbinds all inactive objects. */
4531 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4533 drm_i915_private_t *dev_priv = dev->dev_private;
4535 while (!list_empty(&dev_priv->mm.inactive_list)) {
4536 struct drm_gem_object *obj;
4539 obj = list_first_entry(&dev_priv->mm.inactive_list,
4540 struct drm_i915_gem_object,
4543 ret = i915_gem_object_unbind(obj);
4545 DRM_ERROR("Error unbinding object: %d\n", ret);
4554 i915_gem_idle(struct drm_device *dev)
4556 drm_i915_private_t *dev_priv = dev->dev_private;
4559 mutex_lock(&dev->struct_mutex);
4561 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4562 mutex_unlock(&dev->struct_mutex);
4566 ret = i915_gpu_idle(dev);
4568 mutex_unlock(&dev->struct_mutex);
4572 /* Under UMS, be paranoid and evict. */
4573 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4574 ret = i915_gem_evict_from_inactive_list(dev);
4576 mutex_unlock(&dev->struct_mutex);
4581 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4582 * We need to replace this with a semaphore, or something.
4583 * And not confound mm.suspended!
4585 dev_priv->mm.suspended = 1;
4586 del_timer(&dev_priv->hangcheck_timer);
4588 i915_kernel_lost_context(dev);
4589 i915_gem_cleanup_ringbuffer(dev);
4591 mutex_unlock(&dev->struct_mutex);
4593 /* Cancel the retire work handler, which should be idle now. */
4594 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4600 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4601 * over cache flushing.
4604 i915_gem_init_pipe_control(struct drm_device *dev)
4606 drm_i915_private_t *dev_priv = dev->dev_private;
4607 struct drm_gem_object *obj;
4608 struct drm_i915_gem_object *obj_priv;
4611 obj = drm_gem_object_alloc(dev, 4096);
4613 DRM_ERROR("Failed to allocate seqno page\n");
4617 obj_priv = to_intel_bo(obj);
4618 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4620 ret = i915_gem_object_pin(obj, 4096);
4624 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4625 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4626 if (dev_priv->seqno_page == NULL)
4629 dev_priv->seqno_obj = obj;
4630 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4635 i915_gem_object_unpin(obj);
4637 drm_gem_object_unreference(obj);
4643 i915_gem_init_hws(struct drm_device *dev)
4645 drm_i915_private_t *dev_priv = dev->dev_private;
4646 struct drm_gem_object *obj;
4647 struct drm_i915_gem_object *obj_priv;
4650 /* If we need a physical address for the status page, it's already
4651 * initialized at driver load time.
4653 if (!I915_NEED_GFX_HWS(dev))
4656 obj = drm_gem_object_alloc(dev, 4096);
4658 DRM_ERROR("Failed to allocate status page\n");
4662 obj_priv = to_intel_bo(obj);
4663 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4665 ret = i915_gem_object_pin(obj, 4096);
4667 drm_gem_object_unreference(obj);
4671 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4673 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4674 if (dev_priv->hw_status_page == NULL) {
4675 DRM_ERROR("Failed to map status page.\n");
4676 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4681 if (HAS_PIPE_CONTROL(dev)) {
4682 ret = i915_gem_init_pipe_control(dev);
4687 dev_priv->hws_obj = obj;
4688 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4690 I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
4691 I915_READ(HWS_PGA_GEN6); /* posting read */
4693 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4694 I915_READ(HWS_PGA); /* posting read */
4696 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4701 i915_gem_object_unpin(obj);
4703 drm_gem_object_unreference(obj);
4709 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4711 drm_i915_private_t *dev_priv = dev->dev_private;
4712 struct drm_gem_object *obj;
4713 struct drm_i915_gem_object *obj_priv;
4715 obj = dev_priv->seqno_obj;
4716 obj_priv = to_intel_bo(obj);
4717 kunmap(obj_priv->pages[0]);
4718 i915_gem_object_unpin(obj);
4719 drm_gem_object_unreference(obj);
4720 dev_priv->seqno_obj = NULL;
4722 dev_priv->seqno_page = NULL;
4726 i915_gem_cleanup_hws(struct drm_device *dev)
4728 drm_i915_private_t *dev_priv = dev->dev_private;
4729 struct drm_gem_object *obj;
4730 struct drm_i915_gem_object *obj_priv;
4732 if (dev_priv->hws_obj == NULL)
4735 obj = dev_priv->hws_obj;
4736 obj_priv = to_intel_bo(obj);
4738 kunmap(obj_priv->pages[0]);
4739 i915_gem_object_unpin(obj);
4740 drm_gem_object_unreference(obj);
4741 dev_priv->hws_obj = NULL;
4743 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4744 dev_priv->hw_status_page = NULL;
4746 if (HAS_PIPE_CONTROL(dev))
4747 i915_gem_cleanup_pipe_control(dev);
4749 /* Write high address into HWS_PGA when disabling. */
4750 I915_WRITE(HWS_PGA, 0x1ffff000);
4754 i915_gem_init_ringbuffer(struct drm_device *dev)
4756 drm_i915_private_t *dev_priv = dev->dev_private;
4757 struct drm_gem_object *obj;
4758 struct drm_i915_gem_object *obj_priv;
4759 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4763 ret = i915_gem_init_hws(dev);
4767 obj = drm_gem_object_alloc(dev, 128 * 1024);
4769 DRM_ERROR("Failed to allocate ringbuffer\n");
4770 i915_gem_cleanup_hws(dev);
4773 obj_priv = to_intel_bo(obj);
4775 ret = i915_gem_object_pin(obj, 4096);
4777 drm_gem_object_unreference(obj);
4778 i915_gem_cleanup_hws(dev);
4782 /* Set up the kernel mapping for the ring. */
4783 ring->Size = obj->size;
4785 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4786 ring->map.size = obj->size;
4788 ring->map.flags = 0;
4791 drm_core_ioremap_wc(&ring->map, dev);
4792 if (ring->map.handle == NULL) {
4793 DRM_ERROR("Failed to map ringbuffer.\n");
4794 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4795 i915_gem_object_unpin(obj);
4796 drm_gem_object_unreference(obj);
4797 i915_gem_cleanup_hws(dev);
4800 ring->ring_obj = obj;
4801 ring->virtual_start = ring->map.handle;
4803 /* Stop the ring if it's running. */
4804 I915_WRITE(PRB0_CTL, 0);
4805 I915_WRITE(PRB0_TAIL, 0);
4806 I915_WRITE(PRB0_HEAD, 0);
4808 /* Initialize the ring. */
4809 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4810 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4812 /* G45 ring initialization fails to reset head to zero */
4814 DRM_ERROR("Ring head not reset to zero "
4815 "ctl %08x head %08x tail %08x start %08x\n",
4816 I915_READ(PRB0_CTL),
4817 I915_READ(PRB0_HEAD),
4818 I915_READ(PRB0_TAIL),
4819 I915_READ(PRB0_START));
4820 I915_WRITE(PRB0_HEAD, 0);
4822 DRM_ERROR("Ring head forced to zero "
4823 "ctl %08x head %08x tail %08x start %08x\n",
4824 I915_READ(PRB0_CTL),
4825 I915_READ(PRB0_HEAD),
4826 I915_READ(PRB0_TAIL),
4827 I915_READ(PRB0_START));
4830 I915_WRITE(PRB0_CTL,
4831 ((obj->size - 4096) & RING_NR_PAGES) |
4835 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4837 /* If the head is still not zero, the ring is dead */
4839 DRM_ERROR("Ring initialization failed "
4840 "ctl %08x head %08x tail %08x start %08x\n",
4841 I915_READ(PRB0_CTL),
4842 I915_READ(PRB0_HEAD),
4843 I915_READ(PRB0_TAIL),
4844 I915_READ(PRB0_START));
4848 /* Update our cache of the ring state */
4849 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4850 i915_kernel_lost_context(dev);
4852 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4853 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4854 ring->space = ring->head - (ring->tail + 8);
4855 if (ring->space < 0)
4856 ring->space += ring->Size;
4859 if (IS_I9XX(dev) && !IS_GEN3(dev)) {
4861 (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
4868 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4870 drm_i915_private_t *dev_priv = dev->dev_private;
4872 if (dev_priv->ring.ring_obj == NULL)
4875 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4877 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4878 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4879 dev_priv->ring.ring_obj = NULL;
4880 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4882 i915_gem_cleanup_hws(dev);
4886 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4887 struct drm_file *file_priv)
4889 drm_i915_private_t *dev_priv = dev->dev_private;
4892 if (drm_core_check_feature(dev, DRIVER_MODESET))
4895 if (atomic_read(&dev_priv->mm.wedged)) {
4896 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4897 atomic_set(&dev_priv->mm.wedged, 0);
4900 mutex_lock(&dev->struct_mutex);
4901 dev_priv->mm.suspended = 0;
4903 ret = i915_gem_init_ringbuffer(dev);
4905 mutex_unlock(&dev->struct_mutex);
4909 spin_lock(&dev_priv->mm.active_list_lock);
4910 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4911 spin_unlock(&dev_priv->mm.active_list_lock);
4913 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4914 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4915 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4916 mutex_unlock(&dev->struct_mutex);
4918 drm_irq_install(dev);
4924 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4925 struct drm_file *file_priv)
4927 if (drm_core_check_feature(dev, DRIVER_MODESET))
4930 drm_irq_uninstall(dev);
4931 return i915_gem_idle(dev);
4935 i915_gem_lastclose(struct drm_device *dev)
4939 if (drm_core_check_feature(dev, DRIVER_MODESET))
4942 ret = i915_gem_idle(dev);
4944 DRM_ERROR("failed to idle hardware: %d\n", ret);
4948 i915_gem_load(struct drm_device *dev)
4951 drm_i915_private_t *dev_priv = dev->dev_private;
4953 spin_lock_init(&dev_priv->mm.active_list_lock);
4954 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4955 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4956 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4957 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4958 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4959 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4960 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4961 i915_gem_retire_work_handler);
4962 dev_priv->mm.next_gem_seqno = 1;
4964 spin_lock(&shrink_list_lock);
4965 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4966 spin_unlock(&shrink_list_lock);
4968 /* Old X drivers will take 0-2 for front, back, depth buffers */
4969 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4970 dev_priv->fence_reg_start = 3;
4972 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4973 dev_priv->num_fence_regs = 16;
4975 dev_priv->num_fence_regs = 8;
4977 /* Initialize fence registers to zero */
4978 if (IS_I965G(dev)) {
4979 for (i = 0; i < 16; i++)
4980 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4982 for (i = 0; i < 8; i++)
4983 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4984 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4985 for (i = 0; i < 8; i++)
4986 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4988 i915_gem_detect_bit_6_swizzle(dev);
4989 init_waitqueue_head(&dev_priv->pending_flip_queue);
4993 * Create a physically contiguous memory object for this object
4994 * e.g. for cursor + overlay regs
4996 int i915_gem_init_phys_object(struct drm_device *dev,
4999 drm_i915_private_t *dev_priv = dev->dev_private;
5000 struct drm_i915_gem_phys_object *phys_obj;
5003 if (dev_priv->mm.phys_objs[id - 1] || !size)
5006 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
5012 phys_obj->handle = drm_pci_alloc(dev, size, 0);
5013 if (!phys_obj->handle) {
5018 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
5021 dev_priv->mm.phys_objs[id - 1] = phys_obj;
5029 void i915_gem_free_phys_object(struct drm_device *dev, int id)
5031 drm_i915_private_t *dev_priv = dev->dev_private;
5032 struct drm_i915_gem_phys_object *phys_obj;
5034 if (!dev_priv->mm.phys_objs[id - 1])
5037 phys_obj = dev_priv->mm.phys_objs[id - 1];
5038 if (phys_obj->cur_obj) {
5039 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
5043 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
5045 drm_pci_free(dev, phys_obj->handle);
5047 dev_priv->mm.phys_objs[id - 1] = NULL;
5050 void i915_gem_free_all_phys_object(struct drm_device *dev)
5054 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
5055 i915_gem_free_phys_object(dev, i);
5058 void i915_gem_detach_phys_object(struct drm_device *dev,
5059 struct drm_gem_object *obj)
5061 struct drm_i915_gem_object *obj_priv;
5066 obj_priv = to_intel_bo(obj);
5067 if (!obj_priv->phys_obj)
5070 ret = i915_gem_object_get_pages(obj, 0);
5074 page_count = obj->size / PAGE_SIZE;
5076 for (i = 0; i < page_count; i++) {
5077 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
5078 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5080 memcpy(dst, src, PAGE_SIZE);
5081 kunmap_atomic(dst, KM_USER0);
5083 drm_clflush_pages(obj_priv->pages, page_count);
5084 drm_agp_chipset_flush(dev);
5086 i915_gem_object_put_pages(obj);
5088 obj_priv->phys_obj->cur_obj = NULL;
5089 obj_priv->phys_obj = NULL;
5093 i915_gem_attach_phys_object(struct drm_device *dev,
5094 struct drm_gem_object *obj, int id)
5096 drm_i915_private_t *dev_priv = dev->dev_private;
5097 struct drm_i915_gem_object *obj_priv;
5102 if (id > I915_MAX_PHYS_OBJECT)
5105 obj_priv = to_intel_bo(obj);
5107 if (obj_priv->phys_obj) {
5108 if (obj_priv->phys_obj->id == id)
5110 i915_gem_detach_phys_object(dev, obj);
5114 /* create a new object */
5115 if (!dev_priv->mm.phys_objs[id - 1]) {
5116 ret = i915_gem_init_phys_object(dev, id,
5119 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
5124 /* bind to the object */
5125 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
5126 obj_priv->phys_obj->cur_obj = obj;
5128 ret = i915_gem_object_get_pages(obj, 0);
5130 DRM_ERROR("failed to get page list\n");
5134 page_count = obj->size / PAGE_SIZE;
5136 for (i = 0; i < page_count; i++) {
5137 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
5138 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5140 memcpy(dst, src, PAGE_SIZE);
5141 kunmap_atomic(src, KM_USER0);
5144 i915_gem_object_put_pages(obj);
5152 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5153 struct drm_i915_gem_pwrite *args,
5154 struct drm_file *file_priv)
5156 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5159 char __user *user_data;
5161 user_data = (char __user *) (uintptr_t) args->data_ptr;
5162 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5164 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5165 ret = copy_from_user(obj_addr, user_data, args->size);
5169 drm_agp_chipset_flush(dev);
5173 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5175 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5177 /* Clean up our request list when the client is going away, so that
5178 * later retire_requests won't dereference our soon-to-be-gone
5181 mutex_lock(&dev->struct_mutex);
5182 while (!list_empty(&i915_file_priv->mm.request_list))
5183 list_del_init(i915_file_priv->mm.request_list.next);
5184 mutex_unlock(&dev->struct_mutex);
5188 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5190 drm_i915_private_t *dev_priv, *next_dev;
5191 struct drm_i915_gem_object *obj_priv, *next_obj;
5193 int would_deadlock = 1;
5195 /* "fast-path" to count number of available objects */
5196 if (nr_to_scan == 0) {
5197 spin_lock(&shrink_list_lock);
5198 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5199 struct drm_device *dev = dev_priv->dev;
5201 if (mutex_trylock(&dev->struct_mutex)) {
5202 list_for_each_entry(obj_priv,
5203 &dev_priv->mm.inactive_list,
5206 mutex_unlock(&dev->struct_mutex);
5209 spin_unlock(&shrink_list_lock);
5211 return (cnt / 100) * sysctl_vfs_cache_pressure;
5214 spin_lock(&shrink_list_lock);
5216 /* first scan for clean buffers */
5217 list_for_each_entry_safe(dev_priv, next_dev,
5218 &shrink_list, mm.shrink_list) {
5219 struct drm_device *dev = dev_priv->dev;
5221 if (! mutex_trylock(&dev->struct_mutex))
5224 spin_unlock(&shrink_list_lock);
5226 i915_gem_retire_requests(dev);
5228 list_for_each_entry_safe(obj_priv, next_obj,
5229 &dev_priv->mm.inactive_list,
5231 if (i915_gem_object_is_purgeable(obj_priv)) {
5232 i915_gem_object_unbind(obj_priv->obj);
5233 if (--nr_to_scan <= 0)
5238 spin_lock(&shrink_list_lock);
5239 mutex_unlock(&dev->struct_mutex);
5243 if (nr_to_scan <= 0)
5247 /* second pass, evict/count anything still on the inactive list */
5248 list_for_each_entry_safe(dev_priv, next_dev,
5249 &shrink_list, mm.shrink_list) {
5250 struct drm_device *dev = dev_priv->dev;
5252 if (! mutex_trylock(&dev->struct_mutex))
5255 spin_unlock(&shrink_list_lock);
5257 list_for_each_entry_safe(obj_priv, next_obj,
5258 &dev_priv->mm.inactive_list,
5260 if (nr_to_scan > 0) {
5261 i915_gem_object_unbind(obj_priv->obj);
5267 spin_lock(&shrink_list_lock);
5268 mutex_unlock(&dev->struct_mutex);
5273 spin_unlock(&shrink_list_lock);
5278 return (cnt / 100) * sysctl_vfs_cache_pressure;
5283 static struct shrinker shrinker = {
5284 .shrink = i915_gem_shrink,
5285 .seeks = DEFAULT_SEEKS,
5289 i915_gem_shrinker_init(void)
5291 register_shrinker(&shrinker);
5295 i915_gem_shrinker_exit(void)
5297 unregister_shrinker(&shrinker);