drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include <linux/swap.h>
  33 #include <linux/pci.h>
  34
  35 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  36
  37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  41                                              int write);
  42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  43                                                      uint64_t offset,
  44                                                      uint64_t size);
  45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  46 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  47 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  48                                            unsigned alignment);
  49 static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
  50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  51 static int i915_gem_evict_something(struct drm_device *dev);
  52 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  53                                 struct drm_i915_gem_pwrite *args,
  54                                 struct drm_file *file_priv);
  55
  56 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  57                      unsigned long end)
  58 {
  59         drm_i915_private_t *dev_priv = dev->dev_private;
  60
  61         if (start >= end ||
  62             (start & (PAGE_SIZE - 1)) != 0 ||
  63             (end & (PAGE_SIZE - 1)) != 0) {
  64                 return -EINVAL;
  65         }
  66
  67         drm_mm_init(&dev_priv->mm.gtt_space, start,
  68                     end - start);
  69
  70         dev->gtt_total = (uint32_t) (end - start);
  71
  72         return 0;
  73 }
  74
  75 int
  76 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  77                     struct drm_file *file_priv)
  78 {
  79         struct drm_i915_gem_init *args = data;
  80         int ret;
  81
  82         mutex_lock(&dev->struct_mutex);
  83         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  84         mutex_unlock(&dev->struct_mutex);
  85
  86         return ret;
  87 }
  88
  89 int
  90 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  91                             struct drm_file *file_priv)
  92 {
  93         struct drm_i915_gem_get_aperture *args = data;
  94
  95         if (!(dev->driver->driver_features & DRIVER_GEM))
  96                 return -ENODEV;
  97
  98         args->aper_size = dev->gtt_total;
  99         args->aper_available_size = (args->aper_size -
 100                                      atomic_read(&dev->pin_memory));
 101
 102         return 0;
 103 }
 104
 105
 106 /**
 107  * Creates a new mm object and returns a handle to it.
 108  */
 109 int
 110 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 111                       struct drm_file *file_priv)
 112 {
 113         struct drm_i915_gem_create *args = data;
 114         struct drm_gem_object *obj;
 115         int handle, ret;
 116
 117         args->size = roundup(args->size, PAGE_SIZE);
 118
 119         /* Allocate the new object */
 120         obj = drm_gem_object_alloc(dev, args->size);
 121         if (obj == NULL)
 122                 return -ENOMEM;
 123
 124         ret = drm_gem_handle_create(file_priv, obj, &handle);
 125         mutex_lock(&dev->struct_mutex);
 126         drm_gem_object_handle_unreference(obj);
 127         mutex_unlock(&dev->struct_mutex);
 128
 129         if (ret)
 130                 return ret;
 131
 132         args->handle = handle;
 133
 134         return 0;
 135 }
 136
 137 static inline int
 138 fast_shmem_read(struct page **pages,
 139                 loff_t page_base, int page_offset,
 140                 char __user *data,
 141                 int length)
 142 {
 143         char __iomem *vaddr;
 144         int unwritten;
 145
 146         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 147         if (vaddr == NULL)
 148                 return -ENOMEM;
 149         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 150         kunmap_atomic(vaddr, KM_USER0);
 151
 152         if (unwritten)
 153                 return -EFAULT;
 154
 155         return 0;
 156 }
 157
 158 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 159 {
 160         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 161         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 162
 163         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 164                 obj_priv->tiling_mode != I915_TILING_NONE;
 165 }
 166
 167 static inline int
 168 slow_shmem_copy(struct page *dst_page,
 169                 int dst_offset,
 170                 struct page *src_page,
 171                 int src_offset,
 172                 int length)
 173 {
 174         char *dst_vaddr, *src_vaddr;
 175
 176         dst_vaddr = kmap_atomic(dst_page, KM_USER0);
 177         if (dst_vaddr == NULL)
 178                 return -ENOMEM;
 179
 180         src_vaddr = kmap_atomic(src_page, KM_USER1);
 181         if (src_vaddr == NULL) {
 182                 kunmap_atomic(dst_vaddr, KM_USER0);
 183                 return -ENOMEM;
 184         }
 185
 186         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 187
 188         kunmap_atomic(src_vaddr, KM_USER1);
 189         kunmap_atomic(dst_vaddr, KM_USER0);
 190
 191         return 0;
 192 }
 193
 194 static inline int
 195 slow_shmem_bit17_copy(struct page *gpu_page,
 196                       int gpu_offset,
 197                       struct page *cpu_page,
 198                       int cpu_offset,
 199                       int length,
 200                       int is_read)
 201 {
 202         char *gpu_vaddr, *cpu_vaddr;
 203
 204         /* Use the unswizzled path if this page isn't affected. */
 205         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 206                 if (is_read)
 207                         return slow_shmem_copy(cpu_page, cpu_offset,
 208                                                gpu_page, gpu_offset, length);
 209                 else
 210                         return slow_shmem_copy(gpu_page, gpu_offset,
 211                                                cpu_page, cpu_offset, length);
 212         }
 213
 214         gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
 215         if (gpu_vaddr == NULL)
 216                 return -ENOMEM;
 217
 218         cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
 219         if (cpu_vaddr == NULL) {
 220                 kunmap_atomic(gpu_vaddr, KM_USER0);
 221                 return -ENOMEM;
 222         }
 223
 224         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 225          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 226          */
 227         while (length > 0) {
 228                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 229                 int this_length = min(cacheline_end - gpu_offset, length);
 230                 int swizzled_gpu_offset = gpu_offset ^ 64;
 231
 232                 if (is_read) {
 233                         memcpy(cpu_vaddr + cpu_offset,
 234                                gpu_vaddr + swizzled_gpu_offset,
 235                                this_length);
 236                 } else {
 237                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 238                                cpu_vaddr + cpu_offset,
 239                                this_length);
 240                 }
 241                 cpu_offset += this_length;
 242                 gpu_offset += this_length;
 243                 length -= this_length;
 244         }
 245
 246         kunmap_atomic(cpu_vaddr, KM_USER1);
 247         kunmap_atomic(gpu_vaddr, KM_USER0);
 248
 249         return 0;
 250 }
 251
 252 /**
 253  * This is the fast shmem pread path, which attempts to copy_from_user directly
 254  * from the backing pages of the object to the user's address space.  On a
 255  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 256  */
 257 static int
 258 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 259                           struct drm_i915_gem_pread *args,
 260                           struct drm_file *file_priv)
 261 {
 262         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 263         ssize_t remain;
 264         loff_t offset, page_base;
 265         char __user *user_data;
 266         int page_offset, page_length;
 267         int ret;
 268
 269         user_data = (char __user *) (uintptr_t) args->data_ptr;
 270         remain = args->size;
 271
 272         mutex_lock(&dev->struct_mutex);
 273
 274         ret = i915_gem_object_get_pages(obj);
 275         if (ret != 0)
 276                 goto fail_unlock;
 277
 278         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 279                                                         args->size);
 280         if (ret != 0)
 281                 goto fail_put_pages;
 282
 283         obj_priv = obj->driver_private;
 284         offset = args->offset;
 285
 286         while (remain > 0) {
 287                 /* Operation in this page
 288                  *
 289                  * page_base = page offset within aperture
 290                  * page_offset = offset within page
 291                  * page_length = bytes to copy for this page
 292                  */
 293                 page_base = (offset & ~(PAGE_SIZE-1));
 294                 page_offset = offset & (PAGE_SIZE-1);
 295                 page_length = remain;
 296                 if ((page_offset + remain) > PAGE_SIZE)
 297                         page_length = PAGE_SIZE - page_offset;
 298
 299                 ret = fast_shmem_read(obj_priv->pages,
 300                                       page_base, page_offset,
 301                                       user_data, page_length);
 302                 if (ret)
 303                         goto fail_put_pages;
 304
 305                 remain -= page_length;
 306                 user_data += page_length;
 307                 offset += page_length;
 308         }
 309
 310 fail_put_pages:
 311         i915_gem_object_put_pages(obj);
 312 fail_unlock:
 313         mutex_unlock(&dev->struct_mutex);
 314
 315         return ret;
 316 }
 317
 318 /**
 319  * This is the fallback shmem pread path, which allocates temporary storage
 320  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 321  * can copy out of the object's backing pages while holding the struct mutex
 322  * and not take page faults.
 323  */
 324 static int
 325 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 326                           struct drm_i915_gem_pread *args,
 327                           struct drm_file *file_priv)
 328 {
 329         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 330         struct mm_struct *mm = current->mm;
 331         struct page **user_pages;
 332         ssize_t remain;
 333         loff_t offset, pinned_pages, i;
 334         loff_t first_data_page, last_data_page, num_pages;
 335         int shmem_page_index, shmem_page_offset;
 336         int data_page_index,  data_page_offset;
 337         int page_length;
 338         int ret;
 339         uint64_t data_ptr = args->data_ptr;
 340         int do_bit17_swizzling;
 341
 342         remain = args->size;
 343
 344         /* Pin the user pages containing the data.  We can't fault while
 345          * holding the struct mutex, yet we want to hold it while
 346          * dereferencing the user data.
 347          */
 348         first_data_page = data_ptr / PAGE_SIZE;
 349         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 350         num_pages = last_data_page - first_data_page + 1;
 351
 352         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 353         if (user_pages == NULL)
 354                 return -ENOMEM;
 355
 356         down_read(&mm->mmap_sem);
 357         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 358                                       num_pages, 1, 0, user_pages, NULL);
 359         up_read(&mm->mmap_sem);
 360         if (pinned_pages < num_pages) {
 361                 ret = -EFAULT;
 362                 goto fail_put_user_pages;
 363         }
 364
 365         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 366
 367         mutex_lock(&dev->struct_mutex);
 368
 369         ret = i915_gem_object_get_pages(obj);
 370         if (ret != 0)
 371                 goto fail_unlock;
 372
 373         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 374                                                         args->size);
 375         if (ret != 0)
 376                 goto fail_put_pages;
 377
 378         obj_priv = obj->driver_private;
 379         offset = args->offset;
 380
 381         while (remain > 0) {
 382                 /* Operation in this page
 383                  *
 384                  * shmem_page_index = page number within shmem file
 385                  * shmem_page_offset = offset within page in shmem file
 386                  * data_page_index = page number in get_user_pages return
 387                  * data_page_offset = offset with data_page_index page.
 388                  * page_length = bytes to copy for this page
 389                  */
 390                 shmem_page_index = offset / PAGE_SIZE;
 391                 shmem_page_offset = offset & ~PAGE_MASK;
 392                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 393                 data_page_offset = data_ptr & ~PAGE_MASK;
 394
 395                 page_length = remain;
 396                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 397                         page_length = PAGE_SIZE - shmem_page_offset;
 398                 if ((data_page_offset + page_length) > PAGE_SIZE)
 399                         page_length = PAGE_SIZE - data_page_offset;
 400
 401                 if (do_bit17_swizzling) {
 402                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 403                                                     shmem_page_offset,
 404                                                     user_pages[data_page_index],
 405                                                     data_page_offset,
 406                                                     page_length,
 407                                                     1);
 408                 } else {
 409                         ret = slow_shmem_copy(user_pages[data_page_index],
 410                                               data_page_offset,
 411                                               obj_priv->pages[shmem_page_index],
 412                                               shmem_page_offset,
 413                                               page_length);
 414                 }
 415                 if (ret)
 416                         goto fail_put_pages;
 417
 418                 remain -= page_length;
 419                 data_ptr += page_length;
 420                 offset += page_length;
 421         }
 422
 423 fail_put_pages:
 424         i915_gem_object_put_pages(obj);
 425 fail_unlock:
 426         mutex_unlock(&dev->struct_mutex);
 427 fail_put_user_pages:
 428         for (i = 0; i < pinned_pages; i++) {
 429                 SetPageDirty(user_pages[i]);
 430                 page_cache_release(user_pages[i]);
 431         }
 432         drm_free_large(user_pages);
 433
 434         return ret;
 435 }
 436
 437 /**
 438  * Reads data from the object referenced by handle.
 439  *
 440  * On error, the contents of *data are undefined.
 441  */
 442 int
 443 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 444                      struct drm_file *file_priv)
 445 {
 446         struct drm_i915_gem_pread *args = data;
 447         struct drm_gem_object *obj;
 448         struct drm_i915_gem_object *obj_priv;
 449         int ret;
 450
 451         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 452         if (obj == NULL)
 453                 return -EBADF;
 454         obj_priv = obj->driver_private;
 455
 456         /* Bounds check source.
 457          *
 458          * XXX: This could use review for overflow issues...
 459          */
 460         if (args->offset > obj->size || args->size > obj->size ||
 461             args->offset + args->size > obj->size) {
 462                 drm_gem_object_unreference(obj);
 463                 return -EINVAL;
 464         }
 465
 466         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 467                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 468         } else {
 469                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 470                 if (ret != 0)
 471                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 472                                                         file_priv);
 473         }
 474
 475         drm_gem_object_unreference(obj);
 476
 477         return ret;
 478 }
 479
 480 /* This is the fast write path which cannot handle
 481  * page faults in the source data
 482  */
 483
 484 static inline int
 485 fast_user_write(struct io_mapping *mapping,
 486                 loff_t page_base, int page_offset,
 487                 char __user *user_data,
 488                 int length)
 489 {
 490         char *vaddr_atomic;
 491         unsigned long unwritten;
 492
 493         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 494         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 495                                                       user_data, length);
 496         io_mapping_unmap_atomic(vaddr_atomic);
 497         if (unwritten)
 498                 return -EFAULT;
 499         return 0;
 500 }
 501
 502 /* Here's the write path which can sleep for
 503  * page faults
 504  */
 505
 506 static inline int
 507 slow_kernel_write(struct io_mapping *mapping,
 508                   loff_t gtt_base, int gtt_offset,
 509                   struct page *user_page, int user_offset,
 510                   int length)
 511 {
 512         char *src_vaddr, *dst_vaddr;
 513         unsigned long unwritten;
 514
 515         dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
 516         src_vaddr = kmap_atomic(user_page, KM_USER1);
 517         unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
 518                                                       src_vaddr + user_offset,
 519                                                       length);
 520         kunmap_atomic(src_vaddr, KM_USER1);
 521         io_mapping_unmap_atomic(dst_vaddr);
 522         if (unwritten)
 523                 return -EFAULT;
 524         return 0;
 525 }
 526
 527 static inline int
 528 fast_shmem_write(struct page **pages,
 529                  loff_t page_base, int page_offset,
 530                  char __user *data,
 531                  int length)
 532 {
 533         char __iomem *vaddr;
 534         unsigned long unwritten;
 535
 536         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 537         if (vaddr == NULL)
 538                 return -ENOMEM;
 539         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 540         kunmap_atomic(vaddr, KM_USER0);
 541
 542         if (unwritten)
 543                 return -EFAULT;
 544         return 0;
 545 }
 546
 547 /**
 548  * This is the fast pwrite path, where we copy the data directly from the
 549  * user into the GTT, uncached.
 550  */
 551 static int
 552 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 553                          struct drm_i915_gem_pwrite *args,
 554                          struct drm_file *file_priv)
 555 {
 556         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 557         drm_i915_private_t *dev_priv = dev->dev_private;
 558         ssize_t remain;
 559         loff_t offset, page_base;
 560         char __user *user_data;
 561         int page_offset, page_length;
 562         int ret;
 563
 564         user_data = (char __user *) (uintptr_t) args->data_ptr;
 565         remain = args->size;
 566         if (!access_ok(VERIFY_READ, user_data, remain))
 567                 return -EFAULT;
 568
 569
 570         mutex_lock(&dev->struct_mutex);
 571         ret = i915_gem_object_pin(obj, 0);
 572         if (ret) {
 573                 mutex_unlock(&dev->struct_mutex);
 574                 return ret;
 575         }
 576         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 577         if (ret)
 578                 goto fail;
 579
 580         obj_priv = obj->driver_private;
 581         offset = obj_priv->gtt_offset + args->offset;
 582
 583         while (remain > 0) {
 584                 /* Operation in this page
 585                  *
 586                  * page_base = page offset within aperture
 587                  * page_offset = offset within page
 588                  * page_length = bytes to copy for this page
 589                  */
 590                 page_base = (offset & ~(PAGE_SIZE-1));
 591                 page_offset = offset & (PAGE_SIZE-1);
 592                 page_length = remain;
 593                 if ((page_offset + remain) > PAGE_SIZE)
 594                         page_length = PAGE_SIZE - page_offset;
 595
 596                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 597                                        page_offset, user_data, page_length);
 598
 599                 /* If we get a fault while copying data, then (presumably) our
 600                  * source page isn't available.  Return the error and we'll
 601                  * retry in the slow path.
 602                  */
 603                 if (ret)
 604                         goto fail;
 605
 606                 remain -= page_length;
 607                 user_data += page_length;
 608                 offset += page_length;
 609         }
 610
 611 fail:
 612         i915_gem_object_unpin(obj);
 613         mutex_unlock(&dev->struct_mutex);
 614
 615         return ret;
 616 }
 617
 618 /**
 619  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 620  * the memory and maps it using kmap_atomic for copying.
 621  *
 622  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 623  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 624  */
 625 static int
 626 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 627                          struct drm_i915_gem_pwrite *args,
 628                          struct drm_file *file_priv)
 629 {
 630         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 631         drm_i915_private_t *dev_priv = dev->dev_private;
 632         ssize_t remain;
 633         loff_t gtt_page_base, offset;
 634         loff_t first_data_page, last_data_page, num_pages;
 635         loff_t pinned_pages, i;
 636         struct page **user_pages;
 637         struct mm_struct *mm = current->mm;
 638         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 639         int ret;
 640         uint64_t data_ptr = args->data_ptr;
 641
 642         remain = args->size;
 643
 644         /* Pin the user pages containing the data.  We can't fault while
 645          * holding the struct mutex, and all of the pwrite implementations
 646          * want to hold it while dereferencing the user data.
 647          */
 648         first_data_page = data_ptr / PAGE_SIZE;
 649         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 650         num_pages = last_data_page - first_data_page + 1;
 651
 652         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 653         if (user_pages == NULL)
 654                 return -ENOMEM;
 655
 656         down_read(&mm->mmap_sem);
 657         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 658                                       num_pages, 0, 0, user_pages, NULL);
 659         up_read(&mm->mmap_sem);
 660         if (pinned_pages < num_pages) {
 661                 ret = -EFAULT;
 662                 goto out_unpin_pages;
 663         }
 664
 665         mutex_lock(&dev->struct_mutex);
 666         ret = i915_gem_object_pin(obj, 0);
 667         if (ret)
 668                 goto out_unlock;
 669
 670         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 671         if (ret)
 672                 goto out_unpin_object;
 673
 674         obj_priv = obj->driver_private;
 675         offset = obj_priv->gtt_offset + args->offset;
 676
 677         while (remain > 0) {
 678                 /* Operation in this page
 679                  *
 680                  * gtt_page_base = page offset within aperture
 681                  * gtt_page_offset = offset within page in aperture
 682                  * data_page_index = page number in get_user_pages return
 683                  * data_page_offset = offset with data_page_index page.
 684                  * page_length = bytes to copy for this page
 685                  */
 686                 gtt_page_base = offset & PAGE_MASK;
 687                 gtt_page_offset = offset & ~PAGE_MASK;
 688                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 689                 data_page_offset = data_ptr & ~PAGE_MASK;
 690
 691                 page_length = remain;
 692                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 693                         page_length = PAGE_SIZE - gtt_page_offset;
 694                 if ((data_page_offset + page_length) > PAGE_SIZE)
 695                         page_length = PAGE_SIZE - data_page_offset;
 696
 697                 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
 698                                         gtt_page_base, gtt_page_offset,
 699                                         user_pages[data_page_index],
 700                                         data_page_offset,
 701                                         page_length);
 702
 703                 /* If we get a fault while copying data, then (presumably) our
 704                  * source page isn't available.  Return the error and we'll
 705                  * retry in the slow path.
 706                  */
 707                 if (ret)
 708                         goto out_unpin_object;
 709
 710                 remain -= page_length;
 711                 offset += page_length;
 712                 data_ptr += page_length;
 713         }
 714
 715 out_unpin_object:
 716         i915_gem_object_unpin(obj);
 717 out_unlock:
 718         mutex_unlock(&dev->struct_mutex);
 719 out_unpin_pages:
 720         for (i = 0; i < pinned_pages; i++)
 721                 page_cache_release(user_pages[i]);
 722         drm_free_large(user_pages);
 723
 724         return ret;
 725 }
 726
 727 /**
 728  * This is the fast shmem pwrite path, which attempts to directly
 729  * copy_from_user into the kmapped pages backing the object.
 730  */
 731 static int
 732 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 733                            struct drm_i915_gem_pwrite *args,
 734                            struct drm_file *file_priv)
 735 {
 736         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 737         ssize_t remain;
 738         loff_t offset, page_base;
 739         char __user *user_data;
 740         int page_offset, page_length;
 741         int ret;
 742
 743         user_data = (char __user *) (uintptr_t) args->data_ptr;
 744         remain = args->size;
 745
 746         mutex_lock(&dev->struct_mutex);
 747
 748         ret = i915_gem_object_get_pages(obj);
 749         if (ret != 0)
 750                 goto fail_unlock;
 751
 752         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 753         if (ret != 0)
 754                 goto fail_put_pages;
 755
 756         obj_priv = obj->driver_private;
 757         offset = args->offset;
 758         obj_priv->dirty = 1;
 759
 760         while (remain > 0) {
 761                 /* Operation in this page
 762                  *
 763                  * page_base = page offset within aperture
 764                  * page_offset = offset within page
 765                  * page_length = bytes to copy for this page
 766                  */
 767                 page_base = (offset & ~(PAGE_SIZE-1));
 768                 page_offset = offset & (PAGE_SIZE-1);
 769                 page_length = remain;
 770                 if ((page_offset + remain) > PAGE_SIZE)
 771                         page_length = PAGE_SIZE - page_offset;
 772
 773                 ret = fast_shmem_write(obj_priv->pages,
 774                                        page_base, page_offset,
 775                                        user_data, page_length);
 776                 if (ret)
 777                         goto fail_put_pages;
 778
 779                 remain -= page_length;
 780                 user_data += page_length;
 781                 offset += page_length;
 782         }
 783
 784 fail_put_pages:
 785         i915_gem_object_put_pages(obj);
 786 fail_unlock:
 787         mutex_unlock(&dev->struct_mutex);
 788
 789         return ret;
 790 }
 791
 792 /**
 793  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 794  * the memory and maps it using kmap_atomic for copying.
 795  *
 796  * This avoids taking mmap_sem for faulting on the user's address while the
 797  * struct_mutex is held.
 798  */
 799 static int
 800 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 801                            struct drm_i915_gem_pwrite *args,
 802                            struct drm_file *file_priv)
 803 {
 804         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 805         struct mm_struct *mm = current->mm;
 806         struct page **user_pages;
 807         ssize_t remain;
 808         loff_t offset, pinned_pages, i;
 809         loff_t first_data_page, last_data_page, num_pages;
 810         int shmem_page_index, shmem_page_offset;
 811         int data_page_index,  data_page_offset;
 812         int page_length;
 813         int ret;
 814         uint64_t data_ptr = args->data_ptr;
 815         int do_bit17_swizzling;
 816
 817         remain = args->size;
 818
 819         /* Pin the user pages containing the data.  We can't fault while
 820          * holding the struct mutex, and all of the pwrite implementations
 821          * want to hold it while dereferencing the user data.
 822          */
 823         first_data_page = data_ptr / PAGE_SIZE;
 824         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 825         num_pages = last_data_page - first_data_page + 1;
 826
 827         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 828         if (user_pages == NULL)
 829                 return -ENOMEM;
 830
 831         down_read(&mm->mmap_sem);
 832         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 833                                       num_pages, 0, 0, user_pages, NULL);
 834         up_read(&mm->mmap_sem);
 835         if (pinned_pages < num_pages) {
 836                 ret = -EFAULT;
 837                 goto fail_put_user_pages;
 838         }
 839
 840         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 841
 842         mutex_lock(&dev->struct_mutex);
 843
 844         ret = i915_gem_object_get_pages(obj);
 845         if (ret != 0)
 846                 goto fail_unlock;
 847
 848         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 849         if (ret != 0)
 850                 goto fail_put_pages;
 851
 852         obj_priv = obj->driver_private;
 853         offset = args->offset;
 854         obj_priv->dirty = 1;
 855
 856         while (remain > 0) {
 857                 /* Operation in this page
 858                  *
 859                  * shmem_page_index = page number within shmem file
 860                  * shmem_page_offset = offset within page in shmem file
 861                  * data_page_index = page number in get_user_pages return
 862                  * data_page_offset = offset with data_page_index page.
 863                  * page_length = bytes to copy for this page
 864                  */
 865                 shmem_page_index = offset / PAGE_SIZE;
 866                 shmem_page_offset = offset & ~PAGE_MASK;
 867                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 868                 data_page_offset = data_ptr & ~PAGE_MASK;
 869
 870                 page_length = remain;
 871                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 872                         page_length = PAGE_SIZE - shmem_page_offset;
 873                 if ((data_page_offset + page_length) > PAGE_SIZE)
 874                         page_length = PAGE_SIZE - data_page_offset;
 875
 876                 if (do_bit17_swizzling) {
 877                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 878                                                     shmem_page_offset,
 879                                                     user_pages[data_page_index],
 880                                                     data_page_offset,
 881                                                     page_length,
 882                                                     0);
 883                 } else {
 884                         ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
 885                                               shmem_page_offset,
 886                                               user_pages[data_page_index],
 887                                               data_page_offset,
 888                                               page_length);
 889                 }
 890                 if (ret)
 891                         goto fail_put_pages;
 892
 893                 remain -= page_length;
 894                 data_ptr += page_length;
 895                 offset += page_length;
 896         }
 897
 898 fail_put_pages:
 899         i915_gem_object_put_pages(obj);
 900 fail_unlock:
 901         mutex_unlock(&dev->struct_mutex);
 902 fail_put_user_pages:
 903         for (i = 0; i < pinned_pages; i++)
 904                 page_cache_release(user_pages[i]);
 905         drm_free_large(user_pages);
 906
 907         return ret;
 908 }
 909
 910 /**
 911  * Writes data to the object referenced by handle.
 912  *
 913  * On error, the contents of the buffer that were to be modified are undefined.
 914  */
 915 int
 916 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 917                       struct drm_file *file_priv)
 918 {
 919         struct drm_i915_gem_pwrite *args = data;
 920         struct drm_gem_object *obj;
 921         struct drm_i915_gem_object *obj_priv;
 922         int ret = 0;
 923
 924         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 925         if (obj == NULL)
 926                 return -EBADF;
 927         obj_priv = obj->driver_private;
 928
 929         /* Bounds check destination.
 930          *
 931          * XXX: This could use review for overflow issues...
 932          */
 933         if (args->offset > obj->size || args->size > obj->size ||
 934             args->offset + args->size > obj->size) {
 935                 drm_gem_object_unreference(obj);
 936                 return -EINVAL;
 937         }
 938
 939         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 940          * it would end up going through the fenced access, and we'll get
 941          * different detiling behavior between reading and writing.
 942          * pread/pwrite currently are reading and writing from the CPU
 943          * perspective, requiring manual detiling by the client.
 944          */
 945         if (obj_priv->phys_obj)
 946                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 947         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 948                  dev->gtt_total != 0) {
 949                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 950                 if (ret == -EFAULT) {
 951                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 952                                                        file_priv);
 953                 }
 954         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 955                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 956         } else {
 957                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 958                 if (ret == -EFAULT) {
 959                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 960                                                          file_priv);
 961                 }
 962         }
 963
 964 #if WATCH_PWRITE
 965         if (ret)
 966                 DRM_INFO("pwrite failed %d\n", ret);
 967 #endif
 968
 969         drm_gem_object_unreference(obj);
 970
 971         return ret;
 972 }
 973
 974 /**
 975  * Called when user space prepares to use an object with the CPU, either
 976  * through the mmap ioctl's mapping or a GTT mapping.
 977  */
 978 int
 979 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 980                           struct drm_file *file_priv)
 981 {
 982         struct drm_i915_gem_set_domain *args = data;
 983         struct drm_gem_object *obj;
 984         uint32_t read_domains = args->read_domains;
 985         uint32_t write_domain = args->write_domain;
 986         int ret;
 987
 988         if (!(dev->driver->driver_features & DRIVER_GEM))
 989                 return -ENODEV;
 990
 991         /* Only handle setting domains to types used by the CPU. */
 992         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 993                 return -EINVAL;
 994
 995         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 996                 return -EINVAL;
 997
 998         /* Having something in the write domain implies it's in the read
 999          * domain, and only that read domain.  Enforce that in the request.
1000          */
1001         if (write_domain != 0 && read_domains != write_domain)
1002                 return -EINVAL;
1003
1004         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1005         if (obj == NULL)
1006                 return -EBADF;
1007
1008         mutex_lock(&dev->struct_mutex);
1009 #if WATCH_BUF
1010         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
1011                  obj, obj->size, read_domains, write_domain);
1012 #endif
1013         if (read_domains & I915_GEM_DOMAIN_GTT) {
1014                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1015
1016                 /* Silently promote "you're not bound, there was nothing to do"
1017                  * to success, since the client was just asking us to
1018                  * make sure everything was done.
1019                  */
1020                 if (ret == -EINVAL)
1021                         ret = 0;
1022         } else {
1023                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1024         }
1025
1026         drm_gem_object_unreference(obj);
1027         mutex_unlock(&dev->struct_mutex);
1028         return ret;
1029 }
1030
1031 /**
1032  * Called when user space has done writes to this buffer
1033  */
1034 int
1035 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1036                       struct drm_file *file_priv)
1037 {
1038         struct drm_i915_gem_sw_finish *args = data;
1039         struct drm_gem_object *obj;
1040         struct drm_i915_gem_object *obj_priv;
1041         int ret = 0;
1042
1043         if (!(dev->driver->driver_features & DRIVER_GEM))
1044                 return -ENODEV;
1045
1046         mutex_lock(&dev->struct_mutex);
1047         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1048         if (obj == NULL) {
1049                 mutex_unlock(&dev->struct_mutex);
1050                 return -EBADF;
1051         }
1052
1053 #if WATCH_BUF
1054         DRM_INFO("%s: sw_finish %d (%p %d)\n",
1055                  __func__, args->handle, obj, obj->size);
1056 #endif
1057         obj_priv = obj->driver_private;
1058
1059         /* Pinned buffers may be scanout, so flush the cache */
1060         if (obj_priv->pin_count)
1061                 i915_gem_object_flush_cpu_write_domain(obj);
1062
1063         drm_gem_object_unreference(obj);
1064         mutex_unlock(&dev->struct_mutex);
1065         return ret;
1066 }
1067
1068 /**
1069  * Maps the contents of an object, returning the address it is mapped
1070  * into.
1071  *
1072  * While the mapping holds a reference on the contents of the object, it doesn't
1073  * imply a ref on the object itself.
1074  */
1075 int
1076 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1077                    struct drm_file *file_priv)
1078 {
1079         struct drm_i915_gem_mmap *args = data;
1080         struct drm_gem_object *obj;
1081         loff_t offset;
1082         unsigned long addr;
1083
1084         if (!(dev->driver->driver_features & DRIVER_GEM))
1085                 return -ENODEV;
1086
1087         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1088         if (obj == NULL)
1089                 return -EBADF;
1090
1091         offset = args->offset;
1092
1093         down_write(&current->mm->mmap_sem);
1094         addr = do_mmap(obj->filp, 0, args->size,
1095                        PROT_READ | PROT_WRITE, MAP_SHARED,
1096                        args->offset);
1097         up_write(&current->mm->mmap_sem);
1098         mutex_lock(&dev->struct_mutex);
1099         drm_gem_object_unreference(obj);
1100         mutex_unlock(&dev->struct_mutex);
1101         if (IS_ERR((void *)addr))
1102                 return addr;
1103
1104         args->addr_ptr = (uint64_t) addr;
1105
1106         return 0;
1107 }
1108
1109 /**
1110  * i915_gem_fault - fault a page into the GTT
1111  * vma: VMA in question
1112  * vmf: fault info
1113  *
1114  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1115  * from userspace.  The fault handler takes care of binding the object to
1116  * the GTT (if needed), allocating and programming a fence register (again,
1117  * only if needed based on whether the old reg is still valid or the object
1118  * is tiled) and inserting a new PTE into the faulting process.
1119  *
1120  * Note that the faulting process may involve evicting existing objects
1121  * from the GTT and/or fence registers to make room.  So performance may
1122  * suffer if the GTT working set is large or there are few fence registers
1123  * left.
1124  */
1125 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1126 {
1127         struct drm_gem_object *obj = vma->vm_private_data;
1128         struct drm_device *dev = obj->dev;
1129         struct drm_i915_private *dev_priv = dev->dev_private;
1130         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1131         pgoff_t page_offset;
1132         unsigned long pfn;
1133         int ret = 0;
1134         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1135
1136         /* We don't use vmf->pgoff since that has the fake offset */
1137         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1138                 PAGE_SHIFT;
1139
1140         /* Now bind it into the GTT if needed */
1141         mutex_lock(&dev->struct_mutex);
1142         if (!obj_priv->gtt_space) {
1143                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1144                 if (ret) {
1145                         mutex_unlock(&dev->struct_mutex);
1146                         return VM_FAULT_SIGBUS;
1147                 }
1148
1149                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1150                 if (ret) {
1151                         mutex_unlock(&dev->struct_mutex);
1152                         return VM_FAULT_SIGBUS;
1153                 }
1154
1155                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1156         }
1157
1158         /* Need a new fence register? */
1159         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1160             obj_priv->tiling_mode != I915_TILING_NONE) {
1161                 ret = i915_gem_object_get_fence_reg(obj, write);
1162                 if (ret) {
1163                         mutex_unlock(&dev->struct_mutex);
1164                         return VM_FAULT_SIGBUS;
1165                 }
1166         }
1167
1168         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1169                 page_offset;
1170
1171         /* Finally, remap it using the new GTT offset */
1172         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1173
1174         mutex_unlock(&dev->struct_mutex);
1175
1176         switch (ret) {
1177         case -ENOMEM:
1178         case -EAGAIN:
1179                 return VM_FAULT_OOM;
1180         case -EFAULT:
1181         case -EINVAL:
1182                 return VM_FAULT_SIGBUS;
1183         default:
1184                 return VM_FAULT_NOPAGE;
1185         }
1186 }
1187
1188 /**
1189  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1190  * @obj: obj in question
1191  *
1192  * GEM memory mapping works by handing back to userspace a fake mmap offset
1193  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1194  * up the object based on the offset and sets up the various memory mapping
1195  * structures.
1196  *
1197  * This routine allocates and attaches a fake offset for @obj.
1198  */
1199 static int
1200 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1201 {
1202         struct drm_device *dev = obj->dev;
1203         struct drm_gem_mm *mm = dev->mm_private;
1204         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1205         struct drm_map_list *list;
1206         struct drm_local_map *map;
1207         int ret = 0;
1208
1209         /* Set the object up for mmap'ing */
1210         list = &obj->map_list;
1211         list->map = drm_calloc(1, sizeof(struct drm_map_list),
1212                                DRM_MEM_DRIVER);
1213         if (!list->map)
1214                 return -ENOMEM;
1215
1216         map = list->map;
1217         map->type = _DRM_GEM;
1218         map->size = obj->size;
1219         map->handle = obj;
1220
1221         /* Get a DRM GEM mmap offset allocated... */
1222         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1223                                                     obj->size / PAGE_SIZE, 0, 0);
1224         if (!list->file_offset_node) {
1225                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1226                 ret = -ENOMEM;
1227                 goto out_free_list;
1228         }
1229
1230         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1231                                                   obj->size / PAGE_SIZE, 0);
1232         if (!list->file_offset_node) {
1233                 ret = -ENOMEM;
1234                 goto out_free_list;
1235         }
1236
1237         list->hash.key = list->file_offset_node->start;
1238         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1239                 DRM_ERROR("failed to add to map hash\n");
1240                 goto out_free_mm;
1241         }
1242
1243         /* By now we should be all set, any drm_mmap request on the offset
1244          * below will get to our mmap & fault handler */
1245         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1246
1247         return 0;
1248
1249 out_free_mm:
1250         drm_mm_put_block(list->file_offset_node);
1251 out_free_list:
1252         drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
1253
1254         return ret;
1255 }
1256
1257 static void
1258 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1259 {
1260         struct drm_device *dev = obj->dev;
1261         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262         struct drm_gem_mm *mm = dev->mm_private;
1263         struct drm_map_list *list;
1264
1265         list = &obj->map_list;
1266         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1267
1268         if (list->file_offset_node) {
1269                 drm_mm_put_block(list->file_offset_node);
1270                 list->file_offset_node = NULL;
1271         }
1272
1273         if (list->map) {
1274                 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
1275                 list->map = NULL;
1276         }
1277
1278         obj_priv->mmap_offset = 0;
1279 }
1280
1281 /**
1282  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1283  * @obj: object to check
1284  *
1285  * Return the required GTT alignment for an object, taking into account
1286  * potential fence register mapping if needed.
1287  */
1288 static uint32_t
1289 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1290 {
1291         struct drm_device *dev = obj->dev;
1292         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1293         int start, i;
1294
1295         /*
1296          * Minimum alignment is 4k (GTT page size), but might be greater
1297          * if a fence register is needed for the object.
1298          */
1299         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1300                 return 4096;
1301
1302         /*
1303          * Previous chips need to be aligned to the size of the smallest
1304          * fence register that can contain the object.
1305          */
1306         if (IS_I9XX(dev))
1307                 start = 1024*1024;
1308         else
1309                 start = 512*1024;
1310
1311         for (i = start; i < obj->size; i <<= 1)
1312                 ;
1313
1314         return i;
1315 }
1316
1317 /**
1318  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1319  * @dev: DRM device
1320  * @data: GTT mapping ioctl data
1321  * @file_priv: GEM object info
1322  *
1323  * Simply returns the fake offset to userspace so it can mmap it.
1324  * The mmap call will end up in drm_gem_mmap(), which will set things
1325  * up so we can get faults in the handler above.
1326  *
1327  * The fault handler will take care of binding the object into the GTT
1328  * (since it may have been evicted to make room for something), allocating
1329  * a fence register, and mapping the appropriate aperture address into
1330  * userspace.
1331  */
1332 int
1333 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1334                         struct drm_file *file_priv)
1335 {
1336         struct drm_i915_gem_mmap_gtt *args = data;
1337         struct drm_i915_private *dev_priv = dev->dev_private;
1338         struct drm_gem_object *obj;
1339         struct drm_i915_gem_object *obj_priv;
1340         int ret;
1341
1342         if (!(dev->driver->driver_features & DRIVER_GEM))
1343                 return -ENODEV;
1344
1345         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1346         if (obj == NULL)
1347                 return -EBADF;
1348
1349         mutex_lock(&dev->struct_mutex);
1350
1351         obj_priv = obj->driver_private;
1352
1353         if (!obj_priv->mmap_offset) {
1354                 ret = i915_gem_create_mmap_offset(obj);
1355                 if (ret) {
1356                         drm_gem_object_unreference(obj);
1357                         mutex_unlock(&dev->struct_mutex);
1358                         return ret;
1359                 }
1360         }
1361
1362         args->offset = obj_priv->mmap_offset;
1363
1364         obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
1365
1366         /* Make sure the alignment is correct for fence regs etc */
1367         if (obj_priv->agp_mem &&
1368             (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
1369                 drm_gem_object_unreference(obj);
1370                 mutex_unlock(&dev->struct_mutex);
1371                 return -EINVAL;
1372         }
1373
1374         /*
1375          * Pull it into the GTT so that we have a page list (makes the
1376          * initial fault faster and any subsequent flushing possible).
1377          */
1378         if (!obj_priv->agp_mem) {
1379                 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1380                 if (ret) {
1381                         drm_gem_object_unreference(obj);
1382                         mutex_unlock(&dev->struct_mutex);
1383                         return ret;
1384                 }
1385                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1386         }
1387
1388         drm_gem_object_unreference(obj);
1389         mutex_unlock(&dev->struct_mutex);
1390
1391         return 0;
1392 }
1393
1394 void
1395 i915_gem_object_put_pages(struct drm_gem_object *obj)
1396 {
1397         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1398         int page_count = obj->size / PAGE_SIZE;
1399         int i;
1400
1401         BUG_ON(obj_priv->pages_refcount == 0);
1402
1403         if (--obj_priv->pages_refcount != 0)
1404                 return;
1405
1406         if (obj_priv->tiling_mode != I915_TILING_NONE)
1407                 i915_gem_object_save_bit_17_swizzle(obj);
1408
1409         for (i = 0; i < page_count; i++)
1410                 if (obj_priv->pages[i] != NULL) {
1411                         if (obj_priv->dirty)
1412                                 set_page_dirty(obj_priv->pages[i]);
1413                         mark_page_accessed(obj_priv->pages[i]);
1414                         page_cache_release(obj_priv->pages[i]);
1415                 }
1416         obj_priv->dirty = 0;
1417
1418         drm_free_large(obj_priv->pages);
1419         obj_priv->pages = NULL;
1420 }
1421
1422 static void
1423 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1424 {
1425         struct drm_device *dev = obj->dev;
1426         drm_i915_private_t *dev_priv = dev->dev_private;
1427         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1428
1429         /* Add a reference if we're newly entering the active list. */
1430         if (!obj_priv->active) {
1431                 drm_gem_object_reference(obj);
1432                 obj_priv->active = 1;
1433         }
1434         /* Move from whatever list we were on to the tail of execution. */
1435         spin_lock(&dev_priv->mm.active_list_lock);
1436         list_move_tail(&obj_priv->list,
1437                        &dev_priv->mm.active_list);
1438         spin_unlock(&dev_priv->mm.active_list_lock);
1439         obj_priv->last_rendering_seqno = seqno;
1440 }
1441
1442 static void
1443 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1444 {
1445         struct drm_device *dev = obj->dev;
1446         drm_i915_private_t *dev_priv = dev->dev_private;
1447         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1448
1449         BUG_ON(!obj_priv->active);
1450         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1451         obj_priv->last_rendering_seqno = 0;
1452 }
1453
1454 static void
1455 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1456 {
1457         struct drm_device *dev = obj->dev;
1458         drm_i915_private_t *dev_priv = dev->dev_private;
1459         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1460
1461         i915_verify_inactive(dev, __FILE__, __LINE__);
1462         if (obj_priv->pin_count != 0)
1463                 list_del_init(&obj_priv->list);
1464         else
1465                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1466
1467         obj_priv->last_rendering_seqno = 0;
1468         if (obj_priv->active) {
1469                 obj_priv->active = 0;
1470                 drm_gem_object_unreference(obj);
1471         }
1472         i915_verify_inactive(dev, __FILE__, __LINE__);
1473 }
1474
1475 /**
1476  * Creates a new sequence number, emitting a write of it to the status page
1477  * plus an interrupt, which will trigger i915_user_interrupt_handler.
1478  *
1479  * Must be called with struct_lock held.
1480  *
1481  * Returned sequence numbers are nonzero on success.
1482  */
1483 static uint32_t
1484 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1485                  uint32_t flush_domains)
1486 {
1487         drm_i915_private_t *dev_priv = dev->dev_private;
1488         struct drm_i915_file_private *i915_file_priv = NULL;
1489         struct drm_i915_gem_request *request;
1490         uint32_t seqno;
1491         int was_empty;
1492         RING_LOCALS;
1493
1494         if (file_priv != NULL)
1495                 i915_file_priv = file_priv->driver_priv;
1496
1497         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
1498         if (request == NULL)
1499                 return 0;
1500
1501         /* Grab the seqno we're going to make this request be, and bump the
1502          * next (skipping 0 so it can be the reserved no-seqno value).
1503          */
1504         seqno = dev_priv->mm.next_gem_seqno;
1505         dev_priv->mm.next_gem_seqno++;
1506         if (dev_priv->mm.next_gem_seqno == 0)
1507                 dev_priv->mm.next_gem_seqno++;
1508
1509         BEGIN_LP_RING(4);
1510         OUT_RING(MI_STORE_DWORD_INDEX);
1511         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1512         OUT_RING(seqno);
1513
1514         OUT_RING(MI_USER_INTERRUPT);
1515         ADVANCE_LP_RING();
1516
1517         DRM_DEBUG("%d\n", seqno);
1518
1519         request->seqno = seqno;
1520         request->emitted_jiffies = jiffies;
1521         was_empty = list_empty(&dev_priv->mm.request_list);
1522         list_add_tail(&request->list, &dev_priv->mm.request_list);
1523         if (i915_file_priv) {
1524                 list_add_tail(&request->client_list,
1525                               &i915_file_priv->mm.request_list);
1526         } else {
1527                 INIT_LIST_HEAD(&request->client_list);
1528         }
1529
1530         /* Associate any objects on the flushing list matching the write
1531          * domain we're flushing with our flush.
1532          */
1533         if (flush_domains != 0) {
1534                 struct drm_i915_gem_object *obj_priv, *next;
1535
1536                 list_for_each_entry_safe(obj_priv, next,
1537                                          &dev_priv->mm.flushing_list, list) {
1538                         struct drm_gem_object *obj = obj_priv->obj;
1539
1540                         if ((obj->write_domain & flush_domains) ==
1541                             obj->write_domain) {
1542                                 obj->write_domain = 0;
1543                                 i915_gem_object_move_to_active(obj, seqno);
1544                         }
1545                 }
1546
1547         }
1548
1549         if (was_empty && !dev_priv->mm.suspended)
1550                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1551         return seqno;
1552 }
1553
1554 /**
1555  * Command execution barrier
1556  *
1557  * Ensures that all commands in the ring are finished
1558  * before signalling the CPU
1559  */
1560 static uint32_t
1561 i915_retire_commands(struct drm_device *dev)
1562 {
1563         drm_i915_private_t *dev_priv = dev->dev_private;
1564         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1565         uint32_t flush_domains = 0;
1566         RING_LOCALS;
1567
1568         /* The sampler always gets flushed on i965 (sigh) */
1569         if (IS_I965G(dev))
1570                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1571         BEGIN_LP_RING(2);
1572         OUT_RING(cmd);
1573         OUT_RING(0); /* noop */
1574         ADVANCE_LP_RING();
1575         return flush_domains;
1576 }
1577
1578 /**
1579  * Moves buffers associated only with the given active seqno from the active
1580  * to inactive list, potentially freeing them.
1581  */
1582 static void
1583 i915_gem_retire_request(struct drm_device *dev,
1584                         struct drm_i915_gem_request *request)
1585 {
1586         drm_i915_private_t *dev_priv = dev->dev_private;
1587
1588         /* Move any buffers on the active list that are no longer referenced
1589          * by the ringbuffer to the flushing/inactive lists as appropriate.
1590          */
1591         spin_lock(&dev_priv->mm.active_list_lock);
1592         while (!list_empty(&dev_priv->mm.active_list)) {
1593                 struct drm_gem_object *obj;
1594                 struct drm_i915_gem_object *obj_priv;
1595
1596                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1597                                             struct drm_i915_gem_object,
1598                                             list);
1599                 obj = obj_priv->obj;
1600
1601                 /* If the seqno being retired doesn't match the oldest in the
1602                  * list, then the oldest in the list must still be newer than
1603                  * this seqno.
1604                  */
1605                 if (obj_priv->last_rendering_seqno != request->seqno)
1606                         goto out;
1607
1608 #if WATCH_LRU
1609                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1610                          __func__, request->seqno, obj);
1611 #endif
1612
1613                 if (obj->write_domain != 0)
1614                         i915_gem_object_move_to_flushing(obj);
1615                 else {
1616                         /* Take a reference on the object so it won't be
1617                          * freed while the spinlock is held.  The list
1618                          * protection for this spinlock is safe when breaking
1619                          * the lock like this since the next thing we do
1620                          * is just get the head of the list again.
1621                          */
1622                         drm_gem_object_reference(obj);
1623                         i915_gem_object_move_to_inactive(obj);
1624                         spin_unlock(&dev_priv->mm.active_list_lock);
1625                         drm_gem_object_unreference(obj);
1626                         spin_lock(&dev_priv->mm.active_list_lock);
1627                 }
1628         }
1629 out:
1630         spin_unlock(&dev_priv->mm.active_list_lock);
1631 }
1632
1633 /**
1634  * Returns true if seq1 is later than seq2.
1635  */
1636 static int
1637 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1638 {
1639         return (int32_t)(seq1 - seq2) >= 0;
1640 }
1641
1642 uint32_t
1643 i915_get_gem_seqno(struct drm_device *dev)
1644 {
1645         drm_i915_private_t *dev_priv = dev->dev_private;
1646
1647         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1648 }
1649
1650 /**
1651  * This function clears the request list as sequence numbers are passed.
1652  */
1653 void
1654 i915_gem_retire_requests(struct drm_device *dev)
1655 {
1656         drm_i915_private_t *dev_priv = dev->dev_private;
1657         uint32_t seqno;
1658
1659         if (!dev_priv->hw_status_page)
1660                 return;
1661
1662         seqno = i915_get_gem_seqno(dev);
1663
1664         while (!list_empty(&dev_priv->mm.request_list)) {
1665                 struct drm_i915_gem_request *request;
1666                 uint32_t retiring_seqno;
1667
1668                 request = list_first_entry(&dev_priv->mm.request_list,
1669                                            struct drm_i915_gem_request,
1670                                            list);
1671                 retiring_seqno = request->seqno;
1672
1673                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1674                     dev_priv->mm.wedged) {
1675                         i915_gem_retire_request(dev, request);
1676
1677                         list_del(&request->list);
1678                         list_del(&request->client_list);
1679                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1680                 } else
1681                         break;
1682         }
1683 }
1684
1685 void
1686 i915_gem_retire_work_handler(struct work_struct *work)
1687 {
1688         drm_i915_private_t *dev_priv;
1689         struct drm_device *dev;
1690
1691         dev_priv = container_of(work, drm_i915_private_t,
1692                                 mm.retire_work.work);
1693         dev = dev_priv->dev;
1694
1695         mutex_lock(&dev->struct_mutex);
1696         i915_gem_retire_requests(dev);
1697         if (!dev_priv->mm.suspended &&
1698             !list_empty(&dev_priv->mm.request_list))
1699                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1700         mutex_unlock(&dev->struct_mutex);
1701 }
1702
1703 /**
1704  * Waits for a sequence number to be signaled, and cleans up the
1705  * request and object lists appropriately for that event.
1706  */
1707 static int
1708 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1709 {
1710         drm_i915_private_t *dev_priv = dev->dev_private;
1711         u32 ier;
1712         int ret = 0;
1713
1714         BUG_ON(seqno == 0);
1715
1716         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1717                 if (IS_IGDNG(dev))
1718                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1719                 else
1720                         ier = I915_READ(IER);
1721                 if (!ier) {
1722                         DRM_ERROR("something (likely vbetool) disabled "
1723                                   "interrupts, re-enabling\n");
1724                         i915_driver_irq_preinstall(dev);
1725                         i915_driver_irq_postinstall(dev);
1726                 }
1727
1728                 dev_priv->mm.waiting_gem_seqno = seqno;
1729                 i915_user_irq_get(dev);
1730                 ret = wait_event_interruptible(dev_priv->irq_queue,
1731                                                i915_seqno_passed(i915_get_gem_seqno(dev),
1732                                                                  seqno) ||
1733                                                dev_priv->mm.wedged);
1734                 i915_user_irq_put(dev);
1735                 dev_priv->mm.waiting_gem_seqno = 0;
1736         }
1737         if (dev_priv->mm.wedged)
1738                 ret = -EIO;
1739
1740         if (ret && ret != -ERESTARTSYS)
1741                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1742                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1743
1744         /* Directly dispatch request retiring.  While we have the work queue
1745          * to handle this, the waiter on a request often wants an associated
1746          * buffer to have made it to the inactive list, and we would need
1747          * a separate wait queue to handle that.
1748          */
1749         if (ret == 0)
1750                 i915_gem_retire_requests(dev);
1751
1752         return ret;
1753 }
1754
1755 static void
1756 i915_gem_flush(struct drm_device *dev,
1757                uint32_t invalidate_domains,
1758                uint32_t flush_domains)
1759 {
1760         drm_i915_private_t *dev_priv = dev->dev_private;
1761         uint32_t cmd;
1762         RING_LOCALS;
1763
1764 #if WATCH_EXEC
1765         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1766                   invalidate_domains, flush_domains);
1767 #endif
1768
1769         if (flush_domains & I915_GEM_DOMAIN_CPU)
1770                 drm_agp_chipset_flush(dev);
1771
1772         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1773                                                      I915_GEM_DOMAIN_GTT)) {
1774                 /*
1775                  * read/write caches:
1776                  *
1777                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1778                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1779                  * also flushed at 2d versus 3d pipeline switches.
1780                  *
1781                  * read-only caches:
1782                  *
1783                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1784                  * MI_READ_FLUSH is set, and is always flushed on 965.
1785                  *
1786                  * I915_GEM_DOMAIN_COMMAND may not exist?
1787                  *
1788                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1789                  * invalidated when MI_EXE_FLUSH is set.
1790                  *
1791                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1792                  * invalidated with every MI_FLUSH.
1793                  *
1794                  * TLBs:
1795                  *
1796                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1797                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1798                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1799                  * are flushed at any MI_FLUSH.
1800                  */
1801
1802                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1803                 if ((invalidate_domains|flush_domains) &
1804                     I915_GEM_DOMAIN_RENDER)
1805                         cmd &= ~MI_NO_WRITE_FLUSH;
1806                 if (!IS_I965G(dev)) {
1807                         /*
1808                          * On the 965, the sampler cache always gets flushed
1809                          * and this bit is reserved.
1810                          */
1811                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1812                                 cmd |= MI_READ_FLUSH;
1813                 }
1814                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1815                         cmd |= MI_EXE_FLUSH;
1816
1817 #if WATCH_EXEC
1818                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1819 #endif
1820                 BEGIN_LP_RING(2);
1821                 OUT_RING(cmd);
1822                 OUT_RING(0); /* noop */
1823                 ADVANCE_LP_RING();
1824         }
1825 }
1826
1827 /**
1828  * Ensures that all rendering to the object has completed and the object is
1829  * safe to unbind from the GTT or access from the CPU.
1830  */
1831 static int
1832 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1833 {
1834         struct drm_device *dev = obj->dev;
1835         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1836         int ret;
1837
1838         /* This function only exists to support waiting for existing rendering,
1839          * not for emitting required flushes.
1840          */
1841         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1842
1843         /* If there is rendering queued on the buffer being evicted, wait for
1844          * it.
1845          */
1846         if (obj_priv->active) {
1847 #if WATCH_BUF
1848                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1849                           __func__, obj, obj_priv->last_rendering_seqno);
1850 #endif
1851                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1852                 if (ret != 0)
1853                         return ret;
1854         }
1855
1856         return 0;
1857 }
1858
1859 /**
1860  * Unbinds an object from the GTT aperture.
1861  */
1862 int
1863 i915_gem_object_unbind(struct drm_gem_object *obj)
1864 {
1865         struct drm_device *dev = obj->dev;
1866         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1867         loff_t offset;
1868         int ret = 0;
1869
1870 #if WATCH_BUF
1871         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1872         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1873 #endif
1874         if (obj_priv->gtt_space == NULL)
1875                 return 0;
1876
1877         if (obj_priv->pin_count != 0) {
1878                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1879                 return -EINVAL;
1880         }
1881
1882         /* Move the object to the CPU domain to ensure that
1883          * any possible CPU writes while it's not in the GTT
1884          * are flushed when we go to remap it. This will
1885          * also ensure that all pending GPU writes are finished
1886          * before we unbind.
1887          */
1888         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1889         if (ret) {
1890                 if (ret != -ERESTARTSYS)
1891                         DRM_ERROR("set_domain failed: %d\n", ret);
1892                 return ret;
1893         }
1894
1895         if (obj_priv->agp_mem != NULL) {
1896                 drm_unbind_agp(obj_priv->agp_mem);
1897                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1898                 obj_priv->agp_mem = NULL;
1899         }
1900
1901         BUG_ON(obj_priv->active);
1902
1903         /* blow away mappings if mapped through GTT */
1904         offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
1905         if (dev->dev_mapping)
1906                 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
1907
1908         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1909                 i915_gem_clear_fence_reg(obj);
1910
1911         i915_gem_object_put_pages(obj);
1912
1913         if (obj_priv->gtt_space) {
1914                 atomic_dec(&dev->gtt_count);
1915                 atomic_sub(obj->size, &dev->gtt_memory);
1916
1917                 drm_mm_put_block(obj_priv->gtt_space);
1918                 obj_priv->gtt_space = NULL;
1919         }
1920
1921         /* Remove ourselves from the LRU list if present. */
1922         if (!list_empty(&obj_priv->list))
1923                 list_del_init(&obj_priv->list);
1924
1925         return 0;
1926 }
1927
1928 static int
1929 i915_gem_evict_something(struct drm_device *dev)
1930 {
1931         drm_i915_private_t *dev_priv = dev->dev_private;
1932         struct drm_gem_object *obj;
1933         struct drm_i915_gem_object *obj_priv;
1934         int ret = 0;
1935
1936         for (;;) {
1937                 /* If there's an inactive buffer available now, grab it
1938                  * and be done.
1939                  */
1940                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1941                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1942                                                     struct drm_i915_gem_object,
1943                                                     list);
1944                         obj = obj_priv->obj;
1945                         BUG_ON(obj_priv->pin_count != 0);
1946 #if WATCH_LRU
1947                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1948 #endif
1949                         BUG_ON(obj_priv->active);
1950
1951                         /* Wait on the rendering and unbind the buffer. */
1952                         ret = i915_gem_object_unbind(obj);
1953                         break;
1954                 }
1955
1956                 /* If we didn't get anything, but the ring is still processing
1957                  * things, wait for one of those things to finish and hopefully
1958                  * leave us a buffer to evict.
1959                  */
1960                 if (!list_empty(&dev_priv->mm.request_list)) {
1961                         struct drm_i915_gem_request *request;
1962
1963                         request = list_first_entry(&dev_priv->mm.request_list,
1964                                                    struct drm_i915_gem_request,
1965                                                    list);
1966
1967                         ret = i915_wait_request(dev, request->seqno);
1968                         if (ret)
1969                                 break;
1970
1971                         /* if waiting caused an object to become inactive,
1972                          * then loop around and wait for it. Otherwise, we
1973                          * assume that waiting freed and unbound something,
1974                          * so there should now be some space in the GTT
1975                          */
1976                         if (!list_empty(&dev_priv->mm.inactive_list))
1977                                 continue;
1978                         break;
1979                 }
1980
1981                 /* If we didn't have anything on the request list but there
1982                  * are buffers awaiting a flush, emit one and try again.
1983                  * When we wait on it, those buffers waiting for that flush
1984                  * will get moved to inactive.
1985                  */
1986                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1987                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1988                                                     struct drm_i915_gem_object,
1989                                                     list);
1990                         obj = obj_priv->obj;
1991
1992                         i915_gem_flush(dev,
1993                                        obj->write_domain,
1994                                        obj->write_domain);
1995                         i915_add_request(dev, NULL, obj->write_domain);
1996
1997                         obj = NULL;
1998                         continue;
1999                 }
2000
2001                 DRM_ERROR("inactive empty %d request empty %d "
2002                           "flushing empty %d\n",
2003                           list_empty(&dev_priv->mm.inactive_list),
2004                           list_empty(&dev_priv->mm.request_list),
2005                           list_empty(&dev_priv->mm.flushing_list));
2006                 /* If we didn't do any of the above, there's nothing to be done
2007                  * and we just can't fit it in.
2008                  */
2009                 return -ENOMEM;
2010         }
2011         return ret;
2012 }
2013
2014 static int
2015 i915_gem_evict_everything(struct drm_device *dev)
2016 {
2017         int ret;
2018
2019         for (;;) {
2020                 ret = i915_gem_evict_something(dev);
2021                 if (ret != 0)
2022                         break;
2023         }
2024         if (ret == -ENOMEM)
2025                 return 0;
2026         return ret;
2027 }
2028
2029 int
2030 i915_gem_object_get_pages(struct drm_gem_object *obj)
2031 {
2032         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2033         int page_count, i;
2034         struct address_space *mapping;
2035         struct inode *inode;
2036         struct page *page;
2037         int ret;
2038
2039         if (obj_priv->pages_refcount++ != 0)
2040                 return 0;
2041
2042         /* Get the list of pages out of our struct file.  They'll be pinned
2043          * at this point until we release them.
2044          */
2045         page_count = obj->size / PAGE_SIZE;
2046         BUG_ON(obj_priv->pages != NULL);
2047         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2048         if (obj_priv->pages == NULL) {
2049                 DRM_ERROR("Faled to allocate page list\n");
2050                 obj_priv->pages_refcount--;
2051                 return -ENOMEM;
2052         }
2053
2054         inode = obj->filp->f_path.dentry->d_inode;
2055         mapping = inode->i_mapping;
2056         for (i = 0; i < page_count; i++) {
2057                 page = read_mapping_page(mapping, i, NULL);
2058                 if (IS_ERR(page)) {
2059                         ret = PTR_ERR(page);
2060                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
2061                         i915_gem_object_put_pages(obj);
2062                         return ret;
2063                 }
2064                 obj_priv->pages[i] = page;
2065         }
2066
2067         if (obj_priv->tiling_mode != I915_TILING_NONE)
2068                 i915_gem_object_do_bit_17_swizzle(obj);
2069
2070         return 0;
2071 }
2072
2073 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2074 {
2075         struct drm_gem_object *obj = reg->obj;
2076         struct drm_device *dev = obj->dev;
2077         drm_i915_private_t *dev_priv = dev->dev_private;
2078         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2079         int regnum = obj_priv->fence_reg;
2080         uint64_t val;
2081
2082         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2083                     0xfffff000) << 32;
2084         val |= obj_priv->gtt_offset & 0xfffff000;
2085         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2086         if (obj_priv->tiling_mode == I915_TILING_Y)
2087                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2088         val |= I965_FENCE_REG_VALID;
2089
2090         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2091 }
2092
2093 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2094 {
2095         struct drm_gem_object *obj = reg->obj;
2096         struct drm_device *dev = obj->dev;
2097         drm_i915_private_t *dev_priv = dev->dev_private;
2098         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2099         int regnum = obj_priv->fence_reg;
2100         int tile_width;
2101         uint32_t fence_reg, val;
2102         uint32_t pitch_val;
2103
2104         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2105             (obj_priv->gtt_offset & (obj->size - 1))) {
2106                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2107                      __func__, obj_priv->gtt_offset, obj->size);
2108                 return;
2109         }
2110
2111         if (obj_priv->tiling_mode == I915_TILING_Y &&
2112             HAS_128_BYTE_Y_TILING(dev))
2113                 tile_width = 128;
2114         else
2115                 tile_width = 512;
2116
2117         /* Note: pitch better be a power of two tile widths */
2118         pitch_val = obj_priv->stride / tile_width;
2119         pitch_val = ffs(pitch_val) - 1;
2120
2121         val = obj_priv->gtt_offset;
2122         if (obj_priv->tiling_mode == I915_TILING_Y)
2123                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2124         val |= I915_FENCE_SIZE_BITS(obj->size);
2125         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2126         val |= I830_FENCE_REG_VALID;
2127
2128         if (regnum < 8)
2129                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2130         else
2131                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2132         I915_WRITE(fence_reg, val);
2133 }
2134
2135 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2136 {
2137         struct drm_gem_object *obj = reg->obj;
2138         struct drm_device *dev = obj->dev;
2139         drm_i915_private_t *dev_priv = dev->dev_private;
2140         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2141         int regnum = obj_priv->fence_reg;
2142         uint32_t val;
2143         uint32_t pitch_val;
2144         uint32_t fence_size_bits;
2145
2146         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2147             (obj_priv->gtt_offset & (obj->size - 1))) {
2148                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2149                      __func__, obj_priv->gtt_offset);
2150                 return;
2151         }
2152
2153         pitch_val = obj_priv->stride / 128;
2154         pitch_val = ffs(pitch_val) - 1;
2155         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2156
2157         val = obj_priv->gtt_offset;
2158         if (obj_priv->tiling_mode == I915_TILING_Y)
2159                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2160         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2161         WARN_ON(fence_size_bits & ~0x00000f00);
2162         val |= fence_size_bits;
2163         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2164         val |= I830_FENCE_REG_VALID;
2165
2166         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2167
2168 }
2169
2170 /**
2171  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2172  * @obj: object to map through a fence reg
2173  * @write: object is about to be written
2174  *
2175  * When mapping objects through the GTT, userspace wants to be able to write
2176  * to them without having to worry about swizzling if the object is tiled.
2177  *
2178  * This function walks the fence regs looking for a free one for @obj,
2179  * stealing one if it can't find any.
2180  *
2181  * It then sets up the reg based on the object's properties: address, pitch
2182  * and tiling format.
2183  */
2184 static int
2185 i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
2186 {
2187         struct drm_device *dev = obj->dev;
2188         struct drm_i915_private *dev_priv = dev->dev_private;
2189         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2190         struct drm_i915_fence_reg *reg = NULL;
2191         struct drm_i915_gem_object *old_obj_priv = NULL;
2192         int i, ret, avail;
2193
2194         switch (obj_priv->tiling_mode) {
2195         case I915_TILING_NONE:
2196                 WARN(1, "allocating a fence for non-tiled object?\n");
2197                 break;
2198         case I915_TILING_X:
2199                 if (!obj_priv->stride)
2200                         return -EINVAL;
2201                 WARN((obj_priv->stride & (512 - 1)),
2202                      "object 0x%08x is X tiled but has non-512B pitch\n",
2203                      obj_priv->gtt_offset);
2204                 break;
2205         case I915_TILING_Y:
2206                 if (!obj_priv->stride)
2207                         return -EINVAL;
2208                 WARN((obj_priv->stride & (128 - 1)),
2209                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2210                      obj_priv->gtt_offset);
2211                 break;
2212         }
2213
2214         /* First try to find a free reg */
2215 try_again:
2216         avail = 0;
2217         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2218                 reg = &dev_priv->fence_regs[i];
2219                 if (!reg->obj)
2220                         break;
2221
2222                 old_obj_priv = reg->obj->driver_private;
2223                 if (!old_obj_priv->pin_count)
2224                     avail++;
2225         }
2226
2227         /* None available, try to steal one or wait for a user to finish */
2228         if (i == dev_priv->num_fence_regs) {
2229                 uint32_t seqno = dev_priv->mm.next_gem_seqno;
2230                 loff_t offset;
2231
2232                 if (avail == 0)
2233                         return -ENOMEM;
2234
2235                 for (i = dev_priv->fence_reg_start;
2236                      i < dev_priv->num_fence_regs; i++) {
2237                         uint32_t this_seqno;
2238
2239                         reg = &dev_priv->fence_regs[i];
2240                         old_obj_priv = reg->obj->driver_private;
2241
2242                         if (old_obj_priv->pin_count)
2243                                 continue;
2244
2245                         /* i915 uses fences for GPU access to tiled buffers */
2246                         if (IS_I965G(dev) || !old_obj_priv->active)
2247                                 break;
2248
2249                         /* find the seqno of the first available fence */
2250                         this_seqno = old_obj_priv->last_rendering_seqno;
2251                         if (this_seqno != 0 &&
2252                             reg->obj->write_domain == 0 &&
2253                             i915_seqno_passed(seqno, this_seqno))
2254                                 seqno = this_seqno;
2255                 }
2256
2257                 /*
2258                  * Now things get ugly... we have to wait for one of the
2259                  * objects to finish before trying again.
2260                  */
2261                 if (i == dev_priv->num_fence_regs) {
2262                         if (seqno == dev_priv->mm.next_gem_seqno) {
2263                                 i915_gem_flush(dev,
2264                                                I915_GEM_GPU_DOMAINS,
2265                                                I915_GEM_GPU_DOMAINS);
2266                                 seqno = i915_add_request(dev, NULL,
2267                                                          I915_GEM_GPU_DOMAINS);
2268                                 if (seqno == 0)
2269                                         return -ENOMEM;
2270                         }
2271
2272                         ret = i915_wait_request(dev, seqno);
2273                         if (ret)
2274                                 return ret;
2275                         goto try_again;
2276                 }
2277
2278                 /*
2279                  * Zap this virtual mapping so we can set up a fence again
2280                  * for this object next time we need it.
2281                  */
2282                 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
2283                 if (dev->dev_mapping)
2284                         unmap_mapping_range(dev->dev_mapping, offset,
2285                                             reg->obj->size, 1);
2286                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2287         }
2288
2289         obj_priv->fence_reg = i;
2290         reg->obj = obj;
2291
2292         if (IS_I965G(dev))
2293                 i965_write_fence_reg(reg);
2294         else if (IS_I9XX(dev))
2295                 i915_write_fence_reg(reg);
2296         else
2297                 i830_write_fence_reg(reg);
2298
2299         return 0;
2300 }
2301
2302 /**
2303  * i915_gem_clear_fence_reg - clear out fence register info
2304  * @obj: object to clear
2305  *
2306  * Zeroes out the fence register itself and clears out the associated
2307  * data structures in dev_priv and obj_priv.
2308  */
2309 static void
2310 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2311 {
2312         struct drm_device *dev = obj->dev;
2313         drm_i915_private_t *dev_priv = dev->dev_private;
2314         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2315
2316         if (IS_I965G(dev))
2317                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2318         else {
2319                 uint32_t fence_reg;
2320
2321                 if (obj_priv->fence_reg < 8)
2322                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2323                 else
2324                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2325                                                        8) * 4;
2326
2327                 I915_WRITE(fence_reg, 0);
2328         }
2329
2330         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2331         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2332 }
2333
2334 /**
2335  * Finds free space in the GTT aperture and binds the object there.
2336  */
2337 static int
2338 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2339 {
2340         struct drm_device *dev = obj->dev;
2341         drm_i915_private_t *dev_priv = dev->dev_private;
2342         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2343         struct drm_mm_node *free_space;
2344         int page_count, ret;
2345
2346         if (dev_priv->mm.suspended)
2347                 return -EBUSY;
2348         if (alignment == 0)
2349                 alignment = i915_gem_get_gtt_alignment(obj);
2350         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2351                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2352                 return -EINVAL;
2353         }
2354
2355  search_free:
2356         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2357                                         obj->size, alignment, 0);
2358         if (free_space != NULL) {
2359                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2360                                                        alignment);
2361                 if (obj_priv->gtt_space != NULL) {
2362                         obj_priv->gtt_space->private = obj;
2363                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2364                 }
2365         }
2366         if (obj_priv->gtt_space == NULL) {
2367                 bool lists_empty;
2368
2369                 /* If the gtt is empty and we're still having trouble
2370                  * fitting our object in, we're out of memory.
2371                  */
2372 #if WATCH_LRU
2373                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2374 #endif
2375                 spin_lock(&dev_priv->mm.active_list_lock);
2376                 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2377                                list_empty(&dev_priv->mm.flushing_list) &&
2378                                list_empty(&dev_priv->mm.active_list));
2379                 spin_unlock(&dev_priv->mm.active_list_lock);
2380                 if (lists_empty) {
2381                         DRM_ERROR("GTT full, but LRU list empty\n");
2382                         return -ENOMEM;
2383                 }
2384
2385                 ret = i915_gem_evict_something(dev);
2386                 if (ret != 0) {
2387                         if (ret != -ERESTARTSYS)
2388                                 DRM_ERROR("Failed to evict a buffer %d\n", ret);
2389                         return ret;
2390                 }
2391                 goto search_free;
2392         }
2393
2394 #if WATCH_BUF
2395         DRM_INFO("Binding object of size %d at 0x%08x\n",
2396                  obj->size, obj_priv->gtt_offset);
2397 #endif
2398         ret = i915_gem_object_get_pages(obj);
2399         if (ret) {
2400                 drm_mm_put_block(obj_priv->gtt_space);
2401                 obj_priv->gtt_space = NULL;
2402                 return ret;
2403         }
2404
2405         page_count = obj->size / PAGE_SIZE;
2406         /* Create an AGP memory structure pointing at our pages, and bind it
2407          * into the GTT.
2408          */
2409         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2410                                                obj_priv->pages,
2411                                                page_count,
2412                                                obj_priv->gtt_offset,
2413                                                obj_priv->agp_type);
2414         if (obj_priv->agp_mem == NULL) {
2415                 i915_gem_object_put_pages(obj);
2416                 drm_mm_put_block(obj_priv->gtt_space);
2417                 obj_priv->gtt_space = NULL;
2418                 return -ENOMEM;
2419         }
2420         atomic_inc(&dev->gtt_count);
2421         atomic_add(obj->size, &dev->gtt_memory);
2422
2423         /* Assert that the object is not currently in any GPU domain. As it
2424          * wasn't in the GTT, there shouldn't be any way it could have been in
2425          * a GPU cache
2426          */
2427         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2428         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2429
2430         return 0;
2431 }
2432
2433 void
2434 i915_gem_clflush_object(struct drm_gem_object *obj)
2435 {
2436         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2437
2438         /* If we don't have a page list set up, then we're not pinned
2439          * to GPU, and we can ignore the cache flush because it'll happen
2440          * again at bind time.
2441          */
2442         if (obj_priv->pages == NULL)
2443                 return;
2444
2445         /* XXX: The 865 in particular appears to be weird in how it handles
2446          * cache flushing.  We haven't figured it out, but the
2447          * clflush+agp_chipset_flush doesn't appear to successfully get the
2448          * data visible to the PGU, while wbinvd + agp_chipset_flush does.
2449          */
2450         if (IS_I865G(obj->dev)) {
2451                 wbinvd();
2452                 return;
2453         }
2454
2455         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2456 }
2457
2458 /** Flushes any GPU write domain for the object if it's dirty. */
2459 static void
2460 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2461 {
2462         struct drm_device *dev = obj->dev;
2463         uint32_t seqno;
2464
2465         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2466                 return;
2467
2468         /* Queue the GPU write cache flushing we need. */
2469         i915_gem_flush(dev, 0, obj->write_domain);
2470         seqno = i915_add_request(dev, NULL, obj->write_domain);
2471         obj->write_domain = 0;
2472         i915_gem_object_move_to_active(obj, seqno);
2473 }
2474
2475 /** Flushes the GTT write domain for the object if it's dirty. */
2476 static void
2477 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2478 {
2479         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2480                 return;
2481
2482         /* No actual flushing is required for the GTT write domain.   Writes
2483          * to it immediately go to main memory as far as we know, so there's
2484          * no chipset flush.  It also doesn't land in render cache.
2485          */
2486         obj->write_domain = 0;
2487 }
2488
2489 /** Flushes the CPU write domain for the object if it's dirty. */
2490 static void
2491 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2492 {
2493         struct drm_device *dev = obj->dev;
2494
2495         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2496                 return;
2497
2498         i915_gem_clflush_object(obj);
2499         drm_agp_chipset_flush(dev);
2500         obj->write_domain = 0;
2501 }
2502
2503 /**
2504  * Moves a single object to the GTT read, and possibly write domain.
2505  *
2506  * This function returns when the move is complete, including waiting on
2507  * flushes to occur.
2508  */
2509 int
2510 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2511 {
2512         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2513         int ret;
2514
2515         /* Not valid to be called on unbound objects. */
2516         if (obj_priv->gtt_space == NULL)
2517                 return -EINVAL;
2518
2519         i915_gem_object_flush_gpu_write_domain(obj);
2520         /* Wait on any GPU rendering and flushing to occur. */
2521         ret = i915_gem_object_wait_rendering(obj);
2522         if (ret != 0)
2523                 return ret;
2524
2525         /* If we're writing through the GTT domain, then CPU and GPU caches
2526          * will need to be invalidated at next use.
2527          */
2528         if (write)
2529                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2530
2531         i915_gem_object_flush_cpu_write_domain(obj);
2532
2533         /* It should now be out of any other write domains, and we can update
2534          * the domain values for our changes.
2535          */
2536         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2537         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2538         if (write) {
2539                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2540                 obj_priv->dirty = 1;
2541         }
2542
2543         return 0;
2544 }
2545
2546 /**
2547  * Moves a single object to the CPU read, and possibly write domain.
2548  *
2549  * This function returns when the move is complete, including waiting on
2550  * flushes to occur.
2551  */
2552 static int
2553 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2554 {
2555         int ret;
2556
2557         i915_gem_object_flush_gpu_write_domain(obj);
2558         /* Wait on any GPU rendering and flushing to occur. */
2559         ret = i915_gem_object_wait_rendering(obj);
2560         if (ret != 0)
2561                 return ret;
2562
2563         i915_gem_object_flush_gtt_write_domain(obj);
2564
2565         /* If we have a partially-valid cache of the object in the CPU,
2566          * finish invalidating it and free the per-page flags.
2567          */
2568         i915_gem_object_set_to_full_cpu_read_domain(obj);
2569
2570         /* Flush the CPU cache if it's still invalid. */
2571         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2572                 i915_gem_clflush_object(obj);
2573
2574                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2575         }
2576
2577         /* It should now be out of any other write domains, and we can update
2578          * the domain values for our changes.
2579          */
2580         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2581
2582         /* If we're writing through the CPU, then the GPU read domains will
2583          * need to be invalidated at next use.
2584          */
2585         if (write) {
2586                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2587                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2588         }
2589
2590         return 0;
2591 }
2592
2593 /*
2594  * Set the next domain for the specified object. This
2595  * may not actually perform the necessary flushing/invaliding though,
2596  * as that may want to be batched with other set_domain operations
2597  *
2598  * This is (we hope) the only really tricky part of gem. The goal
2599  * is fairly simple -- track which caches hold bits of the object
2600  * and make sure they remain coherent. A few concrete examples may
2601  * help to explain how it works. For shorthand, we use the notation
2602  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2603  * a pair of read and write domain masks.
2604  *
2605  * Case 1: the batch buffer
2606  *
2607  *      1. Allocated
2608  *      2. Written by CPU
2609  *      3. Mapped to GTT
2610  *      4. Read by GPU
2611  *      5. Unmapped from GTT
2612  *      6. Freed
2613  *
2614  *      Let's take these a step at a time
2615  *
2616  *      1. Allocated
2617  *              Pages allocated from the kernel may still have
2618  *              cache contents, so we set them to (CPU, CPU) always.
2619  *      2. Written by CPU (using pwrite)
2620  *              The pwrite function calls set_domain (CPU, CPU) and
2621  *              this function does nothing (as nothing changes)
2622  *      3. Mapped by GTT
2623  *              This function asserts that the object is not
2624  *              currently in any GPU-based read or write domains
2625  *      4. Read by GPU
2626  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2627  *              As write_domain is zero, this function adds in the
2628  *              current read domains (CPU+COMMAND, 0).
2629  *              flush_domains is set to CPU.
2630  *              invalidate_domains is set to COMMAND
2631  *              clflush is run to get data out of the CPU caches
2632  *              then i915_dev_set_domain calls i915_gem_flush to
2633  *              emit an MI_FLUSH and drm_agp_chipset_flush
2634  *      5. Unmapped from GTT
2635  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
2636  *              flush_domains and invalidate_domains end up both zero
2637  *              so no flushing/invalidating happens
2638  *      6. Freed
2639  *              yay, done
2640  *
2641  * Case 2: The shared render buffer
2642  *
2643  *      1. Allocated
2644  *      2. Mapped to GTT
2645  *      3. Read/written by GPU
2646  *      4. set_domain to (CPU,CPU)
2647  *      5. Read/written by CPU
2648  *      6. Read/written by GPU
2649  *
2650  *      1. Allocated
2651  *              Same as last example, (CPU, CPU)
2652  *      2. Mapped to GTT
2653  *              Nothing changes (assertions find that it is not in the GPU)
2654  *      3. Read/written by GPU
2655  *              execbuffer calls set_domain (RENDER, RENDER)
2656  *              flush_domains gets CPU
2657  *              invalidate_domains gets GPU
2658  *              clflush (obj)
2659  *              MI_FLUSH and drm_agp_chipset_flush
2660  *      4. set_domain (CPU, CPU)
2661  *              flush_domains gets GPU
2662  *              invalidate_domains gets CPU
2663  *              wait_rendering (obj) to make sure all drawing is complete.
2664  *              This will include an MI_FLUSH to get the data from GPU
2665  *              to memory
2666  *              clflush (obj) to invalidate the CPU cache
2667  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2668  *      5. Read/written by CPU
2669  *              cache lines are loaded and dirtied
2670  *      6. Read written by GPU
2671  *              Same as last GPU access
2672  *
2673  * Case 3: The constant buffer
2674  *
2675  *      1. Allocated
2676  *      2. Written by CPU
2677  *      3. Read by GPU
2678  *      4. Updated (written) by CPU again
2679  *      5. Read by GPU
2680  *
2681  *      1. Allocated
2682  *              (CPU, CPU)
2683  *      2. Written by CPU
2684  *              (CPU, CPU)
2685  *      3. Read by GPU
2686  *              (CPU+RENDER, 0)
2687  *              flush_domains = CPU
2688  *              invalidate_domains = RENDER
2689  *              clflush (obj)
2690  *              MI_FLUSH
2691  *              drm_agp_chipset_flush
2692  *      4. Updated (written) by CPU again
2693  *              (CPU, CPU)
2694  *              flush_domains = 0 (no previous write domain)
2695  *              invalidate_domains = 0 (no new read domains)
2696  *      5. Read by GPU
2697  *              (CPU+RENDER, 0)
2698  *              flush_domains = CPU
2699  *              invalidate_domains = RENDER
2700  *              clflush (obj)
2701  *              MI_FLUSH
2702  *              drm_agp_chipset_flush
2703  */
2704 static void
2705 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2706 {
2707         struct drm_device               *dev = obj->dev;
2708         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2709         uint32_t                        invalidate_domains = 0;
2710         uint32_t                        flush_domains = 0;
2711
2712         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2713         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2714
2715 #if WATCH_BUF
2716         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2717                  __func__, obj,
2718                  obj->read_domains, obj->pending_read_domains,
2719                  obj->write_domain, obj->pending_write_domain);
2720 #endif
2721         /*
2722          * If the object isn't moving to a new write domain,
2723          * let the object stay in multiple read domains
2724          */
2725         if (obj->pending_write_domain == 0)
2726                 obj->pending_read_domains |= obj->read_domains;
2727         else
2728                 obj_priv->dirty = 1;
2729
2730         /*
2731          * Flush the current write domain if
2732          * the new read domains don't match. Invalidate
2733          * any read domains which differ from the old
2734          * write domain
2735          */
2736         if (obj->write_domain &&
2737             obj->write_domain != obj->pending_read_domains) {
2738                 flush_domains |= obj->write_domain;
2739                 invalidate_domains |=
2740                         obj->pending_read_domains & ~obj->write_domain;
2741         }
2742         /*
2743          * Invalidate any read caches which may have
2744          * stale data. That is, any new read domains.
2745          */
2746         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2747         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2748 #if WATCH_BUF
2749                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2750                          __func__, flush_domains, invalidate_domains);
2751 #endif
2752                 i915_gem_clflush_object(obj);
2753         }
2754
2755         /* The actual obj->write_domain will be updated with
2756          * pending_write_domain after we emit the accumulated flush for all
2757          * of our domain changes in execbuffers (which clears objects'
2758          * write_domains).  So if we have a current write domain that we
2759          * aren't changing, set pending_write_domain to that.
2760          */
2761         if (flush_domains == 0 && obj->pending_write_domain == 0)
2762                 obj->pending_write_domain = obj->write_domain;
2763         obj->read_domains = obj->pending_read_domains;
2764
2765         dev->invalidate_domains |= invalidate_domains;
2766         dev->flush_domains |= flush_domains;
2767 #if WATCH_BUF
2768         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2769                  __func__,
2770                  obj->read_domains, obj->write_domain,
2771                  dev->invalidate_domains, dev->flush_domains);
2772 #endif
2773 }
2774
2775 /**
2776  * Moves the object from a partially CPU read to a full one.
2777  *
2778  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2779  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2780  */
2781 static void
2782 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2783 {
2784         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2785
2786         if (!obj_priv->page_cpu_valid)
2787                 return;
2788
2789         /* If we're partially in the CPU read domain, finish moving it in.
2790          */
2791         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2792                 int i;
2793
2794                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2795                         if (obj_priv->page_cpu_valid[i])
2796                                 continue;
2797                         drm_clflush_pages(obj_priv->pages + i, 1);
2798                 }
2799         }
2800
2801         /* Free the page_cpu_valid mappings which are now stale, whether
2802          * or not we've got I915_GEM_DOMAIN_CPU.
2803          */
2804         drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2805                  DRM_MEM_DRIVER);
2806         obj_priv->page_cpu_valid = NULL;
2807 }
2808
2809 /**
2810  * Set the CPU read domain on a range of the object.
2811  *
2812  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2813  * not entirely valid.  The page_cpu_valid member of the object flags which
2814  * pages have been flushed, and will be respected by
2815  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2816  * of the whole object.
2817  *
2818  * This function returns when the move is complete, including waiting on
2819  * flushes to occur.
2820  */
2821 static int
2822 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2823                                           uint64_t offset, uint64_t size)
2824 {
2825         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2826         int i, ret;
2827
2828         if (offset == 0 && size == obj->size)
2829                 return i915_gem_object_set_to_cpu_domain(obj, 0);
2830
2831         i915_gem_object_flush_gpu_write_domain(obj);
2832         /* Wait on any GPU rendering and flushing to occur. */
2833         ret = i915_gem_object_wait_rendering(obj);
2834         if (ret != 0)
2835                 return ret;
2836         i915_gem_object_flush_gtt_write_domain(obj);
2837
2838         /* If we're already fully in the CPU read domain, we're done. */
2839         if (obj_priv->page_cpu_valid == NULL &&
2840             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
2841                 return 0;
2842
2843         /* Otherwise, create/clear the per-page CPU read domain flag if we're
2844          * newly adding I915_GEM_DOMAIN_CPU
2845          */
2846         if (obj_priv->page_cpu_valid == NULL) {
2847                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2848                                                       DRM_MEM_DRIVER);
2849                 if (obj_priv->page_cpu_valid == NULL)
2850                         return -ENOMEM;
2851         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2852                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
2853
2854         /* Flush the cache on any pages that are still invalid from the CPU's
2855          * perspective.
2856          */
2857         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2858              i++) {
2859                 if (obj_priv->page_cpu_valid[i])
2860                         continue;
2861
2862                 drm_clflush_pages(obj_priv->pages + i, 1);
2863
2864                 obj_priv->page_cpu_valid[i] = 1;
2865         }
2866
2867         /* It should now be out of any other write domains, and we can update
2868          * the domain values for our changes.
2869          */
2870         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2871
2872         obj->read_domains |= I915_GEM_DOMAIN_CPU;
2873
2874         return 0;
2875 }
2876
2877 /**
2878  * Pin an object to the GTT and evaluate the relocations landing in it.
2879  */
2880 static int
2881 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2882                                  struct drm_file *file_priv,
2883                                  struct drm_i915_gem_exec_object *entry,
2884                                  struct drm_i915_gem_relocation_entry *relocs)
2885 {
2886         struct drm_device *dev = obj->dev;
2887         drm_i915_private_t *dev_priv = dev->dev_private;
2888         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2889         int i, ret;
2890         void __iomem *reloc_page;
2891
2892         /* Choose the GTT offset for our buffer and put it there. */
2893         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2894         if (ret)
2895                 return ret;
2896
2897         entry->offset = obj_priv->gtt_offset;
2898
2899         /* Apply the relocations, using the GTT aperture to avoid cache
2900          * flushing requirements.
2901          */
2902         for (i = 0; i < entry->relocation_count; i++) {
2903                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
2904                 struct drm_gem_object *target_obj;
2905                 struct drm_i915_gem_object *target_obj_priv;
2906                 uint32_t reloc_val, reloc_offset;
2907                 uint32_t __iomem *reloc_entry;
2908
2909                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
2910                                                    reloc->target_handle);
2911                 if (target_obj == NULL) {
2912                         i915_gem_object_unpin(obj);
2913                         return -EBADF;
2914                 }
2915                 target_obj_priv = target_obj->driver_private;
2916
2917                 /* The target buffer should have appeared before us in the
2918                  * exec_object list, so it should have a GTT space bound by now.
2919                  */
2920                 if (target_obj_priv->gtt_space == NULL) {
2921                         DRM_ERROR("No GTT space found for object %d\n",
2922                                   reloc->target_handle);
2923                         drm_gem_object_unreference(target_obj);
2924                         i915_gem_object_unpin(obj);
2925                         return -EINVAL;
2926                 }
2927
2928                 if (reloc->offset > obj->size - 4) {
2929                         DRM_ERROR("Relocation beyond object bounds: "
2930                                   "obj %p target %d offset %d size %d.\n",
2931                                   obj, reloc->target_handle,
2932                                   (int) reloc->offset, (int) obj->size);
2933                         drm_gem_object_unreference(target_obj);
2934                         i915_gem_object_unpin(obj);
2935                         return -EINVAL;
2936                 }
2937                 if (reloc->offset & 3) {
2938                         DRM_ERROR("Relocation not 4-byte aligned: "
2939                                   "obj %p target %d offset %d.\n",
2940                                   obj, reloc->target_handle,
2941                                   (int) reloc->offset);
2942                         drm_gem_object_unreference(target_obj);
2943                         i915_gem_object_unpin(obj);
2944                         return -EINVAL;
2945                 }
2946
2947                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
2948                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
2949                         DRM_ERROR("reloc with read/write CPU domains: "
2950                                   "obj %p target %d offset %d "
2951                                   "read %08x write %08x",
2952                                   obj, reloc->target_handle,
2953                                   (int) reloc->offset,
2954                                   reloc->read_domains,
2955                                   reloc->write_domain);
2956                         drm_gem_object_unreference(target_obj);
2957                         i915_gem_object_unpin(obj);
2958                         return -EINVAL;
2959                 }
2960
2961                 if (reloc->write_domain && target_obj->pending_write_domain &&
2962                     reloc->write_domain != target_obj->pending_write_domain) {
2963                         DRM_ERROR("Write domain conflict: "
2964                                   "obj %p target %d offset %d "
2965                                   "new %08x old %08x\n",
2966                                   obj, reloc->target_handle,
2967                                   (int) reloc->offset,
2968                                   reloc->write_domain,
2969                                   target_obj->pending_write_domain);
2970                         drm_gem_object_unreference(target_obj);
2971                         i915_gem_object_unpin(obj);
2972                         return -EINVAL;
2973                 }
2974
2975 #if WATCH_RELOC
2976                 DRM_INFO("%s: obj %p offset %08x target %d "
2977                          "read %08x write %08x gtt %08x "
2978                          "presumed %08x delta %08x\n",
2979                          __func__,
2980                          obj,
2981                          (int) reloc->offset,
2982                          (int) reloc->target_handle,
2983                          (int) reloc->read_domains,
2984                          (int) reloc->write_domain,
2985                          (int) target_obj_priv->gtt_offset,
2986                          (int) reloc->presumed_offset,
2987                          reloc->delta);
2988 #endif
2989
2990                 target_obj->pending_read_domains |= reloc->read_domains;
2991                 target_obj->pending_write_domain |= reloc->write_domain;
2992
2993                 /* If the relocation already has the right value in it, no
2994                  * more work needs to be done.
2995                  */
2996                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
2997                         drm_gem_object_unreference(target_obj);
2998                         continue;
2999                 }
3000
3001                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3002                 if (ret != 0) {
3003                         drm_gem_object_unreference(target_obj);
3004                         i915_gem_object_unpin(obj);
3005                         return -EINVAL;
3006                 }
3007
3008                 /* Map the page containing the relocation we're going to
3009                  * perform.
3010                  */
3011                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3012                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3013                                                       (reloc_offset &
3014                                                        ~(PAGE_SIZE - 1)));
3015                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3016                                                    (reloc_offset & (PAGE_SIZE - 1)));
3017                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3018
3019 #if WATCH_BUF
3020                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3021                           obj, (unsigned int) reloc->offset,
3022                           readl(reloc_entry), reloc_val);
3023 #endif
3024                 writel(reloc_val, reloc_entry);
3025                 io_mapping_unmap_atomic(reloc_page);
3026
3027                 /* The updated presumed offset for this entry will be
3028                  * copied back out to the user.
3029                  */
3030                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3031
3032                 drm_gem_object_unreference(target_obj);
3033         }
3034
3035 #if WATCH_BUF
3036         if (0)
3037                 i915_gem_dump_object(obj, 128, __func__, ~0);
3038 #endif
3039         return 0;
3040 }
3041
3042 /** Dispatch a batchbuffer to the ring
3043  */
3044 static int
3045 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3046                               struct drm_i915_gem_execbuffer *exec,
3047                               struct drm_clip_rect *cliprects,
3048                               uint64_t exec_offset)
3049 {
3050         drm_i915_private_t *dev_priv = dev->dev_private;
3051         int nbox = exec->num_cliprects;
3052         int i = 0, count;
3053         uint32_t exec_start, exec_len;
3054         RING_LOCALS;
3055
3056         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3057         exec_len = (uint32_t) exec->batch_len;
3058
3059         count = nbox ? nbox : 1;
3060
3061         for (i = 0; i < count; i++) {
3062                 if (i < nbox) {
3063                         int ret = i915_emit_box(dev, cliprects, i,
3064                                                 exec->DR1, exec->DR4);
3065                         if (ret)
3066                                 return ret;
3067                 }
3068
3069                 if (IS_I830(dev) || IS_845G(dev)) {
3070                         BEGIN_LP_RING(4);
3071                         OUT_RING(MI_BATCH_BUFFER);
3072                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3073                         OUT_RING(exec_start + exec_len - 4);
3074                         OUT_RING(0);
3075                         ADVANCE_LP_RING();
3076                 } else {
3077                         BEGIN_LP_RING(2);
3078                         if (IS_I965G(dev)) {
3079                                 OUT_RING(MI_BATCH_BUFFER_START |
3080                                          (2 << 6) |
3081                                          MI_BATCH_NON_SECURE_I965);
3082                                 OUT_RING(exec_start);
3083                         } else {
3084                                 OUT_RING(MI_BATCH_BUFFER_START |
3085                                          (2 << 6));
3086                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3087                         }
3088                         ADVANCE_LP_RING();
3089                 }
3090         }
3091
3092         /* XXX breadcrumb */
3093         return 0;
3094 }
3095
3096 /* Throttle our rendering by waiting until the ring has completed our requests
3097  * emitted over 20 msec ago.
3098  *
3099  * Note that if we were to use the current jiffies each time around the loop,
3100  * we wouldn't escape the function with any frames outstanding if the time to
3101  * render a frame was over 20ms.
3102  *
3103  * This should get us reasonable parallelism between CPU and GPU but also
3104  * relatively low latency when blocking on a particular request to finish.
3105  */
3106 static int
3107 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3108 {
3109         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3110         int ret = 0;
3111         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3112
3113         mutex_lock(&dev->struct_mutex);
3114         while (!list_empty(&i915_file_priv->mm.request_list)) {
3115                 struct drm_i915_gem_request *request;
3116
3117                 request = list_first_entry(&i915_file_priv->mm.request_list,
3118                                            struct drm_i915_gem_request,
3119                                            client_list);
3120
3121                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3122                         break;
3123
3124                 ret = i915_wait_request(dev, request->seqno);
3125                 if (ret != 0)
3126                         break;
3127         }
3128         mutex_unlock(&dev->struct_mutex);
3129
3130         return ret;
3131 }
3132
3133 static int
3134 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3135                               uint32_t buffer_count,
3136                               struct drm_i915_gem_relocation_entry **relocs)
3137 {
3138         uint32_t reloc_count = 0, reloc_index = 0, i;
3139         int ret;
3140
3141         *relocs = NULL;
3142         for (i = 0; i < buffer_count; i++) {
3143                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3144                         return -EINVAL;
3145                 reloc_count += exec_list[i].relocation_count;
3146         }
3147
3148         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3149         if (*relocs == NULL)
3150                 return -ENOMEM;
3151
3152         for (i = 0; i < buffer_count; i++) {
3153                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3154
3155                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3156
3157                 ret = copy_from_user(&(*relocs)[reloc_index],
3158                                      user_relocs,
3159                                      exec_list[i].relocation_count *
3160                                      sizeof(**relocs));
3161                 if (ret != 0) {
3162                         drm_free_large(*relocs);
3163                         *relocs = NULL;
3164                         return -EFAULT;
3165                 }
3166
3167                 reloc_index += exec_list[i].relocation_count;
3168         }
3169
3170         return 0;
3171 }
3172
3173 static int
3174 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3175                             uint32_t buffer_count,
3176                             struct drm_i915_gem_relocation_entry *relocs)
3177 {
3178         uint32_t reloc_count = 0, i;
3179         int ret = 0;
3180
3181         for (i = 0; i < buffer_count; i++) {
3182                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3183                 int unwritten;
3184
3185                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3186
3187                 unwritten = copy_to_user(user_relocs,
3188                                          &relocs[reloc_count],
3189                                          exec_list[i].relocation_count *
3190                                          sizeof(*relocs));
3191
3192                 if (unwritten) {
3193                         ret = -EFAULT;
3194                         goto err;
3195                 }
3196
3197                 reloc_count += exec_list[i].relocation_count;
3198         }
3199
3200 err:
3201         drm_free_large(relocs);
3202
3203         return ret;
3204 }
3205
3206 static int
3207 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3208                            uint64_t exec_offset)
3209 {
3210         uint32_t exec_start, exec_len;
3211
3212         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3213         exec_len = (uint32_t) exec->batch_len;
3214
3215         if ((exec_start | exec_len) & 0x7)
3216                 return -EINVAL;
3217
3218         if (!exec_start)
3219                 return -EINVAL;
3220
3221         return 0;
3222 }
3223
3224 int
3225 i915_gem_execbuffer(struct drm_device *dev, void *data,
3226                     struct drm_file *file_priv)
3227 {
3228         drm_i915_private_t *dev_priv = dev->dev_private;
3229         struct drm_i915_gem_execbuffer *args = data;
3230         struct drm_i915_gem_exec_object *exec_list = NULL;
3231         struct drm_gem_object **object_list = NULL;
3232         struct drm_gem_object *batch_obj;
3233         struct drm_i915_gem_object *obj_priv;
3234         struct drm_clip_rect *cliprects = NULL;
3235         struct drm_i915_gem_relocation_entry *relocs;
3236         int ret, ret2, i, pinned = 0;
3237         uint64_t exec_offset;
3238         uint32_t seqno, flush_domains, reloc_index;
3239         int pin_tries;
3240
3241 #if WATCH_EXEC
3242         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3243                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3244 #endif
3245
3246         if (args->buffer_count < 1) {
3247                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3248                 return -EINVAL;
3249         }
3250         /* Copy in the exec list from userland */
3251         exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3252         object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3253         if (exec_list == NULL || object_list == NULL) {
3254                 DRM_ERROR("Failed to allocate exec or object list "
3255                           "for %d buffers\n",
3256                           args->buffer_count);
3257                 ret = -ENOMEM;
3258                 goto pre_mutex_err;
3259         }
3260         ret = copy_from_user(exec_list,
3261                              (struct drm_i915_relocation_entry __user *)
3262                              (uintptr_t) args->buffers_ptr,
3263                              sizeof(*exec_list) * args->buffer_count);
3264         if (ret != 0) {
3265                 DRM_ERROR("copy %d exec entries failed %d\n",
3266                           args->buffer_count, ret);
3267                 goto pre_mutex_err;
3268         }
3269
3270         if (args->num_cliprects != 0) {
3271                 cliprects = drm_calloc(args->num_cliprects, sizeof(*cliprects),
3272                                        DRM_MEM_DRIVER);
3273                 if (cliprects == NULL)
3274                         goto pre_mutex_err;
3275
3276                 ret = copy_from_user(cliprects,
3277                                      (struct drm_clip_rect __user *)
3278                                      (uintptr_t) args->cliprects_ptr,
3279                                      sizeof(*cliprects) * args->num_cliprects);
3280                 if (ret != 0) {
3281                         DRM_ERROR("copy %d cliprects failed: %d\n",
3282                                   args->num_cliprects, ret);
3283                         goto pre_mutex_err;
3284                 }
3285         }
3286
3287         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3288                                             &relocs);
3289         if (ret != 0)
3290                 goto pre_mutex_err;
3291
3292         mutex_lock(&dev->struct_mutex);
3293
3294         i915_verify_inactive(dev, __FILE__, __LINE__);
3295
3296         if (dev_priv->mm.wedged) {
3297                 DRM_ERROR("Execbuf while wedged\n");
3298                 mutex_unlock(&dev->struct_mutex);
3299                 ret = -EIO;
3300                 goto pre_mutex_err;
3301         }
3302
3303         if (dev_priv->mm.suspended) {
3304                 DRM_ERROR("Execbuf while VT-switched.\n");
3305                 mutex_unlock(&dev->struct_mutex);
3306                 ret = -EBUSY;
3307                 goto pre_mutex_err;
3308         }
3309
3310         /* Look up object handles */
3311         for (i = 0; i < args->buffer_count; i++) {
3312                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3313                                                        exec_list[i].handle);
3314                 if (object_list[i] == NULL) {
3315                         DRM_ERROR("Invalid object handle %d at index %d\n",
3316                                    exec_list[i].handle, i);
3317                         ret = -EBADF;
3318                         goto err;
3319                 }
3320
3321                 obj_priv = object_list[i]->driver_private;
3322                 if (obj_priv->in_execbuffer) {
3323                         DRM_ERROR("Object %p appears more than once in object list\n",
3324                                    object_list[i]);
3325                         ret = -EBADF;
3326                         goto err;
3327                 }
3328                 obj_priv->in_execbuffer = true;
3329         }
3330
3331         /* Pin and relocate */
3332         for (pin_tries = 0; ; pin_tries++) {
3333                 ret = 0;
3334                 reloc_index = 0;
3335
3336                 for (i = 0; i < args->buffer_count; i++) {
3337                         object_list[i]->pending_read_domains = 0;
3338                         object_list[i]->pending_write_domain = 0;
3339                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3340                                                                file_priv,
3341                                                                &exec_list[i],
3342                                                                &relocs[reloc_index]);
3343                         if (ret)
3344                                 break;
3345                         pinned = i + 1;
3346                         reloc_index += exec_list[i].relocation_count;
3347                 }
3348                 /* success */
3349                 if (ret == 0)
3350                         break;
3351
3352                 /* error other than GTT full, or we've already tried again */
3353                 if (ret != -ENOMEM || pin_tries >= 1) {
3354                         if (ret != -ERESTARTSYS)
3355                                 DRM_ERROR("Failed to pin buffers %d\n", ret);
3356                         goto err;
3357                 }
3358
3359                 /* unpin all of our buffers */
3360                 for (i = 0; i < pinned; i++)
3361                         i915_gem_object_unpin(object_list[i]);
3362                 pinned = 0;
3363
3364                 /* evict everyone we can from the aperture */
3365                 ret = i915_gem_evict_everything(dev);
3366                 if (ret)
3367                         goto err;
3368         }
3369
3370         /* Set the pending read domains for the batch buffer to COMMAND */
3371         batch_obj = object_list[args->buffer_count-1];
3372         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
3373         batch_obj->pending_write_domain = 0;
3374
3375         /* Sanity check the batch buffer, prior to moving objects */
3376         exec_offset = exec_list[args->buffer_count - 1].offset;
3377         ret = i915_gem_check_execbuffer (args, exec_offset);
3378         if (ret != 0) {
3379                 DRM_ERROR("execbuf with invalid offset/length\n");
3380                 goto err;
3381         }
3382
3383         i915_verify_inactive(dev, __FILE__, __LINE__);
3384
3385         /* Zero the global flush/invalidate flags. These
3386          * will be modified as new domains are computed
3387          * for each object
3388          */
3389         dev->invalidate_domains = 0;
3390         dev->flush_domains = 0;
3391
3392         for (i = 0; i < args->buffer_count; i++) {
3393                 struct drm_gem_object *obj = object_list[i];
3394
3395                 /* Compute new gpu domains and update invalidate/flush */
3396                 i915_gem_object_set_to_gpu_domain(obj);
3397         }
3398
3399         i915_verify_inactive(dev, __FILE__, __LINE__);
3400
3401         if (dev->invalidate_domains | dev->flush_domains) {
3402 #if WATCH_EXEC
3403                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3404                           __func__,
3405                          dev->invalidate_domains,
3406                          dev->flush_domains);
3407 #endif
3408                 i915_gem_flush(dev,
3409                                dev->invalidate_domains,
3410                                dev->flush_domains);
3411                 if (dev->flush_domains)
3412                         (void)i915_add_request(dev, file_priv,
3413                                                dev->flush_domains);
3414         }
3415
3416         for (i = 0; i < args->buffer_count; i++) {
3417                 struct drm_gem_object *obj = object_list[i];
3418
3419                 obj->write_domain = obj->pending_write_domain;
3420         }
3421
3422         i915_verify_inactive(dev, __FILE__, __LINE__);
3423
3424 #if WATCH_COHERENCY
3425         for (i = 0; i < args->buffer_count; i++) {
3426                 i915_gem_object_check_coherency(object_list[i],
3427                                                 exec_list[i].handle);
3428         }
3429 #endif
3430
3431 #if WATCH_EXEC
3432         i915_gem_dump_object(batch_obj,
3433                               args->batch_len,
3434                               __func__,
3435                               ~0);
3436 #endif
3437
3438         /* Exec the batchbuffer */
3439         ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3440         if (ret) {
3441                 DRM_ERROR("dispatch failed %d\n", ret);
3442                 goto err;
3443         }
3444
3445         /*
3446          * Ensure that the commands in the batch buffer are
3447          * finished before the interrupt fires
3448          */
3449         flush_domains = i915_retire_commands(dev);
3450
3451         i915_verify_inactive(dev, __FILE__, __LINE__);
3452
3453         /*
3454          * Get a seqno representing the execution of the current buffer,
3455          * which we can wait on.  We would like to mitigate these interrupts,
3456          * likely by only creating seqnos occasionally (so that we have
3457          * *some* interrupts representing completion of buffers that we can
3458          * wait on when trying to clear up gtt space).
3459          */
3460         seqno = i915_add_request(dev, file_priv, flush_domains);
3461         BUG_ON(seqno == 0);
3462         for (i = 0; i < args->buffer_count; i++) {
3463                 struct drm_gem_object *obj = object_list[i];
3464
3465                 i915_gem_object_move_to_active(obj, seqno);
3466 #if WATCH_LRU
3467                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3468 #endif
3469         }
3470 #if WATCH_LRU
3471         i915_dump_lru(dev, __func__);
3472 #endif
3473
3474         i915_verify_inactive(dev, __FILE__, __LINE__);
3475
3476 err:
3477         for (i = 0; i < pinned; i++)
3478                 i915_gem_object_unpin(object_list[i]);
3479
3480         for (i = 0; i < args->buffer_count; i++) {
3481                 if (object_list[i]) {
3482                         obj_priv = object_list[i]->driver_private;
3483                         obj_priv->in_execbuffer = false;
3484                 }
3485                 drm_gem_object_unreference(object_list[i]);
3486         }
3487
3488         mutex_unlock(&dev->struct_mutex);
3489
3490         if (!ret) {
3491                 /* Copy the new buffer offsets back to the user's exec list. */
3492                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3493                                    (uintptr_t) args->buffers_ptr,
3494                                    exec_list,
3495                                    sizeof(*exec_list) * args->buffer_count);
3496                 if (ret) {
3497                         ret = -EFAULT;
3498                         DRM_ERROR("failed to copy %d exec entries "
3499                                   "back to user (%d)\n",
3500                                   args->buffer_count, ret);
3501                 }
3502         }
3503
3504         /* Copy the updated relocations out regardless of current error
3505          * state.  Failure to update the relocs would mean that the next
3506          * time userland calls execbuf, it would do so with presumed offset
3507          * state that didn't match the actual object state.
3508          */
3509         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3510                                            relocs);
3511         if (ret2 != 0) {
3512                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3513
3514                 if (ret == 0)
3515                         ret = ret2;
3516         }
3517
3518 pre_mutex_err:
3519         drm_free_large(object_list);
3520         drm_free_large(exec_list);
3521         drm_free(cliprects, sizeof(*cliprects) * args->num_cliprects,
3522                  DRM_MEM_DRIVER);
3523
3524         return ret;
3525 }
3526
3527 int
3528 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3529 {
3530         struct drm_device *dev = obj->dev;
3531         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3532         int ret;
3533
3534         i915_verify_inactive(dev, __FILE__, __LINE__);
3535         if (obj_priv->gtt_space == NULL) {
3536                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3537                 if (ret != 0) {
3538                         if (ret != -EBUSY && ret != -ERESTARTSYS)
3539                                 DRM_ERROR("Failure to bind: %d\n", ret);
3540                         return ret;
3541                 }
3542         }
3543         /*
3544          * Pre-965 chips need a fence register set up in order to
3545          * properly handle tiled surfaces.
3546          */
3547         if (!IS_I965G(dev) &&
3548             obj_priv->fence_reg == I915_FENCE_REG_NONE &&
3549             obj_priv->tiling_mode != I915_TILING_NONE) {
3550                 ret = i915_gem_object_get_fence_reg(obj, true);
3551                 if (ret != 0) {
3552                         if (ret != -EBUSY && ret != -ERESTARTSYS)
3553                                 DRM_ERROR("Failure to install fence: %d\n",
3554                                           ret);
3555                         return ret;
3556                 }
3557         }
3558         obj_priv->pin_count++;
3559
3560         /* If the object is not active and not pending a flush,
3561          * remove it from the inactive list
3562          */
3563         if (obj_priv->pin_count == 1) {
3564                 atomic_inc(&dev->pin_count);
3565                 atomic_add(obj->size, &dev->pin_memory);
3566                 if (!obj_priv->active &&
3567                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
3568                                            I915_GEM_DOMAIN_GTT)) == 0 &&
3569                     !list_empty(&obj_priv->list))
3570                         list_del_init(&obj_priv->list);
3571         }
3572         i915_verify_inactive(dev, __FILE__, __LINE__);
3573
3574         return 0;
3575 }
3576
3577 void
3578 i915_gem_object_unpin(struct drm_gem_object *obj)
3579 {
3580         struct drm_device *dev = obj->dev;
3581         drm_i915_private_t *dev_priv = dev->dev_private;
3582         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3583
3584         i915_verify_inactive(dev, __FILE__, __LINE__);
3585         obj_priv->pin_count--;
3586         BUG_ON(obj_priv->pin_count < 0);
3587         BUG_ON(obj_priv->gtt_space == NULL);
3588
3589         /* If the object is no longer pinned, and is
3590          * neither active nor being flushed, then stick it on
3591          * the inactive list
3592          */
3593         if (obj_priv->pin_count == 0) {
3594                 if (!obj_priv->active &&
3595                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
3596                                            I915_GEM_DOMAIN_GTT)) == 0)
3597                         list_move_tail(&obj_priv->list,
3598                                        &dev_priv->mm.inactive_list);
3599                 atomic_dec(&dev->pin_count);
3600                 atomic_sub(obj->size, &dev->pin_memory);
3601         }
3602         i915_verify_inactive(dev, __FILE__, __LINE__);
3603 }
3604
3605 int
3606 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3607                    struct drm_file *file_priv)
3608 {
3609         struct drm_i915_gem_pin *args = data;
3610         struct drm_gem_object *obj;
3611         struct drm_i915_gem_object *obj_priv;
3612         int ret;
3613
3614         mutex_lock(&dev->struct_mutex);
3615
3616         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3617         if (obj == NULL) {
3618                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3619                           args->handle);
3620                 mutex_unlock(&dev->struct_mutex);
3621                 return -EBADF;
3622         }
3623         obj_priv = obj->driver_private;
3624
3625         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3626                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3627                           args->handle);
3628                 drm_gem_object_unreference(obj);
3629                 mutex_unlock(&dev->struct_mutex);
3630                 return -EINVAL;
3631         }
3632
3633         obj_priv->user_pin_count++;
3634         obj_priv->pin_filp = file_priv;
3635         if (obj_priv->user_pin_count == 1) {
3636                 ret = i915_gem_object_pin(obj, args->alignment);
3637                 if (ret != 0) {
3638                         drm_gem_object_unreference(obj);
3639                         mutex_unlock(&dev->struct_mutex);
3640                         return ret;
3641                 }
3642         }
3643
3644         /* XXX - flush the CPU caches for pinned objects
3645          * as the X server doesn't manage domains yet
3646          */
3647         i915_gem_object_flush_cpu_write_domain(obj);
3648         args->offset = obj_priv->gtt_offset;
3649         drm_gem_object_unreference(obj);
3650         mutex_unlock(&dev->struct_mutex);
3651
3652         return 0;
3653 }
3654
3655 int
3656 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3657                      struct drm_file *file_priv)
3658 {
3659         struct drm_i915_gem_pin *args = data;
3660         struct drm_gem_object *obj;
3661         struct drm_i915_gem_object *obj_priv;
3662
3663         mutex_lock(&dev->struct_mutex);
3664
3665         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3666         if (obj == NULL) {
3667                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3668                           args->handle);
3669                 mutex_unlock(&dev->struct_mutex);
3670                 return -EBADF;
3671         }
3672
3673         obj_priv = obj->driver_private;
3674         if (obj_priv->pin_filp != file_priv) {
3675                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3676                           args->handle);
3677                 drm_gem_object_unreference(obj);
3678                 mutex_unlock(&dev->struct_mutex);
3679                 return -EINVAL;
3680         }
3681         obj_priv->user_pin_count--;
3682         if (obj_priv->user_pin_count == 0) {
3683                 obj_priv->pin_filp = NULL;
3684                 i915_gem_object_unpin(obj);
3685         }
3686
3687         drm_gem_object_unreference(obj);
3688         mutex_unlock(&dev->struct_mutex);
3689         return 0;
3690 }
3691
3692 int
3693 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3694                     struct drm_file *file_priv)
3695 {
3696         struct drm_i915_gem_busy *args = data;
3697         struct drm_gem_object *obj;
3698         struct drm_i915_gem_object *obj_priv;
3699
3700         mutex_lock(&dev->struct_mutex);
3701         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3702         if (obj == NULL) {
3703                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3704                           args->handle);
3705                 mutex_unlock(&dev->struct_mutex);
3706                 return -EBADF;
3707         }
3708
3709         /* Update the active list for the hardware's current position.
3710          * Otherwise this only updates on a delayed timer or when irqs are
3711          * actually unmasked, and our working set ends up being larger than
3712          * required.
3713          */
3714         i915_gem_retire_requests(dev);
3715
3716         obj_priv = obj->driver_private;
3717         /* Don't count being on the flushing list against the object being
3718          * done.  Otherwise, a buffer left on the flushing list but not getting
3719          * flushed (because nobody's flushing that domain) won't ever return
3720          * unbusy and get reused by libdrm's bo cache.  The other expected
3721          * consumer of this interface, OpenGL's occlusion queries, also specs
3722          * that the objects get unbusy "eventually" without any interference.
3723          */
3724         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
3725
3726         drm_gem_object_unreference(obj);
3727         mutex_unlock(&dev->struct_mutex);
3728         return 0;
3729 }
3730
3731 int
3732 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3733                         struct drm_file *file_priv)
3734 {
3735     return i915_gem_ring_throttle(dev, file_priv);
3736 }
3737
3738 int i915_gem_init_object(struct drm_gem_object *obj)
3739 {
3740         struct drm_i915_gem_object *obj_priv;
3741
3742         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
3743         if (obj_priv == NULL)
3744                 return -ENOMEM;
3745
3746         /*
3747          * We've just allocated pages from the kernel,
3748          * so they've just been written by the CPU with
3749          * zeros. They'll need to be clflushed before we
3750          * use them with the GPU.
3751          */
3752         obj->write_domain = I915_GEM_DOMAIN_CPU;
3753         obj->read_domains = I915_GEM_DOMAIN_CPU;
3754
3755         obj_priv->agp_type = AGP_USER_MEMORY;
3756
3757         obj->driver_private = obj_priv;
3758         obj_priv->obj = obj;
3759         obj_priv->fence_reg = I915_FENCE_REG_NONE;
3760         INIT_LIST_HEAD(&obj_priv->list);
3761
3762         return 0;
3763 }
3764
3765 void i915_gem_free_object(struct drm_gem_object *obj)
3766 {
3767         struct drm_device *dev = obj->dev;
3768         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3769
3770         while (obj_priv->pin_count > 0)
3771                 i915_gem_object_unpin(obj);
3772
3773         if (obj_priv->phys_obj)
3774                 i915_gem_detach_phys_object(dev, obj);
3775
3776         i915_gem_object_unbind(obj);
3777
3778         i915_gem_free_mmap_offset(obj);
3779
3780         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
3781         kfree(obj_priv->bit_17);
3782         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
3783 }
3784
3785 /** Unbinds all objects that are on the given buffer list. */
3786 static int
3787 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3788 {
3789         struct drm_gem_object *obj;
3790         struct drm_i915_gem_object *obj_priv;
3791         int ret;
3792
3793         while (!list_empty(head)) {
3794                 obj_priv = list_first_entry(head,
3795                                             struct drm_i915_gem_object,
3796                                             list);
3797                 obj = obj_priv->obj;
3798
3799                 if (obj_priv->pin_count != 0) {
3800                         DRM_ERROR("Pinned object in unbind list\n");
3801                         mutex_unlock(&dev->struct_mutex);
3802                         return -EINVAL;
3803                 }
3804
3805                 ret = i915_gem_object_unbind(obj);
3806                 if (ret != 0) {
3807                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3808                                   ret);
3809                         mutex_unlock(&dev->struct_mutex);
3810                         return ret;
3811                 }
3812         }
3813
3814
3815         return 0;
3816 }
3817
3818 int
3819 i915_gem_idle(struct drm_device *dev)
3820 {
3821         drm_i915_private_t *dev_priv = dev->dev_private;
3822         uint32_t seqno, cur_seqno, last_seqno;
3823         int stuck, ret;
3824
3825         mutex_lock(&dev->struct_mutex);
3826
3827         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3828                 mutex_unlock(&dev->struct_mutex);
3829                 return 0;
3830         }
3831
3832         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
3833          * We need to replace this with a semaphore, or something.
3834          */
3835         dev_priv->mm.suspended = 1;
3836
3837         /* Cancel the retire work handler, wait for it to finish if running
3838          */
3839         mutex_unlock(&dev->struct_mutex);
3840         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3841         mutex_lock(&dev->struct_mutex);
3842
3843         i915_kernel_lost_context(dev);
3844
3845         /* Flush the GPU along with all non-CPU write domains
3846          */
3847         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
3848                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
3849         seqno = i915_add_request(dev, NULL, ~I915_GEM_DOMAIN_CPU);
3850
3851         if (seqno == 0) {
3852                 mutex_unlock(&dev->struct_mutex);
3853                 return -ENOMEM;
3854         }
3855
3856         dev_priv->mm.waiting_gem_seqno = seqno;
3857         last_seqno = 0;
3858         stuck = 0;
3859         for (;;) {
3860                 cur_seqno = i915_get_gem_seqno(dev);
3861                 if (i915_seqno_passed(cur_seqno, seqno))
3862                         break;
3863                 if (last_seqno == cur_seqno) {
3864                         if (stuck++ > 100) {
3865                                 DRM_ERROR("hardware wedged\n");
3866                                 dev_priv->mm.wedged = 1;
3867                                 DRM_WAKEUP(&dev_priv->irq_queue);
3868                                 break;
3869                         }
3870                 }
3871                 msleep(10);
3872                 last_seqno = cur_seqno;
3873         }
3874         dev_priv->mm.waiting_gem_seqno = 0;
3875
3876         i915_gem_retire_requests(dev);
3877
3878         spin_lock(&dev_priv->mm.active_list_lock);
3879         if (!dev_priv->mm.wedged) {
3880                 /* Active and flushing should now be empty as we've
3881                  * waited for a sequence higher than any pending execbuffer
3882                  */
3883                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3884                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3885                 /* Request should now be empty as we've also waited
3886                  * for the last request in the list
3887                  */
3888                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3889         }
3890
3891         /* Empty the active and flushing lists to inactive.  If there's
3892          * anything left at this point, it means that we're wedged and
3893          * nothing good's going to happen by leaving them there.  So strip
3894          * the GPU domains and just stuff them onto inactive.
3895          */
3896         while (!list_empty(&dev_priv->mm.active_list)) {
3897                 struct drm_i915_gem_object *obj_priv;
3898
3899                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3900                                             struct drm_i915_gem_object,
3901                                             list);
3902                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3903                 i915_gem_object_move_to_inactive(obj_priv->obj);
3904         }
3905         spin_unlock(&dev_priv->mm.active_list_lock);
3906
3907         while (!list_empty(&dev_priv->mm.flushing_list)) {
3908                 struct drm_i915_gem_object *obj_priv;
3909
3910                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
3911                                             struct drm_i915_gem_object,
3912                                             list);
3913                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3914                 i915_gem_object_move_to_inactive(obj_priv->obj);
3915         }
3916
3917
3918         /* Move all inactive buffers out of the GTT. */
3919         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
3920         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
3921         if (ret) {
3922                 mutex_unlock(&dev->struct_mutex);
3923                 return ret;
3924         }
3925
3926         i915_gem_cleanup_ringbuffer(dev);
3927         mutex_unlock(&dev->struct_mutex);
3928
3929         return 0;
3930 }
3931
3932 static int
3933 i915_gem_init_hws(struct drm_device *dev)
3934 {
3935         drm_i915_private_t *dev_priv = dev->dev_private;
3936         struct drm_gem_object *obj;
3937         struct drm_i915_gem_object *obj_priv;
3938         int ret;
3939
3940         /* If we need a physical address for the status page, it's already
3941          * initialized at driver load time.
3942          */
3943         if (!I915_NEED_GFX_HWS(dev))
3944                 return 0;
3945
3946         obj = drm_gem_object_alloc(dev, 4096);
3947         if (obj == NULL) {
3948                 DRM_ERROR("Failed to allocate status page\n");
3949                 return -ENOMEM;
3950         }
3951         obj_priv = obj->driver_private;
3952         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
3953
3954         ret = i915_gem_object_pin(obj, 4096);
3955         if (ret != 0) {
3956                 drm_gem_object_unreference(obj);
3957                 return ret;
3958         }
3959
3960         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
3961
3962         dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
3963         if (dev_priv->hw_status_page == NULL) {
3964                 DRM_ERROR("Failed to map status page.\n");
3965                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3966                 i915_gem_object_unpin(obj);
3967                 drm_gem_object_unreference(obj);
3968                 return -EINVAL;
3969         }
3970         dev_priv->hws_obj = obj;
3971         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3972         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
3973         I915_READ(HWS_PGA); /* posting read */
3974         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3975
3976         return 0;
3977 }
3978
3979 static void
3980 i915_gem_cleanup_hws(struct drm_device *dev)
3981 {
3982         drm_i915_private_t *dev_priv = dev->dev_private;
3983         struct drm_gem_object *obj;
3984         struct drm_i915_gem_object *obj_priv;
3985
3986         if (dev_priv->hws_obj == NULL)
3987                 return;
3988
3989         obj = dev_priv->hws_obj;
3990         obj_priv = obj->driver_private;
3991
3992         kunmap(obj_priv->pages[0]);
3993         i915_gem_object_unpin(obj);
3994         drm_gem_object_unreference(obj);
3995         dev_priv->hws_obj = NULL;
3996
3997         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3998         dev_priv->hw_status_page = NULL;
3999
4000         /* Write high address into HWS_PGA when disabling. */
4001         I915_WRITE(HWS_PGA, 0x1ffff000);
4002 }
4003
4004 int
4005 i915_gem_init_ringbuffer(struct drm_device *dev)
4006 {
4007         drm_i915_private_t *dev_priv = dev->dev_private;
4008         struct drm_gem_object *obj;
4009         struct drm_i915_gem_object *obj_priv;
4010         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4011         int ret;
4012         u32 head;
4013
4014         ret = i915_gem_init_hws(dev);
4015         if (ret != 0)
4016                 return ret;
4017
4018         obj = drm_gem_object_alloc(dev, 128 * 1024);
4019         if (obj == NULL) {
4020                 DRM_ERROR("Failed to allocate ringbuffer\n");
4021                 i915_gem_cleanup_hws(dev);
4022                 return -ENOMEM;
4023         }
4024         obj_priv = obj->driver_private;
4025
4026         ret = i915_gem_object_pin(obj, 4096);
4027         if (ret != 0) {
4028                 drm_gem_object_unreference(obj);
4029                 i915_gem_cleanup_hws(dev);
4030                 return ret;
4031         }
4032
4033         /* Set up the kernel mapping for the ring. */
4034         ring->Size = obj->size;
4035         ring->tail_mask = obj->size - 1;
4036
4037         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4038         ring->map.size = obj->size;
4039         ring->map.type = 0;
4040         ring->map.flags = 0;
4041         ring->map.mtrr = 0;
4042
4043         drm_core_ioremap_wc(&ring->map, dev);
4044         if (ring->map.handle == NULL) {
4045                 DRM_ERROR("Failed to map ringbuffer.\n");
4046                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4047                 i915_gem_object_unpin(obj);
4048                 drm_gem_object_unreference(obj);
4049                 i915_gem_cleanup_hws(dev);
4050                 return -EINVAL;
4051         }
4052         ring->ring_obj = obj;
4053         ring->virtual_start = ring->map.handle;
4054
4055         /* Stop the ring if it's running. */
4056         I915_WRITE(PRB0_CTL, 0);
4057         I915_WRITE(PRB0_TAIL, 0);
4058         I915_WRITE(PRB0_HEAD, 0);
4059
4060         /* Initialize the ring. */
4061         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4062         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4063
4064         /* G45 ring initialization fails to reset head to zero */
4065         if (head != 0) {
4066                 DRM_ERROR("Ring head not reset to zero "
4067                           "ctl %08x head %08x tail %08x start %08x\n",
4068                           I915_READ(PRB0_CTL),
4069                           I915_READ(PRB0_HEAD),
4070                           I915_READ(PRB0_TAIL),
4071                           I915_READ(PRB0_START));
4072                 I915_WRITE(PRB0_HEAD, 0);
4073
4074                 DRM_ERROR("Ring head forced to zero "
4075                           "ctl %08x head %08x tail %08x start %08x\n",
4076                           I915_READ(PRB0_CTL),
4077                           I915_READ(PRB0_HEAD),
4078                           I915_READ(PRB0_TAIL),
4079                           I915_READ(PRB0_START));
4080         }
4081
4082         I915_WRITE(PRB0_CTL,
4083                    ((obj->size - 4096) & RING_NR_PAGES) |
4084                    RING_NO_REPORT |
4085                    RING_VALID);
4086
4087         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4088
4089         /* If the head is still not zero, the ring is dead */
4090         if (head != 0) {
4091                 DRM_ERROR("Ring initialization failed "
4092                           "ctl %08x head %08x tail %08x start %08x\n",
4093                           I915_READ(PRB0_CTL),
4094                           I915_READ(PRB0_HEAD),
4095                           I915_READ(PRB0_TAIL),
4096                           I915_READ(PRB0_START));
4097                 return -EIO;
4098         }
4099
4100         /* Update our cache of the ring state */
4101         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4102                 i915_kernel_lost_context(dev);
4103         else {
4104                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4105                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4106                 ring->space = ring->head - (ring->tail + 8);
4107                 if (ring->space < 0)
4108                         ring->space += ring->Size;
4109         }
4110
4111         return 0;
4112 }
4113
4114 void
4115 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4116 {
4117         drm_i915_private_t *dev_priv = dev->dev_private;
4118
4119         if (dev_priv->ring.ring_obj == NULL)
4120                 return;
4121
4122         drm_core_ioremapfree(&dev_priv->ring.map, dev);
4123
4124         i915_gem_object_unpin(dev_priv->ring.ring_obj);
4125         drm_gem_object_unreference(dev_priv->ring.ring_obj);
4126         dev_priv->ring.ring_obj = NULL;
4127         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4128
4129         i915_gem_cleanup_hws(dev);
4130 }
4131
4132 int
4133 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4134                        struct drm_file *file_priv)
4135 {
4136         drm_i915_private_t *dev_priv = dev->dev_private;
4137         int ret;
4138
4139         if (drm_core_check_feature(dev, DRIVER_MODESET))
4140                 return 0;
4141
4142         if (dev_priv->mm.wedged) {
4143                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4144                 dev_priv->mm.wedged = 0;
4145         }
4146
4147         mutex_lock(&dev->struct_mutex);
4148         dev_priv->mm.suspended = 0;
4149
4150         ret = i915_gem_init_ringbuffer(dev);
4151         if (ret != 0) {
4152                 mutex_unlock(&dev->struct_mutex);
4153                 return ret;
4154         }
4155
4156         spin_lock(&dev_priv->mm.active_list_lock);
4157         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4158         spin_unlock(&dev_priv->mm.active_list_lock);
4159
4160         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4161         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4162         BUG_ON(!list_empty(&dev_priv->mm.request_list));
4163         mutex_unlock(&dev->struct_mutex);
4164
4165         drm_irq_install(dev);
4166
4167         return 0;
4168 }
4169
4170 int
4171 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4172                        struct drm_file *file_priv)
4173 {
4174         int ret;
4175
4176         if (drm_core_check_feature(dev, DRIVER_MODESET))
4177                 return 0;
4178
4179         ret = i915_gem_idle(dev);
4180         drm_irq_uninstall(dev);
4181
4182         return ret;
4183 }
4184
4185 void
4186 i915_gem_lastclose(struct drm_device *dev)
4187 {
4188         int ret;
4189
4190         if (drm_core_check_feature(dev, DRIVER_MODESET))
4191                 return;
4192
4193         ret = i915_gem_idle(dev);
4194         if (ret)
4195                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4196 }
4197
4198 void
4199 i915_gem_load(struct drm_device *dev)
4200 {
4201         drm_i915_private_t *dev_priv = dev->dev_private;
4202
4203         spin_lock_init(&dev_priv->mm.active_list_lock);
4204         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4205         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4206         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4207         INIT_LIST_HEAD(&dev_priv->mm.request_list);
4208         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4209                           i915_gem_retire_work_handler);
4210         dev_priv->mm.next_gem_seqno = 1;
4211
4212         /* Old X drivers will take 0-2 for front, back, depth buffers */
4213         dev_priv->fence_reg_start = 3;
4214
4215         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4216                 dev_priv->num_fence_regs = 16;
4217         else
4218                 dev_priv->num_fence_regs = 8;
4219
4220         i915_gem_detect_bit_6_swizzle(dev);
4221 }
4222
4223 /*
4224  * Create a physically contiguous memory object for this object
4225  * e.g. for cursor + overlay regs
4226  */
4227 int i915_gem_init_phys_object(struct drm_device *dev,
4228                               int id, int size)
4229 {
4230         drm_i915_private_t *dev_priv = dev->dev_private;
4231         struct drm_i915_gem_phys_object *phys_obj;
4232         int ret;
4233
4234         if (dev_priv->mm.phys_objs[id - 1] || !size)
4235                 return 0;
4236
4237         phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4238         if (!phys_obj)
4239                 return -ENOMEM;
4240
4241         phys_obj->id = id;
4242
4243         phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4244         if (!phys_obj->handle) {
4245                 ret = -ENOMEM;
4246                 goto kfree_obj;
4247         }
4248 #ifdef CONFIG_X86
4249         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4250 #endif
4251
4252         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4253
4254         return 0;
4255 kfree_obj:
4256         drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4257         return ret;
4258 }
4259
4260 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4261 {
4262         drm_i915_private_t *dev_priv = dev->dev_private;
4263         struct drm_i915_gem_phys_object *phys_obj;
4264
4265         if (!dev_priv->mm.phys_objs[id - 1])
4266                 return;
4267
4268         phys_obj = dev_priv->mm.phys_objs[id - 1];
4269         if (phys_obj->cur_obj) {
4270                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4271         }
4272
4273 #ifdef CONFIG_X86
4274         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4275 #endif
4276         drm_pci_free(dev, phys_obj->handle);
4277         kfree(phys_obj);
4278         dev_priv->mm.phys_objs[id - 1] = NULL;
4279 }
4280
4281 void i915_gem_free_all_phys_object(struct drm_device *dev)
4282 {
4283         int i;
4284
4285         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4286                 i915_gem_free_phys_object(dev, i);
4287 }
4288
4289 void i915_gem_detach_phys_object(struct drm_device *dev,
4290                                  struct drm_gem_object *obj)
4291 {
4292         struct drm_i915_gem_object *obj_priv;
4293         int i;
4294         int ret;
4295         int page_count;
4296
4297         obj_priv = obj->driver_private;
4298         if (!obj_priv->phys_obj)
4299                 return;
4300
4301         ret = i915_gem_object_get_pages(obj);
4302         if (ret)
4303                 goto out;
4304
4305         page_count = obj->size / PAGE_SIZE;
4306
4307         for (i = 0; i < page_count; i++) {
4308                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4309                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4310
4311                 memcpy(dst, src, PAGE_SIZE);
4312                 kunmap_atomic(dst, KM_USER0);
4313         }
4314         drm_clflush_pages(obj_priv->pages, page_count);
4315         drm_agp_chipset_flush(dev);
4316 out:
4317         obj_priv->phys_obj->cur_obj = NULL;
4318         obj_priv->phys_obj = NULL;
4319 }
4320
4321 int
4322 i915_gem_attach_phys_object(struct drm_device *dev,
4323                             struct drm_gem_object *obj, int id)
4324 {
4325         drm_i915_private_t *dev_priv = dev->dev_private;
4326         struct drm_i915_gem_object *obj_priv;
4327         int ret = 0;
4328         int page_count;
4329         int i;
4330
4331         if (id > I915_MAX_PHYS_OBJECT)
4332                 return -EINVAL;
4333
4334         obj_priv = obj->driver_private;
4335
4336         if (obj_priv->phys_obj) {
4337                 if (obj_priv->phys_obj->id == id)
4338                         return 0;
4339                 i915_gem_detach_phys_object(dev, obj);
4340         }
4341
4342
4343         /* create a new object */
4344         if (!dev_priv->mm.phys_objs[id - 1]) {
4345                 ret = i915_gem_init_phys_object(dev, id,
4346                                                 obj->size);
4347                 if (ret) {
4348                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4349                         goto out;
4350                 }
4351         }
4352
4353         /* bind to the object */
4354         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4355         obj_priv->phys_obj->cur_obj = obj;
4356
4357         ret = i915_gem_object_get_pages(obj);
4358         if (ret) {
4359                 DRM_ERROR("failed to get page list\n");
4360                 goto out;
4361         }
4362
4363         page_count = obj->size / PAGE_SIZE;
4364
4365         for (i = 0; i < page_count; i++) {
4366                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4367                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4368
4369                 memcpy(dst, src, PAGE_SIZE);
4370                 kunmap_atomic(src, KM_USER0);
4371         }
4372
4373         return 0;
4374 out:
4375         return ret;
4376 }
4377
4378 static int
4379 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4380                      struct drm_i915_gem_pwrite *args,
4381                      struct drm_file *file_priv)
4382 {
4383         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4384         void *obj_addr;
4385         int ret;
4386         char __user *user_data;
4387
4388         user_data = (char __user *) (uintptr_t) args->data_ptr;
4389         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4390
4391         DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4392         ret = copy_from_user(obj_addr, user_data, args->size);
4393         if (ret)
4394                 return -EFAULT;
4395
4396         drm_agp_chipset_flush(dev);
4397         return 0;
4398 }
4399
4400 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4401 {
4402         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4403
4404         /* Clean up our request list when the client is going away, so that
4405          * later retire_requests won't dereference our soon-to-be-gone
4406          * file_priv.
4407          */
4408         mutex_lock(&dev->struct_mutex);
4409         while (!list_empty(&i915_file_priv->mm.request_list))
4410                 list_del_init(i915_file_priv->mm.request_list.next);
4411         mutex_unlock(&dev->struct_mutex);
4412 }