2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
52 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
57 static LIST_HEAD(shrink_list);
58 static DEFINE_SPINLOCK(shrink_list_lock);
60 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63 drm_i915_private_t *dev_priv = dev->dev_private;
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
71 drm_mm_init(&dev_priv->mm.gtt_space, start,
74 dev->gtt_total = (uint32_t) (end - start);
80 i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
83 struct drm_i915_gem_init *args = data;
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
88 mutex_unlock(&dev->struct_mutex);
94 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
97 struct drm_i915_gem_get_aperture *args = data;
99 if (!(dev->driver->driver_features & DRIVER_GEM))
102 args->aper_size = dev->gtt_total;
103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
111 * Creates a new mm object and returns a handle to it.
114 i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
122 args->size = roundup(args->size, PAGE_SIZE);
124 /* Allocate the new object */
125 obj = i915_gem_alloc_object(dev, args->size);
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
130 drm_gem_object_handle_unreference_unlocked(obj);
135 args->handle = handle;
141 fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
153 kunmap_atomic(vaddr, KM_USER0);
161 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
171 slow_shmem_copy(struct page *dst_page,
173 struct page *src_page,
177 char *dst_vaddr, *src_vaddr;
179 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
180 if (dst_vaddr == NULL)
183 src_vaddr = kmap_atomic(src_page, KM_USER1);
184 if (src_vaddr == NULL) {
185 kunmap_atomic(dst_vaddr, KM_USER0);
189 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
191 kunmap_atomic(src_vaddr, KM_USER1);
192 kunmap_atomic(dst_vaddr, KM_USER0);
198 slow_shmem_bit17_copy(struct page *gpu_page,
200 struct page *cpu_page,
205 char *gpu_vaddr, *cpu_vaddr;
207 /* Use the unswizzled path if this page isn't affected. */
208 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
210 return slow_shmem_copy(cpu_page, cpu_offset,
211 gpu_page, gpu_offset, length);
213 return slow_shmem_copy(gpu_page, gpu_offset,
214 cpu_page, cpu_offset, length);
217 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
218 if (gpu_vaddr == NULL)
221 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
222 if (cpu_vaddr == NULL) {
223 kunmap_atomic(gpu_vaddr, KM_USER0);
227 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
228 * XORing with the other bits (A9 for Y, A9 and A10 for X)
231 int cacheline_end = ALIGN(gpu_offset + 1, 64);
232 int this_length = min(cacheline_end - gpu_offset, length);
233 int swizzled_gpu_offset = gpu_offset ^ 64;
236 memcpy(cpu_vaddr + cpu_offset,
237 gpu_vaddr + swizzled_gpu_offset,
240 memcpy(gpu_vaddr + swizzled_gpu_offset,
241 cpu_vaddr + cpu_offset,
244 cpu_offset += this_length;
245 gpu_offset += this_length;
246 length -= this_length;
249 kunmap_atomic(cpu_vaddr, KM_USER1);
250 kunmap_atomic(gpu_vaddr, KM_USER0);
256 * This is the fast shmem pread path, which attempts to copy_from_user directly
257 * from the backing pages of the object to the user's address space. On a
258 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
261 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
262 struct drm_i915_gem_pread *args,
263 struct drm_file *file_priv)
265 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
267 loff_t offset, page_base;
268 char __user *user_data;
269 int page_offset, page_length;
272 user_data = (char __user *) (uintptr_t) args->data_ptr;
275 mutex_lock(&dev->struct_mutex);
277 ret = i915_gem_object_get_pages(obj, 0);
281 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
286 obj_priv = to_intel_bo(obj);
287 offset = args->offset;
290 /* Operation in this page
292 * page_base = page offset within aperture
293 * page_offset = offset within page
294 * page_length = bytes to copy for this page
296 page_base = (offset & ~(PAGE_SIZE-1));
297 page_offset = offset & (PAGE_SIZE-1);
298 page_length = remain;
299 if ((page_offset + remain) > PAGE_SIZE)
300 page_length = PAGE_SIZE - page_offset;
302 ret = fast_shmem_read(obj_priv->pages,
303 page_base, page_offset,
304 user_data, page_length);
308 remain -= page_length;
309 user_data += page_length;
310 offset += page_length;
314 i915_gem_object_put_pages(obj);
316 mutex_unlock(&dev->struct_mutex);
322 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
326 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
328 /* If we've insufficient memory to map in the pages, attempt
329 * to make some space by throwing out some old buffers.
331 if (ret == -ENOMEM) {
332 struct drm_device *dev = obj->dev;
334 ret = i915_gem_evict_something(dev, obj->size);
338 ret = i915_gem_object_get_pages(obj, 0);
345 * This is the fallback shmem pread path, which allocates temporary storage
346 * in kernel space to copy_to_user into outside of the struct_mutex, so we
347 * can copy out of the object's backing pages while holding the struct mutex
348 * and not take page faults.
351 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
352 struct drm_i915_gem_pread *args,
353 struct drm_file *file_priv)
355 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
356 struct mm_struct *mm = current->mm;
357 struct page **user_pages;
359 loff_t offset, pinned_pages, i;
360 loff_t first_data_page, last_data_page, num_pages;
361 int shmem_page_index, shmem_page_offset;
362 int data_page_index, data_page_offset;
365 uint64_t data_ptr = args->data_ptr;
366 int do_bit17_swizzling;
370 /* Pin the user pages containing the data. We can't fault while
371 * holding the struct mutex, yet we want to hold it while
372 * dereferencing the user data.
374 first_data_page = data_ptr / PAGE_SIZE;
375 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
376 num_pages = last_data_page - first_data_page + 1;
378 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
379 if (user_pages == NULL)
382 down_read(&mm->mmap_sem);
383 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
384 num_pages, 1, 0, user_pages, NULL);
385 up_read(&mm->mmap_sem);
386 if (pinned_pages < num_pages) {
388 goto fail_put_user_pages;
391 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
393 mutex_lock(&dev->struct_mutex);
395 ret = i915_gem_object_get_pages_or_evict(obj);
399 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
404 obj_priv = to_intel_bo(obj);
405 offset = args->offset;
408 /* Operation in this page
410 * shmem_page_index = page number within shmem file
411 * shmem_page_offset = offset within page in shmem file
412 * data_page_index = page number in get_user_pages return
413 * data_page_offset = offset with data_page_index page.
414 * page_length = bytes to copy for this page
416 shmem_page_index = offset / PAGE_SIZE;
417 shmem_page_offset = offset & ~PAGE_MASK;
418 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
419 data_page_offset = data_ptr & ~PAGE_MASK;
421 page_length = remain;
422 if ((shmem_page_offset + page_length) > PAGE_SIZE)
423 page_length = PAGE_SIZE - shmem_page_offset;
424 if ((data_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - data_page_offset;
427 if (do_bit17_swizzling) {
428 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
430 user_pages[data_page_index],
435 ret = slow_shmem_copy(user_pages[data_page_index],
437 obj_priv->pages[shmem_page_index],
444 remain -= page_length;
445 data_ptr += page_length;
446 offset += page_length;
450 i915_gem_object_put_pages(obj);
452 mutex_unlock(&dev->struct_mutex);
454 for (i = 0; i < pinned_pages; i++) {
455 SetPageDirty(user_pages[i]);
456 page_cache_release(user_pages[i]);
458 drm_free_large(user_pages);
464 * Reads data from the object referenced by handle.
466 * On error, the contents of *data are undefined.
469 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv)
472 struct drm_i915_gem_pread *args = data;
473 struct drm_gem_object *obj;
474 struct drm_i915_gem_object *obj_priv;
477 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480 obj_priv = to_intel_bo(obj);
482 /* Bounds check source.
484 * XXX: This could use review for overflow issues...
486 if (args->offset > obj->size || args->size > obj->size ||
487 args->offset + args->size > obj->size) {
488 drm_gem_object_unreference_unlocked(obj);
492 if (i915_gem_object_needs_bit17_swizzle(obj)) {
493 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
495 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
497 ret = i915_gem_shmem_pread_slow(dev, obj, args,
501 drm_gem_object_unreference_unlocked(obj);
506 /* This is the fast write path which cannot handle
507 * page faults in the source data
511 fast_user_write(struct io_mapping *mapping,
512 loff_t page_base, int page_offset,
513 char __user *user_data,
517 unsigned long unwritten;
519 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
520 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
522 io_mapping_unmap_atomic(vaddr_atomic);
528 /* Here's the write path which can sleep for
533 slow_kernel_write(struct io_mapping *mapping,
534 loff_t gtt_base, int gtt_offset,
535 struct page *user_page, int user_offset,
538 char *src_vaddr, *dst_vaddr;
539 unsigned long unwritten;
541 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
542 src_vaddr = kmap_atomic(user_page, KM_USER1);
543 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
544 src_vaddr + user_offset,
546 kunmap_atomic(src_vaddr, KM_USER1);
547 io_mapping_unmap_atomic(dst_vaddr);
554 fast_shmem_write(struct page **pages,
555 loff_t page_base, int page_offset,
560 unsigned long unwritten;
562 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
565 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
566 kunmap_atomic(vaddr, KM_USER0);
574 * This is the fast pwrite path, where we copy the data directly from the
575 * user into the GTT, uncached.
578 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
579 struct drm_i915_gem_pwrite *args,
580 struct drm_file *file_priv)
582 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
583 drm_i915_private_t *dev_priv = dev->dev_private;
585 loff_t offset, page_base;
586 char __user *user_data;
587 int page_offset, page_length;
590 user_data = (char __user *) (uintptr_t) args->data_ptr;
592 if (!access_ok(VERIFY_READ, user_data, remain))
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_gem_object_pin(obj, 0);
599 mutex_unlock(&dev->struct_mutex);
602 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
606 obj_priv = to_intel_bo(obj);
607 offset = obj_priv->gtt_offset + args->offset;
610 /* Operation in this page
612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
616 page_base = (offset & ~(PAGE_SIZE-1));
617 page_offset = offset & (PAGE_SIZE-1);
618 page_length = remain;
619 if ((page_offset + remain) > PAGE_SIZE)
620 page_length = PAGE_SIZE - page_offset;
622 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
623 page_offset, user_data, page_length);
625 /* If we get a fault while copying data, then (presumably) our
626 * source page isn't available. Return the error and we'll
627 * retry in the slow path.
632 remain -= page_length;
633 user_data += page_length;
634 offset += page_length;
638 i915_gem_object_unpin(obj);
639 mutex_unlock(&dev->struct_mutex);
645 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
646 * the memory and maps it using kmap_atomic for copying.
648 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
649 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
652 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
653 struct drm_i915_gem_pwrite *args,
654 struct drm_file *file_priv)
656 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
657 drm_i915_private_t *dev_priv = dev->dev_private;
659 loff_t gtt_page_base, offset;
660 loff_t first_data_page, last_data_page, num_pages;
661 loff_t pinned_pages, i;
662 struct page **user_pages;
663 struct mm_struct *mm = current->mm;
664 int gtt_page_offset, data_page_offset, data_page_index, page_length;
666 uint64_t data_ptr = args->data_ptr;
670 /* Pin the user pages containing the data. We can't fault while
671 * holding the struct mutex, and all of the pwrite implementations
672 * want to hold it while dereferencing the user data.
674 first_data_page = data_ptr / PAGE_SIZE;
675 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
676 num_pages = last_data_page - first_data_page + 1;
678 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
679 if (user_pages == NULL)
682 down_read(&mm->mmap_sem);
683 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
684 num_pages, 0, 0, user_pages, NULL);
685 up_read(&mm->mmap_sem);
686 if (pinned_pages < num_pages) {
688 goto out_unpin_pages;
691 mutex_lock(&dev->struct_mutex);
692 ret = i915_gem_object_pin(obj, 0);
696 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
698 goto out_unpin_object;
700 obj_priv = to_intel_bo(obj);
701 offset = obj_priv->gtt_offset + args->offset;
704 /* Operation in this page
706 * gtt_page_base = page offset within aperture
707 * gtt_page_offset = offset within page in aperture
708 * data_page_index = page number in get_user_pages return
709 * data_page_offset = offset with data_page_index page.
710 * page_length = bytes to copy for this page
712 gtt_page_base = offset & PAGE_MASK;
713 gtt_page_offset = offset & ~PAGE_MASK;
714 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
715 data_page_offset = data_ptr & ~PAGE_MASK;
717 page_length = remain;
718 if ((gtt_page_offset + page_length) > PAGE_SIZE)
719 page_length = PAGE_SIZE - gtt_page_offset;
720 if ((data_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - data_page_offset;
723 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
724 gtt_page_base, gtt_page_offset,
725 user_pages[data_page_index],
729 /* If we get a fault while copying data, then (presumably) our
730 * source page isn't available. Return the error and we'll
731 * retry in the slow path.
734 goto out_unpin_object;
736 remain -= page_length;
737 offset += page_length;
738 data_ptr += page_length;
742 i915_gem_object_unpin(obj);
744 mutex_unlock(&dev->struct_mutex);
746 for (i = 0; i < pinned_pages; i++)
747 page_cache_release(user_pages[i]);
748 drm_free_large(user_pages);
754 * This is the fast shmem pwrite path, which attempts to directly
755 * copy_from_user into the kmapped pages backing the object.
758 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
759 struct drm_i915_gem_pwrite *args,
760 struct drm_file *file_priv)
762 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
764 loff_t offset, page_base;
765 char __user *user_data;
766 int page_offset, page_length;
769 user_data = (char __user *) (uintptr_t) args->data_ptr;
772 mutex_lock(&dev->struct_mutex);
774 ret = i915_gem_object_get_pages(obj, 0);
778 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
782 obj_priv = to_intel_bo(obj);
783 offset = args->offset;
787 /* Operation in this page
789 * page_base = page offset within aperture
790 * page_offset = offset within page
791 * page_length = bytes to copy for this page
793 page_base = (offset & ~(PAGE_SIZE-1));
794 page_offset = offset & (PAGE_SIZE-1);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
799 ret = fast_shmem_write(obj_priv->pages,
800 page_base, page_offset,
801 user_data, page_length);
805 remain -= page_length;
806 user_data += page_length;
807 offset += page_length;
811 i915_gem_object_put_pages(obj);
813 mutex_unlock(&dev->struct_mutex);
819 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
820 * the memory and maps it using kmap_atomic for copying.
822 * This avoids taking mmap_sem for faulting on the user's address while the
823 * struct_mutex is held.
826 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
827 struct drm_i915_gem_pwrite *args,
828 struct drm_file *file_priv)
830 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
831 struct mm_struct *mm = current->mm;
832 struct page **user_pages;
834 loff_t offset, pinned_pages, i;
835 loff_t first_data_page, last_data_page, num_pages;
836 int shmem_page_index, shmem_page_offset;
837 int data_page_index, data_page_offset;
840 uint64_t data_ptr = args->data_ptr;
841 int do_bit17_swizzling;
845 /* Pin the user pages containing the data. We can't fault while
846 * holding the struct mutex, and all of the pwrite implementations
847 * want to hold it while dereferencing the user data.
849 first_data_page = data_ptr / PAGE_SIZE;
850 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
851 num_pages = last_data_page - first_data_page + 1;
853 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
854 if (user_pages == NULL)
857 down_read(&mm->mmap_sem);
858 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
859 num_pages, 0, 0, user_pages, NULL);
860 up_read(&mm->mmap_sem);
861 if (pinned_pages < num_pages) {
863 goto fail_put_user_pages;
866 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
868 mutex_lock(&dev->struct_mutex);
870 ret = i915_gem_object_get_pages_or_evict(obj);
874 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
878 obj_priv = to_intel_bo(obj);
879 offset = args->offset;
883 /* Operation in this page
885 * shmem_page_index = page number within shmem file
886 * shmem_page_offset = offset within page in shmem file
887 * data_page_index = page number in get_user_pages return
888 * data_page_offset = offset with data_page_index page.
889 * page_length = bytes to copy for this page
891 shmem_page_index = offset / PAGE_SIZE;
892 shmem_page_offset = offset & ~PAGE_MASK;
893 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
894 data_page_offset = data_ptr & ~PAGE_MASK;
896 page_length = remain;
897 if ((shmem_page_offset + page_length) > PAGE_SIZE)
898 page_length = PAGE_SIZE - shmem_page_offset;
899 if ((data_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - data_page_offset;
902 if (do_bit17_swizzling) {
903 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
905 user_pages[data_page_index],
910 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
912 user_pages[data_page_index],
919 remain -= page_length;
920 data_ptr += page_length;
921 offset += page_length;
925 i915_gem_object_put_pages(obj);
927 mutex_unlock(&dev->struct_mutex);
929 for (i = 0; i < pinned_pages; i++)
930 page_cache_release(user_pages[i]);
931 drm_free_large(user_pages);
937 * Writes data to the object referenced by handle.
939 * On error, the contents of the buffer that were to be modified are undefined.
942 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file_priv)
945 struct drm_i915_gem_pwrite *args = data;
946 struct drm_gem_object *obj;
947 struct drm_i915_gem_object *obj_priv;
950 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
953 obj_priv = to_intel_bo(obj);
955 /* Bounds check destination.
957 * XXX: This could use review for overflow issues...
959 if (args->offset > obj->size || args->size > obj->size ||
960 args->offset + args->size > obj->size) {
961 drm_gem_object_unreference_unlocked(obj);
965 /* We can only do the GTT pwrite on untiled buffers, as otherwise
966 * it would end up going through the fenced access, and we'll get
967 * different detiling behavior between reading and writing.
968 * pread/pwrite currently are reading and writing from the CPU
969 * perspective, requiring manual detiling by the client.
971 if (obj_priv->phys_obj)
972 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
973 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
974 dev->gtt_total != 0) {
975 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
976 if (ret == -EFAULT) {
977 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
980 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
981 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
983 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
984 if (ret == -EFAULT) {
985 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
992 DRM_INFO("pwrite failed %d\n", ret);
995 drm_gem_object_unreference_unlocked(obj);
1001 * Called when user space prepares to use an object with the CPU, either
1002 * through the mmap ioctl's mapping or a GTT mapping.
1005 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv)
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009 struct drm_i915_gem_set_domain *args = data;
1010 struct drm_gem_object *obj;
1011 struct drm_i915_gem_object *obj_priv;
1012 uint32_t read_domains = args->read_domains;
1013 uint32_t write_domain = args->write_domain;
1016 if (!(dev->driver->driver_features & DRIVER_GEM))
1019 /* Only handle setting domains to types used by the CPU. */
1020 if (write_domain & I915_GEM_GPU_DOMAINS)
1023 if (read_domains & I915_GEM_GPU_DOMAINS)
1026 /* Having something in the write domain implies it's in the read
1027 * domain, and only that read domain. Enforce that in the request.
1029 if (write_domain != 0 && read_domains != write_domain)
1032 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1035 obj_priv = to_intel_bo(obj);
1037 mutex_lock(&dev->struct_mutex);
1039 intel_mark_busy(dev, obj);
1042 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1043 obj, obj->size, read_domains, write_domain);
1045 if (read_domains & I915_GEM_DOMAIN_GTT) {
1046 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1048 /* Update the LRU on the fence for the CPU access that's
1051 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1052 struct drm_i915_fence_reg *reg =
1053 &dev_priv->fence_regs[obj_priv->fence_reg];
1054 list_move_tail(®->lru_list,
1055 &dev_priv->mm.fence_list);
1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1074 * Called when user space has done writes to this buffer
1077 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 mutex_unlock(&dev->struct_mutex);
1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1097 __func__, args->handle, obj, obj->size);
1099 obj_priv = to_intel_bo(obj);
1101 /* Pinned buffers may be scanout, so flush the cache */
1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1111 * Maps the contents of an object, returning the address it is mapped
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1118 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1133 offset = args->offset;
1135 down_write(¤t->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1139 up_write(¤t->mm->mmap_sem);
1140 drm_gem_object_unreference_unlocked(obj);
1141 if (IS_ERR((void *)addr))
1144 args->addr_ptr = (uint64_t) addr;
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1165 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1171 pgoff_t page_offset;
1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1194 /* Need a new fence register? */
1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1196 ret = i915_gem_object_get_fence_reg(obj);
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1207 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_NOPAGE;
1215 return VM_FAULT_OOM;
1217 return VM_FAULT_SIGBUS;
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1230 * This routine allocates and attaches a fake offset for @obj.
1233 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1238 struct drm_map_list *list;
1239 struct drm_local_map *map;
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1283 drm_mm_put_block(list->file_offset_node);
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1294 * Preserve the reservation of the mmapping with the DRM core code, but
1295 * relinquish ownership of the pages back to the system.
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1305 i915_gem_release_mmap(struct drm_gem_object *obj)
1307 struct drm_device *dev = obj->dev;
1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1316 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1318 struct drm_device *dev = obj->dev;
1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1336 obj_priv->mmap_offset = 0;
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1347 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1349 struct drm_device *dev = obj->dev;
1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1369 for (i = start; i < obj->size; i <<= 1)
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1391 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407 mutex_lock(&dev->struct_mutex);
1409 obj_priv = to_intel_bo(obj);
1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
1428 args->offset = obj_priv->mmap_offset;
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1434 if (!obj_priv->agp_mem) {
1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1451 i915_gem_object_put_pages(struct drm_gem_object *obj)
1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1454 int page_count = obj->size / PAGE_SIZE;
1457 BUG_ON(obj_priv->pages_refcount == 0);
1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1460 if (--obj_priv->pages_refcount != 0)
1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1466 if (obj_priv->madv == I915_MADV_DONTNEED)
1467 obj_priv->dirty = 0;
1469 for (i = 0; i < page_count; i++) {
1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
1474 mark_page_accessed(obj_priv->pages[i]);
1476 page_cache_release(obj_priv->pages[i]);
1478 obj_priv->dirty = 0;
1480 drm_free_large(obj_priv->pages);
1481 obj_priv->pages = NULL;
1485 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1491 /* Add a reference if we're newly entering the active list. */
1492 if (!obj_priv->active) {
1493 drm_gem_object_reference(obj);
1494 obj_priv->active = 1;
1496 /* Move from whatever list we were on to the tail of execution. */
1497 spin_lock(&dev_priv->mm.active_list_lock);
1498 list_move_tail(&obj_priv->list,
1499 &dev_priv->mm.active_list);
1500 spin_unlock(&dev_priv->mm.active_list_lock);
1501 obj_priv->last_rendering_seqno = seqno;
1505 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1507 struct drm_device *dev = obj->dev;
1508 drm_i915_private_t *dev_priv = dev->dev_private;
1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1511 BUG_ON(!obj_priv->active);
1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1513 obj_priv->last_rendering_seqno = 0;
1516 /* Immediately discard the backing storage */
1518 i915_gem_object_truncate(struct drm_gem_object *obj)
1520 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1521 struct inode *inode;
1523 inode = obj->filp->f_path.dentry->d_inode;
1524 if (inode->i_op->truncate)
1525 inode->i_op->truncate (inode);
1527 obj_priv->madv = __I915_MADV_PURGED;
1531 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1533 return obj_priv->madv == I915_MADV_DONTNEED;
1537 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1539 struct drm_device *dev = obj->dev;
1540 drm_i915_private_t *dev_priv = dev->dev_private;
1541 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1543 i915_verify_inactive(dev, __FILE__, __LINE__);
1544 if (obj_priv->pin_count != 0)
1545 list_del_init(&obj_priv->list);
1547 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1549 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1551 obj_priv->last_rendering_seqno = 0;
1552 if (obj_priv->active) {
1553 obj_priv->active = 0;
1554 drm_gem_object_unreference(obj);
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1560 i915_gem_process_flushing_list(struct drm_device *dev,
1561 uint32_t flush_domains, uint32_t seqno)
1563 drm_i915_private_t *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj_priv, *next;
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.gpu_write_list,
1569 struct drm_gem_object *obj = &obj_priv->base;
1571 if ((obj->write_domain & flush_domains) ==
1572 obj->write_domain) {
1573 uint32_t old_write_domain = obj->write_domain;
1575 obj->write_domain = 0;
1576 list_del_init(&obj_priv->gpu_write_list);
1577 i915_gem_object_move_to_active(obj, seqno);
1579 /* update the fence lru list */
1580 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1581 struct drm_i915_fence_reg *reg =
1582 &dev_priv->fence_regs[obj_priv->fence_reg];
1583 list_move_tail(®->lru_list,
1584 &dev_priv->mm.fence_list);
1587 trace_i915_gem_object_change_domain(obj,
1594 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1595 uint32_t flush_domains)
1597 drm_i915_private_t *dev_priv = dev->dev_private;
1598 struct drm_i915_file_private *i915_file_priv = NULL;
1599 struct drm_i915_gem_request *request;
1603 if (file_priv != NULL)
1604 i915_file_priv = file_priv->driver_priv;
1606 request = kzalloc(sizeof(*request), GFP_KERNEL);
1607 if (request == NULL)
1610 seqno = i915_ring_add_request(dev);
1612 DRM_DEBUG_DRIVER("%d\n", seqno);
1614 request->seqno = seqno;
1615 request->emitted_jiffies = jiffies;
1616 was_empty = list_empty(&dev_priv->mm.request_list);
1617 list_add_tail(&request->list, &dev_priv->mm.request_list);
1618 if (i915_file_priv) {
1619 list_add_tail(&request->client_list,
1620 &i915_file_priv->mm.request_list);
1622 INIT_LIST_HEAD(&request->client_list);
1625 /* Associate any objects on the flushing list matching the write
1626 * domain we're flushing with our flush.
1628 if (flush_domains != 0)
1629 i915_gem_process_flushing_list(dev, flush_domains, seqno);
1631 if (!dev_priv->mm.suspended) {
1632 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1634 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1640 * Command execution barrier
1642 * Ensures that all commands in the ring are finished
1643 * before signalling the CPU
1646 i915_retire_commands(struct drm_device *dev)
1648 drm_i915_private_t *dev_priv = dev->dev_private;
1649 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1650 uint32_t flush_domains = 0;
1653 /* The sampler always gets flushed on i965 (sigh) */
1655 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1658 OUT_RING(0); /* noop */
1660 return flush_domains;
1664 * Moves buffers associated only with the given active seqno from the active
1665 * to inactive list, potentially freeing them.
1668 i915_gem_retire_request(struct drm_device *dev,
1669 struct drm_i915_gem_request *request)
1671 drm_i915_private_t *dev_priv = dev->dev_private;
1673 trace_i915_gem_request_retire(dev, request->seqno);
1675 /* Move any buffers on the active list that are no longer referenced
1676 * by the ringbuffer to the flushing/inactive lists as appropriate.
1678 spin_lock(&dev_priv->mm.active_list_lock);
1679 while (!list_empty(&dev_priv->mm.active_list)) {
1680 struct drm_gem_object *obj;
1681 struct drm_i915_gem_object *obj_priv;
1683 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1684 struct drm_i915_gem_object,
1686 obj = &obj_priv->base;
1688 /* If the seqno being retired doesn't match the oldest in the
1689 * list, then the oldest in the list must still be newer than
1692 if (obj_priv->last_rendering_seqno != request->seqno)
1696 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1697 __func__, request->seqno, obj);
1700 if (obj->write_domain != 0)
1701 i915_gem_object_move_to_flushing(obj);
1703 /* Take a reference on the object so it won't be
1704 * freed while the spinlock is held. The list
1705 * protection for this spinlock is safe when breaking
1706 * the lock like this since the next thing we do
1707 * is just get the head of the list again.
1709 drm_gem_object_reference(obj);
1710 i915_gem_object_move_to_inactive(obj);
1711 spin_unlock(&dev_priv->mm.active_list_lock);
1712 drm_gem_object_unreference(obj);
1713 spin_lock(&dev_priv->mm.active_list_lock);
1717 spin_unlock(&dev_priv->mm.active_list_lock);
1721 * Returns true if seq1 is later than seq2.
1724 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1726 return (int32_t)(seq1 - seq2) >= 0;
1730 i915_get_gem_seqno(struct drm_device *dev)
1732 drm_i915_private_t *dev_priv = dev->dev_private;
1734 if (HAS_PIPE_CONTROL(dev))
1735 return ((volatile u32 *)(dev_priv->seqno_page))[0];
1737 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1741 * This function clears the request list as sequence numbers are passed.
1744 i915_gem_retire_requests(struct drm_device *dev)
1746 drm_i915_private_t *dev_priv = dev->dev_private;
1749 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1752 seqno = i915_get_gem_seqno(dev);
1754 while (!list_empty(&dev_priv->mm.request_list)) {
1755 struct drm_i915_gem_request *request;
1756 uint32_t retiring_seqno;
1758 request = list_first_entry(&dev_priv->mm.request_list,
1759 struct drm_i915_gem_request,
1761 retiring_seqno = request->seqno;
1763 if (i915_seqno_passed(seqno, retiring_seqno) ||
1764 atomic_read(&dev_priv->mm.wedged)) {
1765 i915_gem_retire_request(dev, request);
1767 list_del(&request->list);
1768 list_del(&request->client_list);
1774 if (unlikely (dev_priv->trace_irq_seqno &&
1775 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1776 i915_user_irq_put(dev);
1777 dev_priv->trace_irq_seqno = 0;
1782 i915_gem_retire_work_handler(struct work_struct *work)
1784 drm_i915_private_t *dev_priv;
1785 struct drm_device *dev;
1787 dev_priv = container_of(work, drm_i915_private_t,
1788 mm.retire_work.work);
1789 dev = dev_priv->dev;
1791 mutex_lock(&dev->struct_mutex);
1792 i915_gem_retire_requests(dev);
1793 if (!dev_priv->mm.suspended &&
1794 !list_empty(&dev_priv->mm.request_list))
1795 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1796 mutex_unlock(&dev->struct_mutex);
1800 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1802 drm_i915_private_t *dev_priv = dev->dev_private;
1808 if (atomic_read(&dev_priv->mm.wedged))
1811 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1812 if (HAS_PCH_SPLIT(dev))
1813 ier = I915_READ(DEIER) | I915_READ(GTIER);
1815 ier = I915_READ(IER);
1817 DRM_ERROR("something (likely vbetool) disabled "
1818 "interrupts, re-enabling\n");
1819 i915_driver_irq_preinstall(dev);
1820 i915_driver_irq_postinstall(dev);
1823 trace_i915_gem_request_wait_begin(dev, seqno);
1825 dev_priv->mm.waiting_gem_seqno = seqno;
1826 i915_user_irq_get(dev);
1828 ret = wait_event_interruptible(dev_priv->irq_queue,
1829 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1830 atomic_read(&dev_priv->mm.wedged));
1832 wait_event(dev_priv->irq_queue,
1833 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1834 atomic_read(&dev_priv->mm.wedged));
1836 i915_user_irq_put(dev);
1837 dev_priv->mm.waiting_gem_seqno = 0;
1839 trace_i915_gem_request_wait_end(dev, seqno);
1841 if (atomic_read(&dev_priv->mm.wedged))
1844 if (ret && ret != -ERESTARTSYS)
1845 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1846 __func__, ret, seqno, i915_get_gem_seqno(dev));
1848 /* Directly dispatch request retiring. While we have the work queue
1849 * to handle this, the waiter on a request often wants an associated
1850 * buffer to have made it to the inactive list, and we would need
1851 * a separate wait queue to handle that.
1854 i915_gem_retire_requests(dev);
1860 * Waits for a sequence number to be signaled, and cleans up the
1861 * request and object lists appropriately for that event.
1864 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1866 return i915_do_wait_request(dev, seqno, 1);
1871 * Ensures that all rendering to the object has completed and the object is
1872 * safe to unbind from the GTT or access from the CPU.
1875 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1877 struct drm_device *dev = obj->dev;
1878 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1881 /* This function only exists to support waiting for existing rendering,
1882 * not for emitting required flushes.
1884 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1886 /* If there is rendering queued on the buffer being evicted, wait for
1889 if (obj_priv->active) {
1891 DRM_INFO("%s: object %p wait for seqno %08x\n",
1892 __func__, obj, obj_priv->last_rendering_seqno);
1894 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1903 * Unbinds an object from the GTT aperture.
1906 i915_gem_object_unbind(struct drm_gem_object *obj)
1908 struct drm_device *dev = obj->dev;
1909 drm_i915_private_t *dev_priv = dev->dev_private;
1910 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1914 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1915 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1917 if (obj_priv->gtt_space == NULL)
1920 if (obj_priv->pin_count != 0) {
1921 DRM_ERROR("Attempting to unbind pinned buffer\n");
1925 /* blow away mappings if mapped through GTT */
1926 i915_gem_release_mmap(obj);
1928 /* Move the object to the CPU domain to ensure that
1929 * any possible CPU writes while it's not in the GTT
1930 * are flushed when we go to remap it. This will
1931 * also ensure that all pending GPU writes are finished
1934 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1936 if (ret != -ERESTARTSYS)
1937 DRM_ERROR("set_domain failed: %d\n", ret);
1941 BUG_ON(obj_priv->active);
1943 /* release the fence reg _after_ flushing */
1944 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1945 i915_gem_clear_fence_reg(obj);
1947 if (obj_priv->agp_mem != NULL) {
1948 drm_unbind_agp(obj_priv->agp_mem);
1949 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1950 obj_priv->agp_mem = NULL;
1953 i915_gem_object_put_pages(obj);
1954 BUG_ON(obj_priv->pages_refcount);
1956 if (obj_priv->gtt_space) {
1957 atomic_dec(&dev->gtt_count);
1958 atomic_sub(obj->size, &dev->gtt_memory);
1960 drm_mm_put_block(obj_priv->gtt_space);
1961 obj_priv->gtt_space = NULL;
1964 /* Remove ourselves from the LRU list if present. */
1965 spin_lock(&dev_priv->mm.active_list_lock);
1966 if (!list_empty(&obj_priv->list))
1967 list_del_init(&obj_priv->list);
1968 spin_unlock(&dev_priv->mm.active_list_lock);
1970 if (i915_gem_object_is_purgeable(obj_priv))
1971 i915_gem_object_truncate(obj);
1973 trace_i915_gem_object_unbind(obj);
1978 static struct drm_gem_object *
1979 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
1981 drm_i915_private_t *dev_priv = dev->dev_private;
1982 struct drm_i915_gem_object *obj_priv;
1983 struct drm_gem_object *best = NULL;
1984 struct drm_gem_object *first = NULL;
1986 /* Try to find the smallest clean object */
1987 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
1988 struct drm_gem_object *obj = &obj_priv->base;
1989 if (obj->size >= min_size) {
1990 if ((!obj_priv->dirty ||
1991 i915_gem_object_is_purgeable(obj_priv)) &&
1992 (!best || obj->size < best->size)) {
1994 if (best->size == min_size)
2002 return best ? best : first;
2006 i915_gpu_idle(struct drm_device *dev)
2008 drm_i915_private_t *dev_priv = dev->dev_private;
2012 spin_lock(&dev_priv->mm.active_list_lock);
2013 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2014 list_empty(&dev_priv->mm.active_list);
2015 spin_unlock(&dev_priv->mm.active_list_lock);
2020 /* Flush everything onto the inactive list. */
2021 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2022 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2026 return i915_wait_request(dev, seqno);
2030 i915_gem_evict_everything(struct drm_device *dev)
2032 drm_i915_private_t *dev_priv = dev->dev_private;
2036 spin_lock(&dev_priv->mm.active_list_lock);
2037 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2038 list_empty(&dev_priv->mm.flushing_list) &&
2039 list_empty(&dev_priv->mm.active_list));
2040 spin_unlock(&dev_priv->mm.active_list_lock);
2045 /* Flush everything (on to the inactive lists) and evict */
2046 ret = i915_gpu_idle(dev);
2050 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2052 ret = i915_gem_evict_from_inactive_list(dev);
2056 spin_lock(&dev_priv->mm.active_list_lock);
2057 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2058 list_empty(&dev_priv->mm.flushing_list) &&
2059 list_empty(&dev_priv->mm.active_list));
2060 spin_unlock(&dev_priv->mm.active_list_lock);
2061 BUG_ON(!lists_empty);
2067 i915_gem_evict_something(struct drm_device *dev, int min_size)
2069 drm_i915_private_t *dev_priv = dev->dev_private;
2070 struct drm_gem_object *obj;
2074 i915_gem_retire_requests(dev);
2076 /* If there's an inactive buffer available now, grab it
2079 obj = i915_gem_find_inactive_object(dev, min_size);
2081 struct drm_i915_gem_object *obj_priv;
2084 DRM_INFO("%s: evicting %p\n", __func__, obj);
2086 obj_priv = to_intel_bo(obj);
2087 BUG_ON(obj_priv->pin_count != 0);
2088 BUG_ON(obj_priv->active);
2090 /* Wait on the rendering and unbind the buffer. */
2091 return i915_gem_object_unbind(obj);
2094 /* If we didn't get anything, but the ring is still processing
2095 * things, wait for the next to finish and hopefully leave us
2096 * a buffer to evict.
2098 if (!list_empty(&dev_priv->mm.request_list)) {
2099 struct drm_i915_gem_request *request;
2101 request = list_first_entry(&dev_priv->mm.request_list,
2102 struct drm_i915_gem_request,
2105 ret = i915_wait_request(dev, request->seqno);
2112 /* If we didn't have anything on the request list but there
2113 * are buffers awaiting a flush, emit one and try again.
2114 * When we wait on it, those buffers waiting for that flush
2115 * will get moved to inactive.
2117 if (!list_empty(&dev_priv->mm.flushing_list)) {
2118 struct drm_i915_gem_object *obj_priv;
2120 /* Find an object that we can immediately reuse */
2121 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2122 obj = &obj_priv->base;
2123 if (obj->size >= min_size)
2135 seqno = i915_add_request(dev, NULL, obj->write_domain);
2142 /* If we didn't do any of the above, there's no single buffer
2143 * large enough to swap out for the new one, so just evict
2144 * everything and start again. (This should be rare.)
2146 if (!list_empty (&dev_priv->mm.inactive_list))
2147 return i915_gem_evict_from_inactive_list(dev);
2149 return i915_gem_evict_everything(dev);
2154 i915_gem_object_get_pages(struct drm_gem_object *obj,
2157 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2159 struct address_space *mapping;
2160 struct inode *inode;
2163 if (obj_priv->pages_refcount++ != 0)
2166 /* Get the list of pages out of our struct file. They'll be pinned
2167 * at this point until we release them.
2169 page_count = obj->size / PAGE_SIZE;
2170 BUG_ON(obj_priv->pages != NULL);
2171 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2172 if (obj_priv->pages == NULL) {
2173 obj_priv->pages_refcount--;
2177 inode = obj->filp->f_path.dentry->d_inode;
2178 mapping = inode->i_mapping;
2179 for (i = 0; i < page_count; i++) {
2180 page = read_cache_page_gfp(mapping, i,
2181 mapping_gfp_mask (mapping) |
2187 obj_priv->pages[i] = page;
2190 if (obj_priv->tiling_mode != I915_TILING_NONE)
2191 i915_gem_object_do_bit_17_swizzle(obj);
2197 page_cache_release(obj_priv->pages[i]);
2199 drm_free_large(obj_priv->pages);
2200 obj_priv->pages = NULL;
2201 obj_priv->pages_refcount--;
2202 return PTR_ERR(page);
2205 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2207 struct drm_gem_object *obj = reg->obj;
2208 struct drm_device *dev = obj->dev;
2209 drm_i915_private_t *dev_priv = dev->dev_private;
2210 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2211 int regnum = obj_priv->fence_reg;
2214 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2216 val |= obj_priv->gtt_offset & 0xfffff000;
2217 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2218 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2220 if (obj_priv->tiling_mode == I915_TILING_Y)
2221 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2222 val |= I965_FENCE_REG_VALID;
2224 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2227 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2229 struct drm_gem_object *obj = reg->obj;
2230 struct drm_device *dev = obj->dev;
2231 drm_i915_private_t *dev_priv = dev->dev_private;
2232 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2233 int regnum = obj_priv->fence_reg;
2236 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2238 val |= obj_priv->gtt_offset & 0xfffff000;
2239 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2240 if (obj_priv->tiling_mode == I915_TILING_Y)
2241 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2242 val |= I965_FENCE_REG_VALID;
2244 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2247 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2249 struct drm_gem_object *obj = reg->obj;
2250 struct drm_device *dev = obj->dev;
2251 drm_i915_private_t *dev_priv = dev->dev_private;
2252 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2253 int regnum = obj_priv->fence_reg;
2255 uint32_t fence_reg, val;
2258 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2259 (obj_priv->gtt_offset & (obj->size - 1))) {
2260 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2261 __func__, obj_priv->gtt_offset, obj->size);
2265 if (obj_priv->tiling_mode == I915_TILING_Y &&
2266 HAS_128_BYTE_Y_TILING(dev))
2271 /* Note: pitch better be a power of two tile widths */
2272 pitch_val = obj_priv->stride / tile_width;
2273 pitch_val = ffs(pitch_val) - 1;
2275 if (obj_priv->tiling_mode == I915_TILING_Y &&
2276 HAS_128_BYTE_Y_TILING(dev))
2277 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2279 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2281 val = obj_priv->gtt_offset;
2282 if (obj_priv->tiling_mode == I915_TILING_Y)
2283 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2284 val |= I915_FENCE_SIZE_BITS(obj->size);
2285 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2286 val |= I830_FENCE_REG_VALID;
2289 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2291 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2292 I915_WRITE(fence_reg, val);
2295 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2297 struct drm_gem_object *obj = reg->obj;
2298 struct drm_device *dev = obj->dev;
2299 drm_i915_private_t *dev_priv = dev->dev_private;
2300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2301 int regnum = obj_priv->fence_reg;
2304 uint32_t fence_size_bits;
2306 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2307 (obj_priv->gtt_offset & (obj->size - 1))) {
2308 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2309 __func__, obj_priv->gtt_offset);
2313 pitch_val = obj_priv->stride / 128;
2314 pitch_val = ffs(pitch_val) - 1;
2315 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2317 val = obj_priv->gtt_offset;
2318 if (obj_priv->tiling_mode == I915_TILING_Y)
2319 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2320 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2321 WARN_ON(fence_size_bits & ~0x00000f00);
2322 val |= fence_size_bits;
2323 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2324 val |= I830_FENCE_REG_VALID;
2326 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2329 static int i915_find_fence_reg(struct drm_device *dev)
2331 struct drm_i915_fence_reg *reg = NULL;
2332 struct drm_i915_gem_object *obj_priv = NULL;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct drm_gem_object *obj = NULL;
2337 /* First try to find a free reg */
2339 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2340 reg = &dev_priv->fence_regs[i];
2344 obj_priv = to_intel_bo(reg->obj);
2345 if (!obj_priv->pin_count)
2352 /* None available, try to steal one or wait for a user to finish */
2353 i = I915_FENCE_REG_NONE;
2354 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2357 obj_priv = to_intel_bo(obj);
2359 if (obj_priv->pin_count)
2363 i = obj_priv->fence_reg;
2367 BUG_ON(i == I915_FENCE_REG_NONE);
2369 /* We only have a reference on obj from the active list. put_fence_reg
2370 * might drop that one, causing a use-after-free in it. So hold a
2371 * private reference to obj like the other callers of put_fence_reg
2372 * (set_tiling ioctl) do. */
2373 drm_gem_object_reference(obj);
2374 ret = i915_gem_object_put_fence_reg(obj);
2375 drm_gem_object_unreference(obj);
2383 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2384 * @obj: object to map through a fence reg
2386 * When mapping objects through the GTT, userspace wants to be able to write
2387 * to them without having to worry about swizzling if the object is tiled.
2389 * This function walks the fence regs looking for a free one for @obj,
2390 * stealing one if it can't find any.
2392 * It then sets up the reg based on the object's properties: address, pitch
2393 * and tiling format.
2396 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2398 struct drm_device *dev = obj->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2401 struct drm_i915_fence_reg *reg = NULL;
2404 /* Just update our place in the LRU if our fence is getting used. */
2405 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2406 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2407 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2411 switch (obj_priv->tiling_mode) {
2412 case I915_TILING_NONE:
2413 WARN(1, "allocating a fence for non-tiled object?\n");
2416 if (!obj_priv->stride)
2418 WARN((obj_priv->stride & (512 - 1)),
2419 "object 0x%08x is X tiled but has non-512B pitch\n",
2420 obj_priv->gtt_offset);
2423 if (!obj_priv->stride)
2425 WARN((obj_priv->stride & (128 - 1)),
2426 "object 0x%08x is Y tiled but has non-128B pitch\n",
2427 obj_priv->gtt_offset);
2431 ret = i915_find_fence_reg(dev);
2435 obj_priv->fence_reg = ret;
2436 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2437 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2442 sandybridge_write_fence_reg(reg);
2443 else if (IS_I965G(dev))
2444 i965_write_fence_reg(reg);
2445 else if (IS_I9XX(dev))
2446 i915_write_fence_reg(reg);
2448 i830_write_fence_reg(reg);
2450 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2451 obj_priv->tiling_mode);
2457 * i915_gem_clear_fence_reg - clear out fence register info
2458 * @obj: object to clear
2460 * Zeroes out the fence register itself and clears out the associated
2461 * data structures in dev_priv and obj_priv.
2464 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2466 struct drm_device *dev = obj->dev;
2467 drm_i915_private_t *dev_priv = dev->dev_private;
2468 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2469 struct drm_i915_fence_reg *reg =
2470 &dev_priv->fence_regs[obj_priv->fence_reg];
2473 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2474 (obj_priv->fence_reg * 8), 0);
2475 } else if (IS_I965G(dev)) {
2476 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2480 if (obj_priv->fence_reg < 8)
2481 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2483 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2486 I915_WRITE(fence_reg, 0);
2490 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2491 list_del_init(®->lru_list);
2495 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2496 * to the buffer to finish, and then resets the fence register.
2497 * @obj: tiled object holding a fence register.
2499 * Zeroes out the fence register itself and clears out the associated
2500 * data structures in dev_priv and obj_priv.
2503 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2505 struct drm_device *dev = obj->dev;
2506 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2508 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2511 /* If we've changed tiling, GTT-mappings of the object
2512 * need to re-fault to ensure that the correct fence register
2513 * setup is in place.
2515 i915_gem_release_mmap(obj);
2517 /* On the i915, GPU access to tiled buffers is via a fence,
2518 * therefore we must wait for any outstanding access to complete
2519 * before clearing the fence.
2521 if (!IS_I965G(dev)) {
2524 i915_gem_object_flush_gpu_write_domain(obj);
2525 ret = i915_gem_object_wait_rendering(obj);
2530 i915_gem_object_flush_gtt_write_domain(obj);
2531 i915_gem_clear_fence_reg (obj);
2537 * Finds free space in the GTT aperture and binds the object there.
2540 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2542 struct drm_device *dev = obj->dev;
2543 drm_i915_private_t *dev_priv = dev->dev_private;
2544 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2545 struct drm_mm_node *free_space;
2546 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2549 if (obj_priv->madv != I915_MADV_WILLNEED) {
2550 DRM_ERROR("Attempting to bind a purgeable object\n");
2555 alignment = i915_gem_get_gtt_alignment(obj);
2556 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2557 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2562 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2563 obj->size, alignment, 0);
2564 if (free_space != NULL) {
2565 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2567 if (obj_priv->gtt_space != NULL) {
2568 obj_priv->gtt_space->private = obj;
2569 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2572 if (obj_priv->gtt_space == NULL) {
2573 /* If the gtt is empty and we're still having trouble
2574 * fitting our object in, we're out of memory.
2577 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2579 ret = i915_gem_evict_something(dev, obj->size);
2587 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2588 obj->size, obj_priv->gtt_offset);
2590 ret = i915_gem_object_get_pages(obj, gfpmask);
2592 drm_mm_put_block(obj_priv->gtt_space);
2593 obj_priv->gtt_space = NULL;
2595 if (ret == -ENOMEM) {
2596 /* first try to clear up some space from the GTT */
2597 ret = i915_gem_evict_something(dev, obj->size);
2599 /* now try to shrink everyone else */
2614 /* Create an AGP memory structure pointing at our pages, and bind it
2617 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2619 obj->size >> PAGE_SHIFT,
2620 obj_priv->gtt_offset,
2621 obj_priv->agp_type);
2622 if (obj_priv->agp_mem == NULL) {
2623 i915_gem_object_put_pages(obj);
2624 drm_mm_put_block(obj_priv->gtt_space);
2625 obj_priv->gtt_space = NULL;
2627 ret = i915_gem_evict_something(dev, obj->size);
2633 atomic_inc(&dev->gtt_count);
2634 atomic_add(obj->size, &dev->gtt_memory);
2636 /* Assert that the object is not currently in any GPU domain. As it
2637 * wasn't in the GTT, there shouldn't be any way it could have been in
2640 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2641 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2643 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2649 i915_gem_clflush_object(struct drm_gem_object *obj)
2651 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2653 /* If we don't have a page list set up, then we're not pinned
2654 * to GPU, and we can ignore the cache flush because it'll happen
2655 * again at bind time.
2657 if (obj_priv->pages == NULL)
2660 trace_i915_gem_object_clflush(obj);
2662 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2665 /** Flushes any GPU write domain for the object if it's dirty. */
2667 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2669 struct drm_device *dev = obj->dev;
2670 uint32_t old_write_domain;
2672 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2675 /* Queue the GPU write cache flushing we need. */
2676 old_write_domain = obj->write_domain;
2677 i915_gem_flush(dev, 0, obj->write_domain);
2678 (void) i915_add_request(dev, NULL, obj->write_domain);
2679 BUG_ON(obj->write_domain);
2681 trace_i915_gem_object_change_domain(obj,
2686 /** Flushes the GTT write domain for the object if it's dirty. */
2688 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2690 uint32_t old_write_domain;
2692 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2695 /* No actual flushing is required for the GTT write domain. Writes
2696 * to it immediately go to main memory as far as we know, so there's
2697 * no chipset flush. It also doesn't land in render cache.
2699 old_write_domain = obj->write_domain;
2700 obj->write_domain = 0;
2702 trace_i915_gem_object_change_domain(obj,
2707 /** Flushes the CPU write domain for the object if it's dirty. */
2709 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2711 struct drm_device *dev = obj->dev;
2712 uint32_t old_write_domain;
2714 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2717 i915_gem_clflush_object(obj);
2718 drm_agp_chipset_flush(dev);
2719 old_write_domain = obj->write_domain;
2720 obj->write_domain = 0;
2722 trace_i915_gem_object_change_domain(obj,
2728 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2730 switch (obj->write_domain) {
2731 case I915_GEM_DOMAIN_GTT:
2732 i915_gem_object_flush_gtt_write_domain(obj);
2734 case I915_GEM_DOMAIN_CPU:
2735 i915_gem_object_flush_cpu_write_domain(obj);
2738 i915_gem_object_flush_gpu_write_domain(obj);
2744 * Moves a single object to the GTT read, and possibly write domain.
2746 * This function returns when the move is complete, including waiting on
2750 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2752 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2753 uint32_t old_write_domain, old_read_domains;
2756 /* Not valid to be called on unbound objects. */
2757 if (obj_priv->gtt_space == NULL)
2760 i915_gem_object_flush_gpu_write_domain(obj);
2761 /* Wait on any GPU rendering and flushing to occur. */
2762 ret = i915_gem_object_wait_rendering(obj);
2766 old_write_domain = obj->write_domain;
2767 old_read_domains = obj->read_domains;
2769 /* If we're writing through the GTT domain, then CPU and GPU caches
2770 * will need to be invalidated at next use.
2773 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2775 i915_gem_object_flush_cpu_write_domain(obj);
2777 /* It should now be out of any other write domains, and we can update
2778 * the domain values for our changes.
2780 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2781 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2783 obj->write_domain = I915_GEM_DOMAIN_GTT;
2784 obj_priv->dirty = 1;
2787 trace_i915_gem_object_change_domain(obj,
2795 * Prepare buffer for display plane. Use uninterruptible for possible flush
2796 * wait, as in modesetting process we're not supposed to be interrupted.
2799 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2801 struct drm_device *dev = obj->dev;
2802 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2803 uint32_t old_write_domain, old_read_domains;
2806 /* Not valid to be called on unbound objects. */
2807 if (obj_priv->gtt_space == NULL)
2810 i915_gem_object_flush_gpu_write_domain(obj);
2812 /* Wait on any GPU rendering and flushing to occur. */
2813 if (obj_priv->active) {
2815 DRM_INFO("%s: object %p wait for seqno %08x\n",
2816 __func__, obj, obj_priv->last_rendering_seqno);
2818 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2823 old_write_domain = obj->write_domain;
2824 old_read_domains = obj->read_domains;
2826 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2828 i915_gem_object_flush_cpu_write_domain(obj);
2830 /* It should now be out of any other write domains, and we can update
2831 * the domain values for our changes.
2833 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2834 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2835 obj->write_domain = I915_GEM_DOMAIN_GTT;
2836 obj_priv->dirty = 1;
2838 trace_i915_gem_object_change_domain(obj,
2846 * Moves a single object to the CPU read, and possibly write domain.
2848 * This function returns when the move is complete, including waiting on
2852 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2854 uint32_t old_write_domain, old_read_domains;
2857 i915_gem_object_flush_gpu_write_domain(obj);
2858 /* Wait on any GPU rendering and flushing to occur. */
2859 ret = i915_gem_object_wait_rendering(obj);
2863 i915_gem_object_flush_gtt_write_domain(obj);
2865 /* If we have a partially-valid cache of the object in the CPU,
2866 * finish invalidating it and free the per-page flags.
2868 i915_gem_object_set_to_full_cpu_read_domain(obj);
2870 old_write_domain = obj->write_domain;
2871 old_read_domains = obj->read_domains;
2873 /* Flush the CPU cache if it's still invalid. */
2874 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2875 i915_gem_clflush_object(obj);
2877 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2880 /* It should now be out of any other write domains, and we can update
2881 * the domain values for our changes.
2883 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2885 /* If we're writing through the CPU, then the GPU read domains will
2886 * need to be invalidated at next use.
2889 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2890 obj->write_domain = I915_GEM_DOMAIN_CPU;
2893 trace_i915_gem_object_change_domain(obj,
2901 * Set the next domain for the specified object. This
2902 * may not actually perform the necessary flushing/invaliding though,
2903 * as that may want to be batched with other set_domain operations
2905 * This is (we hope) the only really tricky part of gem. The goal
2906 * is fairly simple -- track which caches hold bits of the object
2907 * and make sure they remain coherent. A few concrete examples may
2908 * help to explain how it works. For shorthand, we use the notation
2909 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2910 * a pair of read and write domain masks.
2912 * Case 1: the batch buffer
2918 * 5. Unmapped from GTT
2921 * Let's take these a step at a time
2924 * Pages allocated from the kernel may still have
2925 * cache contents, so we set them to (CPU, CPU) always.
2926 * 2. Written by CPU (using pwrite)
2927 * The pwrite function calls set_domain (CPU, CPU) and
2928 * this function does nothing (as nothing changes)
2930 * This function asserts that the object is not
2931 * currently in any GPU-based read or write domains
2933 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2934 * As write_domain is zero, this function adds in the
2935 * current read domains (CPU+COMMAND, 0).
2936 * flush_domains is set to CPU.
2937 * invalidate_domains is set to COMMAND
2938 * clflush is run to get data out of the CPU caches
2939 * then i915_dev_set_domain calls i915_gem_flush to
2940 * emit an MI_FLUSH and drm_agp_chipset_flush
2941 * 5. Unmapped from GTT
2942 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2943 * flush_domains and invalidate_domains end up both zero
2944 * so no flushing/invalidating happens
2948 * Case 2: The shared render buffer
2952 * 3. Read/written by GPU
2953 * 4. set_domain to (CPU,CPU)
2954 * 5. Read/written by CPU
2955 * 6. Read/written by GPU
2958 * Same as last example, (CPU, CPU)
2960 * Nothing changes (assertions find that it is not in the GPU)
2961 * 3. Read/written by GPU
2962 * execbuffer calls set_domain (RENDER, RENDER)
2963 * flush_domains gets CPU
2964 * invalidate_domains gets GPU
2966 * MI_FLUSH and drm_agp_chipset_flush
2967 * 4. set_domain (CPU, CPU)
2968 * flush_domains gets GPU
2969 * invalidate_domains gets CPU
2970 * wait_rendering (obj) to make sure all drawing is complete.
2971 * This will include an MI_FLUSH to get the data from GPU
2973 * clflush (obj) to invalidate the CPU cache
2974 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2975 * 5. Read/written by CPU
2976 * cache lines are loaded and dirtied
2977 * 6. Read written by GPU
2978 * Same as last GPU access
2980 * Case 3: The constant buffer
2985 * 4. Updated (written) by CPU again
2994 * flush_domains = CPU
2995 * invalidate_domains = RENDER
2998 * drm_agp_chipset_flush
2999 * 4. Updated (written) by CPU again
3001 * flush_domains = 0 (no previous write domain)
3002 * invalidate_domains = 0 (no new read domains)
3005 * flush_domains = CPU
3006 * invalidate_domains = RENDER
3009 * drm_agp_chipset_flush
3012 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3014 struct drm_device *dev = obj->dev;
3015 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3016 uint32_t invalidate_domains = 0;
3017 uint32_t flush_domains = 0;
3018 uint32_t old_read_domains;
3020 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3021 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3023 intel_mark_busy(dev, obj);
3026 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3028 obj->read_domains, obj->pending_read_domains,
3029 obj->write_domain, obj->pending_write_domain);
3032 * If the object isn't moving to a new write domain,
3033 * let the object stay in multiple read domains
3035 if (obj->pending_write_domain == 0)
3036 obj->pending_read_domains |= obj->read_domains;
3038 obj_priv->dirty = 1;
3041 * Flush the current write domain if
3042 * the new read domains don't match. Invalidate
3043 * any read domains which differ from the old
3046 if (obj->write_domain &&
3047 obj->write_domain != obj->pending_read_domains) {
3048 flush_domains |= obj->write_domain;
3049 invalidate_domains |=
3050 obj->pending_read_domains & ~obj->write_domain;
3053 * Invalidate any read caches which may have
3054 * stale data. That is, any new read domains.
3056 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3057 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3059 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3060 __func__, flush_domains, invalidate_domains);
3062 i915_gem_clflush_object(obj);
3065 old_read_domains = obj->read_domains;
3067 /* The actual obj->write_domain will be updated with
3068 * pending_write_domain after we emit the accumulated flush for all
3069 * of our domain changes in execbuffers (which clears objects'
3070 * write_domains). So if we have a current write domain that we
3071 * aren't changing, set pending_write_domain to that.
3073 if (flush_domains == 0 && obj->pending_write_domain == 0)
3074 obj->pending_write_domain = obj->write_domain;
3075 obj->read_domains = obj->pending_read_domains;
3077 dev->invalidate_domains |= invalidate_domains;
3078 dev->flush_domains |= flush_domains;
3080 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3082 obj->read_domains, obj->write_domain,
3083 dev->invalidate_domains, dev->flush_domains);
3086 trace_i915_gem_object_change_domain(obj,
3092 * Moves the object from a partially CPU read to a full one.
3094 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3095 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3098 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3100 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3102 if (!obj_priv->page_cpu_valid)
3105 /* If we're partially in the CPU read domain, finish moving it in.
3107 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3110 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3111 if (obj_priv->page_cpu_valid[i])
3113 drm_clflush_pages(obj_priv->pages + i, 1);
3117 /* Free the page_cpu_valid mappings which are now stale, whether
3118 * or not we've got I915_GEM_DOMAIN_CPU.
3120 kfree(obj_priv->page_cpu_valid);
3121 obj_priv->page_cpu_valid = NULL;
3125 * Set the CPU read domain on a range of the object.
3127 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3128 * not entirely valid. The page_cpu_valid member of the object flags which
3129 * pages have been flushed, and will be respected by
3130 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3131 * of the whole object.
3133 * This function returns when the move is complete, including waiting on
3137 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3138 uint64_t offset, uint64_t size)
3140 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3141 uint32_t old_read_domains;
3144 if (offset == 0 && size == obj->size)
3145 return i915_gem_object_set_to_cpu_domain(obj, 0);
3147 i915_gem_object_flush_gpu_write_domain(obj);
3148 /* Wait on any GPU rendering and flushing to occur. */
3149 ret = i915_gem_object_wait_rendering(obj);
3152 i915_gem_object_flush_gtt_write_domain(obj);
3154 /* If we're already fully in the CPU read domain, we're done. */
3155 if (obj_priv->page_cpu_valid == NULL &&
3156 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3159 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3160 * newly adding I915_GEM_DOMAIN_CPU
3162 if (obj_priv->page_cpu_valid == NULL) {
3163 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3165 if (obj_priv->page_cpu_valid == NULL)
3167 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3168 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3170 /* Flush the cache on any pages that are still invalid from the CPU's
3173 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3175 if (obj_priv->page_cpu_valid[i])
3178 drm_clflush_pages(obj_priv->pages + i, 1);
3180 obj_priv->page_cpu_valid[i] = 1;
3183 /* It should now be out of any other write domains, and we can update
3184 * the domain values for our changes.
3186 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3188 old_read_domains = obj->read_domains;
3189 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3191 trace_i915_gem_object_change_domain(obj,
3199 * Pin an object to the GTT and evaluate the relocations landing in it.
3202 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3203 struct drm_file *file_priv,
3204 struct drm_i915_gem_exec_object2 *entry,
3205 struct drm_i915_gem_relocation_entry *relocs)
3207 struct drm_device *dev = obj->dev;
3208 drm_i915_private_t *dev_priv = dev->dev_private;
3209 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3211 void __iomem *reloc_page;
3214 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3215 obj_priv->tiling_mode != I915_TILING_NONE;
3217 /* Check fence reg constraints and rebind if necessary */
3218 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3219 obj_priv->tiling_mode))
3220 i915_gem_object_unbind(obj);
3222 /* Choose the GTT offset for our buffer and put it there. */
3223 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3228 * Pre-965 chips need a fence register set up in order to
3229 * properly handle blits to/from tiled surfaces.
3232 ret = i915_gem_object_get_fence_reg(obj);
3234 if (ret != -EBUSY && ret != -ERESTARTSYS)
3235 DRM_ERROR("Failure to install fence: %d\n",
3237 i915_gem_object_unpin(obj);
3242 entry->offset = obj_priv->gtt_offset;
3244 /* Apply the relocations, using the GTT aperture to avoid cache
3245 * flushing requirements.
3247 for (i = 0; i < entry->relocation_count; i++) {
3248 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3249 struct drm_gem_object *target_obj;
3250 struct drm_i915_gem_object *target_obj_priv;
3251 uint32_t reloc_val, reloc_offset;
3252 uint32_t __iomem *reloc_entry;
3254 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3255 reloc->target_handle);
3256 if (target_obj == NULL) {
3257 i915_gem_object_unpin(obj);
3260 target_obj_priv = to_intel_bo(target_obj);
3263 DRM_INFO("%s: obj %p offset %08x target %d "
3264 "read %08x write %08x gtt %08x "
3265 "presumed %08x delta %08x\n",
3268 (int) reloc->offset,
3269 (int) reloc->target_handle,
3270 (int) reloc->read_domains,
3271 (int) reloc->write_domain,
3272 (int) target_obj_priv->gtt_offset,
3273 (int) reloc->presumed_offset,
3277 /* The target buffer should have appeared before us in the
3278 * exec_object list, so it should have a GTT space bound by now.
3280 if (target_obj_priv->gtt_space == NULL) {
3281 DRM_ERROR("No GTT space found for object %d\n",
3282 reloc->target_handle);
3283 drm_gem_object_unreference(target_obj);
3284 i915_gem_object_unpin(obj);
3288 /* Validate that the target is in a valid r/w GPU domain */
3289 if (reloc->write_domain & (reloc->write_domain - 1)) {
3290 DRM_ERROR("reloc with multiple write domains: "
3291 "obj %p target %d offset %d "
3292 "read %08x write %08x",
3293 obj, reloc->target_handle,
3294 (int) reloc->offset,
3295 reloc->read_domains,
3296 reloc->write_domain);
3299 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3300 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3301 DRM_ERROR("reloc with read/write CPU domains: "
3302 "obj %p target %d offset %d "
3303 "read %08x write %08x",
3304 obj, reloc->target_handle,
3305 (int) reloc->offset,
3306 reloc->read_domains,
3307 reloc->write_domain);
3308 drm_gem_object_unreference(target_obj);
3309 i915_gem_object_unpin(obj);
3312 if (reloc->write_domain && target_obj->pending_write_domain &&
3313 reloc->write_domain != target_obj->pending_write_domain) {
3314 DRM_ERROR("Write domain conflict: "
3315 "obj %p target %d offset %d "
3316 "new %08x old %08x\n",
3317 obj, reloc->target_handle,
3318 (int) reloc->offset,
3319 reloc->write_domain,
3320 target_obj->pending_write_domain);
3321 drm_gem_object_unreference(target_obj);
3322 i915_gem_object_unpin(obj);
3326 target_obj->pending_read_domains |= reloc->read_domains;
3327 target_obj->pending_write_domain |= reloc->write_domain;
3329 /* If the relocation already has the right value in it, no
3330 * more work needs to be done.
3332 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3333 drm_gem_object_unreference(target_obj);
3337 /* Check that the relocation address is valid... */
3338 if (reloc->offset > obj->size - 4) {
3339 DRM_ERROR("Relocation beyond object bounds: "
3340 "obj %p target %d offset %d size %d.\n",
3341 obj, reloc->target_handle,
3342 (int) reloc->offset, (int) obj->size);
3343 drm_gem_object_unreference(target_obj);
3344 i915_gem_object_unpin(obj);
3347 if (reloc->offset & 3) {
3348 DRM_ERROR("Relocation not 4-byte aligned: "
3349 "obj %p target %d offset %d.\n",
3350 obj, reloc->target_handle,
3351 (int) reloc->offset);
3352 drm_gem_object_unreference(target_obj);
3353 i915_gem_object_unpin(obj);
3357 /* and points to somewhere within the target object. */
3358 if (reloc->delta >= target_obj->size) {
3359 DRM_ERROR("Relocation beyond target object bounds: "
3360 "obj %p target %d delta %d size %d.\n",
3361 obj, reloc->target_handle,
3362 (int) reloc->delta, (int) target_obj->size);
3363 drm_gem_object_unreference(target_obj);
3364 i915_gem_object_unpin(obj);
3368 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3370 drm_gem_object_unreference(target_obj);
3371 i915_gem_object_unpin(obj);
3375 /* Map the page containing the relocation we're going to
3378 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3379 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3382 reloc_entry = (uint32_t __iomem *)(reloc_page +
3383 (reloc_offset & (PAGE_SIZE - 1)));
3384 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3387 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3388 obj, (unsigned int) reloc->offset,
3389 readl(reloc_entry), reloc_val);
3391 writel(reloc_val, reloc_entry);
3392 io_mapping_unmap_atomic(reloc_page);
3394 /* The updated presumed offset for this entry will be
3395 * copied back out to the user.
3397 reloc->presumed_offset = target_obj_priv->gtt_offset;
3399 drm_gem_object_unreference(target_obj);
3404 i915_gem_dump_object(obj, 128, __func__, ~0);
3409 /* Throttle our rendering by waiting until the ring has completed our requests
3410 * emitted over 20 msec ago.
3412 * Note that if we were to use the current jiffies each time around the loop,
3413 * we wouldn't escape the function with any frames outstanding if the time to
3414 * render a frame was over 20ms.
3416 * This should get us reasonable parallelism between CPU and GPU but also
3417 * relatively low latency when blocking on a particular request to finish.
3420 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3422 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3424 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3426 mutex_lock(&dev->struct_mutex);
3427 while (!list_empty(&i915_file_priv->mm.request_list)) {
3428 struct drm_i915_gem_request *request;
3430 request = list_first_entry(&i915_file_priv->mm.request_list,
3431 struct drm_i915_gem_request,
3434 if (time_after_eq(request->emitted_jiffies, recent_enough))
3437 ret = i915_wait_request(dev, request->seqno);
3441 mutex_unlock(&dev->struct_mutex);
3447 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3448 uint32_t buffer_count,
3449 struct drm_i915_gem_relocation_entry **relocs)
3451 uint32_t reloc_count = 0, reloc_index = 0, i;
3455 for (i = 0; i < buffer_count; i++) {
3456 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3458 reloc_count += exec_list[i].relocation_count;
3461 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3462 if (*relocs == NULL) {
3463 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3467 for (i = 0; i < buffer_count; i++) {
3468 struct drm_i915_gem_relocation_entry __user *user_relocs;
3470 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3472 ret = copy_from_user(&(*relocs)[reloc_index],
3474 exec_list[i].relocation_count *
3477 drm_free_large(*relocs);
3482 reloc_index += exec_list[i].relocation_count;
3489 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3490 uint32_t buffer_count,
3491 struct drm_i915_gem_relocation_entry *relocs)
3493 uint32_t reloc_count = 0, i;
3499 for (i = 0; i < buffer_count; i++) {
3500 struct drm_i915_gem_relocation_entry __user *user_relocs;
3503 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3505 unwritten = copy_to_user(user_relocs,
3506 &relocs[reloc_count],
3507 exec_list[i].relocation_count *
3515 reloc_count += exec_list[i].relocation_count;
3519 drm_free_large(relocs);
3525 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3526 uint64_t exec_offset)
3528 uint32_t exec_start, exec_len;
3530 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3531 exec_len = (uint32_t) exec->batch_len;
3533 if ((exec_start | exec_len) & 0x7)
3543 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3544 struct drm_gem_object **object_list,
3547 drm_i915_private_t *dev_priv = dev->dev_private;
3548 struct drm_i915_gem_object *obj_priv;
3553 prepare_to_wait(&dev_priv->pending_flip_queue,
3554 &wait, TASK_INTERRUPTIBLE);
3555 for (i = 0; i < count; i++) {
3556 obj_priv = to_intel_bo(object_list[i]);
3557 if (atomic_read(&obj_priv->pending_flip) > 0)
3563 if (!signal_pending(current)) {
3564 mutex_unlock(&dev->struct_mutex);
3566 mutex_lock(&dev->struct_mutex);
3572 finish_wait(&dev_priv->pending_flip_queue, &wait);
3578 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3579 struct drm_file *file_priv,
3580 struct drm_i915_gem_execbuffer2 *args,
3581 struct drm_i915_gem_exec_object2 *exec_list)
3583 drm_i915_private_t *dev_priv = dev->dev_private;
3584 struct drm_gem_object **object_list = NULL;
3585 struct drm_gem_object *batch_obj;
3586 struct drm_i915_gem_object *obj_priv;
3587 struct drm_clip_rect *cliprects = NULL;
3588 struct drm_i915_gem_relocation_entry *relocs = NULL;
3589 int ret = 0, ret2, i, pinned = 0;
3590 uint64_t exec_offset;
3591 uint32_t seqno, flush_domains, reloc_index;
3592 int pin_tries, flips;
3595 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3596 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3599 if (args->buffer_count < 1) {
3600 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3603 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3604 if (object_list == NULL) {
3605 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3606 args->buffer_count);
3611 if (args->num_cliprects != 0) {
3612 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3614 if (cliprects == NULL) {
3619 ret = copy_from_user(cliprects,
3620 (struct drm_clip_rect __user *)
3621 (uintptr_t) args->cliprects_ptr,
3622 sizeof(*cliprects) * args->num_cliprects);
3624 DRM_ERROR("copy %d cliprects failed: %d\n",
3625 args->num_cliprects, ret);
3630 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3635 mutex_lock(&dev->struct_mutex);
3637 i915_verify_inactive(dev, __FILE__, __LINE__);
3639 if (atomic_read(&dev_priv->mm.wedged)) {
3640 mutex_unlock(&dev->struct_mutex);
3645 if (dev_priv->mm.suspended) {
3646 mutex_unlock(&dev->struct_mutex);
3651 /* Look up object handles */
3653 for (i = 0; i < args->buffer_count; i++) {
3654 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3655 exec_list[i].handle);
3656 if (object_list[i] == NULL) {
3657 DRM_ERROR("Invalid object handle %d at index %d\n",
3658 exec_list[i].handle, i);
3659 /* prevent error path from reading uninitialized data */
3660 args->buffer_count = i + 1;
3665 obj_priv = to_intel_bo(object_list[i]);
3666 if (obj_priv->in_execbuffer) {
3667 DRM_ERROR("Object %p appears more than once in object list\n",
3669 /* prevent error path from reading uninitialized data */
3670 args->buffer_count = i + 1;
3674 obj_priv->in_execbuffer = true;
3675 flips += atomic_read(&obj_priv->pending_flip);
3679 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3680 args->buffer_count);
3685 /* Pin and relocate */
3686 for (pin_tries = 0; ; pin_tries++) {
3690 for (i = 0; i < args->buffer_count; i++) {
3691 object_list[i]->pending_read_domains = 0;
3692 object_list[i]->pending_write_domain = 0;
3693 ret = i915_gem_object_pin_and_relocate(object_list[i],
3696 &relocs[reloc_index]);
3700 reloc_index += exec_list[i].relocation_count;
3706 /* error other than GTT full, or we've already tried again */
3707 if (ret != -ENOSPC || pin_tries >= 1) {
3708 if (ret != -ERESTARTSYS) {
3709 unsigned long long total_size = 0;
3710 for (i = 0; i < args->buffer_count; i++)
3711 total_size += object_list[i]->size;
3712 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3713 pinned+1, args->buffer_count,
3715 DRM_ERROR("%d objects [%d pinned], "
3716 "%d object bytes [%d pinned], "
3717 "%d/%d gtt bytes\n",
3718 atomic_read(&dev->object_count),
3719 atomic_read(&dev->pin_count),
3720 atomic_read(&dev->object_memory),
3721 atomic_read(&dev->pin_memory),
3722 atomic_read(&dev->gtt_memory),
3728 /* unpin all of our buffers */
3729 for (i = 0; i < pinned; i++)
3730 i915_gem_object_unpin(object_list[i]);
3733 /* evict everyone we can from the aperture */
3734 ret = i915_gem_evict_everything(dev);
3735 if (ret && ret != -ENOSPC)
3739 /* Set the pending read domains for the batch buffer to COMMAND */
3740 batch_obj = object_list[args->buffer_count-1];
3741 if (batch_obj->pending_write_domain) {
3742 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3746 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3748 /* Sanity check the batch buffer, prior to moving objects */
3749 exec_offset = exec_list[args->buffer_count - 1].offset;
3750 ret = i915_gem_check_execbuffer (args, exec_offset);
3752 DRM_ERROR("execbuf with invalid offset/length\n");
3756 i915_verify_inactive(dev, __FILE__, __LINE__);
3758 /* Zero the global flush/invalidate flags. These
3759 * will be modified as new domains are computed
3762 dev->invalidate_domains = 0;
3763 dev->flush_domains = 0;
3765 for (i = 0; i < args->buffer_count; i++) {
3766 struct drm_gem_object *obj = object_list[i];
3768 /* Compute new gpu domains and update invalidate/flush */
3769 i915_gem_object_set_to_gpu_domain(obj);
3772 i915_verify_inactive(dev, __FILE__, __LINE__);
3774 if (dev->invalidate_domains | dev->flush_domains) {
3776 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3778 dev->invalidate_domains,
3779 dev->flush_domains);
3782 dev->invalidate_domains,
3783 dev->flush_domains);
3784 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3785 (void)i915_add_request(dev, file_priv,
3786 dev->flush_domains);
3789 for (i = 0; i < args->buffer_count; i++) {
3790 struct drm_gem_object *obj = object_list[i];
3791 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3792 uint32_t old_write_domain = obj->write_domain;
3794 obj->write_domain = obj->pending_write_domain;
3795 if (obj->write_domain)
3796 list_move_tail(&obj_priv->gpu_write_list,
3797 &dev_priv->mm.gpu_write_list);
3799 list_del_init(&obj_priv->gpu_write_list);
3801 trace_i915_gem_object_change_domain(obj,
3806 i915_verify_inactive(dev, __FILE__, __LINE__);
3809 for (i = 0; i < args->buffer_count; i++) {
3810 i915_gem_object_check_coherency(object_list[i],
3811 exec_list[i].handle);
3816 i915_gem_dump_object(batch_obj,
3822 /* Exec the batchbuffer */
3823 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3825 DRM_ERROR("dispatch failed %d\n", ret);
3830 * Ensure that the commands in the batch buffer are
3831 * finished before the interrupt fires
3833 flush_domains = i915_retire_commands(dev);
3835 i915_verify_inactive(dev, __FILE__, __LINE__);
3838 * Get a seqno representing the execution of the current buffer,
3839 * which we can wait on. We would like to mitigate these interrupts,
3840 * likely by only creating seqnos occasionally (so that we have
3841 * *some* interrupts representing completion of buffers that we can
3842 * wait on when trying to clear up gtt space).
3844 seqno = i915_add_request(dev, file_priv, flush_domains);
3846 for (i = 0; i < args->buffer_count; i++) {
3847 struct drm_gem_object *obj = object_list[i];
3849 i915_gem_object_move_to_active(obj, seqno);
3851 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3855 i915_dump_lru(dev, __func__);
3858 i915_verify_inactive(dev, __FILE__, __LINE__);
3861 for (i = 0; i < pinned; i++)
3862 i915_gem_object_unpin(object_list[i]);
3864 for (i = 0; i < args->buffer_count; i++) {
3865 if (object_list[i]) {
3866 obj_priv = to_intel_bo(object_list[i]);
3867 obj_priv->in_execbuffer = false;
3869 drm_gem_object_unreference(object_list[i]);
3872 mutex_unlock(&dev->struct_mutex);
3875 /* Copy the updated relocations out regardless of current error
3876 * state. Failure to update the relocs would mean that the next
3877 * time userland calls execbuf, it would do so with presumed offset
3878 * state that didn't match the actual object state.
3880 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3883 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3889 drm_free_large(object_list);
3896 * Legacy execbuffer just creates an exec2 list from the original exec object
3897 * list array and passes it to the real function.
3900 i915_gem_execbuffer(struct drm_device *dev, void *data,
3901 struct drm_file *file_priv)
3903 struct drm_i915_gem_execbuffer *args = data;
3904 struct drm_i915_gem_execbuffer2 exec2;
3905 struct drm_i915_gem_exec_object *exec_list = NULL;
3906 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3910 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3911 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3914 if (args->buffer_count < 1) {
3915 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3919 /* Copy in the exec list from userland */
3920 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3921 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3922 if (exec_list == NULL || exec2_list == NULL) {
3923 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3924 args->buffer_count);
3925 drm_free_large(exec_list);
3926 drm_free_large(exec2_list);
3929 ret = copy_from_user(exec_list,
3930 (struct drm_i915_relocation_entry __user *)
3931 (uintptr_t) args->buffers_ptr,
3932 sizeof(*exec_list) * args->buffer_count);
3934 DRM_ERROR("copy %d exec entries failed %d\n",
3935 args->buffer_count, ret);
3936 drm_free_large(exec_list);
3937 drm_free_large(exec2_list);
3941 for (i = 0; i < args->buffer_count; i++) {
3942 exec2_list[i].handle = exec_list[i].handle;
3943 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3944 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3945 exec2_list[i].alignment = exec_list[i].alignment;
3946 exec2_list[i].offset = exec_list[i].offset;
3948 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3950 exec2_list[i].flags = 0;
3953 exec2.buffers_ptr = args->buffers_ptr;
3954 exec2.buffer_count = args->buffer_count;
3955 exec2.batch_start_offset = args->batch_start_offset;
3956 exec2.batch_len = args->batch_len;
3957 exec2.DR1 = args->DR1;
3958 exec2.DR4 = args->DR4;
3959 exec2.num_cliprects = args->num_cliprects;
3960 exec2.cliprects_ptr = args->cliprects_ptr;
3963 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3965 /* Copy the new buffer offsets back to the user's exec list. */
3966 for (i = 0; i < args->buffer_count; i++)
3967 exec_list[i].offset = exec2_list[i].offset;
3968 /* ... and back out to userspace */
3969 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3970 (uintptr_t) args->buffers_ptr,
3972 sizeof(*exec_list) * args->buffer_count);
3975 DRM_ERROR("failed to copy %d exec entries "
3976 "back to user (%d)\n",
3977 args->buffer_count, ret);
3981 drm_free_large(exec_list);
3982 drm_free_large(exec2_list);
3987 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3988 struct drm_file *file_priv)
3990 struct drm_i915_gem_execbuffer2 *args = data;
3991 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3995 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3996 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3999 if (args->buffer_count < 1) {
4000 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4004 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4005 if (exec2_list == NULL) {
4006 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4007 args->buffer_count);
4010 ret = copy_from_user(exec2_list,
4011 (struct drm_i915_relocation_entry __user *)
4012 (uintptr_t) args->buffers_ptr,
4013 sizeof(*exec2_list) * args->buffer_count);
4015 DRM_ERROR("copy %d exec entries failed %d\n",
4016 args->buffer_count, ret);
4017 drm_free_large(exec2_list);
4021 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4023 /* Copy the new buffer offsets back to the user's exec list. */
4024 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4025 (uintptr_t) args->buffers_ptr,
4027 sizeof(*exec2_list) * args->buffer_count);
4030 DRM_ERROR("failed to copy %d exec entries "
4031 "back to user (%d)\n",
4032 args->buffer_count, ret);
4036 drm_free_large(exec2_list);
4041 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4043 struct drm_device *dev = obj->dev;
4044 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4047 i915_verify_inactive(dev, __FILE__, __LINE__);
4048 if (obj_priv->gtt_space == NULL) {
4049 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4054 obj_priv->pin_count++;
4056 /* If the object is not active and not pending a flush,
4057 * remove it from the inactive list
4059 if (obj_priv->pin_count == 1) {
4060 atomic_inc(&dev->pin_count);
4061 atomic_add(obj->size, &dev->pin_memory);
4062 if (!obj_priv->active &&
4063 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4064 !list_empty(&obj_priv->list))
4065 list_del_init(&obj_priv->list);
4067 i915_verify_inactive(dev, __FILE__, __LINE__);
4073 i915_gem_object_unpin(struct drm_gem_object *obj)
4075 struct drm_device *dev = obj->dev;
4076 drm_i915_private_t *dev_priv = dev->dev_private;
4077 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4079 i915_verify_inactive(dev, __FILE__, __LINE__);
4080 obj_priv->pin_count--;
4081 BUG_ON(obj_priv->pin_count < 0);
4082 BUG_ON(obj_priv->gtt_space == NULL);
4084 /* If the object is no longer pinned, and is
4085 * neither active nor being flushed, then stick it on
4088 if (obj_priv->pin_count == 0) {
4089 if (!obj_priv->active &&
4090 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4091 list_move_tail(&obj_priv->list,
4092 &dev_priv->mm.inactive_list);
4093 atomic_dec(&dev->pin_count);
4094 atomic_sub(obj->size, &dev->pin_memory);
4096 i915_verify_inactive(dev, __FILE__, __LINE__);
4100 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4101 struct drm_file *file_priv)
4103 struct drm_i915_gem_pin *args = data;
4104 struct drm_gem_object *obj;
4105 struct drm_i915_gem_object *obj_priv;
4108 mutex_lock(&dev->struct_mutex);
4110 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4112 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4114 mutex_unlock(&dev->struct_mutex);
4117 obj_priv = to_intel_bo(obj);
4119 if (obj_priv->madv != I915_MADV_WILLNEED) {
4120 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4121 drm_gem_object_unreference(obj);
4122 mutex_unlock(&dev->struct_mutex);
4126 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4127 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4129 drm_gem_object_unreference(obj);
4130 mutex_unlock(&dev->struct_mutex);
4134 obj_priv->user_pin_count++;
4135 obj_priv->pin_filp = file_priv;
4136 if (obj_priv->user_pin_count == 1) {
4137 ret = i915_gem_object_pin(obj, args->alignment);
4139 drm_gem_object_unreference(obj);
4140 mutex_unlock(&dev->struct_mutex);
4145 /* XXX - flush the CPU caches for pinned objects
4146 * as the X server doesn't manage domains yet
4148 i915_gem_object_flush_cpu_write_domain(obj);
4149 args->offset = obj_priv->gtt_offset;
4150 drm_gem_object_unreference(obj);
4151 mutex_unlock(&dev->struct_mutex);
4157 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4158 struct drm_file *file_priv)
4160 struct drm_i915_gem_pin *args = data;
4161 struct drm_gem_object *obj;
4162 struct drm_i915_gem_object *obj_priv;
4164 mutex_lock(&dev->struct_mutex);
4166 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4168 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4170 mutex_unlock(&dev->struct_mutex);
4174 obj_priv = to_intel_bo(obj);
4175 if (obj_priv->pin_filp != file_priv) {
4176 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4178 drm_gem_object_unreference(obj);
4179 mutex_unlock(&dev->struct_mutex);
4182 obj_priv->user_pin_count--;
4183 if (obj_priv->user_pin_count == 0) {
4184 obj_priv->pin_filp = NULL;
4185 i915_gem_object_unpin(obj);
4188 drm_gem_object_unreference(obj);
4189 mutex_unlock(&dev->struct_mutex);
4194 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4195 struct drm_file *file_priv)
4197 struct drm_i915_gem_busy *args = data;
4198 struct drm_gem_object *obj;
4199 struct drm_i915_gem_object *obj_priv;
4201 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4203 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4208 mutex_lock(&dev->struct_mutex);
4209 /* Update the active list for the hardware's current position.
4210 * Otherwise this only updates on a delayed timer or when irqs are
4211 * actually unmasked, and our working set ends up being larger than
4214 i915_gem_retire_requests(dev);
4216 obj_priv = to_intel_bo(obj);
4217 /* Don't count being on the flushing list against the object being
4218 * done. Otherwise, a buffer left on the flushing list but not getting
4219 * flushed (because nobody's flushing that domain) won't ever return
4220 * unbusy and get reused by libdrm's bo cache. The other expected
4221 * consumer of this interface, OpenGL's occlusion queries, also specs
4222 * that the objects get unbusy "eventually" without any interference.
4224 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4226 drm_gem_object_unreference(obj);
4227 mutex_unlock(&dev->struct_mutex);
4232 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4233 struct drm_file *file_priv)
4235 return i915_gem_ring_throttle(dev, file_priv);
4239 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4240 struct drm_file *file_priv)
4242 struct drm_i915_gem_madvise *args = data;
4243 struct drm_gem_object *obj;
4244 struct drm_i915_gem_object *obj_priv;
4246 switch (args->madv) {
4247 case I915_MADV_DONTNEED:
4248 case I915_MADV_WILLNEED:
4254 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4256 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4261 mutex_lock(&dev->struct_mutex);
4262 obj_priv = to_intel_bo(obj);
4264 if (obj_priv->pin_count) {
4265 drm_gem_object_unreference(obj);
4266 mutex_unlock(&dev->struct_mutex);
4268 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4272 if (obj_priv->madv != __I915_MADV_PURGED)
4273 obj_priv->madv = args->madv;
4275 /* if the object is no longer bound, discard its backing storage */
4276 if (i915_gem_object_is_purgeable(obj_priv) &&
4277 obj_priv->gtt_space == NULL)
4278 i915_gem_object_truncate(obj);
4280 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4282 drm_gem_object_unreference(obj);
4283 mutex_unlock(&dev->struct_mutex);
4288 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4291 struct drm_i915_gem_object *obj;
4293 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4297 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4302 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4303 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4305 obj->agp_type = AGP_USER_MEMORY;
4306 obj->base.driver_private = NULL;
4307 obj->fence_reg = I915_FENCE_REG_NONE;
4308 INIT_LIST_HEAD(&obj->list);
4309 INIT_LIST_HEAD(&obj->gpu_write_list);
4310 obj->madv = I915_MADV_WILLNEED;
4312 trace_i915_gem_object_create(&obj->base);
4317 int i915_gem_init_object(struct drm_gem_object *obj)
4324 void i915_gem_free_object(struct drm_gem_object *obj)
4326 struct drm_device *dev = obj->dev;
4327 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4329 trace_i915_gem_object_destroy(obj);
4331 while (obj_priv->pin_count > 0)
4332 i915_gem_object_unpin(obj);
4334 if (obj_priv->phys_obj)
4335 i915_gem_detach_phys_object(dev, obj);
4337 i915_gem_object_unbind(obj);
4339 if (obj_priv->mmap_offset)
4340 i915_gem_free_mmap_offset(obj);
4342 drm_gem_object_release(obj);
4344 kfree(obj_priv->page_cpu_valid);
4345 kfree(obj_priv->bit_17);
4349 /** Unbinds all inactive objects. */
4351 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4353 drm_i915_private_t *dev_priv = dev->dev_private;
4355 while (!list_empty(&dev_priv->mm.inactive_list)) {
4356 struct drm_gem_object *obj;
4359 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4360 struct drm_i915_gem_object,
4363 ret = i915_gem_object_unbind(obj);
4365 DRM_ERROR("Error unbinding object: %d\n", ret);
4374 i915_gem_idle(struct drm_device *dev)
4376 drm_i915_private_t *dev_priv = dev->dev_private;
4379 mutex_lock(&dev->struct_mutex);
4381 if (dev_priv->mm.suspended || dev_priv->render_ring.ring_obj == NULL) {
4382 mutex_unlock(&dev->struct_mutex);
4386 ret = i915_gpu_idle(dev);
4388 mutex_unlock(&dev->struct_mutex);
4392 /* Under UMS, be paranoid and evict. */
4393 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4394 ret = i915_gem_evict_from_inactive_list(dev);
4396 mutex_unlock(&dev->struct_mutex);
4401 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4402 * We need to replace this with a semaphore, or something.
4403 * And not confound mm.suspended!
4405 dev_priv->mm.suspended = 1;
4406 del_timer(&dev_priv->hangcheck_timer);
4408 i915_kernel_lost_context(dev);
4409 i915_gem_cleanup_ringbuffer(dev);
4411 mutex_unlock(&dev->struct_mutex);
4413 /* Cancel the retire work handler, which should be idle now. */
4414 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4420 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4421 * over cache flushing.
4424 i915_gem_init_pipe_control(struct drm_device *dev)
4426 drm_i915_private_t *dev_priv = dev->dev_private;
4427 struct drm_gem_object *obj;
4428 struct drm_i915_gem_object *obj_priv;
4431 obj = i915_gem_alloc_object(dev, 4096);
4433 DRM_ERROR("Failed to allocate seqno page\n");
4437 obj_priv = to_intel_bo(obj);
4438 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4440 ret = i915_gem_object_pin(obj, 4096);
4444 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4445 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4446 if (dev_priv->seqno_page == NULL)
4449 dev_priv->seqno_obj = obj;
4450 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4455 i915_gem_object_unpin(obj);
4457 drm_gem_object_unreference(obj);
4463 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4465 drm_i915_private_t *dev_priv = dev->dev_private;
4466 struct drm_gem_object *obj;
4467 struct drm_i915_gem_object *obj_priv;
4469 obj = dev_priv->seqno_obj;
4470 obj_priv = to_intel_bo(obj);
4471 kunmap(obj_priv->pages[0]);
4472 i915_gem_object_unpin(obj);
4473 drm_gem_object_unreference(obj);
4474 dev_priv->seqno_obj = NULL;
4476 dev_priv->seqno_page = NULL;
4480 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4481 struct drm_file *file_priv)
4483 drm_i915_private_t *dev_priv = dev->dev_private;
4486 if (drm_core_check_feature(dev, DRIVER_MODESET))
4489 if (atomic_read(&dev_priv->mm.wedged)) {
4490 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4491 atomic_set(&dev_priv->mm.wedged, 0);
4494 mutex_lock(&dev->struct_mutex);
4495 dev_priv->mm.suspended = 0;
4497 ret = i915_gem_init_ringbuffer(dev);
4499 mutex_unlock(&dev->struct_mutex);
4503 spin_lock(&dev_priv->mm.active_list_lock);
4504 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4505 spin_unlock(&dev_priv->mm.active_list_lock);
4507 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4508 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4509 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4510 mutex_unlock(&dev->struct_mutex);
4512 drm_irq_install(dev);
4518 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4519 struct drm_file *file_priv)
4521 if (drm_core_check_feature(dev, DRIVER_MODESET))
4524 drm_irq_uninstall(dev);
4525 return i915_gem_idle(dev);
4529 i915_gem_lastclose(struct drm_device *dev)
4533 if (drm_core_check_feature(dev, DRIVER_MODESET))
4536 ret = i915_gem_idle(dev);
4538 DRM_ERROR("failed to idle hardware: %d\n", ret);
4542 i915_gem_load(struct drm_device *dev)
4545 drm_i915_private_t *dev_priv = dev->dev_private;
4547 spin_lock_init(&dev_priv->mm.active_list_lock);
4548 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4549 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4550 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4551 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4552 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4553 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4554 for (i = 0; i < 16; i++)
4555 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4556 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4557 i915_gem_retire_work_handler);
4558 dev_priv->mm.next_gem_seqno = 1;
4560 spin_lock(&shrink_list_lock);
4561 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4562 spin_unlock(&shrink_list_lock);
4564 /* Old X drivers will take 0-2 for front, back, depth buffers */
4565 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4566 dev_priv->fence_reg_start = 3;
4568 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4569 dev_priv->num_fence_regs = 16;
4571 dev_priv->num_fence_regs = 8;
4573 /* Initialize fence registers to zero */
4574 if (IS_I965G(dev)) {
4575 for (i = 0; i < 16; i++)
4576 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4578 for (i = 0; i < 8; i++)
4579 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4580 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4581 for (i = 0; i < 8; i++)
4582 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4584 i915_gem_detect_bit_6_swizzle(dev);
4585 init_waitqueue_head(&dev_priv->pending_flip_queue);
4589 * Create a physically contiguous memory object for this object
4590 * e.g. for cursor + overlay regs
4592 int i915_gem_init_phys_object(struct drm_device *dev,
4595 drm_i915_private_t *dev_priv = dev->dev_private;
4596 struct drm_i915_gem_phys_object *phys_obj;
4599 if (dev_priv->mm.phys_objs[id - 1] || !size)
4602 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4608 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4609 if (!phys_obj->handle) {
4614 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4617 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4625 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4627 drm_i915_private_t *dev_priv = dev->dev_private;
4628 struct drm_i915_gem_phys_object *phys_obj;
4630 if (!dev_priv->mm.phys_objs[id - 1])
4633 phys_obj = dev_priv->mm.phys_objs[id - 1];
4634 if (phys_obj->cur_obj) {
4635 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4639 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4641 drm_pci_free(dev, phys_obj->handle);
4643 dev_priv->mm.phys_objs[id - 1] = NULL;
4646 void i915_gem_free_all_phys_object(struct drm_device *dev)
4650 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4651 i915_gem_free_phys_object(dev, i);
4654 void i915_gem_detach_phys_object(struct drm_device *dev,
4655 struct drm_gem_object *obj)
4657 struct drm_i915_gem_object *obj_priv;
4662 obj_priv = to_intel_bo(obj);
4663 if (!obj_priv->phys_obj)
4666 ret = i915_gem_object_get_pages(obj, 0);
4670 page_count = obj->size / PAGE_SIZE;
4672 for (i = 0; i < page_count; i++) {
4673 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4674 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4676 memcpy(dst, src, PAGE_SIZE);
4677 kunmap_atomic(dst, KM_USER0);
4679 drm_clflush_pages(obj_priv->pages, page_count);
4680 drm_agp_chipset_flush(dev);
4682 i915_gem_object_put_pages(obj);
4684 obj_priv->phys_obj->cur_obj = NULL;
4685 obj_priv->phys_obj = NULL;
4689 i915_gem_attach_phys_object(struct drm_device *dev,
4690 struct drm_gem_object *obj, int id)
4692 drm_i915_private_t *dev_priv = dev->dev_private;
4693 struct drm_i915_gem_object *obj_priv;
4698 if (id > I915_MAX_PHYS_OBJECT)
4701 obj_priv = to_intel_bo(obj);
4703 if (obj_priv->phys_obj) {
4704 if (obj_priv->phys_obj->id == id)
4706 i915_gem_detach_phys_object(dev, obj);
4710 /* create a new object */
4711 if (!dev_priv->mm.phys_objs[id - 1]) {
4712 ret = i915_gem_init_phys_object(dev, id,
4715 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4720 /* bind to the object */
4721 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4722 obj_priv->phys_obj->cur_obj = obj;
4724 ret = i915_gem_object_get_pages(obj, 0);
4726 DRM_ERROR("failed to get page list\n");
4730 page_count = obj->size / PAGE_SIZE;
4732 for (i = 0; i < page_count; i++) {
4733 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4734 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4736 memcpy(dst, src, PAGE_SIZE);
4737 kunmap_atomic(src, KM_USER0);
4740 i915_gem_object_put_pages(obj);
4748 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4749 struct drm_i915_gem_pwrite *args,
4750 struct drm_file *file_priv)
4752 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4755 char __user *user_data;
4757 user_data = (char __user *) (uintptr_t) args->data_ptr;
4758 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4760 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4761 ret = copy_from_user(obj_addr, user_data, args->size);
4765 drm_agp_chipset_flush(dev);
4769 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4771 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4773 /* Clean up our request list when the client is going away, so that
4774 * later retire_requests won't dereference our soon-to-be-gone
4777 mutex_lock(&dev->struct_mutex);
4778 while (!list_empty(&i915_file_priv->mm.request_list))
4779 list_del_init(i915_file_priv->mm.request_list.next);
4780 mutex_unlock(&dev->struct_mutex);
4784 i915_gpu_is_active(struct drm_device *dev)
4786 drm_i915_private_t *dev_priv = dev->dev_private;
4789 spin_lock(&dev_priv->mm.active_list_lock);
4790 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4791 list_empty(&dev_priv->mm.active_list);
4792 spin_unlock(&dev_priv->mm.active_list_lock);
4794 return !lists_empty;
4798 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4800 drm_i915_private_t *dev_priv, *next_dev;
4801 struct drm_i915_gem_object *obj_priv, *next_obj;
4803 int would_deadlock = 1;
4805 /* "fast-path" to count number of available objects */
4806 if (nr_to_scan == 0) {
4807 spin_lock(&shrink_list_lock);
4808 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4809 struct drm_device *dev = dev_priv->dev;
4811 if (mutex_trylock(&dev->struct_mutex)) {
4812 list_for_each_entry(obj_priv,
4813 &dev_priv->mm.inactive_list,
4816 mutex_unlock(&dev->struct_mutex);
4819 spin_unlock(&shrink_list_lock);
4821 return (cnt / 100) * sysctl_vfs_cache_pressure;
4824 spin_lock(&shrink_list_lock);
4827 /* first scan for clean buffers */
4828 list_for_each_entry_safe(dev_priv, next_dev,
4829 &shrink_list, mm.shrink_list) {
4830 struct drm_device *dev = dev_priv->dev;
4832 if (! mutex_trylock(&dev->struct_mutex))
4835 spin_unlock(&shrink_list_lock);
4837 i915_gem_retire_requests(dev);
4839 list_for_each_entry_safe(obj_priv, next_obj,
4840 &dev_priv->mm.inactive_list,
4842 if (i915_gem_object_is_purgeable(obj_priv)) {
4843 i915_gem_object_unbind(&obj_priv->base);
4844 if (--nr_to_scan <= 0)
4849 spin_lock(&shrink_list_lock);
4850 mutex_unlock(&dev->struct_mutex);
4854 if (nr_to_scan <= 0)
4858 /* second pass, evict/count anything still on the inactive list */
4859 list_for_each_entry_safe(dev_priv, next_dev,
4860 &shrink_list, mm.shrink_list) {
4861 struct drm_device *dev = dev_priv->dev;
4863 if (! mutex_trylock(&dev->struct_mutex))
4866 spin_unlock(&shrink_list_lock);
4868 list_for_each_entry_safe(obj_priv, next_obj,
4869 &dev_priv->mm.inactive_list,
4871 if (nr_to_scan > 0) {
4872 i915_gem_object_unbind(&obj_priv->base);
4878 spin_lock(&shrink_list_lock);
4879 mutex_unlock(&dev->struct_mutex);
4888 * We are desperate for pages, so as a last resort, wait
4889 * for the GPU to finish and discard whatever we can.
4890 * This has a dramatic impact to reduce the number of
4891 * OOM-killer events whilst running the GPU aggressively.
4893 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4894 struct drm_device *dev = dev_priv->dev;
4896 if (!mutex_trylock(&dev->struct_mutex))
4899 spin_unlock(&shrink_list_lock);
4901 if (i915_gpu_is_active(dev)) {
4906 spin_lock(&shrink_list_lock);
4907 mutex_unlock(&dev->struct_mutex);
4914 spin_unlock(&shrink_list_lock);
4919 return (cnt / 100) * sysctl_vfs_cache_pressure;
4924 static struct shrinker shrinker = {
4925 .shrink = i915_gem_shrink,
4926 .seeks = DEFAULT_SEEKS,
4930 i915_gem_shrinker_init(void)
4932 register_shrinker(&shrinker);
4936 i915_gem_shrinker_exit(void)
4938 unregister_shrinker(&shrinker);