2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
40 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
43 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
45 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
49 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
50 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
53 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
54 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
55 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
56 struct drm_i915_gem_pwrite *args,
57 struct drm_file *file_priv);
59 static LIST_HEAD(shrink_list);
60 static DEFINE_SPINLOCK(shrink_list_lock);
62 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
65 drm_i915_private_t *dev_priv = dev->dev_private;
68 (start & (PAGE_SIZE - 1)) != 0 ||
69 (end & (PAGE_SIZE - 1)) != 0) {
73 drm_mm_init(&dev_priv->mm.gtt_space, start,
76 dev->gtt_total = (uint32_t) (end - start);
82 i915_gem_init_ioctl(struct drm_device *dev, void *data,
83 struct drm_file *file_priv)
85 struct drm_i915_gem_init *args = data;
88 mutex_lock(&dev->struct_mutex);
89 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
90 mutex_unlock(&dev->struct_mutex);
96 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
97 struct drm_file *file_priv)
99 struct drm_i915_gem_get_aperture *args = data;
101 if (!(dev->driver->driver_features & DRIVER_GEM))
104 args->aper_size = dev->gtt_total;
105 args->aper_available_size = (args->aper_size -
106 atomic_read(&dev->pin_memory));
113 * Creates a new mm object and returns a handle to it.
116 i915_gem_create_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv)
119 struct drm_i915_gem_create *args = data;
120 struct drm_gem_object *obj;
124 args->size = roundup(args->size, PAGE_SIZE);
126 /* Allocate the new object */
127 obj = drm_gem_object_alloc(dev, args->size);
131 ret = drm_gem_handle_create(file_priv, obj, &handle);
132 drm_gem_object_handle_unreference_unlocked(obj);
137 args->handle = handle;
143 fast_shmem_read(struct page **pages,
144 loff_t page_base, int page_offset,
151 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
154 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
155 kunmap_atomic(vaddr, KM_USER0);
163 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165 drm_i915_private_t *dev_priv = obj->dev->dev_private;
166 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
168 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
169 obj_priv->tiling_mode != I915_TILING_NONE;
173 slow_shmem_copy(struct page *dst_page,
175 struct page *src_page,
179 char *dst_vaddr, *src_vaddr;
181 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
182 if (dst_vaddr == NULL)
185 src_vaddr = kmap_atomic(src_page, KM_USER1);
186 if (src_vaddr == NULL) {
187 kunmap_atomic(dst_vaddr, KM_USER0);
191 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193 kunmap_atomic(src_vaddr, KM_USER1);
194 kunmap_atomic(dst_vaddr, KM_USER0);
200 slow_shmem_bit17_copy(struct page *gpu_page,
202 struct page *cpu_page,
207 char *gpu_vaddr, *cpu_vaddr;
209 /* Use the unswizzled path if this page isn't affected. */
210 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 return slow_shmem_copy(cpu_page, cpu_offset,
213 gpu_page, gpu_offset, length);
215 return slow_shmem_copy(gpu_page, gpu_offset,
216 cpu_page, cpu_offset, length);
219 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
220 if (gpu_vaddr == NULL)
223 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
224 if (cpu_vaddr == NULL) {
225 kunmap_atomic(gpu_vaddr, KM_USER0);
229 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
230 * XORing with the other bits (A9 for Y, A9 and A10 for X)
233 int cacheline_end = ALIGN(gpu_offset + 1, 64);
234 int this_length = min(cacheline_end - gpu_offset, length);
235 int swizzled_gpu_offset = gpu_offset ^ 64;
238 memcpy(cpu_vaddr + cpu_offset,
239 gpu_vaddr + swizzled_gpu_offset,
242 memcpy(gpu_vaddr + swizzled_gpu_offset,
243 cpu_vaddr + cpu_offset,
246 cpu_offset += this_length;
247 gpu_offset += this_length;
248 length -= this_length;
251 kunmap_atomic(cpu_vaddr, KM_USER1);
252 kunmap_atomic(gpu_vaddr, KM_USER0);
258 * This is the fast shmem pread path, which attempts to copy_from_user directly
259 * from the backing pages of the object to the user's address space. On a
260 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
263 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
264 struct drm_i915_gem_pread *args,
265 struct drm_file *file_priv)
267 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
269 loff_t offset, page_base;
270 char __user *user_data;
271 int page_offset, page_length;
274 user_data = (char __user *) (uintptr_t) args->data_ptr;
277 mutex_lock(&dev->struct_mutex);
279 ret = i915_gem_object_get_pages(obj, 0);
283 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
288 obj_priv = to_intel_bo(obj);
289 offset = args->offset;
292 /* Operation in this page
294 * page_base = page offset within aperture
295 * page_offset = offset within page
296 * page_length = bytes to copy for this page
298 page_base = (offset & ~(PAGE_SIZE-1));
299 page_offset = offset & (PAGE_SIZE-1);
300 page_length = remain;
301 if ((page_offset + remain) > PAGE_SIZE)
302 page_length = PAGE_SIZE - page_offset;
304 ret = fast_shmem_read(obj_priv->pages,
305 page_base, page_offset,
306 user_data, page_length);
310 remain -= page_length;
311 user_data += page_length;
312 offset += page_length;
316 i915_gem_object_put_pages(obj);
318 mutex_unlock(&dev->struct_mutex);
324 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
328 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
330 /* If we've insufficient memory to map in the pages, attempt
331 * to make some space by throwing out some old buffers.
333 if (ret == -ENOMEM) {
334 struct drm_device *dev = obj->dev;
336 ret = i915_gem_evict_something(dev, obj->size);
340 ret = i915_gem_object_get_pages(obj, 0);
347 * This is the fallback shmem pread path, which allocates temporary storage
348 * in kernel space to copy_to_user into outside of the struct_mutex, so we
349 * can copy out of the object's backing pages while holding the struct mutex
350 * and not take page faults.
353 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
354 struct drm_i915_gem_pread *args,
355 struct drm_file *file_priv)
357 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
358 struct mm_struct *mm = current->mm;
359 struct page **user_pages;
361 loff_t offset, pinned_pages, i;
362 loff_t first_data_page, last_data_page, num_pages;
363 int shmem_page_index, shmem_page_offset;
364 int data_page_index, data_page_offset;
367 uint64_t data_ptr = args->data_ptr;
368 int do_bit17_swizzling;
372 /* Pin the user pages containing the data. We can't fault while
373 * holding the struct mutex, yet we want to hold it while
374 * dereferencing the user data.
376 first_data_page = data_ptr / PAGE_SIZE;
377 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
378 num_pages = last_data_page - first_data_page + 1;
380 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
381 if (user_pages == NULL)
384 down_read(&mm->mmap_sem);
385 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
386 num_pages, 1, 0, user_pages, NULL);
387 up_read(&mm->mmap_sem);
388 if (pinned_pages < num_pages) {
390 goto fail_put_user_pages;
393 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
395 mutex_lock(&dev->struct_mutex);
397 ret = i915_gem_object_get_pages_or_evict(obj);
401 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
406 obj_priv = to_intel_bo(obj);
407 offset = args->offset;
410 /* Operation in this page
412 * shmem_page_index = page number within shmem file
413 * shmem_page_offset = offset within page in shmem file
414 * data_page_index = page number in get_user_pages return
415 * data_page_offset = offset with data_page_index page.
416 * page_length = bytes to copy for this page
418 shmem_page_index = offset / PAGE_SIZE;
419 shmem_page_offset = offset & ~PAGE_MASK;
420 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
421 data_page_offset = data_ptr & ~PAGE_MASK;
423 page_length = remain;
424 if ((shmem_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - shmem_page_offset;
426 if ((data_page_offset + page_length) > PAGE_SIZE)
427 page_length = PAGE_SIZE - data_page_offset;
429 if (do_bit17_swizzling) {
430 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
432 user_pages[data_page_index],
437 ret = slow_shmem_copy(user_pages[data_page_index],
439 obj_priv->pages[shmem_page_index],
446 remain -= page_length;
447 data_ptr += page_length;
448 offset += page_length;
452 i915_gem_object_put_pages(obj);
454 mutex_unlock(&dev->struct_mutex);
456 for (i = 0; i < pinned_pages; i++) {
457 SetPageDirty(user_pages[i]);
458 page_cache_release(user_pages[i]);
460 drm_free_large(user_pages);
466 * Reads data from the object referenced by handle.
468 * On error, the contents of *data are undefined.
471 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv)
474 struct drm_i915_gem_pread *args = data;
475 struct drm_gem_object *obj;
476 struct drm_i915_gem_object *obj_priv;
479 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
482 obj_priv = to_intel_bo(obj);
484 /* Bounds check source.
486 * XXX: This could use review for overflow issues...
488 if (args->offset > obj->size || args->size > obj->size ||
489 args->offset + args->size > obj->size) {
490 drm_gem_object_unreference_unlocked(obj);
494 if (i915_gem_object_needs_bit17_swizzle(obj)) {
495 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
497 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
499 ret = i915_gem_shmem_pread_slow(dev, obj, args,
503 drm_gem_object_unreference_unlocked(obj);
508 /* This is the fast write path which cannot handle
509 * page faults in the source data
513 fast_user_write(struct io_mapping *mapping,
514 loff_t page_base, int page_offset,
515 char __user *user_data,
519 unsigned long unwritten;
521 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
522 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
524 io_mapping_unmap_atomic(vaddr_atomic);
530 /* Here's the write path which can sleep for
535 slow_kernel_write(struct io_mapping *mapping,
536 loff_t gtt_base, int gtt_offset,
537 struct page *user_page, int user_offset,
540 char *src_vaddr, *dst_vaddr;
541 unsigned long unwritten;
543 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
544 src_vaddr = kmap_atomic(user_page, KM_USER1);
545 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
546 src_vaddr + user_offset,
548 kunmap_atomic(src_vaddr, KM_USER1);
549 io_mapping_unmap_atomic(dst_vaddr);
556 fast_shmem_write(struct page **pages,
557 loff_t page_base, int page_offset,
562 unsigned long unwritten;
564 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
567 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
568 kunmap_atomic(vaddr, KM_USER0);
576 * This is the fast pwrite path, where we copy the data directly from the
577 * user into the GTT, uncached.
580 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
581 struct drm_i915_gem_pwrite *args,
582 struct drm_file *file_priv)
584 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
585 drm_i915_private_t *dev_priv = dev->dev_private;
587 loff_t offset, page_base;
588 char __user *user_data;
589 int page_offset, page_length;
592 user_data = (char __user *) (uintptr_t) args->data_ptr;
594 if (!access_ok(VERIFY_READ, user_data, remain))
598 mutex_lock(&dev->struct_mutex);
599 ret = i915_gem_object_pin(obj, 0);
601 mutex_unlock(&dev->struct_mutex);
604 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
608 obj_priv = to_intel_bo(obj);
609 offset = obj_priv->gtt_offset + args->offset;
612 /* Operation in this page
614 * page_base = page offset within aperture
615 * page_offset = offset within page
616 * page_length = bytes to copy for this page
618 page_base = (offset & ~(PAGE_SIZE-1));
619 page_offset = offset & (PAGE_SIZE-1);
620 page_length = remain;
621 if ((page_offset + remain) > PAGE_SIZE)
622 page_length = PAGE_SIZE - page_offset;
624 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
625 page_offset, user_data, page_length);
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
634 remain -= page_length;
635 user_data += page_length;
636 offset += page_length;
640 i915_gem_object_unpin(obj);
641 mutex_unlock(&dev->struct_mutex);
647 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
648 * the memory and maps it using kmap_atomic for copying.
650 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
651 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
654 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
655 struct drm_i915_gem_pwrite *args,
656 struct drm_file *file_priv)
658 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
659 drm_i915_private_t *dev_priv = dev->dev_private;
661 loff_t gtt_page_base, offset;
662 loff_t first_data_page, last_data_page, num_pages;
663 loff_t pinned_pages, i;
664 struct page **user_pages;
665 struct mm_struct *mm = current->mm;
666 int gtt_page_offset, data_page_offset, data_page_index, page_length;
668 uint64_t data_ptr = args->data_ptr;
672 /* Pin the user pages containing the data. We can't fault while
673 * holding the struct mutex, and all of the pwrite implementations
674 * want to hold it while dereferencing the user data.
676 first_data_page = data_ptr / PAGE_SIZE;
677 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
678 num_pages = last_data_page - first_data_page + 1;
680 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
681 if (user_pages == NULL)
684 down_read(&mm->mmap_sem);
685 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
686 num_pages, 0, 0, user_pages, NULL);
687 up_read(&mm->mmap_sem);
688 if (pinned_pages < num_pages) {
690 goto out_unpin_pages;
693 mutex_lock(&dev->struct_mutex);
694 ret = i915_gem_object_pin(obj, 0);
698 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
700 goto out_unpin_object;
702 obj_priv = to_intel_bo(obj);
703 offset = obj_priv->gtt_offset + args->offset;
706 /* Operation in this page
708 * gtt_page_base = page offset within aperture
709 * gtt_page_offset = offset within page in aperture
710 * data_page_index = page number in get_user_pages return
711 * data_page_offset = offset with data_page_index page.
712 * page_length = bytes to copy for this page
714 gtt_page_base = offset & PAGE_MASK;
715 gtt_page_offset = offset & ~PAGE_MASK;
716 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
717 data_page_offset = data_ptr & ~PAGE_MASK;
719 page_length = remain;
720 if ((gtt_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - gtt_page_offset;
722 if ((data_page_offset + page_length) > PAGE_SIZE)
723 page_length = PAGE_SIZE - data_page_offset;
725 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
726 gtt_page_base, gtt_page_offset,
727 user_pages[data_page_index],
731 /* If we get a fault while copying data, then (presumably) our
732 * source page isn't available. Return the error and we'll
733 * retry in the slow path.
736 goto out_unpin_object;
738 remain -= page_length;
739 offset += page_length;
740 data_ptr += page_length;
744 i915_gem_object_unpin(obj);
746 mutex_unlock(&dev->struct_mutex);
748 for (i = 0; i < pinned_pages; i++)
749 page_cache_release(user_pages[i]);
750 drm_free_large(user_pages);
756 * This is the fast shmem pwrite path, which attempts to directly
757 * copy_from_user into the kmapped pages backing the object.
760 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
761 struct drm_i915_gem_pwrite *args,
762 struct drm_file *file_priv)
764 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
766 loff_t offset, page_base;
767 char __user *user_data;
768 int page_offset, page_length;
771 user_data = (char __user *) (uintptr_t) args->data_ptr;
774 mutex_lock(&dev->struct_mutex);
776 ret = i915_gem_object_get_pages(obj, 0);
780 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
784 obj_priv = to_intel_bo(obj);
785 offset = args->offset;
789 /* Operation in this page
791 * page_base = page offset within aperture
792 * page_offset = offset within page
793 * page_length = bytes to copy for this page
795 page_base = (offset & ~(PAGE_SIZE-1));
796 page_offset = offset & (PAGE_SIZE-1);
797 page_length = remain;
798 if ((page_offset + remain) > PAGE_SIZE)
799 page_length = PAGE_SIZE - page_offset;
801 ret = fast_shmem_write(obj_priv->pages,
802 page_base, page_offset,
803 user_data, page_length);
807 remain -= page_length;
808 user_data += page_length;
809 offset += page_length;
813 i915_gem_object_put_pages(obj);
815 mutex_unlock(&dev->struct_mutex);
821 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
822 * the memory and maps it using kmap_atomic for copying.
824 * This avoids taking mmap_sem for faulting on the user's address while the
825 * struct_mutex is held.
828 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
829 struct drm_i915_gem_pwrite *args,
830 struct drm_file *file_priv)
832 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
833 struct mm_struct *mm = current->mm;
834 struct page **user_pages;
836 loff_t offset, pinned_pages, i;
837 loff_t first_data_page, last_data_page, num_pages;
838 int shmem_page_index, shmem_page_offset;
839 int data_page_index, data_page_offset;
842 uint64_t data_ptr = args->data_ptr;
843 int do_bit17_swizzling;
847 /* Pin the user pages containing the data. We can't fault while
848 * holding the struct mutex, and all of the pwrite implementations
849 * want to hold it while dereferencing the user data.
851 first_data_page = data_ptr / PAGE_SIZE;
852 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
853 num_pages = last_data_page - first_data_page + 1;
855 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
856 if (user_pages == NULL)
859 down_read(&mm->mmap_sem);
860 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
861 num_pages, 0, 0, user_pages, NULL);
862 up_read(&mm->mmap_sem);
863 if (pinned_pages < num_pages) {
865 goto fail_put_user_pages;
868 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
870 mutex_lock(&dev->struct_mutex);
872 ret = i915_gem_object_get_pages_or_evict(obj);
876 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
880 obj_priv = to_intel_bo(obj);
881 offset = args->offset;
885 /* Operation in this page
887 * shmem_page_index = page number within shmem file
888 * shmem_page_offset = offset within page in shmem file
889 * data_page_index = page number in get_user_pages return
890 * data_page_offset = offset with data_page_index page.
891 * page_length = bytes to copy for this page
893 shmem_page_index = offset / PAGE_SIZE;
894 shmem_page_offset = offset & ~PAGE_MASK;
895 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
896 data_page_offset = data_ptr & ~PAGE_MASK;
898 page_length = remain;
899 if ((shmem_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - shmem_page_offset;
901 if ((data_page_offset + page_length) > PAGE_SIZE)
902 page_length = PAGE_SIZE - data_page_offset;
904 if (do_bit17_swizzling) {
905 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
907 user_pages[data_page_index],
912 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
914 user_pages[data_page_index],
921 remain -= page_length;
922 data_ptr += page_length;
923 offset += page_length;
927 i915_gem_object_put_pages(obj);
929 mutex_unlock(&dev->struct_mutex);
931 for (i = 0; i < pinned_pages; i++)
932 page_cache_release(user_pages[i]);
933 drm_free_large(user_pages);
939 * Writes data to the object referenced by handle.
941 * On error, the contents of the buffer that were to be modified are undefined.
944 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
945 struct drm_file *file_priv)
947 struct drm_i915_gem_pwrite *args = data;
948 struct drm_gem_object *obj;
949 struct drm_i915_gem_object *obj_priv;
952 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
955 obj_priv = to_intel_bo(obj);
957 /* Bounds check destination.
959 * XXX: This could use review for overflow issues...
961 if (args->offset > obj->size || args->size > obj->size ||
962 args->offset + args->size > obj->size) {
963 drm_gem_object_unreference_unlocked(obj);
967 /* We can only do the GTT pwrite on untiled buffers, as otherwise
968 * it would end up going through the fenced access, and we'll get
969 * different detiling behavior between reading and writing.
970 * pread/pwrite currently are reading and writing from the CPU
971 * perspective, requiring manual detiling by the client.
973 if (obj_priv->phys_obj)
974 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
975 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
976 dev->gtt_total != 0) {
977 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
978 if (ret == -EFAULT) {
979 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
982 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
983 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
985 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
986 if (ret == -EFAULT) {
987 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
994 DRM_INFO("pwrite failed %d\n", ret);
997 drm_gem_object_unreference_unlocked(obj);
1003 * Called when user space prepares to use an object with the CPU, either
1004 * through the mmap ioctl's mapping or a GTT mapping.
1007 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv)
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct drm_i915_gem_set_domain *args = data;
1012 struct drm_gem_object *obj;
1013 struct drm_i915_gem_object *obj_priv;
1014 uint32_t read_domains = args->read_domains;
1015 uint32_t write_domain = args->write_domain;
1018 if (!(dev->driver->driver_features & DRIVER_GEM))
1021 /* Only handle setting domains to types used by the CPU. */
1022 if (write_domain & I915_GEM_GPU_DOMAINS)
1025 if (read_domains & I915_GEM_GPU_DOMAINS)
1028 /* Having something in the write domain implies it's in the read
1029 * domain, and only that read domain. Enforce that in the request.
1031 if (write_domain != 0 && read_domains != write_domain)
1034 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1037 obj_priv = to_intel_bo(obj);
1039 mutex_lock(&dev->struct_mutex);
1041 intel_mark_busy(dev, obj);
1044 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1045 obj, obj->size, read_domains, write_domain);
1047 if (read_domains & I915_GEM_DOMAIN_GTT) {
1048 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1050 /* Update the LRU on the fence for the CPU access that's
1053 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1054 list_move_tail(&obj_priv->fence_list,
1055 &dev_priv->mm.fence_list);
1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1074 * Called when user space has done writes to this buffer
1077 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091 mutex_unlock(&dev->struct_mutex);
1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1097 __func__, args->handle, obj, obj->size);
1099 obj_priv = to_intel_bo(obj);
1101 /* Pinned buffers may be scanout, so flush the cache */
1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1111 * Maps the contents of an object, returning the address it is mapped
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1118 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1133 offset = args->offset;
1135 down_write(¤t->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1139 up_write(¤t->mm->mmap_sem);
1140 drm_gem_object_unreference_unlocked(obj);
1141 if (IS_ERR((void *)addr))
1144 args->addr_ptr = (uint64_t) addr;
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1165 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1171 pgoff_t page_offset;
1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1194 /* Need a new fence register? */
1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1196 ret = i915_gem_object_get_fence_reg(obj);
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1207 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_NOPAGE;
1215 return VM_FAULT_OOM;
1217 return VM_FAULT_SIGBUS;
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1230 * This routine allocates and attaches a fake offset for @obj.
1233 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1238 struct drm_map_list *list;
1239 struct drm_local_map *map;
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1283 drm_mm_put_block(list->file_offset_node);
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1294 * Preserve the reservation of the mmapping with the DRM core code, but
1295 * relinquish ownership of the pages back to the system.
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1305 i915_gem_release_mmap(struct drm_gem_object *obj)
1307 struct drm_device *dev = obj->dev;
1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1316 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1318 struct drm_device *dev = obj->dev;
1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1336 obj_priv->mmap_offset = 0;
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1347 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1349 struct drm_device *dev = obj->dev;
1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1369 for (i = start; i < obj->size; i <<= 1)
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1391 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407 mutex_lock(&dev->struct_mutex);
1409 obj_priv = to_intel_bo(obj);
1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
1428 args->offset = obj_priv->mmap_offset;
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1434 if (!obj_priv->agp_mem) {
1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1451 i915_gem_object_put_pages(struct drm_gem_object *obj)
1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1454 int page_count = obj->size / PAGE_SIZE;
1457 BUG_ON(obj_priv->pages_refcount == 0);
1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1460 if (--obj_priv->pages_refcount != 0)
1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1466 if (obj_priv->madv == I915_MADV_DONTNEED)
1467 obj_priv->dirty = 0;
1469 for (i = 0; i < page_count; i++) {
1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
1474 mark_page_accessed(obj_priv->pages[i]);
1476 page_cache_release(obj_priv->pages[i]);
1478 obj_priv->dirty = 0;
1480 drm_free_large(obj_priv->pages);
1481 obj_priv->pages = NULL;
1485 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1491 /* Add a reference if we're newly entering the active list. */
1492 if (!obj_priv->active) {
1493 drm_gem_object_reference(obj);
1494 obj_priv->active = 1;
1496 /* Move from whatever list we were on to the tail of execution. */
1497 spin_lock(&dev_priv->mm.active_list_lock);
1498 list_move_tail(&obj_priv->list,
1499 &dev_priv->mm.active_list);
1500 spin_unlock(&dev_priv->mm.active_list_lock);
1501 obj_priv->last_rendering_seqno = seqno;
1505 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1507 struct drm_device *dev = obj->dev;
1508 drm_i915_private_t *dev_priv = dev->dev_private;
1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1511 BUG_ON(!obj_priv->active);
1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1513 obj_priv->last_rendering_seqno = 0;
1516 /* Immediately discard the backing storage */
1518 i915_gem_object_truncate(struct drm_gem_object *obj)
1520 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1521 struct inode *inode;
1523 inode = obj->filp->f_path.dentry->d_inode;
1524 if (inode->i_op->truncate)
1525 inode->i_op->truncate (inode);
1527 obj_priv->madv = __I915_MADV_PURGED;
1531 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1533 return obj_priv->madv == I915_MADV_DONTNEED;
1537 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1539 struct drm_device *dev = obj->dev;
1540 drm_i915_private_t *dev_priv = dev->dev_private;
1541 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1543 i915_verify_inactive(dev, __FILE__, __LINE__);
1544 if (obj_priv->pin_count != 0)
1545 list_del_init(&obj_priv->list);
1547 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1549 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1551 obj_priv->last_rendering_seqno = 0;
1552 if (obj_priv->active) {
1553 obj_priv->active = 0;
1554 drm_gem_object_unreference(obj);
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1560 i915_gem_process_flushing_list(struct drm_device *dev,
1561 uint32_t flush_domains, uint32_t seqno)
1563 drm_i915_private_t *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj_priv, *next;
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.gpu_write_list,
1569 struct drm_gem_object *obj = obj_priv->obj;
1571 if ((obj->write_domain & flush_domains) ==
1572 obj->write_domain) {
1573 uint32_t old_write_domain = obj->write_domain;
1575 obj->write_domain = 0;
1576 list_del_init(&obj_priv->gpu_write_list);
1577 i915_gem_object_move_to_active(obj, seqno);
1579 /* update the fence lru list */
1580 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1581 list_move_tail(&obj_priv->fence_list,
1582 &dev_priv->mm.fence_list);
1584 trace_i915_gem_object_change_domain(obj,
1592 * Creates a new sequence number, emitting a write of it to the status page
1593 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1595 * Must be called with struct_lock held.
1597 * Returned sequence numbers are nonzero on success.
1600 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1601 uint32_t flush_domains)
1603 drm_i915_private_t *dev_priv = dev->dev_private;
1604 struct drm_i915_file_private *i915_file_priv = NULL;
1605 struct drm_i915_gem_request *request;
1610 if (file_priv != NULL)
1611 i915_file_priv = file_priv->driver_priv;
1613 request = kzalloc(sizeof(*request), GFP_KERNEL);
1614 if (request == NULL)
1617 /* Grab the seqno we're going to make this request be, and bump the
1618 * next (skipping 0 so it can be the reserved no-seqno value).
1620 seqno = dev_priv->mm.next_gem_seqno;
1621 dev_priv->mm.next_gem_seqno++;
1622 if (dev_priv->mm.next_gem_seqno == 0)
1623 dev_priv->mm.next_gem_seqno++;
1626 OUT_RING(MI_STORE_DWORD_INDEX);
1627 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1630 OUT_RING(MI_USER_INTERRUPT);
1633 DRM_DEBUG_DRIVER("%d\n", seqno);
1635 request->seqno = seqno;
1636 request->emitted_jiffies = jiffies;
1637 was_empty = list_empty(&dev_priv->mm.request_list);
1638 list_add_tail(&request->list, &dev_priv->mm.request_list);
1639 if (i915_file_priv) {
1640 list_add_tail(&request->client_list,
1641 &i915_file_priv->mm.request_list);
1643 INIT_LIST_HEAD(&request->client_list);
1646 /* Associate any objects on the flushing list matching the write
1647 * domain we're flushing with our flush.
1649 if (flush_domains != 0)
1650 i915_gem_process_flushing_list(dev, flush_domains, seqno);
1652 if (!dev_priv->mm.suspended) {
1653 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1655 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1661 * Command execution barrier
1663 * Ensures that all commands in the ring are finished
1664 * before signalling the CPU
1667 i915_retire_commands(struct drm_device *dev)
1669 drm_i915_private_t *dev_priv = dev->dev_private;
1670 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1671 uint32_t flush_domains = 0;
1674 /* The sampler always gets flushed on i965 (sigh) */
1676 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1679 OUT_RING(0); /* noop */
1681 return flush_domains;
1685 * Moves buffers associated only with the given active seqno from the active
1686 * to inactive list, potentially freeing them.
1689 i915_gem_retire_request(struct drm_device *dev,
1690 struct drm_i915_gem_request *request)
1692 drm_i915_private_t *dev_priv = dev->dev_private;
1694 trace_i915_gem_request_retire(dev, request->seqno);
1696 /* Move any buffers on the active list that are no longer referenced
1697 * by the ringbuffer to the flushing/inactive lists as appropriate.
1699 spin_lock(&dev_priv->mm.active_list_lock);
1700 while (!list_empty(&dev_priv->mm.active_list)) {
1701 struct drm_gem_object *obj;
1702 struct drm_i915_gem_object *obj_priv;
1704 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1705 struct drm_i915_gem_object,
1707 obj = obj_priv->obj;
1709 /* If the seqno being retired doesn't match the oldest in the
1710 * list, then the oldest in the list must still be newer than
1713 if (obj_priv->last_rendering_seqno != request->seqno)
1717 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1718 __func__, request->seqno, obj);
1721 if (obj->write_domain != 0)
1722 i915_gem_object_move_to_flushing(obj);
1724 /* Take a reference on the object so it won't be
1725 * freed while the spinlock is held. The list
1726 * protection for this spinlock is safe when breaking
1727 * the lock like this since the next thing we do
1728 * is just get the head of the list again.
1730 drm_gem_object_reference(obj);
1731 i915_gem_object_move_to_inactive(obj);
1732 spin_unlock(&dev_priv->mm.active_list_lock);
1733 drm_gem_object_unreference(obj);
1734 spin_lock(&dev_priv->mm.active_list_lock);
1738 spin_unlock(&dev_priv->mm.active_list_lock);
1742 * Returns true if seq1 is later than seq2.
1745 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1747 return (int32_t)(seq1 - seq2) >= 0;
1751 i915_get_gem_seqno(struct drm_device *dev)
1753 drm_i915_private_t *dev_priv = dev->dev_private;
1755 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1759 * This function clears the request list as sequence numbers are passed.
1762 i915_gem_retire_requests(struct drm_device *dev)
1764 drm_i915_private_t *dev_priv = dev->dev_private;
1767 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1770 seqno = i915_get_gem_seqno(dev);
1772 while (!list_empty(&dev_priv->mm.request_list)) {
1773 struct drm_i915_gem_request *request;
1774 uint32_t retiring_seqno;
1776 request = list_first_entry(&dev_priv->mm.request_list,
1777 struct drm_i915_gem_request,
1779 retiring_seqno = request->seqno;
1781 if (i915_seqno_passed(seqno, retiring_seqno) ||
1782 atomic_read(&dev_priv->mm.wedged)) {
1783 i915_gem_retire_request(dev, request);
1785 list_del(&request->list);
1786 list_del(&request->client_list);
1792 if (unlikely (dev_priv->trace_irq_seqno &&
1793 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1794 i915_user_irq_put(dev);
1795 dev_priv->trace_irq_seqno = 0;
1800 i915_gem_retire_work_handler(struct work_struct *work)
1802 drm_i915_private_t *dev_priv;
1803 struct drm_device *dev;
1805 dev_priv = container_of(work, drm_i915_private_t,
1806 mm.retire_work.work);
1807 dev = dev_priv->dev;
1809 mutex_lock(&dev->struct_mutex);
1810 i915_gem_retire_requests(dev);
1811 if (!dev_priv->mm.suspended &&
1812 !list_empty(&dev_priv->mm.request_list))
1813 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1814 mutex_unlock(&dev->struct_mutex);
1818 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1820 drm_i915_private_t *dev_priv = dev->dev_private;
1826 if (atomic_read(&dev_priv->mm.wedged))
1829 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1830 if (HAS_PCH_SPLIT(dev))
1831 ier = I915_READ(DEIER) | I915_READ(GTIER);
1833 ier = I915_READ(IER);
1835 DRM_ERROR("something (likely vbetool) disabled "
1836 "interrupts, re-enabling\n");
1837 i915_driver_irq_preinstall(dev);
1838 i915_driver_irq_postinstall(dev);
1841 trace_i915_gem_request_wait_begin(dev, seqno);
1843 dev_priv->mm.waiting_gem_seqno = seqno;
1844 i915_user_irq_get(dev);
1846 ret = wait_event_interruptible(dev_priv->irq_queue,
1847 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1848 atomic_read(&dev_priv->mm.wedged));
1850 wait_event(dev_priv->irq_queue,
1851 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1852 atomic_read(&dev_priv->mm.wedged));
1854 i915_user_irq_put(dev);
1855 dev_priv->mm.waiting_gem_seqno = 0;
1857 trace_i915_gem_request_wait_end(dev, seqno);
1859 if (atomic_read(&dev_priv->mm.wedged))
1862 if (ret && ret != -ERESTARTSYS)
1863 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1864 __func__, ret, seqno, i915_get_gem_seqno(dev));
1866 /* Directly dispatch request retiring. While we have the work queue
1867 * to handle this, the waiter on a request often wants an associated
1868 * buffer to have made it to the inactive list, and we would need
1869 * a separate wait queue to handle that.
1872 i915_gem_retire_requests(dev);
1878 * Waits for a sequence number to be signaled, and cleans up the
1879 * request and object lists appropriately for that event.
1882 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1884 return i915_do_wait_request(dev, seqno, 1);
1888 i915_gem_flush(struct drm_device *dev,
1889 uint32_t invalidate_domains,
1890 uint32_t flush_domains)
1892 drm_i915_private_t *dev_priv = dev->dev_private;
1897 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1898 invalidate_domains, flush_domains);
1900 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1901 invalidate_domains, flush_domains);
1903 if (flush_domains & I915_GEM_DOMAIN_CPU)
1904 drm_agp_chipset_flush(dev);
1906 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1908 * read/write caches:
1910 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1911 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1912 * also flushed at 2d versus 3d pipeline switches.
1916 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1917 * MI_READ_FLUSH is set, and is always flushed on 965.
1919 * I915_GEM_DOMAIN_COMMAND may not exist?
1921 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1922 * invalidated when MI_EXE_FLUSH is set.
1924 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1925 * invalidated with every MI_FLUSH.
1929 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1930 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1931 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1932 * are flushed at any MI_FLUSH.
1935 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1936 if ((invalidate_domains|flush_domains) &
1937 I915_GEM_DOMAIN_RENDER)
1938 cmd &= ~MI_NO_WRITE_FLUSH;
1939 if (!IS_I965G(dev)) {
1941 * On the 965, the sampler cache always gets flushed
1942 * and this bit is reserved.
1944 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1945 cmd |= MI_READ_FLUSH;
1947 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1948 cmd |= MI_EXE_FLUSH;
1951 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1961 * Ensures that all rendering to the object has completed and the object is
1962 * safe to unbind from the GTT or access from the CPU.
1965 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1967 struct drm_device *dev = obj->dev;
1968 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1971 /* This function only exists to support waiting for existing rendering,
1972 * not for emitting required flushes.
1974 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1976 /* If there is rendering queued on the buffer being evicted, wait for
1979 if (obj_priv->active) {
1981 DRM_INFO("%s: object %p wait for seqno %08x\n",
1982 __func__, obj, obj_priv->last_rendering_seqno);
1984 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1993 * Unbinds an object from the GTT aperture.
1996 i915_gem_object_unbind(struct drm_gem_object *obj)
1998 struct drm_device *dev = obj->dev;
1999 drm_i915_private_t *dev_priv = dev->dev_private;
2000 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2004 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2005 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2007 if (obj_priv->gtt_space == NULL)
2010 if (obj_priv->pin_count != 0) {
2011 DRM_ERROR("Attempting to unbind pinned buffer\n");
2015 /* blow away mappings if mapped through GTT */
2016 i915_gem_release_mmap(obj);
2018 /* Move the object to the CPU domain to ensure that
2019 * any possible CPU writes while it's not in the GTT
2020 * are flushed when we go to remap it. This will
2021 * also ensure that all pending GPU writes are finished
2024 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2026 if (ret != -ERESTARTSYS)
2027 DRM_ERROR("set_domain failed: %d\n", ret);
2031 BUG_ON(obj_priv->active);
2033 /* release the fence reg _after_ flushing */
2034 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2035 i915_gem_clear_fence_reg(obj);
2037 if (obj_priv->agp_mem != NULL) {
2038 drm_unbind_agp(obj_priv->agp_mem);
2039 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2040 obj_priv->agp_mem = NULL;
2043 i915_gem_object_put_pages(obj);
2044 BUG_ON(obj_priv->pages_refcount);
2046 if (obj_priv->gtt_space) {
2047 atomic_dec(&dev->gtt_count);
2048 atomic_sub(obj->size, &dev->gtt_memory);
2050 drm_mm_put_block(obj_priv->gtt_space);
2051 obj_priv->gtt_space = NULL;
2054 /* Remove ourselves from the LRU list if present. */
2055 spin_lock(&dev_priv->mm.active_list_lock);
2056 if (!list_empty(&obj_priv->list))
2057 list_del_init(&obj_priv->list);
2058 spin_unlock(&dev_priv->mm.active_list_lock);
2060 if (i915_gem_object_is_purgeable(obj_priv))
2061 i915_gem_object_truncate(obj);
2063 trace_i915_gem_object_unbind(obj);
2068 static struct drm_gem_object *
2069 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2071 drm_i915_private_t *dev_priv = dev->dev_private;
2072 struct drm_i915_gem_object *obj_priv;
2073 struct drm_gem_object *best = NULL;
2074 struct drm_gem_object *first = NULL;
2076 /* Try to find the smallest clean object */
2077 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2078 struct drm_gem_object *obj = obj_priv->obj;
2079 if (obj->size >= min_size) {
2080 if ((!obj_priv->dirty ||
2081 i915_gem_object_is_purgeable(obj_priv)) &&
2082 (!best || obj->size < best->size)) {
2084 if (best->size == min_size)
2092 return best ? best : first;
2096 i915_gpu_idle(struct drm_device *dev)
2098 drm_i915_private_t *dev_priv = dev->dev_private;
2102 spin_lock(&dev_priv->mm.active_list_lock);
2103 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2104 list_empty(&dev_priv->mm.active_list);
2105 spin_unlock(&dev_priv->mm.active_list_lock);
2110 /* Flush everything onto the inactive list. */
2111 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2112 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2116 return i915_wait_request(dev, seqno);
2120 i915_gem_evict_everything(struct drm_device *dev)
2122 drm_i915_private_t *dev_priv = dev->dev_private;
2126 spin_lock(&dev_priv->mm.active_list_lock);
2127 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2128 list_empty(&dev_priv->mm.flushing_list) &&
2129 list_empty(&dev_priv->mm.active_list));
2130 spin_unlock(&dev_priv->mm.active_list_lock);
2135 /* Flush everything (on to the inactive lists) and evict */
2136 ret = i915_gpu_idle(dev);
2140 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2142 ret = i915_gem_evict_from_inactive_list(dev);
2146 spin_lock(&dev_priv->mm.active_list_lock);
2147 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2148 list_empty(&dev_priv->mm.flushing_list) &&
2149 list_empty(&dev_priv->mm.active_list));
2150 spin_unlock(&dev_priv->mm.active_list_lock);
2151 BUG_ON(!lists_empty);
2157 i915_gem_evict_something(struct drm_device *dev, int min_size)
2159 drm_i915_private_t *dev_priv = dev->dev_private;
2160 struct drm_gem_object *obj;
2164 i915_gem_retire_requests(dev);
2166 /* If there's an inactive buffer available now, grab it
2169 obj = i915_gem_find_inactive_object(dev, min_size);
2171 struct drm_i915_gem_object *obj_priv;
2174 DRM_INFO("%s: evicting %p\n", __func__, obj);
2176 obj_priv = to_intel_bo(obj);
2177 BUG_ON(obj_priv->pin_count != 0);
2178 BUG_ON(obj_priv->active);
2180 /* Wait on the rendering and unbind the buffer. */
2181 return i915_gem_object_unbind(obj);
2184 /* If we didn't get anything, but the ring is still processing
2185 * things, wait for the next to finish and hopefully leave us
2186 * a buffer to evict.
2188 if (!list_empty(&dev_priv->mm.request_list)) {
2189 struct drm_i915_gem_request *request;
2191 request = list_first_entry(&dev_priv->mm.request_list,
2192 struct drm_i915_gem_request,
2195 ret = i915_wait_request(dev, request->seqno);
2202 /* If we didn't have anything on the request list but there
2203 * are buffers awaiting a flush, emit one and try again.
2204 * When we wait on it, those buffers waiting for that flush
2205 * will get moved to inactive.
2207 if (!list_empty(&dev_priv->mm.flushing_list)) {
2208 struct drm_i915_gem_object *obj_priv;
2210 /* Find an object that we can immediately reuse */
2211 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2212 obj = obj_priv->obj;
2213 if (obj->size >= min_size)
2225 seqno = i915_add_request(dev, NULL, obj->write_domain);
2232 /* If we didn't do any of the above, there's no single buffer
2233 * large enough to swap out for the new one, so just evict
2234 * everything and start again. (This should be rare.)
2236 if (!list_empty (&dev_priv->mm.inactive_list))
2237 return i915_gem_evict_from_inactive_list(dev);
2239 return i915_gem_evict_everything(dev);
2244 i915_gem_object_get_pages(struct drm_gem_object *obj,
2247 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2249 struct address_space *mapping;
2250 struct inode *inode;
2253 if (obj_priv->pages_refcount++ != 0)
2256 /* Get the list of pages out of our struct file. They'll be pinned
2257 * at this point until we release them.
2259 page_count = obj->size / PAGE_SIZE;
2260 BUG_ON(obj_priv->pages != NULL);
2261 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2262 if (obj_priv->pages == NULL) {
2263 obj_priv->pages_refcount--;
2267 inode = obj->filp->f_path.dentry->d_inode;
2268 mapping = inode->i_mapping;
2269 for (i = 0; i < page_count; i++) {
2270 page = read_cache_page_gfp(mapping, i,
2271 mapping_gfp_mask (mapping) |
2277 obj_priv->pages[i] = page;
2280 if (obj_priv->tiling_mode != I915_TILING_NONE)
2281 i915_gem_object_do_bit_17_swizzle(obj);
2287 page_cache_release(obj_priv->pages[i]);
2289 drm_free_large(obj_priv->pages);
2290 obj_priv->pages = NULL;
2291 obj_priv->pages_refcount--;
2292 return PTR_ERR(page);
2295 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2297 struct drm_gem_object *obj = reg->obj;
2298 struct drm_device *dev = obj->dev;
2299 drm_i915_private_t *dev_priv = dev->dev_private;
2300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2301 int regnum = obj_priv->fence_reg;
2304 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2306 val |= obj_priv->gtt_offset & 0xfffff000;
2307 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2308 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2310 if (obj_priv->tiling_mode == I915_TILING_Y)
2311 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2312 val |= I965_FENCE_REG_VALID;
2314 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2317 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2319 struct drm_gem_object *obj = reg->obj;
2320 struct drm_device *dev = obj->dev;
2321 drm_i915_private_t *dev_priv = dev->dev_private;
2322 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2323 int regnum = obj_priv->fence_reg;
2326 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2328 val |= obj_priv->gtt_offset & 0xfffff000;
2329 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2330 if (obj_priv->tiling_mode == I915_TILING_Y)
2331 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2332 val |= I965_FENCE_REG_VALID;
2334 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2337 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2339 struct drm_gem_object *obj = reg->obj;
2340 struct drm_device *dev = obj->dev;
2341 drm_i915_private_t *dev_priv = dev->dev_private;
2342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2343 int regnum = obj_priv->fence_reg;
2345 uint32_t fence_reg, val;
2348 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2349 (obj_priv->gtt_offset & (obj->size - 1))) {
2350 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2351 __func__, obj_priv->gtt_offset, obj->size);
2355 if (obj_priv->tiling_mode == I915_TILING_Y &&
2356 HAS_128_BYTE_Y_TILING(dev))
2361 /* Note: pitch better be a power of two tile widths */
2362 pitch_val = obj_priv->stride / tile_width;
2363 pitch_val = ffs(pitch_val) - 1;
2365 val = obj_priv->gtt_offset;
2366 if (obj_priv->tiling_mode == I915_TILING_Y)
2367 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2368 val |= I915_FENCE_SIZE_BITS(obj->size);
2369 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2370 val |= I830_FENCE_REG_VALID;
2373 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2375 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2376 I915_WRITE(fence_reg, val);
2379 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2381 struct drm_gem_object *obj = reg->obj;
2382 struct drm_device *dev = obj->dev;
2383 drm_i915_private_t *dev_priv = dev->dev_private;
2384 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2385 int regnum = obj_priv->fence_reg;
2388 uint32_t fence_size_bits;
2390 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2391 (obj_priv->gtt_offset & (obj->size - 1))) {
2392 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2393 __func__, obj_priv->gtt_offset);
2397 pitch_val = obj_priv->stride / 128;
2398 pitch_val = ffs(pitch_val) - 1;
2399 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2401 val = obj_priv->gtt_offset;
2402 if (obj_priv->tiling_mode == I915_TILING_Y)
2403 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2404 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2405 WARN_ON(fence_size_bits & ~0x00000f00);
2406 val |= fence_size_bits;
2407 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2408 val |= I830_FENCE_REG_VALID;
2410 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2413 static int i915_find_fence_reg(struct drm_device *dev)
2415 struct drm_i915_fence_reg *reg = NULL;
2416 struct drm_i915_gem_object *obj_priv = NULL;
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct drm_gem_object *obj = NULL;
2421 /* First try to find a free reg */
2423 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2424 reg = &dev_priv->fence_regs[i];
2428 obj_priv = to_intel_bo(reg->obj);
2429 if (!obj_priv->pin_count)
2436 /* None available, try to steal one or wait for a user to finish */
2437 i = I915_FENCE_REG_NONE;
2438 list_for_each_entry(obj_priv, &dev_priv->mm.fence_list,
2440 obj = obj_priv->obj;
2442 if (obj_priv->pin_count)
2446 i = obj_priv->fence_reg;
2450 BUG_ON(i == I915_FENCE_REG_NONE);
2452 /* We only have a reference on obj from the active list. put_fence_reg
2453 * might drop that one, causing a use-after-free in it. So hold a
2454 * private reference to obj like the other callers of put_fence_reg
2455 * (set_tiling ioctl) do. */
2456 drm_gem_object_reference(obj);
2457 ret = i915_gem_object_put_fence_reg(obj);
2458 drm_gem_object_unreference(obj);
2466 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2467 * @obj: object to map through a fence reg
2469 * When mapping objects through the GTT, userspace wants to be able to write
2470 * to them without having to worry about swizzling if the object is tiled.
2472 * This function walks the fence regs looking for a free one for @obj,
2473 * stealing one if it can't find any.
2475 * It then sets up the reg based on the object's properties: address, pitch
2476 * and tiling format.
2479 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2481 struct drm_device *dev = obj->dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2484 struct drm_i915_fence_reg *reg = NULL;
2487 /* Just update our place in the LRU if our fence is getting used. */
2488 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2489 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2493 switch (obj_priv->tiling_mode) {
2494 case I915_TILING_NONE:
2495 WARN(1, "allocating a fence for non-tiled object?\n");
2498 if (!obj_priv->stride)
2500 WARN((obj_priv->stride & (512 - 1)),
2501 "object 0x%08x is X tiled but has non-512B pitch\n",
2502 obj_priv->gtt_offset);
2505 if (!obj_priv->stride)
2507 WARN((obj_priv->stride & (128 - 1)),
2508 "object 0x%08x is Y tiled but has non-128B pitch\n",
2509 obj_priv->gtt_offset);
2513 ret = i915_find_fence_reg(dev);
2517 obj_priv->fence_reg = ret;
2518 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2519 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2524 sandybridge_write_fence_reg(reg);
2525 else if (IS_I965G(dev))
2526 i965_write_fence_reg(reg);
2527 else if (IS_I9XX(dev))
2528 i915_write_fence_reg(reg);
2530 i830_write_fence_reg(reg);
2532 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2533 obj_priv->tiling_mode);
2539 * i915_gem_clear_fence_reg - clear out fence register info
2540 * @obj: object to clear
2542 * Zeroes out the fence register itself and clears out the associated
2543 * data structures in dev_priv and obj_priv.
2546 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2548 struct drm_device *dev = obj->dev;
2549 drm_i915_private_t *dev_priv = dev->dev_private;
2550 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2553 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2554 (obj_priv->fence_reg * 8), 0);
2555 } else if (IS_I965G(dev)) {
2556 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2560 if (obj_priv->fence_reg < 8)
2561 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2563 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2566 I915_WRITE(fence_reg, 0);
2569 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2570 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2571 list_del_init(&obj_priv->fence_list);
2575 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2576 * to the buffer to finish, and then resets the fence register.
2577 * @obj: tiled object holding a fence register.
2579 * Zeroes out the fence register itself and clears out the associated
2580 * data structures in dev_priv and obj_priv.
2583 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2585 struct drm_device *dev = obj->dev;
2586 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2588 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2591 /* If we've changed tiling, GTT-mappings of the object
2592 * need to re-fault to ensure that the correct fence register
2593 * setup is in place.
2595 i915_gem_release_mmap(obj);
2597 /* On the i915, GPU access to tiled buffers is via a fence,
2598 * therefore we must wait for any outstanding access to complete
2599 * before clearing the fence.
2601 if (!IS_I965G(dev)) {
2604 i915_gem_object_flush_gpu_write_domain(obj);
2605 ret = i915_gem_object_wait_rendering(obj);
2610 i915_gem_object_flush_gtt_write_domain(obj);
2611 i915_gem_clear_fence_reg (obj);
2617 * Finds free space in the GTT aperture and binds the object there.
2620 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2622 struct drm_device *dev = obj->dev;
2623 drm_i915_private_t *dev_priv = dev->dev_private;
2624 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2625 struct drm_mm_node *free_space;
2626 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2629 if (obj_priv->madv != I915_MADV_WILLNEED) {
2630 DRM_ERROR("Attempting to bind a purgeable object\n");
2635 alignment = i915_gem_get_gtt_alignment(obj);
2636 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2637 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2642 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2643 obj->size, alignment, 0);
2644 if (free_space != NULL) {
2645 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2647 if (obj_priv->gtt_space != NULL) {
2648 obj_priv->gtt_space->private = obj;
2649 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2652 if (obj_priv->gtt_space == NULL) {
2653 /* If the gtt is empty and we're still having trouble
2654 * fitting our object in, we're out of memory.
2657 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2659 ret = i915_gem_evict_something(dev, obj->size);
2667 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2668 obj->size, obj_priv->gtt_offset);
2670 ret = i915_gem_object_get_pages(obj, gfpmask);
2672 drm_mm_put_block(obj_priv->gtt_space);
2673 obj_priv->gtt_space = NULL;
2675 if (ret == -ENOMEM) {
2676 /* first try to clear up some space from the GTT */
2677 ret = i915_gem_evict_something(dev, obj->size);
2679 /* now try to shrink everyone else */
2694 /* Create an AGP memory structure pointing at our pages, and bind it
2697 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2699 obj->size >> PAGE_SHIFT,
2700 obj_priv->gtt_offset,
2701 obj_priv->agp_type);
2702 if (obj_priv->agp_mem == NULL) {
2703 i915_gem_object_put_pages(obj);
2704 drm_mm_put_block(obj_priv->gtt_space);
2705 obj_priv->gtt_space = NULL;
2707 ret = i915_gem_evict_something(dev, obj->size);
2713 atomic_inc(&dev->gtt_count);
2714 atomic_add(obj->size, &dev->gtt_memory);
2716 /* Assert that the object is not currently in any GPU domain. As it
2717 * wasn't in the GTT, there shouldn't be any way it could have been in
2720 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2721 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2723 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2729 i915_gem_clflush_object(struct drm_gem_object *obj)
2731 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2733 /* If we don't have a page list set up, then we're not pinned
2734 * to GPU, and we can ignore the cache flush because it'll happen
2735 * again at bind time.
2737 if (obj_priv->pages == NULL)
2740 trace_i915_gem_object_clflush(obj);
2742 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2745 /** Flushes any GPU write domain for the object if it's dirty. */
2747 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2749 struct drm_device *dev = obj->dev;
2750 uint32_t old_write_domain;
2752 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2755 /* Queue the GPU write cache flushing we need. */
2756 old_write_domain = obj->write_domain;
2757 i915_gem_flush(dev, 0, obj->write_domain);
2758 (void) i915_add_request(dev, NULL, obj->write_domain);
2759 BUG_ON(obj->write_domain);
2761 trace_i915_gem_object_change_domain(obj,
2766 /** Flushes the GTT write domain for the object if it's dirty. */
2768 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2770 uint32_t old_write_domain;
2772 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2775 /* No actual flushing is required for the GTT write domain. Writes
2776 * to it immediately go to main memory as far as we know, so there's
2777 * no chipset flush. It also doesn't land in render cache.
2779 old_write_domain = obj->write_domain;
2780 obj->write_domain = 0;
2782 trace_i915_gem_object_change_domain(obj,
2787 /** Flushes the CPU write domain for the object if it's dirty. */
2789 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2791 struct drm_device *dev = obj->dev;
2792 uint32_t old_write_domain;
2794 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2797 i915_gem_clflush_object(obj);
2798 drm_agp_chipset_flush(dev);
2799 old_write_domain = obj->write_domain;
2800 obj->write_domain = 0;
2802 trace_i915_gem_object_change_domain(obj,
2808 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2810 switch (obj->write_domain) {
2811 case I915_GEM_DOMAIN_GTT:
2812 i915_gem_object_flush_gtt_write_domain(obj);
2814 case I915_GEM_DOMAIN_CPU:
2815 i915_gem_object_flush_cpu_write_domain(obj);
2818 i915_gem_object_flush_gpu_write_domain(obj);
2824 * Moves a single object to the GTT read, and possibly write domain.
2826 * This function returns when the move is complete, including waiting on
2830 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2832 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2833 uint32_t old_write_domain, old_read_domains;
2836 /* Not valid to be called on unbound objects. */
2837 if (obj_priv->gtt_space == NULL)
2840 i915_gem_object_flush_gpu_write_domain(obj);
2841 /* Wait on any GPU rendering and flushing to occur. */
2842 ret = i915_gem_object_wait_rendering(obj);
2846 old_write_domain = obj->write_domain;
2847 old_read_domains = obj->read_domains;
2849 /* If we're writing through the GTT domain, then CPU and GPU caches
2850 * will need to be invalidated at next use.
2853 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2855 i915_gem_object_flush_cpu_write_domain(obj);
2857 /* It should now be out of any other write domains, and we can update
2858 * the domain values for our changes.
2860 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2861 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2863 obj->write_domain = I915_GEM_DOMAIN_GTT;
2864 obj_priv->dirty = 1;
2867 trace_i915_gem_object_change_domain(obj,
2875 * Prepare buffer for display plane. Use uninterruptible for possible flush
2876 * wait, as in modesetting process we're not supposed to be interrupted.
2879 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2881 struct drm_device *dev = obj->dev;
2882 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2883 uint32_t old_write_domain, old_read_domains;
2886 /* Not valid to be called on unbound objects. */
2887 if (obj_priv->gtt_space == NULL)
2890 i915_gem_object_flush_gpu_write_domain(obj);
2892 /* Wait on any GPU rendering and flushing to occur. */
2893 if (obj_priv->active) {
2895 DRM_INFO("%s: object %p wait for seqno %08x\n",
2896 __func__, obj, obj_priv->last_rendering_seqno);
2898 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2903 old_write_domain = obj->write_domain;
2904 old_read_domains = obj->read_domains;
2906 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2908 i915_gem_object_flush_cpu_write_domain(obj);
2910 /* It should now be out of any other write domains, and we can update
2911 * the domain values for our changes.
2913 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2914 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2915 obj->write_domain = I915_GEM_DOMAIN_GTT;
2916 obj_priv->dirty = 1;
2918 trace_i915_gem_object_change_domain(obj,
2926 * Moves a single object to the CPU read, and possibly write domain.
2928 * This function returns when the move is complete, including waiting on
2932 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2934 uint32_t old_write_domain, old_read_domains;
2937 i915_gem_object_flush_gpu_write_domain(obj);
2938 /* Wait on any GPU rendering and flushing to occur. */
2939 ret = i915_gem_object_wait_rendering(obj);
2943 i915_gem_object_flush_gtt_write_domain(obj);
2945 /* If we have a partially-valid cache of the object in the CPU,
2946 * finish invalidating it and free the per-page flags.
2948 i915_gem_object_set_to_full_cpu_read_domain(obj);
2950 old_write_domain = obj->write_domain;
2951 old_read_domains = obj->read_domains;
2953 /* Flush the CPU cache if it's still invalid. */
2954 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2955 i915_gem_clflush_object(obj);
2957 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2960 /* It should now be out of any other write domains, and we can update
2961 * the domain values for our changes.
2963 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2965 /* If we're writing through the CPU, then the GPU read domains will
2966 * need to be invalidated at next use.
2969 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2970 obj->write_domain = I915_GEM_DOMAIN_CPU;
2973 trace_i915_gem_object_change_domain(obj,
2981 * Set the next domain for the specified object. This
2982 * may not actually perform the necessary flushing/invaliding though,
2983 * as that may want to be batched with other set_domain operations
2985 * This is (we hope) the only really tricky part of gem. The goal
2986 * is fairly simple -- track which caches hold bits of the object
2987 * and make sure they remain coherent. A few concrete examples may
2988 * help to explain how it works. For shorthand, we use the notation
2989 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2990 * a pair of read and write domain masks.
2992 * Case 1: the batch buffer
2998 * 5. Unmapped from GTT
3001 * Let's take these a step at a time
3004 * Pages allocated from the kernel may still have
3005 * cache contents, so we set them to (CPU, CPU) always.
3006 * 2. Written by CPU (using pwrite)
3007 * The pwrite function calls set_domain (CPU, CPU) and
3008 * this function does nothing (as nothing changes)
3010 * This function asserts that the object is not
3011 * currently in any GPU-based read or write domains
3013 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3014 * As write_domain is zero, this function adds in the
3015 * current read domains (CPU+COMMAND, 0).
3016 * flush_domains is set to CPU.
3017 * invalidate_domains is set to COMMAND
3018 * clflush is run to get data out of the CPU caches
3019 * then i915_dev_set_domain calls i915_gem_flush to
3020 * emit an MI_FLUSH and drm_agp_chipset_flush
3021 * 5. Unmapped from GTT
3022 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3023 * flush_domains and invalidate_domains end up both zero
3024 * so no flushing/invalidating happens
3028 * Case 2: The shared render buffer
3032 * 3. Read/written by GPU
3033 * 4. set_domain to (CPU,CPU)
3034 * 5. Read/written by CPU
3035 * 6. Read/written by GPU
3038 * Same as last example, (CPU, CPU)
3040 * Nothing changes (assertions find that it is not in the GPU)
3041 * 3. Read/written by GPU
3042 * execbuffer calls set_domain (RENDER, RENDER)
3043 * flush_domains gets CPU
3044 * invalidate_domains gets GPU
3046 * MI_FLUSH and drm_agp_chipset_flush
3047 * 4. set_domain (CPU, CPU)
3048 * flush_domains gets GPU
3049 * invalidate_domains gets CPU
3050 * wait_rendering (obj) to make sure all drawing is complete.
3051 * This will include an MI_FLUSH to get the data from GPU
3053 * clflush (obj) to invalidate the CPU cache
3054 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3055 * 5. Read/written by CPU
3056 * cache lines are loaded and dirtied
3057 * 6. Read written by GPU
3058 * Same as last GPU access
3060 * Case 3: The constant buffer
3065 * 4. Updated (written) by CPU again
3074 * flush_domains = CPU
3075 * invalidate_domains = RENDER
3078 * drm_agp_chipset_flush
3079 * 4. Updated (written) by CPU again
3081 * flush_domains = 0 (no previous write domain)
3082 * invalidate_domains = 0 (no new read domains)
3085 * flush_domains = CPU
3086 * invalidate_domains = RENDER
3089 * drm_agp_chipset_flush
3092 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3094 struct drm_device *dev = obj->dev;
3095 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3096 uint32_t invalidate_domains = 0;
3097 uint32_t flush_domains = 0;
3098 uint32_t old_read_domains;
3100 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3101 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3103 intel_mark_busy(dev, obj);
3106 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3108 obj->read_domains, obj->pending_read_domains,
3109 obj->write_domain, obj->pending_write_domain);
3112 * If the object isn't moving to a new write domain,
3113 * let the object stay in multiple read domains
3115 if (obj->pending_write_domain == 0)
3116 obj->pending_read_domains |= obj->read_domains;
3118 obj_priv->dirty = 1;
3121 * Flush the current write domain if
3122 * the new read domains don't match. Invalidate
3123 * any read domains which differ from the old
3126 if (obj->write_domain &&
3127 obj->write_domain != obj->pending_read_domains) {
3128 flush_domains |= obj->write_domain;
3129 invalidate_domains |=
3130 obj->pending_read_domains & ~obj->write_domain;
3133 * Invalidate any read caches which may have
3134 * stale data. That is, any new read domains.
3136 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3137 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3139 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3140 __func__, flush_domains, invalidate_domains);
3142 i915_gem_clflush_object(obj);
3145 old_read_domains = obj->read_domains;
3147 /* The actual obj->write_domain will be updated with
3148 * pending_write_domain after we emit the accumulated flush for all
3149 * of our domain changes in execbuffers (which clears objects'
3150 * write_domains). So if we have a current write domain that we
3151 * aren't changing, set pending_write_domain to that.
3153 if (flush_domains == 0 && obj->pending_write_domain == 0)
3154 obj->pending_write_domain = obj->write_domain;
3155 obj->read_domains = obj->pending_read_domains;
3157 dev->invalidate_domains |= invalidate_domains;
3158 dev->flush_domains |= flush_domains;
3160 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3162 obj->read_domains, obj->write_domain,
3163 dev->invalidate_domains, dev->flush_domains);
3166 trace_i915_gem_object_change_domain(obj,
3172 * Moves the object from a partially CPU read to a full one.
3174 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3175 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3178 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3180 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3182 if (!obj_priv->page_cpu_valid)
3185 /* If we're partially in the CPU read domain, finish moving it in.
3187 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3190 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3191 if (obj_priv->page_cpu_valid[i])
3193 drm_clflush_pages(obj_priv->pages + i, 1);
3197 /* Free the page_cpu_valid mappings which are now stale, whether
3198 * or not we've got I915_GEM_DOMAIN_CPU.
3200 kfree(obj_priv->page_cpu_valid);
3201 obj_priv->page_cpu_valid = NULL;
3205 * Set the CPU read domain on a range of the object.
3207 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3208 * not entirely valid. The page_cpu_valid member of the object flags which
3209 * pages have been flushed, and will be respected by
3210 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3211 * of the whole object.
3213 * This function returns when the move is complete, including waiting on
3217 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3218 uint64_t offset, uint64_t size)
3220 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3221 uint32_t old_read_domains;
3224 if (offset == 0 && size == obj->size)
3225 return i915_gem_object_set_to_cpu_domain(obj, 0);
3227 i915_gem_object_flush_gpu_write_domain(obj);
3228 /* Wait on any GPU rendering and flushing to occur. */
3229 ret = i915_gem_object_wait_rendering(obj);
3232 i915_gem_object_flush_gtt_write_domain(obj);
3234 /* If we're already fully in the CPU read domain, we're done. */
3235 if (obj_priv->page_cpu_valid == NULL &&
3236 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3239 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3240 * newly adding I915_GEM_DOMAIN_CPU
3242 if (obj_priv->page_cpu_valid == NULL) {
3243 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3245 if (obj_priv->page_cpu_valid == NULL)
3247 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3248 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3250 /* Flush the cache on any pages that are still invalid from the CPU's
3253 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3255 if (obj_priv->page_cpu_valid[i])
3258 drm_clflush_pages(obj_priv->pages + i, 1);
3260 obj_priv->page_cpu_valid[i] = 1;
3263 /* It should now be out of any other write domains, and we can update
3264 * the domain values for our changes.
3266 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3268 old_read_domains = obj->read_domains;
3269 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3271 trace_i915_gem_object_change_domain(obj,
3279 * Pin an object to the GTT and evaluate the relocations landing in it.
3282 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3283 struct drm_file *file_priv,
3284 struct drm_i915_gem_exec_object2 *entry,
3285 struct drm_i915_gem_relocation_entry *relocs)
3287 struct drm_device *dev = obj->dev;
3288 drm_i915_private_t *dev_priv = dev->dev_private;
3289 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3291 void __iomem *reloc_page;
3294 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3295 obj_priv->tiling_mode != I915_TILING_NONE;
3297 /* Check fence reg constraints and rebind if necessary */
3298 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3299 obj_priv->tiling_mode))
3300 i915_gem_object_unbind(obj);
3302 /* Choose the GTT offset for our buffer and put it there. */
3303 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3308 * Pre-965 chips need a fence register set up in order to
3309 * properly handle blits to/from tiled surfaces.
3312 ret = i915_gem_object_get_fence_reg(obj);
3314 if (ret != -EBUSY && ret != -ERESTARTSYS)
3315 DRM_ERROR("Failure to install fence: %d\n",
3317 i915_gem_object_unpin(obj);
3322 entry->offset = obj_priv->gtt_offset;
3324 /* Apply the relocations, using the GTT aperture to avoid cache
3325 * flushing requirements.
3327 for (i = 0; i < entry->relocation_count; i++) {
3328 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3329 struct drm_gem_object *target_obj;
3330 struct drm_i915_gem_object *target_obj_priv;
3331 uint32_t reloc_val, reloc_offset;
3332 uint32_t __iomem *reloc_entry;
3334 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3335 reloc->target_handle);
3336 if (target_obj == NULL) {
3337 i915_gem_object_unpin(obj);
3340 target_obj_priv = to_intel_bo(target_obj);
3343 DRM_INFO("%s: obj %p offset %08x target %d "
3344 "read %08x write %08x gtt %08x "
3345 "presumed %08x delta %08x\n",
3348 (int) reloc->offset,
3349 (int) reloc->target_handle,
3350 (int) reloc->read_domains,
3351 (int) reloc->write_domain,
3352 (int) target_obj_priv->gtt_offset,
3353 (int) reloc->presumed_offset,
3357 /* The target buffer should have appeared before us in the
3358 * exec_object list, so it should have a GTT space bound by now.
3360 if (target_obj_priv->gtt_space == NULL) {
3361 DRM_ERROR("No GTT space found for object %d\n",
3362 reloc->target_handle);
3363 drm_gem_object_unreference(target_obj);
3364 i915_gem_object_unpin(obj);
3368 /* Validate that the target is in a valid r/w GPU domain */
3369 if (reloc->write_domain & (reloc->write_domain - 1)) {
3370 DRM_ERROR("reloc with multiple write domains: "
3371 "obj %p target %d offset %d "
3372 "read %08x write %08x",
3373 obj, reloc->target_handle,
3374 (int) reloc->offset,
3375 reloc->read_domains,
3376 reloc->write_domain);
3379 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3380 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3381 DRM_ERROR("reloc with read/write CPU domains: "
3382 "obj %p target %d offset %d "
3383 "read %08x write %08x",
3384 obj, reloc->target_handle,
3385 (int) reloc->offset,
3386 reloc->read_domains,
3387 reloc->write_domain);
3388 drm_gem_object_unreference(target_obj);
3389 i915_gem_object_unpin(obj);
3392 if (reloc->write_domain && target_obj->pending_write_domain &&
3393 reloc->write_domain != target_obj->pending_write_domain) {
3394 DRM_ERROR("Write domain conflict: "
3395 "obj %p target %d offset %d "
3396 "new %08x old %08x\n",
3397 obj, reloc->target_handle,
3398 (int) reloc->offset,
3399 reloc->write_domain,
3400 target_obj->pending_write_domain);
3401 drm_gem_object_unreference(target_obj);
3402 i915_gem_object_unpin(obj);
3406 target_obj->pending_read_domains |= reloc->read_domains;
3407 target_obj->pending_write_domain |= reloc->write_domain;
3409 /* If the relocation already has the right value in it, no
3410 * more work needs to be done.
3412 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3413 drm_gem_object_unreference(target_obj);
3417 /* Check that the relocation address is valid... */
3418 if (reloc->offset > obj->size - 4) {
3419 DRM_ERROR("Relocation beyond object bounds: "
3420 "obj %p target %d offset %d size %d.\n",
3421 obj, reloc->target_handle,
3422 (int) reloc->offset, (int) obj->size);
3423 drm_gem_object_unreference(target_obj);
3424 i915_gem_object_unpin(obj);
3427 if (reloc->offset & 3) {
3428 DRM_ERROR("Relocation not 4-byte aligned: "
3429 "obj %p target %d offset %d.\n",
3430 obj, reloc->target_handle,
3431 (int) reloc->offset);
3432 drm_gem_object_unreference(target_obj);
3433 i915_gem_object_unpin(obj);
3437 /* and points to somewhere within the target object. */
3438 if (reloc->delta >= target_obj->size) {
3439 DRM_ERROR("Relocation beyond target object bounds: "
3440 "obj %p target %d delta %d size %d.\n",
3441 obj, reloc->target_handle,
3442 (int) reloc->delta, (int) target_obj->size);
3443 drm_gem_object_unreference(target_obj);
3444 i915_gem_object_unpin(obj);
3448 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3450 drm_gem_object_unreference(target_obj);
3451 i915_gem_object_unpin(obj);
3455 /* Map the page containing the relocation we're going to
3458 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3459 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3462 reloc_entry = (uint32_t __iomem *)(reloc_page +
3463 (reloc_offset & (PAGE_SIZE - 1)));
3464 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3467 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3468 obj, (unsigned int) reloc->offset,
3469 readl(reloc_entry), reloc_val);
3471 writel(reloc_val, reloc_entry);
3472 io_mapping_unmap_atomic(reloc_page);
3474 /* The updated presumed offset for this entry will be
3475 * copied back out to the user.
3477 reloc->presumed_offset = target_obj_priv->gtt_offset;
3479 drm_gem_object_unreference(target_obj);
3484 i915_gem_dump_object(obj, 128, __func__, ~0);
3489 /** Dispatch a batchbuffer to the ring
3492 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3493 struct drm_i915_gem_execbuffer2 *exec,
3494 struct drm_clip_rect *cliprects,
3495 uint64_t exec_offset)
3497 drm_i915_private_t *dev_priv = dev->dev_private;
3498 int nbox = exec->num_cliprects;
3500 uint32_t exec_start, exec_len;
3503 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3504 exec_len = (uint32_t) exec->batch_len;
3506 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3508 count = nbox ? nbox : 1;
3510 for (i = 0; i < count; i++) {
3512 int ret = i915_emit_box(dev, cliprects, i,
3513 exec->DR1, exec->DR4);
3518 if (IS_I830(dev) || IS_845G(dev)) {
3520 OUT_RING(MI_BATCH_BUFFER);
3521 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3522 OUT_RING(exec_start + exec_len - 4);
3527 if (IS_I965G(dev)) {
3528 OUT_RING(MI_BATCH_BUFFER_START |
3530 MI_BATCH_NON_SECURE_I965);
3531 OUT_RING(exec_start);
3533 OUT_RING(MI_BATCH_BUFFER_START |
3535 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3541 /* XXX breadcrumb */
3545 /* Throttle our rendering by waiting until the ring has completed our requests
3546 * emitted over 20 msec ago.
3548 * Note that if we were to use the current jiffies each time around the loop,
3549 * we wouldn't escape the function with any frames outstanding if the time to
3550 * render a frame was over 20ms.
3552 * This should get us reasonable parallelism between CPU and GPU but also
3553 * relatively low latency when blocking on a particular request to finish.
3556 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3558 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3560 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3562 mutex_lock(&dev->struct_mutex);
3563 while (!list_empty(&i915_file_priv->mm.request_list)) {
3564 struct drm_i915_gem_request *request;
3566 request = list_first_entry(&i915_file_priv->mm.request_list,
3567 struct drm_i915_gem_request,
3570 if (time_after_eq(request->emitted_jiffies, recent_enough))
3573 ret = i915_wait_request(dev, request->seqno);
3577 mutex_unlock(&dev->struct_mutex);
3583 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3584 uint32_t buffer_count,
3585 struct drm_i915_gem_relocation_entry **relocs)
3587 uint32_t reloc_count = 0, reloc_index = 0, i;
3591 for (i = 0; i < buffer_count; i++) {
3592 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3594 reloc_count += exec_list[i].relocation_count;
3597 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3598 if (*relocs == NULL) {
3599 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3603 for (i = 0; i < buffer_count; i++) {
3604 struct drm_i915_gem_relocation_entry __user *user_relocs;
3606 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3608 ret = copy_from_user(&(*relocs)[reloc_index],
3610 exec_list[i].relocation_count *
3613 drm_free_large(*relocs);
3618 reloc_index += exec_list[i].relocation_count;
3625 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3626 uint32_t buffer_count,
3627 struct drm_i915_gem_relocation_entry *relocs)
3629 uint32_t reloc_count = 0, i;
3635 for (i = 0; i < buffer_count; i++) {
3636 struct drm_i915_gem_relocation_entry __user *user_relocs;
3639 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3641 unwritten = copy_to_user(user_relocs,
3642 &relocs[reloc_count],
3643 exec_list[i].relocation_count *
3651 reloc_count += exec_list[i].relocation_count;
3655 drm_free_large(relocs);
3661 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3662 uint64_t exec_offset)
3664 uint32_t exec_start, exec_len;
3666 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3667 exec_len = (uint32_t) exec->batch_len;
3669 if ((exec_start | exec_len) & 0x7)
3679 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3680 struct drm_gem_object **object_list,
3683 drm_i915_private_t *dev_priv = dev->dev_private;
3684 struct drm_i915_gem_object *obj_priv;
3689 prepare_to_wait(&dev_priv->pending_flip_queue,
3690 &wait, TASK_INTERRUPTIBLE);
3691 for (i = 0; i < count; i++) {
3692 obj_priv = to_intel_bo(object_list[i]);
3693 if (atomic_read(&obj_priv->pending_flip) > 0)
3699 if (!signal_pending(current)) {
3700 mutex_unlock(&dev->struct_mutex);
3702 mutex_lock(&dev->struct_mutex);
3708 finish_wait(&dev_priv->pending_flip_queue, &wait);
3714 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3715 struct drm_file *file_priv,
3716 struct drm_i915_gem_execbuffer2 *args,
3717 struct drm_i915_gem_exec_object2 *exec_list)
3719 drm_i915_private_t *dev_priv = dev->dev_private;
3720 struct drm_gem_object **object_list = NULL;
3721 struct drm_gem_object *batch_obj;
3722 struct drm_i915_gem_object *obj_priv;
3723 struct drm_clip_rect *cliprects = NULL;
3724 struct drm_i915_gem_relocation_entry *relocs = NULL;
3725 int ret = 0, ret2, i, pinned = 0;
3726 uint64_t exec_offset;
3727 uint32_t seqno, flush_domains, reloc_index;
3728 int pin_tries, flips;
3731 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3732 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3735 if (args->buffer_count < 1) {
3736 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3739 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3740 if (object_list == NULL) {
3741 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3742 args->buffer_count);
3747 if (args->num_cliprects != 0) {
3748 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3750 if (cliprects == NULL) {
3755 ret = copy_from_user(cliprects,
3756 (struct drm_clip_rect __user *)
3757 (uintptr_t) args->cliprects_ptr,
3758 sizeof(*cliprects) * args->num_cliprects);
3760 DRM_ERROR("copy %d cliprects failed: %d\n",
3761 args->num_cliprects, ret);
3766 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3771 mutex_lock(&dev->struct_mutex);
3773 i915_verify_inactive(dev, __FILE__, __LINE__);
3775 if (atomic_read(&dev_priv->mm.wedged)) {
3776 mutex_unlock(&dev->struct_mutex);
3781 if (dev_priv->mm.suspended) {
3782 mutex_unlock(&dev->struct_mutex);
3787 /* Look up object handles */
3789 for (i = 0; i < args->buffer_count; i++) {
3790 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3791 exec_list[i].handle);
3792 if (object_list[i] == NULL) {
3793 DRM_ERROR("Invalid object handle %d at index %d\n",
3794 exec_list[i].handle, i);
3795 /* prevent error path from reading uninitialized data */
3796 args->buffer_count = i + 1;
3801 obj_priv = to_intel_bo(object_list[i]);
3802 if (obj_priv->in_execbuffer) {
3803 DRM_ERROR("Object %p appears more than once in object list\n",
3805 /* prevent error path from reading uninitialized data */
3806 args->buffer_count = i + 1;
3810 obj_priv->in_execbuffer = true;
3811 flips += atomic_read(&obj_priv->pending_flip);
3815 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3816 args->buffer_count);
3821 /* Pin and relocate */
3822 for (pin_tries = 0; ; pin_tries++) {
3826 for (i = 0; i < args->buffer_count; i++) {
3827 object_list[i]->pending_read_domains = 0;
3828 object_list[i]->pending_write_domain = 0;
3829 ret = i915_gem_object_pin_and_relocate(object_list[i],
3832 &relocs[reloc_index]);
3836 reloc_index += exec_list[i].relocation_count;
3842 /* error other than GTT full, or we've already tried again */
3843 if (ret != -ENOSPC || pin_tries >= 1) {
3844 if (ret != -ERESTARTSYS) {
3845 unsigned long long total_size = 0;
3846 for (i = 0; i < args->buffer_count; i++)
3847 total_size += object_list[i]->size;
3848 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3849 pinned+1, args->buffer_count,
3851 DRM_ERROR("%d objects [%d pinned], "
3852 "%d object bytes [%d pinned], "
3853 "%d/%d gtt bytes\n",
3854 atomic_read(&dev->object_count),
3855 atomic_read(&dev->pin_count),
3856 atomic_read(&dev->object_memory),
3857 atomic_read(&dev->pin_memory),
3858 atomic_read(&dev->gtt_memory),
3864 /* unpin all of our buffers */
3865 for (i = 0; i < pinned; i++)
3866 i915_gem_object_unpin(object_list[i]);
3869 /* evict everyone we can from the aperture */
3870 ret = i915_gem_evict_everything(dev);
3871 if (ret && ret != -ENOSPC)
3875 /* Set the pending read domains for the batch buffer to COMMAND */
3876 batch_obj = object_list[args->buffer_count-1];
3877 if (batch_obj->pending_write_domain) {
3878 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3882 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3884 /* Sanity check the batch buffer, prior to moving objects */
3885 exec_offset = exec_list[args->buffer_count - 1].offset;
3886 ret = i915_gem_check_execbuffer (args, exec_offset);
3888 DRM_ERROR("execbuf with invalid offset/length\n");
3892 i915_verify_inactive(dev, __FILE__, __LINE__);
3894 /* Zero the global flush/invalidate flags. These
3895 * will be modified as new domains are computed
3898 dev->invalidate_domains = 0;
3899 dev->flush_domains = 0;
3901 for (i = 0; i < args->buffer_count; i++) {
3902 struct drm_gem_object *obj = object_list[i];
3904 /* Compute new gpu domains and update invalidate/flush */
3905 i915_gem_object_set_to_gpu_domain(obj);
3908 i915_verify_inactive(dev, __FILE__, __LINE__);
3910 if (dev->invalidate_domains | dev->flush_domains) {
3912 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3914 dev->invalidate_domains,
3915 dev->flush_domains);
3918 dev->invalidate_domains,
3919 dev->flush_domains);
3920 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3921 (void)i915_add_request(dev, file_priv,
3922 dev->flush_domains);
3925 for (i = 0; i < args->buffer_count; i++) {
3926 struct drm_gem_object *obj = object_list[i];
3927 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3928 uint32_t old_write_domain = obj->write_domain;
3930 obj->write_domain = obj->pending_write_domain;
3931 if (obj->write_domain)
3932 list_move_tail(&obj_priv->gpu_write_list,
3933 &dev_priv->mm.gpu_write_list);
3935 list_del_init(&obj_priv->gpu_write_list);
3937 trace_i915_gem_object_change_domain(obj,
3942 i915_verify_inactive(dev, __FILE__, __LINE__);
3945 for (i = 0; i < args->buffer_count; i++) {
3946 i915_gem_object_check_coherency(object_list[i],
3947 exec_list[i].handle);
3952 i915_gem_dump_object(batch_obj,
3958 /* Exec the batchbuffer */
3959 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3961 DRM_ERROR("dispatch failed %d\n", ret);
3966 * Ensure that the commands in the batch buffer are
3967 * finished before the interrupt fires
3969 flush_domains = i915_retire_commands(dev);
3971 i915_verify_inactive(dev, __FILE__, __LINE__);
3974 * Get a seqno representing the execution of the current buffer,
3975 * which we can wait on. We would like to mitigate these interrupts,
3976 * likely by only creating seqnos occasionally (so that we have
3977 * *some* interrupts representing completion of buffers that we can
3978 * wait on when trying to clear up gtt space).
3980 seqno = i915_add_request(dev, file_priv, flush_domains);
3982 for (i = 0; i < args->buffer_count; i++) {
3983 struct drm_gem_object *obj = object_list[i];
3985 i915_gem_object_move_to_active(obj, seqno);
3987 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3991 i915_dump_lru(dev, __func__);
3994 i915_verify_inactive(dev, __FILE__, __LINE__);
3997 for (i = 0; i < pinned; i++)
3998 i915_gem_object_unpin(object_list[i]);
4000 for (i = 0; i < args->buffer_count; i++) {
4001 if (object_list[i]) {
4002 obj_priv = to_intel_bo(object_list[i]);
4003 obj_priv->in_execbuffer = false;
4005 drm_gem_object_unreference(object_list[i]);
4008 mutex_unlock(&dev->struct_mutex);
4011 /* Copy the updated relocations out regardless of current error
4012 * state. Failure to update the relocs would mean that the next
4013 * time userland calls execbuf, it would do so with presumed offset
4014 * state that didn't match the actual object state.
4016 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4019 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4025 drm_free_large(object_list);
4032 * Legacy execbuffer just creates an exec2 list from the original exec object
4033 * list array and passes it to the real function.
4036 i915_gem_execbuffer(struct drm_device *dev, void *data,
4037 struct drm_file *file_priv)
4039 struct drm_i915_gem_execbuffer *args = data;
4040 struct drm_i915_gem_execbuffer2 exec2;
4041 struct drm_i915_gem_exec_object *exec_list = NULL;
4042 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4046 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4047 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4050 if (args->buffer_count < 1) {
4051 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4055 /* Copy in the exec list from userland */
4056 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4057 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4058 if (exec_list == NULL || exec2_list == NULL) {
4059 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4060 args->buffer_count);
4061 drm_free_large(exec_list);
4062 drm_free_large(exec2_list);
4065 ret = copy_from_user(exec_list,
4066 (struct drm_i915_relocation_entry __user *)
4067 (uintptr_t) args->buffers_ptr,
4068 sizeof(*exec_list) * args->buffer_count);
4070 DRM_ERROR("copy %d exec entries failed %d\n",
4071 args->buffer_count, ret);
4072 drm_free_large(exec_list);
4073 drm_free_large(exec2_list);
4077 for (i = 0; i < args->buffer_count; i++) {
4078 exec2_list[i].handle = exec_list[i].handle;
4079 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4080 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4081 exec2_list[i].alignment = exec_list[i].alignment;
4082 exec2_list[i].offset = exec_list[i].offset;
4084 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4086 exec2_list[i].flags = 0;
4089 exec2.buffers_ptr = args->buffers_ptr;
4090 exec2.buffer_count = args->buffer_count;
4091 exec2.batch_start_offset = args->batch_start_offset;
4092 exec2.batch_len = args->batch_len;
4093 exec2.DR1 = args->DR1;
4094 exec2.DR4 = args->DR4;
4095 exec2.num_cliprects = args->num_cliprects;
4096 exec2.cliprects_ptr = args->cliprects_ptr;
4099 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4101 /* Copy the new buffer offsets back to the user's exec list. */
4102 for (i = 0; i < args->buffer_count; i++)
4103 exec_list[i].offset = exec2_list[i].offset;
4104 /* ... and back out to userspace */
4105 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4106 (uintptr_t) args->buffers_ptr,
4108 sizeof(*exec_list) * args->buffer_count);
4111 DRM_ERROR("failed to copy %d exec entries "
4112 "back to user (%d)\n",
4113 args->buffer_count, ret);
4117 drm_free_large(exec_list);
4118 drm_free_large(exec2_list);
4123 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4124 struct drm_file *file_priv)
4126 struct drm_i915_gem_execbuffer2 *args = data;
4127 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4131 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4132 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4135 if (args->buffer_count < 1) {
4136 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4140 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4141 if (exec2_list == NULL) {
4142 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4143 args->buffer_count);
4146 ret = copy_from_user(exec2_list,
4147 (struct drm_i915_relocation_entry __user *)
4148 (uintptr_t) args->buffers_ptr,
4149 sizeof(*exec2_list) * args->buffer_count);
4151 DRM_ERROR("copy %d exec entries failed %d\n",
4152 args->buffer_count, ret);
4153 drm_free_large(exec2_list);
4157 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4159 /* Copy the new buffer offsets back to the user's exec list. */
4160 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4161 (uintptr_t) args->buffers_ptr,
4163 sizeof(*exec2_list) * args->buffer_count);
4166 DRM_ERROR("failed to copy %d exec entries "
4167 "back to user (%d)\n",
4168 args->buffer_count, ret);
4172 drm_free_large(exec2_list);
4177 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4179 struct drm_device *dev = obj->dev;
4180 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4183 i915_verify_inactive(dev, __FILE__, __LINE__);
4184 if (obj_priv->gtt_space == NULL) {
4185 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4190 obj_priv->pin_count++;
4192 /* If the object is not active and not pending a flush,
4193 * remove it from the inactive list
4195 if (obj_priv->pin_count == 1) {
4196 atomic_inc(&dev->pin_count);
4197 atomic_add(obj->size, &dev->pin_memory);
4198 if (!obj_priv->active &&
4199 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4200 !list_empty(&obj_priv->list))
4201 list_del_init(&obj_priv->list);
4203 i915_verify_inactive(dev, __FILE__, __LINE__);
4209 i915_gem_object_unpin(struct drm_gem_object *obj)
4211 struct drm_device *dev = obj->dev;
4212 drm_i915_private_t *dev_priv = dev->dev_private;
4213 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4215 i915_verify_inactive(dev, __FILE__, __LINE__);
4216 obj_priv->pin_count--;
4217 BUG_ON(obj_priv->pin_count < 0);
4218 BUG_ON(obj_priv->gtt_space == NULL);
4220 /* If the object is no longer pinned, and is
4221 * neither active nor being flushed, then stick it on
4224 if (obj_priv->pin_count == 0) {
4225 if (!obj_priv->active &&
4226 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4227 list_move_tail(&obj_priv->list,
4228 &dev_priv->mm.inactive_list);
4229 atomic_dec(&dev->pin_count);
4230 atomic_sub(obj->size, &dev->pin_memory);
4232 i915_verify_inactive(dev, __FILE__, __LINE__);
4236 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4237 struct drm_file *file_priv)
4239 struct drm_i915_gem_pin *args = data;
4240 struct drm_gem_object *obj;
4241 struct drm_i915_gem_object *obj_priv;
4244 mutex_lock(&dev->struct_mutex);
4246 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4248 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4250 mutex_unlock(&dev->struct_mutex);
4253 obj_priv = to_intel_bo(obj);
4255 if (obj_priv->madv != I915_MADV_WILLNEED) {
4256 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4257 drm_gem_object_unreference(obj);
4258 mutex_unlock(&dev->struct_mutex);
4262 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4263 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4265 drm_gem_object_unreference(obj);
4266 mutex_unlock(&dev->struct_mutex);
4270 obj_priv->user_pin_count++;
4271 obj_priv->pin_filp = file_priv;
4272 if (obj_priv->user_pin_count == 1) {
4273 ret = i915_gem_object_pin(obj, args->alignment);
4275 drm_gem_object_unreference(obj);
4276 mutex_unlock(&dev->struct_mutex);
4281 /* XXX - flush the CPU caches for pinned objects
4282 * as the X server doesn't manage domains yet
4284 i915_gem_object_flush_cpu_write_domain(obj);
4285 args->offset = obj_priv->gtt_offset;
4286 drm_gem_object_unreference(obj);
4287 mutex_unlock(&dev->struct_mutex);
4293 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4294 struct drm_file *file_priv)
4296 struct drm_i915_gem_pin *args = data;
4297 struct drm_gem_object *obj;
4298 struct drm_i915_gem_object *obj_priv;
4300 mutex_lock(&dev->struct_mutex);
4302 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4304 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4306 mutex_unlock(&dev->struct_mutex);
4310 obj_priv = to_intel_bo(obj);
4311 if (obj_priv->pin_filp != file_priv) {
4312 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4314 drm_gem_object_unreference(obj);
4315 mutex_unlock(&dev->struct_mutex);
4318 obj_priv->user_pin_count--;
4319 if (obj_priv->user_pin_count == 0) {
4320 obj_priv->pin_filp = NULL;
4321 i915_gem_object_unpin(obj);
4324 drm_gem_object_unreference(obj);
4325 mutex_unlock(&dev->struct_mutex);
4330 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4331 struct drm_file *file_priv)
4333 struct drm_i915_gem_busy *args = data;
4334 struct drm_gem_object *obj;
4335 struct drm_i915_gem_object *obj_priv;
4337 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4339 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4344 mutex_lock(&dev->struct_mutex);
4345 /* Update the active list for the hardware's current position.
4346 * Otherwise this only updates on a delayed timer or when irqs are
4347 * actually unmasked, and our working set ends up being larger than
4350 i915_gem_retire_requests(dev);
4352 obj_priv = to_intel_bo(obj);
4353 /* Don't count being on the flushing list against the object being
4354 * done. Otherwise, a buffer left on the flushing list but not getting
4355 * flushed (because nobody's flushing that domain) won't ever return
4356 * unbusy and get reused by libdrm's bo cache. The other expected
4357 * consumer of this interface, OpenGL's occlusion queries, also specs
4358 * that the objects get unbusy "eventually" without any interference.
4360 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4362 drm_gem_object_unreference(obj);
4363 mutex_unlock(&dev->struct_mutex);
4368 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4369 struct drm_file *file_priv)
4371 return i915_gem_ring_throttle(dev, file_priv);
4375 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4376 struct drm_file *file_priv)
4378 struct drm_i915_gem_madvise *args = data;
4379 struct drm_gem_object *obj;
4380 struct drm_i915_gem_object *obj_priv;
4382 switch (args->madv) {
4383 case I915_MADV_DONTNEED:
4384 case I915_MADV_WILLNEED:
4390 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4392 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4397 mutex_lock(&dev->struct_mutex);
4398 obj_priv = to_intel_bo(obj);
4400 if (obj_priv->pin_count) {
4401 drm_gem_object_unreference(obj);
4402 mutex_unlock(&dev->struct_mutex);
4404 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4408 if (obj_priv->madv != __I915_MADV_PURGED)
4409 obj_priv->madv = args->madv;
4411 /* if the object is no longer bound, discard its backing storage */
4412 if (i915_gem_object_is_purgeable(obj_priv) &&
4413 obj_priv->gtt_space == NULL)
4414 i915_gem_object_truncate(obj);
4416 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4418 drm_gem_object_unreference(obj);
4419 mutex_unlock(&dev->struct_mutex);
4424 int i915_gem_init_object(struct drm_gem_object *obj)
4426 struct drm_i915_gem_object *obj_priv;
4428 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4429 if (obj_priv == NULL)
4433 * We've just allocated pages from the kernel,
4434 * so they've just been written by the CPU with
4435 * zeros. They'll need to be clflushed before we
4436 * use them with the GPU.
4438 obj->write_domain = I915_GEM_DOMAIN_CPU;
4439 obj->read_domains = I915_GEM_DOMAIN_CPU;
4441 obj_priv->agp_type = AGP_USER_MEMORY;
4443 obj->driver_private = obj_priv;
4444 obj_priv->obj = obj;
4445 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4446 INIT_LIST_HEAD(&obj_priv->list);
4447 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4448 INIT_LIST_HEAD(&obj_priv->fence_list);
4449 obj_priv->madv = I915_MADV_WILLNEED;
4451 trace_i915_gem_object_create(obj);
4456 void i915_gem_free_object(struct drm_gem_object *obj)
4458 struct drm_device *dev = obj->dev;
4459 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4461 trace_i915_gem_object_destroy(obj);
4463 while (obj_priv->pin_count > 0)
4464 i915_gem_object_unpin(obj);
4466 if (obj_priv->phys_obj)
4467 i915_gem_detach_phys_object(dev, obj);
4469 i915_gem_object_unbind(obj);
4471 if (obj_priv->mmap_offset)
4472 i915_gem_free_mmap_offset(obj);
4474 kfree(obj_priv->page_cpu_valid);
4475 kfree(obj_priv->bit_17);
4476 kfree(obj->driver_private);
4479 /** Unbinds all inactive objects. */
4481 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4483 drm_i915_private_t *dev_priv = dev->dev_private;
4485 while (!list_empty(&dev_priv->mm.inactive_list)) {
4486 struct drm_gem_object *obj;
4489 obj = list_first_entry(&dev_priv->mm.inactive_list,
4490 struct drm_i915_gem_object,
4493 ret = i915_gem_object_unbind(obj);
4495 DRM_ERROR("Error unbinding object: %d\n", ret);
4504 i915_gem_idle(struct drm_device *dev)
4506 drm_i915_private_t *dev_priv = dev->dev_private;
4509 mutex_lock(&dev->struct_mutex);
4511 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4512 mutex_unlock(&dev->struct_mutex);
4516 ret = i915_gpu_idle(dev);
4518 mutex_unlock(&dev->struct_mutex);
4522 /* Under UMS, be paranoid and evict. */
4523 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4524 ret = i915_gem_evict_from_inactive_list(dev);
4526 mutex_unlock(&dev->struct_mutex);
4531 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4532 * We need to replace this with a semaphore, or something.
4533 * And not confound mm.suspended!
4535 dev_priv->mm.suspended = 1;
4536 del_timer(&dev_priv->hangcheck_timer);
4538 i915_kernel_lost_context(dev);
4539 i915_gem_cleanup_ringbuffer(dev);
4541 mutex_unlock(&dev->struct_mutex);
4543 /* Cancel the retire work handler, which should be idle now. */
4544 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4550 i915_gem_init_hws(struct drm_device *dev)
4552 drm_i915_private_t *dev_priv = dev->dev_private;
4553 struct drm_gem_object *obj;
4554 struct drm_i915_gem_object *obj_priv;
4557 /* If we need a physical address for the status page, it's already
4558 * initialized at driver load time.
4560 if (!I915_NEED_GFX_HWS(dev))
4563 obj = drm_gem_object_alloc(dev, 4096);
4565 DRM_ERROR("Failed to allocate status page\n");
4568 obj_priv = to_intel_bo(obj);
4569 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4571 ret = i915_gem_object_pin(obj, 4096);
4573 drm_gem_object_unreference(obj);
4577 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4579 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4580 if (dev_priv->hw_status_page == NULL) {
4581 DRM_ERROR("Failed to map status page.\n");
4582 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4583 i915_gem_object_unpin(obj);
4584 drm_gem_object_unreference(obj);
4587 dev_priv->hws_obj = obj;
4588 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4590 I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
4591 I915_READ(HWS_PGA_GEN6); /* posting read */
4593 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4594 I915_READ(HWS_PGA); /* posting read */
4596 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4602 i915_gem_cleanup_hws(struct drm_device *dev)
4604 drm_i915_private_t *dev_priv = dev->dev_private;
4605 struct drm_gem_object *obj;
4606 struct drm_i915_gem_object *obj_priv;
4608 if (dev_priv->hws_obj == NULL)
4611 obj = dev_priv->hws_obj;
4612 obj_priv = to_intel_bo(obj);
4614 kunmap(obj_priv->pages[0]);
4615 i915_gem_object_unpin(obj);
4616 drm_gem_object_unreference(obj);
4617 dev_priv->hws_obj = NULL;
4619 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4620 dev_priv->hw_status_page = NULL;
4622 /* Write high address into HWS_PGA when disabling. */
4623 I915_WRITE(HWS_PGA, 0x1ffff000);
4627 i915_gem_init_ringbuffer(struct drm_device *dev)
4629 drm_i915_private_t *dev_priv = dev->dev_private;
4630 struct drm_gem_object *obj;
4631 struct drm_i915_gem_object *obj_priv;
4632 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4636 ret = i915_gem_init_hws(dev);
4640 obj = drm_gem_object_alloc(dev, 128 * 1024);
4642 DRM_ERROR("Failed to allocate ringbuffer\n");
4643 i915_gem_cleanup_hws(dev);
4646 obj_priv = to_intel_bo(obj);
4648 ret = i915_gem_object_pin(obj, 4096);
4650 drm_gem_object_unreference(obj);
4651 i915_gem_cleanup_hws(dev);
4655 /* Set up the kernel mapping for the ring. */
4656 ring->Size = obj->size;
4658 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4659 ring->map.size = obj->size;
4661 ring->map.flags = 0;
4664 drm_core_ioremap_wc(&ring->map, dev);
4665 if (ring->map.handle == NULL) {
4666 DRM_ERROR("Failed to map ringbuffer.\n");
4667 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4668 i915_gem_object_unpin(obj);
4669 drm_gem_object_unreference(obj);
4670 i915_gem_cleanup_hws(dev);
4673 ring->ring_obj = obj;
4674 ring->virtual_start = ring->map.handle;
4676 /* Stop the ring if it's running. */
4677 I915_WRITE(PRB0_CTL, 0);
4678 I915_WRITE(PRB0_TAIL, 0);
4679 I915_WRITE(PRB0_HEAD, 0);
4681 /* Initialize the ring. */
4682 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4683 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4685 /* G45 ring initialization fails to reset head to zero */
4687 DRM_ERROR("Ring head not reset to zero "
4688 "ctl %08x head %08x tail %08x start %08x\n",
4689 I915_READ(PRB0_CTL),
4690 I915_READ(PRB0_HEAD),
4691 I915_READ(PRB0_TAIL),
4692 I915_READ(PRB0_START));
4693 I915_WRITE(PRB0_HEAD, 0);
4695 DRM_ERROR("Ring head forced to zero "
4696 "ctl %08x head %08x tail %08x start %08x\n",
4697 I915_READ(PRB0_CTL),
4698 I915_READ(PRB0_HEAD),
4699 I915_READ(PRB0_TAIL),
4700 I915_READ(PRB0_START));
4703 I915_WRITE(PRB0_CTL,
4704 ((obj->size - 4096) & RING_NR_PAGES) |
4708 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4710 /* If the head is still not zero, the ring is dead */
4712 DRM_ERROR("Ring initialization failed "
4713 "ctl %08x head %08x tail %08x start %08x\n",
4714 I915_READ(PRB0_CTL),
4715 I915_READ(PRB0_HEAD),
4716 I915_READ(PRB0_TAIL),
4717 I915_READ(PRB0_START));
4721 /* Update our cache of the ring state */
4722 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4723 i915_kernel_lost_context(dev);
4725 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4726 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4727 ring->space = ring->head - (ring->tail + 8);
4728 if (ring->space < 0)
4729 ring->space += ring->Size;
4732 if (IS_I9XX(dev) && !IS_GEN3(dev)) {
4734 (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
4741 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4743 drm_i915_private_t *dev_priv = dev->dev_private;
4745 if (dev_priv->ring.ring_obj == NULL)
4748 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4750 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4751 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4752 dev_priv->ring.ring_obj = NULL;
4753 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4755 i915_gem_cleanup_hws(dev);
4759 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4760 struct drm_file *file_priv)
4762 drm_i915_private_t *dev_priv = dev->dev_private;
4765 if (drm_core_check_feature(dev, DRIVER_MODESET))
4768 if (atomic_read(&dev_priv->mm.wedged)) {
4769 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4770 atomic_set(&dev_priv->mm.wedged, 0);
4773 mutex_lock(&dev->struct_mutex);
4774 dev_priv->mm.suspended = 0;
4776 ret = i915_gem_init_ringbuffer(dev);
4778 mutex_unlock(&dev->struct_mutex);
4782 spin_lock(&dev_priv->mm.active_list_lock);
4783 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4784 spin_unlock(&dev_priv->mm.active_list_lock);
4786 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4787 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4788 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4789 mutex_unlock(&dev->struct_mutex);
4791 drm_irq_install(dev);
4797 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4798 struct drm_file *file_priv)
4800 if (drm_core_check_feature(dev, DRIVER_MODESET))
4803 drm_irq_uninstall(dev);
4804 return i915_gem_idle(dev);
4808 i915_gem_lastclose(struct drm_device *dev)
4812 if (drm_core_check_feature(dev, DRIVER_MODESET))
4815 ret = i915_gem_idle(dev);
4817 DRM_ERROR("failed to idle hardware: %d\n", ret);
4821 i915_gem_load(struct drm_device *dev)
4824 drm_i915_private_t *dev_priv = dev->dev_private;
4826 spin_lock_init(&dev_priv->mm.active_list_lock);
4827 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4828 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4829 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4830 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4831 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4832 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4833 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4834 i915_gem_retire_work_handler);
4835 dev_priv->mm.next_gem_seqno = 1;
4837 spin_lock(&shrink_list_lock);
4838 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4839 spin_unlock(&shrink_list_lock);
4841 /* Old X drivers will take 0-2 for front, back, depth buffers */
4842 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4843 dev_priv->fence_reg_start = 3;
4845 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4846 dev_priv->num_fence_regs = 16;
4848 dev_priv->num_fence_regs = 8;
4850 /* Initialize fence registers to zero */
4851 if (IS_I965G(dev)) {
4852 for (i = 0; i < 16; i++)
4853 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4855 for (i = 0; i < 8; i++)
4856 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4857 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4858 for (i = 0; i < 8; i++)
4859 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4861 i915_gem_detect_bit_6_swizzle(dev);
4862 init_waitqueue_head(&dev_priv->pending_flip_queue);
4866 * Create a physically contiguous memory object for this object
4867 * e.g. for cursor + overlay regs
4869 int i915_gem_init_phys_object(struct drm_device *dev,
4872 drm_i915_private_t *dev_priv = dev->dev_private;
4873 struct drm_i915_gem_phys_object *phys_obj;
4876 if (dev_priv->mm.phys_objs[id - 1] || !size)
4879 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4885 phys_obj->handle = drm_pci_alloc(dev, size, 0);
4886 if (!phys_obj->handle) {
4891 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4894 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4902 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4904 drm_i915_private_t *dev_priv = dev->dev_private;
4905 struct drm_i915_gem_phys_object *phys_obj;
4907 if (!dev_priv->mm.phys_objs[id - 1])
4910 phys_obj = dev_priv->mm.phys_objs[id - 1];
4911 if (phys_obj->cur_obj) {
4912 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4916 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4918 drm_pci_free(dev, phys_obj->handle);
4920 dev_priv->mm.phys_objs[id - 1] = NULL;
4923 void i915_gem_free_all_phys_object(struct drm_device *dev)
4927 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4928 i915_gem_free_phys_object(dev, i);
4931 void i915_gem_detach_phys_object(struct drm_device *dev,
4932 struct drm_gem_object *obj)
4934 struct drm_i915_gem_object *obj_priv;
4939 obj_priv = to_intel_bo(obj);
4940 if (!obj_priv->phys_obj)
4943 ret = i915_gem_object_get_pages(obj, 0);
4947 page_count = obj->size / PAGE_SIZE;
4949 for (i = 0; i < page_count; i++) {
4950 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4951 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4953 memcpy(dst, src, PAGE_SIZE);
4954 kunmap_atomic(dst, KM_USER0);
4956 drm_clflush_pages(obj_priv->pages, page_count);
4957 drm_agp_chipset_flush(dev);
4959 i915_gem_object_put_pages(obj);
4961 obj_priv->phys_obj->cur_obj = NULL;
4962 obj_priv->phys_obj = NULL;
4966 i915_gem_attach_phys_object(struct drm_device *dev,
4967 struct drm_gem_object *obj, int id)
4969 drm_i915_private_t *dev_priv = dev->dev_private;
4970 struct drm_i915_gem_object *obj_priv;
4975 if (id > I915_MAX_PHYS_OBJECT)
4978 obj_priv = to_intel_bo(obj);
4980 if (obj_priv->phys_obj) {
4981 if (obj_priv->phys_obj->id == id)
4983 i915_gem_detach_phys_object(dev, obj);
4987 /* create a new object */
4988 if (!dev_priv->mm.phys_objs[id - 1]) {
4989 ret = i915_gem_init_phys_object(dev, id,
4992 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4997 /* bind to the object */
4998 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4999 obj_priv->phys_obj->cur_obj = obj;
5001 ret = i915_gem_object_get_pages(obj, 0);
5003 DRM_ERROR("failed to get page list\n");
5007 page_count = obj->size / PAGE_SIZE;
5009 for (i = 0; i < page_count; i++) {
5010 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
5011 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5013 memcpy(dst, src, PAGE_SIZE);
5014 kunmap_atomic(src, KM_USER0);
5017 i915_gem_object_put_pages(obj);
5025 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5026 struct drm_i915_gem_pwrite *args,
5027 struct drm_file *file_priv)
5029 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5032 char __user *user_data;
5034 user_data = (char __user *) (uintptr_t) args->data_ptr;
5035 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5037 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5038 ret = copy_from_user(obj_addr, user_data, args->size);
5042 drm_agp_chipset_flush(dev);
5046 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5048 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5050 /* Clean up our request list when the client is going away, so that
5051 * later retire_requests won't dereference our soon-to-be-gone
5054 mutex_lock(&dev->struct_mutex);
5055 while (!list_empty(&i915_file_priv->mm.request_list))
5056 list_del_init(i915_file_priv->mm.request_list.next);
5057 mutex_unlock(&dev->struct_mutex);
5061 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5063 drm_i915_private_t *dev_priv, *next_dev;
5064 struct drm_i915_gem_object *obj_priv, *next_obj;
5066 int would_deadlock = 1;
5068 /* "fast-path" to count number of available objects */
5069 if (nr_to_scan == 0) {
5070 spin_lock(&shrink_list_lock);
5071 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5072 struct drm_device *dev = dev_priv->dev;
5074 if (mutex_trylock(&dev->struct_mutex)) {
5075 list_for_each_entry(obj_priv,
5076 &dev_priv->mm.inactive_list,
5079 mutex_unlock(&dev->struct_mutex);
5082 spin_unlock(&shrink_list_lock);
5084 return (cnt / 100) * sysctl_vfs_cache_pressure;
5087 spin_lock(&shrink_list_lock);
5089 /* first scan for clean buffers */
5090 list_for_each_entry_safe(dev_priv, next_dev,
5091 &shrink_list, mm.shrink_list) {
5092 struct drm_device *dev = dev_priv->dev;
5094 if (! mutex_trylock(&dev->struct_mutex))
5097 spin_unlock(&shrink_list_lock);
5099 i915_gem_retire_requests(dev);
5101 list_for_each_entry_safe(obj_priv, next_obj,
5102 &dev_priv->mm.inactive_list,
5104 if (i915_gem_object_is_purgeable(obj_priv)) {
5105 i915_gem_object_unbind(obj_priv->obj);
5106 if (--nr_to_scan <= 0)
5111 spin_lock(&shrink_list_lock);
5112 mutex_unlock(&dev->struct_mutex);
5116 if (nr_to_scan <= 0)
5120 /* second pass, evict/count anything still on the inactive list */
5121 list_for_each_entry_safe(dev_priv, next_dev,
5122 &shrink_list, mm.shrink_list) {
5123 struct drm_device *dev = dev_priv->dev;
5125 if (! mutex_trylock(&dev->struct_mutex))
5128 spin_unlock(&shrink_list_lock);
5130 list_for_each_entry_safe(obj_priv, next_obj,
5131 &dev_priv->mm.inactive_list,
5133 if (nr_to_scan > 0) {
5134 i915_gem_object_unbind(obj_priv->obj);
5140 spin_lock(&shrink_list_lock);
5141 mutex_unlock(&dev->struct_mutex);
5146 spin_unlock(&shrink_list_lock);
5151 return (cnt / 100) * sysctl_vfs_cache_pressure;
5156 static struct shrinker shrinker = {
5157 .shrink = i915_gem_shrink,
5158 .seeks = DEFAULT_SEEKS,
5162 i915_gem_shrinker_init(void)
5164 register_shrinker(&shrinker);
5168 i915_gem_shrinker_exit(void)
5170 unregister_shrinker(&shrinker);