drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/swap.h>
  35 #include <linux/pci.h>
  36
  37 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  38
  39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  43                                              int write);
  44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  45                                                      uint64_t offset,
  46                                                      uint64_t size);
  47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  50                                            unsigned alignment);
  51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
  53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
  54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  55                                 struct drm_i915_gem_pwrite *args,
  56                                 struct drm_file *file_priv);
  57
  58 static LIST_HEAD(shrink_list);
  59 static DEFINE_SPINLOCK(shrink_list_lock);
  60
  61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  62                      unsigned long end)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65
  66         if (start >= end ||
  67             (start & (PAGE_SIZE - 1)) != 0 ||
  68             (end & (PAGE_SIZE - 1)) != 0) {
  69                 return -EINVAL;
  70         }
  71
  72         drm_mm_init(&dev_priv->mm.gtt_space, start,
  73                     end - start);
  74
  75         dev->gtt_total = (uint32_t) (end - start);
  76
  77         return 0;
  78 }
  79
  80 int
  81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  82                     struct drm_file *file_priv)
  83 {
  84         struct drm_i915_gem_init *args = data;
  85         int ret;
  86
  87         mutex_lock(&dev->struct_mutex);
  88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  89         mutex_unlock(&dev->struct_mutex);
  90
  91         return ret;
  92 }
  93
  94 int
  95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  96                             struct drm_file *file_priv)
  97 {
  98         struct drm_i915_gem_get_aperture *args = data;
  99
 100         if (!(dev->driver->driver_features & DRIVER_GEM))
 101                 return -ENODEV;
 102
 103         args->aper_size = dev->gtt_total;
 104         args->aper_available_size = (args->aper_size -
 105                                      atomic_read(&dev->pin_memory));
 106
 107         return 0;
 108 }
 109
 110
 111 /**
 112  * Creates a new mm object and returns a handle to it.
 113  */
 114 int
 115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 116                       struct drm_file *file_priv)
 117 {
 118         struct drm_i915_gem_create *args = data;
 119         struct drm_gem_object *obj;
 120         int ret;
 121         u32 handle;
 122
 123         args->size = roundup(args->size, PAGE_SIZE);
 124
 125         /* Allocate the new object */
 126         obj = drm_gem_object_alloc(dev, args->size);
 127         if (obj == NULL)
 128                 return -ENOMEM;
 129
 130         ret = drm_gem_handle_create(file_priv, obj, &handle);
 131         mutex_lock(&dev->struct_mutex);
 132         drm_gem_object_handle_unreference(obj);
 133         mutex_unlock(&dev->struct_mutex);
 134
 135         if (ret)
 136                 return ret;
 137
 138         args->handle = handle;
 139
 140         return 0;
 141 }
 142
 143 static inline int
 144 fast_shmem_read(struct page **pages,
 145                 loff_t page_base, int page_offset,
 146                 char __user *data,
 147                 int length)
 148 {
 149         char __iomem *vaddr;
 150         int unwritten;
 151
 152         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 153         if (vaddr == NULL)
 154                 return -ENOMEM;
 155         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 156         kunmap_atomic(vaddr, KM_USER0);
 157
 158         if (unwritten)
 159                 return -EFAULT;
 160
 161         return 0;
 162 }
 163
 164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 165 {
 166         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 167         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 168
 169         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 170                 obj_priv->tiling_mode != I915_TILING_NONE;
 171 }
 172
 173 static inline int
 174 slow_shmem_copy(struct page *dst_page,
 175                 int dst_offset,
 176                 struct page *src_page,
 177                 int src_offset,
 178                 int length)
 179 {
 180         char *dst_vaddr, *src_vaddr;
 181
 182         dst_vaddr = kmap_atomic(dst_page, KM_USER0);
 183         if (dst_vaddr == NULL)
 184                 return -ENOMEM;
 185
 186         src_vaddr = kmap_atomic(src_page, KM_USER1);
 187         if (src_vaddr == NULL) {
 188                 kunmap_atomic(dst_vaddr, KM_USER0);
 189                 return -ENOMEM;
 190         }
 191
 192         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 193
 194         kunmap_atomic(src_vaddr, KM_USER1);
 195         kunmap_atomic(dst_vaddr, KM_USER0);
 196
 197         return 0;
 198 }
 199
 200 static inline int
 201 slow_shmem_bit17_copy(struct page *gpu_page,
 202                       int gpu_offset,
 203                       struct page *cpu_page,
 204                       int cpu_offset,
 205                       int length,
 206                       int is_read)
 207 {
 208         char *gpu_vaddr, *cpu_vaddr;
 209
 210         /* Use the unswizzled path if this page isn't affected. */
 211         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 212                 if (is_read)
 213                         return slow_shmem_copy(cpu_page, cpu_offset,
 214                                                gpu_page, gpu_offset, length);
 215                 else
 216                         return slow_shmem_copy(gpu_page, gpu_offset,
 217                                                cpu_page, cpu_offset, length);
 218         }
 219
 220         gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
 221         if (gpu_vaddr == NULL)
 222                 return -ENOMEM;
 223
 224         cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
 225         if (cpu_vaddr == NULL) {
 226                 kunmap_atomic(gpu_vaddr, KM_USER0);
 227                 return -ENOMEM;
 228         }
 229
 230         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 231          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 232          */
 233         while (length > 0) {
 234                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 235                 int this_length = min(cacheline_end - gpu_offset, length);
 236                 int swizzled_gpu_offset = gpu_offset ^ 64;
 237
 238                 if (is_read) {
 239                         memcpy(cpu_vaddr + cpu_offset,
 240                                gpu_vaddr + swizzled_gpu_offset,
 241                                this_length);
 242                 } else {
 243                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 244                                cpu_vaddr + cpu_offset,
 245                                this_length);
 246                 }
 247                 cpu_offset += this_length;
 248                 gpu_offset += this_length;
 249                 length -= this_length;
 250         }
 251
 252         kunmap_atomic(cpu_vaddr, KM_USER1);
 253         kunmap_atomic(gpu_vaddr, KM_USER0);
 254
 255         return 0;
 256 }
 257
 258 /**
 259  * This is the fast shmem pread path, which attempts to copy_from_user directly
 260  * from the backing pages of the object to the user's address space.  On a
 261  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 262  */
 263 static int
 264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 265                           struct drm_i915_gem_pread *args,
 266                           struct drm_file *file_priv)
 267 {
 268         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 269         ssize_t remain;
 270         loff_t offset, page_base;
 271         char __user *user_data;
 272         int page_offset, page_length;
 273         int ret;
 274
 275         user_data = (char __user *) (uintptr_t) args->data_ptr;
 276         remain = args->size;
 277
 278         mutex_lock(&dev->struct_mutex);
 279
 280         ret = i915_gem_object_get_pages(obj, 0);
 281         if (ret != 0)
 282                 goto fail_unlock;
 283
 284         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 285                                                         args->size);
 286         if (ret != 0)
 287                 goto fail_put_pages;
 288
 289         obj_priv = obj->driver_private;
 290         offset = args->offset;
 291
 292         while (remain > 0) {
 293                 /* Operation in this page
 294                  *
 295                  * page_base = page offset within aperture
 296                  * page_offset = offset within page
 297                  * page_length = bytes to copy for this page
 298                  */
 299                 page_base = (offset & ~(PAGE_SIZE-1));
 300                 page_offset = offset & (PAGE_SIZE-1);
 301                 page_length = remain;
 302                 if ((page_offset + remain) > PAGE_SIZE)
 303                         page_length = PAGE_SIZE - page_offset;
 304
 305                 ret = fast_shmem_read(obj_priv->pages,
 306                                       page_base, page_offset,
 307                                       user_data, page_length);
 308                 if (ret)
 309                         goto fail_put_pages;
 310
 311                 remain -= page_length;
 312                 user_data += page_length;
 313                 offset += page_length;
 314         }
 315
 316 fail_put_pages:
 317         i915_gem_object_put_pages(obj);
 318 fail_unlock:
 319         mutex_unlock(&dev->struct_mutex);
 320
 321         return ret;
 322 }
 323
 324 static int
 325 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 326 {
 327         int ret;
 328
 329         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 330
 331         /* If we've insufficient memory to map in the pages, attempt
 332          * to make some space by throwing out some old buffers.
 333          */
 334         if (ret == -ENOMEM) {
 335                 struct drm_device *dev = obj->dev;
 336
 337                 ret = i915_gem_evict_something(dev, obj->size);
 338                 if (ret)
 339                         return ret;
 340
 341                 ret = i915_gem_object_get_pages(obj, 0);
 342         }
 343
 344         return ret;
 345 }
 346
 347 /**
 348  * This is the fallback shmem pread path, which allocates temporary storage
 349  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 350  * can copy out of the object's backing pages while holding the struct mutex
 351  * and not take page faults.
 352  */
 353 static int
 354 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 355                           struct drm_i915_gem_pread *args,
 356                           struct drm_file *file_priv)
 357 {
 358         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 359         struct mm_struct *mm = current->mm;
 360         struct page **user_pages;
 361         ssize_t remain;
 362         loff_t offset, pinned_pages, i;
 363         loff_t first_data_page, last_data_page, num_pages;
 364         int shmem_page_index, shmem_page_offset;
 365         int data_page_index,  data_page_offset;
 366         int page_length;
 367         int ret;
 368         uint64_t data_ptr = args->data_ptr;
 369         int do_bit17_swizzling;
 370
 371         remain = args->size;
 372
 373         /* Pin the user pages containing the data.  We can't fault while
 374          * holding the struct mutex, yet we want to hold it while
 375          * dereferencing the user data.
 376          */
 377         first_data_page = data_ptr / PAGE_SIZE;
 378         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 379         num_pages = last_data_page - first_data_page + 1;
 380
 381         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 382         if (user_pages == NULL)
 383                 return -ENOMEM;
 384
 385         down_read(&mm->mmap_sem);
 386         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 387                                       num_pages, 1, 0, user_pages, NULL);
 388         up_read(&mm->mmap_sem);
 389         if (pinned_pages < num_pages) {
 390                 ret = -EFAULT;
 391                 goto fail_put_user_pages;
 392         }
 393
 394         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 395
 396         mutex_lock(&dev->struct_mutex);
 397
 398         ret = i915_gem_object_get_pages_or_evict(obj);
 399         if (ret)
 400                 goto fail_unlock;
 401
 402         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 403                                                         args->size);
 404         if (ret != 0)
 405                 goto fail_put_pages;
 406
 407         obj_priv = obj->driver_private;
 408         offset = args->offset;
 409
 410         while (remain > 0) {
 411                 /* Operation in this page
 412                  *
 413                  * shmem_page_index = page number within shmem file
 414                  * shmem_page_offset = offset within page in shmem file
 415                  * data_page_index = page number in get_user_pages return
 416                  * data_page_offset = offset with data_page_index page.
 417                  * page_length = bytes to copy for this page
 418                  */
 419                 shmem_page_index = offset / PAGE_SIZE;
 420                 shmem_page_offset = offset & ~PAGE_MASK;
 421                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 422                 data_page_offset = data_ptr & ~PAGE_MASK;
 423
 424                 page_length = remain;
 425                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 426                         page_length = PAGE_SIZE - shmem_page_offset;
 427                 if ((data_page_offset + page_length) > PAGE_SIZE)
 428                         page_length = PAGE_SIZE - data_page_offset;
 429
 430                 if (do_bit17_swizzling) {
 431                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 432                                                     shmem_page_offset,
 433                                                     user_pages[data_page_index],
 434                                                     data_page_offset,
 435                                                     page_length,
 436                                                     1);
 437                 } else {
 438                         ret = slow_shmem_copy(user_pages[data_page_index],
 439                                               data_page_offset,
 440                                               obj_priv->pages[shmem_page_index],
 441                                               shmem_page_offset,
 442                                               page_length);
 443                 }
 444                 if (ret)
 445                         goto fail_put_pages;
 446
 447                 remain -= page_length;
 448                 data_ptr += page_length;
 449                 offset += page_length;
 450         }
 451
 452 fail_put_pages:
 453         i915_gem_object_put_pages(obj);
 454 fail_unlock:
 455         mutex_unlock(&dev->struct_mutex);
 456 fail_put_user_pages:
 457         for (i = 0; i < pinned_pages; i++) {
 458                 SetPageDirty(user_pages[i]);
 459                 page_cache_release(user_pages[i]);
 460         }
 461         drm_free_large(user_pages);
 462
 463         return ret;
 464 }
 465
 466 /**
 467  * Reads data from the object referenced by handle.
 468  *
 469  * On error, the contents of *data are undefined.
 470  */
 471 int
 472 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 473                      struct drm_file *file_priv)
 474 {
 475         struct drm_i915_gem_pread *args = data;
 476         struct drm_gem_object *obj;
 477         struct drm_i915_gem_object *obj_priv;
 478         int ret;
 479
 480         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 481         if (obj == NULL)
 482                 return -EBADF;
 483         obj_priv = obj->driver_private;
 484
 485         /* Bounds check source.
 486          *
 487          * XXX: This could use review for overflow issues...
 488          */
 489         if (args->offset > obj->size || args->size > obj->size ||
 490             args->offset + args->size > obj->size) {
 491                 drm_gem_object_unreference(obj);
 492                 return -EINVAL;
 493         }
 494
 495         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 496                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 497         } else {
 498                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 499                 if (ret != 0)
 500                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 501                                                         file_priv);
 502         }
 503
 504         drm_gem_object_unreference(obj);
 505
 506         return ret;
 507 }
 508
 509 /* This is the fast write path which cannot handle
 510  * page faults in the source data
 511  */
 512
 513 static inline int
 514 fast_user_write(struct io_mapping *mapping,
 515                 loff_t page_base, int page_offset,
 516                 char __user *user_data,
 517                 int length)
 518 {
 519         char *vaddr_atomic;
 520         unsigned long unwritten;
 521
 522         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 523         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 524                                                       user_data, length);
 525         io_mapping_unmap_atomic(vaddr_atomic);
 526         if (unwritten)
 527                 return -EFAULT;
 528         return 0;
 529 }
 530
 531 /* Here's the write path which can sleep for
 532  * page faults
 533  */
 534
 535 static inline int
 536 slow_kernel_write(struct io_mapping *mapping,
 537                   loff_t gtt_base, int gtt_offset,
 538                   struct page *user_page, int user_offset,
 539                   int length)
 540 {
 541         char *src_vaddr, *dst_vaddr;
 542         unsigned long unwritten;
 543
 544         dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
 545         src_vaddr = kmap_atomic(user_page, KM_USER1);
 546         unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
 547                                                       src_vaddr + user_offset,
 548                                                       length);
 549         kunmap_atomic(src_vaddr, KM_USER1);
 550         io_mapping_unmap_atomic(dst_vaddr);
 551         if (unwritten)
 552                 return -EFAULT;
 553         return 0;
 554 }
 555
 556 static inline int
 557 fast_shmem_write(struct page **pages,
 558                  loff_t page_base, int page_offset,
 559                  char __user *data,
 560                  int length)
 561 {
 562         char __iomem *vaddr;
 563         unsigned long unwritten;
 564
 565         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 566         if (vaddr == NULL)
 567                 return -ENOMEM;
 568         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 569         kunmap_atomic(vaddr, KM_USER0);
 570
 571         if (unwritten)
 572                 return -EFAULT;
 573         return 0;
 574 }
 575
 576 /**
 577  * This is the fast pwrite path, where we copy the data directly from the
 578  * user into the GTT, uncached.
 579  */
 580 static int
 581 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 582                          struct drm_i915_gem_pwrite *args,
 583                          struct drm_file *file_priv)
 584 {
 585         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 586         drm_i915_private_t *dev_priv = dev->dev_private;
 587         ssize_t remain;
 588         loff_t offset, page_base;
 589         char __user *user_data;
 590         int page_offset, page_length;
 591         int ret;
 592
 593         user_data = (char __user *) (uintptr_t) args->data_ptr;
 594         remain = args->size;
 595         if (!access_ok(VERIFY_READ, user_data, remain))
 596                 return -EFAULT;
 597
 598
 599         mutex_lock(&dev->struct_mutex);
 600         ret = i915_gem_object_pin(obj, 0);
 601         if (ret) {
 602                 mutex_unlock(&dev->struct_mutex);
 603                 return ret;
 604         }
 605         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 606         if (ret)
 607                 goto fail;
 608
 609         obj_priv = obj->driver_private;
 610         offset = obj_priv->gtt_offset + args->offset;
 611
 612         while (remain > 0) {
 613                 /* Operation in this page
 614                  *
 615                  * page_base = page offset within aperture
 616                  * page_offset = offset within page
 617                  * page_length = bytes to copy for this page
 618                  */
 619                 page_base = (offset & ~(PAGE_SIZE-1));
 620                 page_offset = offset & (PAGE_SIZE-1);
 621                 page_length = remain;
 622                 if ((page_offset + remain) > PAGE_SIZE)
 623                         page_length = PAGE_SIZE - page_offset;
 624
 625                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 626                                        page_offset, user_data, page_length);
 627
 628                 /* If we get a fault while copying data, then (presumably) our
 629                  * source page isn't available.  Return the error and we'll
 630                  * retry in the slow path.
 631                  */
 632                 if (ret)
 633                         goto fail;
 634
 635                 remain -= page_length;
 636                 user_data += page_length;
 637                 offset += page_length;
 638         }
 639
 640 fail:
 641         i915_gem_object_unpin(obj);
 642         mutex_unlock(&dev->struct_mutex);
 643
 644         return ret;
 645 }
 646
 647 /**
 648  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 649  * the memory and maps it using kmap_atomic for copying.
 650  *
 651  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 652  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 653  */
 654 static int
 655 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 656                          struct drm_i915_gem_pwrite *args,
 657                          struct drm_file *file_priv)
 658 {
 659         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 660         drm_i915_private_t *dev_priv = dev->dev_private;
 661         ssize_t remain;
 662         loff_t gtt_page_base, offset;
 663         loff_t first_data_page, last_data_page, num_pages;
 664         loff_t pinned_pages, i;
 665         struct page **user_pages;
 666         struct mm_struct *mm = current->mm;
 667         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 668         int ret;
 669         uint64_t data_ptr = args->data_ptr;
 670
 671         remain = args->size;
 672
 673         /* Pin the user pages containing the data.  We can't fault while
 674          * holding the struct mutex, and all of the pwrite implementations
 675          * want to hold it while dereferencing the user data.
 676          */
 677         first_data_page = data_ptr / PAGE_SIZE;
 678         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 679         num_pages = last_data_page - first_data_page + 1;
 680
 681         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 682         if (user_pages == NULL)
 683                 return -ENOMEM;
 684
 685         down_read(&mm->mmap_sem);
 686         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 687                                       num_pages, 0, 0, user_pages, NULL);
 688         up_read(&mm->mmap_sem);
 689         if (pinned_pages < num_pages) {
 690                 ret = -EFAULT;
 691                 goto out_unpin_pages;
 692         }
 693
 694         mutex_lock(&dev->struct_mutex);
 695         ret = i915_gem_object_pin(obj, 0);
 696         if (ret)
 697                 goto out_unlock;
 698
 699         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 700         if (ret)
 701                 goto out_unpin_object;
 702
 703         obj_priv = obj->driver_private;
 704         offset = obj_priv->gtt_offset + args->offset;
 705
 706         while (remain > 0) {
 707                 /* Operation in this page
 708                  *
 709                  * gtt_page_base = page offset within aperture
 710                  * gtt_page_offset = offset within page in aperture
 711                  * data_page_index = page number in get_user_pages return
 712                  * data_page_offset = offset with data_page_index page.
 713                  * page_length = bytes to copy for this page
 714                  */
 715                 gtt_page_base = offset & PAGE_MASK;
 716                 gtt_page_offset = offset & ~PAGE_MASK;
 717                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 718                 data_page_offset = data_ptr & ~PAGE_MASK;
 719
 720                 page_length = remain;
 721                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 722                         page_length = PAGE_SIZE - gtt_page_offset;
 723                 if ((data_page_offset + page_length) > PAGE_SIZE)
 724                         page_length = PAGE_SIZE - data_page_offset;
 725
 726                 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
 727                                         gtt_page_base, gtt_page_offset,
 728                                         user_pages[data_page_index],
 729                                         data_page_offset,
 730                                         page_length);
 731
 732                 /* If we get a fault while copying data, then (presumably) our
 733                  * source page isn't available.  Return the error and we'll
 734                  * retry in the slow path.
 735                  */
 736                 if (ret)
 737                         goto out_unpin_object;
 738
 739                 remain -= page_length;
 740                 offset += page_length;
 741                 data_ptr += page_length;
 742         }
 743
 744 out_unpin_object:
 745         i915_gem_object_unpin(obj);
 746 out_unlock:
 747         mutex_unlock(&dev->struct_mutex);
 748 out_unpin_pages:
 749         for (i = 0; i < pinned_pages; i++)
 750                 page_cache_release(user_pages[i]);
 751         drm_free_large(user_pages);
 752
 753         return ret;
 754 }
 755
 756 /**
 757  * This is the fast shmem pwrite path, which attempts to directly
 758  * copy_from_user into the kmapped pages backing the object.
 759  */
 760 static int
 761 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 762                            struct drm_i915_gem_pwrite *args,
 763                            struct drm_file *file_priv)
 764 {
 765         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 766         ssize_t remain;
 767         loff_t offset, page_base;
 768         char __user *user_data;
 769         int page_offset, page_length;
 770         int ret;
 771
 772         user_data = (char __user *) (uintptr_t) args->data_ptr;
 773         remain = args->size;
 774
 775         mutex_lock(&dev->struct_mutex);
 776
 777         ret = i915_gem_object_get_pages(obj, 0);
 778         if (ret != 0)
 779                 goto fail_unlock;
 780
 781         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 782         if (ret != 0)
 783                 goto fail_put_pages;
 784
 785         obj_priv = obj->driver_private;
 786         offset = args->offset;
 787         obj_priv->dirty = 1;
 788
 789         while (remain > 0) {
 790                 /* Operation in this page
 791                  *
 792                  * page_base = page offset within aperture
 793                  * page_offset = offset within page
 794                  * page_length = bytes to copy for this page
 795                  */
 796                 page_base = (offset & ~(PAGE_SIZE-1));
 797                 page_offset = offset & (PAGE_SIZE-1);
 798                 page_length = remain;
 799                 if ((page_offset + remain) > PAGE_SIZE)
 800                         page_length = PAGE_SIZE - page_offset;
 801
 802                 ret = fast_shmem_write(obj_priv->pages,
 803                                        page_base, page_offset,
 804                                        user_data, page_length);
 805                 if (ret)
 806                         goto fail_put_pages;
 807
 808                 remain -= page_length;
 809                 user_data += page_length;
 810                 offset += page_length;
 811         }
 812
 813 fail_put_pages:
 814         i915_gem_object_put_pages(obj);
 815 fail_unlock:
 816         mutex_unlock(&dev->struct_mutex);
 817
 818         return ret;
 819 }
 820
 821 /**
 822  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 823  * the memory and maps it using kmap_atomic for copying.
 824  *
 825  * This avoids taking mmap_sem for faulting on the user's address while the
 826  * struct_mutex is held.
 827  */
 828 static int
 829 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 830                            struct drm_i915_gem_pwrite *args,
 831                            struct drm_file *file_priv)
 832 {
 833         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 834         struct mm_struct *mm = current->mm;
 835         struct page **user_pages;
 836         ssize_t remain;
 837         loff_t offset, pinned_pages, i;
 838         loff_t first_data_page, last_data_page, num_pages;
 839         int shmem_page_index, shmem_page_offset;
 840         int data_page_index,  data_page_offset;
 841         int page_length;
 842         int ret;
 843         uint64_t data_ptr = args->data_ptr;
 844         int do_bit17_swizzling;
 845
 846         remain = args->size;
 847
 848         /* Pin the user pages containing the data.  We can't fault while
 849          * holding the struct mutex, and all of the pwrite implementations
 850          * want to hold it while dereferencing the user data.
 851          */
 852         first_data_page = data_ptr / PAGE_SIZE;
 853         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 854         num_pages = last_data_page - first_data_page + 1;
 855
 856         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 857         if (user_pages == NULL)
 858                 return -ENOMEM;
 859
 860         down_read(&mm->mmap_sem);
 861         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 862                                       num_pages, 0, 0, user_pages, NULL);
 863         up_read(&mm->mmap_sem);
 864         if (pinned_pages < num_pages) {
 865                 ret = -EFAULT;
 866                 goto fail_put_user_pages;
 867         }
 868
 869         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 870
 871         mutex_lock(&dev->struct_mutex);
 872
 873         ret = i915_gem_object_get_pages_or_evict(obj);
 874         if (ret)
 875                 goto fail_unlock;
 876
 877         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 878         if (ret != 0)
 879                 goto fail_put_pages;
 880
 881         obj_priv = obj->driver_private;
 882         offset = args->offset;
 883         obj_priv->dirty = 1;
 884
 885         while (remain > 0) {
 886                 /* Operation in this page
 887                  *
 888                  * shmem_page_index = page number within shmem file
 889                  * shmem_page_offset = offset within page in shmem file
 890                  * data_page_index = page number in get_user_pages return
 891                  * data_page_offset = offset with data_page_index page.
 892                  * page_length = bytes to copy for this page
 893                  */
 894                 shmem_page_index = offset / PAGE_SIZE;
 895                 shmem_page_offset = offset & ~PAGE_MASK;
 896                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 897                 data_page_offset = data_ptr & ~PAGE_MASK;
 898
 899                 page_length = remain;
 900                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 901                         page_length = PAGE_SIZE - shmem_page_offset;
 902                 if ((data_page_offset + page_length) > PAGE_SIZE)
 903                         page_length = PAGE_SIZE - data_page_offset;
 904
 905                 if (do_bit17_swizzling) {
 906                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 907                                                     shmem_page_offset,
 908                                                     user_pages[data_page_index],
 909                                                     data_page_offset,
 910                                                     page_length,
 911                                                     0);
 912                 } else {
 913                         ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
 914                                               shmem_page_offset,
 915                                               user_pages[data_page_index],
 916                                               data_page_offset,
 917                                               page_length);
 918                 }
 919                 if (ret)
 920                         goto fail_put_pages;
 921
 922                 remain -= page_length;
 923                 data_ptr += page_length;
 924                 offset += page_length;
 925         }
 926
 927 fail_put_pages:
 928         i915_gem_object_put_pages(obj);
 929 fail_unlock:
 930         mutex_unlock(&dev->struct_mutex);
 931 fail_put_user_pages:
 932         for (i = 0; i < pinned_pages; i++)
 933                 page_cache_release(user_pages[i]);
 934         drm_free_large(user_pages);
 935
 936         return ret;
 937 }
 938
 939 /**
 940  * Writes data to the object referenced by handle.
 941  *
 942  * On error, the contents of the buffer that were to be modified are undefined.
 943  */
 944 int
 945 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 946                       struct drm_file *file_priv)
 947 {
 948         struct drm_i915_gem_pwrite *args = data;
 949         struct drm_gem_object *obj;
 950         struct drm_i915_gem_object *obj_priv;
 951         int ret = 0;
 952
 953         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 954         if (obj == NULL)
 955                 return -EBADF;
 956         obj_priv = obj->driver_private;
 957
 958         /* Bounds check destination.
 959          *
 960          * XXX: This could use review for overflow issues...
 961          */
 962         if (args->offset > obj->size || args->size > obj->size ||
 963             args->offset + args->size > obj->size) {
 964                 drm_gem_object_unreference(obj);
 965                 return -EINVAL;
 966         }
 967
 968         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 969          * it would end up going through the fenced access, and we'll get
 970          * different detiling behavior between reading and writing.
 971          * pread/pwrite currently are reading and writing from the CPU
 972          * perspective, requiring manual detiling by the client.
 973          */
 974         if (obj_priv->phys_obj)
 975                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 976         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 977                  dev->gtt_total != 0) {
 978                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 979                 if (ret == -EFAULT) {
 980                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 981                                                        file_priv);
 982                 }
 983         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 984                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 985         } else {
 986                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 987                 if (ret == -EFAULT) {
 988                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 989                                                          file_priv);
 990                 }
 991         }
 992
 993 #if WATCH_PWRITE
 994         if (ret)
 995                 DRM_INFO("pwrite failed %d\n", ret);
 996 #endif
 997
 998         drm_gem_object_unreference(obj);
 999
1000         return ret;
1001 }
1002
1003 /**
1004  * Called when user space prepares to use an object with the CPU, either
1005  * through the mmap ioctl's mapping or a GTT mapping.
1006  */
1007 int
1008 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1009                           struct drm_file *file_priv)
1010 {
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012         struct drm_i915_gem_set_domain *args = data;
1013         struct drm_gem_object *obj;
1014         struct drm_i915_gem_object *obj_priv;
1015         uint32_t read_domains = args->read_domains;
1016         uint32_t write_domain = args->write_domain;
1017         int ret;
1018
1019         if (!(dev->driver->driver_features & DRIVER_GEM))
1020                 return -ENODEV;
1021
1022         /* Only handle setting domains to types used by the CPU. */
1023         if (write_domain & I915_GEM_GPU_DOMAINS)
1024                 return -EINVAL;
1025
1026         if (read_domains & I915_GEM_GPU_DOMAINS)
1027                 return -EINVAL;
1028
1029         /* Having something in the write domain implies it's in the read
1030          * domain, and only that read domain.  Enforce that in the request.
1031          */
1032         if (write_domain != 0 && read_domains != write_domain)
1033                 return -EINVAL;
1034
1035         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036         if (obj == NULL)
1037                 return -EBADF;
1038         obj_priv = obj->driver_private;
1039
1040         mutex_lock(&dev->struct_mutex);
1041
1042         intel_mark_busy(dev, obj);
1043
1044 #if WATCH_BUF
1045         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1046                  obj, obj->size, read_domains, write_domain);
1047 #endif
1048         if (read_domains & I915_GEM_DOMAIN_GTT) {
1049                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1050
1051                 /* Update the LRU on the fence for the CPU access that's
1052                  * about to occur.
1053                  */
1054                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1055                         list_move_tail(&obj_priv->fence_list,
1056                                        &dev_priv->mm.fence_list);
1057                 }
1058
1059                 /* Silently promote "you're not bound, there was nothing to do"
1060                  * to success, since the client was just asking us to
1061                  * make sure everything was done.
1062                  */
1063                 if (ret == -EINVAL)
1064                         ret = 0;
1065         } else {
1066                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1067         }
1068
1069         drm_gem_object_unreference(obj);
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 /**
1075  * Called when user space has done writes to this buffer
1076  */
1077 int
1078 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079                       struct drm_file *file_priv)
1080 {
1081         struct drm_i915_gem_sw_finish *args = data;
1082         struct drm_gem_object *obj;
1083         struct drm_i915_gem_object *obj_priv;
1084         int ret = 0;
1085
1086         if (!(dev->driver->driver_features & DRIVER_GEM))
1087                 return -ENODEV;
1088
1089         mutex_lock(&dev->struct_mutex);
1090         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091         if (obj == NULL) {
1092                 mutex_unlock(&dev->struct_mutex);
1093                 return -EBADF;
1094         }
1095
1096 #if WATCH_BUF
1097         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1098                  __func__, args->handle, obj, obj->size);
1099 #endif
1100         obj_priv = obj->driver_private;
1101
1102         /* Pinned buffers may be scanout, so flush the cache */
1103         if (obj_priv->pin_count)
1104                 i915_gem_object_flush_cpu_write_domain(obj);
1105
1106         drm_gem_object_unreference(obj);
1107         mutex_unlock(&dev->struct_mutex);
1108         return ret;
1109 }
1110
1111 /**
1112  * Maps the contents of an object, returning the address it is mapped
1113  * into.
1114  *
1115  * While the mapping holds a reference on the contents of the object, it doesn't
1116  * imply a ref on the object itself.
1117  */
1118 int
1119 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120                    struct drm_file *file_priv)
1121 {
1122         struct drm_i915_gem_mmap *args = data;
1123         struct drm_gem_object *obj;
1124         loff_t offset;
1125         unsigned long addr;
1126
1127         if (!(dev->driver->driver_features & DRIVER_GEM))
1128                 return -ENODEV;
1129
1130         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1131         if (obj == NULL)
1132                 return -EBADF;
1133
1134         offset = args->offset;
1135
1136         down_write(&current->mm->mmap_sem);
1137         addr = do_mmap(obj->filp, 0, args->size,
1138                        PROT_READ | PROT_WRITE, MAP_SHARED,
1139                        args->offset);
1140         up_write(&current->mm->mmap_sem);
1141         mutex_lock(&dev->struct_mutex);
1142         drm_gem_object_unreference(obj);
1143         mutex_unlock(&dev->struct_mutex);
1144         if (IS_ERR((void *)addr))
1145                 return addr;
1146
1147         args->addr_ptr = (uint64_t) addr;
1148
1149         return 0;
1150 }
1151
1152 /**
1153  * i915_gem_fault - fault a page into the GTT
1154  * vma: VMA in question
1155  * vmf: fault info
1156  *
1157  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158  * from userspace.  The fault handler takes care of binding the object to
1159  * the GTT (if needed), allocating and programming a fence register (again,
1160  * only if needed based on whether the old reg is still valid or the object
1161  * is tiled) and inserting a new PTE into the faulting process.
1162  *
1163  * Note that the faulting process may involve evicting existing objects
1164  * from the GTT and/or fence registers to make room.  So performance may
1165  * suffer if the GTT working set is large or there are few fence registers
1166  * left.
1167  */
1168 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1169 {
1170         struct drm_gem_object *obj = vma->vm_private_data;
1171         struct drm_device *dev = obj->dev;
1172         struct drm_i915_private *dev_priv = dev->dev_private;
1173         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1174         pgoff_t page_offset;
1175         unsigned long pfn;
1176         int ret = 0;
1177         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1178
1179         /* We don't use vmf->pgoff since that has the fake offset */
1180         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181                 PAGE_SHIFT;
1182
1183         /* Now bind it into the GTT if needed */
1184         mutex_lock(&dev->struct_mutex);
1185         if (!obj_priv->gtt_space) {
1186                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187                 if (ret)
1188                         goto unlock;
1189
1190                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1191
1192                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1193                 if (ret)
1194                         goto unlock;
1195         }
1196
1197         /* Need a new fence register? */
1198         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1199                 ret = i915_gem_object_get_fence_reg(obj);
1200                 if (ret)
1201                         goto unlock;
1202         }
1203
1204         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1205                 page_offset;
1206
1207         /* Finally, remap it using the new GTT offset */
1208         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1209 unlock:
1210         mutex_unlock(&dev->struct_mutex);
1211
1212         switch (ret) {
1213         case 0:
1214         case -ERESTARTSYS:
1215                 return VM_FAULT_NOPAGE;
1216         case -ENOMEM:
1217         case -EAGAIN:
1218                 return VM_FAULT_OOM;
1219         default:
1220                 return VM_FAULT_SIGBUS;
1221         }
1222 }
1223
1224 /**
1225  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226  * @obj: obj in question
1227  *
1228  * GEM memory mapping works by handing back to userspace a fake mmap offset
1229  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1230  * up the object based on the offset and sets up the various memory mapping
1231  * structures.
1232  *
1233  * This routine allocates and attaches a fake offset for @obj.
1234  */
1235 static int
1236 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1237 {
1238         struct drm_device *dev = obj->dev;
1239         struct drm_gem_mm *mm = dev->mm_private;
1240         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241         struct drm_map_list *list;
1242         struct drm_local_map *map;
1243         int ret = 0;
1244
1245         /* Set the object up for mmap'ing */
1246         list = &obj->map_list;
1247         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1248         if (!list->map)
1249                 return -ENOMEM;
1250
1251         map = list->map;
1252         map->type = _DRM_GEM;
1253         map->size = obj->size;
1254         map->handle = obj;
1255
1256         /* Get a DRM GEM mmap offset allocated... */
1257         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1258                                                     obj->size / PAGE_SIZE, 0, 0);
1259         if (!list->file_offset_node) {
1260                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261                 ret = -ENOMEM;
1262                 goto out_free_list;
1263         }
1264
1265         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1266                                                   obj->size / PAGE_SIZE, 0);
1267         if (!list->file_offset_node) {
1268                 ret = -ENOMEM;
1269                 goto out_free_list;
1270         }
1271
1272         list->hash.key = list->file_offset_node->start;
1273         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1274                 DRM_ERROR("failed to add to map hash\n");
1275                 ret = -ENOMEM;
1276                 goto out_free_mm;
1277         }
1278
1279         /* By now we should be all set, any drm_mmap request on the offset
1280          * below will get to our mmap & fault handler */
1281         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1282
1283         return 0;
1284
1285 out_free_mm:
1286         drm_mm_put_block(list->file_offset_node);
1287 out_free_list:
1288         kfree(list->map);
1289
1290         return ret;
1291 }
1292
1293 /**
1294  * i915_gem_release_mmap - remove physical page mappings
1295  * @obj: obj in question
1296  *
1297  * Preserve the reservation of the mmapping with the DRM core code, but
1298  * relinquish ownership of the pages back to the system.
1299  *
1300  * It is vital that we remove the page mapping if we have mapped a tiled
1301  * object through the GTT and then lose the fence register due to
1302  * resource pressure. Similarly if the object has been moved out of the
1303  * aperture, than pages mapped into userspace must be revoked. Removing the
1304  * mapping will then trigger a page fault on the next user access, allowing
1305  * fixup by i915_gem_fault().
1306  */
1307 void
1308 i915_gem_release_mmap(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1312
1313         if (dev->dev_mapping)
1314                 unmap_mapping_range(dev->dev_mapping,
1315                                     obj_priv->mmap_offset, obj->size, 1);
1316 }
1317
1318 static void
1319 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1320 {
1321         struct drm_device *dev = obj->dev;
1322         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1323         struct drm_gem_mm *mm = dev->mm_private;
1324         struct drm_map_list *list;
1325
1326         list = &obj->map_list;
1327         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1328
1329         if (list->file_offset_node) {
1330                 drm_mm_put_block(list->file_offset_node);
1331                 list->file_offset_node = NULL;
1332         }
1333
1334         if (list->map) {
1335                 kfree(list->map);
1336                 list->map = NULL;
1337         }
1338
1339         obj_priv->mmap_offset = 0;
1340 }
1341
1342 /**
1343  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344  * @obj: object to check
1345  *
1346  * Return the required GTT alignment for an object, taking into account
1347  * potential fence register mapping if needed.
1348  */
1349 static uint32_t
1350 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1351 {
1352         struct drm_device *dev = obj->dev;
1353         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1354         int start, i;
1355
1356         /*
1357          * Minimum alignment is 4k (GTT page size), but might be greater
1358          * if a fence register is needed for the object.
1359          */
1360         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361                 return 4096;
1362
1363         /*
1364          * Previous chips need to be aligned to the size of the smallest
1365          * fence register that can contain the object.
1366          */
1367         if (IS_I9XX(dev))
1368                 start = 1024*1024;
1369         else
1370                 start = 512*1024;
1371
1372         for (i = start; i < obj->size; i <<= 1)
1373                 ;
1374
1375         return i;
1376 }
1377
1378 /**
1379  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1380  * @dev: DRM device
1381  * @data: GTT mapping ioctl data
1382  * @file_priv: GEM object info
1383  *
1384  * Simply returns the fake offset to userspace so it can mmap it.
1385  * The mmap call will end up in drm_gem_mmap(), which will set things
1386  * up so we can get faults in the handler above.
1387  *
1388  * The fault handler will take care of binding the object into the GTT
1389  * (since it may have been evicted to make room for something), allocating
1390  * a fence register, and mapping the appropriate aperture address into
1391  * userspace.
1392  */
1393 int
1394 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1395                         struct drm_file *file_priv)
1396 {
1397         struct drm_i915_gem_mmap_gtt *args = data;
1398         struct drm_i915_private *dev_priv = dev->dev_private;
1399         struct drm_gem_object *obj;
1400         struct drm_i915_gem_object *obj_priv;
1401         int ret;
1402
1403         if (!(dev->driver->driver_features & DRIVER_GEM))
1404                 return -ENODEV;
1405
1406         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407         if (obj == NULL)
1408                 return -EBADF;
1409
1410         mutex_lock(&dev->struct_mutex);
1411
1412         obj_priv = obj->driver_private;
1413
1414         if (obj_priv->madv != I915_MADV_WILLNEED) {
1415                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416                 drm_gem_object_unreference(obj);
1417                 mutex_unlock(&dev->struct_mutex);
1418                 return -EINVAL;
1419         }
1420
1421
1422         if (!obj_priv->mmap_offset) {
1423                 ret = i915_gem_create_mmap_offset(obj);
1424                 if (ret) {
1425                         drm_gem_object_unreference(obj);
1426                         mutex_unlock(&dev->struct_mutex);
1427                         return ret;
1428                 }
1429         }
1430
1431         args->offset = obj_priv->mmap_offset;
1432
1433         /*
1434          * Pull it into the GTT so that we have a page list (makes the
1435          * initial fault faster and any subsequent flushing possible).
1436          */
1437         if (!obj_priv->agp_mem) {
1438                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1439                 if (ret) {
1440                         drm_gem_object_unreference(obj);
1441                         mutex_unlock(&dev->struct_mutex);
1442                         return ret;
1443                 }
1444                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1445         }
1446
1447         drm_gem_object_unreference(obj);
1448         mutex_unlock(&dev->struct_mutex);
1449
1450         return 0;
1451 }
1452
1453 void
1454 i915_gem_object_put_pages(struct drm_gem_object *obj)
1455 {
1456         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457         int page_count = obj->size / PAGE_SIZE;
1458         int i;
1459
1460         BUG_ON(obj_priv->pages_refcount == 0);
1461         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1462
1463         if (--obj_priv->pages_refcount != 0)
1464                 return;
1465
1466         if (obj_priv->tiling_mode != I915_TILING_NONE)
1467                 i915_gem_object_save_bit_17_swizzle(obj);
1468
1469         if (obj_priv->madv == I915_MADV_DONTNEED)
1470                 obj_priv->dirty = 0;
1471
1472         for (i = 0; i < page_count; i++) {
1473                 if (obj_priv->pages[i] == NULL)
1474                         break;
1475
1476                 if (obj_priv->dirty)
1477                         set_page_dirty(obj_priv->pages[i]);
1478
1479                 if (obj_priv->madv == I915_MADV_WILLNEED)
1480                         mark_page_accessed(obj_priv->pages[i]);
1481
1482                 page_cache_release(obj_priv->pages[i]);
1483         }
1484         obj_priv->dirty = 0;
1485
1486         drm_free_large(obj_priv->pages);
1487         obj_priv->pages = NULL;
1488 }
1489
1490 static void
1491 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1492 {
1493         struct drm_device *dev = obj->dev;
1494         drm_i915_private_t *dev_priv = dev->dev_private;
1495         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1496
1497         /* Add a reference if we're newly entering the active list. */
1498         if (!obj_priv->active) {
1499                 drm_gem_object_reference(obj);
1500                 obj_priv->active = 1;
1501         }
1502         /* Move from whatever list we were on to the tail of execution. */
1503         spin_lock(&dev_priv->mm.active_list_lock);
1504         list_move_tail(&obj_priv->list,
1505                        &dev_priv->mm.active_list);
1506         spin_unlock(&dev_priv->mm.active_list_lock);
1507         obj_priv->last_rendering_seqno = seqno;
1508 }
1509
1510 static void
1511 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1512 {
1513         struct drm_device *dev = obj->dev;
1514         drm_i915_private_t *dev_priv = dev->dev_private;
1515         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1516
1517         BUG_ON(!obj_priv->active);
1518         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1519         obj_priv->last_rendering_seqno = 0;
1520 }
1521
1522 /* Immediately discard the backing storage */
1523 static void
1524 i915_gem_object_truncate(struct drm_gem_object *obj)
1525 {
1526         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527         struct inode *inode;
1528
1529         inode = obj->filp->f_path.dentry->d_inode;
1530         if (inode->i_op->truncate)
1531                 inode->i_op->truncate (inode);
1532
1533         obj_priv->madv = __I915_MADV_PURGED;
1534 }
1535
1536 static inline int
1537 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1538 {
1539         return obj_priv->madv == I915_MADV_DONTNEED;
1540 }
1541
1542 static void
1543 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1544 {
1545         struct drm_device *dev = obj->dev;
1546         drm_i915_private_t *dev_priv = dev->dev_private;
1547         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1548
1549         i915_verify_inactive(dev, __FILE__, __LINE__);
1550         if (obj_priv->pin_count != 0)
1551                 list_del_init(&obj_priv->list);
1552         else
1553                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1554
1555         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1556
1557         obj_priv->last_rendering_seqno = 0;
1558         if (obj_priv->active) {
1559                 obj_priv->active = 0;
1560                 drm_gem_object_unreference(obj);
1561         }
1562         i915_verify_inactive(dev, __FILE__, __LINE__);
1563 }
1564
1565 /**
1566  * Creates a new sequence number, emitting a write of it to the status page
1567  * plus an interrupt, which will trigger i915_user_interrupt_handler.
1568  *
1569  * Must be called with struct_lock held.
1570  *
1571  * Returned sequence numbers are nonzero on success.
1572  */
1573 uint32_t
1574 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1575                  uint32_t flush_domains)
1576 {
1577         drm_i915_private_t *dev_priv = dev->dev_private;
1578         struct drm_i915_file_private *i915_file_priv = NULL;
1579         struct drm_i915_gem_request *request;
1580         uint32_t seqno;
1581         int was_empty;
1582         RING_LOCALS;
1583
1584         if (file_priv != NULL)
1585                 i915_file_priv = file_priv->driver_priv;
1586
1587         request = kzalloc(sizeof(*request), GFP_KERNEL);
1588         if (request == NULL)
1589                 return 0;
1590
1591         /* Grab the seqno we're going to make this request be, and bump the
1592          * next (skipping 0 so it can be the reserved no-seqno value).
1593          */
1594         seqno = dev_priv->mm.next_gem_seqno;
1595         dev_priv->mm.next_gem_seqno++;
1596         if (dev_priv->mm.next_gem_seqno == 0)
1597                 dev_priv->mm.next_gem_seqno++;
1598
1599         BEGIN_LP_RING(4);
1600         OUT_RING(MI_STORE_DWORD_INDEX);
1601         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1602         OUT_RING(seqno);
1603
1604         OUT_RING(MI_USER_INTERRUPT);
1605         ADVANCE_LP_RING();
1606
1607         DRM_DEBUG_DRIVER("%d\n", seqno);
1608
1609         request->seqno = seqno;
1610         request->emitted_jiffies = jiffies;
1611         was_empty = list_empty(&dev_priv->mm.request_list);
1612         list_add_tail(&request->list, &dev_priv->mm.request_list);
1613         if (i915_file_priv) {
1614                 list_add_tail(&request->client_list,
1615                               &i915_file_priv->mm.request_list);
1616         } else {
1617                 INIT_LIST_HEAD(&request->client_list);
1618         }
1619
1620         /* Associate any objects on the flushing list matching the write
1621          * domain we're flushing with our flush.
1622          */
1623         if (flush_domains != 0) {
1624                 struct drm_i915_gem_object *obj_priv, *next;
1625
1626                 list_for_each_entry_safe(obj_priv, next,
1627                                          &dev_priv->mm.gpu_write_list,
1628                                          gpu_write_list) {
1629                         struct drm_gem_object *obj = obj_priv->obj;
1630
1631                         if ((obj->write_domain & flush_domains) ==
1632                             obj->write_domain) {
1633                                 uint32_t old_write_domain = obj->write_domain;
1634
1635                                 obj->write_domain = 0;
1636                                 list_del_init(&obj_priv->gpu_write_list);
1637                                 i915_gem_object_move_to_active(obj, seqno);
1638
1639                                 trace_i915_gem_object_change_domain(obj,
1640                                                                     obj->read_domains,
1641                                                                     old_write_domain);
1642                         }
1643                 }
1644
1645         }
1646
1647         if (!dev_priv->mm.suspended) {
1648                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1649                 if (was_empty)
1650                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1651         }
1652         return seqno;
1653 }
1654
1655 /**
1656  * Command execution barrier
1657  *
1658  * Ensures that all commands in the ring are finished
1659  * before signalling the CPU
1660  */
1661 static uint32_t
1662 i915_retire_commands(struct drm_device *dev)
1663 {
1664         drm_i915_private_t *dev_priv = dev->dev_private;
1665         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1666         uint32_t flush_domains = 0;
1667         RING_LOCALS;
1668
1669         /* The sampler always gets flushed on i965 (sigh) */
1670         if (IS_I965G(dev))
1671                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1672         BEGIN_LP_RING(2);
1673         OUT_RING(cmd);
1674         OUT_RING(0); /* noop */
1675         ADVANCE_LP_RING();
1676         return flush_domains;
1677 }
1678
1679 /**
1680  * Moves buffers associated only with the given active seqno from the active
1681  * to inactive list, potentially freeing them.
1682  */
1683 static void
1684 i915_gem_retire_request(struct drm_device *dev,
1685                         struct drm_i915_gem_request *request)
1686 {
1687         drm_i915_private_t *dev_priv = dev->dev_private;
1688
1689         trace_i915_gem_request_retire(dev, request->seqno);
1690
1691         /* Move any buffers on the active list that are no longer referenced
1692          * by the ringbuffer to the flushing/inactive lists as appropriate.
1693          */
1694         spin_lock(&dev_priv->mm.active_list_lock);
1695         while (!list_empty(&dev_priv->mm.active_list)) {
1696                 struct drm_gem_object *obj;
1697                 struct drm_i915_gem_object *obj_priv;
1698
1699                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1700                                             struct drm_i915_gem_object,
1701                                             list);
1702                 obj = obj_priv->obj;
1703
1704                 /* If the seqno being retired doesn't match the oldest in the
1705                  * list, then the oldest in the list must still be newer than
1706                  * this seqno.
1707                  */
1708                 if (obj_priv->last_rendering_seqno != request->seqno)
1709                         goto out;
1710
1711 #if WATCH_LRU
1712                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1713                          __func__, request->seqno, obj);
1714 #endif
1715
1716                 if (obj->write_domain != 0)
1717                         i915_gem_object_move_to_flushing(obj);
1718                 else {
1719                         /* Take a reference on the object so it won't be
1720                          * freed while the spinlock is held.  The list
1721                          * protection for this spinlock is safe when breaking
1722                          * the lock like this since the next thing we do
1723                          * is just get the head of the list again.
1724                          */
1725                         drm_gem_object_reference(obj);
1726                         i915_gem_object_move_to_inactive(obj);
1727                         spin_unlock(&dev_priv->mm.active_list_lock);
1728                         drm_gem_object_unreference(obj);
1729                         spin_lock(&dev_priv->mm.active_list_lock);
1730                 }
1731         }
1732 out:
1733         spin_unlock(&dev_priv->mm.active_list_lock);
1734 }
1735
1736 /**
1737  * Returns true if seq1 is later than seq2.
1738  */
1739 bool
1740 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1741 {
1742         return (int32_t)(seq1 - seq2) >= 0;
1743 }
1744
1745 uint32_t
1746 i915_get_gem_seqno(struct drm_device *dev)
1747 {
1748         drm_i915_private_t *dev_priv = dev->dev_private;
1749
1750         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1751 }
1752
1753 /**
1754  * This function clears the request list as sequence numbers are passed.
1755  */
1756 void
1757 i915_gem_retire_requests(struct drm_device *dev)
1758 {
1759         drm_i915_private_t *dev_priv = dev->dev_private;
1760         uint32_t seqno;
1761
1762         if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1763                 return;
1764
1765         seqno = i915_get_gem_seqno(dev);
1766
1767         while (!list_empty(&dev_priv->mm.request_list)) {
1768                 struct drm_i915_gem_request *request;
1769                 uint32_t retiring_seqno;
1770
1771                 request = list_first_entry(&dev_priv->mm.request_list,
1772                                            struct drm_i915_gem_request,
1773                                            list);
1774                 retiring_seqno = request->seqno;
1775
1776                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1777                     atomic_read(&dev_priv->mm.wedged)) {
1778                         i915_gem_retire_request(dev, request);
1779
1780                         list_del(&request->list);
1781                         list_del(&request->client_list);
1782                         kfree(request);
1783                 } else
1784                         break;
1785         }
1786
1787         if (unlikely (dev_priv->trace_irq_seqno &&
1788                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1789                 i915_user_irq_put(dev);
1790                 dev_priv->trace_irq_seqno = 0;
1791         }
1792 }
1793
1794 void
1795 i915_gem_retire_work_handler(struct work_struct *work)
1796 {
1797         drm_i915_private_t *dev_priv;
1798         struct drm_device *dev;
1799
1800         dev_priv = container_of(work, drm_i915_private_t,
1801                                 mm.retire_work.work);
1802         dev = dev_priv->dev;
1803
1804         mutex_lock(&dev->struct_mutex);
1805         i915_gem_retire_requests(dev);
1806         if (!dev_priv->mm.suspended &&
1807             !list_empty(&dev_priv->mm.request_list))
1808                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1809         mutex_unlock(&dev->struct_mutex);
1810 }
1811
1812 int
1813 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1814 {
1815         drm_i915_private_t *dev_priv = dev->dev_private;
1816         u32 ier;
1817         int ret = 0;
1818
1819         BUG_ON(seqno == 0);
1820
1821         if (atomic_read(&dev_priv->mm.wedged))
1822                 return -EIO;
1823
1824         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1825                 if (IS_IRONLAKE(dev))
1826                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1827                 else
1828                         ier = I915_READ(IER);
1829                 if (!ier) {
1830                         DRM_ERROR("something (likely vbetool) disabled "
1831                                   "interrupts, re-enabling\n");
1832                         i915_driver_irq_preinstall(dev);
1833                         i915_driver_irq_postinstall(dev);
1834                 }
1835
1836                 trace_i915_gem_request_wait_begin(dev, seqno);
1837
1838                 dev_priv->mm.waiting_gem_seqno = seqno;
1839                 i915_user_irq_get(dev);
1840                 if (interruptible)
1841                         ret = wait_event_interruptible(dev_priv->irq_queue,
1842                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1843                                 atomic_read(&dev_priv->mm.wedged));
1844                 else
1845                         wait_event(dev_priv->irq_queue,
1846                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1847                                 atomic_read(&dev_priv->mm.wedged));
1848
1849                 i915_user_irq_put(dev);
1850                 dev_priv->mm.waiting_gem_seqno = 0;
1851
1852                 trace_i915_gem_request_wait_end(dev, seqno);
1853         }
1854         if (atomic_read(&dev_priv->mm.wedged))
1855                 ret = -EIO;
1856
1857         if (ret && ret != -ERESTARTSYS)
1858                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1859                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1860
1861         /* Directly dispatch request retiring.  While we have the work queue
1862          * to handle this, the waiter on a request often wants an associated
1863          * buffer to have made it to the inactive list, and we would need
1864          * a separate wait queue to handle that.
1865          */
1866         if (ret == 0)
1867                 i915_gem_retire_requests(dev);
1868
1869         return ret;
1870 }
1871
1872 /**
1873  * Waits for a sequence number to be signaled, and cleans up the
1874  * request and object lists appropriately for that event.
1875  */
1876 static int
1877 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1878 {
1879         return i915_do_wait_request(dev, seqno, 1);
1880 }
1881
1882 static void
1883 i915_gem_flush(struct drm_device *dev,
1884                uint32_t invalidate_domains,
1885                uint32_t flush_domains)
1886 {
1887         drm_i915_private_t *dev_priv = dev->dev_private;
1888         uint32_t cmd;
1889         RING_LOCALS;
1890
1891 #if WATCH_EXEC
1892         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1893                   invalidate_domains, flush_domains);
1894 #endif
1895         trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1896                                      invalidate_domains, flush_domains);
1897
1898         if (flush_domains & I915_GEM_DOMAIN_CPU)
1899                 drm_agp_chipset_flush(dev);
1900
1901         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1902                 /*
1903                  * read/write caches:
1904                  *
1905                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1906                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1907                  * also flushed at 2d versus 3d pipeline switches.
1908                  *
1909                  * read-only caches:
1910                  *
1911                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1912                  * MI_READ_FLUSH is set, and is always flushed on 965.
1913                  *
1914                  * I915_GEM_DOMAIN_COMMAND may not exist?
1915                  *
1916                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1917                  * invalidated when MI_EXE_FLUSH is set.
1918                  *
1919                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1920                  * invalidated with every MI_FLUSH.
1921                  *
1922                  * TLBs:
1923                  *
1924                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1925                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1926                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1927                  * are flushed at any MI_FLUSH.
1928                  */
1929
1930                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1931                 if ((invalidate_domains|flush_domains) &
1932                     I915_GEM_DOMAIN_RENDER)
1933                         cmd &= ~MI_NO_WRITE_FLUSH;
1934                 if (!IS_I965G(dev)) {
1935                         /*
1936                          * On the 965, the sampler cache always gets flushed
1937                          * and this bit is reserved.
1938                          */
1939                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1940                                 cmd |= MI_READ_FLUSH;
1941                 }
1942                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1943                         cmd |= MI_EXE_FLUSH;
1944
1945 #if WATCH_EXEC
1946                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1947 #endif
1948                 BEGIN_LP_RING(2);
1949                 OUT_RING(cmd);
1950                 OUT_RING(MI_NOOP);
1951                 ADVANCE_LP_RING();
1952         }
1953 }
1954
1955 /**
1956  * Ensures that all rendering to the object has completed and the object is
1957  * safe to unbind from the GTT or access from the CPU.
1958  */
1959 static int
1960 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1961 {
1962         struct drm_device *dev = obj->dev;
1963         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1964         int ret;
1965
1966         /* This function only exists to support waiting for existing rendering,
1967          * not for emitting required flushes.
1968          */
1969         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1970
1971         /* If there is rendering queued on the buffer being evicted, wait for
1972          * it.
1973          */
1974         if (obj_priv->active) {
1975 #if WATCH_BUF
1976                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1977                           __func__, obj, obj_priv->last_rendering_seqno);
1978 #endif
1979                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1980                 if (ret != 0)
1981                         return ret;
1982         }
1983
1984         return 0;
1985 }
1986
1987 /**
1988  * Unbinds an object from the GTT aperture.
1989  */
1990 int
1991 i915_gem_object_unbind(struct drm_gem_object *obj)
1992 {
1993         struct drm_device *dev = obj->dev;
1994         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1995         int ret = 0;
1996
1997 #if WATCH_BUF
1998         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1999         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2000 #endif
2001         if (obj_priv->gtt_space == NULL)
2002                 return 0;
2003
2004         if (obj_priv->pin_count != 0) {
2005                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2006                 return -EINVAL;
2007         }
2008
2009         /* blow away mappings if mapped through GTT */
2010         i915_gem_release_mmap(obj);
2011
2012         /* Move the object to the CPU domain to ensure that
2013          * any possible CPU writes while it's not in the GTT
2014          * are flushed when we go to remap it. This will
2015          * also ensure that all pending GPU writes are finished
2016          * before we unbind.
2017          */
2018         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2019         if (ret) {
2020                 if (ret != -ERESTARTSYS)
2021                         DRM_ERROR("set_domain failed: %d\n", ret);
2022                 return ret;
2023         }
2024
2025         BUG_ON(obj_priv->active);
2026
2027         /* release the fence reg _after_ flushing */
2028         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2029                 i915_gem_clear_fence_reg(obj);
2030
2031         if (obj_priv->agp_mem != NULL) {
2032                 drm_unbind_agp(obj_priv->agp_mem);
2033                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2034                 obj_priv->agp_mem = NULL;
2035         }
2036
2037         i915_gem_object_put_pages(obj);
2038         BUG_ON(obj_priv->pages_refcount);
2039
2040         if (obj_priv->gtt_space) {
2041                 atomic_dec(&dev->gtt_count);
2042                 atomic_sub(obj->size, &dev->gtt_memory);
2043
2044                 drm_mm_put_block(obj_priv->gtt_space);
2045                 obj_priv->gtt_space = NULL;
2046         }
2047
2048         /* Remove ourselves from the LRU list if present. */
2049         if (!list_empty(&obj_priv->list))
2050                 list_del_init(&obj_priv->list);
2051
2052         if (i915_gem_object_is_purgeable(obj_priv))
2053                 i915_gem_object_truncate(obj);
2054
2055         trace_i915_gem_object_unbind(obj);
2056
2057         return 0;
2058 }
2059
2060 static struct drm_gem_object *
2061 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2062 {
2063         drm_i915_private_t *dev_priv = dev->dev_private;
2064         struct drm_i915_gem_object *obj_priv;
2065         struct drm_gem_object *best = NULL;
2066         struct drm_gem_object *first = NULL;
2067
2068         /* Try to find the smallest clean object */
2069         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2070                 struct drm_gem_object *obj = obj_priv->obj;
2071                 if (obj->size >= min_size) {
2072                         if ((!obj_priv->dirty ||
2073                              i915_gem_object_is_purgeable(obj_priv)) &&
2074                             (!best || obj->size < best->size)) {
2075                                 best = obj;
2076                                 if (best->size == min_size)
2077                                         return best;
2078                         }
2079                         if (!first)
2080                             first = obj;
2081                 }
2082         }
2083
2084         return best ? best : first;
2085 }
2086
2087 static int
2088 i915_gem_evict_everything(struct drm_device *dev)
2089 {
2090         drm_i915_private_t *dev_priv = dev->dev_private;
2091         int ret;
2092         uint32_t seqno;
2093         bool lists_empty;
2094
2095         spin_lock(&dev_priv->mm.active_list_lock);
2096         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2097                        list_empty(&dev_priv->mm.flushing_list) &&
2098                        list_empty(&dev_priv->mm.active_list));
2099         spin_unlock(&dev_priv->mm.active_list_lock);
2100
2101         if (lists_empty)
2102                 return -ENOSPC;
2103
2104         /* Flush everything (on to the inactive lists) and evict */
2105         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2106         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2107         if (seqno == 0)
2108                 return -ENOMEM;
2109
2110         ret = i915_wait_request(dev, seqno);
2111         if (ret)
2112                 return ret;
2113
2114         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2115
2116         ret = i915_gem_evict_from_inactive_list(dev);
2117         if (ret)
2118                 return ret;
2119
2120         spin_lock(&dev_priv->mm.active_list_lock);
2121         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2122                        list_empty(&dev_priv->mm.flushing_list) &&
2123                        list_empty(&dev_priv->mm.active_list));
2124         spin_unlock(&dev_priv->mm.active_list_lock);
2125         BUG_ON(!lists_empty);
2126
2127         return 0;
2128 }
2129
2130 static int
2131 i915_gem_evict_something(struct drm_device *dev, int min_size)
2132 {
2133         drm_i915_private_t *dev_priv = dev->dev_private;
2134         struct drm_gem_object *obj;
2135         int ret;
2136
2137         for (;;) {
2138                 i915_gem_retire_requests(dev);
2139
2140                 /* If there's an inactive buffer available now, grab it
2141                  * and be done.
2142                  */
2143                 obj = i915_gem_find_inactive_object(dev, min_size);
2144                 if (obj) {
2145                         struct drm_i915_gem_object *obj_priv;
2146
2147 #if WATCH_LRU
2148                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2149 #endif
2150                         obj_priv = obj->driver_private;
2151                         BUG_ON(obj_priv->pin_count != 0);
2152                         BUG_ON(obj_priv->active);
2153
2154                         /* Wait on the rendering and unbind the buffer. */
2155                         return i915_gem_object_unbind(obj);
2156                 }
2157
2158                 /* If we didn't get anything, but the ring is still processing
2159                  * things, wait for the next to finish and hopefully leave us
2160                  * a buffer to evict.
2161                  */
2162                 if (!list_empty(&dev_priv->mm.request_list)) {
2163                         struct drm_i915_gem_request *request;
2164
2165                         request = list_first_entry(&dev_priv->mm.request_list,
2166                                                    struct drm_i915_gem_request,
2167                                                    list);
2168
2169                         ret = i915_wait_request(dev, request->seqno);
2170                         if (ret)
2171                                 return ret;
2172
2173                         continue;
2174                 }
2175
2176                 /* If we didn't have anything on the request list but there
2177                  * are buffers awaiting a flush, emit one and try again.
2178                  * When we wait on it, those buffers waiting for that flush
2179                  * will get moved to inactive.
2180                  */
2181                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2182                         struct drm_i915_gem_object *obj_priv;
2183
2184                         /* Find an object that we can immediately reuse */
2185                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2186                                 obj = obj_priv->obj;
2187                                 if (obj->size >= min_size)
2188                                         break;
2189
2190                                 obj = NULL;
2191                         }
2192
2193                         if (obj != NULL) {
2194                                 uint32_t seqno;
2195
2196                                 i915_gem_flush(dev,
2197                                                obj->write_domain,
2198                                                obj->write_domain);
2199                                 seqno = i915_add_request(dev, NULL, obj->write_domain);
2200                                 if (seqno == 0)
2201                                         return -ENOMEM;
2202
2203                                 ret = i915_wait_request(dev, seqno);
2204                                 if (ret)
2205                                         return ret;
2206
2207                                 continue;
2208                         }
2209                 }
2210
2211                 /* If we didn't do any of the above, there's no single buffer
2212                  * large enough to swap out for the new one, so just evict
2213                  * everything and start again. (This should be rare.)
2214                  */
2215                 if (!list_empty (&dev_priv->mm.inactive_list))
2216                         return i915_gem_evict_from_inactive_list(dev);
2217                 else
2218                         return i915_gem_evict_everything(dev);
2219         }
2220 }
2221
2222 int
2223 i915_gem_object_get_pages(struct drm_gem_object *obj,
2224                           gfp_t gfpmask)
2225 {
2226         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2227         int page_count, i;
2228         struct address_space *mapping;
2229         struct inode *inode;
2230         struct page *page;
2231         int ret;
2232
2233         if (obj_priv->pages_refcount++ != 0)
2234                 return 0;
2235
2236         /* Get the list of pages out of our struct file.  They'll be pinned
2237          * at this point until we release them.
2238          */
2239         page_count = obj->size / PAGE_SIZE;
2240         BUG_ON(obj_priv->pages != NULL);
2241         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2242         if (obj_priv->pages == NULL) {
2243                 obj_priv->pages_refcount--;
2244                 return -ENOMEM;
2245         }
2246
2247         inode = obj->filp->f_path.dentry->d_inode;
2248         mapping = inode->i_mapping;
2249         for (i = 0; i < page_count; i++) {
2250                 page = read_cache_page_gfp(mapping, i,
2251                                            mapping_gfp_mask (mapping) |
2252                                            __GFP_COLD |
2253                                            gfpmask);
2254                 if (IS_ERR(page)) {
2255                         ret = PTR_ERR(page);
2256                         i915_gem_object_put_pages(obj);
2257                         return ret;
2258                 }
2259                 obj_priv->pages[i] = page;
2260         }
2261
2262         if (obj_priv->tiling_mode != I915_TILING_NONE)
2263                 i915_gem_object_do_bit_17_swizzle(obj);
2264
2265         return 0;
2266 }
2267
2268 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2269 {
2270         struct drm_gem_object *obj = reg->obj;
2271         struct drm_device *dev = obj->dev;
2272         drm_i915_private_t *dev_priv = dev->dev_private;
2273         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2274         int regnum = obj_priv->fence_reg;
2275         uint64_t val;
2276
2277         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2278                     0xfffff000) << 32;
2279         val |= obj_priv->gtt_offset & 0xfffff000;
2280         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2281         if (obj_priv->tiling_mode == I915_TILING_Y)
2282                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2283         val |= I965_FENCE_REG_VALID;
2284
2285         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2286 }
2287
2288 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2289 {
2290         struct drm_gem_object *obj = reg->obj;
2291         struct drm_device *dev = obj->dev;
2292         drm_i915_private_t *dev_priv = dev->dev_private;
2293         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2294         int regnum = obj_priv->fence_reg;
2295         int tile_width;
2296         uint32_t fence_reg, val;
2297         uint32_t pitch_val;
2298
2299         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2300             (obj_priv->gtt_offset & (obj->size - 1))) {
2301                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2302                      __func__, obj_priv->gtt_offset, obj->size);
2303                 return;
2304         }
2305
2306         if (obj_priv->tiling_mode == I915_TILING_Y &&
2307             HAS_128_BYTE_Y_TILING(dev))
2308                 tile_width = 128;
2309         else
2310                 tile_width = 512;
2311
2312         /* Note: pitch better be a power of two tile widths */
2313         pitch_val = obj_priv->stride / tile_width;
2314         pitch_val = ffs(pitch_val) - 1;
2315
2316         val = obj_priv->gtt_offset;
2317         if (obj_priv->tiling_mode == I915_TILING_Y)
2318                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2319         val |= I915_FENCE_SIZE_BITS(obj->size);
2320         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2321         val |= I830_FENCE_REG_VALID;
2322
2323         if (regnum < 8)
2324                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2325         else
2326                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2327         I915_WRITE(fence_reg, val);
2328 }
2329
2330 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2331 {
2332         struct drm_gem_object *obj = reg->obj;
2333         struct drm_device *dev = obj->dev;
2334         drm_i915_private_t *dev_priv = dev->dev_private;
2335         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2336         int regnum = obj_priv->fence_reg;
2337         uint32_t val;
2338         uint32_t pitch_val;
2339         uint32_t fence_size_bits;
2340
2341         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2342             (obj_priv->gtt_offset & (obj->size - 1))) {
2343                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2344                      __func__, obj_priv->gtt_offset);
2345                 return;
2346         }
2347
2348         pitch_val = obj_priv->stride / 128;
2349         pitch_val = ffs(pitch_val) - 1;
2350         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2351
2352         val = obj_priv->gtt_offset;
2353         if (obj_priv->tiling_mode == I915_TILING_Y)
2354                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2355         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2356         WARN_ON(fence_size_bits & ~0x00000f00);
2357         val |= fence_size_bits;
2358         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2359         val |= I830_FENCE_REG_VALID;
2360
2361         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2362 }
2363
2364 /**
2365  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2366  * @obj: object to map through a fence reg
2367  *
2368  * When mapping objects through the GTT, userspace wants to be able to write
2369  * to them without having to worry about swizzling if the object is tiled.
2370  *
2371  * This function walks the fence regs looking for a free one for @obj,
2372  * stealing one if it can't find any.
2373  *
2374  * It then sets up the reg based on the object's properties: address, pitch
2375  * and tiling format.
2376  */
2377 int
2378 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2379 {
2380         struct drm_device *dev = obj->dev;
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2383         struct drm_i915_fence_reg *reg = NULL;
2384         struct drm_i915_gem_object *old_obj_priv = NULL;
2385         int i, ret, avail;
2386
2387         /* Just update our place in the LRU if our fence is getting used. */
2388         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2389                 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2390                 return 0;
2391         }
2392
2393         switch (obj_priv->tiling_mode) {
2394         case I915_TILING_NONE:
2395                 WARN(1, "allocating a fence for non-tiled object?\n");
2396                 break;
2397         case I915_TILING_X:
2398                 if (!obj_priv->stride)
2399                         return -EINVAL;
2400                 WARN((obj_priv->stride & (512 - 1)),
2401                      "object 0x%08x is X tiled but has non-512B pitch\n",
2402                      obj_priv->gtt_offset);
2403                 break;
2404         case I915_TILING_Y:
2405                 if (!obj_priv->stride)
2406                         return -EINVAL;
2407                 WARN((obj_priv->stride & (128 - 1)),
2408                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2409                      obj_priv->gtt_offset);
2410                 break;
2411         }
2412
2413         /* First try to find a free reg */
2414         avail = 0;
2415         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2416                 reg = &dev_priv->fence_regs[i];
2417                 if (!reg->obj)
2418                         break;
2419
2420                 old_obj_priv = reg->obj->driver_private;
2421                 if (!old_obj_priv->pin_count)
2422                     avail++;
2423         }
2424
2425         /* None available, try to steal one or wait for a user to finish */
2426         if (i == dev_priv->num_fence_regs) {
2427                 struct drm_gem_object *old_obj = NULL;
2428
2429                 if (avail == 0)
2430                         return -ENOSPC;
2431
2432                 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2433                                     fence_list) {
2434                         old_obj = old_obj_priv->obj;
2435
2436                         if (old_obj_priv->pin_count)
2437                                 continue;
2438
2439                         /* Take a reference, as otherwise the wait_rendering
2440                          * below may cause the object to get freed out from
2441                          * under us.
2442                          */
2443                         drm_gem_object_reference(old_obj);
2444
2445                         /* i915 uses fences for GPU access to tiled buffers */
2446                         if (IS_I965G(dev) || !old_obj_priv->active)
2447                                 break;
2448
2449                         /* This brings the object to the head of the LRU if it
2450                          * had been written to.  The only way this should
2451                          * result in us waiting longer than the expected
2452                          * optimal amount of time is if there was a
2453                          * fence-using buffer later that was read-only.
2454                          */
2455                         i915_gem_object_flush_gpu_write_domain(old_obj);
2456                         ret = i915_gem_object_wait_rendering(old_obj);
2457                         if (ret != 0) {
2458                                 drm_gem_object_unreference(old_obj);
2459                                 return ret;
2460                         }
2461
2462                         break;
2463                 }
2464
2465                 /*
2466                  * Zap this virtual mapping so we can set up a fence again
2467                  * for this object next time we need it.
2468                  */
2469                 i915_gem_release_mmap(old_obj);
2470
2471                 i = old_obj_priv->fence_reg;
2472                 reg = &dev_priv->fence_regs[i];
2473
2474                 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2475                 list_del_init(&old_obj_priv->fence_list);
2476
2477                 drm_gem_object_unreference(old_obj);
2478         }
2479
2480         obj_priv->fence_reg = i;
2481         list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2482
2483         reg->obj = obj;
2484
2485         if (IS_I965G(dev))
2486                 i965_write_fence_reg(reg);
2487         else if (IS_I9XX(dev))
2488                 i915_write_fence_reg(reg);
2489         else
2490                 i830_write_fence_reg(reg);
2491
2492         trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2493
2494         return 0;
2495 }
2496
2497 /**
2498  * i915_gem_clear_fence_reg - clear out fence register info
2499  * @obj: object to clear
2500  *
2501  * Zeroes out the fence register itself and clears out the associated
2502  * data structures in dev_priv and obj_priv.
2503  */
2504 static void
2505 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2506 {
2507         struct drm_device *dev = obj->dev;
2508         drm_i915_private_t *dev_priv = dev->dev_private;
2509         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2510
2511         if (IS_I965G(dev))
2512                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2513         else {
2514                 uint32_t fence_reg;
2515
2516                 if (obj_priv->fence_reg < 8)
2517                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2518                 else
2519                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2520                                                        8) * 4;
2521
2522                 I915_WRITE(fence_reg, 0);
2523         }
2524
2525         dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2526         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2527         list_del_init(&obj_priv->fence_list);
2528 }
2529
2530 /**
2531  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2532  * to the buffer to finish, and then resets the fence register.
2533  * @obj: tiled object holding a fence register.
2534  *
2535  * Zeroes out the fence register itself and clears out the associated
2536  * data structures in dev_priv and obj_priv.
2537  */
2538 int
2539 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2540 {
2541         struct drm_device *dev = obj->dev;
2542         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2543
2544         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2545                 return 0;
2546
2547         /* If we've changed tiling, GTT-mappings of the object
2548          * need to re-fault to ensure that the correct fence register
2549          * setup is in place.
2550          */
2551         i915_gem_release_mmap(obj);
2552
2553         /* On the i915, GPU access to tiled buffers is via a fence,
2554          * therefore we must wait for any outstanding access to complete
2555          * before clearing the fence.
2556          */
2557         if (!IS_I965G(dev)) {
2558                 int ret;
2559
2560                 i915_gem_object_flush_gpu_write_domain(obj);
2561                 ret = i915_gem_object_wait_rendering(obj);
2562                 if (ret != 0)
2563                         return ret;
2564         }
2565
2566         i915_gem_object_flush_gtt_write_domain(obj);
2567         i915_gem_clear_fence_reg (obj);
2568
2569         return 0;
2570 }
2571
2572 /**
2573  * Finds free space in the GTT aperture and binds the object there.
2574  */
2575 static int
2576 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2577 {
2578         struct drm_device *dev = obj->dev;
2579         drm_i915_private_t *dev_priv = dev->dev_private;
2580         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2581         struct drm_mm_node *free_space;
2582         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2583         int ret;
2584
2585         if (obj_priv->madv != I915_MADV_WILLNEED) {
2586                 DRM_ERROR("Attempting to bind a purgeable object\n");
2587                 return -EINVAL;
2588         }
2589
2590         if (alignment == 0)
2591                 alignment = i915_gem_get_gtt_alignment(obj);
2592         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2593                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2594                 return -EINVAL;
2595         }
2596
2597  search_free:
2598         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2599                                         obj->size, alignment, 0);
2600         if (free_space != NULL) {
2601                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2602                                                        alignment);
2603                 if (obj_priv->gtt_space != NULL) {
2604                         obj_priv->gtt_space->private = obj;
2605                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2606                 }
2607         }
2608         if (obj_priv->gtt_space == NULL) {
2609                 /* If the gtt is empty and we're still having trouble
2610                  * fitting our object in, we're out of memory.
2611                  */
2612 #if WATCH_LRU
2613                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2614 #endif
2615                 ret = i915_gem_evict_something(dev, obj->size);
2616                 if (ret)
2617                         return ret;
2618
2619                 goto search_free;
2620         }
2621
2622 #if WATCH_BUF
2623         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2624                  obj->size, obj_priv->gtt_offset);
2625 #endif
2626         ret = i915_gem_object_get_pages(obj, gfpmask);
2627         if (ret) {
2628                 drm_mm_put_block(obj_priv->gtt_space);
2629                 obj_priv->gtt_space = NULL;
2630
2631                 if (ret == -ENOMEM) {
2632                         /* first try to clear up some space from the GTT */
2633                         ret = i915_gem_evict_something(dev, obj->size);
2634                         if (ret) {
2635                                 /* now try to shrink everyone else */
2636                                 if (gfpmask) {
2637                                         gfpmask = 0;
2638                                         goto search_free;
2639                                 }
2640
2641                                 return ret;
2642                         }
2643
2644                         goto search_free;
2645                 }
2646
2647                 return ret;
2648         }
2649
2650         /* Create an AGP memory structure pointing at our pages, and bind it
2651          * into the GTT.
2652          */
2653         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2654                                                obj_priv->pages,
2655                                                obj->size >> PAGE_SHIFT,
2656                                                obj_priv->gtt_offset,
2657                                                obj_priv->agp_type);
2658         if (obj_priv->agp_mem == NULL) {
2659                 i915_gem_object_put_pages(obj);
2660                 drm_mm_put_block(obj_priv->gtt_space);
2661                 obj_priv->gtt_space = NULL;
2662
2663                 ret = i915_gem_evict_something(dev, obj->size);
2664                 if (ret)
2665                         return ret;
2666
2667                 goto search_free;
2668         }
2669         atomic_inc(&dev->gtt_count);
2670         atomic_add(obj->size, &dev->gtt_memory);
2671
2672         /* Assert that the object is not currently in any GPU domain. As it
2673          * wasn't in the GTT, there shouldn't be any way it could have been in
2674          * a GPU cache
2675          */
2676         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2677         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2678
2679         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2680
2681         return 0;
2682 }
2683
2684 void
2685 i915_gem_clflush_object(struct drm_gem_object *obj)
2686 {
2687         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
2688
2689         /* If we don't have a page list set up, then we're not pinned
2690          * to GPU, and we can ignore the cache flush because it'll happen
2691          * again at bind time.
2692          */
2693         if (obj_priv->pages == NULL)
2694                 return;
2695
2696         trace_i915_gem_object_clflush(obj);
2697
2698         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2699 }
2700
2701 /** Flushes any GPU write domain for the object if it's dirty. */
2702 static void
2703 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2704 {
2705         struct drm_device *dev = obj->dev;
2706         uint32_t seqno;
2707         uint32_t old_write_domain;
2708
2709         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2710                 return;
2711
2712         /* Queue the GPU write cache flushing we need. */
2713         old_write_domain = obj->write_domain;
2714         i915_gem_flush(dev, 0, obj->write_domain);
2715         seqno = i915_add_request(dev, NULL, obj->write_domain);
2716         BUG_ON(obj->write_domain);
2717         i915_gem_object_move_to_active(obj, seqno);
2718
2719         trace_i915_gem_object_change_domain(obj,
2720                                             obj->read_domains,
2721                                             old_write_domain);
2722 }
2723
2724 /** Flushes the GTT write domain for the object if it's dirty. */
2725 static void
2726 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2727 {
2728         uint32_t old_write_domain;
2729
2730         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2731                 return;
2732
2733         /* No actual flushing is required for the GTT write domain.   Writes
2734          * to it immediately go to main memory as far as we know, so there's
2735          * no chipset flush.  It also doesn't land in render cache.
2736          */
2737         old_write_domain = obj->write_domain;
2738         obj->write_domain = 0;
2739
2740         trace_i915_gem_object_change_domain(obj,
2741                                             obj->read_domains,
2742                                             old_write_domain);
2743 }
2744
2745 /** Flushes the CPU write domain for the object if it's dirty. */
2746 static void
2747 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2748 {
2749         struct drm_device *dev = obj->dev;
2750         uint32_t old_write_domain;
2751
2752         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2753                 return;
2754
2755         i915_gem_clflush_object(obj);
2756         drm_agp_chipset_flush(dev);
2757         old_write_domain = obj->write_domain;
2758         obj->write_domain = 0;
2759
2760         trace_i915_gem_object_change_domain(obj,
2761                                             obj->read_domains,
2762                                             old_write_domain);
2763 }
2764
2765 void
2766 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2767 {
2768         switch (obj->write_domain) {
2769         case I915_GEM_DOMAIN_GTT:
2770                 i915_gem_object_flush_gtt_write_domain(obj);
2771                 break;
2772         case I915_GEM_DOMAIN_CPU:
2773                 i915_gem_object_flush_cpu_write_domain(obj);
2774                 break;
2775         default:
2776                 i915_gem_object_flush_gpu_write_domain(obj);
2777                 break;
2778         }
2779 }
2780
2781 /**
2782  * Moves a single object to the GTT read, and possibly write domain.
2783  *
2784  * This function returns when the move is complete, including waiting on
2785  * flushes to occur.
2786  */
2787 int
2788 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2789 {
2790         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2791         uint32_t old_write_domain, old_read_domains;
2792         int ret;
2793
2794         /* Not valid to be called on unbound objects. */
2795         if (obj_priv->gtt_space == NULL)
2796                 return -EINVAL;
2797
2798         i915_gem_object_flush_gpu_write_domain(obj);
2799         /* Wait on any GPU rendering and flushing to occur. */
2800         ret = i915_gem_object_wait_rendering(obj);
2801         if (ret != 0)
2802                 return ret;
2803
2804         old_write_domain = obj->write_domain;
2805         old_read_domains = obj->read_domains;
2806
2807         /* If we're writing through the GTT domain, then CPU and GPU caches
2808          * will need to be invalidated at next use.
2809          */
2810         if (write)
2811                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2812
2813         i915_gem_object_flush_cpu_write_domain(obj);
2814
2815         /* It should now be out of any other write domains, and we can update
2816          * the domain values for our changes.
2817          */
2818         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2819         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2820         if (write) {
2821                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2822                 obj_priv->dirty = 1;
2823         }
2824
2825         trace_i915_gem_object_change_domain(obj,
2826                                             old_read_domains,
2827                                             old_write_domain);
2828
2829         return 0;
2830 }
2831
2832 /*
2833  * Prepare buffer for display plane. Use uninterruptible for possible flush
2834  * wait, as in modesetting process we're not supposed to be interrupted.
2835  */
2836 int
2837 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2838 {
2839         struct drm_device *dev = obj->dev;
2840         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2841         uint32_t old_write_domain, old_read_domains;
2842         int ret;
2843
2844         /* Not valid to be called on unbound objects. */
2845         if (obj_priv->gtt_space == NULL)
2846                 return -EINVAL;
2847
2848         i915_gem_object_flush_gpu_write_domain(obj);
2849
2850         /* Wait on any GPU rendering and flushing to occur. */
2851         if (obj_priv->active) {
2852 #if WATCH_BUF
2853                 DRM_INFO("%s: object %p wait for seqno %08x\n",
2854                           __func__, obj, obj_priv->last_rendering_seqno);
2855 #endif
2856                 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2857                 if (ret != 0)
2858                         return ret;
2859         }
2860
2861         old_write_domain = obj->write_domain;
2862         old_read_domains = obj->read_domains;
2863
2864         obj->read_domains &= I915_GEM_DOMAIN_GTT;
2865
2866         i915_gem_object_flush_cpu_write_domain(obj);
2867
2868         /* It should now be out of any other write domains, and we can update
2869          * the domain values for our changes.
2870          */
2871         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2872         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2873         obj->write_domain = I915_GEM_DOMAIN_GTT;
2874         obj_priv->dirty = 1;
2875
2876         trace_i915_gem_object_change_domain(obj,
2877                                             old_read_domains,
2878                                             old_write_domain);
2879
2880         return 0;
2881 }
2882
2883 /**
2884  * Moves a single object to the CPU read, and possibly write domain.
2885  *
2886  * This function returns when the move is complete, including waiting on
2887  * flushes to occur.
2888  */
2889 static int
2890 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2891 {
2892         uint32_t old_write_domain, old_read_domains;
2893         int ret;
2894
2895         i915_gem_object_flush_gpu_write_domain(obj);
2896         /* Wait on any GPU rendering and flushing to occur. */
2897         ret = i915_gem_object_wait_rendering(obj);
2898         if (ret != 0)
2899                 return ret;
2900
2901         i915_gem_object_flush_gtt_write_domain(obj);
2902
2903         /* If we have a partially-valid cache of the object in the CPU,
2904          * finish invalidating it and free the per-page flags.
2905          */
2906         i915_gem_object_set_to_full_cpu_read_domain(obj);
2907
2908         old_write_domain = obj->write_domain;
2909         old_read_domains = obj->read_domains;
2910
2911         /* Flush the CPU cache if it's still invalid. */
2912         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2913                 i915_gem_clflush_object(obj);
2914
2915                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2916         }
2917
2918         /* It should now be out of any other write domains, and we can update
2919          * the domain values for our changes.
2920          */
2921         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2922
2923         /* If we're writing through the CPU, then the GPU read domains will
2924          * need to be invalidated at next use.
2925          */
2926         if (write) {
2927                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2928                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2929         }
2930
2931         trace_i915_gem_object_change_domain(obj,
2932                                             old_read_domains,
2933                                             old_write_domain);
2934
2935         return 0;
2936 }
2937
2938 /*
2939  * Set the next domain for the specified object. This
2940  * may not actually perform the necessary flushing/invaliding though,
2941  * as that may want to be batched with other set_domain operations
2942  *
2943  * This is (we hope) the only really tricky part of gem. The goal
2944  * is fairly simple -- track which caches hold bits of the object
2945  * and make sure they remain coherent. A few concrete examples may
2946  * help to explain how it works. For shorthand, we use the notation
2947  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2948  * a pair of read and write domain masks.
2949  *
2950  * Case 1: the batch buffer
2951  *
2952  *      1. Allocated
2953  *      2. Written by CPU
2954  *      3. Mapped to GTT
2955  *      4. Read by GPU
2956  *      5. Unmapped from GTT
2957  *      6. Freed
2958  *
2959  *      Let's take these a step at a time
2960  *
2961  *      1. Allocated
2962  *              Pages allocated from the kernel may still have
2963  *              cache contents, so we set them to (CPU, CPU) always.
2964  *      2. Written by CPU (using pwrite)
2965  *              The pwrite function calls set_domain (CPU, CPU) and
2966  *              this function does nothing (as nothing changes)
2967  *      3. Mapped by GTT
2968  *              This function asserts that the object is not
2969  *              currently in any GPU-based read or write domains
2970  *      4. Read by GPU
2971  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
2972  *              As write_domain is zero, this function adds in the
2973  *              current read domains (CPU+COMMAND, 0).
2974  *              flush_domains is set to CPU.
2975  *              invalidate_domains is set to COMMAND
2976  *              clflush is run to get data out of the CPU caches
2977  *              then i915_dev_set_domain calls i915_gem_flush to
2978  *              emit an MI_FLUSH and drm_agp_chipset_flush
2979  *      5. Unmapped from GTT
2980  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
2981  *              flush_domains and invalidate_domains end up both zero
2982  *              so no flushing/invalidating happens
2983  *      6. Freed
2984  *              yay, done
2985  *
2986  * Case 2: The shared render buffer
2987  *
2988  *      1. Allocated
2989  *      2. Mapped to GTT
2990  *      3. Read/written by GPU
2991  *      4. set_domain to (CPU,CPU)
2992  *      5. Read/written by CPU
2993  *      6. Read/written by GPU
2994  *
2995  *      1. Allocated
2996  *              Same as last example, (CPU, CPU)
2997  *      2. Mapped to GTT
2998  *              Nothing changes (assertions find that it is not in the GPU)
2999  *      3. Read/written by GPU
3000  *              execbuffer calls set_domain (RENDER, RENDER)
3001  *              flush_domains gets CPU
3002  *              invalidate_domains gets GPU
3003  *              clflush (obj)
3004  *              MI_FLUSH and drm_agp_chipset_flush
3005  *      4. set_domain (CPU, CPU)
3006  *              flush_domains gets GPU
3007  *              invalidate_domains gets CPU
3008  *              wait_rendering (obj) to make sure all drawing is complete.
3009  *              This will include an MI_FLUSH to get the data from GPU
3010  *              to memory
3011  *              clflush (obj) to invalidate the CPU cache
3012  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3013  *      5. Read/written by CPU
3014  *              cache lines are loaded and dirtied
3015  *      6. Read written by GPU
3016  *              Same as last GPU access
3017  *
3018  * Case 3: The constant buffer
3019  *
3020  *      1. Allocated
3021  *      2. Written by CPU
3022  *      3. Read by GPU
3023  *      4. Updated (written) by CPU again
3024  *      5. Read by GPU
3025  *
3026  *      1. Allocated
3027  *              (CPU, CPU)
3028  *      2. Written by CPU
3029  *              (CPU, CPU)
3030  *      3. Read by GPU
3031  *              (CPU+RENDER, 0)
3032  *              flush_domains = CPU
3033  *              invalidate_domains = RENDER
3034  *              clflush (obj)
3035  *              MI_FLUSH
3036  *              drm_agp_chipset_flush
3037  *      4. Updated (written) by CPU again
3038  *              (CPU, CPU)
3039  *              flush_domains = 0 (no previous write domain)
3040  *              invalidate_domains = 0 (no new read domains)
3041  *      5. Read by GPU
3042  *              (CPU+RENDER, 0)
3043  *              flush_domains = CPU
3044  *              invalidate_domains = RENDER
3045  *              clflush (obj)
3046  *              MI_FLUSH
3047  *              drm_agp_chipset_flush
3048  */
3049 static void
3050 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3051 {
3052         struct drm_device               *dev = obj->dev;
3053         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
3054         uint32_t                        invalidate_domains = 0;
3055         uint32_t                        flush_domains = 0;
3056         uint32_t                        old_read_domains;
3057
3058         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3059         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3060
3061         intel_mark_busy(dev, obj);
3062
3063 #if WATCH_BUF
3064         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3065                  __func__, obj,
3066                  obj->read_domains, obj->pending_read_domains,
3067                  obj->write_domain, obj->pending_write_domain);
3068 #endif
3069         /*
3070          * If the object isn't moving to a new write domain,
3071          * let the object stay in multiple read domains
3072          */
3073         if (obj->pending_write_domain == 0)
3074                 obj->pending_read_domains |= obj->read_domains;
3075         else
3076                 obj_priv->dirty = 1;
3077
3078         /*
3079          * Flush the current write domain if
3080          * the new read domains don't match. Invalidate
3081          * any read domains which differ from the old
3082          * write domain
3083          */
3084         if (obj->write_domain &&
3085             obj->write_domain != obj->pending_read_domains) {
3086                 flush_domains |= obj->write_domain;
3087                 invalidate_domains |=
3088                         obj->pending_read_domains & ~obj->write_domain;
3089         }
3090         /*
3091          * Invalidate any read caches which may have
3092          * stale data. That is, any new read domains.
3093          */
3094         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3095         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3096 #if WATCH_BUF
3097                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3098                          __func__, flush_domains, invalidate_domains);
3099 #endif
3100                 i915_gem_clflush_object(obj);
3101         }
3102
3103         old_read_domains = obj->read_domains;
3104
3105         /* The actual obj->write_domain will be updated with
3106          * pending_write_domain after we emit the accumulated flush for all
3107          * of our domain changes in execbuffers (which clears objects'
3108          * write_domains).  So if we have a current write domain that we
3109          * aren't changing, set pending_write_domain to that.
3110          */
3111         if (flush_domains == 0 && obj->pending_write_domain == 0)
3112                 obj->pending_write_domain = obj->write_domain;
3113         obj->read_domains = obj->pending_read_domains;
3114
3115         dev->invalidate_domains |= invalidate_domains;
3116         dev->flush_domains |= flush_domains;
3117 #if WATCH_BUF
3118         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3119                  __func__,
3120                  obj->read_domains, obj->write_domain,
3121                  dev->invalidate_domains, dev->flush_domains);
3122 #endif
3123
3124         trace_i915_gem_object_change_domain(obj,
3125                                             old_read_domains,
3126                                             obj->write_domain);
3127 }
3128
3129 /**
3130  * Moves the object from a partially CPU read to a full one.
3131  *
3132  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3133  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3134  */
3135 static void
3136 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3137 {
3138         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3139
3140         if (!obj_priv->page_cpu_valid)
3141                 return;
3142
3143         /* If we're partially in the CPU read domain, finish moving it in.
3144          */
3145         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3146                 int i;
3147
3148                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3149                         if (obj_priv->page_cpu_valid[i])
3150                                 continue;
3151                         drm_clflush_pages(obj_priv->pages + i, 1);
3152                 }
3153         }
3154
3155         /* Free the page_cpu_valid mappings which are now stale, whether
3156          * or not we've got I915_GEM_DOMAIN_CPU.
3157          */
3158         kfree(obj_priv->page_cpu_valid);
3159         obj_priv->page_cpu_valid = NULL;
3160 }
3161
3162 /**
3163  * Set the CPU read domain on a range of the object.
3164  *
3165  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3166  * not entirely valid.  The page_cpu_valid member of the object flags which
3167  * pages have been flushed, and will be respected by
3168  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3169  * of the whole object.
3170  *
3171  * This function returns when the move is complete, including waiting on
3172  * flushes to occur.
3173  */
3174 static int
3175 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3176                                           uint64_t offset, uint64_t size)
3177 {
3178         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3179         uint32_t old_read_domains;
3180         int i, ret;
3181
3182         if (offset == 0 && size == obj->size)
3183                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3184
3185         i915_gem_object_flush_gpu_write_domain(obj);
3186         /* Wait on any GPU rendering and flushing to occur. */
3187         ret = i915_gem_object_wait_rendering(obj);
3188         if (ret != 0)
3189                 return ret;
3190         i915_gem_object_flush_gtt_write_domain(obj);
3191
3192         /* If we're already fully in the CPU read domain, we're done. */
3193         if (obj_priv->page_cpu_valid == NULL &&
3194             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3195                 return 0;
3196
3197         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3198          * newly adding I915_GEM_DOMAIN_CPU
3199          */
3200         if (obj_priv->page_cpu_valid == NULL) {
3201                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3202                                                    GFP_KERNEL);
3203                 if (obj_priv->page_cpu_valid == NULL)
3204                         return -ENOMEM;
3205         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3206                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3207
3208         /* Flush the cache on any pages that are still invalid from the CPU's
3209          * perspective.
3210          */
3211         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3212              i++) {
3213                 if (obj_priv->page_cpu_valid[i])
3214                         continue;
3215
3216                 drm_clflush_pages(obj_priv->pages + i, 1);
3217
3218                 obj_priv->page_cpu_valid[i] = 1;
3219         }
3220
3221         /* It should now be out of any other write domains, and we can update
3222          * the domain values for our changes.
3223          */
3224         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3225
3226         old_read_domains = obj->read_domains;
3227         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3228
3229         trace_i915_gem_object_change_domain(obj,
3230                                             old_read_domains,
3231                                             obj->write_domain);
3232
3233         return 0;
3234 }
3235
3236 /**
3237  * Pin an object to the GTT and evaluate the relocations landing in it.
3238  */
3239 static int
3240 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3241                                  struct drm_file *file_priv,
3242                                  struct drm_i915_gem_exec_object2 *entry,
3243                                  struct drm_i915_gem_relocation_entry *relocs)
3244 {
3245         struct drm_device *dev = obj->dev;
3246         drm_i915_private_t *dev_priv = dev->dev_private;
3247         struct drm_i915_gem_object *obj_priv = obj->driver_private;
3248         int i, ret;
3249         void __iomem *reloc_page;
3250         bool need_fence;
3251
3252         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3253                      obj_priv->tiling_mode != I915_TILING_NONE;
3254
3255         /* Check fence reg constraints and rebind if necessary */
3256         if (need_fence && !i915_obj_fenceable(dev, obj))
3257                 i915_gem_object_unbind(obj);
3258
3259         /* Choose the GTT offset for our buffer and put it there. */
3260         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3261         if (ret)
3262                 return ret;
3263
3264         /*
3265          * Pre-965 chips need a fence register set up in order to
3266          * properly handle blits to/from tiled surfaces.
3267          */
3268         if (need_fence) {
3269                 ret = i915_gem_object_get_fence_reg(obj);
3270                 if (ret != 0) {
3271                         if (ret != -EBUSY && ret != -ERESTARTSYS)
3272                                 DRM_ERROR("Failure to install fence: %d\n",
3273                                           ret);
3274                         i915_gem_object_unpin(obj);
3275                         return ret;
3276                 }
3277         }
3278
3279         entry->offset = obj_priv->gtt_offset;
3280
3281         /* Apply the relocations, using the GTT aperture to avoid cache
3282          * flushing requirements.
3283          */
3284         for (i = 0; i < entry->relocation_count; i++) {
3285                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3286                 struct drm_gem_object *target_obj;
3287                 struct drm_i915_gem_object *target_obj_priv;
3288                 uint32_t reloc_val, reloc_offset;
3289                 uint32_t __iomem *reloc_entry;
3290
3291                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3292                                                    reloc->target_handle);
3293                 if (target_obj == NULL) {
3294                         i915_gem_object_unpin(obj);
3295                         return -EBADF;
3296                 }
3297                 target_obj_priv = target_obj->driver_private;
3298
3299 #if WATCH_RELOC
3300                 DRM_INFO("%s: obj %p offset %08x target %d "
3301                          "read %08x write %08x gtt %08x "
3302                          "presumed %08x delta %08x\n",
3303                          __func__,
3304                          obj,
3305                          (int) reloc->offset,
3306                          (int) reloc->target_handle,
3307                          (int) reloc->read_domains,
3308                          (int) reloc->write_domain,
3309                          (int) target_obj_priv->gtt_offset,
3310                          (int) reloc->presumed_offset,
3311                          reloc->delta);
3312 #endif
3313
3314                 /* The target buffer should have appeared before us in the
3315                  * exec_object list, so it should have a GTT space bound by now.
3316                  */
3317                 if (target_obj_priv->gtt_space == NULL) {
3318                         DRM_ERROR("No GTT space found for object %d\n",
3319                                   reloc->target_handle);
3320                         drm_gem_object_unreference(target_obj);
3321                         i915_gem_object_unpin(obj);
3322                         return -EINVAL;
3323                 }
3324
3325                 /* Validate that the target is in a valid r/w GPU domain */
3326                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3327                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3328                         DRM_ERROR("reloc with read/write CPU domains: "
3329                                   "obj %p target %d offset %d "
3330                                   "read %08x write %08x",
3331                                   obj, reloc->target_handle,
3332                                   (int) reloc->offset,
3333                                   reloc->read_domains,
3334                                   reloc->write_domain);
3335                         drm_gem_object_unreference(target_obj);
3336                         i915_gem_object_unpin(obj);
3337                         return -EINVAL;
3338                 }
3339                 if (reloc->write_domain && target_obj->pending_write_domain &&
3340                     reloc->write_domain != target_obj->pending_write_domain) {
3341                         DRM_ERROR("Write domain conflict: "
3342                                   "obj %p target %d offset %d "
3343                                   "new %08x old %08x\n",
3344                                   obj, reloc->target_handle,
3345                                   (int) reloc->offset,
3346                                   reloc->write_domain,
3347                                   target_obj->pending_write_domain);
3348                         drm_gem_object_unreference(target_obj);
3349                         i915_gem_object_unpin(obj);
3350                         return -EINVAL;
3351                 }
3352
3353                 target_obj->pending_read_domains |= reloc->read_domains;
3354                 target_obj->pending_write_domain |= reloc->write_domain;
3355
3356                 /* If the relocation already has the right value in it, no
3357                  * more work needs to be done.
3358                  */
3359                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3360                         drm_gem_object_unreference(target_obj);
3361                         continue;
3362                 }
3363
3364                 /* Check that the relocation address is valid... */
3365                 if (reloc->offset > obj->size - 4) {
3366                         DRM_ERROR("Relocation beyond object bounds: "
3367                                   "obj %p target %d offset %d size %d.\n",
3368                                   obj, reloc->target_handle,
3369                                   (int) reloc->offset, (int) obj->size);
3370                         drm_gem_object_unreference(target_obj);
3371                         i915_gem_object_unpin(obj);
3372                         return -EINVAL;
3373                 }
3374                 if (reloc->offset & 3) {
3375                         DRM_ERROR("Relocation not 4-byte aligned: "
3376                                   "obj %p target %d offset %d.\n",
3377                                   obj, reloc->target_handle,
3378                                   (int) reloc->offset);
3379                         drm_gem_object_unreference(target_obj);
3380                         i915_gem_object_unpin(obj);
3381                         return -EINVAL;
3382                 }
3383
3384                 /* and points to somewhere within the target object. */
3385                 if (reloc->delta >= target_obj->size) {
3386                         DRM_ERROR("Relocation beyond target object bounds: "
3387                                   "obj %p target %d delta %d size %d.\n",
3388                                   obj, reloc->target_handle,
3389                                   (int) reloc->delta, (int) target_obj->size);
3390                         drm_gem_object_unreference(target_obj);
3391                         i915_gem_object_unpin(obj);
3392                         return -EINVAL;
3393                 }
3394
3395                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3396                 if (ret != 0) {
3397                         drm_gem_object_unreference(target_obj);
3398                         i915_gem_object_unpin(obj);
3399                         return -EINVAL;
3400                 }
3401
3402                 /* Map the page containing the relocation we're going to
3403                  * perform.
3404                  */
3405                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3406                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3407                                                       (reloc_offset &
3408                                                        ~(PAGE_SIZE - 1)));
3409                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3410                                                    (reloc_offset & (PAGE_SIZE - 1)));
3411                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3412
3413 #if WATCH_BUF
3414                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3415                           obj, (unsigned int) reloc->offset,
3416                           readl(reloc_entry), reloc_val);
3417 #endif
3418                 writel(reloc_val, reloc_entry);
3419                 io_mapping_unmap_atomic(reloc_page);
3420
3421                 /* The updated presumed offset for this entry will be
3422                  * copied back out to the user.
3423                  */
3424                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3425
3426                 drm_gem_object_unreference(target_obj);
3427         }
3428
3429 #if WATCH_BUF
3430         if (0)
3431                 i915_gem_dump_object(obj, 128, __func__, ~0);
3432 #endif
3433         return 0;
3434 }
3435
3436 /** Dispatch a batchbuffer to the ring
3437  */
3438 static int
3439 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3440                               struct drm_i915_gem_execbuffer2 *exec,
3441                               struct drm_clip_rect *cliprects,
3442                               uint64_t exec_offset)
3443 {
3444         drm_i915_private_t *dev_priv = dev->dev_private;
3445         int nbox = exec->num_cliprects;
3446         int i = 0, count;
3447         uint32_t exec_start, exec_len;
3448         RING_LOCALS;
3449
3450         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3451         exec_len = (uint32_t) exec->batch_len;
3452
3453         trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
3454
3455         count = nbox ? nbox : 1;
3456
3457         for (i = 0; i < count; i++) {
3458                 if (i < nbox) {
3459                         int ret = i915_emit_box(dev, cliprects, i,
3460                                                 exec->DR1, exec->DR4);
3461                         if (ret)
3462                                 return ret;
3463                 }
3464
3465                 if (IS_I830(dev) || IS_845G(dev)) {
3466                         BEGIN_LP_RING(4);
3467                         OUT_RING(MI_BATCH_BUFFER);
3468                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3469                         OUT_RING(exec_start + exec_len - 4);
3470                         OUT_RING(0);
3471                         ADVANCE_LP_RING();
3472                 } else {
3473                         BEGIN_LP_RING(2);
3474                         if (IS_I965G(dev)) {
3475                                 OUT_RING(MI_BATCH_BUFFER_START |
3476                                          (2 << 6) |
3477                                          MI_BATCH_NON_SECURE_I965);
3478                                 OUT_RING(exec_start);
3479                         } else {
3480                                 OUT_RING(MI_BATCH_BUFFER_START |
3481                                          (2 << 6));
3482                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3483                         }
3484                         ADVANCE_LP_RING();
3485                 }
3486         }
3487
3488         /* XXX breadcrumb */
3489         return 0;
3490 }
3491
3492 /* Throttle our rendering by waiting until the ring has completed our requests
3493  * emitted over 20 msec ago.
3494  *
3495  * Note that if we were to use the current jiffies each time around the loop,
3496  * we wouldn't escape the function with any frames outstanding if the time to
3497  * render a frame was over 20ms.
3498  *
3499  * This should get us reasonable parallelism between CPU and GPU but also
3500  * relatively low latency when blocking on a particular request to finish.
3501  */
3502 static int
3503 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3504 {
3505         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3506         int ret = 0;
3507         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3508
3509         mutex_lock(&dev->struct_mutex);
3510         while (!list_empty(&i915_file_priv->mm.request_list)) {
3511                 struct drm_i915_gem_request *request;
3512
3513                 request = list_first_entry(&i915_file_priv->mm.request_list,
3514                                            struct drm_i915_gem_request,
3515                                            client_list);
3516
3517                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3518                         break;
3519
3520                 ret = i915_wait_request(dev, request->seqno);
3521                 if (ret != 0)
3522                         break;
3523         }
3524         mutex_unlock(&dev->struct_mutex);
3525
3526         return ret;
3527 }
3528
3529 static int
3530 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3531                               uint32_t buffer_count,
3532                               struct drm_i915_gem_relocation_entry **relocs)
3533 {
3534         uint32_t reloc_count = 0, reloc_index = 0, i;
3535         int ret;
3536
3537         *relocs = NULL;
3538         for (i = 0; i < buffer_count; i++) {
3539                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3540                         return -EINVAL;
3541                 reloc_count += exec_list[i].relocation_count;
3542         }
3543
3544         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3545         if (*relocs == NULL) {
3546                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3547                 return -ENOMEM;
3548         }
3549
3550         for (i = 0; i < buffer_count; i++) {
3551                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3552
3553                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3554
3555                 ret = copy_from_user(&(*relocs)[reloc_index],
3556                                      user_relocs,
3557                                      exec_list[i].relocation_count *
3558                                      sizeof(**relocs));
3559                 if (ret != 0) {
3560                         drm_free_large(*relocs);
3561                         *relocs = NULL;
3562                         return -EFAULT;
3563                 }
3564
3565                 reloc_index += exec_list[i].relocation_count;
3566         }
3567
3568         return 0;
3569 }
3570
3571 static int
3572 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3573                             uint32_t buffer_count,
3574                             struct drm_i915_gem_relocation_entry *relocs)
3575 {
3576         uint32_t reloc_count = 0, i;
3577         int ret = 0;
3578
3579         if (relocs == NULL)
3580             return 0;
3581
3582         for (i = 0; i < buffer_count; i++) {
3583                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3584                 int unwritten;
3585
3586                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3587
3588                 unwritten = copy_to_user(user_relocs,
3589                                          &relocs[reloc_count],
3590                                          exec_list[i].relocation_count *
3591                                          sizeof(*relocs));
3592
3593                 if (unwritten) {
3594                         ret = -EFAULT;
3595                         goto err;
3596                 }
3597
3598                 reloc_count += exec_list[i].relocation_count;
3599         }
3600
3601 err:
3602         drm_free_large(relocs);
3603
3604         return ret;
3605 }
3606
3607 static int
3608 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3609                            uint64_t exec_offset)
3610 {
3611         uint32_t exec_start, exec_len;
3612
3613         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3614         exec_len = (uint32_t) exec->batch_len;
3615
3616         if ((exec_start | exec_len) & 0x7)
3617                 return -EINVAL;
3618
3619         if (!exec_start)
3620                 return -EINVAL;
3621
3622         return 0;
3623 }
3624
3625 static int
3626 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3627                                struct drm_gem_object **object_list,
3628                                int count)
3629 {
3630         drm_i915_private_t *dev_priv = dev->dev_private;
3631         struct drm_i915_gem_object *obj_priv;
3632         DEFINE_WAIT(wait);
3633         int i, ret = 0;
3634
3635         for (;;) {
3636                 prepare_to_wait(&dev_priv->pending_flip_queue,
3637                                 &wait, TASK_INTERRUPTIBLE);
3638                 for (i = 0; i < count; i++) {
3639                         obj_priv = object_list[i]->driver_private;
3640                         if (atomic_read(&obj_priv->pending_flip) > 0)
3641                                 break;
3642                 }
3643                 if (i == count)
3644                         break;
3645
3646                 if (!signal_pending(current)) {
3647                         mutex_unlock(&dev->struct_mutex);
3648                         schedule();
3649                         mutex_lock(&dev->struct_mutex);
3650                         continue;
3651                 }
3652                 ret = -ERESTARTSYS;
3653                 break;
3654         }
3655         finish_wait(&dev_priv->pending_flip_queue, &wait);
3656
3657         return ret;
3658 }
3659
3660 int
3661 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3662                        struct drm_file *file_priv,
3663                        struct drm_i915_gem_execbuffer2 *args,
3664                        struct drm_i915_gem_exec_object2 *exec_list)
3665 {
3666         drm_i915_private_t *dev_priv = dev->dev_private;
3667         struct drm_gem_object **object_list = NULL;
3668         struct drm_gem_object *batch_obj;
3669         struct drm_i915_gem_object *obj_priv;
3670         struct drm_clip_rect *cliprects = NULL;
3671         struct drm_i915_gem_relocation_entry *relocs = NULL;
3672         int ret = 0, ret2, i, pinned = 0;
3673         uint64_t exec_offset;
3674         uint32_t seqno, flush_domains, reloc_index;
3675         int pin_tries, flips;
3676
3677 #if WATCH_EXEC
3678         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3679                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3680 #endif
3681
3682         if (args->buffer_count < 1) {
3683                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3684                 return -EINVAL;
3685         }
3686         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3687         if (object_list == NULL) {
3688                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3689                           args->buffer_count);
3690                 ret = -ENOMEM;
3691                 goto pre_mutex_err;
3692         }
3693
3694         if (args->num_cliprects != 0) {
3695                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3696                                     GFP_KERNEL);
3697                 if (cliprects == NULL) {
3698                         ret = -ENOMEM;
3699                         goto pre_mutex_err;
3700                 }
3701
3702                 ret = copy_from_user(cliprects,
3703                                      (struct drm_clip_rect __user *)
3704                                      (uintptr_t) args->cliprects_ptr,
3705                                      sizeof(*cliprects) * args->num_cliprects);
3706                 if (ret != 0) {
3707                         DRM_ERROR("copy %d cliprects failed: %d\n",
3708                                   args->num_cliprects, ret);
3709                         goto pre_mutex_err;
3710                 }
3711         }
3712
3713         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3714                                             &relocs);
3715         if (ret != 0)
3716                 goto pre_mutex_err;
3717
3718         mutex_lock(&dev->struct_mutex);
3719
3720         i915_verify_inactive(dev, __FILE__, __LINE__);
3721
3722         if (atomic_read(&dev_priv->mm.wedged)) {
3723                 mutex_unlock(&dev->struct_mutex);
3724                 ret = -EIO;
3725                 goto pre_mutex_err;
3726         }
3727
3728         if (dev_priv->mm.suspended) {
3729                 mutex_unlock(&dev->struct_mutex);
3730                 ret = -EBUSY;
3731                 goto pre_mutex_err;
3732         }
3733
3734         /* Look up object handles */
3735         flips = 0;
3736         for (i = 0; i < args->buffer_count; i++) {
3737                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3738                                                        exec_list[i].handle);
3739                 if (object_list[i] == NULL) {
3740                         DRM_ERROR("Invalid object handle %d at index %d\n",
3741                                    exec_list[i].handle, i);
3742                         /* prevent error path from reading uninitialized data */
3743                         args->buffer_count = i + 1;
3744                         ret = -EBADF;
3745                         goto err;
3746                 }
3747
3748                 obj_priv = object_list[i]->driver_private;
3749                 if (obj_priv->in_execbuffer) {
3750                         DRM_ERROR("Object %p appears more than once in object list\n",
3751                                    object_list[i]);
3752                         /* prevent error path from reading uninitialized data */
3753                         args->buffer_count = i + 1;
3754                         ret = -EBADF;
3755                         goto err;
3756                 }
3757                 obj_priv->in_execbuffer = true;
3758                 flips += atomic_read(&obj_priv->pending_flip);
3759         }
3760
3761         if (flips > 0) {
3762                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3763                                                      args->buffer_count);
3764                 if (ret)
3765                         goto err;
3766         }
3767
3768         /* Pin and relocate */
3769         for (pin_tries = 0; ; pin_tries++) {
3770                 ret = 0;
3771                 reloc_index = 0;
3772
3773                 for (i = 0; i < args->buffer_count; i++) {
3774                         object_list[i]->pending_read_domains = 0;
3775                         object_list[i]->pending_write_domain = 0;
3776                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3777                                                                file_priv,
3778                                                                &exec_list[i],
3779                                                                &relocs[reloc_index]);
3780                         if (ret)
3781                                 break;
3782                         pinned = i + 1;
3783                         reloc_index += exec_list[i].relocation_count;
3784                 }
3785                 /* success */
3786                 if (ret == 0)
3787                         break;
3788
3789                 /* error other than GTT full, or we've already tried again */
3790                 if (ret != -ENOSPC || pin_tries >= 1) {
3791                         if (ret != -ERESTARTSYS) {
3792                                 unsigned long long total_size = 0;
3793                                 for (i = 0; i < args->buffer_count; i++)
3794                                         total_size += object_list[i]->size;
3795                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3796                                           pinned+1, args->buffer_count,
3797                                           total_size, ret);
3798                                 DRM_ERROR("%d objects [%d pinned], "
3799                                           "%d object bytes [%d pinned], "
3800                                           "%d/%d gtt bytes\n",
3801                                           atomic_read(&dev->object_count),
3802                                           atomic_read(&dev->pin_count),
3803                                           atomic_read(&dev->object_memory),
3804                                           atomic_read(&dev->pin_memory),
3805                                           atomic_read(&dev->gtt_memory),
3806                                           dev->gtt_total);
3807                         }
3808                         goto err;
3809                 }
3810
3811                 /* unpin all of our buffers */
3812                 for (i = 0; i < pinned; i++)
3813                         i915_gem_object_unpin(object_list[i]);
3814                 pinned = 0;
3815
3816                 /* evict everyone we can from the aperture */
3817                 ret = i915_gem_evict_everything(dev);
3818                 if (ret && ret != -ENOSPC)
3819                         goto err;
3820         }
3821
3822         /* Set the pending read domains for the batch buffer to COMMAND */
3823         batch_obj = object_list[args->buffer_count-1];
3824         if (batch_obj->pending_write_domain) {
3825                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3826                 ret = -EINVAL;
3827                 goto err;
3828         }
3829         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3830
3831         /* Sanity check the batch buffer, prior to moving objects */
3832         exec_offset = exec_list[args->buffer_count - 1].offset;
3833         ret = i915_gem_check_execbuffer (args, exec_offset);
3834         if (ret != 0) {
3835                 DRM_ERROR("execbuf with invalid offset/length\n");
3836                 goto err;
3837         }
3838
3839         i915_verify_inactive(dev, __FILE__, __LINE__);
3840
3841         /* Zero the global flush/invalidate flags. These
3842          * will be modified as new domains are computed
3843          * for each object
3844          */
3845         dev->invalidate_domains = 0;
3846         dev->flush_domains = 0;
3847
3848         for (i = 0; i < args->buffer_count; i++) {
3849                 struct drm_gem_object *obj = object_list[i];
3850
3851                 /* Compute new gpu domains and update invalidate/flush */
3852                 i915_gem_object_set_to_gpu_domain(obj);
3853         }
3854
3855         i915_verify_inactive(dev, __FILE__, __LINE__);
3856
3857         if (dev->invalidate_domains | dev->flush_domains) {
3858 #if WATCH_EXEC
3859                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3860                           __func__,
3861                          dev->invalidate_domains,
3862                          dev->flush_domains);
3863 #endif
3864                 i915_gem_flush(dev,
3865                                dev->invalidate_domains,
3866                                dev->flush_domains);
3867                 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
3868                         (void)i915_add_request(dev, file_priv,
3869                                                dev->flush_domains);
3870         }
3871
3872         for (i = 0; i < args->buffer_count; i++) {
3873                 struct drm_gem_object *obj = object_list[i];
3874                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3875                 uint32_t old_write_domain = obj->write_domain;
3876
3877                 obj->write_domain = obj->pending_write_domain;
3878                 if (obj->write_domain)
3879                         list_move_tail(&obj_priv->gpu_write_list,
3880                                        &dev_priv->mm.gpu_write_list);
3881                 else
3882                         list_del_init(&obj_priv->gpu_write_list);
3883
3884                 trace_i915_gem_object_change_domain(obj,
3885                                                     obj->read_domains,
3886                                                     old_write_domain);
3887         }
3888
3889         i915_verify_inactive(dev, __FILE__, __LINE__);
3890
3891 #if WATCH_COHERENCY
3892         for (i = 0; i < args->buffer_count; i++) {
3893                 i915_gem_object_check_coherency(object_list[i],
3894                                                 exec_list[i].handle);
3895         }
3896 #endif
3897
3898 #if WATCH_EXEC
3899         i915_gem_dump_object(batch_obj,
3900                               args->batch_len,
3901                               __func__,
3902                               ~0);
3903 #endif
3904
3905         /* Exec the batchbuffer */
3906         ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3907         if (ret) {
3908                 DRM_ERROR("dispatch failed %d\n", ret);
3909                 goto err;
3910         }
3911
3912         /*
3913          * Ensure that the commands in the batch buffer are
3914          * finished before the interrupt fires
3915          */
3916         flush_domains = i915_retire_commands(dev);
3917
3918         i915_verify_inactive(dev, __FILE__, __LINE__);
3919
3920         /*
3921          * Get a seqno representing the execution of the current buffer,
3922          * which we can wait on.  We would like to mitigate these interrupts,
3923          * likely by only creating seqnos occasionally (so that we have
3924          * *some* interrupts representing completion of buffers that we can
3925          * wait on when trying to clear up gtt space).
3926          */
3927         seqno = i915_add_request(dev, file_priv, flush_domains);
3928         BUG_ON(seqno == 0);
3929         for (i = 0; i < args->buffer_count; i++) {
3930                 struct drm_gem_object *obj = object_list[i];
3931
3932                 i915_gem_object_move_to_active(obj, seqno);
3933 #if WATCH_LRU
3934                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3935 #endif
3936         }
3937 #if WATCH_LRU
3938         i915_dump_lru(dev, __func__);
3939 #endif
3940
3941         i915_verify_inactive(dev, __FILE__, __LINE__);
3942
3943 err:
3944         for (i = 0; i < pinned; i++)
3945                 i915_gem_object_unpin(object_list[i]);
3946
3947         for (i = 0; i < args->buffer_count; i++) {
3948                 if (object_list[i]) {
3949                         obj_priv = object_list[i]->driver_private;
3950                         obj_priv->in_execbuffer = false;
3951                 }
3952                 drm_gem_object_unreference(object_list[i]);
3953         }
3954
3955         mutex_unlock(&dev->struct_mutex);
3956
3957 pre_mutex_err:
3958         /* Copy the updated relocations out regardless of current error
3959          * state.  Failure to update the relocs would mean that the next
3960          * time userland calls execbuf, it would do so with presumed offset
3961          * state that didn't match the actual object state.
3962          */
3963         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3964                                            relocs);
3965         if (ret2 != 0) {
3966                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3967
3968                 if (ret == 0)
3969                         ret = ret2;
3970         }
3971
3972         drm_free_large(object_list);
3973         kfree(cliprects);
3974
3975         return ret;
3976 }
3977
3978 /*
3979  * Legacy execbuffer just creates an exec2 list from the original exec object
3980  * list array and passes it to the real function.
3981  */
3982 int
3983 i915_gem_execbuffer(struct drm_device *dev, void *data,
3984                     struct drm_file *file_priv)
3985 {
3986         struct drm_i915_gem_execbuffer *args = data;
3987         struct drm_i915_gem_execbuffer2 exec2;
3988         struct drm_i915_gem_exec_object *exec_list = NULL;
3989         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3990         int ret, i;
3991
3992 #if WATCH_EXEC
3993         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3994                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3995 #endif
3996
3997         if (args->buffer_count < 1) {
3998                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3999                 return -EINVAL;
4000         }
4001
4002         /* Copy in the exec list from userland */
4003         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4004         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4005         if (exec_list == NULL || exec2_list == NULL) {
4006                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4007                           args->buffer_count);
4008                 drm_free_large(exec_list);
4009                 drm_free_large(exec2_list);
4010                 return -ENOMEM;
4011         }
4012         ret = copy_from_user(exec_list,
4013                              (struct drm_i915_relocation_entry __user *)
4014                              (uintptr_t) args->buffers_ptr,
4015                              sizeof(*exec_list) * args->buffer_count);
4016         if (ret != 0) {
4017                 DRM_ERROR("copy %d exec entries failed %d\n",
4018                           args->buffer_count, ret);
4019                 drm_free_large(exec_list);
4020                 drm_free_large(exec2_list);
4021                 return -EFAULT;
4022         }
4023
4024         for (i = 0; i < args->buffer_count; i++) {
4025                 exec2_list[i].handle = exec_list[i].handle;
4026                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4027                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4028                 exec2_list[i].alignment = exec_list[i].alignment;
4029                 exec2_list[i].offset = exec_list[i].offset;
4030                 if (!IS_I965G(dev))
4031                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4032                 else
4033                         exec2_list[i].flags = 0;
4034         }
4035
4036         exec2.buffers_ptr = args->buffers_ptr;
4037         exec2.buffer_count = args->buffer_count;
4038         exec2.batch_start_offset = args->batch_start_offset;
4039         exec2.batch_len = args->batch_len;
4040         exec2.DR1 = args->DR1;
4041         exec2.DR4 = args->DR4;
4042         exec2.num_cliprects = args->num_cliprects;
4043         exec2.cliprects_ptr = args->cliprects_ptr;
4044         exec2.flags = 0;
4045
4046         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4047         if (!ret) {
4048                 /* Copy the new buffer offsets back to the user's exec list. */
4049                 for (i = 0; i < args->buffer_count; i++)
4050                         exec_list[i].offset = exec2_list[i].offset;
4051                 /* ... and back out to userspace */
4052                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4053                                    (uintptr_t) args->buffers_ptr,
4054                                    exec_list,
4055                                    sizeof(*exec_list) * args->buffer_count);
4056                 if (ret) {
4057                         ret = -EFAULT;
4058                         DRM_ERROR("failed to copy %d exec entries "
4059                                   "back to user (%d)\n",
4060                                   args->buffer_count, ret);
4061                 }
4062         }
4063
4064         drm_free_large(exec_list);
4065         drm_free_large(exec2_list);
4066         return ret;
4067 }
4068
4069 int
4070 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4071                      struct drm_file *file_priv)
4072 {
4073         struct drm_i915_gem_execbuffer2 *args = data;
4074         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4075         int ret;
4076
4077 #if WATCH_EXEC
4078         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4079                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4080 #endif
4081
4082         if (args->buffer_count < 1) {
4083                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4084                 return -EINVAL;
4085         }
4086
4087         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4088         if (exec2_list == NULL) {
4089                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4090                           args->buffer_count);
4091                 return -ENOMEM;
4092         }
4093         ret = copy_from_user(exec2_list,
4094                              (struct drm_i915_relocation_entry __user *)
4095                              (uintptr_t) args->buffers_ptr,
4096                              sizeof(*exec2_list) * args->buffer_count);
4097         if (ret != 0) {
4098                 DRM_ERROR("copy %d exec entries failed %d\n",
4099                           args->buffer_count, ret);
4100                 drm_free_large(exec2_list);
4101                 return -EFAULT;
4102         }
4103
4104         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4105         if (!ret) {
4106                 /* Copy the new buffer offsets back to the user's exec list. */
4107                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4108                                    (uintptr_t) args->buffers_ptr,
4109                                    exec2_list,
4110                                    sizeof(*exec2_list) * args->buffer_count);
4111                 if (ret) {
4112                         ret = -EFAULT;
4113                         DRM_ERROR("failed to copy %d exec entries "
4114                                   "back to user (%d)\n",
4115                                   args->buffer_count, ret);
4116                 }
4117         }
4118
4119         drm_free_large(exec2_list);
4120         return ret;
4121 }
4122
4123 int
4124 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4125 {
4126         struct drm_device *dev = obj->dev;
4127         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4128         int ret;
4129
4130         i915_verify_inactive(dev, __FILE__, __LINE__);
4131         if (obj_priv->gtt_space == NULL) {
4132                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4133                 if (ret)
4134                         return ret;
4135         }
4136
4137         obj_priv->pin_count++;
4138
4139         /* If the object is not active and not pending a flush,
4140          * remove it from the inactive list
4141          */
4142         if (obj_priv->pin_count == 1) {
4143                 atomic_inc(&dev->pin_count);
4144                 atomic_add(obj->size, &dev->pin_memory);
4145                 if (!obj_priv->active &&
4146                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4147                     !list_empty(&obj_priv->list))
4148                         list_del_init(&obj_priv->list);
4149         }
4150         i915_verify_inactive(dev, __FILE__, __LINE__);
4151
4152         return 0;
4153 }
4154
4155 void
4156 i915_gem_object_unpin(struct drm_gem_object *obj)
4157 {
4158         struct drm_device *dev = obj->dev;
4159         drm_i915_private_t *dev_priv = dev->dev_private;
4160         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4161
4162         i915_verify_inactive(dev, __FILE__, __LINE__);
4163         obj_priv->pin_count--;
4164         BUG_ON(obj_priv->pin_count < 0);
4165         BUG_ON(obj_priv->gtt_space == NULL);
4166
4167         /* If the object is no longer pinned, and is
4168          * neither active nor being flushed, then stick it on
4169          * the inactive list
4170          */
4171         if (obj_priv->pin_count == 0) {
4172                 if (!obj_priv->active &&
4173                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4174                         list_move_tail(&obj_priv->list,
4175                                        &dev_priv->mm.inactive_list);
4176                 atomic_dec(&dev->pin_count);
4177                 atomic_sub(obj->size, &dev->pin_memory);
4178         }
4179         i915_verify_inactive(dev, __FILE__, __LINE__);
4180 }
4181
4182 int
4183 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4184                    struct drm_file *file_priv)
4185 {
4186         struct drm_i915_gem_pin *args = data;
4187         struct drm_gem_object *obj;
4188         struct drm_i915_gem_object *obj_priv;
4189         int ret;
4190
4191         mutex_lock(&dev->struct_mutex);
4192
4193         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4194         if (obj == NULL) {
4195                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4196                           args->handle);
4197                 mutex_unlock(&dev->struct_mutex);
4198                 return -EBADF;
4199         }
4200         obj_priv = obj->driver_private;
4201
4202         if (obj_priv->madv != I915_MADV_WILLNEED) {
4203                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4204                 drm_gem_object_unreference(obj);
4205                 mutex_unlock(&dev->struct_mutex);
4206                 return -EINVAL;
4207         }
4208
4209         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4210                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4211                           args->handle);
4212                 drm_gem_object_unreference(obj);
4213                 mutex_unlock(&dev->struct_mutex);
4214                 return -EINVAL;
4215         }
4216
4217         obj_priv->user_pin_count++;
4218         obj_priv->pin_filp = file_priv;
4219         if (obj_priv->user_pin_count == 1) {
4220                 ret = i915_gem_object_pin(obj, args->alignment);
4221                 if (ret != 0) {
4222                         drm_gem_object_unreference(obj);
4223                         mutex_unlock(&dev->struct_mutex);
4224                         return ret;
4225                 }
4226         }
4227
4228         /* XXX - flush the CPU caches for pinned objects
4229          * as the X server doesn't manage domains yet
4230          */
4231         i915_gem_object_flush_cpu_write_domain(obj);
4232         args->offset = obj_priv->gtt_offset;
4233         drm_gem_object_unreference(obj);
4234         mutex_unlock(&dev->struct_mutex);
4235
4236         return 0;
4237 }
4238
4239 int
4240 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4241                      struct drm_file *file_priv)
4242 {
4243         struct drm_i915_gem_pin *args = data;
4244         struct drm_gem_object *obj;
4245         struct drm_i915_gem_object *obj_priv;
4246
4247         mutex_lock(&dev->struct_mutex);
4248
4249         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4250         if (obj == NULL) {
4251                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4252                           args->handle);
4253                 mutex_unlock(&dev->struct_mutex);
4254                 return -EBADF;
4255         }
4256
4257         obj_priv = obj->driver_private;
4258         if (obj_priv->pin_filp != file_priv) {
4259                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4260                           args->handle);
4261                 drm_gem_object_unreference(obj);
4262                 mutex_unlock(&dev->struct_mutex);
4263                 return -EINVAL;
4264         }
4265         obj_priv->user_pin_count--;
4266         if (obj_priv->user_pin_count == 0) {
4267                 obj_priv->pin_filp = NULL;
4268                 i915_gem_object_unpin(obj);
4269         }
4270
4271         drm_gem_object_unreference(obj);
4272         mutex_unlock(&dev->struct_mutex);
4273         return 0;
4274 }
4275
4276 int
4277 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4278                     struct drm_file *file_priv)
4279 {
4280         struct drm_i915_gem_busy *args = data;
4281         struct drm_gem_object *obj;
4282         struct drm_i915_gem_object *obj_priv;
4283
4284         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4285         if (obj == NULL) {
4286                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4287                           args->handle);
4288                 return -EBADF;
4289         }
4290
4291         mutex_lock(&dev->struct_mutex);
4292         /* Update the active list for the hardware's current position.
4293          * Otherwise this only updates on a delayed timer or when irqs are
4294          * actually unmasked, and our working set ends up being larger than
4295          * required.
4296          */
4297         i915_gem_retire_requests(dev);
4298
4299         obj_priv = obj->driver_private;
4300         /* Don't count being on the flushing list against the object being
4301          * done.  Otherwise, a buffer left on the flushing list but not getting
4302          * flushed (because nobody's flushing that domain) won't ever return
4303          * unbusy and get reused by libdrm's bo cache.  The other expected
4304          * consumer of this interface, OpenGL's occlusion queries, also specs
4305          * that the objects get unbusy "eventually" without any interference.
4306          */
4307         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4308
4309         drm_gem_object_unreference(obj);
4310         mutex_unlock(&dev->struct_mutex);
4311         return 0;
4312 }
4313
4314 int
4315 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4316                         struct drm_file *file_priv)
4317 {
4318     return i915_gem_ring_throttle(dev, file_priv);
4319 }
4320
4321 int
4322 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4323                        struct drm_file *file_priv)
4324 {
4325         struct drm_i915_gem_madvise *args = data;
4326         struct drm_gem_object *obj;
4327         struct drm_i915_gem_object *obj_priv;
4328
4329         switch (args->madv) {
4330         case I915_MADV_DONTNEED:
4331         case I915_MADV_WILLNEED:
4332             break;
4333         default:
4334             return -EINVAL;
4335         }
4336
4337         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4338         if (obj == NULL) {
4339                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4340                           args->handle);
4341                 return -EBADF;
4342         }
4343
4344         mutex_lock(&dev->struct_mutex);
4345         obj_priv = obj->driver_private;
4346
4347         if (obj_priv->pin_count) {
4348                 drm_gem_object_unreference(obj);
4349                 mutex_unlock(&dev->struct_mutex);
4350
4351                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4352                 return -EINVAL;
4353         }
4354
4355         if (obj_priv->madv != __I915_MADV_PURGED)
4356                 obj_priv->madv = args->madv;
4357
4358         /* if the object is no longer bound, discard its backing storage */
4359         if (i915_gem_object_is_purgeable(obj_priv) &&
4360             obj_priv->gtt_space == NULL)
4361                 i915_gem_object_truncate(obj);
4362
4363         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4364
4365         drm_gem_object_unreference(obj);
4366         mutex_unlock(&dev->struct_mutex);
4367
4368         return 0;
4369 }
4370
4371 int i915_gem_init_object(struct drm_gem_object *obj)
4372 {
4373         struct drm_i915_gem_object *obj_priv;
4374
4375         obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4376         if (obj_priv == NULL)
4377                 return -ENOMEM;
4378
4379         /*
4380          * We've just allocated pages from the kernel,
4381          * so they've just been written by the CPU with
4382          * zeros. They'll need to be clflushed before we
4383          * use them with the GPU.
4384          */
4385         obj->write_domain = I915_GEM_DOMAIN_CPU;
4386         obj->read_domains = I915_GEM_DOMAIN_CPU;
4387
4388         obj_priv->agp_type = AGP_USER_MEMORY;
4389
4390         obj->driver_private = obj_priv;
4391         obj_priv->obj = obj;
4392         obj_priv->fence_reg = I915_FENCE_REG_NONE;
4393         INIT_LIST_HEAD(&obj_priv->list);
4394         INIT_LIST_HEAD(&obj_priv->gpu_write_list);
4395         INIT_LIST_HEAD(&obj_priv->fence_list);
4396         obj_priv->madv = I915_MADV_WILLNEED;
4397
4398         trace_i915_gem_object_create(obj);
4399
4400         return 0;
4401 }
4402
4403 void i915_gem_free_object(struct drm_gem_object *obj)
4404 {
4405         struct drm_device *dev = obj->dev;
4406         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4407
4408         trace_i915_gem_object_destroy(obj);
4409
4410         while (obj_priv->pin_count > 0)
4411                 i915_gem_object_unpin(obj);
4412
4413         if (obj_priv->phys_obj)
4414                 i915_gem_detach_phys_object(dev, obj);
4415
4416         i915_gem_object_unbind(obj);
4417
4418         if (obj_priv->mmap_offset)
4419                 i915_gem_free_mmap_offset(obj);
4420
4421         kfree(obj_priv->page_cpu_valid);
4422         kfree(obj_priv->bit_17);
4423         kfree(obj->driver_private);
4424 }
4425
4426 /** Unbinds all inactive objects. */
4427 static int
4428 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4429 {
4430         drm_i915_private_t *dev_priv = dev->dev_private;
4431
4432         while (!list_empty(&dev_priv->mm.inactive_list)) {
4433                 struct drm_gem_object *obj;
4434                 int ret;
4435
4436                 obj = list_first_entry(&dev_priv->mm.inactive_list,
4437                                        struct drm_i915_gem_object,
4438                                        list)->obj;
4439
4440                 ret = i915_gem_object_unbind(obj);
4441                 if (ret != 0) {
4442                         DRM_ERROR("Error unbinding object: %d\n", ret);
4443                         return ret;
4444                 }
4445         }
4446
4447         return 0;
4448 }
4449
4450 static int
4451 i915_gpu_idle(struct drm_device *dev)
4452 {
4453         drm_i915_private_t *dev_priv = dev->dev_private;
4454         bool lists_empty;
4455         uint32_t seqno;
4456
4457         spin_lock(&dev_priv->mm.active_list_lock);
4458         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4459                       list_empty(&dev_priv->mm.active_list);
4460         spin_unlock(&dev_priv->mm.active_list_lock);
4461
4462         if (lists_empty)
4463                 return 0;
4464
4465         /* Flush everything onto the inactive list. */
4466         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4467         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4468         if (seqno == 0)
4469                 return -ENOMEM;
4470
4471         return i915_wait_request(dev, seqno);
4472 }
4473
4474 int
4475 i915_gem_idle(struct drm_device *dev)
4476 {
4477         drm_i915_private_t *dev_priv = dev->dev_private;
4478         int ret;
4479
4480         mutex_lock(&dev->struct_mutex);
4481
4482         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4483                 mutex_unlock(&dev->struct_mutex);
4484                 return 0;
4485         }
4486
4487         ret = i915_gpu_idle(dev);
4488         if (ret) {
4489                 mutex_unlock(&dev->struct_mutex);
4490                 return ret;
4491         }
4492
4493         /* Under UMS, be paranoid and evict. */
4494         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4495                 ret = i915_gem_evict_from_inactive_list(dev);
4496                 if (ret) {
4497                         mutex_unlock(&dev->struct_mutex);
4498                         return ret;
4499                 }
4500         }
4501
4502         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4503          * We need to replace this with a semaphore, or something.
4504          * And not confound mm.suspended!
4505          */
4506         dev_priv->mm.suspended = 1;
4507         del_timer(&dev_priv->hangcheck_timer);
4508
4509         i915_kernel_lost_context(dev);
4510         i915_gem_cleanup_ringbuffer(dev);
4511
4512         mutex_unlock(&dev->struct_mutex);
4513
4514         /* Cancel the retire work handler, which should be idle now. */
4515         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4516
4517         return 0;
4518 }
4519
4520 static int
4521 i915_gem_init_hws(struct drm_device *dev)
4522 {
4523         drm_i915_private_t *dev_priv = dev->dev_private;
4524         struct drm_gem_object *obj;
4525         struct drm_i915_gem_object *obj_priv;
4526         int ret;
4527
4528         /* If we need a physical address for the status page, it's already
4529          * initialized at driver load time.
4530          */
4531         if (!I915_NEED_GFX_HWS(dev))
4532                 return 0;
4533
4534         obj = drm_gem_object_alloc(dev, 4096);
4535         if (obj == NULL) {
4536                 DRM_ERROR("Failed to allocate status page\n");
4537                 return -ENOMEM;
4538         }
4539         obj_priv = obj->driver_private;
4540         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4541
4542         ret = i915_gem_object_pin(obj, 4096);
4543         if (ret != 0) {
4544                 drm_gem_object_unreference(obj);
4545                 return ret;
4546         }
4547
4548         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4549
4550         dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4551         if (dev_priv->hw_status_page == NULL) {
4552                 DRM_ERROR("Failed to map status page.\n");
4553                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4554                 i915_gem_object_unpin(obj);
4555                 drm_gem_object_unreference(obj);
4556                 return -EINVAL;
4557         }
4558         dev_priv->hws_obj = obj;
4559         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4560         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4561         I915_READ(HWS_PGA); /* posting read */
4562         DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4563
4564         return 0;
4565 }
4566
4567 static void
4568 i915_gem_cleanup_hws(struct drm_device *dev)
4569 {
4570         drm_i915_private_t *dev_priv = dev->dev_private;
4571         struct drm_gem_object *obj;
4572         struct drm_i915_gem_object *obj_priv;
4573
4574         if (dev_priv->hws_obj == NULL)
4575                 return;
4576
4577         obj = dev_priv->hws_obj;
4578         obj_priv = obj->driver_private;
4579
4580         kunmap(obj_priv->pages[0]);
4581         i915_gem_object_unpin(obj);
4582         drm_gem_object_unreference(obj);
4583         dev_priv->hws_obj = NULL;
4584
4585         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4586         dev_priv->hw_status_page = NULL;
4587
4588         /* Write high address into HWS_PGA when disabling. */
4589         I915_WRITE(HWS_PGA, 0x1ffff000);
4590 }
4591
4592 int
4593 i915_gem_init_ringbuffer(struct drm_device *dev)
4594 {
4595         drm_i915_private_t *dev_priv = dev->dev_private;
4596         struct drm_gem_object *obj;
4597         struct drm_i915_gem_object *obj_priv;
4598         drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4599         int ret;
4600         u32 head;
4601
4602         ret = i915_gem_init_hws(dev);
4603         if (ret != 0)
4604                 return ret;
4605
4606         obj = drm_gem_object_alloc(dev, 128 * 1024);
4607         if (obj == NULL) {
4608                 DRM_ERROR("Failed to allocate ringbuffer\n");
4609                 i915_gem_cleanup_hws(dev);
4610                 return -ENOMEM;
4611         }
4612         obj_priv = obj->driver_private;
4613
4614         ret = i915_gem_object_pin(obj, 4096);
4615         if (ret != 0) {
4616                 drm_gem_object_unreference(obj);
4617                 i915_gem_cleanup_hws(dev);
4618                 return ret;
4619         }
4620
4621         /* Set up the kernel mapping for the ring. */
4622         ring->Size = obj->size;
4623
4624         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4625         ring->map.size = obj->size;
4626         ring->map.type = 0;
4627         ring->map.flags = 0;
4628         ring->map.mtrr = 0;
4629
4630         drm_core_ioremap_wc(&ring->map, dev);
4631         if (ring->map.handle == NULL) {
4632                 DRM_ERROR("Failed to map ringbuffer.\n");
4633                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4634                 i915_gem_object_unpin(obj);
4635                 drm_gem_object_unreference(obj);
4636                 i915_gem_cleanup_hws(dev);
4637                 return -EINVAL;
4638         }
4639         ring->ring_obj = obj;
4640         ring->virtual_start = ring->map.handle;
4641
4642         /* Stop the ring if it's running. */
4643         I915_WRITE(PRB0_CTL, 0);
4644         I915_WRITE(PRB0_TAIL, 0);
4645         I915_WRITE(PRB0_HEAD, 0);
4646
4647         /* Initialize the ring. */
4648         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4649         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4650
4651         /* G45 ring initialization fails to reset head to zero */
4652         if (head != 0) {
4653                 DRM_ERROR("Ring head not reset to zero "
4654                           "ctl %08x head %08x tail %08x start %08x\n",
4655                           I915_READ(PRB0_CTL),
4656                           I915_READ(PRB0_HEAD),
4657                           I915_READ(PRB0_TAIL),
4658                           I915_READ(PRB0_START));
4659                 I915_WRITE(PRB0_HEAD, 0);
4660
4661                 DRM_ERROR("Ring head forced to zero "
4662                           "ctl %08x head %08x tail %08x start %08x\n",
4663                           I915_READ(PRB0_CTL),
4664                           I915_READ(PRB0_HEAD),
4665                           I915_READ(PRB0_TAIL),
4666                           I915_READ(PRB0_START));
4667         }
4668
4669         I915_WRITE(PRB0_CTL,
4670                    ((obj->size - 4096) & RING_NR_PAGES) |
4671                    RING_NO_REPORT |
4672                    RING_VALID);
4673
4674         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4675
4676         /* If the head is still not zero, the ring is dead */
4677         if (head != 0) {
4678                 DRM_ERROR("Ring initialization failed "
4679                           "ctl %08x head %08x tail %08x start %08x\n",
4680                           I915_READ(PRB0_CTL),
4681                           I915_READ(PRB0_HEAD),
4682                           I915_READ(PRB0_TAIL),
4683                           I915_READ(PRB0_START));
4684                 return -EIO;
4685         }
4686
4687         /* Update our cache of the ring state */
4688         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4689                 i915_kernel_lost_context(dev);
4690         else {
4691                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4692                 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4693                 ring->space = ring->head - (ring->tail + 8);
4694                 if (ring->space < 0)
4695                         ring->space += ring->Size;
4696         }
4697
4698         return 0;
4699 }
4700
4701 void
4702 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4703 {
4704         drm_i915_private_t *dev_priv = dev->dev_private;
4705
4706         if (dev_priv->ring.ring_obj == NULL)
4707                 return;
4708
4709         drm_core_ioremapfree(&dev_priv->ring.map, dev);
4710
4711         i915_gem_object_unpin(dev_priv->ring.ring_obj);
4712         drm_gem_object_unreference(dev_priv->ring.ring_obj);
4713         dev_priv->ring.ring_obj = NULL;
4714         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4715
4716         i915_gem_cleanup_hws(dev);
4717 }
4718
4719 int
4720 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4721                        struct drm_file *file_priv)
4722 {
4723         drm_i915_private_t *dev_priv = dev->dev_private;
4724         int ret;
4725
4726         if (drm_core_check_feature(dev, DRIVER_MODESET))
4727                 return 0;
4728
4729         if (atomic_read(&dev_priv->mm.wedged)) {
4730                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4731                 atomic_set(&dev_priv->mm.wedged, 0);
4732         }
4733
4734         mutex_lock(&dev->struct_mutex);
4735         dev_priv->mm.suspended = 0;
4736
4737         ret = i915_gem_init_ringbuffer(dev);
4738         if (ret != 0) {
4739                 mutex_unlock(&dev->struct_mutex);
4740                 return ret;
4741         }
4742
4743         spin_lock(&dev_priv->mm.active_list_lock);
4744         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4745         spin_unlock(&dev_priv->mm.active_list_lock);
4746
4747         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4748         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4749         BUG_ON(!list_empty(&dev_priv->mm.request_list));
4750         mutex_unlock(&dev->struct_mutex);
4751
4752         drm_irq_install(dev);
4753
4754         return 0;
4755 }
4756
4757 int
4758 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4759                        struct drm_file *file_priv)
4760 {
4761         if (drm_core_check_feature(dev, DRIVER_MODESET))
4762                 return 0;
4763
4764         drm_irq_uninstall(dev);
4765         return i915_gem_idle(dev);
4766 }
4767
4768 void
4769 i915_gem_lastclose(struct drm_device *dev)
4770 {
4771         int ret;
4772
4773         if (drm_core_check_feature(dev, DRIVER_MODESET))
4774                 return;
4775
4776         ret = i915_gem_idle(dev);
4777         if (ret)
4778                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4779 }
4780
4781 void
4782 i915_gem_load(struct drm_device *dev)
4783 {
4784         int i;
4785         drm_i915_private_t *dev_priv = dev->dev_private;
4786
4787         spin_lock_init(&dev_priv->mm.active_list_lock);
4788         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4789         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4790         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4791         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4792         INIT_LIST_HEAD(&dev_priv->mm.request_list);
4793         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4794         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4795                           i915_gem_retire_work_handler);
4796         dev_priv->mm.next_gem_seqno = 1;
4797
4798         spin_lock(&shrink_list_lock);
4799         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4800         spin_unlock(&shrink_list_lock);
4801
4802         /* Old X drivers will take 0-2 for front, back, depth buffers */
4803         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4804                 dev_priv->fence_reg_start = 3;
4805
4806         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4807                 dev_priv->num_fence_regs = 16;
4808         else
4809                 dev_priv->num_fence_regs = 8;
4810
4811         /* Initialize fence registers to zero */
4812         if (IS_I965G(dev)) {
4813                 for (i = 0; i < 16; i++)
4814                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4815         } else {
4816                 for (i = 0; i < 8; i++)
4817                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4818                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4819                         for (i = 0; i < 8; i++)
4820                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4821         }
4822         i915_gem_detect_bit_6_swizzle(dev);
4823         init_waitqueue_head(&dev_priv->pending_flip_queue);
4824 }
4825
4826 /*
4827  * Create a physically contiguous memory object for this object
4828  * e.g. for cursor + overlay regs
4829  */
4830 int i915_gem_init_phys_object(struct drm_device *dev,
4831                               int id, int size)
4832 {
4833         drm_i915_private_t *dev_priv = dev->dev_private;
4834         struct drm_i915_gem_phys_object *phys_obj;
4835         int ret;
4836
4837         if (dev_priv->mm.phys_objs[id - 1] || !size)
4838                 return 0;
4839
4840         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4841         if (!phys_obj)
4842                 return -ENOMEM;
4843
4844         phys_obj->id = id;
4845
4846         phys_obj->handle = drm_pci_alloc(dev, size, 0);
4847         if (!phys_obj->handle) {
4848                 ret = -ENOMEM;
4849                 goto kfree_obj;
4850         }
4851 #ifdef CONFIG_X86
4852         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4853 #endif
4854
4855         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4856
4857         return 0;
4858 kfree_obj:
4859         kfree(phys_obj);
4860         return ret;
4861 }
4862
4863 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4864 {
4865         drm_i915_private_t *dev_priv = dev->dev_private;
4866         struct drm_i915_gem_phys_object *phys_obj;
4867
4868         if (!dev_priv->mm.phys_objs[id - 1])
4869                 return;
4870
4871         phys_obj = dev_priv->mm.phys_objs[id - 1];
4872         if (phys_obj->cur_obj) {
4873                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4874         }
4875
4876 #ifdef CONFIG_X86
4877         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4878 #endif
4879         drm_pci_free(dev, phys_obj->handle);
4880         kfree(phys_obj);
4881         dev_priv->mm.phys_objs[id - 1] = NULL;
4882 }
4883
4884 void i915_gem_free_all_phys_object(struct drm_device *dev)
4885 {
4886         int i;
4887
4888         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4889                 i915_gem_free_phys_object(dev, i);
4890 }
4891
4892 void i915_gem_detach_phys_object(struct drm_device *dev,
4893                                  struct drm_gem_object *obj)
4894 {
4895         struct drm_i915_gem_object *obj_priv;
4896         int i;
4897         int ret;
4898         int page_count;
4899
4900         obj_priv = obj->driver_private;
4901         if (!obj_priv->phys_obj)
4902                 return;
4903
4904         ret = i915_gem_object_get_pages(obj, 0);
4905         if (ret)
4906                 goto out;
4907
4908         page_count = obj->size / PAGE_SIZE;
4909
4910         for (i = 0; i < page_count; i++) {
4911                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4912                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4913
4914                 memcpy(dst, src, PAGE_SIZE);
4915                 kunmap_atomic(dst, KM_USER0);
4916         }
4917         drm_clflush_pages(obj_priv->pages, page_count);
4918         drm_agp_chipset_flush(dev);
4919
4920         i915_gem_object_put_pages(obj);
4921 out:
4922         obj_priv->phys_obj->cur_obj = NULL;
4923         obj_priv->phys_obj = NULL;
4924 }
4925
4926 int
4927 i915_gem_attach_phys_object(struct drm_device *dev,
4928                             struct drm_gem_object *obj, int id)
4929 {
4930         drm_i915_private_t *dev_priv = dev->dev_private;
4931         struct drm_i915_gem_object *obj_priv;
4932         int ret = 0;
4933         int page_count;
4934         int i;
4935
4936         if (id > I915_MAX_PHYS_OBJECT)
4937                 return -EINVAL;
4938
4939         obj_priv = obj->driver_private;
4940
4941         if (obj_priv->phys_obj) {
4942                 if (obj_priv->phys_obj->id == id)
4943                         return 0;
4944                 i915_gem_detach_phys_object(dev, obj);
4945         }
4946
4947
4948         /* create a new object */
4949         if (!dev_priv->mm.phys_objs[id - 1]) {
4950                 ret = i915_gem_init_phys_object(dev, id,
4951                                                 obj->size);
4952                 if (ret) {
4953                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4954                         goto out;
4955                 }
4956         }
4957
4958         /* bind to the object */
4959         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4960         obj_priv->phys_obj->cur_obj = obj;
4961
4962         ret = i915_gem_object_get_pages(obj, 0);
4963         if (ret) {
4964                 DRM_ERROR("failed to get page list\n");
4965                 goto out;
4966         }
4967
4968         page_count = obj->size / PAGE_SIZE;
4969
4970         for (i = 0; i < page_count; i++) {
4971                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4972                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4973
4974                 memcpy(dst, src, PAGE_SIZE);
4975                 kunmap_atomic(src, KM_USER0);
4976         }
4977
4978         i915_gem_object_put_pages(obj);
4979
4980         return 0;
4981 out:
4982         return ret;
4983 }
4984
4985 static int
4986 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4987                      struct drm_i915_gem_pwrite *args,
4988                      struct drm_file *file_priv)
4989 {
4990         struct drm_i915_gem_object *obj_priv = obj->driver_private;
4991         void *obj_addr;
4992         int ret;
4993         char __user *user_data;
4994
4995         user_data = (char __user *) (uintptr_t) args->data_ptr;
4996         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4997
4998         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4999         ret = copy_from_user(obj_addr, user_data, args->size);
5000         if (ret)
5001                 return -EFAULT;
5002
5003         drm_agp_chipset_flush(dev);
5004         return 0;
5005 }
5006
5007 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5008 {
5009         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5010
5011         /* Clean up our request list when the client is going away, so that
5012          * later retire_requests won't dereference our soon-to-be-gone
5013          * file_priv.
5014          */
5015         mutex_lock(&dev->struct_mutex);
5016         while (!list_empty(&i915_file_priv->mm.request_list))
5017                 list_del_init(i915_file_priv->mm.request_list.next);
5018         mutex_unlock(&dev->struct_mutex);
5019 }
5020
5021 static int
5022 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5023 {
5024         drm_i915_private_t *dev_priv, *next_dev;
5025         struct drm_i915_gem_object *obj_priv, *next_obj;
5026         int cnt = 0;
5027         int would_deadlock = 1;
5028
5029         /* "fast-path" to count number of available objects */
5030         if (nr_to_scan == 0) {
5031                 spin_lock(&shrink_list_lock);
5032                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5033                         struct drm_device *dev = dev_priv->dev;
5034
5035                         if (mutex_trylock(&dev->struct_mutex)) {
5036                                 list_for_each_entry(obj_priv,
5037                                                     &dev_priv->mm.inactive_list,
5038                                                     list)
5039                                         cnt++;
5040                                 mutex_unlock(&dev->struct_mutex);
5041                         }
5042                 }
5043                 spin_unlock(&shrink_list_lock);
5044
5045                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5046         }
5047
5048         spin_lock(&shrink_list_lock);
5049
5050         /* first scan for clean buffers */
5051         list_for_each_entry_safe(dev_priv, next_dev,
5052                                  &shrink_list, mm.shrink_list) {
5053                 struct drm_device *dev = dev_priv->dev;
5054
5055                 if (! mutex_trylock(&dev->struct_mutex))
5056                         continue;
5057
5058                 spin_unlock(&shrink_list_lock);
5059
5060                 i915_gem_retire_requests(dev);
5061
5062                 list_for_each_entry_safe(obj_priv, next_obj,
5063                                          &dev_priv->mm.inactive_list,
5064                                          list) {
5065                         if (i915_gem_object_is_purgeable(obj_priv)) {
5066                                 i915_gem_object_unbind(obj_priv->obj);
5067                                 if (--nr_to_scan <= 0)
5068                                         break;
5069                         }
5070                 }
5071
5072                 spin_lock(&shrink_list_lock);
5073                 mutex_unlock(&dev->struct_mutex);
5074
5075                 would_deadlock = 0;
5076
5077                 if (nr_to_scan <= 0)
5078                         break;
5079         }
5080
5081         /* second pass, evict/count anything still on the inactive list */
5082         list_for_each_entry_safe(dev_priv, next_dev,
5083                                  &shrink_list, mm.shrink_list) {
5084                 struct drm_device *dev = dev_priv->dev;
5085
5086                 if (! mutex_trylock(&dev->struct_mutex))
5087                         continue;
5088
5089                 spin_unlock(&shrink_list_lock);
5090
5091                 list_for_each_entry_safe(obj_priv, next_obj,
5092                                          &dev_priv->mm.inactive_list,
5093                                          list) {
5094                         if (nr_to_scan > 0) {
5095                                 i915_gem_object_unbind(obj_priv->obj);
5096                                 nr_to_scan--;
5097                         } else
5098                                 cnt++;
5099                 }
5100
5101                 spin_lock(&shrink_list_lock);
5102                 mutex_unlock(&dev->struct_mutex);
5103
5104                 would_deadlock = 0;
5105         }
5106
5107         spin_unlock(&shrink_list_lock);
5108
5109         if (would_deadlock)
5110                 return -1;
5111         else if (cnt > 0)
5112                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5113         else
5114                 return 0;
5115 }
5116
5117 static struct shrinker shrinker = {
5118         .shrink = i915_gem_shrink,
5119         .seeks = DEFAULT_SEEKS,
5120 };
5121
5122 __init void
5123 i915_gem_shrinker_init(void)
5124 {
5125     register_shrinker(&shrinker);
5126 }
5127
5128 __exit void
5129 i915_gem_shrinker_exit(void)
5130 {
5131     unregister_shrinker(&shrinker);
5132 }